lsi64854.c revision 1.32
1 /* $NetBSD: lsi64854.c,v 1.32 2008/04/13 04:55:53 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: lsi64854.c,v 1.32 2008/04/13 04:55:53 tsutsui Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <sys/bus.h> 52 #include <machine/autoconf.h> 53 #include <sys/cpu.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 59 #include <dev/ic/lsi64854reg.h> 60 #include <dev/ic/lsi64854var.h> 61 62 #include <dev/ic/ncr53c9xreg.h> 63 #include <dev/ic/ncr53c9xvar.h> 64 65 void lsi64854_reset(struct lsi64854_softc *); 66 int lsi64854_setup(struct lsi64854_softc *, uint8_t **, size_t *, 67 int, size_t *); 68 int lsi64854_setup_pp(struct lsi64854_softc *, uint8_t **, size_t *, 69 int, size_t *); 70 71 #ifdef DEBUG 72 #define LDB_SCSI 1 73 #define LDB_ENET 2 74 #define LDB_PP 4 75 #define LDB_ANY 0xff 76 int lsi64854debug = 0; 77 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 78 #else 79 #define DPRINTF(a,x) 80 #endif 81 82 #define MAX_DMA_SZ (16 * 1024 * 1024) 83 84 /* 85 * Finish attaching this DMA device. 86 * Front-end must fill in these fields: 87 * sc_bustag 88 * sc_dmatag 89 * sc_regs 90 * sc_burst 91 * sc_channel (one of SCSI, ENET, PP) 92 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 93 */ 94 void 95 lsi64854_attach(struct lsi64854_softc *sc) 96 { 97 uint32_t csr; 98 99 /* Indirect functions */ 100 switch (sc->sc_channel) { 101 case L64854_CHANNEL_SCSI: 102 sc->intr = lsi64854_scsi_intr; 103 sc->setup = lsi64854_setup; 104 break; 105 case L64854_CHANNEL_ENET: 106 sc->intr = lsi64854_enet_intr; 107 break; 108 case L64854_CHANNEL_PP: 109 sc->setup = lsi64854_setup_pp; 110 break; 111 default: 112 aprint_error(": unknown channel"); 113 } 114 sc->reset = lsi64854_reset; 115 116 /* Allocate a dmamap */ 117 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 118 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 119 aprint_error(": DMA map create failed\n"); 120 return; 121 } 122 123 csr = L64854_GCSR(sc); 124 sc->sc_rev = csr & L64854_DEVID; 125 if (sc->sc_rev == DMAREV_HME) { 126 return; 127 } 128 aprint_normal(": DMA rev "); 129 switch (sc->sc_rev) { 130 case DMAREV_0: 131 aprint_normal("0"); 132 break; 133 case DMAREV_ESC: 134 aprint_normal("esc"); 135 break; 136 case DMAREV_1: 137 aprint_normal("1"); 138 break; 139 case DMAREV_PLUS: 140 aprint_normal("1+"); 141 break; 142 case DMAREV_2: 143 aprint_normal("2"); 144 break; 145 default: 146 aprint_normal("unknown (0x%x)", sc->sc_rev); 147 } 148 149 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 150 aprint_normal("\n"); 151 } 152 153 /* 154 * DMAWAIT waits while condition is true 155 */ 156 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 157 int count = 500000; \ 158 while ((COND) && --count > 0) DELAY(1); \ 159 if (count == 0) { \ 160 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 161 (u_long)L64854_GCSR(SC)); \ 162 if (DONTPANIC) \ 163 printf(MSG); \ 164 else \ 165 panic(MSG); \ 166 } \ 167 } while (/* CONSTCOND */ 0) 168 169 #define DMA_DRAIN(sc, dontpanic) do { \ 170 uint32_t _csr; \ 171 /* \ 172 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 173 * and "drain" bits while it is still thinking about a \ 174 * request. \ 175 * other revs: D_ESC_R_PEND bit reads as 0 \ 176 */ \ 177 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 178 if (sc->sc_rev != DMAREV_HME) { \ 179 /* \ 180 * Select drain bit based on revision \ 181 * also clears errors and D_TC flag \ 182 */ \ 183 _csr = L64854_GCSR(sc); \ 184 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 185 _csr |= D_ESC_DRAIN; \ 186 else \ 187 _csr |= L64854_INVALIDATE; \ 188 \ 189 L64854_SCSR(sc,_csr); \ 190 } \ 191 /* \ 192 * Wait for draining to finish \ 193 * rev0 & rev1 call this PACKCNT \ 194 */ \ 195 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 196 } while (/* CONSTCOND */ 0) 197 198 #define DMA_FLUSH(sc, dontpanic) do { \ 199 uint32_t _csr; \ 200 /* \ 201 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 202 * and "drain" bits while it is still thinking about a \ 203 * request. \ 204 * other revs: D_ESC_R_PEND bit reads as 0 \ 205 */ \ 206 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 207 _csr = L64854_GCSR(sc); \ 208 _csr &= ~(L64854_WRITE | L64854_EN_DMA); /* no-ops on ENET */ \ 209 _csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 210 L64854_SCSR(sc,_csr); \ 211 } while (/* CONSTCOND */ 0) 212 213 void 214 lsi64854_reset(struct lsi64854_softc *sc) 215 { 216 uint32_t csr; 217 218 DMA_FLUSH(sc, 1); 219 csr = L64854_GCSR(sc); 220 221 DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr)); 222 223 /* 224 * XXX is sync needed? 225 */ 226 if (sc->sc_dmamap->dm_nsegs > 0) 227 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 228 229 if (sc->sc_rev == DMAREV_HME) 230 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 231 232 233 csr |= L64854_RESET; /* reset DMA */ 234 L64854_SCSR(sc, csr); 235 DELAY(200); /* > 10 Sbus clocks(?) */ 236 237 /*DMAWAIT1(sc); why was this here? */ 238 csr = L64854_GCSR(sc); 239 csr &= ~L64854_RESET; /* de-assert reset line */ 240 L64854_SCSR(sc, csr); 241 DELAY(5); /* allow a few ticks to settle */ 242 243 csr = L64854_GCSR(sc); 244 csr |= L64854_INT_EN; /* enable interrupts */ 245 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 246 if (sc->sc_rev == DMAREV_HME) 247 csr |= D_TWO_CYCLE; 248 else 249 csr |= D_FASTER; 250 } 251 252 /* Set burst */ 253 switch (sc->sc_rev) { 254 case DMAREV_HME: 255 case DMAREV_2: 256 csr &= ~L64854_BURST_SIZE; 257 if (sc->sc_burst == 32) { 258 csr |= L64854_BURST_32; 259 } else if (sc->sc_burst == 16) { 260 csr |= L64854_BURST_16; 261 } else { 262 csr |= L64854_BURST_0; 263 } 264 break; 265 case DMAREV_ESC: 266 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 267 if (sc->sc_burst == 32) { 268 csr &= ~D_ESC_BURST; 269 } else 270 csr |= D_ESC_BURST; 271 break; 272 default: 273 break; 274 } 275 L64854_SCSR(sc, csr); 276 277 if (sc->sc_rev == DMAREV_HME) { 278 bus_space_write_4(sc->sc_bustag, sc->sc_regs, 279 L64854_REG_ADDR, 0); 280 sc->sc_dmactl = csr; 281 } 282 sc->sc_active = 0; 283 284 DPRINTF(LDB_ANY, ("%s: done, csr 0x%x\n", __func__, csr)); 285 } 286 287 288 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 289 /* 290 * setup a DMA transfer 291 */ 292 int 293 lsi64854_setup(struct lsi64854_softc *sc, uint8_t **addr, size_t *len, 294 int datain, size_t *dmasize) 295 { 296 uint32_t csr; 297 298 DMA_FLUSH(sc, 0); 299 300 #if 0 301 DMACSR(sc) &= ~D_INT_EN; 302 #endif 303 sc->sc_dmaaddr = addr; 304 sc->sc_dmalen = len; 305 306 /* 307 * the rules say we cannot transfer more than the limit 308 * of this DMA chip (64k for old and 16Mb for new), 309 * and we cannot cross a 16Mb boundary. 310 */ 311 *dmasize = sc->sc_dmasize = 312 min(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr)); 313 314 DPRINTF(LDB_ANY, ("%s: dmasize = %ld\n", 315 __func__, (long)sc->sc_dmasize)); 316 317 /* 318 * XXX what length? 319 */ 320 if (sc->sc_rev == DMAREV_HME) { 321 322 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 323 L64854_SCSR(sc, sc->sc_dmactl); 324 325 bus_space_write_4(sc->sc_bustag, sc->sc_regs, 326 L64854_REG_CNT, *dmasize); 327 } 328 329 /* Program the DMA address */ 330 if (sc->sc_dmasize) { 331 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 332 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 333 *sc->sc_dmaaddr, sc->sc_dmasize, 334 NULL /* kernel address */, 335 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 336 panic("%s: cannot allocate DVMA address", 337 device_xname(sc->sc_dev)); 338 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 339 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 340 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 341 sc->sc_dmamap->dm_segs[0].ds_addr); 342 } 343 344 if (sc->sc_rev == DMAREV_ESC) { 345 /* DMA ESC chip bug work-around */ 346 long bcnt = sc->sc_dmasize; 347 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 348 349 if ((eaddr & PGOFSET) != 0) 350 bcnt = roundup(bcnt, PAGE_SIZE); 351 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 352 bcnt); 353 } 354 355 /* Setup DMA control register */ 356 csr = L64854_GCSR(sc); 357 358 if (datain) 359 csr |= L64854_WRITE; 360 else 361 csr &= ~L64854_WRITE; 362 csr |= L64854_INT_EN; 363 364 if (sc->sc_rev == DMAREV_HME) { 365 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 366 } 367 368 L64854_SCSR(sc, csr); 369 370 return 0; 371 } 372 373 /* 374 * Pseudo (chained) interrupt from the esp driver to kick the 375 * current running DMA transfer. Called from ncr53c9x_intr() 376 * for now. 377 * 378 * return 1 if it was a DMA continue. 379 */ 380 int 381 lsi64854_scsi_intr(void *arg) 382 { 383 struct lsi64854_softc *sc = arg; 384 struct ncr53c9x_softc *nsc = sc->sc_client; 385 char bits[64]; 386 int trans, resid; 387 uint32_t csr; 388 389 csr = L64854_GCSR(sc); 390 391 DPRINTF(LDB_SCSI, ("%s: %s: addr 0x%x, csr %s\n", 392 device_xname(sc->sc_dev), __func__, 393 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 394 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 395 396 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 397 printf("%s: error: csr=%s\n", device_xname(sc->sc_dev), 398 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 399 csr &= ~D_EN_DMA; /* Stop DMA */ 400 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 401 csr |= D_INVALIDATE|D_SLAVE_ERR; 402 L64854_SCSR(sc, csr); 403 return -1; 404 } 405 406 /* This is an "assertion" :) */ 407 if (sc->sc_active == 0) 408 panic("%s: DMA wasn't active", __func__); 409 410 DMA_DRAIN(sc, 0); 411 412 /* DMA has stopped */ 413 csr &= ~D_EN_DMA; 414 L64854_SCSR(sc, csr); 415 sc->sc_active = 0; 416 417 if (sc->sc_dmasize == 0) { 418 /* A "Transfer Pad" operation completed */ 419 DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", 420 __func__, 421 NCR_READ_REG(nsc, NCR_TCL) | 422 (NCR_READ_REG(nsc, NCR_TCM) << 8), 423 NCR_READ_REG(nsc, NCR_TCL), 424 NCR_READ_REG(nsc, NCR_TCM))); 425 return 0; 426 } 427 428 resid = 0; 429 /* 430 * If a transfer onto the SCSI bus gets interrupted by the device 431 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 432 * as residual since the NCR53C9X counter registers get decremented 433 * as bytes are clocked into the FIFO. 434 */ 435 if (!(csr & D_WRITE) && 436 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 437 DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", 438 __func__, resid)); 439 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 440 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 441 resid <<= 1; 442 } 443 444 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 445 /* 446 * `Terminal count' is off, so read the residue 447 * out of the NCR53C9X counter registers. 448 */ 449 resid += (NCR_READ_REG(nsc, NCR_TCL) | 450 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 451 ((nsc->sc_cfg2 & NCRCFG2_FE) ? 452 (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0)); 453 454 if (resid == 0 && sc->sc_dmasize == 65536 && 455 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 456 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 457 resid = 65536; 458 } 459 460 trans = sc->sc_dmasize - resid; 461 if (trans < 0) { /* transferred < 0 ? */ 462 #if 0 463 /* 464 * This situation can happen in perfectly normal operation 465 * if the ESP is reselected while using DMA to select 466 * another target. As such, don't print the warning. 467 */ 468 printf("%s: xfer (%d) > req (%d)\n", 469 device_xname(&sc->sc_dev), trans, sc->sc_dmasize); 470 #endif 471 trans = sc->sc_dmasize; 472 } 473 474 DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 475 __func__, 476 NCR_READ_REG(nsc, NCR_TCL), 477 NCR_READ_REG(nsc, NCR_TCM), 478 (nsc->sc_cfg2 & NCRCFG2_FE) ? 479 NCR_READ_REG(nsc, NCR_TCH) : 0, 480 trans, resid)); 481 482 if (sc->sc_dmamap->dm_nsegs > 0) { 483 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 484 (csr & D_WRITE) != 0 ? 485 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 486 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 487 } 488 489 *sc->sc_dmalen -= trans; 490 *sc->sc_dmaaddr += trans; 491 492 #if 0 /* this is not normal operation just yet */ 493 if (*sc->sc_dmalen == 0 || 494 nsc->sc_phase != nsc->sc_prevphase) 495 return 0; 496 497 /* and again */ 498 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 499 return 1; 500 #endif 501 return 0; 502 } 503 504 /* 505 * Pseudo (chained) interrupt to le driver to handle DMA errors. 506 */ 507 int 508 lsi64854_enet_intr(void *arg) 509 { 510 struct lsi64854_softc *sc = arg; 511 char bits[64]; 512 uint32_t csr; 513 static int dodrain = 0; 514 int rv; 515 516 csr = L64854_GCSR(sc); 517 518 /* If the DMA logic shows an interrupt, claim it */ 519 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 520 521 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 522 printf("%s: error: csr=%s\n", device_xname(sc->sc_dev), 523 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 524 csr &= ~L64854_EN_DMA; /* Stop DMA */ 525 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 526 csr |= E_INVALIDATE|E_SLAVE_ERR; 527 L64854_SCSR(sc, csr); 528 DMA_RESET(sc); 529 dodrain = 1; 530 return 1; 531 } 532 533 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 534 int i = 10; 535 csr |= E_DRAIN; 536 L64854_SCSR(sc, csr); 537 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 538 delay(1); 539 } 540 541 return rv | (*sc->sc_intrchain)(sc->sc_intrchainarg); 542 } 543 544 /* 545 * setup a DMA transfer 546 */ 547 int 548 lsi64854_setup_pp(struct lsi64854_softc *sc, uint8_t **addr, size_t *len, 549 int datain, size_t *dmasize) 550 { 551 uint32_t csr; 552 553 DMA_FLUSH(sc, 0); 554 555 sc->sc_dmaaddr = addr; 556 sc->sc_dmalen = len; 557 558 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", device_xname(sc->sc_dev), 559 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 560 561 /* 562 * the rules say we cannot transfer more than the limit 563 * of this DMA chip (64k for old and 16Mb for new), 564 * and we cannot cross a 16Mb boundary. 565 */ 566 *dmasize = sc->sc_dmasize = 567 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 568 569 DPRINTF(LDB_PP, ("%s: dmasize = %ld\n", 570 __func__, (long)sc->sc_dmasize)); 571 572 /* Program the DMA address */ 573 if (sc->sc_dmasize) { 574 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 575 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 576 *sc->sc_dmaaddr, sc->sc_dmasize, 577 NULL /* kernel address */, 578 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 579 panic("%s: pp cannot allocate DVMA address", 580 device_xname(sc->sc_dev)); 581 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 582 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 583 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 584 sc->sc_dmamap->dm_segs[0].ds_addr); 585 586 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 587 sc->sc_dmasize); 588 } 589 590 /* Setup DMA control register */ 591 csr = L64854_GCSR(sc); 592 csr &= ~L64854_BURST_SIZE; 593 if (sc->sc_burst == 32) { 594 csr |= L64854_BURST_32; 595 } else if (sc->sc_burst == 16) { 596 csr |= L64854_BURST_16; 597 } else { 598 csr |= L64854_BURST_0; 599 } 600 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 601 #if 0 602 /* This bit is read-only in PP csr register */ 603 if (datain) 604 csr |= P_WRITE; 605 else 606 csr &= ~P_WRITE; 607 #endif 608 L64854_SCSR(sc, csr); 609 610 return 0; 611 } 612 /* 613 * Parallel port DMA interrupt. 614 */ 615 int 616 lsi64854_pp_intr(void *arg) 617 { 618 struct lsi64854_softc *sc = arg; 619 char bits[64]; 620 int ret, trans, resid = 0; 621 uint32_t csr; 622 623 csr = L64854_GCSR(sc); 624 625 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", 626 device_xname(sc->sc_dev), 627 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 628 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 629 630 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 631 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 632 L64854_REG_CNT); 633 printf("%s: pp error: resid %d csr=%s\n", 634 device_xname(sc->sc_dev), resid, 635 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 636 csr &= ~P_EN_DMA; /* Stop DMA */ 637 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 638 csr |= P_INVALIDATE|P_SLAVE_ERR; 639 L64854_SCSR(sc, csr); 640 return 1; 641 } 642 643 ret = (csr & P_INT_PEND) != 0; 644 645 if (sc->sc_active != 0) { 646 DMA_DRAIN(sc, 0); 647 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 648 L64854_REG_CNT); 649 } 650 651 /* DMA has stopped */ 652 csr &= ~D_EN_DMA; 653 L64854_SCSR(sc, csr); 654 sc->sc_active = 0; 655 656 trans = sc->sc_dmasize - resid; 657 if (trans < 0) { /* transferred < 0 ? */ 658 trans = sc->sc_dmasize; 659 } 660 *sc->sc_dmalen -= trans; 661 *sc->sc_dmaaddr += trans; 662 663 if (sc->sc_dmamap->dm_nsegs > 0) { 664 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 665 (csr & D_WRITE) != 0 ? 666 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 667 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 668 } 669 670 return ret != 0; 671 } 672
Indexes created Thu Sep 25 02:09:54 GMT 2025