lsi64854.c revision 1.4 1 /* $NetBSD: lsi64854.c,v 1.4 1998/09/21 21:26:51 pk Exp $ */
2
3 /*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Kranenburg.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <sys/types.h>
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/errno.h>
44 #include <sys/device.h>
45 #include <sys/malloc.h>
46
47 #include <machine/bus.h>
48 #include <machine/autoconf.h>
49 #include <machine/cpu.h>
50
51 #include <dev/scsipi/scsi_all.h>
52 #include <dev/scsipi/scsipi_all.h>
53 #include <dev/scsipi/scsiconf.h>
54
55 #include <dev/ic/lsi64854reg.h>
56 #include <dev/ic/lsi64854var.h>
57
58 #include <dev/ic/ncr53c9xreg.h>
59 #include <dev/ic/ncr53c9xvar.h>
60
61 void lsi64854_reset __P((struct lsi64854_softc *));
62 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *,
63 int, size_t *));
64 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *,
65 int, size_t *));
66
67 #ifdef DEBUG
68 int lsi64854debug = 0;
69 #define DPRINTF(x) do { if (lsi64854debug != 0) printf x ; } while (0)
70 #else
71 #define DPRINTF(x)
72 #endif
73
74 #define MAX_DMA_SZ (16*1024*1024)
75
76 /*
77 * Finish attaching this DMA device.
78 * Front-end must fill in these fields:
79 * sc_bustag
80 * sc_dmatag
81 * sc_regs
82 * sc_burst
83 * sc_channel (one of SCSI, ENET, PP)
84 * sc_client (one of SCSI, ENET, PP `soft_c' pointers)
85 */
86 void
87 lsi64854_attach(sc)
88 struct lsi64854_softc *sc;
89 {
90
91 /* Indirect functions */
92 switch (sc->sc_channel) {
93 case L64854_CHANNEL_SCSI:
94 sc->intr = lsi64854_scsi_intr;
95 sc->setup = lsi64854_setup;
96 break;
97 case L64854_CHANNEL_ENET:
98 sc->intr = lsi64854_enet_intr;
99 break;
100 case L64854_CHANNEL_PP:
101 sc->setup = lsi64854_setup_pp;
102 break;
103 default:
104 printf("%s: unknown channel\n", sc->sc_dev.dv_xname);
105 }
106 sc->reset = lsi64854_reset;
107
108 /* Allocate a dmamap */
109 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ,
110 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) {
111 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname);
112 return;
113 }
114
115 printf(": rev ");
116 sc->sc_rev = L64854_GCSR(sc) & L64854_DEVID;
117 switch (sc->sc_rev) {
118 case DMAREV_0:
119 printf("0");
120 break;
121 case DMAREV_ESC:
122 printf("esc");
123 break;
124 case DMAREV_1:
125 printf("1");
126 break;
127 case DMAREV_PLUS:
128 printf("1+");
129 break;
130 case DMAREV_2:
131 printf("2");
132 break;
133 default:
134 printf("unknown (0x%x)", sc->sc_rev);
135 }
136 printf("\n");
137
138 }
139
140 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
141 int count = 500000; \
142 while ((COND) && --count > 0) DELAY(1); \
143 if (count == 0) { \
144 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
145 (u_long)L64854_GCSR(SC)); \
146 if (DONTPANIC) \
147 printf(MSG); \
148 else \
149 panic(MSG); \
150 } \
151 } while (0)
152
153 #define DMA_DRAIN(sc, dontpanic) do { \
154 u_int32_t csr; \
155 /* \
156 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
157 * and "drain" bits while it is still thinking about a \
158 * request. \
159 * other revs: D_ESC_R_PEND bit reads as 0 \
160 */ \
161 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
162 /* \
163 * Select drain bit based on revision \
164 * also clears errors and D_TC flag \
165 */ \
166 csr = L64854_GCSR(sc); \
167 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
168 csr |= D_ESC_DRAIN; \
169 else \
170 csr |= L64854_INVALIDATE; \
171 \
172 L64854_SCSR(sc,csr); \
173 /* \
174 * Wait for draining to finish \
175 * rev0 & rev1 call this PACKCNT \
176 */ \
177 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
178 } while(0)
179
180 #define DMA_FLUSH(sc, dontpanic) do { \
181 u_int32_t csr; \
182 /* \
183 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
184 * and "drain" bits while it is still thinking about a \
185 * request. \
186 * other revs: D_ESC_R_PEND bit reads as 0 \
187 */ \
188 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
189 csr = L64854_GCSR(sc); \
190 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
191 csr |= L64854_INVALIDATE; \
192 L64854_SCSR(sc,csr); \
193 } while(0)
194
195 void
196 lsi64854_reset(sc)
197 struct lsi64854_softc *sc;
198 {
199 u_int32_t csr;
200
201 DMA_FLUSH(sc, 1);
202 csr = L64854_GCSR(sc);
203 csr |= L64854_RESET; /* reset DMA */
204 L64854_SCSR(sc, csr);
205 DELAY(200); /* > 10 Sbus clocks(?) */
206
207 /*DMAWAIT1(sc); why was this here? */
208 csr = L64854_GCSR(sc);
209 csr &= ~L64854_RESET; /* de-assert reset line */
210 L64854_SCSR(sc, csr);
211 DELAY(5); /* allow a few ticks to settle */
212
213 csr = L64854_GCSR(sc);
214 csr |= L64854_INT_EN; /* enable interrupts */
215 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI)
216 csr |= D_FASTER;
217
218 /* Set burst */
219 switch (sc->sc_rev) {
220 case DMAREV_2:
221 csr &= ~L64854_BURST_SIZE;
222 if (sc->sc_burst == 32) {
223 csr |= L64854_BURST_32;
224 } else if (sc->sc_burst == 16) {
225 csr |= L64854_BURST_16;
226 } else {
227 csr |= L64854_BURST_0;
228 }
229 break;
230 case DMAREV_ESC:
231 csr |= D_ESC_AUTODRAIN; /* Auto-drain */
232 if (sc->sc_burst == 32) {
233 csr &= ~D_ESC_BURST;
234 } else
235 csr |= D_ESC_BURST;
236 break;
237 default:
238 }
239 L64854_SCSR(sc, csr);
240
241 sc->sc_active = 0;
242 }
243
244
245 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
246 /*
247 * setup a dma transfer
248 */
249 int
250 lsi64854_setup(sc, addr, len, datain, dmasize)
251 struct lsi64854_softc *sc;
252 caddr_t *addr;
253 size_t *len;
254 int datain;
255 size_t *dmasize; /* IN-OUT */
256 {
257 u_int32_t csr;
258
259 DMA_FLUSH(sc, 0);
260
261 #if 0
262 DMACSR(sc) &= ~D_INT_EN;
263 #endif
264 sc->sc_dmaaddr = addr;
265 sc->sc_dmalen = len;
266
267 DPRINTF(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
268 *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
269
270 /*
271 * the rules say we cannot transfer more than the limit
272 * of this DMA chip (64k for old and 16Mb for new),
273 * and we cannot cross a 16Mb boundary.
274 */
275 *dmasize = sc->sc_dmasize =
276 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
277
278 DPRINTF(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
279
280 /* Program the DMA address */
281 if (sc->sc_dmasize) {
282 sc->sc_dvmaaddr = *sc->sc_dmaaddr;
283 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
284 *sc->sc_dmaaddr, sc->sc_dmasize,
285 NULL /* kernel address */,
286 BUS_DMA_NOWAIT))
287 panic("%s: cannot allocate DVMA address",
288 sc->sc_dev.dv_xname);
289 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
290 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
291 datain
292 ? BUS_DMASYNC_PREREAD
293 : BUS_DMASYNC_PREWRITE);
294 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
295 sc->sc_dmamap->dm_segs[0].ds_addr);
296 }
297
298 if (sc->sc_rev == DMAREV_ESC) {
299 /* DMA ESC chip bug work-around */
300 long bcnt = sc->sc_dmasize;
301 long eaddr = bcnt + (long)*sc->sc_dmaaddr;
302 if ((eaddr & PGOFSET) != 0)
303 bcnt = roundup(bcnt, NBPG);
304 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
305 bcnt);
306 }
307 /* Setup DMA control register */
308 csr = L64854_GCSR(sc);
309 if (datain)
310 csr |= L64854_WRITE;
311 else
312 csr &= ~L64854_WRITE;
313 csr |= L64854_INT_EN;
314 L64854_SCSR(sc, csr);
315
316 return (0);
317 }
318
319 /*
320 * Pseudo (chained) interrupt from the esp driver to kick the
321 * current running DMA transfer. Called from ncr53c9x_intr()
322 * for now.
323 *
324 * return 1 if it was a DMA continue.
325 */
326 int
327 lsi64854_scsi_intr(arg)
328 void *arg;
329 {
330 struct lsi64854_softc *sc = arg;
331 struct ncr53c9x_softc *nsc = sc->sc_client;
332 char bits[64];
333 int trans, resid;
334 u_int32_t csr;
335
336 csr = L64854_GCSR(sc);
337
338 DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname,
339 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
340 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits))));
341
342 if (csr & D_ERR_PEND) {
343 csr &= ~D_EN_DMA; /* Stop DMA */
344 csr |= D_INVALIDATE;
345 L64854_SCSR(sc, csr);
346 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
347 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits)));
348 return (-1);
349 }
350
351 /* This is an "assertion" :) */
352 if (sc->sc_active == 0)
353 panic("dmaintr: DMA wasn't active");
354
355 DMA_DRAIN(sc, 0);
356
357 /* DMA has stopped */
358 csr &= ~D_EN_DMA;
359 L64854_SCSR(sc, csr);
360 sc->sc_active = 0;
361
362 if (sc->sc_dmasize == 0) {
363 /* A "Transfer Pad" operation completed */
364 DPRINTF(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
365 NCR_READ_REG(nsc, NCR_TCL) |
366 (NCR_READ_REG(nsc, NCR_TCM) << 8),
367 NCR_READ_REG(nsc, NCR_TCL),
368 NCR_READ_REG(nsc, NCR_TCM)));
369 return 0;
370 }
371
372 resid = 0;
373 /*
374 * If a transfer onto the SCSI bus gets interrupted by the device
375 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts
376 * as residual since the NCR53C9X counter registers get decremented
377 * as bytes are clocked into the FIFO.
378 */
379 if (!(csr & D_WRITE) &&
380 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
381 DPRINTF(("dmaintr: empty esp FIFO of %d ", resid));
382 }
383
384 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
385 /*
386 * `Terminal count' is off, so read the residue
387 * out of the NCR53C9X counter registers.
388 */
389 resid += (NCR_READ_REG(nsc, NCR_TCL) |
390 (NCR_READ_REG(nsc, NCR_TCM) << 8) |
391 ((nsc->sc_cfg2 & NCRCFG2_FE)
392 ? (NCR_READ_REG(nsc, NCR_TCH) << 16)
393 : 0));
394
395 if (resid == 0 && sc->sc_dmasize == 65536 &&
396 (nsc->sc_cfg2 & NCRCFG2_FE) == 0)
397 /* A transfer of 64K is encoded as `TCL=TCM=0' */
398 resid = 65536;
399 }
400
401 trans = sc->sc_dmasize - resid;
402 if (trans < 0) { /* transferred < 0 ? */
403 #if 0
404 /*
405 * This situation can happen in perfectly normal operation
406 * if the ESP is reselected while using DMA to select
407 * another target. As such, don't print the warning.
408 */
409 printf("%s: xfer (%d) > req (%d)\n",
410 sc->sc_dev.dv_xname, trans, sc->sc_dmasize);
411 #endif
412 trans = sc->sc_dmasize;
413 }
414
415 DPRINTF(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
416 NCR_READ_REG(nsc, NCR_TCL),
417 NCR_READ_REG(nsc, NCR_TCM),
418 (nsc->sc_cfg2 & NCRCFG2_FE)
419 ? NCR_READ_REG(nsc, NCR_TCH) : 0,
420 trans, resid));
421
422 if (sc->sc_dmamap->dm_nsegs > 0) {
423 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
424 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
425 (csr & D_WRITE) != 0
426 ? BUS_DMASYNC_POSTREAD
427 : BUS_DMASYNC_POSTWRITE);
428 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
429 }
430
431 *sc->sc_dmalen -= trans;
432 *sc->sc_dmaaddr += trans;
433
434 #if 0 /* this is not normal operation just yet */
435 if (*sc->sc_dmalen == 0 ||
436 nsc->sc_phase != nsc->sc_prevphase)
437 return 0;
438
439 /* and again */
440 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
441 return 1;
442 #endif
443 return 0;
444 }
445
446 /*
447 * Pseudo (chained) interrupt to le driver to handle DMA errors.
448 */
449 int
450 lsi64854_enet_intr(arg)
451 void *arg;
452 {
453 struct lsi64854_softc *sc = arg;
454 char bits[64];
455 u_int32_t csr;
456 static int dodrain=0;
457
458 csr = L64854_GCSR(sc);
459
460 if (csr & E_ERR_PEND) {
461 csr &= ~L64854_EN_DMA; /* Stop DMA */
462 csr |= E_INVALIDATE;
463 L64854_SCSR(sc, csr);
464 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
465 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits)));
466 DMA_RESET(sc);
467 dodrain = 1;
468 }
469
470 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
471 int i = 10;
472 csr |= E_DRAIN;
473 L64854_SCSR(sc, csr);
474 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
475 delay(1);
476 }
477
478 return (*sc->sc_intrchain)(sc->sc_intrchainarg);
479 }
480
481 /*
482 * setup a dma transfer
483 */
484 int
485 lsi64854_setup_pp(sc, addr, len, datain, dmasize)
486 struct lsi64854_softc *sc;
487 caddr_t *addr;
488 size_t *len;
489 int datain;
490 size_t *dmasize; /* IN-OUT */
491 {
492 u_int32_t csr;
493
494 DMA_FLUSH(sc, 0);
495
496 sc->sc_dmaaddr = addr;
497 sc->sc_dmalen = len;
498
499 DPRINTF(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
500 *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
501
502 /*
503 * the rules say we cannot transfer more than the limit
504 * of this DMA chip (64k for old and 16Mb for new),
505 * and we cannot cross a 16Mb boundary.
506 */
507 *dmasize = sc->sc_dmasize =
508 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
509
510 DPRINTF(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
511
512 /* Program the DMA address */
513 if (sc->sc_dmasize) {
514 sc->sc_dvmaaddr = *sc->sc_dmaaddr;
515 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
516 *sc->sc_dmaaddr, sc->sc_dmasize,
517 NULL /* kernel address */,
518 BUS_DMA_NOWAIT))
519 panic("%s: cannot allocate DVMA address",
520 sc->sc_dev.dv_xname);
521 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
522 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
523 datain
524 ? BUS_DMASYNC_PREREAD
525 : BUS_DMASYNC_PREWRITE);
526 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
527 sc->sc_dmamap->dm_segs[0].ds_addr);
528
529 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
530 sc->sc_dmasize);
531 }
532
533 /* Setup DMA control register */
534 csr = L64854_GCSR(sc);
535 #if 0
536 /* This bit is read-only in PP csr register */
537 if (datain)
538 csr |= L64854_WRITE;
539 else
540 csr &= ~L64854_WRITE;
541 #endif
542 csr |= L64854_INT_EN;
543 L64854_SCSR(sc, csr);
544
545 return (0);
546 }
547 /*
548 * Parallel port DMA interrupt.
549 */
550 int
551 lsi64854_pp_intr(arg)
552 void *arg;
553 {
554 struct lsi64854_softc *sc = arg;
555 char bits[64];
556 int ret, trans, resid = 0;
557 u_int32_t csr;
558
559 csr = L64854_GCSR(sc);
560
561 DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname,
562 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
563 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits))));
564
565 if (csr & P_ERR_PEND) {
566 csr &= ~P_EN_DMA; /* Stop DMA */
567 csr |= P_INVALIDATE;
568 L64854_SCSR(sc, csr);
569 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
570 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits)));
571 }
572
573 ret = (csr & P_INT_PEND) != 0;
574
575 if (sc->sc_active != 0) {
576 DMA_DRAIN(sc, 0);
577 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs,
578 L64854_REG_CNT);
579 }
580
581 /* DMA has stopped */
582 csr &= ~D_EN_DMA;
583 L64854_SCSR(sc, csr);
584 sc->sc_active = 0;
585
586 trans = sc->sc_dmasize - resid;
587 if (trans < 0) { /* transferred < 0 ? */
588 trans = sc->sc_dmasize;
589 }
590 *sc->sc_dmalen -= trans;
591 *sc->sc_dmaaddr += trans;
592
593 if (sc->sc_dmamap->dm_nsegs > 0) {
594 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
595 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
596 (csr & D_WRITE) != 0
597 ? BUS_DMASYNC_POSTREAD
598 : BUS_DMASYNC_POSTWRITE);
599 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
600 }
601
602 ret |= (*sc->sc_intrchain)(sc->sc_intrchainarg);
603 return (ret != 0);
604 }
605