lsi64854.c revision 1.6
1 /* $NetBSD: lsi64854.c,v 1.6 1999/04/16 13:35:41 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 #include <machine/cpu.h> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsipi_all.h> 53 #include <dev/scsipi/scsiconf.h> 54 55 #include <dev/ic/lsi64854reg.h> 56 #include <dev/ic/lsi64854var.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 void lsi64854_reset __P((struct lsi64854_softc *)); 62 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 63 int, size_t *)); 64 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 65 int, size_t *)); 66 67 #ifdef DEBUG 68 int lsi64854debug = 0; 69 #define DPRINTF(x) do { if (lsi64854debug != 0) printf x ; } while (0) 70 #else 71 #define DPRINTF(x) 72 #endif 73 74 #define MAX_DMA_SZ (16*1024*1024) 75 76 /* 77 * Finish attaching this DMA device. 78 * Front-end must fill in these fields: 79 * sc_bustag 80 * sc_dmatag 81 * sc_regs 82 * sc_burst 83 * sc_channel (one of SCSI, ENET, PP) 84 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 85 */ 86 void 87 lsi64854_attach(sc) 88 struct lsi64854_softc *sc; 89 { 90 91 /* Indirect functions */ 92 switch (sc->sc_channel) { 93 case L64854_CHANNEL_SCSI: 94 sc->intr = lsi64854_scsi_intr; 95 sc->setup = lsi64854_setup; 96 break; 97 case L64854_CHANNEL_ENET: 98 sc->intr = lsi64854_enet_intr; 99 break; 100 case L64854_CHANNEL_PP: 101 sc->setup = lsi64854_setup_pp; 102 break; 103 default: 104 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 105 } 106 sc->reset = lsi64854_reset; 107 108 /* Allocate a dmamap */ 109 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 110 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 111 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 112 return; 113 } 114 115 printf(": rev "); 116 sc->sc_rev = L64854_GCSR(sc) & L64854_DEVID; 117 switch (sc->sc_rev) { 118 case DMAREV_0: 119 printf("0"); 120 break; 121 case DMAREV_ESC: 122 printf("esc"); 123 break; 124 case DMAREV_1: 125 printf("1"); 126 break; 127 case DMAREV_PLUS: 128 printf("1+"); 129 break; 130 case DMAREV_2: 131 printf("2"); 132 break; 133 default: 134 printf("unknown (0x%x)", sc->sc_rev); 135 } 136 printf("\n"); 137 138 } 139 140 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 141 int count = 500000; \ 142 while ((COND) && --count > 0) DELAY(1); \ 143 if (count == 0) { \ 144 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 145 (u_long)L64854_GCSR(SC)); \ 146 if (DONTPANIC) \ 147 printf(MSG); \ 148 else \ 149 panic(MSG); \ 150 } \ 151 } while (0) 152 153 #define DMA_DRAIN(sc, dontpanic) do { \ 154 u_int32_t csr; \ 155 /* \ 156 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 157 * and "drain" bits while it is still thinking about a \ 158 * request. \ 159 * other revs: D_ESC_R_PEND bit reads as 0 \ 160 */ \ 161 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 162 /* \ 163 * Select drain bit based on revision \ 164 * also clears errors and D_TC flag \ 165 */ \ 166 csr = L64854_GCSR(sc); \ 167 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 168 csr |= D_ESC_DRAIN; \ 169 else \ 170 csr |= L64854_INVALIDATE; \ 171 \ 172 L64854_SCSR(sc,csr); \ 173 /* \ 174 * Wait for draining to finish \ 175 * rev0 & rev1 call this PACKCNT \ 176 */ \ 177 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 178 } while(0) 179 180 #define DMA_FLUSH(sc, dontpanic) do { \ 181 u_int32_t csr; \ 182 /* \ 183 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 184 * and "drain" bits while it is still thinking about a \ 185 * request. \ 186 * other revs: D_ESC_R_PEND bit reads as 0 \ 187 */ \ 188 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 189 csr = L64854_GCSR(sc); \ 190 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 191 csr |= L64854_INVALIDATE; \ 192 L64854_SCSR(sc,csr); \ 193 } while(0) 194 195 void 196 lsi64854_reset(sc) 197 struct lsi64854_softc *sc; 198 { 199 u_int32_t csr; 200 201 DMA_FLUSH(sc, 1); 202 csr = L64854_GCSR(sc); 203 csr |= L64854_RESET; /* reset DMA */ 204 L64854_SCSR(sc, csr); 205 DELAY(200); /* > 10 Sbus clocks(?) */ 206 207 /*DMAWAIT1(sc); why was this here? */ 208 csr = L64854_GCSR(sc); 209 csr &= ~L64854_RESET; /* de-assert reset line */ 210 L64854_SCSR(sc, csr); 211 DELAY(5); /* allow a few ticks to settle */ 212 213 csr = L64854_GCSR(sc); 214 csr |= L64854_INT_EN; /* enable interrupts */ 215 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) 216 csr |= D_FASTER; 217 218 /* Set burst */ 219 switch (sc->sc_rev) { 220 case DMAREV_2: 221 csr &= ~L64854_BURST_SIZE; 222 if (sc->sc_burst == 32) { 223 csr |= L64854_BURST_32; 224 } else if (sc->sc_burst == 16) { 225 csr |= L64854_BURST_16; 226 } else { 227 csr |= L64854_BURST_0; 228 } 229 break; 230 case DMAREV_ESC: 231 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 232 if (sc->sc_burst == 32) { 233 csr &= ~D_ESC_BURST; 234 } else 235 csr |= D_ESC_BURST; 236 break; 237 default: 238 } 239 L64854_SCSR(sc, csr); 240 241 sc->sc_active = 0; 242 } 243 244 245 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 246 /* 247 * setup a dma transfer 248 */ 249 int 250 lsi64854_setup(sc, addr, len, datain, dmasize) 251 struct lsi64854_softc *sc; 252 caddr_t *addr; 253 size_t *len; 254 int datain; 255 size_t *dmasize; /* IN-OUT */ 256 { 257 u_int32_t csr; 258 259 DMA_FLUSH(sc, 0); 260 261 #if 0 262 DMACSR(sc) &= ~D_INT_EN; 263 #endif 264 sc->sc_dmaaddr = addr; 265 sc->sc_dmalen = len; 266 267 DPRINTF(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 268 *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 269 270 /* 271 * the rules say we cannot transfer more than the limit 272 * of this DMA chip (64k for old and 16Mb for new), 273 * and we cannot cross a 16Mb boundary. 274 */ 275 *dmasize = sc->sc_dmasize = 276 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 277 278 DPRINTF(("dma_setup: dmasize = %d\n", sc->sc_dmasize)); 279 280 /* Program the DMA address */ 281 if (sc->sc_dmasize) { 282 int s = splbio(); 283 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 284 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 285 *sc->sc_dmaaddr, sc->sc_dmasize, 286 NULL /* kernel address */, 287 BUS_DMA_NOWAIT)) 288 panic("%s: cannot allocate DVMA address", 289 sc->sc_dev.dv_xname); 290 splx(s); 291 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 292 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize, 293 datain 294 ? BUS_DMASYNC_PREREAD 295 : BUS_DMASYNC_PREWRITE); 296 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 297 sc->sc_dmamap->dm_segs[0].ds_addr); 298 } 299 300 if (sc->sc_rev == DMAREV_ESC) { 301 /* DMA ESC chip bug work-around */ 302 long bcnt = sc->sc_dmasize; 303 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 304 if ((eaddr & PGOFSET) != 0) 305 bcnt = roundup(bcnt, NBPG); 306 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 307 bcnt); 308 } 309 /* Setup DMA control register */ 310 csr = L64854_GCSR(sc); 311 if (datain) 312 csr |= L64854_WRITE; 313 else 314 csr &= ~L64854_WRITE; 315 csr |= L64854_INT_EN; 316 L64854_SCSR(sc, csr); 317 318 return (0); 319 } 320 321 /* 322 * Pseudo (chained) interrupt from the esp driver to kick the 323 * current running DMA transfer. Called from ncr53c9x_intr() 324 * for now. 325 * 326 * return 1 if it was a DMA continue. 327 */ 328 int 329 lsi64854_scsi_intr(arg) 330 void *arg; 331 { 332 struct lsi64854_softc *sc = arg; 333 struct ncr53c9x_softc *nsc = sc->sc_client; 334 char bits[64]; 335 int trans, resid; 336 u_int32_t csr; 337 338 csr = L64854_GCSR(sc); 339 340 DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 341 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 342 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 343 344 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 345 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 346 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 347 csr &= ~D_EN_DMA; /* Stop DMA */ 348 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 349 csr |= D_INVALIDATE|D_SLAVE_ERR; 350 L64854_SCSR(sc, csr); 351 return (-1); 352 } 353 354 /* This is an "assertion" :) */ 355 if (sc->sc_active == 0) 356 panic("dmaintr: DMA wasn't active"); 357 358 DMA_DRAIN(sc, 0); 359 360 /* DMA has stopped */ 361 csr &= ~D_EN_DMA; 362 L64854_SCSR(sc, csr); 363 sc->sc_active = 0; 364 365 if (sc->sc_dmasize == 0) { 366 /* A "Transfer Pad" operation completed */ 367 DPRINTF(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 368 NCR_READ_REG(nsc, NCR_TCL) | 369 (NCR_READ_REG(nsc, NCR_TCM) << 8), 370 NCR_READ_REG(nsc, NCR_TCL), 371 NCR_READ_REG(nsc, NCR_TCM))); 372 return 0; 373 } 374 375 resid = 0; 376 /* 377 * If a transfer onto the SCSI bus gets interrupted by the device 378 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 379 * as residual since the NCR53C9X counter registers get decremented 380 * as bytes are clocked into the FIFO. 381 */ 382 if (!(csr & D_WRITE) && 383 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 384 DPRINTF(("dmaintr: empty esp FIFO of %d ", resid)); 385 } 386 387 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 388 /* 389 * `Terminal count' is off, so read the residue 390 * out of the NCR53C9X counter registers. 391 */ 392 resid += (NCR_READ_REG(nsc, NCR_TCL) | 393 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 394 ((nsc->sc_cfg2 & NCRCFG2_FE) 395 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 396 : 0)); 397 398 if (resid == 0 && sc->sc_dmasize == 65536 && 399 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 400 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 401 resid = 65536; 402 } 403 404 trans = sc->sc_dmasize - resid; 405 if (trans < 0) { /* transferred < 0 ? */ 406 #if 0 407 /* 408 * This situation can happen in perfectly normal operation 409 * if the ESP is reselected while using DMA to select 410 * another target. As such, don't print the warning. 411 */ 412 printf("%s: xfer (%d) > req (%d)\n", 413 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 414 #endif 415 trans = sc->sc_dmasize; 416 } 417 418 DPRINTF(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 419 NCR_READ_REG(nsc, NCR_TCL), 420 NCR_READ_REG(nsc, NCR_TCM), 421 (nsc->sc_cfg2 & NCRCFG2_FE) 422 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 423 trans, resid)); 424 425 if (sc->sc_dmamap->dm_nsegs > 0) { 426 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 427 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize, 428 (csr & D_WRITE) != 0 429 ? BUS_DMASYNC_POSTREAD 430 : BUS_DMASYNC_POSTWRITE); 431 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 432 } 433 434 *sc->sc_dmalen -= trans; 435 *sc->sc_dmaaddr += trans; 436 437 #if 0 /* this is not normal operation just yet */ 438 if (*sc->sc_dmalen == 0 || 439 nsc->sc_phase != nsc->sc_prevphase) 440 return 0; 441 442 /* and again */ 443 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 444 return 1; 445 #endif 446 return 0; 447 } 448 449 /* 450 * Pseudo (chained) interrupt to le driver to handle DMA errors. 451 */ 452 int 453 lsi64854_enet_intr(arg) 454 void *arg; 455 { 456 struct lsi64854_softc *sc = arg; 457 char bits[64]; 458 u_int32_t csr; 459 static int dodrain=0; 460 461 csr = L64854_GCSR(sc); 462 463 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 464 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 465 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 466 csr &= ~L64854_EN_DMA; /* Stop DMA */ 467 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 468 csr |= E_INVALIDATE|E_SLAVE_ERR; 469 L64854_SCSR(sc, csr); 470 DMA_RESET(sc); 471 dodrain = 1; 472 return (1); 473 } 474 475 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 476 int i = 10; 477 csr |= E_DRAIN; 478 L64854_SCSR(sc, csr); 479 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 480 delay(1); 481 } 482 483 return (*sc->sc_intrchain)(sc->sc_intrchainarg); 484 } 485 486 /* 487 * setup a dma transfer 488 */ 489 int 490 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 491 struct lsi64854_softc *sc; 492 caddr_t *addr; 493 size_t *len; 494 int datain; 495 size_t *dmasize; /* IN-OUT */ 496 { 497 u_int32_t csr; 498 499 DMA_FLUSH(sc, 0); 500 501 sc->sc_dmaaddr = addr; 502 sc->sc_dmalen = len; 503 504 DPRINTF(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 505 *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 506 507 /* 508 * the rules say we cannot transfer more than the limit 509 * of this DMA chip (64k for old and 16Mb for new), 510 * and we cannot cross a 16Mb boundary. 511 */ 512 *dmasize = sc->sc_dmasize = 513 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 514 515 DPRINTF(("dma_setup: dmasize = %d\n", sc->sc_dmasize)); 516 517 /* Program the DMA address */ 518 if (sc->sc_dmasize) { 519 int s = splserial(); /* XXX - what shall we choose? */ 520 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 521 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 522 *sc->sc_dmaaddr, sc->sc_dmasize, 523 NULL /* kernel address */, 524 BUS_DMA_NOWAIT)) 525 panic("%s: cannot allocate DVMA address", 526 sc->sc_dev.dv_xname); 527 splx(s); 528 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 529 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize, 530 datain 531 ? BUS_DMASYNC_PREREAD 532 : BUS_DMASYNC_PREWRITE); 533 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 534 sc->sc_dmamap->dm_segs[0].ds_addr); 535 536 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 537 sc->sc_dmasize); 538 } 539 540 /* Setup DMA control register */ 541 csr = L64854_GCSR(sc); 542 #if 0 543 /* This bit is read-only in PP csr register */ 544 if (datain) 545 csr |= L64854_WRITE; 546 else 547 csr &= ~L64854_WRITE; 548 #endif 549 csr |= L64854_INT_EN; 550 L64854_SCSR(sc, csr); 551 552 return (0); 553 } 554 /* 555 * Parallel port DMA interrupt. 556 */ 557 int 558 lsi64854_pp_intr(arg) 559 void *arg; 560 { 561 struct lsi64854_softc *sc = arg; 562 char bits[64]; 563 int ret, trans, resid = 0; 564 u_int32_t csr; 565 566 csr = L64854_GCSR(sc); 567 568 DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 569 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 570 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 571 572 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 573 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 574 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 575 csr &= ~P_EN_DMA; /* Stop DMA */ 576 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 577 csr |= P_INVALIDATE|P_SLAVE_ERR; 578 L64854_SCSR(sc, csr); 579 return (1); 580 } 581 582 ret = (csr & P_INT_PEND) != 0; 583 584 if (sc->sc_active != 0) { 585 DMA_DRAIN(sc, 0); 586 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 587 L64854_REG_CNT); 588 } 589 590 /* DMA has stopped */ 591 csr &= ~D_EN_DMA; 592 L64854_SCSR(sc, csr); 593 sc->sc_active = 0; 594 595 trans = sc->sc_dmasize - resid; 596 if (trans < 0) { /* transferred < 0 ? */ 597 trans = sc->sc_dmasize; 598 } 599 *sc->sc_dmalen -= trans; 600 *sc->sc_dmaaddr += trans; 601 602 if (sc->sc_dmamap->dm_nsegs > 0) { 603 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 604 (bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize, 605 (csr & D_WRITE) != 0 606 ? BUS_DMASYNC_POSTREAD 607 : BUS_DMASYNC_POSTWRITE); 608 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 609 } 610 611 ret |= (*sc->sc_intrchain)(sc->sc_intrchainarg); 612 return (ret != 0); 613 } 614
Indexes created Tue Sep 23 13:09:54 GMT 2025