malo.c revision 1.18.10.1
1 /* $NetBSD: malo.c,v 1.18.10.1 2021/06/17 04:46:28 thorpej Exp $ */ 2 /* $OpenBSD: malo.c,v 1.92 2010/08/27 17:08:00 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Claudio Jeker <claudio (at) openbsd.org> 6 * Copyright (c) 2006 Marcus Glocker <mglocker (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: malo.c,v 1.18.10.1 2021/06/17 04:46:28 thorpej Exp $"); 23 24 #include <sys/param.h> 25 #include <sys/types.h> 26 27 #include <sys/device.h> 28 #include <sys/kernel.h> 29 #include <sys/malloc.h> 30 #include <sys/mbuf.h> 31 #include <sys/proc.h> 32 #include <sys/socket.h> 33 #include <sys/sockio.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <machine/endian.h> 38 #include <machine/intr.h> 39 40 #include <net/if.h> 41 #include <net/if_media.h> 42 #include <net/if_ether.h> 43 44 #include <net/bpf.h> 45 46 #include <netinet/in.h> 47 #include <netinet/in_systm.h> 48 49 #include <net80211/ieee80211_var.h> 50 #include <net80211/ieee80211_radiotap.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/ic/malovar.h> 55 #include <dev/ic/maloreg.h> 56 57 #ifdef MALO_DEBUG 58 int malo_d = 2; 59 #define DPRINTF(l, x...) do { if ((l) <= malo_d) printf(x); } while (0) 60 #else 61 #define DPRINTF(l, x...) 62 #endif 63 64 /* internal structures and defines */ 65 struct malo_node { 66 struct ieee80211_node ni; 67 }; 68 69 struct malo_rx_data { 70 bus_dmamap_t map; 71 struct mbuf *m; 72 }; 73 74 struct malo_tx_data { 75 bus_dmamap_t map; 76 struct mbuf *m; 77 uint32_t softstat; 78 struct ieee80211_node *ni; 79 }; 80 81 /* RX descriptor used by HW */ 82 struct malo_rx_desc { 83 uint8_t rxctrl; 84 uint8_t rssi; 85 uint8_t status; 86 uint8_t channel; 87 uint16_t len; 88 uint8_t reserved1; /* actually unused */ 89 uint8_t datarate; 90 uint32_t physdata; /* DMA address of data */ 91 uint32_t physnext; /* DMA address of next control block */ 92 uint16_t qosctrl; 93 uint16_t reserved2; 94 } __packed; 95 96 /* TX descriptor used by HW */ 97 struct malo_tx_desc { 98 uint32_t status; 99 #define MALO_TXD_STATUS_IDLE 0x00000000 100 #define MALO_TXD_STATUS_USED 0x00000001 101 #define MALO_TXD_STATUS_OK 0x00000001 102 #define MALO_TXD_STATUS_OK_RETRY 0x00000002 103 #define MALO_TXD_STATUS_OK_MORE_RETRY 0x00000004 104 #define MALO_TXD_STATUS_MULTICAST_TX 0x00000008 105 #define MALO_TXD_STATUS_BROADCAST_TX 0x00000010 106 #define MALO_TXD_STATUS_FAILED_LINK_ERROR 0x00000020 107 #define MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040 108 #define MALO_TXD_STATUS_FAILED_XRETRY MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 109 #define MALO_TXD_STATUS_FAILED_AGING 0x00000080 110 #define MALO_TXD_STATUS_FW_OWNED 0x80000000 111 uint8_t datarate; 112 uint8_t txpriority; 113 uint16_t qosctrl; 114 uint32_t physdata; /* DMA address of data */ 115 uint16_t len; 116 uint8_t destaddr[6]; 117 uint32_t physnext; /* DMA address of next control block */ 118 uint32_t reserved1; /* SAP packet info ??? */ 119 uint32_t reserved2; 120 } __packed; 121 122 #define MALO_RX_RING_COUNT 256 123 #define MALO_TX_RING_COUNT 256 124 #define MALO_MAX_SCATTER 8 /* XXX unknown, wild guess */ 125 #define MALO_CMD_TIMEOUT 50 /* MALO_CMD_TIMEOUT * 100us */ 126 127 /* 128 * Firmware commands 129 */ 130 #define MALO_CMD_GET_HW_SPEC 0x0003 131 #define MALO_CMD_SET_RADIO 0x001c 132 #define MALO_CMD_SET_AID 0x010d 133 #define MALO_CMD_SET_TXPOWER 0x001e 134 #define MALO_CMD_SET_ANTENNA 0x0020 135 #define MALO_CMD_SET_PRESCAN 0x0107 136 #define MALO_CMD_SET_POSTSCAN 0x0108 137 #define MALO_CMD_SET_RATE 0x0110 138 #define MALO_CMD_SET_CHANNEL 0x010a 139 #define MALO_CMD_SET_RTS 0x0113 140 #define MALO_CMD_SET_SLOT 0x0114 141 #define MALO_CMD_RESPONSE 0x8000 142 143 #define MALO_CMD_RESULT_OK 0x0000 /* everything is fine */ 144 #define MALO_CMD_RESULT_ERROR 0x0001 /* general error */ 145 #define MALO_CMD_RESULT_NOSUPPORT 0x0002 /* command not valid */ 146 #define MALO_CMD_RESULT_PENDING 0x0003 /* will be processed */ 147 #define MALO_CMD_RESULT_BUSY 0x0004 /* command ignored */ 148 #define MALO_CMD_RESULT_PARTIALDATA 0x0005 /* buffer too small */ 149 150 struct malo_cmdheader { 151 uint16_t cmd; 152 uint16_t size; /* size of the command, incl. header */ 153 uint16_t seqnum; /* seems not to matter that much */ 154 uint16_t result; /* set to 0 on request */ 155 /* following the data payload, up to 256 bytes */ 156 }; 157 158 struct malo_hw_spec { 159 uint16_t HwVersion; 160 uint16_t NumOfWCB; 161 uint16_t NumOfMCastAdr; 162 uint8_t PermanentAddress[6]; 163 uint16_t RegionCode; 164 uint16_t NumberOfAntenna; 165 uint32_t FWReleaseNumber; 166 uint32_t WcbBase0; 167 uint32_t RxPdWrPtr; 168 uint32_t RxPdRdPtr; 169 uint32_t CookiePtr; 170 uint32_t WcbBase1; 171 uint32_t WcbBase2; 172 uint32_t WcbBase3; 173 } __packed; 174 175 struct malo_cmd_radio { 176 uint16_t action; 177 uint16_t preamble_mode; 178 uint16_t enable; 179 } __packed; 180 181 struct malo_cmd_aid { 182 uint16_t associd; 183 uint8_t macaddr[6]; 184 uint32_t gprotection; 185 uint8_t aprates[14]; 186 } __packed; 187 188 struct malo_cmd_txpower { 189 uint16_t action; 190 uint16_t supportpowerlvl; 191 uint16_t currentpowerlvl; 192 uint16_t reserved; 193 uint16_t powerlvllist[8]; 194 } __packed; 195 196 struct malo_cmd_antenna { 197 uint16_t action; 198 uint16_t mode; 199 } __packed; 200 201 struct malo_cmd_postscan { 202 uint32_t isibss; 203 uint8_t bssid[6]; 204 } __packed; 205 206 struct malo_cmd_channel { 207 uint16_t action; 208 uint8_t channel; 209 } __packed; 210 211 struct malo_cmd_rate { 212 uint8_t dataratetype; 213 uint8_t rateindex; 214 uint8_t aprates[14]; 215 } __packed; 216 217 struct malo_cmd_rts { 218 uint16_t action; 219 uint32_t threshold; 220 } __packed; 221 222 struct malo_cmd_slot { 223 uint16_t action; 224 uint8_t slot; 225 } __packed; 226 227 #define malo_mem_write4(sc, off, x) \ 228 bus_space_write_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off), (x)) 229 #define malo_mem_write2(sc, off, x) \ 230 bus_space_write_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off), (x)) 231 #define malo_mem_write1(sc, off, x) \ 232 bus_space_write_1((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off), (x)) 233 234 #define malo_mem_read4(sc, off) \ 235 bus_space_read_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off)) 236 #define malo_mem_read1(sc, off) \ 237 bus_space_read_1((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off)) 238 239 #define malo_ctl_write4(sc, off, x) \ 240 bus_space_write_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (x)) 241 #define malo_ctl_read4(sc, off) \ 242 bus_space_read_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off)) 243 #define malo_ctl_read1(sc, off) \ 244 bus_space_read_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off)) 245 246 #define malo_ctl_barrier(sc, t) \ 247 bus_space_barrier((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, 0x0c00, 0xff, (t)) 248 249 static int malo_alloc_cmd(struct malo_softc *sc); 250 static void malo_free_cmd(struct malo_softc *sc); 251 static void malo_send_cmd(struct malo_softc *sc, bus_addr_t addr); 252 static int malo_send_cmd_dma(struct malo_softc *sc, bus_addr_t addr); 253 static int malo_alloc_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring, 254 int count); 255 static void malo_reset_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring); 256 static void malo_free_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring); 257 static int malo_alloc_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring, 258 int count); 259 static void malo_reset_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring); 260 static void malo_free_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring); 261 static int malo_ioctl(struct ifnet *ifp, u_long cmd, void* data); 262 static void malo_start(struct ifnet *ifp); 263 static void malo_watchdog(struct ifnet *ifp); 264 static int malo_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 265 int arg); 266 static void malo_newassoc(struct ieee80211_node *ni, int isnew); 267 static struct ieee80211_node * 268 malo_node_alloc(struct ieee80211_node_table *nt); 269 static int malo_media_change(struct ifnet *ifp); 270 static void malo_media_status(struct ifnet *ifp, struct ifmediareq *imr); 271 static int malo_chip2rate(int chip_rate); 272 static int malo_fix2rate(int fix_rate); 273 static void malo_next_scan(void *arg); 274 static void malo_tx_intr(struct malo_softc *sc); 275 static int malo_tx_data(struct malo_softc *sc, struct mbuf *m0, 276 struct ieee80211_node *ni); 277 static void malo_tx_setup_desc(struct malo_softc *sc, struct malo_tx_desc *desc, 278 int len, int rate, const bus_dma_segment_t *segs, int nsegs); 279 static void malo_rx_intr(struct malo_softc *sc); 280 static int malo_load_bootimg(struct malo_softc *sc); 281 static int malo_load_firmware(struct malo_softc *sc); 282 283 static int malo_set_slot(struct malo_softc *sc); 284 static void malo_update_slot(struct ifnet* ifp); 285 #ifdef MALO_DEBUG 286 static void malo_hexdump(void *buf, int len); 287 #endif 288 static const char *malo_cmd_string(uint16_t cmd); 289 static const char *malo_cmd_string_result(uint16_t result); 290 static int malo_cmd_get_spec(struct malo_softc *sc); 291 static int malo_cmd_set_prescan(struct malo_softc *sc); 292 static int malo_cmd_set_postscan(struct malo_softc *sc, uint8_t *macaddr, 293 uint8_t ibsson); 294 static int malo_cmd_set_channel(struct malo_softc *sc, struct ieee80211_channel *chan); 295 static int malo_cmd_set_antenna(struct malo_softc *sc, uint16_t antenna_type); 296 static int malo_cmd_set_radio(struct malo_softc *sc, uint16_t mode, 297 uint16_t preamble); 298 static int malo_cmd_set_aid(struct malo_softc *sc, uint8_t *bssid, 299 uint16_t associd); 300 static int malo_cmd_set_txpower(struct malo_softc *sc, unsigned int powerlevel); 301 static int malo_cmd_set_rts(struct malo_softc *sc, uint32_t threshold); 302 static int malo_cmd_set_slot(struct malo_softc *sc, uint8_t slot); 303 static int malo_cmd_set_rate(struct malo_softc *sc, uint8_t rate); 304 static void malo_cmd_response(struct malo_softc *sc); 305 306 int 307 malo_intr(void *arg) 308 { 309 struct malo_softc *sc = arg; 310 uint32_t status; 311 312 status = malo_ctl_read4(sc, MALO_REG_A2H_INTERRUPT_CAUSE); 313 if (status == 0xffffffff || status == 0) 314 /* not for us */ 315 return (0); 316 317 /* disable interrupts */ 318 malo_ctl_read4(sc, MALO_REG_A2H_INTERRUPT_CAUSE); 319 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_CAUSE, 0); 320 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_MASK, 0); 321 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 0); 322 323 softint_schedule(sc->sc_soft_ih); 324 return (1); 325 } 326 327 void 328 malo_softintr(void *arg) 329 { 330 struct malo_softc *sc = arg; 331 uint32_t status; 332 333 status = malo_ctl_read4(sc, MALO_REG_A2H_INTERRUPT_CAUSE); 334 if (status == 0xffffffff || status == 0) 335 goto out; /* not for us */ 336 337 if (status & MALO_A2HRIC_BIT_TX_DONE) 338 malo_tx_intr(sc); 339 if (status & MALO_A2HRIC_BIT_RX_RDY) 340 malo_rx_intr(sc); 341 if (status & MALO_A2HRIC_BIT_OPC_DONE) { 342 /* XXX cmd done interrupt handling doesn't work yet */ 343 DPRINTF(1, "%s: got cmd done interrupt\n", 344 device_xname(sc->sc_dev)); 345 //malo_cmd_response(sc); 346 } 347 348 if (status & ~0x7) { 349 DPRINTF(1, "%s: unknown interrupt %x\n", 350 device_xname(sc->sc_dev), status); 351 } 352 353 /* just ack the interrupt */ 354 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_CAUSE, 0); 355 356 out: 357 /* enable interrupts */ 358 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_MASK, 0x1f); 359 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 360 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 0x1f); 361 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 362 } 363 364 int 365 malo_attach(struct malo_softc *sc) 366 { 367 struct ieee80211com *ic = &sc->sc_ic; 368 struct ifnet *ifp = &sc->sc_if; 369 int i; 370 371 /* initialize channel scanning timer */ 372 callout_init(&sc->sc_scan_to, 0); 373 callout_setfunc(&sc->sc_scan_to, malo_next_scan, sc); 374 375 /* allocate DMA structures */ 376 malo_alloc_cmd(sc); 377 malo_alloc_rx_ring(sc, &sc->sc_rxring, MALO_RX_RING_COUNT); 378 malo_alloc_tx_ring(sc, &sc->sc_txring, MALO_TX_RING_COUNT); 379 380 /* setup interface */ 381 ifp->if_softc = sc; 382 ifp->if_init = malo_init; 383 ifp->if_stop = malo_stop; 384 ifp->if_ioctl = malo_ioctl; 385 ifp->if_start = malo_start; 386 ifp->if_watchdog = malo_watchdog; 387 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 388 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 389 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 390 IFQ_SET_READY(&ifp->if_snd); 391 392 /* set supported rates */ 393 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 394 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 395 sc->sc_last_txrate = -1; 396 397 /* set channels */ 398 for (i = 1; i <= 14; i++) { 399 ic->ic_channels[i].ic_freq = 400 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 401 ic->ic_channels[i].ic_flags = 402 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 403 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 404 } 405 406 /* OpenBSD supports IEEE80211_C_RSN too */ 407 /* set the rest */ 408 ic->ic_ifp = ifp; 409 ic->ic_caps = 410 IEEE80211_C_IBSS | 411 IEEE80211_C_MONITOR | 412 IEEE80211_C_SHPREAMBLE | 413 IEEE80211_C_SHSLOT | 414 IEEE80211_C_WEP | 415 IEEE80211_C_WPA; 416 ic->ic_opmode = IEEE80211_M_STA; 417 ic->ic_state = IEEE80211_S_INIT; 418 for (i = 0; i < 6; i++) 419 ic->ic_myaddr[i] = malo_ctl_read1(sc, 0xa528 + i); 420 421 /* show our mac address */ 422 aprint_normal(", address %s\n", ether_sprintf(ic->ic_myaddr)); 423 424 /* attach interface */ 425 if_initialize(ifp); 426 ieee80211_ifattach(ic); 427 /* Use common softint-based if_input */ 428 ifp->if_percpuq = if_percpuq_create(ifp); 429 if_register(ifp); 430 431 /* post attach vector functions */ 432 sc->sc_newstate = ic->ic_newstate; 433 ic->ic_newstate = malo_newstate; 434 ic->ic_newassoc = malo_newassoc; 435 ic->ic_node_alloc = malo_node_alloc; 436 ic->ic_updateslot = malo_update_slot; 437 438 ieee80211_media_init(ic, malo_media_change, malo_media_status); 439 440 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 441 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 442 &sc->sc_drvbpf); 443 444 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 445 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 446 sc->sc_rxtap.wr_ihdr.it_present = htole32(MALO_RX_RADIOTAP_PRESENT); 447 448 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 449 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 450 sc->sc_txtap.wt_ihdr.it_present = htole32(MALO_TX_RADIOTAP_PRESENT); 451 452 ieee80211_announce(ic); 453 454 return (0); 455 } 456 457 int 458 malo_detach(void *arg) 459 { 460 struct malo_softc *sc = arg; 461 struct ieee80211com *ic = &sc->sc_ic; 462 struct ifnet *ifp = &sc->sc_if; 463 464 malo_stop(ifp, 1); 465 /* remove channel scanning timer */ 466 callout_destroy(&sc->sc_scan_to); 467 ieee80211_ifdetach(ic); 468 if_detach(ifp); 469 malo_free_cmd(sc); 470 malo_free_rx_ring(sc, &sc->sc_rxring); 471 malo_free_tx_ring(sc, &sc->sc_txring); 472 473 return (0); 474 } 475 476 static int 477 malo_alloc_cmd(struct malo_softc *sc) 478 { 479 int error, nsegs; 480 481 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, 482 PAGE_SIZE, 0, BUS_DMA_ALLOCNOW, &sc->sc_cmd_dmam); 483 if (error != 0) { 484 aprint_error_dev(sc->sc_dev, "can not create DMA tag\n"); 485 return (-1); 486 } 487 488 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 489 0, &sc->sc_cmd_dmas, 1, &nsegs, BUS_DMA_WAITOK); 490 if (error != 0) { 491 aprint_error_dev(sc->sc_dev, "error alloc dma memory\n"); 492 return (-1); 493 } 494 495 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_dmas, nsegs, 496 PAGE_SIZE, (void **)&sc->sc_cmd_mem, BUS_DMA_WAITOK); 497 if (error != 0) { 498 aprint_error_dev(sc->sc_dev, "error map dma memory\n"); 499 return (-1); 500 } 501 502 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_dmam, 503 sc->sc_cmd_mem, PAGE_SIZE, NULL, BUS_DMA_NOWAIT); 504 if (error != 0) { 505 aprint_error_dev(sc->sc_dev, "error load dma memory\n"); 506 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_dmas, nsegs); 507 return (-1); 508 } 509 510 sc->sc_cookie = sc->sc_cmd_mem; 511 *sc->sc_cookie = htole32(0xaa55aa55); 512 sc->sc_cmd_mem = ((char*)sc->sc_cmd_mem) + sizeof(uint32_t); 513 sc->sc_cookie_dmaaddr = sc->sc_cmd_dmam->dm_segs[0].ds_addr; 514 sc->sc_cmd_dmaaddr = sc->sc_cmd_dmam->dm_segs[0].ds_addr + 515 sizeof(uint32_t); 516 517 return (0); 518 } 519 520 static void 521 malo_free_cmd(struct malo_softc *sc) 522 { 523 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 524 BUS_DMASYNC_POSTWRITE); 525 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_dmam); 526 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cookie, PAGE_SIZE); 527 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_dmas, 1); 528 } 529 530 static void 531 malo_send_cmd(struct malo_softc *sc, bus_addr_t addr) 532 { 533 malo_ctl_write4(sc, MALO_REG_GEN_PTR, (uint32_t)addr); 534 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 535 malo_ctl_write4(sc, MALO_REG_H2A_INTERRUPT_EVENTS, 2); /* CPU_TRANSFER_CMD */ 536 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 537 } 538 539 static int 540 malo_send_cmd_dma(struct malo_softc *sc, bus_addr_t addr) 541 { 542 int i; 543 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 544 545 malo_send_cmd(sc, addr); 546 547 for (i = 0; i < MALO_CMD_TIMEOUT; i++) { 548 delay(100); 549 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 550 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 551 if (hdr->cmd & htole16(0x8000)) 552 break; 553 } 554 if (i == MALO_CMD_TIMEOUT) { 555 aprint_error_dev(sc->sc_dev, "timeout while waiting for cmd response!\n"); 556 return (ETIMEDOUT); 557 } 558 559 malo_cmd_response(sc); 560 561 return (0); 562 } 563 564 static int 565 malo_alloc_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring, int count) 566 { 567 struct malo_rx_desc *desc; 568 struct malo_rx_data *data; 569 int i, nsegs, error; 570 571 ring->count = count; 572 ring->cur = ring->next = 0; 573 574 error = bus_dmamap_create(sc->sc_dmat, 575 count * sizeof(struct malo_rx_desc), 1, 576 count * sizeof(struct malo_rx_desc), 0, 577 BUS_DMA_NOWAIT, &ring->map); 578 if (error != 0) { 579 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 580 goto fail; 581 } 582 583 error = bus_dmamem_alloc(sc->sc_dmat, 584 count * sizeof(struct malo_rx_desc), 585 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 586 587 if (error != 0) { 588 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 589 goto fail; 590 } 591 592 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 593 count * sizeof(struct malo_rx_desc), (void **)&ring->desc, 594 BUS_DMA_NOWAIT); 595 if (error != 0) { 596 aprint_error_dev(sc->sc_dev, "can't map desc DMA memory\n"); 597 goto fail; 598 } 599 600 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 601 count * sizeof(struct malo_rx_desc), NULL, BUS_DMA_NOWAIT); 602 if (error != 0) { 603 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 604 goto fail; 605 } 606 607 ring->physaddr = ring->map->dm_segs->ds_addr; 608 609 ring->data = malloc(count * sizeof (struct malo_rx_data), M_DEVBUF, 610 M_WAITOK); 611 612 /* 613 * Pre-allocate Rx buffers and populate Rx ring. 614 */ 615 memset(ring->data, 0, count * sizeof (struct malo_rx_data)); 616 for (i = 0; i < count; i++) { 617 desc = &ring->desc[i]; 618 data = &ring->data[i]; 619 620 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 621 0, BUS_DMA_NOWAIT, &data->map); 622 if (error != 0) { 623 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 624 goto fail; 625 } 626 627 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 628 if (data->m == NULL) { 629 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 630 error = ENOMEM; 631 goto fail; 632 } 633 634 MCLGET(data->m, M_DONTWAIT); 635 if (!(data->m->m_flags & M_EXT)) { 636 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 637 error = ENOMEM; 638 goto fail; 639 } 640 641 error = bus_dmamap_load(sc->sc_dmat, data->map, 642 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 643 if (error != 0) { 644 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map"); 645 goto fail; 646 } 647 648 desc->status = 1; 649 desc->physdata = htole32(data->map->dm_segs->ds_addr); 650 desc->physnext = htole32(ring->physaddr + 651 (i + 1) % count * sizeof(struct malo_rx_desc)); 652 } 653 654 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 655 BUS_DMASYNC_PREWRITE); 656 657 return (0); 658 659 fail: malo_free_rx_ring(sc, ring); 660 return (error); 661 } 662 663 static void 664 malo_reset_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring) 665 { 666 int i; 667 668 for (i = 0; i < ring->count; i++) 669 ring->desc[i].status = 0; 670 671 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 672 BUS_DMASYNC_PREWRITE); 673 674 ring->cur = ring->next = 0; 675 } 676 677 static void 678 malo_free_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring) 679 { 680 struct malo_rx_data *data; 681 int i; 682 683 if (ring->desc != NULL) { 684 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 685 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 686 bus_dmamap_unload(sc->sc_dmat, ring->map); 687 bus_dmamem_unmap(sc->sc_dmat, ring->desc, 688 ring->count * sizeof(struct malo_rx_desc)); 689 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 690 } 691 692 if (ring->data != NULL) { 693 for (i = 0; i < ring->count; i++) { 694 data = &ring->data[i]; 695 696 if (data->m != NULL) { 697 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 698 data->map->dm_mapsize, 699 BUS_DMASYNC_POSTREAD); 700 bus_dmamap_unload(sc->sc_dmat, data->map); 701 m_freem(data->m); 702 } 703 704 if (data->map != NULL) 705 bus_dmamap_destroy(sc->sc_dmat, data->map); 706 } 707 free(ring->data, M_DEVBUF); 708 } 709 } 710 711 static int 712 malo_alloc_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring, 713 int count) 714 { 715 int i, nsegs, error; 716 717 ring->count = count; 718 ring->queued = 0; 719 ring->cur = ring->next = ring->stat = 0; 720 721 error = bus_dmamap_create(sc->sc_dmat, 722 count * sizeof(struct malo_tx_desc), 1, 723 count * sizeof(struct malo_tx_desc), 0, BUS_DMA_NOWAIT, &ring->map); 724 if (error != 0) { 725 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 726 goto fail; 727 } 728 729 error = bus_dmamem_alloc(sc->sc_dmat, 730 count * sizeof(struct malo_tx_desc), PAGE_SIZE, 0, 731 &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 732 if (error != 0) { 733 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 734 goto fail; 735 } 736 737 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 738 count * sizeof(struct malo_tx_desc), (void **)&ring->desc, 739 BUS_DMA_NOWAIT); 740 if (error != 0) { 741 aprint_error_dev(sc->sc_dev, "can't map desc DMA memory\n"); 742 goto fail; 743 } 744 745 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 746 count * sizeof(struct malo_tx_desc), NULL, BUS_DMA_NOWAIT); 747 if (error != 0) { 748 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 749 goto fail; 750 } 751 752 ring->physaddr = ring->map->dm_segs->ds_addr; 753 754 ring->data = malloc(count * sizeof(struct malo_tx_data), M_DEVBUF, 755 M_WAITOK | M_ZERO); 756 757 for (i = 0; i < count; i++) { 758 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 759 MALO_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 760 &ring->data[i].map); 761 if (error != 0) { 762 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 763 goto fail; 764 } 765 ring->desc[i].physnext = htole32(ring->physaddr + 766 (i + 1) % count * sizeof(struct malo_tx_desc)); 767 } 768 769 return (0); 770 771 fail: malo_free_tx_ring(sc, ring); 772 return (error); 773 } 774 775 static void 776 malo_reset_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring) 777 { 778 struct malo_tx_desc *desc; 779 struct malo_tx_data *data; 780 int i; 781 782 for (i = 0; i < ring->count; i++) { 783 desc = &ring->desc[i]; 784 data = &ring->data[i]; 785 786 if (data->m != NULL) { 787 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 788 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 789 bus_dmamap_unload(sc->sc_dmat, data->map); 790 m_freem(data->m); 791 data->m = NULL; 792 } 793 794 /* 795 * The node has already been freed at that point so don't call 796 * ieee80211_release_node() here. 797 */ 798 data->ni = NULL; 799 800 desc->status = 0; 801 } 802 803 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 804 BUS_DMASYNC_PREWRITE); 805 806 ring->queued = 0; 807 ring->cur = ring->next = ring->stat = 0; 808 } 809 810 static void 811 malo_free_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring) 812 { 813 struct malo_tx_data *data; 814 int i; 815 816 if (ring->desc != NULL) { 817 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 818 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 819 bus_dmamap_unload(sc->sc_dmat, ring->map); 820 bus_dmamem_unmap(sc->sc_dmat, ring->desc, 821 ring->count * sizeof(struct malo_tx_desc)); 822 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 823 } 824 825 if (ring->data != NULL) { 826 for (i = 0; i < ring->count; i++) { 827 data = &ring->data[i]; 828 829 if (data->m != NULL) { 830 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 831 data->map->dm_mapsize, 832 BUS_DMASYNC_POSTWRITE); 833 bus_dmamap_unload(sc->sc_dmat, data->map); 834 m_freem(data->m); 835 } 836 837 /* 838 * The node has already been freed at that point so 839 * don't call ieee80211_release_node() here. 840 */ 841 data->ni = NULL; 842 843 if (data->map != NULL) 844 bus_dmamap_destroy(sc->sc_dmat, data->map); 845 } 846 free(ring->data, M_DEVBUF); 847 } 848 } 849 850 int 851 malo_init(struct ifnet *ifp) 852 { 853 struct malo_softc *sc = ifp->if_softc; 854 struct ieee80211com *ic = &sc->sc_ic; 855 int error; 856 857 DPRINTF(1, "%s: %s\n", ifp->if_xname, __func__); 858 859 /* if interface already runs stop it first */ 860 if (ifp->if_flags & IFF_RUNNING) 861 malo_stop(ifp, 1); 862 863 /* power on cardbus socket */ 864 if (sc->sc_enable) 865 sc->sc_enable(sc); 866 867 /* disable interrupts */ 868 malo_ctl_read4(sc, MALO_REG_A2H_INTERRUPT_CAUSE); 869 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_CAUSE, 0); 870 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_MASK, 0); 871 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 0); 872 873 /* load firmware */ 874 if ((error = malo_load_bootimg(sc))) 875 goto fail; 876 if ((error = malo_load_firmware(sc))) 877 goto fail; 878 879 /* enable interrupts */ 880 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_MASK, 0x1f); 881 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 882 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 0x1f); 883 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 884 885 if ((error = malo_cmd_get_spec(sc))) 886 goto fail; 887 888 /* select default channel */ 889 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 890 891 /* initialize hardware */ 892 if ((error = malo_cmd_set_channel(sc, ic->ic_bss->ni_chan))) { 893 aprint_error_dev(sc->sc_dev, "setting channel failed!\n"); 894 goto fail; 895 } 896 if ((error = malo_cmd_set_antenna(sc, 1))) { 897 aprint_error_dev(sc->sc_dev, "setting RX antenna failed!\n"); 898 goto fail; 899 } 900 if ((error = malo_cmd_set_antenna(sc, 2))) { 901 aprint_error_dev(sc->sc_dev, "setting TX antenna failed!\n"); 902 goto fail; 903 } 904 if ((error = malo_cmd_set_radio(sc, 1, 5))) { 905 aprint_error_dev(sc->sc_dev, "turn radio on failed!\n"); 906 goto fail; 907 } 908 if ((error = malo_cmd_set_txpower(sc, 100))) { 909 aprint_error_dev(sc->sc_dev, "setting TX power failed!\n"); 910 goto fail; 911 } 912 if ((error = malo_cmd_set_rts(sc, IEEE80211_RTS_MAX))) { 913 aprint_error_dev(sc->sc_dev, "setting RTS failed!\n"); 914 goto fail; 915 } 916 917 ifp->if_flags |= IFF_RUNNING; 918 919 if (ic->ic_opmode != IEEE80211_M_MONITOR) 920 /* start background scanning */ 921 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 922 else 923 /* in monitor mode change directly into run state */ 924 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 925 926 return (0); 927 928 fail: 929 /* reset adapter */ 930 DPRINTF(1, "%s: malo_init failed, resetting card\n", 931 device_xname(sc->sc_dev)); 932 malo_stop(ifp, 1); 933 return (error); 934 } 935 936 static int 937 malo_ioctl(struct ifnet *ifp, u_long cmd, void* data) 938 { 939 struct malo_softc *sc = ifp->if_softc; 940 struct ieee80211com *ic = &sc->sc_ic; 941 int s, error = 0; 942 943 s = splnet(); 944 945 switch (cmd) { 946 case SIOCSIFFLAGS: 947 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 948 break; 949 if (ifp->if_flags & IFF_UP) { 950 if ((ifp->if_flags & IFF_RUNNING) == 0) 951 malo_init(ifp); 952 } else { 953 if (ifp->if_flags & IFF_RUNNING) 954 malo_stop(ifp, 1); 955 } 956 break; 957 case SIOCADDMULTI: 958 case SIOCDELMULTI: 959 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 960 /* setup multicast filter, etc */ 961 error = 0; 962 } 963 break; 964 case SIOCS80211CHANNEL: 965 /* allow fast channel switching in monitor mode */ 966 error = ieee80211_ioctl(ic, cmd, data); 967 if (error == ENETRESET && 968 ic->ic_opmode == IEEE80211_M_MONITOR) { 969 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 970 (IFF_UP | IFF_RUNNING)) { 971 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 972 malo_cmd_set_channel(sc, ic->ic_bss->ni_chan); 973 } 974 error = 0; 975 } 976 break; 977 default: 978 error = ieee80211_ioctl(ic, cmd, data); 979 break; 980 } 981 982 if (error == ENETRESET) { 983 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 984 (IFF_UP | IFF_RUNNING)) 985 malo_init(ifp); 986 error = 0; 987 } 988 989 splx(s); 990 991 return (error); 992 } 993 994 static void 995 malo_start(struct ifnet *ifp) 996 { 997 struct malo_softc *sc = ifp->if_softc; 998 struct ieee80211com *ic = &sc->sc_ic; 999 struct mbuf *m0; 1000 struct ether_header *eh; 1001 struct ieee80211_node *ni = NULL; 1002 1003 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 1004 1005 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1006 return; 1007 1008 for (;;) { 1009 IF_POLL(&ic->ic_mgtq, m0); 1010 if (m0 != NULL) { 1011 if (sc->sc_txring.queued >= MALO_TX_RING_COUNT) { 1012 ifp->if_flags |= IFF_OACTIVE; 1013 break; 1014 } 1015 IF_DEQUEUE(&ic->ic_mgtq, m0); 1016 1017 ni = M_GETCTX(m0, struct ieee80211_node *); 1018 M_CLEARCTX(m0); 1019 1020 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1021 1022 if (malo_tx_data(sc, m0, ni) != 0) 1023 break; 1024 } else { 1025 if (ic->ic_state != IEEE80211_S_RUN) 1026 break; 1027 IFQ_POLL(&ifp->if_snd, m0); 1028 if (m0 == NULL) 1029 break; 1030 if (sc->sc_txring.queued >= MALO_TX_RING_COUNT - 1) { 1031 ifp->if_flags |= IFF_OACTIVE; 1032 break; 1033 } 1034 1035 if (m0->m_len < sizeof (*eh) && 1036 (m0 = m_pullup(m0, sizeof (*eh))) == NULL) { 1037 if_statinc(ifp, if_oerrors); 1038 continue; 1039 } 1040 eh = mtod(m0, struct ether_header *); 1041 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1042 if (ni == NULL) { 1043 m_freem(m0); 1044 if_statinc(ifp, if_oerrors); 1045 continue; 1046 } 1047 1048 // XXX must I call ieee_classify at this point ? 1049 1050 IFQ_DEQUEUE(&ifp->if_snd, m0); 1051 bpf_mtap(ifp, m0, BPF_D_OUT); 1052 1053 m0 = ieee80211_encap(ic, m0, ni); 1054 if (m0 == NULL) 1055 continue; 1056 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1057 1058 if (malo_tx_data(sc, m0, ni) != 0) { 1059 ieee80211_free_node(ni); 1060 if_statinc(ifp, if_oerrors); 1061 break; 1062 } 1063 } 1064 } 1065 } 1066 1067 void 1068 malo_stop(struct ifnet* ifp, int disable) 1069 { 1070 struct malo_softc *sc = ifp->if_softc; 1071 struct ieee80211com *ic = &sc->sc_ic; 1072 1073 DPRINTF(1, "%s: %s\n", ifp->if_xname, __func__); 1074 1075 /* reset adapter */ 1076 if (ifp->if_flags & IFF_RUNNING) 1077 malo_ctl_write4(sc, MALO_REG_H2A_INTERRUPT_EVENTS, (1 << 15)); 1078 1079 /* device is not running anymore */ 1080 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1081 1082 /* change back to initial state */ 1083 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1084 1085 /* reset RX / TX rings */ 1086 malo_reset_tx_ring(sc, &sc->sc_txring); 1087 malo_reset_rx_ring(sc, &sc->sc_rxring); 1088 1089 /* set initial rate */ 1090 sc->sc_last_txrate = -1; 1091 1092 /* power off cardbus socket */ 1093 if (sc->sc_disable) 1094 sc->sc_disable(sc); 1095 } 1096 1097 static void 1098 malo_watchdog(struct ifnet *ifp) 1099 { 1100 1101 } 1102 1103 static int 1104 malo_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1105 { 1106 struct ifnet *ifp = ic->ic_ifp; 1107 struct malo_softc *sc = ifp->if_softc; 1108 enum ieee80211_state ostate; 1109 int rate; 1110 1111 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 1112 1113 ostate = ic->ic_state; 1114 callout_stop(&sc->sc_scan_to); 1115 1116 switch (nstate) { 1117 case IEEE80211_S_INIT: 1118 DPRINTF(1, "%s: newstate INIT\n", device_xname(sc->sc_dev)); 1119 break; 1120 case IEEE80211_S_SCAN: 1121 DPRINTF(1, "%s: newstate SCAN\n", device_xname(sc->sc_dev)); 1122 if (ostate == IEEE80211_S_INIT) { 1123 if (malo_cmd_set_prescan(sc) != 0) { 1124 DPRINTF(1, "%s: can't set prescan\n", 1125 device_xname(sc->sc_dev)); 1126 } 1127 } else { 1128 malo_cmd_set_channel(sc, ic->ic_curchan); 1129 } 1130 callout_schedule(&sc->sc_scan_to, hz/2); 1131 break; 1132 case IEEE80211_S_AUTH: 1133 DPRINTF(1, "%s: newstate AUTH\n", device_xname(sc->sc_dev)); 1134 malo_cmd_set_postscan(sc, ic->ic_myaddr, 1); 1135 malo_cmd_set_channel(sc, ic->ic_curchan); 1136 break; 1137 case IEEE80211_S_ASSOC: 1138 DPRINTF(1, "%s: newstate ASSOC\n", device_xname(sc->sc_dev)); 1139 malo_cmd_set_channel(sc, ic->ic_curchan); 1140 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1141 malo_cmd_set_radio(sc, 1, 3); /* short preamble */ 1142 else 1143 malo_cmd_set_radio(sc, 1, 1); /* long preamble */ 1144 1145 malo_cmd_set_aid(sc, ic->ic_bss->ni_bssid, 1146 ic->ic_bss->ni_associd); 1147 1148 if (ic->ic_fixed_rate == -1) 1149 /* automatic rate adaption */ 1150 malo_cmd_set_rate(sc, 0); 1151 else { 1152 /* fixed rate */ 1153 rate = malo_fix2rate(ic->ic_fixed_rate); 1154 malo_cmd_set_rate(sc, rate); 1155 } 1156 1157 malo_set_slot(sc); 1158 break; 1159 case IEEE80211_S_RUN: 1160 DPRINTF(1, "%s: newstate RUN\n", device_xname(sc->sc_dev)); 1161 break; 1162 default: 1163 break; 1164 } 1165 1166 return (sc->sc_newstate(ic, nstate, arg)); 1167 } 1168 1169 static void 1170 malo_newassoc(struct ieee80211_node *ni, int isnew) 1171 { 1172 } 1173 1174 static struct ieee80211_node * 1175 malo_node_alloc(struct ieee80211_node_table *nt) 1176 { 1177 struct malo_node *wn; 1178 1179 wn = malloc(sizeof(*wn), M_DEVBUF, M_NOWAIT | M_ZERO); 1180 if (wn == NULL) 1181 return (NULL); 1182 1183 return ((struct ieee80211_node *)wn); 1184 } 1185 1186 static int 1187 malo_media_change(struct ifnet *ifp) 1188 { 1189 int error; 1190 1191 DPRINTF(1, "%s: %s\n", ifp->if_xname, __func__); 1192 1193 error = ieee80211_media_change(ifp); 1194 if (error != ENETRESET) 1195 return (error); 1196 1197 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1198 malo_init(ifp); 1199 1200 return (0); 1201 } 1202 1203 static void 1204 malo_media_status(struct ifnet *ifp, struct ifmediareq *imr) 1205 { 1206 struct malo_softc *sc = ifp->if_softc; 1207 struct ieee80211com *ic = &sc->sc_ic; 1208 1209 imr->ifm_status = IFM_AVALID; 1210 imr->ifm_active = IFM_IEEE80211; 1211 if (ic->ic_state == IEEE80211_S_RUN) 1212 imr->ifm_status |= IFM_ACTIVE; 1213 1214 /* report last TX rate used by chip */ 1215 imr->ifm_active |= ieee80211_rate2media(ic, sc->sc_last_txrate, 1216 ic->ic_curmode); 1217 1218 switch (ic->ic_opmode) { 1219 case IEEE80211_M_STA: 1220 break; 1221 case IEEE80211_M_IBSS: 1222 imr->ifm_active |= IFM_IEEE80211_ADHOC; 1223 break; 1224 case IEEE80211_M_AHDEMO: 1225 break; 1226 case IEEE80211_M_HOSTAP: 1227 break; 1228 case IEEE80211_M_MONITOR: 1229 imr->ifm_active |= IFM_IEEE80211_MONITOR; 1230 break; 1231 default: 1232 break; 1233 } 1234 1235 switch (ic->ic_curmode) { 1236 case IEEE80211_MODE_11B: 1237 imr->ifm_active |= IFM_IEEE80211_11B; 1238 break; 1239 case IEEE80211_MODE_11G: 1240 imr->ifm_active |= IFM_IEEE80211_11G; 1241 break; 1242 } 1243 } 1244 1245 static int 1246 malo_chip2rate(int chip_rate) 1247 { 1248 switch (chip_rate) { 1249 /* CCK rates */ 1250 case 0: return (2); 1251 case 1: return (4); 1252 case 2: return (11); 1253 case 3: return (22); 1254 1255 /* OFDM rates */ 1256 case 4: return (0); /* reserved */ 1257 case 5: return (12); 1258 case 6: return (18); 1259 case 7: return (24); 1260 case 8: return (36); 1261 case 9: return (48); 1262 case 10: return (72); 1263 case 11: return (96); 1264 case 12: return (108); 1265 1266 /* no rate select yet or unknown rate */ 1267 default: return (-1); 1268 } 1269 } 1270 1271 static int 1272 malo_fix2rate(int fix_rate) 1273 { 1274 switch (fix_rate) { 1275 /* CCK rates */ 1276 case 0: return (2); 1277 case 1: return (4); 1278 case 2: return (11); 1279 case 3: return (22); 1280 1281 /* OFDM rates */ 1282 case 4: return (12); 1283 case 5: return (18); 1284 case 6: return (24); 1285 case 7: return (36); 1286 case 8: return (48); 1287 case 9: return (72); 1288 case 10: return (96); 1289 case 11: return (108); 1290 1291 /* unknown rate: should not happen */ 1292 default: return (0); 1293 } 1294 } 1295 1296 static void 1297 malo_next_scan(void *arg) 1298 { 1299 struct malo_softc *sc = arg; 1300 struct ieee80211com *ic = &sc->sc_ic; 1301 int s; 1302 1303 DPRINTF(1, "%s: %s\n", sc->sc_if.if_xname, __func__); 1304 1305 s = splnet(); 1306 1307 if (ic->ic_state == IEEE80211_S_SCAN) 1308 ieee80211_next_scan(ic); 1309 1310 splx(s); 1311 } 1312 1313 static void 1314 malo_tx_intr(struct malo_softc *sc) 1315 { 1316 struct ifnet *ifp = &sc->sc_if; 1317 struct malo_tx_desc *desc; 1318 struct malo_tx_data *data; 1319 struct malo_node *rn; 1320 int stat, s; 1321 1322 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 1323 1324 s = splnet(); 1325 1326 stat = sc->sc_txring.stat; 1327 for (;;) { 1328 desc = &sc->sc_txring.desc[sc->sc_txring.stat]; 1329 data = &sc->sc_txring.data[sc->sc_txring.stat]; 1330 rn = (struct malo_node *)data->ni; 1331 1332 /* check if TX descriptor is not owned by FW anymore */ 1333 if ((le32toh(desc->status) & MALO_TXD_STATUS_FW_OWNED) || 1334 !(le32toh(data->softstat) & MALO_TXD_STATUS_FAILED_AGING)) 1335 break; 1336 1337 /* if no frame has been sent, ignore */ 1338 if (rn == NULL) 1339 goto next; 1340 1341 /* check TX state */ 1342 switch (le32toh(desc->status) & MALO_TXD_STATUS_USED) { 1343 case MALO_TXD_STATUS_OK: 1344 DPRINTF(2, "%s: data frame was sent successfully\n", 1345 device_xname(sc->sc_dev)); 1346 if_statinc(ifp, if_opackets); 1347 break; 1348 default: 1349 DPRINTF(1, "%s: data frame sending error\n", 1350 device_xname(sc->sc_dev)); 1351 if_statinc(ifp, if_oerrors); 1352 break; 1353 } 1354 1355 /* save last used TX rate */ 1356 sc->sc_last_txrate = malo_chip2rate(desc->datarate); 1357 1358 /* cleanup TX data and TX descriptor */ 1359 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1360 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1361 bus_dmamap_unload(sc->sc_dmat, data->map); 1362 m_freem(data->m); 1363 ieee80211_free_node(data->ni); 1364 data->m = NULL; 1365 data->ni = NULL; 1366 data->softstat &= htole32(~0x80); 1367 desc->status = 0; 1368 desc->len = 0; 1369 1370 DPRINTF(2, "%s: tx done idx=%u\n", 1371 device_xname(sc->sc_dev), sc->sc_txring.stat); 1372 1373 sc->sc_txring.queued--; 1374 next: 1375 if (++sc->sc_txring.stat >= sc->sc_txring.count) 1376 sc->sc_txring.stat = 0; 1377 if (sc->sc_txring.stat == stat) 1378 break; 1379 } 1380 1381 sc->sc_tx_timer = 0; 1382 ifp->if_flags &= ~IFF_OACTIVE; 1383 malo_start(ifp); 1384 1385 splx(s); 1386 } 1387 1388 static int 1389 malo_tx_data(struct malo_softc *sc, struct mbuf *m0, 1390 struct ieee80211_node *ni) 1391 { 1392 struct ieee80211com *ic = &sc->sc_ic; 1393 struct ifnet *ifp = &sc->sc_if; 1394 struct malo_tx_desc *desc; 1395 struct malo_tx_data *data; 1396 struct ieee80211_frame *wh; 1397 struct ieee80211_key *k; 1398 struct mbuf *mnew; 1399 int error; 1400 1401 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 1402 1403 desc = &sc->sc_txring.desc[sc->sc_txring.cur]; 1404 data = &sc->sc_txring.data[sc->sc_txring.cur]; 1405 1406 if (m0->m_len < sizeof(struct ieee80211_frame)) { 1407 m0 = m_pullup(m0, sizeof(struct ieee80211_frame)); 1408 if (m0 == NULL) { 1409 if_statinc(ifp, if_ierrors); 1410 return (ENOBUFS); 1411 } 1412 } 1413 wh = mtod(m0, struct ieee80211_frame *); 1414 1415 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1416 k = ieee80211_crypto_encap(ic, ni, m0); 1417 if (k == NULL) { 1418 m_freem(m0); 1419 return ENOBUFS; 1420 } 1421 1422 /* packet header may have moved, reset our local pointer */ 1423 wh = mtod(m0, struct ieee80211_frame *); 1424 } 1425 1426 if (sc->sc_drvbpf != NULL) { 1427 struct malo_tx_radiotap_hdr *tap = &sc->sc_txtap; 1428 1429 tap->wt_flags = 0; 1430 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 1431 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 1432 tap->wt_rate = sc->sc_last_txrate; 1433 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1434 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1435 1436 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1437 } 1438 1439 /* 1440 * inject FW specific fields into the 802.11 frame 1441 * 1442 * 2 bytes FW len (inject) 1443 * 24 bytes 802.11 frame header 1444 * 6 bytes addr4 (inject) 1445 * n bytes 802.11 frame body 1446 * 1447 * For now copy all into a new mcluster. 1448 */ 1449 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1450 if (mnew == NULL) 1451 return (ENOBUFS); 1452 MCLGET(mnew, M_DONTWAIT); 1453 if (!(mnew->m_flags & M_EXT)) { 1454 m_free(mnew); 1455 return (ENOBUFS); 1456 } 1457 1458 *mtod(mnew, uint16_t *) = htole16(m0->m_pkthdr.len - 24); /* FW len */ 1459 memmove(mtod(mnew, char*) + 2, wh, sizeof(*wh)); 1460 memset(mtod(mnew, char*) + 26, 0, 6); 1461 m_copydata(m0, sizeof(*wh), m0->m_pkthdr.len - sizeof(*wh), 1462 mtod(mnew, char*) + 32); 1463 mnew->m_pkthdr.len = mnew->m_len = m0->m_pkthdr.len + 8; 1464 m_freem(m0); 1465 m0 = mnew; 1466 1467 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1468 BUS_DMA_NOWAIT); 1469 if (error != 0) { 1470 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", error); 1471 m_freem(m0); 1472 return (error); 1473 } 1474 1475 data->m = m0; 1476 data->ni = ni; 1477 data->softstat |= htole32(0x80); 1478 1479 malo_tx_setup_desc(sc, desc, m0->m_pkthdr.len, 1, 1480 data->map->dm_segs, data->map->dm_nsegs); 1481 1482 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1483 BUS_DMASYNC_PREWRITE); 1484 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring.map, 1485 sc->sc_txring.cur * sizeof(struct malo_tx_desc), 1486 sizeof(struct malo_tx_desc), BUS_DMASYNC_PREWRITE); 1487 1488 DPRINTF(2, "%s: sending frame, pktlen=%u, idx=%u\n", 1489 device_xname(sc->sc_dev), m0->m_pkthdr.len, sc->sc_txring.cur); 1490 1491 sc->sc_txring.queued++; 1492 sc->sc_txring.cur = (sc->sc_txring.cur + 1) % MALO_TX_RING_COUNT; 1493 1494 /* kick data TX */ 1495 malo_ctl_write4(sc, MALO_REG_H2A_INTERRUPT_EVENTS, 1); 1496 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 1497 1498 return (0); 1499 } 1500 1501 static void 1502 malo_tx_setup_desc(struct malo_softc *sc, struct malo_tx_desc *desc, 1503 int len, int rate, const bus_dma_segment_t *segs, int nsegs) 1504 { 1505 desc->len = htole16(segs[0].ds_len); 1506 desc->datarate = rate; /* 0 = mgmt frame, 1 = data frame */ 1507 desc->physdata = htole32(segs[0].ds_addr); 1508 desc->status = htole32(MALO_TXD_STATUS_OK | MALO_TXD_STATUS_FW_OWNED); 1509 } 1510 1511 static void 1512 malo_rx_intr(struct malo_softc *sc) 1513 { 1514 struct ieee80211com *ic = &sc->sc_ic; 1515 struct ifnet *ifp = &sc->sc_if; 1516 struct malo_rx_desc *desc; 1517 struct malo_rx_data *data; 1518 struct ieee80211_frame *wh; 1519 struct ieee80211_node *ni; 1520 struct mbuf *mnew, *m; 1521 uint32_t rxRdPtr, rxWrPtr; 1522 int error, i, s; 1523 1524 rxRdPtr = malo_mem_read4(sc, sc->sc_RxPdRdPtr); 1525 rxWrPtr = malo_mem_read4(sc, sc->sc_RxPdWrPtr); 1526 1527 for (i = 0; i < MALO_RX_RING_COUNT && rxRdPtr != rxWrPtr; i++) { 1528 desc = &sc->sc_rxring.desc[sc->sc_rxring.cur]; 1529 data = &sc->sc_rxring.data[sc->sc_rxring.cur]; 1530 1531 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring.map, 1532 sc->sc_rxring.cur * sizeof(struct malo_rx_desc), 1533 sizeof(struct malo_rx_desc), BUS_DMASYNC_POSTREAD); 1534 1535 DPRINTF(3, "%s: rx intr idx=%d, rxctrl=0x%02x, rssi=%d, " 1536 "status=0x%02x, channel=%d, len=%d, res1=%02x, rate=%d, " 1537 "physdata=0x%04x, physnext=0x%04x, qosctrl=%02x, res2=%d\n", 1538 device_xname(sc->sc_dev), 1539 sc->sc_rxring.cur, desc->rxctrl, desc->rssi, desc->status, 1540 desc->channel, le16toh(desc->len), desc->reserved1, 1541 desc->datarate, le32toh(desc->physdata), 1542 le32toh(desc->physnext), desc->qosctrl, desc->reserved2); 1543 1544 if ((desc->rxctrl & 0x80) == 0) 1545 break; 1546 1547 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1548 if (mnew == NULL) { 1549 if_statinc(ifp, if_ierrors); 1550 goto skip; 1551 } 1552 1553 MCLGET(mnew, M_DONTWAIT); 1554 if (!(mnew->m_flags & M_EXT)) { 1555 m_freem(mnew); 1556 if_statinc(ifp, if_ierrors); 1557 goto skip; 1558 } 1559 1560 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1561 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1562 bus_dmamap_unload(sc->sc_dmat, data->map); 1563 1564 error = bus_dmamap_load(sc->sc_dmat, data->map, 1565 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1566 if (error != 0) { 1567 m_freem(mnew); 1568 1569 error = bus_dmamap_load(sc->sc_dmat, data->map, 1570 mtod(data->m, void *), MCLBYTES, NULL, 1571 BUS_DMA_NOWAIT); 1572 if (error != 0) { 1573 panic("%s: could not load old rx mbuf", 1574 device_xname(sc->sc_dev)); 1575 } 1576 if_statinc(ifp, if_ierrors); 1577 goto skip; 1578 } 1579 1580 /* 1581 * New mbuf mbuf successfully loaded 1582 */ 1583 m = data->m; 1584 data->m = mnew; 1585 desc->physdata = htole32(data->map->dm_segs->ds_addr); 1586 1587 /* finalize mbuf */ 1588 m_set_rcvif(m, ifp); 1589 m->m_pkthdr.len = m->m_len = le16toh(desc->len); 1590 1591 /* 1592 * cut out FW specific fields from the 802.11 frame 1593 * 1594 * 2 bytes FW len (cut out) 1595 * 24 bytes 802.11 frame header 1596 * 6 bytes addr4 (cut out) 1597 * n bytes 802.11 frame data 1598 */ 1599 memmove(m->m_data +6, m->m_data, 26); 1600 m_adj(m, 8); 1601 1602 s = splnet(); 1603 1604 if (sc->sc_drvbpf != NULL) { 1605 struct malo_rx_radiotap_hdr *tap = &sc->sc_rxtap; 1606 1607 tap->wr_flags = 0; 1608 tap->wr_chan_freq = 1609 htole16(ic->ic_bss->ni_chan->ic_freq); 1610 tap->wr_chan_flags = 1611 htole16(ic->ic_bss->ni_chan->ic_flags); 1612 1613 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, 1614 BPF_D_IN); 1615 } 1616 1617 wh = mtod(m, struct ieee80211_frame *); 1618 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1619 1620 /* send the frame to the 802.11 layer */ 1621 ieee80211_input(ic, m, ni, desc->rssi, 0); 1622 1623 /* node is no longer needed */ 1624 ieee80211_free_node(ni); 1625 1626 splx(s); 1627 1628 skip: 1629 desc->rxctrl = 0; 1630 rxRdPtr = le32toh(desc->physnext); 1631 1632 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring.map, 1633 sc->sc_rxring.cur * sizeof(struct malo_rx_desc), 1634 sizeof(struct malo_rx_desc), BUS_DMASYNC_PREWRITE); 1635 1636 sc->sc_rxring.cur = (sc->sc_rxring.cur + 1) % 1637 MALO_RX_RING_COUNT; 1638 } 1639 1640 malo_mem_write4(sc, sc->sc_RxPdRdPtr, rxRdPtr); 1641 } 1642 1643 static int 1644 malo_get_firmware(struct malo_softc *sc, const char *name, 1645 uint8_t** firmware_image, size_t* size) 1646 { 1647 firmware_handle_t fw; 1648 int error; 1649 1650 1651 /* load firmware image from disk */ 1652 if ((error = firmware_open("malo", name, &fw)) != 0) { 1653 aprint_error_dev(sc->sc_dev, "could not read firmware file\n"); 1654 return error; 1655 } 1656 1657 *size = firmware_get_size(fw); 1658 1659 *firmware_image = firmware_malloc(*size); 1660 if (*firmware_image == NULL) { 1661 aprint_error_dev(sc->sc_dev, "not enough memory to stock firmware\n"); 1662 error = ENOMEM; 1663 goto fail1; 1664 } 1665 1666 if ((error = firmware_read(fw, 0, *firmware_image, *size)) != 0) { 1667 aprint_error_dev(sc->sc_dev, "can't get firmware\n"); 1668 goto fail2; 1669 } 1670 1671 firmware_close(fw); 1672 1673 return 0; 1674 fail2: 1675 firmware_free(*firmware_image, *size); 1676 fail1: 1677 firmware_close(fw); 1678 return error; 1679 } 1680 1681 static int 1682 malo_load_bootimg(struct malo_softc *sc) 1683 { 1684 const char *name = "malo8335-h"; 1685 uint8_t *ucode; 1686 size_t size; 1687 int error, i; 1688 1689 /* load boot firmware */ 1690 if ((error = malo_get_firmware(sc, name, &ucode, &size)) != 0) { 1691 aprint_error_dev(sc->sc_dev, "error %d, could not read firmware %s\n", 1692 error, name); 1693 return (EIO); 1694 } 1695 1696 /* 1697 * It seems we are putting this code directly onto the stack of 1698 * the ARM cpu. I don't know why we need to instruct the DMA 1699 * engine to move the code. This is a big riddle without docu. 1700 */ 1701 DPRINTF(1, "%s: loading boot firmware\n", device_xname(sc->sc_dev)); 1702 malo_mem_write2(sc, 0xbef8, 0x001); 1703 malo_mem_write2(sc, 0xbefa, size); 1704 malo_mem_write4(sc, 0xbefc, 0); 1705 1706 bus_space_write_region_1(sc->sc_mem1_bt, sc->sc_mem1_bh, 0xbf00, 1707 ucode, size); 1708 1709 firmware_free(ucode, size); 1710 1711 /* 1712 * we loaded the firmware into card memory now tell the CPU 1713 * to fetch the code and execute it. The memory mapped via the 1714 * first bar is internaly mapped to 0xc0000000. 1715 */ 1716 malo_send_cmd(sc, 0xc000bef8); 1717 1718 /* wait for the device to go into FW loading mode */ 1719 for (i = 0; i < 10; i++) { 1720 delay(50); 1721 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_READ); 1722 if (malo_ctl_read4(sc, 0x0c14) == 0x5) 1723 break; 1724 } 1725 if (i == 10) { 1726 aprint_error_dev(sc->sc_dev, "timeout at boot firmware load!\n"); 1727 return (ETIMEDOUT); 1728 } 1729 1730 /* tell the card we're done and... */ 1731 malo_mem_write2(sc, 0xbef8, 0x001); 1732 malo_mem_write2(sc, 0xbefa, 0); 1733 malo_mem_write4(sc, 0xbefc, 0); 1734 malo_send_cmd(sc, 0xc000bef8); 1735 1736 DPRINTF(1, "%s: boot firmware loaded\n", device_xname(sc->sc_dev)); 1737 1738 return (0); 1739 } 1740 1741 1742 static int 1743 malo_load_firmware(struct malo_softc *sc) 1744 { 1745 struct malo_cmdheader *hdr; 1746 const char *name = "malo8335-m"; 1747 void *data; 1748 uint8_t *ucode; 1749 size_t size, count, bsize; 1750 int i, sn, error; 1751 1752 /* load real firmware now */ 1753 if ((error = malo_get_firmware(sc, name, &ucode, &size)) != 0) { 1754 aprint_error_dev(sc->sc_dev, "error %d, could not read firmware %s\n", 1755 error, name); 1756 return (EIO); 1757 } 1758 1759 DPRINTF(1, "%s: uploading firmware\n", device_xname(sc->sc_dev)); 1760 1761 hdr = sc->sc_cmd_mem; 1762 data = hdr + 1; 1763 sn = 1; 1764 for (count = 0; count < size; count += bsize) { 1765 bsize = MIN(256, size - count); 1766 1767 hdr->cmd = htole16(0x0001); 1768 hdr->size = htole16(bsize); 1769 hdr->seqnum = htole16(sn++); 1770 hdr->result = 0; 1771 1772 memcpy(data, ucode + count, bsize); 1773 1774 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1775 BUS_DMASYNC_PREWRITE); 1776 malo_send_cmd(sc, sc->sc_cmd_dmaaddr); 1777 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1778 BUS_DMASYNC_POSTWRITE); 1779 delay(500); 1780 } 1781 firmware_free(ucode, size); 1782 1783 DPRINTF(1, "%s: firmware upload finished\n", device_xname(sc->sc_dev)); 1784 1785 /* 1786 * send a command with size 0 to tell that the firmware has been 1787 * uploaded 1788 */ 1789 hdr->cmd = htole16(0x0001); 1790 hdr->size = 0; 1791 hdr->seqnum = htole16(sn++); 1792 hdr->result = 0; 1793 1794 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1795 BUS_DMASYNC_PREWRITE); 1796 malo_send_cmd(sc, sc->sc_cmd_dmaaddr); 1797 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1798 BUS_DMASYNC_POSTWRITE); 1799 delay(100); 1800 1801 DPRINTF(1, "%s: loading firmware\n", device_xname(sc->sc_dev)); 1802 1803 /* wait until firmware has been loaded */ 1804 for (i = 0; i < 200; i++) { 1805 malo_ctl_write4(sc, 0x0c10, 0x5a); 1806 delay(500); 1807 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE | 1808 BUS_SPACE_BARRIER_READ); 1809 if (malo_ctl_read4(sc, 0x0c14) == 0xf0f1f2f4) 1810 break; 1811 } 1812 if (i == 200) { 1813 aprint_error_dev(sc->sc_dev, "timeout at firmware load!\n"); 1814 return (ETIMEDOUT); 1815 } 1816 1817 DPRINTF(1, "%s: firmware loaded\n", device_xname(sc->sc_dev)); 1818 1819 return (0); 1820 } 1821 1822 static int 1823 malo_set_slot(struct malo_softc *sc) 1824 { 1825 struct ieee80211com *ic = &sc->sc_ic; 1826 1827 if (ic->ic_flags & IEEE80211_F_SHSLOT) { 1828 /* set short slot */ 1829 if (malo_cmd_set_slot(sc, 1)) { 1830 aprint_error_dev(sc->sc_dev, "setting short slot failed\n"); 1831 return (ENXIO); 1832 } 1833 } else { 1834 /* set long slot */ 1835 if (malo_cmd_set_slot(sc, 0)) { 1836 aprint_error_dev(sc->sc_dev, "setting long slot failed\n"); 1837 return (ENXIO); 1838 } 1839 } 1840 1841 return (0); 1842 } 1843 1844 static void 1845 malo_update_slot(struct ifnet* ifp) 1846 { 1847 struct malo_softc *sc = ifp->if_softc; 1848 struct ieee80211com *ic = &sc->sc_ic; 1849 1850 malo_set_slot(sc); 1851 1852 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1853 /* TODO */ 1854 } 1855 } 1856 1857 #ifdef MALO_DEBUG 1858 static void 1859 malo_hexdump(void *buf, int len) 1860 { 1861 u_char b[16]; 1862 int i, j, l; 1863 1864 for (i = 0; i < len; i += l) { 1865 printf("%4i:", i); 1866 l = uimin(sizeof(b), len - i); 1867 memcpy(b, (char*)buf + i, l); 1868 1869 for (j = 0; j < sizeof(b); j++) { 1870 if (j % 2 == 0) 1871 printf(" "); 1872 if (j % 8 == 0) 1873 printf(" "); 1874 if (j < l) 1875 printf("%02x", (int)b[j]); 1876 else 1877 printf(" "); 1878 } 1879 printf(" |"); 1880 for (j = 0; j < l; j++) { 1881 if (b[j] >= 0x20 && b[j] <= 0x7e) 1882 printf("%c", b[j]); 1883 else 1884 printf("."); 1885 } 1886 printf("|\n"); 1887 } 1888 } 1889 #endif 1890 1891 static const char * 1892 malo_cmd_string(uint16_t cmd) 1893 { 1894 int i; 1895 static char cmd_buf[16]; 1896 static const struct { 1897 uint16_t cmd_code; 1898 const char *cmd_string; 1899 } cmds[] = { 1900 { MALO_CMD_GET_HW_SPEC, "GetHwSpecifications" }, 1901 { MALO_CMD_SET_RADIO, "SetRadio" }, 1902 { MALO_CMD_SET_AID, "SetAid" }, 1903 { MALO_CMD_SET_TXPOWER, "SetTxPower" }, 1904 { MALO_CMD_SET_ANTENNA, "SetAntenna" }, 1905 { MALO_CMD_SET_PRESCAN, "SetPrescan" }, 1906 { MALO_CMD_SET_POSTSCAN, "SetPostscan" }, 1907 { MALO_CMD_SET_RATE, "SetRate" }, 1908 { MALO_CMD_SET_CHANNEL, "SetChannel" }, 1909 { MALO_CMD_SET_RTS, "SetRTS" }, 1910 { MALO_CMD_SET_SLOT, "SetSlot" }, 1911 }; 1912 1913 for (i = 0; i < sizeof(cmds) / sizeof(cmds[0]); i++) 1914 if ((le16toh(cmd) & 0x7fff) == cmds[i].cmd_code) 1915 return (cmds[i].cmd_string); 1916 1917 snprintf(cmd_buf, sizeof(cmd_buf), "unknown %#x", cmd); 1918 return (cmd_buf); 1919 } 1920 1921 static const char * 1922 malo_cmd_string_result(uint16_t result) 1923 { 1924 int i; 1925 static const struct { 1926 uint16_t result_code; 1927 const char *result_string; 1928 } results[] = { 1929 { MALO_CMD_RESULT_OK, "OK" }, 1930 { MALO_CMD_RESULT_ERROR, "general error" }, 1931 { MALO_CMD_RESULT_NOSUPPORT, "not supported" }, 1932 { MALO_CMD_RESULT_PENDING, "pending" }, 1933 { MALO_CMD_RESULT_BUSY, "ignored" }, 1934 { MALO_CMD_RESULT_PARTIALDATA, "incomplete" }, 1935 }; 1936 1937 for (i = 0; i < sizeof(results) / sizeof(results[0]); i++) 1938 if (le16toh(result) == results[i].result_code) 1939 return (results[i].result_string); 1940 1941 return ("unknown"); 1942 } 1943 1944 static int 1945 malo_cmd_get_spec(struct malo_softc *sc) 1946 { 1947 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 1948 struct malo_hw_spec *spec; 1949 1950 hdr->cmd = htole16(MALO_CMD_GET_HW_SPEC); 1951 hdr->size = htole16(sizeof(*hdr) + sizeof(*spec)); 1952 hdr->seqnum = htole16(42); /* the one and only */ 1953 hdr->result = 0; 1954 spec = (struct malo_hw_spec *)(hdr + 1); 1955 1956 memset(spec, 0, sizeof(*spec)); 1957 memset(spec->PermanentAddress, 0xff, ETHER_ADDR_LEN); 1958 spec->CookiePtr = htole32(sc->sc_cookie_dmaaddr); 1959 1960 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1961 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1962 1963 if (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr) != 0) 1964 return (ETIMEDOUT); 1965 1966 /* get the data from the buffer */ 1967 DPRINTF(1, "%s: get_hw_spec: V%x R%x, #WCB %d, #Mcast %d, Regcode %d, " 1968 "#Ant %d\n", device_xname(sc->sc_dev), htole16(spec->HwVersion), 1969 htole32(spec->FWReleaseNumber), htole16(spec->NumOfWCB), 1970 htole16(spec->NumOfMCastAdr), htole16(spec->RegionCode), 1971 htole16(spec->NumberOfAntenna)); 1972 1973 /* tell the DMA engine where our rings are */ 1974 malo_mem_write4(sc, le32toh(spec->RxPdRdPtr) & 0xffff, 1975 sc->sc_rxring.physaddr); 1976 malo_mem_write4(sc, le32toh(spec->RxPdWrPtr) & 0xffff, 1977 sc->sc_rxring.physaddr); 1978 malo_mem_write4(sc, le32toh(spec->WcbBase0) & 0xffff, 1979 sc->sc_txring.physaddr); 1980 1981 /* save DMA RX pointers for later use */ 1982 sc->sc_RxPdRdPtr = le32toh(spec->RxPdRdPtr) & 0xffff; 1983 sc->sc_RxPdWrPtr = le32toh(spec->RxPdWrPtr) & 0xffff; 1984 1985 return (0); 1986 } 1987 1988 static int 1989 malo_cmd_set_prescan(struct malo_softc *sc) 1990 { 1991 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 1992 1993 hdr->cmd = htole16(MALO_CMD_SET_PRESCAN); 1994 hdr->size = htole16(sizeof(*hdr)); 1995 hdr->seqnum = 1; 1996 hdr->result = 0; 1997 1998 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1999 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2000 2001 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2002 } 2003 2004 static int 2005 malo_cmd_set_postscan(struct malo_softc *sc, uint8_t *macaddr, uint8_t ibsson) 2006 { 2007 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2008 struct malo_cmd_postscan *body; 2009 2010 hdr->cmd = htole16(MALO_CMD_SET_POSTSCAN); 2011 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2012 hdr->seqnum = 1; 2013 hdr->result = 0; 2014 body = (struct malo_cmd_postscan *)(hdr + 1); 2015 2016 memset(body, 0, sizeof(*body)); 2017 memcpy(&body->bssid, macaddr, ETHER_ADDR_LEN); 2018 body->isibss = htole32(ibsson); 2019 2020 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2021 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2022 2023 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2024 } 2025 2026 static int 2027 malo_cmd_set_channel(struct malo_softc *sc, struct ieee80211_channel* chan) 2028 { 2029 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2030 struct ieee80211com *ic = &sc->sc_ic; 2031 struct malo_cmd_channel *body; 2032 uint8_t channel; 2033 2034 channel = ieee80211_chan2ieee(ic, chan); 2035 2036 hdr->cmd = htole16(MALO_CMD_SET_CHANNEL); 2037 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2038 hdr->seqnum = 1; 2039 hdr->result = 0; 2040 body = (struct malo_cmd_channel *)(hdr + 1); 2041 2042 memset(body, 0, sizeof(*body)); 2043 body->action = htole16(1); 2044 body->channel = channel; 2045 2046 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2047 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2048 2049 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2050 } 2051 2052 static int 2053 malo_cmd_set_antenna(struct malo_softc *sc, uint16_t antenna) 2054 { 2055 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2056 struct malo_cmd_antenna *body; 2057 2058 hdr->cmd = htole16(MALO_CMD_SET_ANTENNA); 2059 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2060 hdr->seqnum = 1; 2061 hdr->result = 0; 2062 body = (struct malo_cmd_antenna *)(hdr + 1); 2063 2064 memset(body, 0, sizeof(*body)); 2065 body->action = htole16(antenna); 2066 if (antenna == 1) 2067 body->mode = htole16(0xffff); 2068 else 2069 body->mode = htole16(2); 2070 2071 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2072 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2073 2074 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2075 } 2076 2077 static int 2078 malo_cmd_set_radio(struct malo_softc *sc, uint16_t enable, 2079 uint16_t preamble_mode) 2080 { 2081 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2082 struct malo_cmd_radio *body; 2083 2084 hdr->cmd = htole16(MALO_CMD_SET_RADIO); 2085 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2086 hdr->seqnum = 1; 2087 hdr->result = 0; 2088 body = (struct malo_cmd_radio *)(hdr + 1); 2089 2090 memset(body, 0, sizeof(*body)); 2091 body->action = htole16(1); 2092 body->preamble_mode = htole16(preamble_mode); 2093 body->enable = htole16(enable); 2094 2095 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2096 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2097 2098 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2099 } 2100 2101 static int 2102 malo_cmd_set_aid(struct malo_softc *sc, uint8_t *bssid, uint16_t associd) 2103 { 2104 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2105 struct malo_cmd_aid *body; 2106 2107 hdr->cmd = htole16(MALO_CMD_SET_AID); 2108 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2109 hdr->seqnum = 1; 2110 hdr->result = 0; 2111 body = (struct malo_cmd_aid *)(hdr + 1); 2112 2113 memset(body, 0, sizeof(*body)); 2114 body->associd = htole16(associd); 2115 memcpy(&body->macaddr[0], bssid, IEEE80211_ADDR_LEN); 2116 2117 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2118 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2119 2120 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2121 } 2122 2123 static int 2124 malo_cmd_set_txpower(struct malo_softc *sc, unsigned int powerlevel) 2125 { 2126 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2127 struct malo_cmd_txpower *body; 2128 2129 hdr->cmd = htole16(MALO_CMD_SET_TXPOWER); 2130 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2131 hdr->seqnum = 1; 2132 hdr->result = 0; 2133 body = (struct malo_cmd_txpower *)(hdr + 1); 2134 2135 memset(body, 0, sizeof(*body)); 2136 body->action = htole16(1); 2137 if (powerlevel < 30) 2138 body->supportpowerlvl = htole16(5); /* LOW */ 2139 else if (powerlevel < 60) 2140 body->supportpowerlvl = htole16(10); /* MEDIUM */ 2141 else 2142 body->supportpowerlvl = htole16(15); /* HIGH */ 2143 2144 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2145 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2146 2147 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2148 } 2149 2150 static int 2151 malo_cmd_set_rts(struct malo_softc *sc, uint32_t threshold) 2152 { 2153 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2154 struct malo_cmd_rts *body; 2155 2156 hdr->cmd = htole16(MALO_CMD_SET_RTS); 2157 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2158 hdr->seqnum = 1; 2159 hdr->result = 0; 2160 body = (struct malo_cmd_rts *)(hdr + 1); 2161 2162 memset(body, 0, sizeof(*body)); 2163 body->action = htole16(1); 2164 body->threshold = htole32(threshold); 2165 2166 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2168 2169 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2170 } 2171 2172 static int 2173 malo_cmd_set_slot(struct malo_softc *sc, uint8_t slot) 2174 { 2175 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2176 struct malo_cmd_slot *body; 2177 2178 hdr->cmd = htole16(MALO_CMD_SET_SLOT); 2179 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2180 hdr->seqnum = 1; 2181 hdr->result = 0; 2182 body = (struct malo_cmd_slot *)(hdr + 1); 2183 2184 memset(body, 0, sizeof(*body)); 2185 body->action = htole16(1); 2186 body->slot = slot; 2187 2188 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2189 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2190 2191 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2192 } 2193 2194 static int 2195 malo_cmd_set_rate(struct malo_softc *sc, uint8_t rate) 2196 { 2197 struct ieee80211com *ic = &sc->sc_ic; 2198 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2199 struct malo_cmd_rate *body; 2200 int i; 2201 2202 hdr->cmd = htole16(MALO_CMD_SET_RATE); 2203 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2204 hdr->seqnum = 1; 2205 hdr->result = 0; 2206 body = (struct malo_cmd_rate *)(hdr + 1); 2207 2208 memset(body, 0,sizeof(*body)); 2209 2210 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2211 /* TODO */ 2212 } else 2213 { 2214 body->aprates[0] = 2; 2215 body->aprates[1] = 4; 2216 body->aprates[2] = 11; 2217 body->aprates[3] = 22; 2218 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2219 body->aprates[4] = 0; 2220 body->aprates[5] = 12; 2221 body->aprates[6] = 18; 2222 body->aprates[7] = 24; 2223 body->aprates[8] = 36; 2224 body->aprates[9] = 48; 2225 body->aprates[10] = 72; 2226 body->aprates[11] = 96; 2227 body->aprates[12] = 108; 2228 } 2229 } 2230 2231 if (rate != 0) { 2232 /* fixed rate */ 2233 for (i = 0; i < 13; i++) { 2234 if (body->aprates[i] == rate) { 2235 body->rateindex = i; 2236 body->dataratetype = 1; 2237 break; 2238 } 2239 } 2240 } 2241 2242 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2243 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2244 2245 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2246 } 2247 2248 static void 2249 malo_cmd_response(struct malo_softc *sc) 2250 { 2251 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2252 2253 if (le16toh(hdr->result) != MALO_CMD_RESULT_OK) { 2254 aprint_error_dev(sc->sc_dev, "firmware cmd %s failed with %s\n", 2255 malo_cmd_string(hdr->cmd), 2256 malo_cmd_string_result(hdr->result)); 2257 } 2258 2259 #ifdef MALO_DEBUG 2260 aprint_error_dev(sc->sc_dev, "cmd answer for %s=%s\n", 2261 malo_cmd_string(hdr->cmd), 2262 malo_cmd_string_result(hdr->result)); 2263 2264 if (malo_d > 2) 2265 malo_hexdump(hdr, le16toh(hdr->size)); 2266 #endif 2267 } 2268
Indexes created Thu Oct 23 22:10:10 GMT 2025