malo.c revision 1.2
1 /* $NetBSD: malo.c,v 1.2 2012/07/30 20:30:41 degroote Exp $ */ 2 /* $OpenBSD: malo.c,v 1.92 2010/08/27 17:08:00 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Claudio Jeker <claudio (at) openbsd.org> 6 * Copyright (c) 2006 Marcus Glocker <mglocker (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: malo.c,v 1.2 2012/07/30 20:30:41 degroote Exp $"); 23 24 #include <sys/param.h> 25 #include <sys/types.h> 26 27 #include <sys/device.h> 28 #include <sys/kernel.h> 29 #include <sys/malloc.h> 30 #include <sys/mbuf.h> 31 #include <sys/proc.h> 32 #include <sys/socket.h> 33 #include <sys/sockio.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <machine/endian.h> 38 #include <machine/intr.h> 39 40 #include <net/if.h> 41 #include <net/if_media.h> 42 #include <net/if_ether.h> 43 44 #include <net/bpf.h> 45 46 #include <netinet/in.h> 47 #include <netinet/in_systm.h> 48 49 #include <net80211/ieee80211_var.h> 50 #include <net80211/ieee80211_radiotap.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/ic/malovar.h> 55 #include <dev/ic/maloreg.h> 56 57 #ifdef MALO_DEBUG 58 int malo_d = 2; 59 #define DPRINTF(l, x...) do { if ((l) <= malo_d) printf(x); } while (0) 60 #else 61 #define DPRINTF(l, x...) 62 #endif 63 64 /* internal structures and defines */ 65 struct malo_node { 66 struct ieee80211_node ni; 67 }; 68 69 struct malo_rx_data { 70 bus_dmamap_t map; 71 struct mbuf *m; 72 }; 73 74 struct malo_tx_data { 75 bus_dmamap_t map; 76 struct mbuf *m; 77 uint32_t softstat; 78 struct ieee80211_node *ni; 79 }; 80 81 /* RX descriptor used by HW */ 82 struct malo_rx_desc { 83 uint8_t rxctrl; 84 uint8_t rssi; 85 uint8_t status; 86 uint8_t channel; 87 uint16_t len; 88 uint8_t reserved1; /* actually unused */ 89 uint8_t datarate; 90 uint32_t physdata; /* DMA address of data */ 91 uint32_t physnext; /* DMA address of next control block */ 92 uint16_t qosctrl; 93 uint16_t reserved2; 94 } __packed; 95 96 /* TX descriptor used by HW */ 97 struct malo_tx_desc { 98 uint32_t status; 99 #define MALO_TXD_STATUS_IDLE 0x00000000 100 #define MALO_TXD_STATUS_USED 0x00000001 101 #define MALO_TXD_STATUS_OK 0x00000001 102 #define MALO_TXD_STATUS_OK_RETRY 0x00000002 103 #define MALO_TXD_STATUS_OK_MORE_RETRY 0x00000004 104 #define MALO_TXD_STATUS_MULTICAST_TX 0x00000008 105 #define MALO_TXD_STATUS_BROADCAST_TX 0x00000010 106 #define MALO_TXD_STATUS_FAILED_LINK_ERROR 0x00000020 107 #define MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040 108 #define MALO_TXD_STATUS_FAILED_XRETRY MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 109 #define MALO_TXD_STATUS_FAILED_AGING 0x00000080 110 #define MALO_TXD_STATUS_FW_OWNED 0x80000000 111 uint8_t datarate; 112 uint8_t txpriority; 113 uint16_t qosctrl; 114 uint32_t physdata; /* DMA address of data */ 115 uint16_t len; 116 uint8_t destaddr[6]; 117 uint32_t physnext; /* DMA address of next control block */ 118 uint32_t reserved1; /* SAP packet info ??? */ 119 uint32_t reserved2; 120 } __packed; 121 122 #define MALO_RX_RING_COUNT 256 123 #define MALO_TX_RING_COUNT 256 124 #define MALO_MAX_SCATTER 8 /* XXX unknown, wild guess */ 125 #define MALO_CMD_TIMEOUT 50 /* MALO_CMD_TIMEOUT * 100us */ 126 127 /* 128 * Firmware commands 129 */ 130 #define MALO_CMD_GET_HW_SPEC 0x0003 131 #define MALO_CMD_SET_RADIO 0x001c 132 #define MALO_CMD_SET_AID 0x010d 133 #define MALO_CMD_SET_TXPOWER 0x001e 134 #define MALO_CMD_SET_ANTENNA 0x0020 135 #define MALO_CMD_SET_PRESCAN 0x0107 136 #define MALO_CMD_SET_POSTSCAN 0x0108 137 #define MALO_CMD_SET_RATE 0x0110 138 #define MALO_CMD_SET_CHANNEL 0x010a 139 #define MALO_CMD_SET_RTS 0x0113 140 #define MALO_CMD_SET_SLOT 0x0114 141 #define MALO_CMD_RESPONSE 0x8000 142 143 #define MALO_CMD_RESULT_OK 0x0000 /* everything is fine */ 144 #define MALO_CMD_RESULT_ERROR 0x0001 /* general error */ 145 #define MALO_CMD_RESULT_NOSUPPORT 0x0002 /* command not valid */ 146 #define MALO_CMD_RESULT_PENDING 0x0003 /* will be processed */ 147 #define MALO_CMD_RESULT_BUSY 0x0004 /* command ignored */ 148 #define MALO_CMD_RESULT_PARTIALDATA 0x0005 /* buffer too small */ 149 150 struct malo_cmdheader { 151 uint16_t cmd; 152 uint16_t size; /* size of the command, incl. header */ 153 uint16_t seqnum; /* seems not to matter that much */ 154 uint16_t result; /* set to 0 on request */ 155 /* following the data payload, up to 256 bytes */ 156 }; 157 158 struct malo_hw_spec { 159 uint16_t HwVersion; 160 uint16_t NumOfWCB; 161 uint16_t NumOfMCastAdr; 162 uint8_t PermanentAddress[6]; 163 uint16_t RegionCode; 164 uint16_t NumberOfAntenna; 165 uint32_t FWReleaseNumber; 166 uint32_t WcbBase0; 167 uint32_t RxPdWrPtr; 168 uint32_t RxPdRdPtr; 169 uint32_t CookiePtr; 170 uint32_t WcbBase1; 171 uint32_t WcbBase2; 172 uint32_t WcbBase3; 173 } __packed; 174 175 struct malo_cmd_radio { 176 uint16_t action; 177 uint16_t preamble_mode; 178 uint16_t enable; 179 } __packed; 180 181 struct malo_cmd_aid { 182 uint16_t associd; 183 uint8_t macaddr[6]; 184 uint32_t gprotection; 185 uint8_t aprates[14]; 186 } __packed; 187 188 struct malo_cmd_txpower { 189 uint16_t action; 190 uint16_t supportpowerlvl; 191 uint16_t currentpowerlvl; 192 uint16_t reserved; 193 uint16_t powerlvllist[8]; 194 } __packed; 195 196 struct malo_cmd_antenna { 197 uint16_t action; 198 uint16_t mode; 199 } __packed; 200 201 struct malo_cmd_postscan { 202 uint32_t isibss; 203 uint8_t bssid[6]; 204 } __packed; 205 206 struct malo_cmd_channel { 207 uint16_t action; 208 uint8_t channel; 209 } __packed; 210 211 struct malo_cmd_rate { 212 uint8_t dataratetype; 213 uint8_t rateindex; 214 uint8_t aprates[14]; 215 } __packed; 216 217 struct malo_cmd_rts { 218 uint16_t action; 219 uint32_t threshold; 220 } __packed; 221 222 struct malo_cmd_slot { 223 uint16_t action; 224 uint8_t slot; 225 } __packed; 226 227 #define malo_mem_write4(sc, off, x) \ 228 bus_space_write_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off), (x)) 229 #define malo_mem_write2(sc, off, x) \ 230 bus_space_write_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off), (x)) 231 #define malo_mem_write1(sc, off, x) \ 232 bus_space_write_1((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off), (x)) 233 234 #define malo_mem_read4(sc, off) \ 235 bus_space_read_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off)) 236 #define malo_mem_read1(sc, off) \ 237 bus_space_read_1((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, (off)) 238 239 #define malo_ctl_write4(sc, off, x) \ 240 bus_space_write_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (x)) 241 #define malo_ctl_read4(sc, off) \ 242 bus_space_read_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off)) 243 #define malo_ctl_read1(sc, off) \ 244 bus_space_read_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off)) 245 246 #define malo_ctl_barrier(sc, t) \ 247 bus_space_barrier((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, 0x0c00, 0xff, (t)) 248 249 static int malo_init(struct ifnet *); 250 static void malo_stop(struct ifnet *, int disable); 251 static int malo_alloc_cmd(struct malo_softc *sc); 252 static void malo_free_cmd(struct malo_softc *sc); 253 static void malo_send_cmd(struct malo_softc *sc, bus_addr_t addr); 254 static int malo_send_cmd_dma(struct malo_softc *sc, bus_addr_t addr); 255 static int malo_alloc_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring, 256 int count); 257 static void malo_reset_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring); 258 static void malo_free_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring); 259 static int malo_alloc_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring, 260 int count); 261 static void malo_reset_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring); 262 static void malo_free_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring); 263 static int malo_ioctl(struct ifnet *ifp, u_long cmd, void* data); 264 static void malo_start(struct ifnet *ifp); 265 static void malo_watchdog(struct ifnet *ifp); 266 static int malo_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 267 int arg); 268 static void malo_newassoc(struct ieee80211_node *ni, int isnew); 269 static struct ieee80211_node * 270 malo_node_alloc(struct ieee80211_node_table *nt); 271 static int malo_media_change(struct ifnet *ifp); 272 static void malo_media_status(struct ifnet *ifp, struct ifmediareq *imr); 273 static int malo_chip2rate(int chip_rate); 274 static int malo_fix2rate(int fix_rate); 275 static void malo_next_scan(void *arg); 276 static void malo_tx_intr(struct malo_softc *sc); 277 static int malo_tx_data(struct malo_softc *sc, struct mbuf *m0, 278 struct ieee80211_node *ni); 279 static void malo_tx_setup_desc(struct malo_softc *sc, struct malo_tx_desc *desc, 280 int len, int rate, const bus_dma_segment_t *segs, int nsegs); 281 static void malo_rx_intr(struct malo_softc *sc); 282 static int malo_load_bootimg(struct malo_softc *sc); 283 static int malo_load_firmware(struct malo_softc *sc); 284 285 static int malo_set_slot(struct malo_softc *sc); 286 static void malo_update_slot(struct ifnet* ifp); 287 #ifdef MALO_DEBUG 288 static void malo_hexdump(void *buf, int len); 289 #endif 290 static const char *malo_cmd_string(uint16_t cmd); 291 static const char *malo_cmd_string_result(uint16_t result); 292 static int malo_cmd_get_spec(struct malo_softc *sc); 293 static int malo_cmd_set_prescan(struct malo_softc *sc); 294 static int malo_cmd_set_postscan(struct malo_softc *sc, uint8_t *macaddr, 295 uint8_t ibsson); 296 static int malo_cmd_set_channel(struct malo_softc *sc, struct ieee80211_channel *chan); 297 static int malo_cmd_set_antenna(struct malo_softc *sc, uint16_t antenna_type); 298 static int malo_cmd_set_radio(struct malo_softc *sc, uint16_t mode, 299 uint16_t preamble); 300 static int malo_cmd_set_aid(struct malo_softc *sc, uint8_t *bssid, 301 uint16_t associd); 302 static int malo_cmd_set_txpower(struct malo_softc *sc, unsigned int powerlevel); 303 static int malo_cmd_set_rts(struct malo_softc *sc, uint32_t threshold); 304 static int malo_cmd_set_slot(struct malo_softc *sc, uint8_t slot); 305 static int malo_cmd_set_rate(struct malo_softc *sc, uint8_t rate); 306 static void malo_cmd_response(struct malo_softc *sc); 307 308 int 309 malo_intr(void *arg) 310 { 311 struct malo_softc *sc = arg; 312 uint32_t status; 313 314 status = malo_ctl_read4(sc, MALO_REG_A2H_INTERRUPT_CAUSE); 315 if (status == 0xffffffff || status == 0) 316 /* not for us */ 317 return (0); 318 319 if (status & MALO_A2HRIC_BIT_TX_DONE) 320 malo_tx_intr(sc); 321 if (status & MALO_A2HRIC_BIT_RX_RDY) 322 malo_rx_intr(sc); 323 if (status & MALO_A2HRIC_BIT_OPC_DONE) { 324 /* XXX cmd done interrupt handling doesn't work yet */ 325 DPRINTF(1, "%s: got cmd done interrupt\n", device_xname(sc->sc_dev)); 326 //malo_cmd_response(sc); 327 } 328 329 if (status & ~0x7) { 330 DPRINTF(1, "%s: unknown interrupt %x\n", 331 device_xname(sc->sc_dev), status); 332 } 333 334 /* just ack the interrupt */ 335 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_CAUSE, 0); 336 337 return (1); 338 } 339 340 int 341 malo_attach(struct malo_softc *sc) 342 { 343 struct ieee80211com *ic = &sc->sc_ic; 344 struct ifnet *ifp = &sc->sc_if; 345 int i; 346 347 /* initialize channel scanning timer */ 348 callout_init(&sc->sc_scan_to, 0); 349 callout_setfunc(&sc->sc_scan_to, malo_next_scan, sc); 350 351 /* allocate DMA structures */ 352 malo_alloc_cmd(sc); 353 malo_alloc_rx_ring(sc, &sc->sc_rxring, MALO_RX_RING_COUNT); 354 malo_alloc_tx_ring(sc, &sc->sc_txring, MALO_TX_RING_COUNT); 355 356 /* setup interface */ 357 ifp->if_softc = sc; 358 ifp->if_init = malo_init; 359 ifp->if_stop = malo_stop; 360 ifp->if_ioctl = malo_ioctl; 361 ifp->if_start = malo_start; 362 ifp->if_watchdog = malo_watchdog; 363 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 364 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 365 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 366 IFQ_SET_READY(&ifp->if_snd); 367 368 /* set supported rates */ 369 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 370 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 371 sc->sc_last_txrate = -1; 372 373 /* set channels */ 374 for (i = 1; i <= 14; i++) { 375 ic->ic_channels[i].ic_freq = 376 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 377 ic->ic_channels[i].ic_flags = 378 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 379 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 380 } 381 382 /* OpenBSD supports IEEE80211_C_RSN too */ 383 /* set the rest */ 384 ic->ic_ifp = ifp; 385 ic->ic_caps = 386 IEEE80211_C_IBSS | 387 IEEE80211_C_MONITOR | 388 IEEE80211_C_SHPREAMBLE | 389 IEEE80211_C_SHSLOT | 390 IEEE80211_C_WEP | 391 IEEE80211_C_WPA; 392 ic->ic_opmode = IEEE80211_M_STA; 393 ic->ic_state = IEEE80211_S_INIT; 394 for (i = 0; i < 6; i++) 395 ic->ic_myaddr[i] = malo_ctl_read1(sc, 0xa528 + i); 396 397 /* show our mac address */ 398 aprint_normal(", address %s\n", ether_sprintf(ic->ic_myaddr)); 399 400 /* attach interface */ 401 if_attach(ifp); 402 ieee80211_ifattach(ic); 403 404 /* post attach vector functions */ 405 sc->sc_newstate = ic->ic_newstate; 406 ic->ic_newstate = malo_newstate; 407 ic->ic_newassoc = malo_newassoc; 408 ic->ic_node_alloc = malo_node_alloc; 409 ic->ic_updateslot = malo_update_slot; 410 411 ieee80211_media_init(ic, malo_media_change, malo_media_status); 412 413 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 414 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 415 &sc->sc_drvbpf); 416 417 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 418 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 419 sc->sc_rxtap.wr_ihdr.it_present = htole32(MALO_RX_RADIOTAP_PRESENT); 420 421 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 422 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 423 sc->sc_txtap.wt_ihdr.it_present = htole32(MALO_TX_RADIOTAP_PRESENT); 424 425 ieee80211_announce(ic); 426 427 return (0); 428 } 429 430 int 431 malo_detach(void *arg) 432 { 433 struct malo_softc *sc = arg; 434 struct ieee80211com *ic = &sc->sc_ic; 435 struct ifnet *ifp = &sc->sc_if; 436 437 /* remove channel scanning timer */ 438 callout_stop(&sc->sc_scan_to); 439 440 malo_stop(ifp, 1); 441 ieee80211_ifdetach(ic); 442 if_detach(ifp); 443 malo_free_cmd(sc); 444 malo_free_rx_ring(sc, &sc->sc_rxring); 445 malo_free_tx_ring(sc, &sc->sc_txring); 446 447 return (0); 448 } 449 450 static int 451 malo_alloc_cmd(struct malo_softc *sc) 452 { 453 int error, nsegs; 454 455 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, 456 PAGE_SIZE, 0, BUS_DMA_ALLOCNOW, &sc->sc_cmd_dmam); 457 if (error != 0) { 458 aprint_error_dev(sc->sc_dev, "can not create DMA tag\n"); 459 return (-1); 460 } 461 462 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 463 0, &sc->sc_cmd_dmas, 1, &nsegs, BUS_DMA_WAITOK); 464 if (error != 0) { 465 aprint_error_dev(sc->sc_dev, "error alloc dma memory\n"); 466 return (-1); 467 } 468 469 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_dmas, nsegs, 470 PAGE_SIZE, (void **)&sc->sc_cmd_mem, BUS_DMA_WAITOK); 471 if (error != 0) { 472 aprint_error_dev(sc->sc_dev, "error map dma memory\n"); 473 return (-1); 474 } 475 476 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_dmam, 477 sc->sc_cmd_mem, PAGE_SIZE, NULL, BUS_DMA_NOWAIT); 478 if (error != 0) { 479 aprint_error_dev(sc->sc_dev, "error load dma memory\n"); 480 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_dmas, nsegs); 481 return (-1); 482 } 483 484 sc->sc_cookie = sc->sc_cmd_mem; 485 *sc->sc_cookie = htole32(0xaa55aa55); 486 sc->sc_cmd_mem = ((char*)sc->sc_cmd_mem) + sizeof(uint32_t); 487 sc->sc_cookie_dmaaddr = sc->sc_cmd_dmam->dm_segs[0].ds_addr; 488 sc->sc_cmd_dmaaddr = sc->sc_cmd_dmam->dm_segs[0].ds_addr + 489 sizeof(uint32_t); 490 491 return (0); 492 } 493 494 static void 495 malo_free_cmd(struct malo_softc *sc) 496 { 497 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 498 BUS_DMASYNC_POSTWRITE); 499 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_dmam); 500 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cookie, PAGE_SIZE); 501 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_dmas, 1); 502 } 503 504 static void 505 malo_send_cmd(struct malo_softc *sc, bus_addr_t addr) 506 { 507 malo_ctl_write4(sc, MALO_REG_GEN_PTR, (uint32_t)addr); 508 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 509 malo_ctl_write4(sc, MALO_REG_H2A_INTERRUPT_EVENTS, 2); /* CPU_TRANSFER_CMD */ 510 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 511 } 512 513 static int 514 malo_send_cmd_dma(struct malo_softc *sc, bus_addr_t addr) 515 { 516 int i; 517 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 518 519 malo_send_cmd(sc, addr); 520 521 for (i = 0; i < MALO_CMD_TIMEOUT; i++) { 522 delay(100); 523 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 524 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 525 if (hdr->cmd & htole16(0x8000)) 526 break; 527 } 528 if (i == MALO_CMD_TIMEOUT) { 529 aprint_error_dev(sc->sc_dev, "timeout while waiting for cmd response!\n"); 530 return (ETIMEDOUT); 531 } 532 533 malo_cmd_response(sc); 534 535 return (0); 536 } 537 538 static int 539 malo_alloc_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring, int count) 540 { 541 struct malo_rx_desc *desc; 542 struct malo_rx_data *data; 543 int i, nsegs, error; 544 545 ring->count = count; 546 ring->cur = ring->next = 0; 547 548 error = bus_dmamap_create(sc->sc_dmat, 549 count * sizeof(struct malo_rx_desc), 1, 550 count * sizeof(struct malo_rx_desc), 0, 551 BUS_DMA_NOWAIT, &ring->map); 552 if (error != 0) { 553 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 554 goto fail; 555 } 556 557 error = bus_dmamem_alloc(sc->sc_dmat, 558 count * sizeof(struct malo_rx_desc), 559 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 560 561 if (error != 0) { 562 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 563 goto fail; 564 } 565 566 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 567 count * sizeof(struct malo_rx_desc), (void **)&ring->desc, 568 BUS_DMA_NOWAIT); 569 if (error != 0) { 570 aprint_error_dev(sc->sc_dev, "can't map desc DMA memory\n"); 571 goto fail; 572 } 573 574 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 575 count * sizeof(struct malo_rx_desc), NULL, BUS_DMA_NOWAIT); 576 if (error != 0) { 577 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 578 goto fail; 579 } 580 581 ring->physaddr = ring->map->dm_segs->ds_addr; 582 583 ring->data = malloc(count * sizeof (struct malo_rx_data), M_DEVBUF, 584 M_NOWAIT); 585 if (ring->data == NULL) { 586 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 587 error = ENOMEM; 588 goto fail; 589 } 590 591 /* 592 * Pre-allocate Rx buffers and populate Rx ring. 593 */ 594 memset(ring->data, 0, count * sizeof (struct malo_rx_data)); 595 for (i = 0; i < count; i++) { 596 desc = &ring->desc[i]; 597 data = &ring->data[i]; 598 599 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 600 0, BUS_DMA_NOWAIT, &data->map); 601 if (error != 0) { 602 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 603 goto fail; 604 } 605 606 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 607 if (data->m == NULL) { 608 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 609 error = ENOMEM; 610 goto fail; 611 } 612 613 MCLGET(data->m, M_DONTWAIT); 614 if (!(data->m->m_flags & M_EXT)) { 615 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 616 error = ENOMEM; 617 goto fail; 618 } 619 620 error = bus_dmamap_load(sc->sc_dmat, data->map, 621 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 622 if (error != 0) { 623 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map"); 624 goto fail; 625 } 626 627 desc->status = htole16(1); 628 desc->physdata = htole32(data->map->dm_segs->ds_addr); 629 desc->physnext = htole32(ring->physaddr + 630 (i + 1) % count * sizeof(struct malo_rx_desc)); 631 } 632 633 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 634 BUS_DMASYNC_PREWRITE); 635 636 return (0); 637 638 fail: malo_free_rx_ring(sc, ring); 639 return (error); 640 } 641 642 static void 643 malo_reset_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring) 644 { 645 int i; 646 647 for (i = 0; i < ring->count; i++) 648 ring->desc[i].status = 0; 649 650 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 651 BUS_DMASYNC_PREWRITE); 652 653 ring->cur = ring->next = 0; 654 } 655 656 static void 657 malo_free_rx_ring(struct malo_softc *sc, struct malo_rx_ring *ring) 658 { 659 struct malo_rx_data *data; 660 int i; 661 662 if (ring->desc != NULL) { 663 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 664 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 665 bus_dmamap_unload(sc->sc_dmat, ring->map); 666 bus_dmamem_unmap(sc->sc_dmat, ring->desc, 667 ring->count * sizeof(struct malo_rx_desc)); 668 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 669 } 670 671 if (ring->data != NULL) { 672 for (i = 0; i < ring->count; i++) { 673 data = &ring->data[i]; 674 675 if (data->m != NULL) { 676 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 677 data->map->dm_mapsize, 678 BUS_DMASYNC_POSTREAD); 679 bus_dmamap_unload(sc->sc_dmat, data->map); 680 m_freem(data->m); 681 } 682 683 if (data->map != NULL) 684 bus_dmamap_destroy(sc->sc_dmat, data->map); 685 } 686 free(ring->data, M_DEVBUF); 687 } 688 } 689 690 static int 691 malo_alloc_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring, 692 int count) 693 { 694 int i, nsegs, error; 695 696 ring->count = count; 697 ring->queued = 0; 698 ring->cur = ring->next = ring->stat = 0; 699 700 error = bus_dmamap_create(sc->sc_dmat, 701 count * sizeof(struct malo_tx_desc), 1, 702 count * sizeof(struct malo_tx_desc), 0, BUS_DMA_NOWAIT, &ring->map); 703 if (error != 0) { 704 aprint_error_dev(sc->sc_dev, "could not create desc DMA map\n"); 705 goto fail; 706 } 707 708 error = bus_dmamem_alloc(sc->sc_dmat, 709 count * sizeof(struct malo_tx_desc), PAGE_SIZE, 0, 710 &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 711 if (error != 0) { 712 aprint_error_dev(sc->sc_dev, "could not allocate DMA memory\n"); 713 goto fail; 714 } 715 716 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 717 count * sizeof(struct malo_tx_desc), (void **)&ring->desc, 718 BUS_DMA_NOWAIT); 719 if (error != 0) { 720 aprint_error_dev(sc->sc_dev, "can't map desc DMA memory\n"); 721 goto fail; 722 } 723 724 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 725 count * sizeof(struct malo_tx_desc), NULL, BUS_DMA_NOWAIT); 726 if (error != 0) { 727 aprint_error_dev(sc->sc_dev, "could not load desc DMA map\n"); 728 goto fail; 729 } 730 731 ring->physaddr = ring->map->dm_segs->ds_addr; 732 733 ring->data = malloc(count * sizeof(struct malo_tx_data), M_DEVBUF, 734 M_NOWAIT); 735 if (ring->data == NULL) { 736 aprint_error_dev(sc->sc_dev, "could not allocate soft data\n"); 737 error = ENOMEM; 738 goto fail; 739 } 740 741 memset(ring->data, 0, count * sizeof(struct malo_tx_data)); 742 for (i = 0; i < count; i++) { 743 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 744 MALO_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 745 &ring->data[i].map); 746 if (error != 0) { 747 aprint_error_dev(sc->sc_dev, "could not create DMA map\n"); 748 goto fail; 749 } 750 ring->desc[i].physnext = htole32(ring->physaddr + 751 (i + 1) % count * sizeof(struct malo_tx_desc)); 752 } 753 754 return (0); 755 756 fail: malo_free_tx_ring(sc, ring); 757 return (error); 758 } 759 760 static void 761 malo_reset_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring) 762 { 763 struct malo_tx_desc *desc; 764 struct malo_tx_data *data; 765 int i; 766 767 for (i = 0; i < ring->count; i++) { 768 desc = &ring->desc[i]; 769 data = &ring->data[i]; 770 771 if (data->m != NULL) { 772 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 773 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 774 bus_dmamap_unload(sc->sc_dmat, data->map); 775 m_freem(data->m); 776 data->m = NULL; 777 } 778 779 /* 780 * The node has already been freed at that point so don't call 781 * ieee80211_release_node() here. 782 */ 783 data->ni = NULL; 784 785 desc->status = 0; 786 } 787 788 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 789 BUS_DMASYNC_PREWRITE); 790 791 ring->queued = 0; 792 ring->cur = ring->next = ring->stat = 0; 793 } 794 795 static void 796 malo_free_tx_ring(struct malo_softc *sc, struct malo_tx_ring *ring) 797 { 798 struct malo_tx_data *data; 799 int i; 800 801 if (ring->desc != NULL) { 802 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 803 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 804 bus_dmamap_unload(sc->sc_dmat, ring->map); 805 bus_dmamem_unmap(sc->sc_dmat, ring->desc, 806 ring->count * sizeof(struct malo_tx_desc)); 807 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 808 } 809 810 if (ring->data != NULL) { 811 for (i = 0; i < ring->count; i++) { 812 data = &ring->data[i]; 813 814 if (data->m != NULL) { 815 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 816 data->map->dm_mapsize, 817 BUS_DMASYNC_POSTWRITE); 818 bus_dmamap_unload(sc->sc_dmat, data->map); 819 m_freem(data->m); 820 } 821 822 /* 823 * The node has already been freed at that point so 824 * don't call ieee80211_release_node() here. 825 */ 826 data->ni = NULL; 827 828 if (data->map != NULL) 829 bus_dmamap_destroy(sc->sc_dmat, data->map); 830 } 831 free(ring->data, M_DEVBUF); 832 } 833 } 834 835 static int 836 malo_init(struct ifnet *ifp) 837 { 838 struct malo_softc *sc = ifp->if_softc; 839 struct ieee80211com *ic = &sc->sc_ic; 840 int error; 841 842 DPRINTF(1, "%s: %s\n", ifp->if_xname, __func__); 843 844 /* if interface already runs stop it first */ 845 if (ifp->if_flags & IFF_RUNNING) 846 malo_stop(ifp, 1); 847 848 /* power on cardbus socket */ 849 if (sc->sc_enable) 850 sc->sc_enable(sc); 851 852 /* disable interrupts */ 853 malo_ctl_read4(sc, MALO_REG_A2H_INTERRUPT_CAUSE); 854 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_CAUSE, 0); 855 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_MASK, 0); 856 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 0); 857 858 /* load firmware */ 859 if ((error = malo_load_bootimg(sc))) 860 goto fail; 861 if ((error = malo_load_firmware(sc))) 862 goto fail; 863 864 /* enable interrupts */ 865 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_MASK, 0x1f); 866 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 867 malo_ctl_write4(sc, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 0x1f); 868 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 869 870 if ((error = malo_cmd_get_spec(sc))) 871 goto fail; 872 873 /* select default channel */ 874 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 875 876 /* initialize hardware */ 877 if ((error = malo_cmd_set_channel(sc, ic->ic_bss->ni_chan))) { 878 aprint_error_dev(sc->sc_dev, "setting channel failed!\n"); 879 goto fail; 880 } 881 if ((error = malo_cmd_set_antenna(sc, 1))) { 882 aprint_error_dev(sc->sc_dev, "setting RX antenna failed!\n"); 883 goto fail; 884 } 885 if ((error = malo_cmd_set_antenna(sc, 2))) { 886 aprint_error_dev(sc->sc_dev, "setting TX antenna failed!\n"); 887 goto fail; 888 } 889 if ((error = malo_cmd_set_radio(sc, 1, 5))) { 890 aprint_error_dev(sc->sc_dev, "turn radio on failed!\n"); 891 goto fail; 892 } 893 if ((error = malo_cmd_set_txpower(sc, 100))) { 894 aprint_error_dev(sc->sc_dev, "setting TX power failed!\n"); 895 goto fail; 896 } 897 if ((error = malo_cmd_set_rts(sc, IEEE80211_RTS_MAX))) { 898 aprint_error_dev(sc->sc_dev, "setting RTS failed!\n"); 899 goto fail; 900 } 901 902 ifp->if_flags |= IFF_RUNNING; 903 904 if (ic->ic_opmode != IEEE80211_M_MONITOR) 905 /* start background scanning */ 906 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 907 else 908 /* in monitor mode change directly into run state */ 909 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 910 911 return (0); 912 913 fail: 914 /* reset adapter */ 915 DPRINTF(1, "%s: malo_init failed, resetting card\n", 916 device_xname(sc->sc_dev)); 917 malo_stop(ifp, 1); 918 return (error); 919 } 920 921 static int 922 malo_ioctl(struct ifnet *ifp, u_long cmd, void* data) 923 { 924 struct malo_softc *sc = ifp->if_softc; 925 struct ieee80211com *ic = &sc->sc_ic; 926 int s, error = 0; 927 928 s = splnet(); 929 930 switch (cmd) { 931 case SIOCSIFFLAGS: 932 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 933 break; 934 if (ifp->if_flags & IFF_UP) { 935 if ((ifp->if_flags & IFF_RUNNING) == 0) 936 malo_init(ifp); 937 } else { 938 if (ifp->if_flags & IFF_RUNNING) 939 malo_stop(ifp, 1); 940 } 941 break; 942 case SIOCADDMULTI: 943 case SIOCDELMULTI: 944 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 945 /* setup multicast filter, etc */ 946 error = 0; 947 } 948 break; 949 case SIOCS80211CHANNEL: 950 /* allow fast channel switching in monitor mode */ 951 error = ieee80211_ioctl(ic, cmd, data); 952 if (error == ENETRESET && 953 ic->ic_opmode == IEEE80211_M_MONITOR) { 954 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 955 (IFF_UP | IFF_RUNNING)) { 956 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 957 malo_cmd_set_channel(sc, ic->ic_bss->ni_chan); 958 } 959 error = 0; 960 } 961 break; 962 default: 963 error = ieee80211_ioctl(ic, cmd, data); 964 break; 965 } 966 967 if (error == ENETRESET) { 968 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 969 (IFF_UP | IFF_RUNNING)) 970 malo_init(ifp); 971 error = 0; 972 } 973 974 splx(s); 975 976 return (error); 977 } 978 979 static void 980 malo_start(struct ifnet *ifp) 981 { 982 struct malo_softc *sc = ifp->if_softc; 983 struct ieee80211com *ic = &sc->sc_ic; 984 struct mbuf *m0; 985 struct ether_header *eh; 986 struct ieee80211_node *ni = NULL; 987 988 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 989 990 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 991 return; 992 993 for (;;) { 994 IF_POLL(&ic->ic_mgtq, m0); 995 if (m0 != NULL) { 996 if (sc->sc_txring.queued >= MALO_TX_RING_COUNT) { 997 ifp->if_flags |= IFF_OACTIVE; 998 break; 999 } 1000 IF_DEQUEUE(&ic->ic_mgtq, m0); 1001 1002 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1003 m0->m_pkthdr.rcvif = NULL; 1004 1005 bpf_mtap3(ic->ic_rawbpf, m0); 1006 1007 if (malo_tx_data(sc, m0, ni) != 0) 1008 break; 1009 } else { 1010 if (ic->ic_state != IEEE80211_S_RUN) 1011 break; 1012 IFQ_POLL(&ifp->if_snd, m0); 1013 if (m0 == NULL) 1014 break; 1015 if (sc->sc_txring.queued >= MALO_TX_RING_COUNT - 1) { 1016 ifp->if_flags |= IFF_OACTIVE; 1017 break; 1018 } 1019 1020 if (m0->m_len < sizeof (*eh) && 1021 (m0 = m_pullup(m0, sizeof (*eh))) == NULL) { 1022 ifp->if_oerrors++; 1023 continue; 1024 } 1025 eh = mtod(m0, struct ether_header *); 1026 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1027 if (ni == NULL) { 1028 m_freem(m0); 1029 ifp->if_oerrors++; 1030 continue; 1031 } 1032 1033 // XXX must I call ieee_classify at this point ? 1034 1035 IFQ_DEQUEUE(&ifp->if_snd, m0); 1036 bpf_mtap(ifp, m0); 1037 1038 m0 = ieee80211_encap(ic, m0, ni); 1039 if (m0 == NULL) 1040 continue; 1041 bpf_mtap(ifp, m0); 1042 1043 if (malo_tx_data(sc, m0, ni) != 0) { 1044 ieee80211_free_node(ni); 1045 ifp->if_oerrors++; 1046 break; 1047 } 1048 } 1049 } 1050 } 1051 1052 static void 1053 malo_stop(struct ifnet* ifp, int disable) 1054 { 1055 struct malo_softc *sc = ifp->if_softc; 1056 struct ieee80211com *ic = &sc->sc_ic; 1057 1058 DPRINTF(1, "%s: %s\n", ifp->if_xname, __func__); 1059 1060 /* reset adapter */ 1061 if (ifp->if_flags & IFF_RUNNING) 1062 malo_ctl_write4(sc, MALO_REG_H2A_INTERRUPT_EVENTS, (1 << 15)); 1063 1064 /* device is not running anymore */ 1065 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1066 1067 /* change back to initial state */ 1068 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1069 1070 /* reset RX / TX rings */ 1071 malo_reset_tx_ring(sc, &sc->sc_txring); 1072 malo_reset_rx_ring(sc, &sc->sc_rxring); 1073 1074 /* set initial rate */ 1075 sc->sc_last_txrate = -1; 1076 1077 /* power off cardbus socket */ 1078 if (sc->sc_disable) 1079 sc->sc_disable(sc); 1080 } 1081 1082 static void 1083 malo_watchdog(struct ifnet *ifp) 1084 { 1085 1086 } 1087 1088 static int 1089 malo_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1090 { 1091 struct ifnet *ifp = ic->ic_ifp; 1092 struct malo_softc *sc = ifp->if_softc; 1093 enum ieee80211_state ostate; 1094 int rate; 1095 1096 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 1097 1098 ostate = ic->ic_state; 1099 callout_stop(&sc->sc_scan_to); 1100 1101 switch (nstate) { 1102 case IEEE80211_S_INIT: 1103 DPRINTF(1, "%s: newstate INIT\n", device_xname(sc->sc_dev)); 1104 break; 1105 case IEEE80211_S_SCAN: 1106 DPRINTF(1, "%s: newstate SCAN\n", device_xname(sc->sc_dev)); 1107 if (ostate == IEEE80211_S_INIT) { 1108 if (malo_cmd_set_prescan(sc) != 0) { 1109 DPRINTF(1, "%s: can't set prescan\n", 1110 device_xname(sc->sc_dev)); 1111 } 1112 } else { 1113 malo_cmd_set_channel(sc, ic->ic_curchan); 1114 } 1115 callout_schedule(&sc->sc_scan_to, hz/2); 1116 break; 1117 case IEEE80211_S_AUTH: 1118 DPRINTF(1, "%s: newstate AUTH\n", device_xname(sc->sc_dev)); 1119 malo_cmd_set_postscan(sc, ic->ic_myaddr, 1); 1120 malo_cmd_set_channel(sc, ic->ic_curchan); 1121 break; 1122 case IEEE80211_S_ASSOC: 1123 DPRINTF(1, "%s: newstate ASSOC\n", device_xname(sc->sc_dev)); 1124 malo_cmd_set_channel(sc, ic->ic_curchan); 1125 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1126 malo_cmd_set_radio(sc, 1, 3); /* short preamble */ 1127 else 1128 malo_cmd_set_radio(sc, 1, 1); /* long preamble */ 1129 1130 malo_cmd_set_aid(sc, ic->ic_bss->ni_bssid, 1131 ic->ic_bss->ni_associd); 1132 1133 if (ic->ic_fixed_rate == -1) 1134 /* automatic rate adaption */ 1135 malo_cmd_set_rate(sc, 0); 1136 else { 1137 /* fixed rate */ 1138 rate = malo_fix2rate(ic->ic_fixed_rate); 1139 malo_cmd_set_rate(sc, rate); 1140 } 1141 1142 malo_set_slot(sc); 1143 break; 1144 case IEEE80211_S_RUN: 1145 DPRINTF(1, "%s: newstate RUN\n", device_xname(sc->sc_dev)); 1146 break; 1147 default: 1148 break; 1149 } 1150 1151 return (sc->sc_newstate(ic, nstate, arg)); 1152 } 1153 1154 static void 1155 malo_newassoc(struct ieee80211_node *ni, int isnew) 1156 { 1157 } 1158 1159 static struct ieee80211_node * 1160 malo_node_alloc(struct ieee80211_node_table *nt) 1161 { 1162 struct malo_node *wn; 1163 1164 wn = malloc(sizeof(*wn), M_DEVBUF, M_NOWAIT | M_ZERO); 1165 if (wn == NULL) 1166 return (NULL); 1167 1168 return ((struct ieee80211_node *)wn); 1169 } 1170 1171 static int 1172 malo_media_change(struct ifnet *ifp) 1173 { 1174 int error; 1175 1176 DPRINTF(1, "%s: %s\n", ifp->if_xname, __func__); 1177 1178 error = ieee80211_media_change(ifp); 1179 if (error != ENETRESET) 1180 return (error); 1181 1182 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1183 malo_init(ifp); 1184 1185 return (0); 1186 } 1187 1188 static void 1189 malo_media_status(struct ifnet *ifp, struct ifmediareq *imr) 1190 { 1191 struct malo_softc *sc = ifp->if_softc; 1192 struct ieee80211com *ic = &sc->sc_ic; 1193 1194 imr->ifm_status = IFM_AVALID; 1195 imr->ifm_active = IFM_IEEE80211; 1196 if (ic->ic_state == IEEE80211_S_RUN) 1197 imr->ifm_status |= IFM_ACTIVE; 1198 1199 /* report last TX rate used by chip */ 1200 imr->ifm_active |= ieee80211_rate2media(ic, sc->sc_last_txrate, 1201 ic->ic_curmode); 1202 1203 switch (ic->ic_opmode) { 1204 case IEEE80211_M_STA: 1205 break; 1206 case IEEE80211_M_IBSS: 1207 imr->ifm_active |= IFM_IEEE80211_ADHOC; 1208 break; 1209 case IEEE80211_M_AHDEMO: 1210 break; 1211 case IEEE80211_M_HOSTAP: 1212 break; 1213 case IEEE80211_M_MONITOR: 1214 imr->ifm_active |= IFM_IEEE80211_MONITOR; 1215 break; 1216 default: 1217 break; 1218 } 1219 1220 switch (ic->ic_curmode) { 1221 case IEEE80211_MODE_11B: 1222 imr->ifm_active |= IFM_IEEE80211_11B; 1223 break; 1224 case IEEE80211_MODE_11G: 1225 imr->ifm_active |= IFM_IEEE80211_11G; 1226 break; 1227 } 1228 } 1229 1230 static int 1231 malo_chip2rate(int chip_rate) 1232 { 1233 switch (chip_rate) { 1234 /* CCK rates */ 1235 case 0: return (2); 1236 case 1: return (4); 1237 case 2: return (11); 1238 case 3: return (22); 1239 1240 /* OFDM rates */ 1241 case 4: return (0); /* reserved */ 1242 case 5: return (12); 1243 case 6: return (18); 1244 case 7: return (24); 1245 case 8: return (36); 1246 case 9: return (48); 1247 case 10: return (72); 1248 case 11: return (96); 1249 case 12: return (108); 1250 1251 /* no rate select yet or unknown rate */ 1252 default: return (-1); 1253 } 1254 } 1255 1256 static int 1257 malo_fix2rate(int fix_rate) 1258 { 1259 switch (fix_rate) { 1260 /* CCK rates */ 1261 case 0: return (2); 1262 case 1: return (4); 1263 case 2: return (11); 1264 case 3: return (22); 1265 1266 /* OFDM rates */ 1267 case 4: return (12); 1268 case 5: return (18); 1269 case 6: return (24); 1270 case 7: return (36); 1271 case 8: return (48); 1272 case 9: return (72); 1273 case 10: return (96); 1274 case 11: return (108); 1275 1276 /* unknown rate: should not happen */ 1277 default: return (0); 1278 } 1279 } 1280 1281 static void 1282 malo_next_scan(void *arg) 1283 { 1284 struct malo_softc *sc = arg; 1285 struct ieee80211com *ic = &sc->sc_ic; 1286 int s; 1287 1288 DPRINTF(1, "%s: %s\n", sc->sc_if.if_xname, __func__); 1289 1290 s = splnet(); 1291 1292 if (ic->ic_state == IEEE80211_S_SCAN) 1293 ieee80211_next_scan(ic); 1294 1295 splx(s); 1296 } 1297 1298 static void 1299 malo_tx_intr(struct malo_softc *sc) 1300 { 1301 struct ifnet *ifp = &sc->sc_if; 1302 struct malo_tx_desc *desc; 1303 struct malo_tx_data *data; 1304 struct malo_node *rn; 1305 int stat; 1306 1307 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 1308 1309 stat = sc->sc_txring.stat; 1310 for (;;) { 1311 desc = &sc->sc_txring.desc[sc->sc_txring.stat]; 1312 data = &sc->sc_txring.data[sc->sc_txring.stat]; 1313 rn = (struct malo_node *)data->ni; 1314 1315 /* check if TX descriptor is not owned by FW anymore */ 1316 if ((le32toh(desc->status) & MALO_TXD_STATUS_FW_OWNED) || 1317 !(le32toh(data->softstat) & MALO_TXD_STATUS_FAILED_AGING)) 1318 break; 1319 1320 /* if no frame has been sent, ignore */ 1321 if (rn == NULL) 1322 goto next; 1323 1324 /* check TX state */ 1325 switch (le32toh(desc->status) & MALO_TXD_STATUS_USED) { 1326 case MALO_TXD_STATUS_OK: 1327 DPRINTF(2, "%s: data frame was sent successfully\n", 1328 device_xname(sc->sc_dev)); 1329 ifp->if_opackets++; 1330 break; 1331 default: 1332 DPRINTF(1, "%s: data frame sending error\n", 1333 device_xname(sc->sc_dev)); 1334 ifp->if_oerrors++; 1335 break; 1336 } 1337 1338 /* save last used TX rate */ 1339 sc->sc_last_txrate = malo_chip2rate(desc->datarate); 1340 1341 /* cleanup TX data and TX descriptor */ 1342 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1343 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1344 bus_dmamap_unload(sc->sc_dmat, data->map); 1345 m_freem(data->m); 1346 ieee80211_free_node(data->ni); 1347 data->m = NULL; 1348 data->ni = NULL; 1349 data->softstat &= htole32(~0x80); 1350 desc->status = 0; 1351 desc->len = 0; 1352 1353 DPRINTF(2, "%s: tx done idx=%u\n", 1354 device_xname(sc->sc_dev), sc->sc_txring.stat); 1355 1356 sc->sc_txring.queued--; 1357 next: 1358 if (++sc->sc_txring.stat >= sc->sc_txring.count) 1359 sc->sc_txring.stat = 0; 1360 if (sc->sc_txring.stat == stat) 1361 break; 1362 } 1363 1364 sc->sc_tx_timer = 0; 1365 ifp->if_flags &= ~IFF_OACTIVE; 1366 malo_start(ifp); 1367 } 1368 1369 static int 1370 malo_tx_data(struct malo_softc *sc, struct mbuf *m0, 1371 struct ieee80211_node *ni) 1372 { 1373 struct ieee80211com *ic = &sc->sc_ic; 1374 struct ifnet *ifp = &sc->sc_if; 1375 struct malo_tx_desc *desc; 1376 struct malo_tx_data *data; 1377 struct ieee80211_frame *wh; 1378 struct ieee80211_key *k; 1379 struct mbuf *mnew; 1380 int error; 1381 1382 DPRINTF(2, "%s: %s\n", device_xname(sc->sc_dev), __func__); 1383 1384 desc = &sc->sc_txring.desc[sc->sc_txring.cur]; 1385 data = &sc->sc_txring.data[sc->sc_txring.cur]; 1386 1387 if (m0->m_len < sizeof(struct ieee80211_frame)) { 1388 m0 = m_pullup(m0, sizeof(struct ieee80211_frame)); 1389 if (m0 == NULL) { 1390 ifp->if_ierrors++; 1391 return (ENOBUFS); 1392 } 1393 } 1394 wh = mtod(m0, struct ieee80211_frame *); 1395 1396 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1397 k = ieee80211_crypto_encap(ic, ni, m0); 1398 if (k == NULL) { 1399 m_freem(m0); 1400 return ENOBUFS; 1401 } 1402 1403 /* packet header may have moved, reset our local pointer */ 1404 wh = mtod(m0, struct ieee80211_frame *); 1405 } 1406 1407 if (sc->sc_drvbpf != NULL) { 1408 struct malo_tx_radiotap_hdr *tap = &sc->sc_txtap; 1409 1410 tap->wt_flags = 0; 1411 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 1412 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 1413 tap->wt_rate = sc->sc_last_txrate; 1414 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1415 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1416 1417 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1418 } 1419 1420 /* 1421 * inject FW specific fields into the 802.11 frame 1422 * 1423 * 2 bytes FW len (inject) 1424 * 24 bytes 802.11 frame header 1425 * 6 bytes addr4 (inject) 1426 * n bytes 802.11 frame body 1427 * 1428 * For now copy all into a new mcluster. 1429 */ 1430 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1431 if (mnew == NULL) 1432 return (ENOBUFS); 1433 MCLGET(mnew, M_DONTWAIT); 1434 if (!(mnew->m_flags & M_EXT)) { 1435 m_free(mnew); 1436 return (ENOBUFS); 1437 } 1438 1439 *mtod(mnew, uint16_t *) = htole16(m0->m_pkthdr.len - 24); /* FW len */ 1440 memmove(mtod(mnew, char*) + 2, wh, sizeof(*wh)); 1441 memset(mtod(mnew, char*) + 26, 0, 6); 1442 m_copydata(m0, sizeof(*wh), m0->m_pkthdr.len - sizeof(*wh), 1443 mtod(mnew, char*) + 32); 1444 mnew->m_pkthdr.len = mnew->m_len = m0->m_pkthdr.len + 8; 1445 m_freem(m0); 1446 m0 = mnew; 1447 1448 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1449 BUS_DMA_NOWAIT); 1450 if (error != 0) { 1451 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", error); 1452 m_freem(m0); 1453 return (error); 1454 } 1455 1456 data->m = m0; 1457 data->ni = ni; 1458 data->softstat |= htole32(0x80); 1459 1460 malo_tx_setup_desc(sc, desc, m0->m_pkthdr.len, 1, 1461 data->map->dm_segs, data->map->dm_nsegs); 1462 1463 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1464 BUS_DMASYNC_PREWRITE); 1465 bus_dmamap_sync(sc->sc_dmat, sc->sc_txring.map, 1466 sc->sc_txring.cur * sizeof(struct malo_tx_desc), 1467 sizeof(struct malo_tx_desc), BUS_DMASYNC_PREWRITE); 1468 1469 DPRINTF(2, "%s: sending frame, pktlen=%u, idx=%u\n", 1470 device_xname(sc->sc_dev), m0->m_pkthdr.len, sc->sc_txring.cur); 1471 1472 sc->sc_txring.queued++; 1473 sc->sc_txring.cur = (sc->sc_txring.cur + 1) % MALO_TX_RING_COUNT; 1474 1475 /* kick data TX */ 1476 malo_ctl_write4(sc, MALO_REG_H2A_INTERRUPT_EVENTS, 1); 1477 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE); 1478 1479 return (0); 1480 } 1481 1482 static void 1483 malo_tx_setup_desc(struct malo_softc *sc, struct malo_tx_desc *desc, 1484 int len, int rate, const bus_dma_segment_t *segs, int nsegs) 1485 { 1486 desc->len = htole16(segs[0].ds_len); 1487 desc->datarate = rate; /* 0 = mgmt frame, 1 = data frame */ 1488 desc->physdata = htole32(segs[0].ds_addr); 1489 desc->status = htole32(MALO_TXD_STATUS_OK | MALO_TXD_STATUS_FW_OWNED); 1490 } 1491 1492 static void 1493 malo_rx_intr(struct malo_softc *sc) 1494 { 1495 struct ieee80211com *ic = &sc->sc_ic; 1496 struct ifnet *ifp = &sc->sc_if; 1497 struct malo_rx_desc *desc; 1498 struct malo_rx_data *data; 1499 struct ieee80211_frame *wh; 1500 struct ieee80211_node *ni; 1501 struct mbuf *mnew, *m; 1502 uint32_t rxRdPtr, rxWrPtr; 1503 int error, i; 1504 1505 rxRdPtr = malo_mem_read4(sc, sc->sc_RxPdRdPtr); 1506 rxWrPtr = malo_mem_read4(sc, sc->sc_RxPdWrPtr); 1507 1508 for (i = 0; i < MALO_RX_RING_COUNT && rxRdPtr != rxWrPtr; i++) { 1509 desc = &sc->sc_rxring.desc[sc->sc_rxring.cur]; 1510 data = &sc->sc_rxring.data[sc->sc_rxring.cur]; 1511 1512 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring.map, 1513 sc->sc_rxring.cur * sizeof(struct malo_rx_desc), 1514 sizeof(struct malo_rx_desc), BUS_DMASYNC_POSTREAD); 1515 1516 DPRINTF(3, "%s: rx intr idx=%d, rxctrl=0x%02x, rssi=%d, " 1517 "status=0x%02x, channel=%d, len=%d, res1=%02x, rate=%d, " 1518 "physdata=0x%04x, physnext=0x%04x, qosctrl=%02x, res2=%d\n", 1519 device_xname(sc->sc_dev), 1520 sc->sc_rxring.cur, desc->rxctrl, desc->rssi, desc->status, 1521 desc->channel, le16toh(desc->len), desc->reserved1, 1522 desc->datarate, le32toh(desc->physdata), 1523 le32toh(desc->physnext), desc->qosctrl, desc->reserved2); 1524 1525 if ((desc->rxctrl & 0x80) == 0) 1526 break; 1527 1528 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1529 if (mnew == NULL) { 1530 ifp->if_ierrors++; 1531 goto skip; 1532 } 1533 1534 MCLGET(mnew, M_DONTWAIT); 1535 if (!(mnew->m_flags & M_EXT)) { 1536 m_freem(mnew); 1537 ifp->if_ierrors++; 1538 goto skip; 1539 } 1540 1541 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1542 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1543 bus_dmamap_unload(sc->sc_dmat, data->map); 1544 1545 error = bus_dmamap_load(sc->sc_dmat, data->map, 1546 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1547 if (error != 0) { 1548 m_freem(mnew); 1549 1550 error = bus_dmamap_load(sc->sc_dmat, data->map, 1551 mtod(data->m, void *), MCLBYTES, NULL, 1552 BUS_DMA_NOWAIT); 1553 if (error != 0) { 1554 panic("%s: could not load old rx mbuf", 1555 device_xname(sc->sc_dev)); 1556 } 1557 ifp->if_ierrors++; 1558 goto skip; 1559 } 1560 1561 /* 1562 * New mbuf mbuf successfully loaded 1563 */ 1564 m = data->m; 1565 data->m = mnew; 1566 desc->physdata = htole32(data->map->dm_segs->ds_addr); 1567 1568 /* finalize mbuf */ 1569 m->m_pkthdr.rcvif = ifp; 1570 m->m_pkthdr.len = m->m_len = le16toh(desc->len); 1571 1572 /* 1573 * cut out FW specific fields from the 802.11 frame 1574 * 1575 * 2 bytes FW len (cut out) 1576 * 24 bytes 802.11 frame header 1577 * 6 bytes addr4 (cut out) 1578 * n bytes 802.11 frame data 1579 */ 1580 memmove(m->m_data +6, m->m_data, 26); 1581 m_adj(m, 8); 1582 1583 if (sc->sc_drvbpf != NULL) { 1584 struct malo_rx_radiotap_hdr *tap = &sc->sc_rxtap; 1585 1586 tap->wr_flags = 0; 1587 tap->wr_chan_freq = 1588 htole16(ic->ic_bss->ni_chan->ic_freq); 1589 tap->wr_chan_flags = 1590 htole16(ic->ic_bss->ni_chan->ic_flags); 1591 1592 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1593 } 1594 1595 wh = mtod(m, struct ieee80211_frame *); 1596 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1597 1598 /* send the frame to the 802.11 layer */ 1599 ieee80211_input(ic, m, ni, desc->rssi, 0); 1600 1601 /* node is no longer needed */ 1602 ieee80211_free_node(ni); 1603 1604 skip: 1605 desc->rxctrl = 0; 1606 rxRdPtr = le32toh(desc->physnext); 1607 1608 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxring.map, 1609 sc->sc_rxring.cur * sizeof(struct malo_rx_desc), 1610 sizeof(struct malo_rx_desc), BUS_DMASYNC_PREWRITE); 1611 1612 sc->sc_rxring.cur = (sc->sc_rxring.cur + 1) % 1613 MALO_RX_RING_COUNT; 1614 } 1615 1616 malo_mem_write4(sc, sc->sc_RxPdRdPtr, rxRdPtr); 1617 } 1618 1619 static int 1620 malo_get_firmware(struct malo_softc *sc, const char *name, 1621 uint8_t** firmware_image, size_t* size) 1622 { 1623 firmware_handle_t fw; 1624 int error; 1625 1626 1627 /* load firmware image from disk */ 1628 if ((error = firmware_open("malo", name, &fw) != 0)) { 1629 aprint_error_dev(sc->sc_dev, "could not read firmware file\n"); 1630 return error; 1631 } 1632 1633 *size = firmware_get_size(fw); 1634 1635 *firmware_image = firmware_malloc(*size); 1636 if (*firmware_image == NULL) { 1637 aprint_error_dev(sc->sc_dev, "not enough memory to stock firmware\n"); 1638 error = ENOMEM; 1639 goto fail1; 1640 } 1641 1642 if ((error = firmware_read(fw, 0, *firmware_image, *size)) != 0) { 1643 aprint_error_dev(sc->sc_dev, "can't get firmware\n"); 1644 goto fail2; 1645 } 1646 1647 firmware_close(fw); 1648 1649 return 0; 1650 fail2: 1651 firmware_free(*firmware_image, *size); 1652 fail1: 1653 firmware_close(fw); 1654 return error; 1655 } 1656 1657 static int 1658 malo_load_bootimg(struct malo_softc *sc) 1659 { 1660 const char *name = "malo8335-h"; 1661 uint8_t *ucode; 1662 size_t size; 1663 int error, i; 1664 1665 /* load boot firmware */ 1666 if ((error = malo_get_firmware(sc, name, &ucode, &size)) != 0) { 1667 aprint_error_dev(sc->sc_dev, "error %d, could not read firmware %s\n", 1668 error, name); 1669 return (EIO); 1670 } 1671 1672 /* 1673 * It seems we are putting this code directly onto the stack of 1674 * the ARM cpu. I don't know why we need to instruct the DMA 1675 * engine to move the code. This is a big riddle without docu. 1676 */ 1677 DPRINTF(1, "%s: loading boot firmware\n", device_xname(sc->sc_dev)); 1678 malo_mem_write2(sc, 0xbef8, 0x001); 1679 malo_mem_write2(sc, 0xbefa, size); 1680 malo_mem_write4(sc, 0xbefc, 0); 1681 1682 bus_space_write_region_1(sc->sc_mem1_bt, sc->sc_mem1_bh, 0xbf00, 1683 ucode, size); 1684 1685 /* 1686 * we loaded the firmware into card memory now tell the CPU 1687 * to fetch the code and execute it. The memory mapped via the 1688 * first bar is internaly mapped to 0xc0000000. 1689 */ 1690 malo_send_cmd(sc, 0xc000bef8); 1691 1692 /* wait for the device to go into FW loading mode */ 1693 for (i = 0; i < 10; i++) { 1694 delay(50); 1695 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_READ); 1696 if (malo_ctl_read4(sc, 0x0c14) == 0x5) 1697 break; 1698 } 1699 if (i == 10) { 1700 aprint_error_dev(sc->sc_dev, "timeout at boot firmware load!\n"); 1701 free(ucode, M_DEVBUF); 1702 return (ETIMEDOUT); 1703 } 1704 firmware_free(ucode, size); 1705 1706 /* tell the card we're done and... */ 1707 malo_mem_write2(sc, 0xbef8, 0x001); 1708 malo_mem_write2(sc, 0xbefa, 0); 1709 malo_mem_write4(sc, 0xbefc, 0); 1710 malo_send_cmd(sc, 0xc000bef8); 1711 1712 DPRINTF(1, "%s: boot firmware loaded\n", device_xname(sc->sc_dev)); 1713 1714 return (0); 1715 } 1716 1717 1718 static int 1719 malo_load_firmware(struct malo_softc *sc) 1720 { 1721 struct malo_cmdheader *hdr; 1722 const char *name = "malo8335-m"; 1723 void *data; 1724 uint8_t *ucode; 1725 size_t size, count, bsize; 1726 int i, sn, error; 1727 1728 /* load real firmware now */ 1729 if ((error = malo_get_firmware(sc, name, &ucode, &size)) != 0) { 1730 aprint_error_dev(sc->sc_dev, "error %d, could not read firmware %s\n", 1731 error, name); 1732 return (EIO); 1733 } 1734 1735 DPRINTF(1, "%s: uploading firmware\n", device_xname(sc->sc_dev)); 1736 1737 hdr = sc->sc_cmd_mem; 1738 data = hdr + 1; 1739 sn = 1; 1740 for (count = 0; count < size; count += bsize) { 1741 bsize = MIN(256, size - count); 1742 1743 hdr->cmd = htole16(0x0001); 1744 hdr->size = htole16(bsize); 1745 hdr->seqnum = htole16(sn++); 1746 hdr->result = 0; 1747 1748 memcpy(data, ucode + count, bsize); 1749 1750 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1751 BUS_DMASYNC_PREWRITE); 1752 malo_send_cmd(sc, sc->sc_cmd_dmaaddr); 1753 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1754 BUS_DMASYNC_POSTWRITE); 1755 delay(500); 1756 } 1757 firmware_free(ucode, size); 1758 1759 DPRINTF(1, "%s: firmware upload finished\n", device_xname(sc->sc_dev)); 1760 1761 /* 1762 * send a command with size 0 to tell that the firmware has been 1763 * uploaded 1764 */ 1765 hdr->cmd = htole16(0x0001); 1766 hdr->size = 0; 1767 hdr->seqnum = htole16(sn++); 1768 hdr->result = 0; 1769 1770 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1771 BUS_DMASYNC_PREWRITE); 1772 malo_send_cmd(sc, sc->sc_cmd_dmaaddr); 1773 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1774 BUS_DMASYNC_POSTWRITE); 1775 delay(100); 1776 1777 DPRINTF(1, "%s: loading firmware\n", device_xname(sc->sc_dev)); 1778 1779 /* wait until firmware has been loaded */ 1780 for (i = 0; i < 200; i++) { 1781 malo_ctl_write4(sc, 0x0c10, 0x5a); 1782 delay(500); 1783 malo_ctl_barrier(sc, BUS_SPACE_BARRIER_WRITE | 1784 BUS_SPACE_BARRIER_READ); 1785 if (malo_ctl_read4(sc, 0x0c14) == 0xf0f1f2f4) 1786 break; 1787 } 1788 if (i == 200) { 1789 aprint_error_dev(sc->sc_dev, "timeout at firmware load!\n"); 1790 return (ETIMEDOUT); 1791 } 1792 1793 DPRINTF(1, "%s: firmware loaded\n", device_xname(sc->sc_dev)); 1794 1795 return (0); 1796 } 1797 1798 static int 1799 malo_set_slot(struct malo_softc *sc) 1800 { 1801 struct ieee80211com *ic = &sc->sc_ic; 1802 1803 if (ic->ic_flags & IEEE80211_F_SHSLOT) { 1804 /* set short slot */ 1805 if (malo_cmd_set_slot(sc, 1)) { 1806 aprint_error_dev(sc->sc_dev, "setting short slot failed\n"); 1807 return (ENXIO); 1808 } 1809 } else { 1810 /* set long slot */ 1811 if (malo_cmd_set_slot(sc, 0)) { 1812 aprint_error_dev(sc->sc_dev, "setting long slot failed\n"); 1813 return (ENXIO); 1814 } 1815 } 1816 1817 return (0); 1818 } 1819 1820 static void 1821 malo_update_slot(struct ifnet* ifp) 1822 { 1823 struct malo_softc *sc = ifp->if_softc; 1824 struct ieee80211com *ic = &sc->sc_ic; 1825 1826 malo_set_slot(sc); 1827 1828 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1829 /* TODO */ 1830 } 1831 } 1832 1833 #ifdef MALO_DEBUG 1834 static void 1835 malo_hexdump(void *buf, int len) 1836 { 1837 u_char b[16]; 1838 int i, j, l; 1839 1840 for (i = 0; i < len; i += l) { 1841 printf("%4i:", i); 1842 l = min(sizeof(b), len - i); 1843 memcpy(b, (char*)buf + i, l); 1844 1845 for (j = 0; j < sizeof(b); j++) { 1846 if (j % 2 == 0) 1847 printf(" "); 1848 if (j % 8 == 0) 1849 printf(" "); 1850 if (j < l) 1851 printf("%02x", (int)b[j]); 1852 else 1853 printf(" "); 1854 } 1855 printf(" |"); 1856 for (j = 0; j < l; j++) { 1857 if (b[j] >= 0x20 && b[j] <= 0x7e) 1858 printf("%c", b[j]); 1859 else 1860 printf("."); 1861 } 1862 printf("|\n"); 1863 } 1864 } 1865 #endif 1866 1867 static const char * 1868 malo_cmd_string(uint16_t cmd) 1869 { 1870 int i; 1871 static char cmd_buf[16]; 1872 static const struct { 1873 uint16_t cmd_code; 1874 const char *cmd_string; 1875 } cmds[] = { 1876 { MALO_CMD_GET_HW_SPEC, "GetHwSpecifications" }, 1877 { MALO_CMD_SET_RADIO, "SetRadio" }, 1878 { MALO_CMD_SET_AID, "SetAid" }, 1879 { MALO_CMD_SET_TXPOWER, "SetTxPower" }, 1880 { MALO_CMD_SET_ANTENNA, "SetAntenna" }, 1881 { MALO_CMD_SET_PRESCAN, "SetPrescan" }, 1882 { MALO_CMD_SET_POSTSCAN, "SetPostscan" }, 1883 { MALO_CMD_SET_RATE, "SetRate" }, 1884 { MALO_CMD_SET_CHANNEL, "SetChannel" }, 1885 { MALO_CMD_SET_RTS, "SetRTS" }, 1886 { MALO_CMD_SET_SLOT, "SetSlot" }, 1887 }; 1888 1889 for (i = 0; i < sizeof(cmds) / sizeof(cmds[0]); i++) 1890 if ((le16toh(cmd) & 0x7fff) == cmds[i].cmd_code) 1891 return (cmds[i].cmd_string); 1892 1893 snprintf(cmd_buf, sizeof(cmd_buf), "unknown %#x", cmd); 1894 return (cmd_buf); 1895 } 1896 1897 static const char * 1898 malo_cmd_string_result(uint16_t result) 1899 { 1900 int i; 1901 static const struct { 1902 uint16_t result_code; 1903 const char *result_string; 1904 } results[] = { 1905 { MALO_CMD_RESULT_OK, "OK" }, 1906 { MALO_CMD_RESULT_ERROR, "general error" }, 1907 { MALO_CMD_RESULT_NOSUPPORT, "not supported" }, 1908 { MALO_CMD_RESULT_PENDING, "pending" }, 1909 { MALO_CMD_RESULT_BUSY, "ignored" }, 1910 { MALO_CMD_RESULT_PARTIALDATA, "incomplete" }, 1911 }; 1912 1913 for (i = 0; i < sizeof(results) / sizeof(results[0]); i++) 1914 if (le16toh(result) == results[i].result_code) 1915 return (results[i].result_string); 1916 1917 return ("unknown"); 1918 } 1919 1920 static int 1921 malo_cmd_get_spec(struct malo_softc *sc) 1922 { 1923 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 1924 struct malo_hw_spec *spec; 1925 1926 hdr->cmd = htole16(MALO_CMD_GET_HW_SPEC); 1927 hdr->size = htole16(sizeof(*hdr) + sizeof(*spec)); 1928 hdr->seqnum = htole16(42); /* the one and only */ 1929 hdr->result = 0; 1930 spec = (struct malo_hw_spec *)(hdr + 1); 1931 1932 memset(spec, 0, sizeof(*spec)); 1933 memset(spec->PermanentAddress, 0xff, ETHER_ADDR_LEN); 1934 spec->CookiePtr = htole32(sc->sc_cookie_dmaaddr); 1935 1936 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1937 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1938 1939 if (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr) != 0) 1940 return (ETIMEDOUT); 1941 1942 /* get the data from the buffer */ 1943 DPRINTF(1, "%s: get_hw_spec: V%x R%x, #WCB %d, #Mcast %d, Regcode %d, " 1944 "#Ant %d\n", device_xname(sc->sc_dev), htole16(spec->HwVersion), 1945 htole32(spec->FWReleaseNumber), htole16(spec->NumOfWCB), 1946 htole16(spec->NumOfMCastAdr), htole16(spec->RegionCode), 1947 htole16(spec->NumberOfAntenna)); 1948 1949 /* tell the DMA engine where our rings are */ 1950 malo_mem_write4(sc, le32toh(spec->RxPdRdPtr) & 0xffff, 1951 sc->sc_rxring.physaddr); 1952 malo_mem_write4(sc, le32toh(spec->RxPdWrPtr) & 0xffff, 1953 sc->sc_rxring.physaddr); 1954 malo_mem_write4(sc, le32toh(spec->WcbBase0) & 0xffff, 1955 sc->sc_txring.physaddr); 1956 1957 /* save DMA RX pointers for later use */ 1958 sc->sc_RxPdRdPtr = le32toh(spec->RxPdRdPtr) & 0xffff; 1959 sc->sc_RxPdWrPtr = le32toh(spec->RxPdWrPtr) & 0xffff; 1960 1961 return (0); 1962 } 1963 1964 static int 1965 malo_cmd_set_prescan(struct malo_softc *sc) 1966 { 1967 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 1968 1969 hdr->cmd = htole16(MALO_CMD_SET_PRESCAN); 1970 hdr->size = htole16(sizeof(*hdr)); 1971 hdr->seqnum = 1; 1972 hdr->result = 0; 1973 1974 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1975 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1976 1977 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 1978 } 1979 1980 static int 1981 malo_cmd_set_postscan(struct malo_softc *sc, uint8_t *macaddr, uint8_t ibsson) 1982 { 1983 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 1984 struct malo_cmd_postscan *body; 1985 1986 hdr->cmd = htole16(MALO_CMD_SET_POSTSCAN); 1987 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 1988 hdr->seqnum = 1; 1989 hdr->result = 0; 1990 body = (struct malo_cmd_postscan *)(hdr + 1); 1991 1992 memset(body, 0, sizeof(*body)); 1993 memcpy(&body->bssid, macaddr, ETHER_ADDR_LEN); 1994 body->isibss = htole32(ibsson); 1995 1996 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 1997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1998 1999 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2000 } 2001 2002 static int 2003 malo_cmd_set_channel(struct malo_softc *sc, struct ieee80211_channel* chan) 2004 { 2005 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2006 struct ieee80211com *ic = &sc->sc_ic; 2007 struct malo_cmd_channel *body; 2008 uint8_t channel; 2009 2010 channel = ieee80211_chan2ieee(ic, chan); 2011 2012 hdr->cmd = htole16(MALO_CMD_SET_CHANNEL); 2013 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2014 hdr->seqnum = 1; 2015 hdr->result = 0; 2016 body = (struct malo_cmd_channel *)(hdr + 1); 2017 2018 memset(body, 0, sizeof(*body)); 2019 body->action = htole16(1); 2020 body->channel = channel; 2021 2022 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2023 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2024 2025 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2026 } 2027 2028 static int 2029 malo_cmd_set_antenna(struct malo_softc *sc, uint16_t antenna) 2030 { 2031 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2032 struct malo_cmd_antenna *body; 2033 2034 hdr->cmd = htole16(MALO_CMD_SET_ANTENNA); 2035 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2036 hdr->seqnum = 1; 2037 hdr->result = 0; 2038 body = (struct malo_cmd_antenna *)(hdr + 1); 2039 2040 memset(body, 0, sizeof(*body)); 2041 body->action = htole16(antenna); 2042 if (antenna == 1) 2043 body->mode = htole16(0xffff); 2044 else 2045 body->mode = htole16(2); 2046 2047 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2048 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2049 2050 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2051 } 2052 2053 static int 2054 malo_cmd_set_radio(struct malo_softc *sc, uint16_t enable, 2055 uint16_t preamble_mode) 2056 { 2057 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2058 struct malo_cmd_radio *body; 2059 2060 hdr->cmd = htole16(MALO_CMD_SET_RADIO); 2061 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2062 hdr->seqnum = 1; 2063 hdr->result = 0; 2064 body = (struct malo_cmd_radio *)(hdr + 1); 2065 2066 memset(body, 0, sizeof(*body)); 2067 body->action = htole16(1); 2068 body->preamble_mode = htole16(preamble_mode); 2069 body->enable = htole16(enable); 2070 2071 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2072 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2073 2074 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2075 } 2076 2077 static int 2078 malo_cmd_set_aid(struct malo_softc *sc, uint8_t *bssid, uint16_t associd) 2079 { 2080 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2081 struct malo_cmd_aid *body; 2082 2083 hdr->cmd = htole16(MALO_CMD_SET_AID); 2084 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2085 hdr->seqnum = 1; 2086 hdr->result = 0; 2087 body = (struct malo_cmd_aid *)(hdr + 1); 2088 2089 memset(body, 0, sizeof(*body)); 2090 body->associd = htole16(associd); 2091 memcpy(&body->macaddr[0], bssid, IEEE80211_ADDR_LEN); 2092 2093 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2095 2096 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2097 } 2098 2099 static int 2100 malo_cmd_set_txpower(struct malo_softc *sc, unsigned int powerlevel) 2101 { 2102 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2103 struct malo_cmd_txpower *body; 2104 2105 hdr->cmd = htole16(MALO_CMD_SET_TXPOWER); 2106 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2107 hdr->seqnum = 1; 2108 hdr->result = 0; 2109 body = (struct malo_cmd_txpower *)(hdr + 1); 2110 2111 memset(body, 0, sizeof(*body)); 2112 body->action = htole16(1); 2113 if (powerlevel < 30) 2114 body->supportpowerlvl = htole16(5); /* LOW */ 2115 else if (powerlevel >= 30 && powerlevel < 60) 2116 body->supportpowerlvl = htole16(10); /* MEDIUM */ 2117 else 2118 body->supportpowerlvl = htole16(15); /* HIGH */ 2119 2120 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2121 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2122 2123 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2124 } 2125 2126 static int 2127 malo_cmd_set_rts(struct malo_softc *sc, uint32_t threshold) 2128 { 2129 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2130 struct malo_cmd_rts *body; 2131 2132 hdr->cmd = htole16(MALO_CMD_SET_RTS); 2133 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2134 hdr->seqnum = 1; 2135 hdr->result = 0; 2136 body = (struct malo_cmd_rts *)(hdr + 1); 2137 2138 memset(body, 0, sizeof(*body)); 2139 body->action = htole16(1); 2140 body->threshold = htole32(threshold); 2141 2142 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2143 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2144 2145 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2146 } 2147 2148 static int 2149 malo_cmd_set_slot(struct malo_softc *sc, uint8_t slot) 2150 { 2151 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2152 struct malo_cmd_slot *body; 2153 2154 hdr->cmd = htole16(MALO_CMD_SET_SLOT); 2155 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2156 hdr->seqnum = 1; 2157 hdr->result = 0; 2158 body = (struct malo_cmd_slot *)(hdr + 1); 2159 2160 memset(body, 0, sizeof(*body)); 2161 body->action = htole16(1); 2162 body->slot = slot; 2163 2164 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2165 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2166 2167 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2168 } 2169 2170 static int 2171 malo_cmd_set_rate(struct malo_softc *sc, uint8_t rate) 2172 { 2173 struct ieee80211com *ic = &sc->sc_ic; 2174 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2175 struct malo_cmd_rate *body; 2176 int i; 2177 2178 hdr->cmd = htole16(MALO_CMD_SET_RATE); 2179 hdr->size = htole16(sizeof(*hdr) + sizeof(*body)); 2180 hdr->seqnum = 1; 2181 hdr->result = 0; 2182 body = (struct malo_cmd_rate *)(hdr + 1); 2183 2184 memset(body, 0,sizeof(*body)); 2185 2186 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2187 /* TODO */ 2188 } else 2189 { 2190 body->aprates[0] = 2; 2191 body->aprates[1] = 4; 2192 body->aprates[2] = 11; 2193 body->aprates[3] = 22; 2194 if (ic->ic_curmode == IEEE80211_MODE_11G) { 2195 body->aprates[4] = 0; 2196 body->aprates[5] = 12; 2197 body->aprates[6] = 18; 2198 body->aprates[7] = 24; 2199 body->aprates[8] = 36; 2200 body->aprates[9] = 48; 2201 body->aprates[10] = 72; 2202 body->aprates[11] = 96; 2203 body->aprates[12] = 108; 2204 } 2205 } 2206 2207 if (rate != 0) { 2208 /* fixed rate */ 2209 for (i = 0; i < 13; i++) { 2210 if (body->aprates[i] == rate) { 2211 body->rateindex = i; 2212 body->dataratetype = 1; 2213 break; 2214 } 2215 } 2216 } 2217 2218 bus_dmamap_sync(sc->sc_dmat, sc->sc_cmd_dmam, 0, PAGE_SIZE, 2219 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2220 2221 return (malo_send_cmd_dma(sc, sc->sc_cmd_dmaaddr)); 2222 } 2223 2224 static void 2225 malo_cmd_response(struct malo_softc *sc) 2226 { 2227 struct malo_cmdheader *hdr = sc->sc_cmd_mem; 2228 2229 if (le16toh(hdr->result) != MALO_CMD_RESULT_OK) { 2230 aprint_error_dev(sc->sc_dev, "firmware cmd %s failed with %s\n", 2231 malo_cmd_string(hdr->cmd), 2232 malo_cmd_string_result(hdr->result)); 2233 } 2234 2235 #ifdef MALO_DEBUG 2236 aprint_error_dev(sc->sc_dev, "cmd answer for %s=%s\n", 2237 malo_cmd_string(hdr->cmd), 2238 malo_cmd_string_result(hdr->result)); 2239 2240 if (malo_d > 2) 2241 malo_hexdump(hdr, le16toh(hdr->size)); 2242 #endif 2243 } 2244
Indexes created Wed Sep 24 05:09:52 GMT 2025