mb89352.c revision 1.22
1 /* $NetBSD: mb89352.c,v 1.22 2003/08/01 00:38:38 tsutsui Exp $ */ 2 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */ 3 4 /*- 5 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Charles M. Hannum. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * Copyright (c) 1994 Jarle Greipsland 26 * All rights reserved. 27 * 28 * Redistribution and use in source and binary forms, with or without 29 * modification, are permitted provided that the following conditions 30 * are met: 31 * 1. Redistributions of source code must retain the above copyright 32 * notice, this list of conditions and the following disclaimer. 33 * 2. Redistributions in binary form must reproduce the above copyright 34 * notice, this list of conditions and the following disclaimer in the 35 * documentation and/or other materials provided with the distribution. 36 * 3. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 41 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 42 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 43 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 44 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 46 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 47 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 48 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 49 * POSSIBILITY OF SUCH DAMAGE. 50 */ 51 /* 52 * [NetBSD for NEC PC-98 series] 53 * Copyright (c) 1996, 1997, 1998 54 * NetBSD/pc98 porting staff. All rights reserved. 55 * Copyright (c) 1996, 1997, 1998 56 * Kouichi Matsuda. All rights reserved. 57 */ 58 59 /* 60 * Acknowledgements: Many of the algorithms used in this driver are 61 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 62 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 63 */ 64 65 /* TODO list: 66 * 1) Get the DMA stuff working. 67 * 2) Get the iov/uio stuff working. Is this a good thing ??? 68 * 3) Get the synch stuff working. 69 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: mb89352.c,v 1.22 2003/08/01 00:38:38 tsutsui Exp $"); 74 75 #ifdef DDB 76 #define integrate 77 #else 78 #define integrate __inline static 79 #endif 80 81 /* 82 * A few customizable items: 83 */ 84 85 /* Synchronous data transfers? */ 86 #define SPC_USE_SYNCHRONOUS 0 87 #define SPC_SYNC_REQ_ACK_OFS 8 88 89 /* Wide data transfers? */ 90 #define SPC_USE_WIDE 0 91 #define SPC_MAX_WIDTH 0 92 93 /* Max attempts made to transmit a message */ 94 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 95 96 /* 97 * Some spin loop parameters (essentially how long to wait some places) 98 * The problem(?) is that sometimes we expect either to be able to transmit a 99 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 100 * returning from the interrupt just to get yanked back for the next byte we 101 * may spin in the interrupt routine waiting for this byte to come. How long? 102 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 103 */ 104 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 105 #define SPC_MSGOUT_SPIN 1 106 107 /* 108 * Include debug functions? At the end of this file there are a bunch of 109 * functions that will print out various information regarding queued SCSI 110 * commands, driver state and chip contents. You can call them from the 111 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 112 * kernel uses less memory) but you lose the debugging facilities. 113 */ 114 #if 0 115 #define SPC_DEBUG 1 116 #endif 117 118 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 119 120 /* threshold length for DMA transfer */ 121 #define SPC_MIN_DMA_LEN 32 122 123 #ifdef x68k /* XXX it seems x68k SPC SCSI hardware has some quirks */ 124 #define NEED_DREQ_ON_HARDWARE_XFER 125 #define NO_MANUAL_XFER 126 #endif 127 128 /* End of customizable parameters */ 129 130 /* 131 * MB89352 SCSI Protocol Controller (SPC) routines. 132 */ 133 134 #include "opt_ddb.h" 135 136 #include <sys/param.h> 137 #include <sys/systm.h> 138 #include <sys/kernel.h> 139 #include <sys/errno.h> 140 #include <sys/ioctl.h> 141 #include <sys/device.h> 142 #include <sys/buf.h> 143 #include <sys/proc.h> 144 #include <sys/user.h> 145 #include <sys/queue.h> 146 147 #include <machine/intr.h> 148 #include <machine/bus.h> 149 150 #include <dev/scsipi/scsi_all.h> 151 #include <dev/scsipi/scsipi_all.h> 152 #include <dev/scsipi/scsi_message.h> 153 #include <dev/scsipi/scsiconf.h> 154 155 #include <dev/ic/mb89352reg.h> 156 #include <dev/ic/mb89352var.h> 157 158 #ifndef DDB 159 #define Debugger() panic("should call debugger here (mb89352.c)") 160 #endif /* ! DDB */ 161 162 #if SPC_DEBUG 163 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */ 164 #endif 165 166 void spc_done __P((struct spc_softc *, struct spc_acb *)); 167 void spc_dequeue __P((struct spc_softc *, struct spc_acb *)); 168 void spc_scsipi_request __P((struct scsipi_channel *, 169 scsipi_adapter_req_t, void *)); 170 int spc_poll __P((struct spc_softc *, struct scsipi_xfer *, int)); 171 integrate void spc_sched_msgout __P((struct spc_softc *, u_char)); 172 integrate void spc_setsync __P((struct spc_softc *, struct spc_tinfo *)); 173 void spc_select __P((struct spc_softc *, struct spc_acb *)); 174 void spc_timeout __P((void *)); 175 void spc_scsi_reset __P((struct spc_softc *)); 176 void spc_reset __P((struct spc_softc *)); 177 void spc_free_acb __P((struct spc_softc *, struct spc_acb *, int)); 178 struct spc_acb* spc_get_acb __P((struct spc_softc *)); 179 int spc_reselect __P((struct spc_softc *, int)); 180 void spc_msgin __P((struct spc_softc *)); 181 void spc_abort __P((struct spc_softc *, struct spc_acb *)); 182 void spc_msgout __P((struct spc_softc *)); 183 int spc_dataout_pio __P((struct spc_softc *, u_char *, int)); 184 int spc_datain_pio __P((struct spc_softc *, u_char *, int)); 185 #if SPC_DEBUG 186 void spc_print_acb __P((struct spc_acb *)); 187 void spc_dump_driver __P((struct spc_softc *)); 188 void spc_dump89352 __P((struct spc_softc *)); 189 void spc_show_scsi_cmd __P((struct spc_acb *)); 190 void spc_print_active_acb __P((void)); 191 #endif 192 193 extern struct cfdriver spc_cd; 194 195 /* 196 * INITIALIZATION ROUTINES (probe, attach ++) 197 */ 198 199 /* 200 * Do the real search-for-device. 201 * Prerequisite: sc->sc_iobase should be set to the proper value 202 */ 203 int 204 spc_find(iot, ioh, bdid) 205 bus_space_tag_t iot; 206 bus_space_handle_t ioh; 207 int bdid; 208 { 209 long timeout = SPC_ABORT_TIMEOUT; 210 211 SPC_TRACE(("spc: probing for spc-chip\n")); 212 /* 213 * Disable interrupts then reset the FUJITSU chip. 214 */ 215 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 216 bus_space_write_1(iot, ioh, SCMD, 0); 217 bus_space_write_1(iot, ioh, PCTL, 0); 218 bus_space_write_1(iot, ioh, TEMP, 0); 219 bus_space_write_1(iot, ioh, TCH, 0); 220 bus_space_write_1(iot, ioh, TCM, 0); 221 bus_space_write_1(iot, ioh, TCL, 0); 222 bus_space_write_1(iot, ioh, INTS, 0); 223 bus_space_write_1(iot, ioh, SCTL, 224 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 225 bus_space_write_1(iot, ioh, BDID, bdid); 226 delay(400); 227 bus_space_write_1(iot, ioh, SCTL, 228 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 229 230 /* The following detection is derived from spc.c 231 * (by Takahide Matsutsuka) in FreeBSD/pccard-test. 232 */ 233 while (bus_space_read_1(iot, ioh, PSNS) && timeout) { 234 timeout--; 235 DELAY(1); 236 } 237 if (timeout == 0) { 238 printf("spc: find failed\n"); 239 return 0; 240 } 241 242 SPC_START(("SPC found")); 243 return 1; 244 } 245 246 void 247 spc_attach(sc) 248 struct spc_softc *sc; 249 { 250 251 SPC_TRACE(("spc_attach ")); 252 sc->sc_state = SPC_INIT; 253 254 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 255 256 #if SPC_USE_SYNCHRONOUS 257 /* 258 * These are the bounds of the sync period, based on the frequency of 259 * the chip's clock input and the size and offset of the sync period 260 * register. 261 * 262 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 263 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 264 * minimum transfer rate. 265 */ 266 sc->sc_minsync = (2 * 250) / sc->sc_freq; 267 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 268 #endif 269 270 spc_init(sc); /* Init chip and driver */ 271 272 /* 273 * Fill in the adapter. 274 */ 275 sc->sc_adapter.adapt_dev = &sc->sc_dev; 276 sc->sc_adapter.adapt_nchannels = 1; 277 sc->sc_adapter.adapt_openings = 7; 278 sc->sc_adapter.adapt_max_periph = 1; 279 sc->sc_adapter.adapt_minphys = minphys; 280 sc->sc_adapter.adapt_request = spc_scsipi_request; 281 282 sc->sc_channel.chan_adapter = &sc->sc_adapter; 283 sc->sc_channel.chan_bustype = &scsi_bustype; 284 sc->sc_channel.chan_channel = 0; 285 sc->sc_channel.chan_ntargets = 8; 286 sc->sc_channel.chan_nluns = 8; 287 sc->sc_channel.chan_id = sc->sc_initiator; 288 289 /* 290 * ask the adapter what subunits are present 291 */ 292 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 293 } 294 295 /* 296 * Initialize MB89352 chip itself 297 * The following conditions should hold: 298 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc 299 * must be valid. 300 */ 301 void 302 spc_reset(sc) 303 struct spc_softc *sc; 304 { 305 bus_space_tag_t iot = sc->sc_iot; 306 bus_space_handle_t ioh = sc->sc_ioh; 307 308 SPC_TRACE(("spc_reset ")); 309 /* 310 * Disable interrupts then reset the FUJITSU chip. 311 */ 312 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 313 bus_space_write_1(iot, ioh, SCMD, 0); 314 bus_space_write_1(iot, ioh, TMOD, 0); 315 bus_space_write_1(iot, ioh, PCTL, 0); 316 bus_space_write_1(iot, ioh, TEMP, 0); 317 bus_space_write_1(iot, ioh, TCH, 0); 318 bus_space_write_1(iot, ioh, TCM, 0); 319 bus_space_write_1(iot, ioh, TCL, 0); 320 bus_space_write_1(iot, ioh, INTS, 0); 321 bus_space_write_1(iot, ioh, SCTL, 322 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 323 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator); 324 delay(400); 325 bus_space_write_1(iot, ioh, SCTL, 326 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 327 } 328 329 330 /* 331 * Pull the SCSI RST line for 500us. 332 */ 333 void 334 spc_scsi_reset(sc) 335 struct spc_softc *sc; 336 { 337 bus_space_tag_t iot = sc->sc_iot; 338 bus_space_handle_t ioh = sc->sc_ioh; 339 340 SPC_TRACE(("spc_scsi_reset ")); 341 bus_space_write_1(iot, ioh, SCMD, 342 bus_space_read_1(iot, ioh, SCMD) | SCMD_RST); 343 delay(500); 344 bus_space_write_1(iot, ioh, SCMD, 345 bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST); 346 delay(50); 347 } 348 349 /* 350 * Initialize spc SCSI driver. 351 */ 352 void 353 spc_init(sc) 354 struct spc_softc *sc; 355 { 356 struct spc_acb *acb; 357 int r; 358 359 SPC_TRACE(("spc_init ")); 360 spc_reset(sc); 361 spc_scsi_reset(sc); 362 spc_reset(sc); 363 364 if (sc->sc_state == SPC_INIT) { 365 /* First time through; initialize. */ 366 TAILQ_INIT(&sc->ready_list); 367 TAILQ_INIT(&sc->nexus_list); 368 TAILQ_INIT(&sc->free_list); 369 sc->sc_nexus = NULL; 370 acb = sc->sc_acb; 371 memset(acb, 0, sizeof(sc->sc_acb)); 372 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 373 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 374 acb++; 375 } 376 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 377 } else { 378 /* Cancel any active commands. */ 379 sc->sc_state = SPC_CLEANING; 380 if ((acb = sc->sc_nexus) != NULL) { 381 acb->xs->error = XS_DRIVER_STUFFUP; 382 callout_stop(&acb->xs->xs_callout); 383 spc_done(sc, acb); 384 } 385 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) { 386 acb->xs->error = XS_DRIVER_STUFFUP; 387 callout_stop(&acb->xs->xs_callout); 388 spc_done(sc, acb); 389 } 390 } 391 392 sc->sc_prevphase = PH_INVALID; 393 for (r = 0; r < 8; r++) { 394 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 395 396 ti->flags = 0; 397 #if SPC_USE_SYNCHRONOUS 398 ti->flags |= DO_SYNC; 399 ti->period = sc->sc_minsync; 400 ti->offset = SPC_SYNC_REQ_ACK_OFS; 401 #else 402 ti->period = ti->offset = 0; 403 #endif 404 #if SPC_USE_WIDE 405 ti->flags |= DO_WIDE; 406 ti->width = SPC_MAX_WIDTH; 407 #else 408 ti->width = 0; 409 #endif 410 } 411 412 sc->sc_state = SPC_IDLE; 413 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL, 414 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB); 415 } 416 417 void 418 spc_free_acb(sc, acb, flags) 419 struct spc_softc *sc; 420 struct spc_acb *acb; 421 int flags; 422 { 423 int s; 424 425 SPC_TRACE(("spc_free_acb ")); 426 s = splbio(); 427 428 acb->flags = 0; 429 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 430 splx(s); 431 } 432 433 struct spc_acb * 434 spc_get_acb(sc) 435 struct spc_softc *sc; 436 { 437 struct spc_acb *acb; 438 int s; 439 440 SPC_TRACE(("spc_get_acb ")); 441 s = splbio(); 442 acb = TAILQ_FIRST(&sc->free_list); 443 if (acb != NULL) { 444 TAILQ_REMOVE(&sc->free_list, acb, chain); 445 acb->flags |= ACB_ALLOC; 446 } 447 splx(s); 448 return acb; 449 } 450 451 /* 452 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 453 */ 454 455 /* 456 * Expected sequence: 457 * 1) Command inserted into ready list 458 * 2) Command selected for execution 459 * 3) Command won arbitration and has selected target device 460 * 4) Send message out (identify message, eventually also sync.negotiations) 461 * 5) Send command 462 * 5a) Receive disconnect message, disconnect. 463 * 5b) Reselected by target 464 * 5c) Receive identify message from target. 465 * 6) Send or receive data 466 * 7) Receive status 467 * 8) Receive message (command complete etc.) 468 */ 469 470 /* 471 * Start a SCSI-command 472 * This function is called by the higher level SCSI-driver to queue/run 473 * SCSI-commands. 474 */ 475 void 476 spc_scsipi_request(chan, req, arg) 477 struct scsipi_channel *chan; 478 scsipi_adapter_req_t req; 479 void *arg; 480 { 481 struct scsipi_xfer *xs; 482 struct scsipi_periph *periph; 483 struct spc_softc *sc = (void *)chan->chan_adapter->adapt_dev; 484 struct spc_acb *acb; 485 int s, flags; 486 487 switch (req) { 488 case ADAPTER_REQ_RUN_XFER: 489 xs = arg; 490 periph = xs->xs_periph; 491 SPC_TRACE(("spc_scsipi_request ")); 492 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 493 periph->periph_target)); 494 495 flags = xs->xs_control; 496 acb = spc_get_acb(sc); 497 #ifdef DIAGNOSTIC 498 /* 499 * This should nerver happen as we track the resources 500 * in the mid-layer. 501 */ 502 if (acb == NULL) { 503 scsipi_printaddr(periph); 504 printf("unable to allocate acb\n"); 505 panic("spc_scsipi_request"); 506 } 507 #endif 508 509 /* Initialize acb */ 510 acb->xs = xs; 511 acb->timeout = xs->timeout; 512 513 if (xs->xs_control & XS_CTL_RESET) { 514 acb->flags |= ACB_RESET; 515 acb->scsipi_cmd_length = 0; 516 acb->data_length = 0; 517 } else { 518 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen); 519 acb->scsipi_cmd_length = xs->cmdlen; 520 acb->data_addr = xs->data; 521 acb->data_length = xs->datalen; 522 } 523 acb->target_stat = 0; 524 525 s = splbio(); 526 527 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 528 /* 529 * Start scheduling unless a queue process is in progress. 530 */ 531 if (sc->sc_state == SPC_IDLE) 532 spc_sched(sc); 533 /* 534 * After successful sending, check if we should return just now. 535 * If so, return SUCCESSFULLY_QUEUED. 536 */ 537 538 splx(s); 539 540 if ((flags & XS_CTL_POLL) == 0) 541 return; 542 543 /* Not allowed to use interrupts, use polling instead */ 544 s = splbio(); 545 if (spc_poll(sc, xs, acb->timeout)) { 546 spc_timeout(acb); 547 if (spc_poll(sc, xs, acb->timeout)) 548 spc_timeout(acb); 549 } 550 splx(s); 551 return; 552 case ADAPTER_REQ_GROW_RESOURCES: 553 /* XXX Not supported. */ 554 return; 555 case ADAPTER_REQ_SET_XFER_MODE: 556 { 557 /* 558 * We don't support Sync, Wide, or Tagged Command Queuing. 559 * Just callback now, to report this. 560 */ 561 struct scsipi_xfer_mode *xm = arg; 562 563 xm->xm_mode = 0; 564 xm->xm_period = 0; 565 xm->xm_offset = 0; 566 scsipi_async_event(chan, ASYNC_EVENT_XFER_MODE, xm); 567 return; 568 } 569 } 570 } 571 572 /* 573 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 574 */ 575 int 576 spc_poll(sc, xs, count) 577 struct spc_softc *sc; 578 struct scsipi_xfer *xs; 579 int count; 580 { 581 bus_space_tag_t iot = sc->sc_iot; 582 bus_space_handle_t ioh = sc->sc_ioh; 583 584 SPC_TRACE(("spc_poll ")); 585 while (count) { 586 /* 587 * If we had interrupts enabled, would we 588 * have got an interrupt? 589 */ 590 if (bus_space_read_1(iot, ioh, INTS) != 0) 591 spc_intr(sc); 592 if ((xs->xs_status & XS_STS_DONE) != 0) 593 return 0; 594 delay(1000); 595 count--; 596 } 597 return 1; 598 } 599 600 /* 601 * LOW LEVEL SCSI UTILITIES 602 */ 603 604 integrate void 605 spc_sched_msgout(sc, m) 606 struct spc_softc *sc; 607 u_char m; 608 { 609 bus_space_tag_t iot = sc->sc_iot; 610 bus_space_handle_t ioh = sc->sc_ioh; 611 612 SPC_TRACE(("spc_sched_msgout ")); 613 if (sc->sc_msgpriq == 0) 614 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 615 sc->sc_msgpriq |= m; 616 } 617 618 /* 619 * Set synchronous transfer offset and period. 620 */ 621 integrate void 622 spc_setsync(sc, ti) 623 struct spc_softc *sc; 624 struct spc_tinfo *ti; 625 { 626 #if SPC_USE_SYNCHRONOUS 627 bus_space_tag_t iot = sc->sc_iot; 628 bus_space_handle_t ioh = sc->sc_ioh; 629 630 SPC_TRACE(("spc_setsync ")); 631 if (ti->offset != 0) 632 bus_space_write_1(iot, ioh, TMOD, 633 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 634 else 635 bus_space_write_1(iot, ioh, TMOD, 0); 636 #endif 637 } 638 639 /* 640 * Start a selection. This is used by spc_sched() to select an idle target. 641 */ 642 void 643 spc_select(sc, acb) 644 struct spc_softc *sc; 645 struct spc_acb *acb; 646 { 647 struct scsipi_periph *periph = acb->xs->xs_periph; 648 int target = periph->periph_target; 649 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 650 bus_space_tag_t iot = sc->sc_iot; 651 bus_space_handle_t ioh = sc->sc_ioh; 652 653 SPC_TRACE(("spc_select ")); 654 spc_setsync(sc, ti); 655 656 #if 0 657 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 658 #endif 659 #ifdef x68k /* XXX? */ 660 do { 661 asm ("nop"); 662 } while (bus_space_read_1(iot, ioh, SSTS) & 663 (SSTS_ACTIVE|SSTS_TARGET|SSTS_BUSY)); 664 #endif 665 666 bus_space_write_1(iot, ioh, PCTL, 0); 667 bus_space_write_1(iot, ioh, TEMP, 668 (1 << sc->sc_initiator) | (1 << target)); 669 /* 670 * Setup BSY timeout (selection timeout). 671 * 250ms according to the SCSI specification. 672 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k) 673 * To setup 256ms timeout, 674 * 128000ns/200ns = X * 256 + 15 675 * 640 - 15 = X * 256 676 * X = 625 / 256 677 * X = 2 + 113 / 256 678 * ==> tch = 2, tcm = 113 (correct?) 679 */ 680 /* Time to the information transfer phase start. */ 681 /* XXX These values should be calculated from sc_freq */ 682 bus_space_write_1(iot, ioh, TCH, 2); 683 bus_space_write_1(iot, ioh, TCM, 113); 684 bus_space_write_1(iot, ioh, TCL, 3); 685 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT); 686 687 sc->sc_state = SPC_SELECTING; 688 } 689 690 int 691 spc_reselect(sc, message) 692 struct spc_softc *sc; 693 int message; 694 { 695 u_char selid, target, lun; 696 struct spc_acb *acb; 697 struct scsipi_periph *periph; 698 struct spc_tinfo *ti; 699 700 SPC_TRACE(("spc_reselect ")); 701 /* 702 * The SCSI chip made a snapshot of the data bus while the reselection 703 * was being negotiated. This enables us to determine which target did 704 * the reselect. 705 */ 706 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 707 if (selid & (selid - 1)) { 708 printf("%s: reselect with invalid selid %02x; " 709 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 710 SPC_BREAK(); 711 goto reset; 712 } 713 714 /* 715 * Search wait queue for disconnected cmd 716 * The list should be short, so I haven't bothered with 717 * any more sophisticated structures than a simple 718 * singly linked list. 719 */ 720 target = ffs(selid) - 1; 721 lun = message & 0x07; 722 TAILQ_FOREACH(acb, &sc->nexus_list, chain) { 723 periph = acb->xs->xs_periph; 724 if (periph->periph_target == target && 725 periph->periph_lun == lun) 726 break; 727 } 728 if (acb == NULL) { 729 printf("%s: reselect from target %d lun %d with no nexus; " 730 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 731 SPC_BREAK(); 732 goto abort; 733 } 734 735 /* Make this nexus active again. */ 736 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 737 sc->sc_state = SPC_CONNECTED; 738 sc->sc_nexus = acb; 739 ti = &sc->sc_tinfo[target]; 740 ti->lubusy |= (1 << lun); 741 spc_setsync(sc, ti); 742 743 if (acb->flags & ACB_RESET) 744 spc_sched_msgout(sc, SEND_DEV_RESET); 745 else if (acb->flags & ACB_ABORT) 746 spc_sched_msgout(sc, SEND_ABORT); 747 748 /* Do an implicit RESTORE POINTERS. */ 749 sc->sc_dp = acb->data_addr; 750 sc->sc_dleft = acb->data_length; 751 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 752 sc->sc_cleft = acb->scsipi_cmd_length; 753 754 return (0); 755 756 reset: 757 spc_sched_msgout(sc, SEND_DEV_RESET); 758 return (1); 759 760 abort: 761 spc_sched_msgout(sc, SEND_ABORT); 762 return (1); 763 } 764 765 /* 766 * Schedule a SCSI operation. This has now been pulled out of the interrupt 767 * handler so that we may call it from spc_scsi_cmd and spc_done. This may 768 * save us an unecessary interrupt just to get things going. Should only be 769 * called when state == SPC_IDLE and at bio pl. 770 */ 771 void 772 spc_sched(sc) 773 struct spc_softc *sc; 774 { 775 struct spc_acb *acb; 776 struct scsipi_periph *periph; 777 struct spc_tinfo *ti; 778 779 /* missing the hw, just return and wait for our hw */ 780 if (sc->sc_flags & SPC_INACTIVE) 781 return; 782 SPC_TRACE(("spc_sched ")); 783 /* 784 * Find first acb in ready queue that is for a target/lunit pair that 785 * is not busy. 786 */ 787 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 788 periph = acb->xs->xs_periph; 789 ti = &sc->sc_tinfo[periph->periph_target]; 790 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 791 SPC_MISC(("selecting %d:%d ", 792 periph->periph_target, periph->periph_lun)); 793 TAILQ_REMOVE(&sc->ready_list, acb, chain); 794 sc->sc_nexus = acb; 795 spc_select(sc, acb); 796 return; 797 } else 798 SPC_MISC(("%d:%d busy\n", 799 periph->periph_target, periph->periph_lun)); 800 } 801 SPC_MISC(("idle ")); 802 /* Nothing to start; just enable reselections and wait. */ 803 } 804 805 /* 806 * POST PROCESSING OF SCSI_CMD (usually current) 807 */ 808 void 809 spc_done(sc, acb) 810 struct spc_softc *sc; 811 struct spc_acb *acb; 812 { 813 struct scsipi_xfer *xs = acb->xs; 814 struct scsipi_periph *periph = xs->xs_periph; 815 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 816 817 SPC_TRACE(("spc_done ")); 818 819 if (xs->error == XS_NOERROR) { 820 if (acb->flags & ACB_ABORT) { 821 xs->error = XS_DRIVER_STUFFUP; 822 } else { 823 switch (acb->target_stat) { 824 case SCSI_CHECK: 825 /* First, save the return values */ 826 xs->resid = acb->data_length; 827 /* FALLTHROUGH */ 828 case SCSI_BUSY: 829 xs->status = acb->target_stat; 830 xs->error = XS_BUSY; 831 break; 832 case SCSI_OK: 833 xs->resid = acb->data_length; 834 break; 835 default: 836 xs->error = XS_DRIVER_STUFFUP; 837 #if SPC_DEBUG 838 printf("%s: spc_done: bad stat 0x%x\n", 839 sc->sc_dev.dv_xname, acb->target_stat); 840 #endif 841 break; 842 } 843 } 844 } 845 846 #if SPC_DEBUG 847 if ((spc_debug & SPC_SHOWMISC) != 0) { 848 if (xs->resid != 0) 849 printf("resid=%d ", xs->resid); 850 else 851 printf("error=%d\n", xs->error); 852 } 853 #endif 854 855 /* 856 * Remove the ACB from whatever queue it happens to be on. 857 */ 858 if (acb->flags & ACB_NEXUS) 859 ti->lubusy &= ~(1 << periph->periph_lun); 860 if (acb == sc->sc_nexus) { 861 sc->sc_nexus = NULL; 862 sc->sc_state = SPC_IDLE; 863 spc_sched(sc); 864 } else 865 spc_dequeue(sc, acb); 866 867 spc_free_acb(sc, acb, xs->xs_control); 868 ti->cmds++; 869 scsipi_done(xs); 870 } 871 872 void 873 spc_dequeue(sc, acb) 874 struct spc_softc *sc; 875 struct spc_acb *acb; 876 { 877 878 SPC_TRACE(("spc_dequeue ")); 879 if (acb->flags & ACB_NEXUS) 880 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 881 else 882 TAILQ_REMOVE(&sc->ready_list, acb, chain); 883 } 884 885 /* 886 * INTERRUPT/PROTOCOL ENGINE 887 */ 888 889 /* 890 * Precondition: 891 * The SCSI bus is already in the MSGI phase and there is a message byte 892 * on the bus, along with an asserted REQ signal. 893 */ 894 void 895 spc_msgin(sc) 896 struct spc_softc *sc; 897 { 898 bus_space_tag_t iot = sc->sc_iot; 899 bus_space_handle_t ioh = sc->sc_ioh; 900 int n; 901 u_int8_t msg; 902 903 SPC_TRACE(("spc_msgin ")); 904 905 if (sc->sc_prevphase == PH_MSGIN) { 906 /* This is a continuation of the previous message. */ 907 n = sc->sc_imp - sc->sc_imess; 908 goto nextbyte; 909 } 910 911 /* This is a new MESSAGE IN phase. Clean up our state. */ 912 sc->sc_flags &= ~SPC_DROP_MSGIN; 913 914 nextmsg: 915 n = 0; 916 sc->sc_imp = &sc->sc_imess[n]; 917 918 nextbyte: 919 /* 920 * Read a whole message, but don't ack the last byte. If we reject the 921 * message, we have to assert ATN during the message transfer phase 922 * itself. 923 */ 924 for (;;) { 925 #ifdef NO_MANUAL_XFER /* XXX */ 926 if (bus_space_read_1(iot, ioh, INTS) != 0) { 927 /* 928 * Target left MESSAGE IN, probably because it 929 * a) noticed our ATN signal, or 930 * b) ran out of messages. 931 */ 932 goto out; 933 } 934 #endif 935 /* If parity error, just dump everything on the floor. */ 936 if ((bus_space_read_1(iot, ioh, SERR) & 937 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) { 938 sc->sc_flags |= SPC_DROP_MSGIN; 939 spc_sched_msgout(sc, SEND_PARITY_ERROR); 940 } 941 942 #ifdef NO_MANUAL_XFER /* XXX */ 943 /* send TRANSFER command. */ 944 bus_space_write_1(iot, ioh, TCH, 0); 945 bus_space_write_1(iot, ioh, TCM, 0); 946 bus_space_write_1(iot, ioh, TCL, 1); 947 bus_space_write_1(iot, ioh, PCTL, 948 sc->sc_phase | PCTL_BFINT_ENAB); 949 #ifdef NEED_DREQ_ON_HARDWARE_XFER 950 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); 951 #else 952 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); 953 #endif 954 for (;;) { 955 if ((bus_space_read_1(iot, ioh, SSTS) & 956 SSTS_DREG_EMPTY) == 0) 957 break; 958 if (bus_space_read_1(iot, ioh, INTS) != 0) 959 goto out; 960 } 961 msg = bus_space_read_1(iot, ioh, DREG); 962 #else 963 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_ATN) != 0) 964 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 965 966 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 967 /* XXX needs timeout */ 968 if ((bus_space_read_1(iot, ioh, PSNS) & PH_MASK) 969 != PH_MSGIN) 970 /* 971 * Target left MESSAGE IN, probably because it 972 * a) noticed our ATN signal, or 973 * b) ran out of messages. 974 */ 975 goto out; 976 } 977 978 bus_space_write_1(iot, ioh, PCTL, PH_MSGIN); 979 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 980 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 981 continue; /* XXX needs timeout */ 982 msg = bus_space_read_1(iot, ioh, TEMP); 983 #endif 984 985 /* Gather incoming message bytes if needed. */ 986 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) { 987 if (n >= SPC_MAX_MSG_LEN) { 988 sc->sc_flags |= SPC_DROP_MSGIN; 989 spc_sched_msgout(sc, SEND_REJECT); 990 } else { 991 *sc->sc_imp++ = msg; 992 n++; 993 /* 994 * This testing is suboptimal, but most 995 * messages will be of the one byte variety, so 996 * it should not affect performance 997 * significantly. 998 */ 999 if (n == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1000 break; 1001 if (n == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1002 break; 1003 if (n >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1004 n == sc->sc_imess[1] + 2) 1005 break; 1006 } 1007 } 1008 /* 1009 * If we reach this spot we're either: 1010 * a) in the middle of a multi-byte message, or 1011 * b) dropping bytes. 1012 */ 1013 1014 #ifndef NO_MANUAL_XFER /* XXX */ 1015 /* Ack the last byte read. */ 1016 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1017 #endif 1018 } 1019 1020 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1021 1022 /* We now have a complete message. Parse it. */ 1023 switch (sc->sc_state) { 1024 struct spc_acb *acb; 1025 struct scsipi_periph *periph; 1026 struct spc_tinfo *ti; 1027 1028 case SPC_CONNECTED: 1029 SPC_ASSERT(sc->sc_nexus != NULL); 1030 acb = sc->sc_nexus; 1031 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1032 1033 switch (sc->sc_imess[0]) { 1034 case MSG_CMDCOMPLETE: 1035 if (sc->sc_dleft < 0) { 1036 periph = acb->xs->xs_periph; 1037 printf("%s: %d extra bytes from %d:%d\n", 1038 sc->sc_dev.dv_xname, -sc->sc_dleft, 1039 periph->periph_target, periph->periph_lun); 1040 sc->sc_dleft = 0; 1041 } 1042 acb->xs->resid = acb->data_length = sc->sc_dleft; 1043 sc->sc_state = SPC_CMDCOMPLETE; 1044 break; 1045 1046 case MSG_PARITY_ERROR: 1047 /* Resend the last message. */ 1048 spc_sched_msgout(sc, sc->sc_lastmsg); 1049 break; 1050 1051 case MSG_MESSAGE_REJECT: 1052 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1053 switch (sc->sc_lastmsg) { 1054 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1055 case SEND_IDENTIFY: 1056 ti->flags &= ~(DO_SYNC | DO_WIDE); 1057 ti->period = ti->offset = 0; 1058 spc_setsync(sc, ti); 1059 ti->width = 0; 1060 break; 1061 #endif 1062 #if SPC_USE_SYNCHRONOUS 1063 case SEND_SDTR: 1064 ti->flags &= ~DO_SYNC; 1065 ti->period = ti->offset = 0; 1066 spc_setsync(sc, ti); 1067 break; 1068 #endif 1069 #if SPC_USE_WIDE 1070 case SEND_WDTR: 1071 ti->flags &= ~DO_WIDE; 1072 ti->width = 0; 1073 break; 1074 #endif 1075 case SEND_INIT_DET_ERR: 1076 spc_sched_msgout(sc, SEND_ABORT); 1077 break; 1078 } 1079 break; 1080 1081 case MSG_NOOP: 1082 break; 1083 1084 case MSG_DISCONNECT: 1085 ti->dconns++; 1086 sc->sc_state = SPC_DISCONNECT; 1087 break; 1088 1089 case MSG_SAVEDATAPOINTER: 1090 acb->data_addr = sc->sc_dp; 1091 acb->data_length = sc->sc_dleft; 1092 break; 1093 1094 case MSG_RESTOREPOINTERS: 1095 sc->sc_dp = acb->data_addr; 1096 sc->sc_dleft = acb->data_length; 1097 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1098 sc->sc_cleft = acb->scsipi_cmd_length; 1099 break; 1100 1101 case MSG_EXTENDED: 1102 switch (sc->sc_imess[2]) { 1103 #if SPC_USE_SYNCHRONOUS 1104 case MSG_EXT_SDTR: 1105 if (sc->sc_imess[1] != 3) 1106 goto reject; 1107 ti->period = sc->sc_imess[3]; 1108 ti->offset = sc->sc_imess[4]; 1109 ti->flags &= ~DO_SYNC; 1110 if (ti->offset == 0) { 1111 } else if (ti->period < sc->sc_minsync || 1112 ti->period > sc->sc_maxsync || 1113 ti->offset > 8) { 1114 ti->period = ti->offset = 0; 1115 spc_sched_msgout(sc, SEND_SDTR); 1116 } else { 1117 scsipi_printaddr(acb->xs->xs_periph); 1118 printf("sync, offset %d, " 1119 "period %dnsec\n", 1120 ti->offset, ti->period * 4); 1121 } 1122 spc_setsync(sc, ti); 1123 break; 1124 #endif 1125 1126 #if SPC_USE_WIDE 1127 case MSG_EXT_WDTR: 1128 if (sc->sc_imess[1] != 2) 1129 goto reject; 1130 ti->width = sc->sc_imess[3]; 1131 ti->flags &= ~DO_WIDE; 1132 if (ti->width == 0) { 1133 } else if (ti->width > SPC_MAX_WIDTH) { 1134 ti->width = 0; 1135 spc_sched_msgout(sc, SEND_WDTR); 1136 } else { 1137 scsipi_printaddr(acb->xs->xs_periph); 1138 printf("wide, width %d\n", 1139 1 << (3 + ti->width)); 1140 } 1141 break; 1142 #endif 1143 1144 default: 1145 printf("%s: unrecognized MESSAGE EXTENDED; " 1146 "sending REJECT\n", sc->sc_dev.dv_xname); 1147 SPC_BREAK(); 1148 goto reject; 1149 } 1150 break; 1151 1152 default: 1153 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1154 sc->sc_dev.dv_xname); 1155 SPC_BREAK(); 1156 reject: 1157 spc_sched_msgout(sc, SEND_REJECT); 1158 break; 1159 } 1160 break; 1161 1162 case SPC_RESELECTED: 1163 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1164 printf("%s: reselect without IDENTIFY; " 1165 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1166 SPC_BREAK(); 1167 goto reset; 1168 } 1169 1170 (void) spc_reselect(sc, sc->sc_imess[0]); 1171 break; 1172 1173 default: 1174 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1175 sc->sc_dev.dv_xname); 1176 SPC_BREAK(); 1177 reset: 1178 spc_sched_msgout(sc, SEND_DEV_RESET); 1179 break; 1180 1181 #ifdef notdef 1182 abort: 1183 spc_sched_msgout(sc, SEND_ABORT); 1184 break; 1185 #endif 1186 } 1187 1188 #ifndef NO_MANUAL_XFER /* XXX */ 1189 /* Ack the last message byte. */ 1190 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1191 #endif 1192 1193 /* Go get the next message, if any. */ 1194 goto nextmsg; 1195 1196 out: 1197 #ifndef NO_MANUAL_XFER /* XXX */ 1198 /* Ack the last message byte. */ 1199 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1200 #endif 1201 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1202 } 1203 1204 /* 1205 * Send the highest priority, scheduled message. 1206 */ 1207 void 1208 spc_msgout(sc) 1209 struct spc_softc *sc; 1210 { 1211 bus_space_tag_t iot = sc->sc_iot; 1212 bus_space_handle_t ioh = sc->sc_ioh; 1213 #if SPC_USE_SYNCHRONOUS 1214 struct spc_tinfo *ti; 1215 #endif 1216 int n; 1217 1218 SPC_TRACE(("spc_msgout ")); 1219 1220 if (sc->sc_prevphase == PH_MSGOUT) { 1221 if (sc->sc_omp == sc->sc_omess) { 1222 /* 1223 * This is a retransmission. 1224 * 1225 * We get here if the target stayed in MESSAGE OUT 1226 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1227 * that all of the previously transmitted messages must 1228 * be sent again, in the same order. Therefore, we 1229 * requeue all the previously transmitted messages, and 1230 * start again from the top. Our simple priority 1231 * scheme keeps the messages in the right order. 1232 */ 1233 SPC_MISC(("retransmitting ")); 1234 sc->sc_msgpriq |= sc->sc_msgoutq; 1235 /* 1236 * Set ATN. If we're just sending a trivial 1-byte 1237 * message, we'll clear ATN later on anyway. 1238 */ 1239 bus_space_write_1(iot, ioh, SCMD, 1240 SCMD_SET_ATN); /* XXX? */ 1241 } else { 1242 /* This is a continuation of the previous message. */ 1243 n = sc->sc_omp - sc->sc_omess; 1244 goto nextbyte; 1245 } 1246 } 1247 1248 /* No messages transmitted so far. */ 1249 sc->sc_msgoutq = 0; 1250 sc->sc_lastmsg = 0; 1251 1252 nextmsg: 1253 /* Pick up highest priority message. */ 1254 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1255 sc->sc_msgpriq &= ~sc->sc_currmsg; 1256 sc->sc_msgoutq |= sc->sc_currmsg; 1257 1258 /* Build the outgoing message data. */ 1259 switch (sc->sc_currmsg) { 1260 case SEND_IDENTIFY: 1261 SPC_ASSERT(sc->sc_nexus != NULL); 1262 sc->sc_omess[0] = 1263 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1264 n = 1; 1265 break; 1266 1267 #if SPC_USE_SYNCHRONOUS 1268 case SEND_SDTR: 1269 SPC_ASSERT(sc->sc_nexus != NULL); 1270 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1271 sc->sc_omess[4] = MSG_EXTENDED; 1272 sc->sc_omess[3] = MSG_EXT_SDTR_LEN; 1273 sc->sc_omess[2] = MSG_EXT_SDTR; 1274 sc->sc_omess[1] = ti->period >> 2; 1275 sc->sc_omess[0] = ti->offset; 1276 n = 5; 1277 break; 1278 #endif 1279 1280 #if SPC_USE_WIDE 1281 case SEND_WDTR: 1282 SPC_ASSERT(sc->sc_nexus != NULL); 1283 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1284 sc->sc_omess[3] = MSG_EXTENDED; 1285 sc->sc_omess[2] = MSG_EXT_WDTR_LEN; 1286 sc->sc_omess[1] = MSG_EXT_WDTR; 1287 sc->sc_omess[0] = ti->width; 1288 n = 4; 1289 break; 1290 #endif 1291 1292 case SEND_DEV_RESET: 1293 sc->sc_flags |= SPC_ABORTING; 1294 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1295 n = 1; 1296 break; 1297 1298 case SEND_REJECT: 1299 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1300 n = 1; 1301 break; 1302 1303 case SEND_PARITY_ERROR: 1304 sc->sc_omess[0] = MSG_PARITY_ERROR; 1305 n = 1; 1306 break; 1307 1308 case SEND_INIT_DET_ERR: 1309 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1310 n = 1; 1311 break; 1312 1313 case SEND_ABORT: 1314 sc->sc_flags |= SPC_ABORTING; 1315 sc->sc_omess[0] = MSG_ABORT; 1316 n = 1; 1317 break; 1318 1319 default: 1320 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1321 sc->sc_dev.dv_xname); 1322 SPC_BREAK(); 1323 sc->sc_omess[0] = MSG_NOOP; 1324 n = 1; 1325 break; 1326 } 1327 sc->sc_omp = &sc->sc_omess[n]; 1328 1329 nextbyte: 1330 /* Send message bytes. */ 1331 /* send TRANSFER command. */ 1332 bus_space_write_1(iot, ioh, TCH, n >> 16); 1333 bus_space_write_1(iot, ioh, TCM, n >> 8); 1334 bus_space_write_1(iot, ioh, TCL, n); 1335 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1336 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1337 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1338 #else 1339 bus_space_write_1(iot, ioh, SCMD, 1340 SCMD_XFR | SCMD_PROG_XFR); 1341 #endif 1342 for (;;) { 1343 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1344 break; 1345 if (bus_space_read_1(iot, ioh, INTS) != 0) 1346 goto out; 1347 } 1348 for (;;) { 1349 #if 0 1350 for (;;) { 1351 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1352 break; 1353 /* Wait for REQINIT. XXX Need timeout. */ 1354 } 1355 #endif 1356 if (bus_space_read_1(iot, ioh, INTS) != 0) { 1357 /* 1358 * Target left MESSAGE OUT, possibly to reject 1359 * our message. 1360 * 1361 * If this is the last message being sent, then we 1362 * deassert ATN, since either the target is going to 1363 * ignore this message, or it's going to ask for a 1364 * retransmission via MESSAGE PARITY ERROR (in which 1365 * case we reassert ATN anyway). 1366 */ 1367 #if 0 1368 if (sc->sc_msgpriq == 0) 1369 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1370 #endif 1371 goto out; 1372 } 1373 1374 #if 0 1375 /* Clear ATN before last byte if this is the last message. */ 1376 if (n == 1 && sc->sc_msgpriq == 0) 1377 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1378 #endif 1379 1380 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0) 1381 ; 1382 /* Send message byte. */ 1383 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp); 1384 --n; 1385 /* Keep track of the last message we've sent any bytes of. */ 1386 sc->sc_lastmsg = sc->sc_currmsg; 1387 #if 0 1388 /* Wait for ACK to be negated. XXX Need timeout. */ 1389 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1390 ; 1391 #endif 1392 1393 if (n == 0) 1394 break; 1395 } 1396 1397 /* We get here only if the entire message has been transmitted. */ 1398 if (sc->sc_msgpriq != 0) { 1399 /* There are more outgoing messages. */ 1400 goto nextmsg; 1401 } 1402 1403 /* 1404 * The last message has been transmitted. We need to remember the last 1405 * message transmitted (in case the target switches to MESSAGE IN phase 1406 * and sends a MESSAGE REJECT), and the list of messages transmitted 1407 * this time around (in case the target stays in MESSAGE OUT phase to 1408 * request a retransmit). 1409 */ 1410 1411 out: 1412 /* Disable REQ/ACK protocol. */ 1413 return; 1414 } 1415 1416 /* 1417 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc 1418 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1419 * and ACK deasserted (i.e. waiting for a data byte) 1420 * 1421 * This new revision has been optimized (I tried) to make the common case fast, 1422 * and the rarer cases (as a result) somewhat more comlex 1423 */ 1424 int 1425 spc_dataout_pio(sc, p, n) 1426 struct spc_softc *sc; 1427 u_char *p; 1428 int n; 1429 { 1430 bus_space_tag_t iot = sc->sc_iot; 1431 bus_space_handle_t ioh = sc->sc_ioh; 1432 u_char intstat = 0; 1433 int out = 0; 1434 #define DOUTAMOUNT 8 /* Full FIFO */ 1435 1436 SPC_TRACE(("spc_dataout_pio ")); 1437 /* send TRANSFER command. */ 1438 bus_space_write_1(iot, ioh, TCH, n >> 16); 1439 bus_space_write_1(iot, ioh, TCM, n >> 8); 1440 bus_space_write_1(iot, ioh, TCL, n); 1441 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1442 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1443 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1444 #else 1445 bus_space_write_1(iot, ioh, SCMD, 1446 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1447 #endif 1448 for (;;) { 1449 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1450 break; 1451 if (bus_space_read_1(iot, ioh, INTS) != 0) 1452 break; 1453 } 1454 1455 /* 1456 * I have tried to make the main loop as tight as possible. This 1457 * means that some of the code following the loop is a bit more 1458 * complex than otherwise. 1459 */ 1460 while (n > 0) { 1461 int xfer; 1462 1463 for (;;) { 1464 intstat = bus_space_read_1(iot, ioh, INTS); 1465 /* Wait till buffer is empty. */ 1466 if ((bus_space_read_1(iot, ioh, SSTS) & 1467 SSTS_DREG_EMPTY) != 0) 1468 break; 1469 /* Break on interrupt. */ 1470 if (intstat != 0) 1471 goto phasechange; 1472 } 1473 1474 xfer = min(DOUTAMOUNT, n); 1475 1476 SPC_MISC(("%d> ", xfer)); 1477 1478 n -= xfer; 1479 out += xfer; 1480 1481 bus_space_write_multi_1(iot, ioh, DREG, p, xfer); 1482 p += xfer; 1483 } 1484 1485 if (out == 0) { 1486 for (;;) { 1487 if (bus_space_read_1(iot, ioh, INTS) != 0) 1488 break; 1489 } 1490 SPC_MISC(("extra data ")); 1491 } else { 1492 /* See the bytes off chip */ 1493 for (;;) { 1494 /* Wait till buffer is empty. */ 1495 if ((bus_space_read_1(iot, ioh, SSTS) & 1496 SSTS_DREG_EMPTY) != 0) 1497 break; 1498 intstat = bus_space_read_1(iot, ioh, INTS); 1499 /* Break on interrupt. */ 1500 if (intstat != 0) 1501 goto phasechange; 1502 } 1503 } 1504 1505 phasechange: 1506 /* Stop the FIFO data path. */ 1507 1508 if (intstat != 0) { 1509 /* Some sort of phase change. */ 1510 int amount; 1511 1512 amount = (bus_space_read_1(iot, ioh, TCH) << 16) | 1513 (bus_space_read_1(iot, ioh, TCM) << 8) | 1514 bus_space_read_1(iot, ioh, TCL); 1515 if (amount > 0) { 1516 out -= amount; 1517 SPC_MISC(("+%d ", amount)); 1518 } 1519 } 1520 1521 return out; 1522 } 1523 1524 /* 1525 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc 1526 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1527 * and ACK deasserted (i.e. at least one byte is ready). 1528 * 1529 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1530 * transferred. This, is OK for fast targets, but not so smart for slow 1531 * targets which don't disconnect or for huge transfers. 1532 */ 1533 int 1534 spc_datain_pio(sc, p, n) 1535 struct spc_softc *sc; 1536 u_char *p; 1537 int n; 1538 { 1539 bus_space_tag_t iot = sc->sc_iot; 1540 bus_space_handle_t ioh = sc->sc_ioh; 1541 int in = 0; 1542 u_int8_t intstat, sstat; 1543 #define DINAMOUNT 8 /* Full FIFO */ 1544 1545 SPC_TRACE(("spc_datain_pio ")); 1546 /* send TRANSFER command. */ 1547 bus_space_write_1(iot, ioh, TCH, n >> 16); 1548 bus_space_write_1(iot, ioh, TCM, n >> 8); 1549 bus_space_write_1(iot, ioh, TCL, n); 1550 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1551 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1552 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1553 #else 1554 bus_space_write_1(iot, ioh, SCMD, 1555 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1556 #endif 1557 for (;;) { 1558 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1559 break; 1560 if (bus_space_read_1(iot, ioh, INTS) != 0) 1561 goto phasechange; 1562 } 1563 1564 /* 1565 * We leave this loop if one or more of the following is true: 1566 * a) phase != PH_DATAIN && FIFOs are empty 1567 * b) reset has occurred or busfree is detected. 1568 */ 1569 while (n > 0) { 1570 int xfer; 1571 1572 /* Wait for fifo half full or phase mismatch */ 1573 for (;;) { 1574 /* XXX needs timeout */ 1575 intstat = bus_space_read_1(iot, ioh, INTS); 1576 sstat = bus_space_read_1(iot, ioh, SSTS); 1577 if (intstat != 0 || 1578 (sstat & SSTS_DREG_EMPTY) == 0) 1579 break; 1580 } 1581 1582 if (sstat & SSTS_DREG_FULL) { 1583 xfer = DINAMOUNT; 1584 n -= xfer; 1585 in += xfer; 1586 bus_space_read_multi_1(iot, ioh, DREG, p, xfer); 1587 p += xfer; 1588 } 1589 while (n > 0 && 1590 (bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) == 0) { 1591 n--; 1592 in++; 1593 *p++ = bus_space_read_1(iot, ioh, DREG); 1594 } 1595 1596 if (intstat != 0) 1597 goto phasechange; 1598 } 1599 1600 /* 1601 * Some SCSI-devices are rude enough to transfer more data than what 1602 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1603 * requested 512. Test for progress, i.e. real transfers. If no real 1604 * transfers have been performed (n is probably already zero) and the 1605 * FIFO is not empty, waste some bytes.... 1606 */ 1607 if (in == 0) { 1608 for (;;) { 1609 /* XXX needs timeout */ 1610 if (bus_space_read_1(iot, ioh, INTS) != 0) 1611 break; 1612 } 1613 SPC_MISC(("extra data ")); 1614 } 1615 1616 phasechange: 1617 /* Stop the FIFO data path. */ 1618 1619 return in; 1620 } 1621 1622 /* 1623 * Catch an interrupt from the adaptor 1624 */ 1625 /* 1626 * This is the workhorse routine of the driver. 1627 * Deficiencies (for now): 1628 * 1) always uses programmed I/O 1629 */ 1630 int 1631 spc_intr(arg) 1632 void *arg; 1633 { 1634 struct spc_softc *sc = arg; 1635 bus_space_tag_t iot = sc->sc_iot; 1636 bus_space_handle_t ioh = sc->sc_ioh; 1637 u_char ints; 1638 struct spc_acb *acb; 1639 struct scsipi_periph *periph; 1640 struct spc_tinfo *ti; 1641 int n; 1642 1643 /* 1644 * Disable interrupt. 1645 */ 1646 bus_space_write_1(iot, ioh, SCTL, 1647 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB); 1648 1649 SPC_TRACE(("spc_intr ")); 1650 1651 ints = bus_space_read_1(iot, ioh, INTS); 1652 if (ints == 0) 1653 goto out; 1654 1655 if (sc->sc_dma_done != NULL && 1656 sc->sc_state == SPC_CONNECTED && 1657 (sc->sc_flags & SPC_DOINGDMA) != 0 && 1658 (sc->sc_phase == PH_DATAOUT || sc->sc_phase == PH_DATAIN)) { 1659 (*sc->sc_dma_done)(sc); 1660 } 1661 1662 loop: 1663 /* 1664 * Loop until transfer completion. 1665 */ 1666 /* 1667 * First check for abnormal conditions, such as reset. 1668 */ 1669 #ifdef x68k /* XXX? */ 1670 while ((ints = bus_space_read_1(iot, ioh, INTS)) == 0) 1671 delay(1); 1672 SPC_MISC(("ints = 0x%x ", ints)); 1673 #else 1674 ints = bus_space_read_1(iot, ioh, INTS); 1675 SPC_MISC(("ints = 0x%x ", ints)); 1676 #endif 1677 1678 if ((ints & INTS_RST) != 0) { 1679 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1680 goto reset; 1681 } 1682 1683 /* 1684 * Check for less serious errors. 1685 */ 1686 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR)) 1687 != 0) { 1688 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1689 if (sc->sc_prevphase == PH_MSGIN) { 1690 sc->sc_flags |= SPC_DROP_MSGIN; 1691 spc_sched_msgout(sc, SEND_PARITY_ERROR); 1692 } else 1693 spc_sched_msgout(sc, SEND_INIT_DET_ERR); 1694 } 1695 1696 /* 1697 * If we're not already busy doing something test for the following 1698 * conditions: 1699 * 1) We have been reselected by something 1700 * 2) We have selected something successfully 1701 * 3) Our selection process has timed out 1702 * 4) This is really a bus free interrupt just to get a new command 1703 * going? 1704 * 5) Spurious interrupt? 1705 */ 1706 switch (sc->sc_state) { 1707 case SPC_IDLE: 1708 case SPC_SELECTING: 1709 SPC_MISC(("ints:0x%02x ", ints)); 1710 1711 if ((ints & INTS_SEL) != 0) { 1712 /* 1713 * We don't currently support target mode. 1714 */ 1715 printf("%s: target mode selected; going to BUS FREE\n", 1716 sc->sc_dev.dv_xname); 1717 1718 goto sched; 1719 } else if ((ints & INTS_RESEL) != 0) { 1720 SPC_MISC(("reselected ")); 1721 1722 /* 1723 * If we're trying to select a target ourselves, 1724 * push our command back into the ready list. 1725 */ 1726 if (sc->sc_state == SPC_SELECTING) { 1727 SPC_MISC(("backoff selector ")); 1728 SPC_ASSERT(sc->sc_nexus != NULL); 1729 acb = sc->sc_nexus; 1730 sc->sc_nexus = NULL; 1731 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1732 } 1733 1734 /* Save reselection ID. */ 1735 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP); 1736 1737 sc->sc_state = SPC_RESELECTED; 1738 } else if ((ints & INTS_CMD_DONE) != 0) { 1739 SPC_MISC(("selected ")); 1740 1741 /* 1742 * We have selected a target. Things to do: 1743 * a) Determine what message(s) to send. 1744 * b) Verify that we're still selecting the target. 1745 * c) Mark device as busy. 1746 */ 1747 if (sc->sc_state != SPC_SELECTING) { 1748 printf("%s: selection out while idle; " 1749 "resetting\n", sc->sc_dev.dv_xname); 1750 SPC_BREAK(); 1751 goto reset; 1752 } 1753 SPC_ASSERT(sc->sc_nexus != NULL); 1754 acb = sc->sc_nexus; 1755 periph = acb->xs->xs_periph; 1756 ti = &sc->sc_tinfo[periph->periph_target]; 1757 1758 sc->sc_msgpriq = SEND_IDENTIFY; 1759 if (acb->flags & ACB_RESET) 1760 sc->sc_msgpriq |= SEND_DEV_RESET; 1761 else if (acb->flags & ACB_ABORT) 1762 sc->sc_msgpriq |= SEND_ABORT; 1763 else { 1764 #if SPC_USE_SYNCHRONOUS 1765 if ((ti->flags & DO_SYNC) != 0) 1766 sc->sc_msgpriq |= SEND_SDTR; 1767 #endif 1768 #if SPC_USE_WIDE 1769 if ((ti->flags & DO_WIDE) != 0) 1770 sc->sc_msgpriq |= SEND_WDTR; 1771 #endif 1772 } 1773 1774 acb->flags |= ACB_NEXUS; 1775 ti->lubusy |= (1 << periph->periph_lun); 1776 1777 /* Do an implicit RESTORE POINTERS. */ 1778 sc->sc_dp = acb->data_addr; 1779 sc->sc_dleft = acb->data_length; 1780 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1781 sc->sc_cleft = acb->scsipi_cmd_length; 1782 1783 /* On our first connection, schedule a timeout. */ 1784 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1785 callout_reset(&acb->xs->xs_callout, 1786 mstohz(acb->timeout), spc_timeout, acb); 1787 1788 sc->sc_state = SPC_CONNECTED; 1789 } else if ((ints & INTS_TIMEOUT) != 0) { 1790 SPC_MISC(("selection timeout ")); 1791 1792 if (sc->sc_state != SPC_SELECTING) { 1793 printf("%s: selection timeout while idle; " 1794 "resetting\n", sc->sc_dev.dv_xname); 1795 SPC_BREAK(); 1796 goto reset; 1797 } 1798 SPC_ASSERT(sc->sc_nexus != NULL); 1799 acb = sc->sc_nexus; 1800 1801 delay(250); 1802 1803 acb->xs->error = XS_SELTIMEOUT; 1804 goto finish; 1805 } else { 1806 if (sc->sc_state != SPC_IDLE) { 1807 printf("%s: BUS FREE while not idle; " 1808 "state=%d\n", 1809 sc->sc_dev.dv_xname, sc->sc_state); 1810 SPC_BREAK(); 1811 goto out; 1812 } 1813 1814 goto sched; 1815 } 1816 1817 /* 1818 * Turn off selection stuff, and prepare to catch bus free 1819 * interrupts, parity errors, and phase changes. 1820 */ 1821 1822 sc->sc_flags = 0; 1823 sc->sc_prevphase = PH_INVALID; 1824 goto dophase; 1825 } 1826 1827 if ((ints & INTS_DISCON) != 0) { 1828 /* We've gone to BUS FREE phase. */ 1829 /* disable disconnect interrupt */ 1830 bus_space_write_1(iot, ioh, PCTL, 1831 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB); 1832 /* XXX reset interrput */ 1833 bus_space_write_1(iot, ioh, INTS, ints); 1834 1835 switch (sc->sc_state) { 1836 case SPC_RESELECTED: 1837 goto sched; 1838 1839 case SPC_CONNECTED: 1840 SPC_ASSERT(sc->sc_nexus != NULL); 1841 acb = sc->sc_nexus; 1842 1843 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1844 if (sc->sc_prevphase == PH_MSGOUT) { 1845 /* 1846 * If the target went to BUS FREE phase during 1847 * or immediately after sending a SDTR or WDTR 1848 * message, disable negotiation. 1849 */ 1850 periph = acb->xs->xs_periph; 1851 ti = &sc->sc_tinfo[periph->periph_target]; 1852 switch (sc->sc_lastmsg) { 1853 #if SPC_USE_SYNCHRONOUS 1854 case SEND_SDTR: 1855 ti->flags &= ~DO_SYNC; 1856 ti->period = ti->offset = 0; 1857 break; 1858 #endif 1859 #if SPC_USE_WIDE 1860 case SEND_WDTR: 1861 ti->flags &= ~DO_WIDE; 1862 ti->width = 0; 1863 break; 1864 #endif 1865 } 1866 } 1867 #endif 1868 1869 if ((sc->sc_flags & SPC_ABORTING) == 0) { 1870 /* 1871 * Section 5.1.1 of the SCSI 2 spec suggests 1872 * issuing a REQUEST SENSE following an 1873 * unexpected disconnect. Some devices go into 1874 * a contingent allegiance condition when 1875 * disconnecting, and this is necessary to 1876 * clean up their state. 1877 */ 1878 printf("%s: unexpected disconnect; " 1879 "sending REQUEST SENSE\n", 1880 sc->sc_dev.dv_xname); 1881 SPC_BREAK(); 1882 acb->target_stat = SCSI_CHECK; 1883 acb->xs->error = XS_NOERROR; 1884 goto finish; 1885 } 1886 1887 acb->xs->error = XS_DRIVER_STUFFUP; 1888 goto finish; 1889 1890 case SPC_DISCONNECT: 1891 SPC_ASSERT(sc->sc_nexus != NULL); 1892 acb = sc->sc_nexus; 1893 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1894 sc->sc_nexus = NULL; 1895 goto sched; 1896 1897 case SPC_CMDCOMPLETE: 1898 SPC_ASSERT(sc->sc_nexus != NULL); 1899 acb = sc->sc_nexus; 1900 goto finish; 1901 } 1902 } 1903 else if ((ints & INTS_CMD_DONE) != 0 && 1904 sc->sc_prevphase == PH_MSGIN && 1905 sc->sc_state != SPC_CONNECTED) 1906 goto out; 1907 1908 dophase: 1909 #if 0 1910 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 1911 /* Wait for REQINIT. */ 1912 goto out; 1913 } 1914 #else 1915 bus_space_write_1(iot, ioh, INTS, ints); 1916 ints = 0; 1917 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 1918 delay(1); /* need timeout XXX */ 1919 #endif 1920 1921 /* 1922 * State transition. 1923 */ 1924 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK; 1925 #if 0 1926 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase); 1927 #endif 1928 1929 SPC_MISC(("phase=%d\n", sc->sc_phase)); 1930 switch (sc->sc_phase) { 1931 case PH_MSGOUT: 1932 if (sc->sc_state != SPC_CONNECTED && 1933 sc->sc_state != SPC_RESELECTED) 1934 break; 1935 spc_msgout(sc); 1936 sc->sc_prevphase = PH_MSGOUT; 1937 goto loop; 1938 1939 case PH_MSGIN: 1940 if (sc->sc_state != SPC_CONNECTED && 1941 sc->sc_state != SPC_RESELECTED) 1942 break; 1943 spc_msgin(sc); 1944 sc->sc_prevphase = PH_MSGIN; 1945 goto loop; 1946 1947 case PH_CMD: 1948 if (sc->sc_state != SPC_CONNECTED) 1949 break; 1950 #if SPC_DEBUG 1951 if ((spc_debug & SPC_SHOWMISC) != 0) { 1952 SPC_ASSERT(sc->sc_nexus != NULL); 1953 acb = sc->sc_nexus; 1954 printf("cmd=0x%02x+%d ", 1955 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length - 1); 1956 } 1957 #endif 1958 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 1959 sc->sc_cp += n; 1960 sc->sc_cleft -= n; 1961 sc->sc_prevphase = PH_CMD; 1962 goto loop; 1963 1964 case PH_DATAOUT: 1965 if (sc->sc_state != SPC_CONNECTED) 1966 break; 1967 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft)); 1968 if (sc->sc_dma_start != NULL && 1969 sc->sc_dleft > SPC_MIN_DMA_LEN) { 1970 (*sc->sc_dma_start)(sc, sc->sc_dp, sc->sc_dleft, 0); 1971 sc->sc_prevphase = PH_DATAOUT; 1972 goto out; 1973 } 1974 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 1975 sc->sc_dp += n; 1976 sc->sc_dleft -= n; 1977 sc->sc_prevphase = PH_DATAOUT; 1978 goto loop; 1979 1980 case PH_DATAIN: 1981 if (sc->sc_state != SPC_CONNECTED) 1982 break; 1983 SPC_MISC(("datain ")); 1984 if (sc->sc_dma_start != NULL && 1985 sc->sc_dleft > SPC_MIN_DMA_LEN) { 1986 (*sc->sc_dma_start)(sc, sc->sc_dp, sc->sc_dleft, 1); 1987 sc->sc_prevphase = PH_DATAIN; 1988 goto out; 1989 } 1990 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 1991 sc->sc_dp += n; 1992 sc->sc_dleft -= n; 1993 sc->sc_prevphase = PH_DATAIN; 1994 goto loop; 1995 1996 case PH_STAT: 1997 if (sc->sc_state != SPC_CONNECTED) 1998 break; 1999 SPC_ASSERT(sc->sc_nexus != NULL); 2000 acb = sc->sc_nexus; 2001 2002 #ifdef NO_MANUAL_XFER 2003 spc_datain_pio(sc, &acb->target_stat, 1); 2004 #else 2005 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_ATN) != 0) 2006 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 2007 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 2008 continue; /* XXX needs timeout */ 2009 bus_space_write_1(iot, ioh, PCTL, PH_STAT); 2010 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 2011 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 2012 continue; /* XXX needs timeout */ 2013 acb->target_stat = bus_space_read_1(iot, ioh, TEMP); 2014 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 2015 #endif 2016 2017 SPC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2018 sc->sc_prevphase = PH_STAT; 2019 goto loop; 2020 } 2021 2022 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2023 SPC_BREAK(); 2024 reset: 2025 spc_init(sc); 2026 return 1; 2027 2028 finish: 2029 callout_stop(&acb->xs->xs_callout); 2030 bus_space_write_1(iot, ioh, INTS, ints); 2031 ints = 0; 2032 spc_done(sc, acb); 2033 goto out; 2034 2035 sched: 2036 sc->sc_state = SPC_IDLE; 2037 spc_sched(sc); 2038 goto out; 2039 2040 out: 2041 if (ints) 2042 bus_space_write_1(iot, ioh, INTS, ints); 2043 bus_space_write_1(iot, ioh, SCTL, 2044 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB); 2045 return 1; 2046 } 2047 2048 void 2049 spc_abort(sc, acb) 2050 struct spc_softc *sc; 2051 struct spc_acb *acb; 2052 { 2053 2054 /* 2 secs for the abort */ 2055 acb->timeout = SPC_ABORT_TIMEOUT; 2056 acb->flags |= ACB_ABORT; 2057 2058 if (acb == sc->sc_nexus) { 2059 /* 2060 * If we're still selecting, the message will be scheduled 2061 * after selection is complete. 2062 */ 2063 if (sc->sc_state == SPC_CONNECTED) 2064 spc_sched_msgout(sc, SEND_ABORT); 2065 } else { 2066 spc_dequeue(sc, acb); 2067 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2068 if (sc->sc_state == SPC_IDLE) 2069 spc_sched(sc); 2070 } 2071 } 2072 2073 void 2074 spc_timeout(arg) 2075 void *arg; 2076 { 2077 struct spc_acb *acb = arg; 2078 struct scsipi_xfer *xs = acb->xs; 2079 struct scsipi_periph *periph = xs->xs_periph; 2080 struct spc_softc *sc; 2081 int s; 2082 2083 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 2084 scsipi_printaddr(periph); 2085 printf("timed out"); 2086 2087 s = splbio(); 2088 2089 if (acb->flags & ACB_ABORT) { 2090 /* abort timed out */ 2091 printf(" AGAIN\n"); 2092 /* XXX Must reset! */ 2093 } else { 2094 /* abort the operation that has timed out */ 2095 printf("\n"); 2096 acb->xs->error = XS_TIMEOUT; 2097 spc_abort(sc, acb); 2098 } 2099 2100 splx(s); 2101 } 2102 2103 #ifdef SPC_DEBUG 2104 /* 2105 * The following functions are mostly used for debugging purposes, either 2106 * directly called from the driver or from the kernel debugger. 2107 */ 2108 2109 void 2110 spc_show_scsi_cmd(acb) 2111 struct spc_acb *acb; 2112 { 2113 u_char *b = (u_char *)&acb->scsipi_cmd; 2114 int i; 2115 2116 scsipi_printaddr(acb->xs->xs_periph); 2117 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2118 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2119 if (i) 2120 printf(","); 2121 printf("%x", b[i]); 2122 } 2123 printf("\n"); 2124 } else 2125 printf("RESET\n"); 2126 } 2127 2128 void 2129 spc_print_acb(acb) 2130 struct spc_acb *acb; 2131 { 2132 2133 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2134 printf(" dp=%p dleft=%d target_stat=%x\n", 2135 acb->data_addr, acb->data_length, acb->target_stat); 2136 spc_show_scsi_cmd(acb); 2137 } 2138 2139 void 2140 spc_print_active_acb() 2141 { 2142 struct spc_acb *acb; 2143 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */ 2144 2145 printf("ready list:\n"); 2146 TAILQ_FOREACH(acb, &sc->ready_list, chain) 2147 spc_print_acb(acb); 2148 printf("nexus:\n"); 2149 if (sc->sc_nexus != NULL) 2150 spc_print_acb(sc->sc_nexus); 2151 printf("nexus list:\n"); 2152 TAILQ_FOREACH(acb, &sc->nexus_list, chain) 2153 spc_print_acb(acb); 2154 } 2155 2156 void 2157 spc_dump89352(sc) 2158 struct spc_softc *sc; 2159 { 2160 bus_space_tag_t iot = sc->sc_iot; 2161 bus_space_handle_t ioh = sc->sc_ioh; 2162 2163 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n", 2164 bus_space_read_1(iot, ioh, BDID), 2165 bus_space_read_1(iot, ioh, SCTL), 2166 bus_space_read_1(iot, ioh, SCMD), 2167 bus_space_read_1(iot, ioh, TMOD)); 2168 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n", 2169 bus_space_read_1(iot, ioh, INTS), 2170 bus_space_read_1(iot, ioh, PSNS), 2171 bus_space_read_1(iot, ioh, SSTS), 2172 bus_space_read_1(iot, ioh, SERR), 2173 bus_space_read_1(iot, ioh, PCTL)); 2174 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n", 2175 bus_space_read_1(iot, ioh, MBC), 2176 #if 0 2177 bus_space_read_1(iot, ioh, DREG), 2178 #else 2179 0, 2180 #endif 2181 bus_space_read_1(iot, ioh, TEMP), 2182 bus_space_read_1(iot, ioh, TCH), 2183 bus_space_read_1(iot, ioh, TCM)); 2184 printf(" TCL=%x EXBF=%x\n", 2185 bus_space_read_1(iot, ioh, TCL), 2186 bus_space_read_1(iot, ioh, EXBF)); 2187 } 2188 2189 void 2190 spc_dump_driver(sc) 2191 struct spc_softc *sc; 2192 { 2193 struct spc_tinfo *ti; 2194 int i; 2195 2196 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2197 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2198 "currmsg=%x\n", sc->sc_state, sc->sc_imess[0], 2199 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2200 for (i = 0; i < 7; i++) { 2201 ti = &sc->sc_tinfo[i]; 2202 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2203 i, ti->cmds, ti->dconns, ti->touts); 2204 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2205 } 2206 } 2207 #endif 2208
Indexes created Thu Sep 25 16:09:42 GMT 2025