mb89352.c revision 1.8 1 /* $NetBSD: mb89352.c,v 1.8 2001/07/07 16:13:49 thorpej Exp $ */
2 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */
3
4 #ifdef DDB
5 #define integrate
6 #else
7 #define integrate __inline static
8 #endif
9
10 /*-
11 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc.
12 * All rights reserved.
13 *
14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by Charles M. Hannum.
28 * 4. The name of the author may not be used to endorse or promote products
29 * derived from this software without specific prior written permission.
30 *
31 * Copyright (c) 1994 Jarle Greipsland
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
47 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
48 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
49 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
51 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
53 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
54 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
55 * POSSIBILITY OF SUCH DAMAGE.
56 */
57 /*
58 * [NetBSD for NEC PC-98 series]
59 * Copyright (c) 1996, 1997, 1998
60 * NetBSD/pc98 porting staff. All rights reserved.
61 * Copyright (c) 1996, 1997, 1998
62 * Kouichi Matsuda. All rights reserved.
63 */
64
65 /*
66 * Acknowledgements: Many of the algorithms used in this driver are
67 * inspired by the work of Julian Elischer (julian (at) tfs.com) and
68 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million!
69 */
70
71 /* TODO list:
72 * 1) Get the DMA stuff working.
73 * 2) Get the iov/uio stuff working. Is this a good thing ???
74 * 3) Get the synch stuff working.
75 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.?
76 */
77
78 /*
79 * A few customizable items:
80 */
81
82 /* Use doubleword transfers to/from SCSI chip. Note: This requires
83 * motherboard support. Basicly, some motherboard chipsets are able to
84 * split a 32 bit I/O operation into two 16 bit I/O operations,
85 * transparently to the processor. This speeds up some things, notably long
86 * data transfers.
87 */
88 #define SPC_USE_DWORDS 0
89
90 /* Synchronous data transfers? */
91 #define SPC_USE_SYNCHRONOUS 0
92 #define SPC_SYNC_REQ_ACK_OFS 8
93
94 /* Wide data transfers? */
95 #define SPC_USE_WIDE 0
96 #define SPC_MAX_WIDTH 0
97
98 /* Max attempts made to transmit a message */
99 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */
100
101 /*
102 * Some spin loop parameters (essentially how long to wait some places)
103 * The problem(?) is that sometimes we expect either to be able to transmit a
104 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid
105 * returning from the interrupt just to get yanked back for the next byte we
106 * may spin in the interrupt routine waiting for this byte to come. How long?
107 * This is really (SCSI) device and processor dependent. Tuneable, I guess.
108 */
109 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */
110 #define SPC_MSGOUT_SPIN 1
111
112 /* Include debug functions? At the end of this file there are a bunch of
113 * functions that will print out various information regarding queued SCSI
114 * commands, driver state and chip contents. You can call them from the
115 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the
116 * kernel uses less memory) but you lose the debugging facilities.
117 */
118 #define SPC_DEBUG 1
119
120 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */
121
122 /* End of customizable parameters */
123
124 /*
125 * MB89352 SCSI Protocol Controller (SPC) routines.
126 */
127
128 #include "opt_ddb.h"
129
130 #include <sys/types.h>
131 #include <sys/param.h>
132 #include <sys/systm.h>
133 #include <sys/kernel.h>
134 #include <sys/errno.h>
135 #include <sys/ioctl.h>
136 #include <sys/device.h>
137 #include <sys/buf.h>
138 #include <sys/proc.h>
139 #include <sys/user.h>
140 #include <sys/queue.h>
141
142 #include <machine/intr.h>
143 #include <machine/bus.h>
144
145 #include <dev/scsipi/scsi_all.h>
146 #include <dev/scsipi/scsipi_all.h>
147 #include <dev/scsipi/scsi_message.h>
148 #include <dev/scsipi/scsiconf.h>
149
150 #include <dev/ic/mb89352reg.h>
151 #include <dev/ic/mb89352var.h>
152
153 #ifndef DDB
155 #define Debugger() panic("should call debugger here (mb89352.c)")
156 #endif /* ! DDB */
157
158 #if SPC_DEBUG
159 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */
160 #endif
161
162 void spc_minphys __P((struct buf *));
163 void spc_done __P((struct spc_softc *, struct spc_acb *));
164 void spc_dequeue __P((struct spc_softc *, struct spc_acb *));
165 void spc_scsipi_request __P((struct scsipi_channel *,
166 scsipi_adapter_req_t, void *));
167 int spc_poll __P((struct spc_softc *, struct scsipi_xfer *, int));
168 integrate void spc_sched_msgout __P((struct spc_softc *, u_char));
169 integrate void spc_setsync __P((struct spc_softc *, struct spc_tinfo *));
170 void spc_select __P((struct spc_softc *, struct spc_acb *));
171 void spc_timeout __P((void *));
172 void spc_scsi_reset __P((struct spc_softc *));
173 void spc_reset __P((struct spc_softc *));
174 void spc_free_acb __P((struct spc_softc *, struct spc_acb *, int));
175 struct spc_acb* spc_get_acb __P((struct spc_softc *));
176 int spc_reselect __P((struct spc_softc *, int));
177 void spc_msgin __P((struct spc_softc *));
178 void spc_abort __P((struct spc_softc *, struct spc_acb *));
179 void spc_msgout __P((struct spc_softc *));
180 int spc_dataout_pio __P((struct spc_softc *, u_char *, int));
181 int spc_datain_pio __P((struct spc_softc *, u_char *, int));
182 #if SPC_DEBUG
183 void spc_print_acb __P((struct spc_acb *));
184 void spc_dump_driver __P((struct spc_softc *));
185 void spc_dump89352 __P((struct spc_softc *));
186 void spc_show_scsi_cmd __P((struct spc_acb *));
187 void spc_print_active_acb __P((void));
188 #endif
189
190 extern struct cfdriver spc_cd;
191
192
193 /*
195 * INITIALIZATION ROUTINES (probe, attach ++)
196 */
197
198 /*
199 * Do the real search-for-device.
200 * Prerequisite: sc->sc_iobase should be set to the proper value
201 */
202 int
203 spc_find(iot, ioh, bdid)
204 bus_space_tag_t iot;
205 bus_space_handle_t ioh;
206 int bdid;
207 {
208 long timeout = SPC_ABORT_TIMEOUT;
209
210 SPC_TRACE(("spc: probing for spc-chip\n"));
211 /*
212 * Disable interrupts then reset the FUJITSU chip.
213 */
214 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST);
215 bus_space_write_1(iot, ioh, SCMD, 0);
216 bus_space_write_1(iot, ioh, PCTL, 0);
217 bus_space_write_1(iot, ioh, TEMP, 0);
218 bus_space_write_1(iot, ioh, TCH, 0);
219 bus_space_write_1(iot, ioh, TCM, 0);
220 bus_space_write_1(iot, ioh, TCL, 0);
221 bus_space_write_1(iot, ioh, INTS, 0);
222 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB);
223 bus_space_write_1(iot, ioh, BDID, bdid);
224 delay(400);
225 bus_space_write_1(iot, ioh, SCTL, bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE);
226
227 /* The following detection is derived from spc.c
228 * (by Takahide Matsutsuka) in FreeBSD/pccard-test.
229 */
230 while (bus_space_read_1(iot, ioh, PSNS) && timeout)
231 timeout--;
232 if (!timeout) {
233 printf("spc: find failed\n");
234 return 0;
235 }
236
237 SPC_START(("SPC found"));
238 return 1;
239 }
240
241 void
242 spcattach(sc)
243 struct spc_softc *sc;
244 {
245
246 SPC_TRACE(("spcattach "));
247 sc->sc_state = SPC_INIT;
248
249 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */
250
251 #if SPC_USE_SYNCHRONOUS
252 /*
253 * These are the bounds of the sync period, based on the frequency of
254 * the chip's clock input and the size and offset of the sync period
255 * register.
256 *
257 * For a 20Mhz clock, this gives us 25, or 100nS, or 10MB/s, as a
258 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a
259 * minimum transfer rate.
260 */
261 sc->sc_minsync = (2 * 250) / sc->sc_freq;
262 sc->sc_maxsync = (9 * 250) / sc->sc_freq;
263 #endif
264
265 spc_init(sc); /* Init chip and driver */
266
267 /*
268 * Fill in the adapter.
269 */
270 sc->sc_adapter.adapt_dev = &sc->sc_dev;
271 sc->sc_adapter.adapt_nchannels = 1;
272 sc->sc_adapter.adapt_openings = 7;
273 sc->sc_adapter.adapt_max_periph = 1;
274 sc->sc_adapter.adapt_minphys = spc_minphys;
275 sc->sc_adapter.adapt_request = spc_scsipi_request;
276
277 sc->sc_channel.chan_adapter = &sc->sc_adapter;
278 sc->sc_channel.chan_bustype = &scsi_bustype;
279 sc->sc_channel.chan_channel = 0;
280 sc->sc_channel.chan_ntargets = 8;
281 sc->sc_channel.chan_nluns = 8;
282 sc->sc_channel.chan_id = sc->sc_initiator;
283
284 /*
285 * ask the adapter what subunits are present
286 */
287 config_found((struct device*)sc, &sc->sc_channel, scsiprint);
288 }
289
290 /*
291 * Initialize MB89352 chip itself
292 * The following conditions should hold:
293 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc
294 * must be valid.
295 */
296 void
297 spc_reset(sc)
298 struct spc_softc *sc;
299 {
300 bus_space_tag_t iot = sc->sc_iot;
301 bus_space_handle_t ioh = sc->sc_ioh;
302
303 SPC_TRACE(("spc_reset "));
304 /*
305 * Disable interrupts then reset the FUJITSU chip.
306 */
307 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST);
308 bus_space_write_1(iot, ioh, SCMD, 0);
309 bus_space_write_1(iot, ioh, PCTL, 0);
310 bus_space_write_1(iot, ioh, TEMP, 0);
311 bus_space_write_1(iot, ioh, TCH, 0);
312 bus_space_write_1(iot, ioh, TCM, 0);
313 bus_space_write_1(iot, ioh, TCL, 0);
314 bus_space_write_1(iot, ioh, INTS, 0);
315 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB);
316 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator);
317 delay(400);
318 bus_space_write_1(iot, ioh, SCTL, bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE);
319 }
320
321
322 /*
323 * Pull the SCSI RST line for 500us.
324 */
325 void
326 spc_scsi_reset(sc)
327 struct spc_softc *sc;
328 {
329 bus_space_tag_t iot = sc->sc_iot;
330 bus_space_handle_t ioh = sc->sc_ioh;
331
332 SPC_TRACE(("spc_scsi_reset "));
333 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) | SCMD_RST);
334 delay(500);
335 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST);
336 delay(50);
337 }
338
339 /*
340 * Initialize spc SCSI driver.
341 */
342 void
343 spc_init(sc)
344 struct spc_softc *sc;
345 {
346 struct spc_acb *acb;
347 int r;
348
349 SPC_TRACE(("spc_init "));
350 spc_reset(sc);
351 spc_scsi_reset(sc);
352 spc_reset(sc);
353
354 if (sc->sc_state == SPC_INIT) {
355 /* First time through; initialize. */
356 TAILQ_INIT(&sc->ready_list);
357 TAILQ_INIT(&sc->nexus_list);
358 TAILQ_INIT(&sc->free_list);
359 sc->sc_nexus = NULL;
360 acb = sc->sc_acb;
361 memset(acb, 0, sizeof(sc->sc_acb));
362 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) {
363 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain);
364 acb++;
365 }
366 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo));
367 } else {
368 /* Cancel any active commands. */
369 sc->sc_state = SPC_CLEANING;
370 if ((acb = sc->sc_nexus) != NULL) {
371 acb->xs->error = XS_DRIVER_STUFFUP;
372 callout_stop(&acb->xs->xs_callout);
373 spc_done(sc, acb);
374 }
375 while ((acb = sc->nexus_list.tqh_first) != NULL) {
376 acb->xs->error = XS_DRIVER_STUFFUP;
377 callout_stop(&acb->xs->xs_callout);
378 spc_done(sc, acb);
379 }
380 }
381
382 sc->sc_prevphase = PH_INVALID;
383 for (r = 0; r < 8; r++) {
384 struct spc_tinfo *ti = &sc->sc_tinfo[r];
385
386 ti->flags = 0;
387 #if SPC_USE_SYNCHRONOUS
388 ti->flags |= DO_SYNC;
389 ti->period = sc->sc_minsync;
390 ti->offset = SPC_SYNC_REQ_ACK_OFS;
391 #else
392 ti->period = ti->offset = 0;
393 #endif
394 #if SPC_USE_WIDE
395 ti->flags |= DO_WIDE;
396 ti->width = SPC_MAX_WIDTH;
397 #else
398 ti->width = 0;
399 #endif
400 }
401
402 sc->sc_state = SPC_IDLE;
403 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL,
404 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB);
405 }
406
407 void
408 spc_free_acb(sc, acb, flags)
409 struct spc_softc *sc;
410 struct spc_acb *acb;
411 int flags;
412 {
413 int s;
414
415 SPC_TRACE(("spc_free_acb "));
416 s = splbio();
417
418 acb->flags = 0;
419 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain);
420 splx(s);
421 }
422
423 struct spc_acb *
424 spc_get_acb(sc)
425 struct spc_softc *sc;
426 {
427 struct spc_acb *acb;
428 int s;
429
430 SPC_TRACE(("spc_get_acb "));
431 s = splbio();
432 acb = TAILQ_FIRST(&sc->free_list);
433 if (acb != NULL) {
434 TAILQ_REMOVE(&sc->free_list, acb, chain);
435 acb->flags |= ACB_ALLOC;
436 }
437 splx(s);
438 return acb;
439 }
440
441 /*
443 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
444 */
445
446 /*
447 * Expected sequence:
448 * 1) Command inserted into ready list
449 * 2) Command selected for execution
450 * 3) Command won arbitration and has selected target device
451 * 4) Send message out (identify message, eventually also sync.negotiations)
452 * 5) Send command
453 * 5a) Receive disconnect message, disconnect.
454 * 5b) Reselected by target
455 * 5c) Receive identify message from target.
456 * 6) Send or receive data
457 * 7) Receive status
458 * 8) Receive message (command complete etc.)
459 */
460
461 /*
462 * Start a SCSI-command
463 * This function is called by the higher level SCSI-driver to queue/run
464 * SCSI-commands.
465 */
466 void
467 spc_scsipi_request(chan, req, arg)
468 struct scsipi_channel *chan;
469 scsipi_adapter_req_t req;
470 void *arg;
471 {
472 struct scsipi_xfer *xs;
473 struct scsipi_periph *periph;
474 struct spc_softc *sc = (void *)chan->chan_adapter->adapt_dev;
475 struct spc_acb *acb;
476 int s, flags;
477
478 switch (req) {
479 case ADAPTER_REQ_RUN_XFER:
480 xs = arg;
481 periph = xs->xs_periph;
482 SPC_TRACE(("spc_scsipi_request "));
483 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen,
484 periph->periph_target));
485
486 flags = xs->xs_control;
487 if ((acb = spc_get_acb(sc)) == NULL) {
488 xs->error = XS_DRIVER_STUFFUP;
489 scsipi_done(xs);
490 return;
491 }
492
493 /* Initialize acb */
494 acb->xs = xs;
495 acb->timeout = xs->timeout;
496
497 if (xs->xs_control & XS_CTL_RESET) {
498 acb->flags |= ACB_RESET;
499 acb->scsipi_cmd_length = 0;
500 acb->data_length = 0;
501 } else {
502 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen);
503 #if 1
504 acb->scsipi_cmd.bytes[0] |= periph->periph_lun << 5; /* XXX? */
505 #endif
506 acb->scsipi_cmd_length = xs->cmdlen;
507 acb->data_addr = xs->data;
508 acb->data_length = xs->datalen;
509 }
510 acb->target_stat = 0;
511
512 s = splbio();
513
514 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain);
515 /*
516 * Start scheduling unless a queue process is in progress.
517 */
518 if (sc->sc_state == SPC_IDLE)
519 spc_sched(sc);
520 /*
521 * After successful sending, check if we should return just now.
522 * If so, return SUCCESSFULLY_QUEUED.
523 */
524
525 splx(s);
526
527 if ((flags & XS_CTL_POLL) == 0)
528 return;
529
530 /* Not allowed to use interrupts, use polling instead */
531 s = splbio();
532 if (spc_poll(sc, xs, acb->timeout)) {
533 spc_timeout(acb);
534 if (spc_poll(sc, xs, acb->timeout))
535 spc_timeout(acb);
536 }
537 splx(s);
538 return;
539 case ADAPTER_REQ_GROW_RESOURCES:
540 /* XXX Not supported. */
541 return;
542 case ADAPTER_REQ_SET_XFER_MODE:
543 /* XXX Not supported. */
544 return;
545 }
546 }
547
548 /*
549 * Adjust transfer size in buffer structure
550 */
551 void
552 spc_minphys(bp)
553 struct buf *bp;
554 {
555
556 SPC_TRACE(("spc_minphys "));
557 minphys(bp);
558 }
559
560 /*
561 * Used when interrupt driven I/O isn't allowed, e.g. during boot.
562 */
563 int
564 spc_poll(sc, xs, count)
565 struct spc_softc *sc;
566 struct scsipi_xfer *xs;
567 int count;
568 {
569 bus_space_tag_t iot = sc->sc_iot;
570 bus_space_handle_t ioh = sc->sc_ioh;
571
572 SPC_TRACE(("spc_poll "));
573 while (count) {
574 /*
575 * If we had interrupts enabled, would we
576 * have got an interrupt?
577 */
578 if (bus_space_read_1(iot, ioh, INTS) != 0)
579 spcintr(sc);
580 if ((xs->xs_status & XS_STS_DONE) != 0)
581 return 0;
582 delay(1000);
583 count--;
584 }
585 return 1;
586 }
587
588 /*
590 * LOW LEVEL SCSI UTILITIES
591 */
592
593 integrate void
594 spc_sched_msgout(sc, m)
595 struct spc_softc *sc;
596 u_char m;
597 {
598 bus_space_tag_t iot = sc->sc_iot;
599 bus_space_handle_t ioh = sc->sc_ioh;
600
601 SPC_TRACE(("spc_sched_msgout "));
602 if (sc->sc_msgpriq == 0)
603 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN);
604 sc->sc_msgpriq |= m;
605 }
606
607 /*
608 * Set synchronous transfer offset and period.
609 */
610 integrate void
611 spc_setsync(sc, ti)
612 struct spc_softc *sc;
613 struct spc_tinfo *ti;
614 {
615 #if SPC_USE_SYNCHRONOUS
616 bus_space_tag_t iot = sc->sc_iot;
617 bus_space_handle_t ioh = sc->sc_ioh;
618
619 SPC_TRACE(("spc_setsync "));
620 if (ti->offset != 0)
621 bus_space_write_1(iot, ioh, TMOD,
622 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset);
623 else
624 bus_space_write_1(iot, ioh, TMOD, 0);
625 #endif
626 }
627
628 /*
629 * Start a selection. This is used by spc_sched() to select an idle target.
630 */
631 void
632 spc_select(sc, acb)
633 struct spc_softc *sc;
634 struct spc_acb *acb;
635 {
636 struct scsipi_periph *periph = acb->xs->xs_periph;
637 int target = periph->periph_target;
638 struct spc_tinfo *ti = &sc->sc_tinfo[target];
639 bus_space_tag_t iot = sc->sc_iot;
640 bus_space_handle_t ioh = sc->sc_ioh;
641
642 SPC_TRACE(("spc_select "));
643 spc_setsync(sc, ti);
644
645 #if 0
646 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN);
647 #endif
648 #ifdef x68k /* XXX? */
649 do {
650 asm ("nop");
651 } while (bus_space_read_1(iot, ioh, SSTS) &
652 (SSTS_ACTIVE|SSTS_TARGET|SSTS_BUSY));
653 #endif
654
655 bus_space_write_1(iot, ioh, PCTL, 0);
656 bus_space_write_1(iot, ioh, TEMP, (1 << sc->sc_initiator) | (1 << target));
657 /*
658 * Setup BSY timeout (selection timeout).
659 * 250ms according to the SCSI specification.
660 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k)
661 * To setup 256ms timeout,
662 * 128000ns/200ns = X * 256 + 15
663 * 640 - 15 = X * 256
664 * X = 625 / 256
665 * X = 2 + 113 / 256
666 * ==> tch = 2, tcm = 113 (correct?)
667 */
668 bus_space_write_1(iot, ioh, TCH, 2);
669 bus_space_write_1(iot, ioh, TCM, 113);
670 /* Time to the information transfer phase start. */
671 bus_space_write_1(iot, ioh, TCL, 3);
672 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT);
673
674 sc->sc_state = SPC_SELECTING;
675 }
676
677 int
678 spc_reselect(sc, message)
679 struct spc_softc *sc;
680 int message;
681 {
682 u_char selid, target, lun;
683 struct spc_acb *acb;
684 struct scsipi_periph *periph;
685 struct spc_tinfo *ti;
686
687 SPC_TRACE(("spc_reselect "));
688 /*
689 * The SCSI chip made a snapshot of the data bus while the reselection
690 * was being negotiated. This enables us to determine which target did
691 * the reselect.
692 */
693 selid = sc->sc_selid & ~(1 << sc->sc_initiator);
694 if (selid & (selid - 1)) {
695 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n",
696 sc->sc_dev.dv_xname, selid);
697 SPC_BREAK();
698 goto reset;
699 }
700
701 /*
702 * Search wait queue for disconnected cmd
703 * The list should be short, so I haven't bothered with
704 * any more sophisticated structures than a simple
705 * singly linked list.
706 */
707 target = ffs(selid) - 1;
708 lun = message & 0x07;
709 for (acb = sc->nexus_list.tqh_first; acb != NULL;
710 acb = acb->chain.tqe_next) {
711 periph = acb->xs->xs_periph;
712 if (periph->periph_target == target &&
713 periph->periph_lun == lun)
714 break;
715 }
716 if (acb == NULL) {
717 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n",
718 sc->sc_dev.dv_xname, target, lun);
719 SPC_BREAK();
720 goto abort;
721 }
722
723 /* Make this nexus active again. */
724 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
725 sc->sc_state = SPC_CONNECTED;
726 sc->sc_nexus = acb;
727 ti = &sc->sc_tinfo[target];
728 ti->lubusy |= (1 << lun);
729 spc_setsync(sc, ti);
730
731 if (acb->flags & ACB_RESET)
732 spc_sched_msgout(sc, SEND_DEV_RESET);
733 else if (acb->flags & ACB_ABORT)
734 spc_sched_msgout(sc, SEND_ABORT);
735
736 /* Do an implicit RESTORE POINTERS. */
737 sc->sc_dp = acb->data_addr;
738 sc->sc_dleft = acb->data_length;
739 sc->sc_cp = (u_char *)&acb->scsipi_cmd;
740 sc->sc_cleft = acb->scsipi_cmd_length;
741
742 return (0);
743
744 reset:
745 spc_sched_msgout(sc, SEND_DEV_RESET);
746 return (1);
747
748 abort:
749 spc_sched_msgout(sc, SEND_ABORT);
750 return (1);
751 }
752
753 /*
755 * Schedule a SCSI operation. This has now been pulled out of the interrupt
756 * handler so that we may call it from spc_scsi_cmd and spc_done. This may
757 * save us an unecessary interrupt just to get things going. Should only be
758 * called when state == SPC_IDLE and at bio pl.
759 */
760 void
761 spc_sched(sc)
762 struct spc_softc *sc;
763 {
764 struct spc_acb *acb;
765 struct scsipi_periph *periph;
766 struct spc_tinfo *ti;
767
768 /* missing the hw, just return and wait for our hw */
769 if (sc->sc_flags & SPC_INACTIVE)
770 return;
771 SPC_TRACE(("spc_sched "));
772 /*
773 * Find first acb in ready queue that is for a target/lunit pair that
774 * is not busy.
775 */
776 for (acb = sc->ready_list.tqh_first; acb != NULL;
777 acb = acb->chain.tqe_next) {
778 periph = acb->xs->xs_periph;
779 ti = &sc->sc_tinfo[periph->periph_target];
780 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) {
781 SPC_MISC(("selecting %d:%d ",
782 periph->periph_target, periph->periph_lun));
783 TAILQ_REMOVE(&sc->ready_list, acb, chain);
784 sc->sc_nexus = acb;
785 spc_select(sc, acb);
786 return;
787 } else
788 SPC_MISC(("%d:%d busy\n",
789 periph->periph_target, periph->periph_lun));
790 }
791 SPC_MISC(("idle "));
792 /* Nothing to start; just enable reselections and wait. */
793 }
794
795 /*
797 * POST PROCESSING OF SCSI_CMD (usually current)
798 */
799 void
800 spc_done(sc, acb)
801 struct spc_softc *sc;
802 struct spc_acb *acb;
803 {
804 struct scsipi_xfer *xs = acb->xs;
805 struct scsipi_periph *periph = xs->xs_periph;
806 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target];
807
808 SPC_TRACE(("spc_done "));
809
810 if (xs->error == XS_NOERROR) {
811 if (acb->flags & ACB_ABORT) {
812 xs->error = XS_DRIVER_STUFFUP;
813 } else {
814 switch (acb->target_stat) {
815 case SCSI_CHECK:
816 /* First, save the return values */
817 xs->resid = acb->data_length;
818 /* FALLBACK */
819 case SCSI_BUSY:
820 xs->status = acb->target_stat;
821 xs->error = XS_BUSY;
822 break;
823 case SCSI_OK:
824 xs->resid = acb->data_length;
825 break;
826 default:
827 xs->error = XS_DRIVER_STUFFUP;
828 #if SPC_DEBUG
829 printf("%s: spc_done: bad stat 0x%x\n",
830 sc->sc_dev.dv_xname, acb->target_stat);
831 #endif
832 break;
833 }
834 }
835 }
836
837 #if SPC_DEBUG
838 if ((spc_debug & SPC_SHOWMISC) != 0) {
839 if (xs->resid != 0)
840 printf("resid=%d ", xs->resid);
841 else
842 printf("error=%d\n", xs->error);
843 }
844 #endif
845
846 /*
847 * Remove the ACB from whatever queue it happens to be on.
848 */
849 if (acb->flags & ACB_NEXUS)
850 ti->lubusy &= ~(1 << periph->periph_lun);
851 if (acb == sc->sc_nexus) {
852 sc->sc_nexus = NULL;
853 sc->sc_state = SPC_IDLE;
854 spc_sched(sc);
855 } else
856 spc_dequeue(sc, acb);
857
858 spc_free_acb(sc, acb, xs->xs_control);
859 ti->cmds++;
860 scsipi_done(xs);
861 }
862
863 void
864 spc_dequeue(sc, acb)
865 struct spc_softc *sc;
866 struct spc_acb *acb;
867 {
868
869 SPC_TRACE(("spc_dequeue "));
870 if (acb->flags & ACB_NEXUS) {
871 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
872 } else {
873 TAILQ_REMOVE(&sc->ready_list, acb, chain);
874 }
875 }
876
877 /*
879 * INTERRUPT/PROTOCOL ENGINE
880 */
881
882 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80)
883 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20)
884 #define ISEXTMSG(m) ((m) == 0x01)
885
886 /*
887 * Precondition:
888 * The SCSI bus is already in the MSGI phase and there is a message byte
889 * on the bus, along with an asserted REQ signal.
890 */
891 void
892 spc_msgin(sc)
893 struct spc_softc *sc;
894 {
895 bus_space_tag_t iot = sc->sc_iot;
896 bus_space_handle_t ioh = sc->sc_ioh;
897 int n;
898
899 SPC_TRACE(("spc_msgin "));
900
901 if (sc->sc_prevphase == PH_MSGIN) {
902 /* This is a continuation of the previous message. */
903 n = sc->sc_imp - sc->sc_imess;
904 goto nextbyte;
905 }
906
907 /* This is a new MESSAGE IN phase. Clean up our state. */
908 sc->sc_flags &= ~SPC_DROP_MSGIN;
909
910 nextmsg:
911 n = 0;
912 sc->sc_imp = &sc->sc_imess[n];
913
914 nextbyte:
915 /*
916 * Read a whole message, but don't ack the last byte. If we reject the
917 * message, we have to assert ATN during the message transfer phase
918 * itself.
919 */
920 for (;;) {
921 #if 0
922 for (;;) {
923 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0)
924 break;
925 /* Wait for REQINIT. XXX Need timeout. */
926 }
927 #endif
928 if (bus_space_read_1(iot, ioh, INTS) != 0) {
929 /*
930 * Target left MESSAGE IN, probably because it
931 * a) noticed our ATN signal, or
932 * b) ran out of messages.
933 */
934 goto out;
935 }
936
937 /* If parity error, just dump everything on the floor. */
938 if ((bus_space_read_1(iot, ioh, SERR) &
939 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) {
940 sc->sc_flags |= SPC_DROP_MSGIN;
941 spc_sched_msgout(sc, SEND_PARITY_ERROR);
942 }
943
944 /* send TRANSFER command. */
945 bus_space_write_1(iot, ioh, TCH, 0);
946 bus_space_write_1(iot, ioh, TCM, 0);
947 bus_space_write_1(iot, ioh, TCL, 1);
948 bus_space_write_1(iot, ioh, PCTL,
949 sc->sc_phase | PCTL_BFINT_ENAB);
950 #ifdef x68k
951 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* | SCMD_PROG_XFR */
952 #else
953 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); /* XXX */
954 #endif
955 for (;;) {
956 /*if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0
957 && (bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)*/
958 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) == 0)
959 break;
960 if (bus_space_read_1(iot, ioh, INTS) != 0)
961 goto out;
962 }
963
964 /* Gather incoming message bytes if needed. */
965 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) {
966 if (n >= SPC_MAX_MSG_LEN) {
967 (void) bus_space_read_1(iot, ioh, DREG);
968 sc->sc_flags |= SPC_DROP_MSGIN;
969 spc_sched_msgout(sc, SEND_REJECT);
970 } else {
971 *sc->sc_imp++ = bus_space_read_1(iot, ioh, DREG);
972 n++;
973 /*
974 * This testing is suboptimal, but most
975 * messages will be of the one byte variety, so
976 * it should not affect performance
977 * significantly.
978 */
979 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0]))
980 break;
981 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0]))
982 break;
983 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) &&
984 n == sc->sc_imess[1] + 2)
985 break;
986 }
987 } else
988 (void) bus_space_read_1(iot, ioh, DREG);
989
990 /*
991 * If we reach this spot we're either:
992 * a) in the middle of a multi-byte message, or
993 * b) dropping bytes.
994 */
995 #if 0
996 /* Ack the last byte read. */
997 /*(void) bus_space_read_1(iot, ioh, DREG);*/
998 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
999 ;
1000 #endif
1001 }
1002
1003 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0]));
1004
1005 /* We now have a complete message. Parse it. */
1006 switch (sc->sc_state) {
1007 struct spc_acb *acb;
1008 struct scsipi_periph *periph;
1009 struct spc_tinfo *ti;
1010
1011 case SPC_CONNECTED:
1012 SPC_ASSERT(sc->sc_nexus != NULL);
1013 acb = sc->sc_nexus;
1014 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target];
1015
1016 switch (sc->sc_imess[0]) {
1017 case MSG_CMDCOMPLETE:
1018 if (sc->sc_dleft < 0) {
1019 periph = acb->xs->xs_periph;
1020 printf("%s: %d extra bytes from %d:%d\n",
1021 sc->sc_dev.dv_xname, -sc->sc_dleft,
1022 periph->periph_target, periph->periph_lun);
1023 acb->data_length = 0;
1024 }
1025 acb->xs->resid = acb->data_length = sc->sc_dleft;
1026 sc->sc_state = SPC_CMDCOMPLETE;
1027 break;
1028
1029 case MSG_PARITY_ERROR:
1030 /* Resend the last message. */
1031 spc_sched_msgout(sc, sc->sc_lastmsg);
1032 break;
1033
1034 case MSG_MESSAGE_REJECT:
1035 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg));
1036 switch (sc->sc_lastmsg) {
1037 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE
1038 case SEND_IDENTIFY:
1039 ti->flags &= ~(DO_SYNC | DO_WIDE);
1040 ti->period = ti->offset = 0;
1041 spc_setsync(sc, ti);
1042 ti->width = 0;
1043 break;
1044 #endif
1045 #if SPC_USE_SYNCHRONOUS
1046 case SEND_SDTR:
1047 ti->flags &= ~DO_SYNC;
1048 ti->period = ti->offset = 0;
1049 spc_setsync(sc, ti);
1050 break;
1051 #endif
1052 #if SPC_USE_WIDE
1053 case SEND_WDTR:
1054 ti->flags &= ~DO_WIDE;
1055 ti->width = 0;
1056 break;
1057 #endif
1058 case SEND_INIT_DET_ERR:
1059 spc_sched_msgout(sc, SEND_ABORT);
1060 break;
1061 }
1062 break;
1063
1064 case MSG_NOOP:
1065 break;
1066
1067 case MSG_DISCONNECT:
1068 ti->dconns++;
1069 sc->sc_state = SPC_DISCONNECT;
1070 break;
1071
1072 case MSG_SAVEDATAPOINTER:
1073 acb->data_addr = sc->sc_dp;
1074 acb->data_length = sc->sc_dleft;
1075 break;
1076
1077 case MSG_RESTOREPOINTERS:
1078 sc->sc_dp = acb->data_addr;
1079 sc->sc_dleft = acb->data_length;
1080 sc->sc_cp = (u_char *)&acb->scsipi_cmd;
1081 sc->sc_cleft = acb->scsipi_cmd_length;
1082 break;
1083
1084 case MSG_EXTENDED:
1085 switch (sc->sc_imess[2]) {
1086 #if SPC_USE_SYNCHRONOUS
1087 case MSG_EXT_SDTR:
1088 if (sc->sc_imess[1] != 3)
1089 goto reject;
1090 ti->period = sc->sc_imess[3];
1091 ti->offset = sc->sc_imess[4];
1092 ti->flags &= ~DO_SYNC;
1093 if (ti->offset == 0) {
1094 } else if (ti->period < sc->sc_minsync ||
1095 ti->period > sc->sc_maxsync ||
1096 ti->offset > 8) {
1097 ti->period = ti->offset = 0;
1098 spc_sched_msgout(sc, SEND_SDTR);
1099 } else {
1100 scsipi_printaddr(acb->xs->xs_periph);
1101 printf("sync, offset %d, period %dnsec\n",
1102 ti->offset, ti->period * 4);
1103 }
1104 spc_setsync(sc, ti);
1105 break;
1106 #endif
1107
1108 #if SPC_USE_WIDE
1109 case MSG_EXT_WDTR:
1110 if (sc->sc_imess[1] != 2)
1111 goto reject;
1112 ti->width = sc->sc_imess[3];
1113 ti->flags &= ~DO_WIDE;
1114 if (ti->width == 0) {
1115 } else if (ti->width > SPC_MAX_WIDTH) {
1116 ti->width = 0;
1117 spc_sched_msgout(sc, SEND_WDTR);
1118 } else {
1119 scsipi_printaddr(acb->xs->xs_periph);
1120 printf("wide, width %d\n",
1121 1 << (3 + ti->width));
1122 }
1123 break;
1124 #endif
1125
1126 default:
1127 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n",
1128 sc->sc_dev.dv_xname);
1129 SPC_BREAK();
1130 goto reject;
1131 }
1132 break;
1133
1134 default:
1135 printf("%s: unrecognized MESSAGE; sending REJECT\n",
1136 sc->sc_dev.dv_xname);
1137 SPC_BREAK();
1138 reject:
1139 spc_sched_msgout(sc, SEND_REJECT);
1140 break;
1141 }
1142 break;
1143
1144 case SPC_RESELECTED:
1145 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) {
1146 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n",
1147 sc->sc_dev.dv_xname);
1148 SPC_BREAK();
1149 goto reset;
1150 }
1151
1152 (void) spc_reselect(sc, sc->sc_imess[0]);
1153 break;
1154
1155 default:
1156 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n",
1157 sc->sc_dev.dv_xname);
1158 SPC_BREAK();
1159 reset:
1160 spc_sched_msgout(sc, SEND_DEV_RESET);
1161 break;
1162
1163 #ifdef notdef
1164 abort:
1165 spc_sched_msgout(sc, SEND_ABORT);
1166 break;
1167 #endif
1168 }
1169
1170 /* Ack the last message byte. */
1171 #if 0 /* XXX? */
1172 (void) bus_space_read_1(iot, ioh, DREG);
1173 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
1174 ;
1175 #endif
1176
1177 /* Go get the next message, if any. */
1178 goto nextmsg;
1179
1180 out:
1181 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK);
1182 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0]));
1183 }
1184
1185 /*
1186 * Send the highest priority, scheduled message.
1187 */
1188 void
1189 spc_msgout(sc)
1190 struct spc_softc *sc;
1191 {
1192 bus_space_tag_t iot = sc->sc_iot;
1193 bus_space_handle_t ioh = sc->sc_ioh;
1194 #if SPC_USE_SYNCHRONOUS
1195 struct spc_tinfo *ti;
1196 #endif
1197 int n;
1198
1199 SPC_TRACE(("spc_msgout "));
1200
1201 if (sc->sc_prevphase == PH_MSGOUT) {
1202 if (sc->sc_omp == sc->sc_omess) {
1203 /*
1204 * This is a retransmission.
1205 *
1206 * We get here if the target stayed in MESSAGE OUT
1207 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates
1208 * that all of the previously transmitted messages must
1209 * be sent again, in the same order. Therefore, we
1210 * requeue all the previously transmitted messages, and
1211 * start again from the top. Our simple priority
1212 * scheme keeps the messages in the right order.
1213 */
1214 SPC_MISC(("retransmitting "));
1215 sc->sc_msgpriq |= sc->sc_msgoutq;
1216 /*
1217 * Set ATN. If we're just sending a trivial 1-byte
1218 * message, we'll clear ATN later on anyway.
1219 */
1220 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); /* XXX? */
1221 } else {
1222 /* This is a continuation of the previous message. */
1223 n = sc->sc_omp - sc->sc_omess;
1224 goto nextbyte;
1225 }
1226 }
1227
1228 /* No messages transmitted so far. */
1229 sc->sc_msgoutq = 0;
1230 sc->sc_lastmsg = 0;
1231
1232 nextmsg:
1233 /* Pick up highest priority message. */
1234 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq;
1235 sc->sc_msgpriq &= ~sc->sc_currmsg;
1236 sc->sc_msgoutq |= sc->sc_currmsg;
1237
1238 /* Build the outgoing message data. */
1239 switch (sc->sc_currmsg) {
1240 case SEND_IDENTIFY:
1241 SPC_ASSERT(sc->sc_nexus != NULL);
1242 sc->sc_omess[0] =
1243 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1);
1244 n = 1;
1245 break;
1246
1247 #if SPC_USE_SYNCHRONOUS
1248 case SEND_SDTR:
1249 SPC_ASSERT(sc->sc_nexus != NULL);
1250 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
1251 sc->sc_omess[4] = MSG_EXTENDED;
1252 sc->sc_omess[3] = 3;
1253 sc->sc_omess[2] = MSG_EXT_SDTR;
1254 sc->sc_omess[1] = ti->period >> 2;
1255 sc->sc_omess[0] = ti->offset;
1256 n = 5;
1257 break;
1258 #endif
1259
1260 #if SPC_USE_WIDE
1261 case SEND_WDTR:
1262 SPC_ASSERT(sc->sc_nexus != NULL);
1263 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
1264 sc->sc_omess[3] = MSG_EXTENDED;
1265 sc->sc_omess[2] = 2;
1266 sc->sc_omess[1] = MSG_EXT_WDTR;
1267 sc->sc_omess[0] = ti->width;
1268 n = 4;
1269 break;
1270 #endif
1271
1272 case SEND_DEV_RESET:
1273 sc->sc_flags |= SPC_ABORTING;
1274 sc->sc_omess[0] = MSG_BUS_DEV_RESET;
1275 n = 1;
1276 break;
1277
1278 case SEND_REJECT:
1279 sc->sc_omess[0] = MSG_MESSAGE_REJECT;
1280 n = 1;
1281 break;
1282
1283 case SEND_PARITY_ERROR:
1284 sc->sc_omess[0] = MSG_PARITY_ERROR;
1285 n = 1;
1286 break;
1287
1288 case SEND_INIT_DET_ERR:
1289 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
1290 n = 1;
1291 break;
1292
1293 case SEND_ABORT:
1294 sc->sc_flags |= SPC_ABORTING;
1295 sc->sc_omess[0] = MSG_ABORT;
1296 n = 1;
1297 break;
1298
1299 default:
1300 printf("%s: unexpected MESSAGE OUT; sending NOOP\n",
1301 sc->sc_dev.dv_xname);
1302 SPC_BREAK();
1303 sc->sc_omess[0] = MSG_NOOP;
1304 n = 1;
1305 break;
1306 }
1307 sc->sc_omp = &sc->sc_omess[n];
1308
1309 nextbyte:
1310 /* Send message bytes. */
1311 /* send TRANSFER command. */
1312 bus_space_write_1(iot, ioh, TCH, n >> 16);
1313 bus_space_write_1(iot, ioh, TCM, n >> 8);
1314 bus_space_write_1(iot, ioh, TCL, n);
1315 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1316 #ifdef x68k
1317 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1318 #else
1319 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR);
1320 #endif
1321 for (;;) {
1322 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1323 break;
1324 if (bus_space_read_1(iot, ioh, INTS) != 0)
1325 goto out;
1326 }
1327 for (;;) {
1328 #if 0
1329 for (;;) {
1330 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0)
1331 break;
1332 /* Wait for REQINIT. XXX Need timeout. */
1333 }
1334 #endif
1335 if (bus_space_read_1(iot, ioh, INTS) != 0) {
1336 /*
1337 * Target left MESSAGE OUT, possibly to reject
1338 * our message.
1339 *
1340 * If this is the last message being sent, then we
1341 * deassert ATN, since either the target is going to
1342 * ignore this message, or it's going to ask for a
1343 * retransmission via MESSAGE PARITY ERROR (in which
1344 * case we reassert ATN anyway).
1345 */
1346 #if 0
1347 if (sc->sc_msgpriq == 0)
1348 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN);
1349 #endif
1350 goto out;
1351 }
1352
1353 #if 0
1354 /* Clear ATN before last byte if this is the last message. */
1355 if (n == 1 && sc->sc_msgpriq == 0)
1356 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN);
1357 #endif
1358
1359 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0)
1360 ;
1361 /* Send message byte. */
1362 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp);
1363 --n;
1364 /* Keep track of the last message we've sent any bytes of. */
1365 sc->sc_lastmsg = sc->sc_currmsg;
1366 #if 0
1367 /* Wait for ACK to be negated. XXX Need timeout. */
1368 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
1369 ;
1370 #endif
1371
1372 if (n == 0)
1373 break;
1374 }
1375
1376 /* We get here only if the entire message has been transmitted. */
1377 if (sc->sc_msgpriq != 0) {
1378 /* There are more outgoing messages. */
1379 goto nextmsg;
1380 }
1381
1382 /*
1383 * The last message has been transmitted. We need to remember the last
1384 * message transmitted (in case the target switches to MESSAGE IN phase
1385 * and sends a MESSAGE REJECT), and the list of messages transmitted
1386 * this time around (in case the target stays in MESSAGE OUT phase to
1387 * request a retransmit).
1388 */
1389
1390 out:
1391 /* Disable REQ/ACK protocol. */
1392 }
1393
1394 /*
1396 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc
1397 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted
1398 * and ACK deasserted (i.e. waiting for a data byte)
1399 *
1400 * This new revision has been optimized (I tried) to make the common case fast,
1401 * and the rarer cases (as a result) somewhat more comlex
1402 */
1403 int
1404 spc_dataout_pio(sc, p, n)
1405 struct spc_softc *sc;
1406 u_char *p;
1407 int n;
1408 {
1409 bus_space_tag_t iot = sc->sc_iot;
1410 bus_space_handle_t ioh = sc->sc_ioh;
1411 u_char intstat = 0;
1412 int out = 0;
1413 #define DOUTAMOUNT 8 /* Full FIFO */
1414
1415 SPC_TRACE(("spc_dataout_pio "));
1416 /* send TRANSFER command. */
1417 bus_space_write_1(iot, ioh, TCH, n >> 16);
1418 bus_space_write_1(iot, ioh, TCM, n >> 8);
1419 bus_space_write_1(iot, ioh, TCL, n);
1420 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1421 #ifdef x68k
1422 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1423 #else
1424 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR); /* XXX */
1425 #endif
1426 for (;;) {
1427 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1428 break;
1429 if (bus_space_read_1(iot, ioh, INTS) != 0)
1430 break;
1431 }
1432
1433 /*
1434 * I have tried to make the main loop as tight as possible. This
1435 * means that some of the code following the loop is a bit more
1436 * complex than otherwise.
1437 */
1438 while (n > 0) {
1439 int xfer;
1440
1441 for (;;) {
1442 intstat = bus_space_read_1(iot, ioh, INTS);
1443 /* Wait till buffer is empty. */
1444 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)
1445 break;
1446 /* Break on interrupt. */
1447 if (intstat != 0)
1448 goto phasechange;
1449 }
1450
1451 xfer = min(DOUTAMOUNT, n);
1452
1453 SPC_MISC(("%d> ", xfer));
1454
1455 n -= xfer;
1456 out += xfer;
1457
1458 while (xfer-- > 0) {
1459 bus_space_write_1(iot, ioh, DREG, *p++);
1460 }
1461 }
1462
1463 if (out == 0) {
1464 for (;;) {
1465 if (bus_space_read_1(iot, ioh, INTS) != 0)
1466 break;
1467 }
1468 SPC_MISC(("extra data "));
1469 } else {
1470 /* See the bytes off chip */
1471 for (;;) {
1472 /* Wait till buffer is empty. */
1473 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)
1474 break;
1475 intstat = bus_space_read_1(iot, ioh, INTS);
1476 /* Break on interrupt. */
1477 if (intstat != 0)
1478 goto phasechange;
1479 }
1480 }
1481
1482 phasechange:
1483 /* Stop the FIFO data path. */
1484
1485 if (intstat != 0) {
1486 /* Some sort of phase change. */
1487 int amount;
1488
1489 amount = ((bus_space_read_1(iot, ioh, TCH) << 16) |
1490 (bus_space_read_1(iot, ioh, TCM) << 8) |
1491 bus_space_read_1(iot, ioh, TCL));
1492 if (amount > 0) {
1493 out -= amount;
1494 SPC_MISC(("+%d ", amount));
1495 }
1496 }
1497
1498 /* Turn on ENREQINIT again. */
1499
1500 return out;
1501 }
1502
1503 /*
1505 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc
1506 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted
1507 * and ACK deasserted (i.e. at least one byte is ready).
1508 *
1509 * For now, uses a pretty dumb algorithm, hangs around until all data has been
1510 * transferred. This, is OK for fast targets, but not so smart for slow
1511 * targets which don't disconnect or for huge transfers.
1512 */
1513 int
1514 spc_datain_pio(sc, p, n)
1515 struct spc_softc *sc;
1516 u_char *p;
1517 int n;
1518 {
1519 bus_space_tag_t iot = sc->sc_iot;
1520 bus_space_handle_t ioh = sc->sc_ioh;
1521 u_short intstat;
1522 int in = 0;
1523 #define DINAMOUNT 8 /* Full FIFO */
1524
1525 SPC_TRACE(("spc_datain_pio "));
1526 /* send TRANSFER command. */
1527 bus_space_write_1(iot, ioh, TCH, n >> 16);
1528 bus_space_write_1(iot, ioh, TCM, n >> 8);
1529 bus_space_write_1(iot, ioh, TCL, n);
1530 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1531 #ifdef x68k
1532 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1533 #else
1534 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); /* XXX */
1535 #endif
1536 for (;;) {
1537 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1538 break;
1539 if (bus_space_read_1(iot, ioh, INTS) != 0)
1540 goto phasechange;
1541 }
1542
1543 /*
1544 * We leave this loop if one or more of the following is true:
1545 * a) phase != PH_DATAIN && FIFOs are empty
1546 * b) reset has occurred or busfree is detected.
1547 */
1548 while (n > 0) {
1549 int xfer;
1550
1551 #define INTSMASK 0xff
1552 /* Wait for fifo half full or phase mismatch */
1553 for (;;) {
1554 intstat = ((bus_space_read_1(iot, ioh, SSTS) << 8) |
1555 bus_space_read_1(iot, ioh, INTS));
1556 if ((intstat & (INTSMASK | (SSTS_DREG_FULL << 8))) !=
1557 0)
1558 break;
1559 if ((intstat & (SSTS_DREG_EMPTY << 8)) == 0)
1560 break;
1561 }
1562
1563 #if 1
1564 if ((intstat & INTSMASK) != 0)
1565 goto phasechange;
1566 #else
1567 if ((intstat & INTSMASK) != 0 &&
1568 (intstat & (SSTS_DREG_EMPTY << 8)))
1569 goto phasechange;
1570 #endif
1571 if ((intstat & (SSTS_DREG_FULL << 8)) != 0)
1572 xfer = min(DINAMOUNT, n);
1573 else
1574 xfer = min(1, n);
1575
1576 SPC_MISC((">%d ", xfer));
1577
1578 n -= xfer;
1579 in += xfer;
1580
1581 while (xfer-- > 0) {
1582 *p++ = bus_space_read_1(iot, ioh, DREG);
1583 }
1584
1585 if ((intstat & INTSMASK) != 0)
1586 goto phasechange;
1587 }
1588
1589 /*
1590 * Some SCSI-devices are rude enough to transfer more data than what
1591 * was requested, e.g. 2048 bytes from a CD-ROM instead of the
1592 * requested 512. Test for progress, i.e. real transfers. If no real
1593 * transfers have been performed (n is probably already zero) and the
1594 * FIFO is not empty, waste some bytes....
1595 */
1596 if (in == 0) {
1597 for (;;) {
1598 if (bus_space_read_1(iot, ioh, INTS) != 0)
1599 break;
1600 }
1601 SPC_MISC(("extra data "));
1602 }
1603
1604 phasechange:
1605 /* Stop the FIFO data path. */
1606
1607 /* Turn on ENREQINIT again. */
1608
1609 return in;
1610 }
1611
1612 /*
1614 * Catch an interrupt from the adaptor
1615 */
1616 /*
1617 * This is the workhorse routine of the driver.
1618 * Deficiencies (for now):
1619 * 1) always uses programmed I/O
1620 */
1621 int
1622 spcintr(arg)
1623 void *arg;
1624 {
1625 struct spc_softc *sc = arg;
1626 bus_space_tag_t iot = sc->sc_iot;
1627 bus_space_handle_t ioh = sc->sc_ioh;
1628 u_char ints;
1629 struct spc_acb *acb;
1630 struct scsipi_periph *periph;
1631 struct spc_tinfo *ti;
1632 int n;
1633
1634 /*
1635 * Disable interrupt.
1636 */
1637 bus_space_write_1(iot, ioh, SCTL, bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB);
1638
1639 SPC_TRACE(("spcintr "));
1640
1641 loop:
1642 /*
1643 * Loop until transfer completion.
1644 */
1645 /*
1646 * First check for abnormal conditions, such as reset.
1647 */
1648 #ifdef x68k /* XXX? */
1649 while ((ints = bus_space_read_1(iot, ioh, INTS)) == 0)
1650 delay(1);
1651 SPC_MISC(("ints = 0x%x ", ints));
1652 #else
1653 ints = bus_space_read_1(iot, ioh, INTS);
1654 SPC_MISC(("ints = 0x%x ", ints));
1655 #endif
1656
1657 if ((ints & INTS_RST) != 0) {
1658 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname);
1659 goto reset;
1660 }
1661
1662 /*
1663 * Check for less serious errors.
1664 */
1665 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) {
1666 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname);
1667 if (sc->sc_prevphase == PH_MSGIN) {
1668 sc->sc_flags |= SPC_DROP_MSGIN;
1669 spc_sched_msgout(sc, SEND_PARITY_ERROR);
1670 } else
1671 spc_sched_msgout(sc, SEND_INIT_DET_ERR);
1672 }
1673
1674 /*
1675 * If we're not already busy doing something test for the following
1676 * conditions:
1677 * 1) We have been reselected by something
1678 * 2) We have selected something successfully
1679 * 3) Our selection process has timed out
1680 * 4) This is really a bus free interrupt just to get a new command
1681 * going?
1682 * 5) Spurious interrupt?
1683 */
1684 switch (sc->sc_state) {
1685 case SPC_IDLE:
1686 case SPC_SELECTING:
1687 SPC_MISC(("ints:0x%02x ", ints));
1688
1689 if ((ints & INTS_SEL) != 0) {
1690 /*
1691 * We don't currently support target mode.
1692 */
1693 printf("%s: target mode selected; going to BUS FREE\n",
1694 sc->sc_dev.dv_xname);
1695
1696 goto sched;
1697 } else if ((ints & INTS_RESEL) != 0) {
1698 SPC_MISC(("reselected "));
1699
1700 /*
1701 * If we're trying to select a target ourselves,
1702 * push our command back into the ready list.
1703 */
1704 if (sc->sc_state == SPC_SELECTING) {
1705 SPC_MISC(("backoff selector "));
1706 SPC_ASSERT(sc->sc_nexus != NULL);
1707 acb = sc->sc_nexus;
1708 sc->sc_nexus = NULL;
1709 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain);
1710 }
1711
1712 /* Save reselection ID. */
1713 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP);
1714
1715 sc->sc_state = SPC_RESELECTED;
1716 } else if ((ints & INTS_CMD_DONE) != 0) {
1717 SPC_MISC(("selected "));
1718
1719 /*
1720 * We have selected a target. Things to do:
1721 * a) Determine what message(s) to send.
1722 * b) Verify that we're still selecting the target.
1723 * c) Mark device as busy.
1724 */
1725 if (sc->sc_state != SPC_SELECTING) {
1726 printf("%s: selection out while idle; resetting\n",
1727 sc->sc_dev.dv_xname);
1728 SPC_BREAK();
1729 goto reset;
1730 }
1731 SPC_ASSERT(sc->sc_nexus != NULL);
1732 acb = sc->sc_nexus;
1733 periph = acb->xs->xs_periph;
1734 ti = &sc->sc_tinfo[periph->periph_target];
1735
1736 sc->sc_msgpriq = SEND_IDENTIFY;
1737 if (acb->flags & ACB_RESET)
1738 sc->sc_msgpriq |= SEND_DEV_RESET;
1739 else if (acb->flags & ACB_ABORT)
1740 sc->sc_msgpriq |= SEND_ABORT;
1741 else {
1742 #if SPC_USE_SYNCHRONOUS
1743 if ((ti->flags & DO_SYNC) != 0)
1744 sc->sc_msgpriq |= SEND_SDTR;
1745 #endif
1746 #if SPC_USE_WIDE
1747 if ((ti->flags & DO_WIDE) != 0)
1748 sc->sc_msgpriq |= SEND_WDTR;
1749 #endif
1750 }
1751
1752 acb->flags |= ACB_NEXUS;
1753 ti->lubusy |= (1 << periph->periph_lun);
1754
1755 /* Do an implicit RESTORE POINTERS. */
1756 sc->sc_dp = acb->data_addr;
1757 sc->sc_dleft = acb->data_length;
1758 sc->sc_cp = (u_char *)&acb->scsipi_cmd;
1759 sc->sc_cleft = acb->scsipi_cmd_length;
1760
1761 /* On our first connection, schedule a timeout. */
1762 if ((acb->xs->xs_control & XS_CTL_POLL) == 0)
1763 callout_reset(&acb->xs->xs_callout,
1764 (acb->timeout * hz) / 1000,
1765 spc_timeout, acb);
1766
1767 sc->sc_state = SPC_CONNECTED;
1768 } else if ((ints & INTS_TIMEOUT) != 0) {
1769 SPC_MISC(("selection timeout "));
1770
1771 if (sc->sc_state != SPC_SELECTING) {
1772 printf("%s: selection timeout while idle; resetting\n",
1773 sc->sc_dev.dv_xname);
1774 SPC_BREAK();
1775 goto reset;
1776 }
1777 SPC_ASSERT(sc->sc_nexus != NULL);
1778 acb = sc->sc_nexus;
1779
1780 delay(250);
1781
1782 acb->xs->error = XS_SELTIMEOUT;
1783 goto finish;
1784 } else {
1785 if (sc->sc_state != SPC_IDLE) {
1786 printf("%s: BUS FREE while not idle; state=%d\n",
1787 sc->sc_dev.dv_xname, sc->sc_state);
1788 SPC_BREAK();
1789 goto out;
1790 }
1791
1792 goto sched;
1793 }
1794
1795 /*
1796 * Turn off selection stuff, and prepare to catch bus free
1797 * interrupts, parity errors, and phase changes.
1798 */
1799
1800 sc->sc_flags = 0;
1801 sc->sc_prevphase = PH_INVALID;
1802 goto dophase;
1803 }
1804
1805 if ((ints & INTS_DISCON) != 0) {
1806 /* We've gone to BUS FREE phase. */
1807 bus_space_write_1(iot, ioh, PCTL,
1808 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB);
1809 /* disable disconnect interrupt */
1810 bus_space_write_1(iot, ioh, INTS, ints);
1811 /* XXX reset interrput */
1812
1813 switch (sc->sc_state) {
1814 case SPC_RESELECTED:
1815 goto sched;
1816
1817 case SPC_CONNECTED:
1818 SPC_ASSERT(sc->sc_nexus != NULL);
1819 acb = sc->sc_nexus;
1820
1821 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE
1822 if (sc->sc_prevphase == PH_MSGOUT) {
1823 /*
1824 * If the target went to BUS FREE phase during
1825 * or immediately after sending a SDTR or WDTR
1826 * message, disable negotiation.
1827 */
1828 periph = acb->xs->xs_periph;
1829 ti = &sc->sc_tinfo[periph->periph_target];
1830 switch (sc->sc_lastmsg) {
1831 #if SPC_USE_SYNCHRONOUS
1832 case SEND_SDTR:
1833 ti->flags &= ~DO_SYNC;
1834 ti->period = ti->offset = 0;
1835 break;
1836 #endif
1837 #if SPC_USE_WIDE
1838 case SEND_WDTR:
1839 ti->flags &= ~DO_WIDE;
1840 ti->width = 0;
1841 break;
1842 #endif
1843 }
1844 }
1845 #endif
1846
1847 if ((sc->sc_flags & SPC_ABORTING) == 0) {
1848 /*
1849 * Section 5.1.1 of the SCSI 2 spec suggests
1850 * issuing a REQUEST SENSE following an
1851 * unexpected disconnect. Some devices go into
1852 * a contingent allegiance condition when
1853 * disconnecting, and this is necessary to
1854 * clean up their state.
1855 */
1856 printf("%s: unexpected disconnect; sending REQUEST SENSE\n",
1857 sc->sc_dev.dv_xname);
1858 SPC_BREAK();
1859 acb->target_stat = SCSI_CHECK;
1860 acb->xs->error = XS_NOERROR;
1861 goto finish;
1862 }
1863
1864 acb->xs->error = XS_DRIVER_STUFFUP;
1865 goto finish;
1866
1867 case SPC_DISCONNECT:
1868 SPC_ASSERT(sc->sc_nexus != NULL);
1869 acb = sc->sc_nexus;
1870 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain);
1871 sc->sc_nexus = NULL;
1872 goto sched;
1873
1874 case SPC_CMDCOMPLETE:
1875 SPC_ASSERT(sc->sc_nexus != NULL);
1876 acb = sc->sc_nexus;
1877 goto finish;
1878 }
1879 }
1880 else if ((ints & INTS_CMD_DONE) != 0 &&
1881 sc->sc_prevphase == PH_MSGIN && sc->sc_state != SPC_CONNECTED)
1882 goto out;
1883
1884 dophase:
1885 #if 0
1886 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) {
1887 /* Wait for REQINIT. */
1888 goto out;
1889 }
1890 #else
1891 bus_space_write_1(iot, ioh, INTS, ints);
1892 ints = 0;
1893 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0)
1894 delay(1); /* need timeout XXX */
1895 #endif
1896
1897 /*
1898 * State transition.
1899 */
1900 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK;
1901 /* bus_space_write_1(iot, ioh, PCTL, sc->sc_phase);*/
1902
1903 SPC_MISC(("phase=%d\n", sc->sc_phase));
1904 switch (sc->sc_phase) {
1905 case PH_MSGOUT:
1906 if (sc->sc_state != SPC_CONNECTED &&
1907 sc->sc_state != SPC_RESELECTED)
1908 break;
1909 spc_msgout(sc);
1910 sc->sc_prevphase = PH_MSGOUT;
1911 goto loop;
1912
1913 case PH_MSGIN:
1914 if (sc->sc_state != SPC_CONNECTED &&
1915 sc->sc_state != SPC_RESELECTED)
1916 break;
1917 spc_msgin(sc);
1918 sc->sc_prevphase = PH_MSGIN;
1919 goto loop;
1920
1921 case PH_CMD:
1922 if (sc->sc_state != SPC_CONNECTED)
1923 break;
1924 #if SPC_DEBUG
1925 if ((spc_debug & SPC_SHOWMISC) != 0) {
1926 SPC_ASSERT(sc->sc_nexus != NULL);
1927 acb = sc->sc_nexus;
1928 printf("cmd=0x%02x+%d ",
1929 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length-1);
1930 }
1931 #endif
1932 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft);
1933 sc->sc_cp += n;
1934 sc->sc_cleft -= n;
1935 sc->sc_prevphase = PH_CMD;
1936 goto loop;
1937
1938 case PH_DATAOUT:
1939 if (sc->sc_state != SPC_CONNECTED)
1940 break;
1941 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft));
1942 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft);
1943 sc->sc_dp += n;
1944 sc->sc_dleft -= n;
1945 sc->sc_prevphase = PH_DATAOUT;
1946 goto loop;
1947
1948 case PH_DATAIN:
1949 if (sc->sc_state != SPC_CONNECTED)
1950 break;
1951 SPC_MISC(("datain "));
1952 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft);
1953 sc->sc_dp += n;
1954 sc->sc_dleft -= n;
1955 sc->sc_prevphase = PH_DATAIN;
1956 goto loop;
1957
1958 case PH_STAT:
1959 if (sc->sc_state != SPC_CONNECTED)
1960 break;
1961 SPC_ASSERT(sc->sc_nexus != NULL);
1962 acb = sc->sc_nexus;
1963 /*acb->target_stat = bus_space_read_1(iot, ioh, DREG);*/
1964 spc_datain_pio(sc, &acb->target_stat, 1);
1965 SPC_MISC(("target_stat=0x%02x ", acb->target_stat));
1966 sc->sc_prevphase = PH_STAT;
1967 goto loop;
1968 }
1969
1970 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname);
1971 SPC_BREAK();
1972 reset:
1973 spc_init(sc);
1974 return 1;
1975
1976 finish:
1977 callout_stop(&acb->xs->xs_callout);
1978 bus_space_write_1(iot, ioh, INTS, ints);
1979 ints = 0;
1980 spc_done(sc, acb);
1981 goto out;
1982
1983 sched:
1984 sc->sc_state = SPC_IDLE;
1985 spc_sched(sc);
1986 goto out;
1987
1988 out:
1989 if (ints)
1990 bus_space_write_1(iot, ioh, INTS, ints);
1991 bus_space_write_1(iot, ioh, SCTL,
1992 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB);
1993 return 1;
1994 }
1995
1996 void
1997 spc_abort(sc, acb)
1998 struct spc_softc *sc;
1999 struct spc_acb *acb;
2000 {
2001
2002 /* 2 secs for the abort */
2003 acb->timeout = SPC_ABORT_TIMEOUT;
2004 acb->flags |= ACB_ABORT;
2005
2006 if (acb == sc->sc_nexus) {
2007 /*
2008 * If we're still selecting, the message will be scheduled
2009 * after selection is complete.
2010 */
2011 if (sc->sc_state == SPC_CONNECTED)
2012 spc_sched_msgout(sc, SEND_ABORT);
2013 } else {
2014 spc_dequeue(sc, acb);
2015 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain);
2016 if (sc->sc_state == SPC_IDLE)
2017 spc_sched(sc);
2018 }
2019 }
2020
2021 void
2022 spc_timeout(arg)
2023 void *arg;
2024 {
2025 struct spc_acb *acb = arg;
2026 struct scsipi_xfer *xs = acb->xs;
2027 struct scsipi_periph *periph = xs->xs_periph;
2028 struct spc_softc *sc = (void*)periph->periph_channel->chan_adapter->adapt_dev;
2029 int s;
2030
2031 scsipi_printaddr(periph);
2032 printf("timed out");
2033
2034 s = splbio();
2035
2036 if (acb->flags & ACB_ABORT) {
2037 /* abort timed out */
2038 printf(" AGAIN\n");
2039 /* XXX Must reset! */
2040 } else {
2041 /* abort the operation that has timed out */
2042 printf("\n");
2043 acb->xs->error = XS_TIMEOUT;
2044 spc_abort(sc, acb);
2045 }
2046
2047 splx(s);
2048 }
2049
2050 #ifdef SPC_DEBUG
2052 /*
2053 * The following functions are mostly used for debugging purposes, either
2054 * directly called from the driver or from the kernel debugger.
2055 */
2056
2057 void
2058 spc_show_scsi_cmd(acb)
2059 struct spc_acb *acb;
2060 {
2061 u_char *b = (u_char *)&acb->scsipi_cmd;
2062 int i;
2063
2064 scsipi_printaddr(acb->xs->xs_periph);
2065 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) {
2066 for (i = 0; i < acb->scsipi_cmd_length; i++) {
2067 if (i)
2068 printf(",");
2069 printf("%x", b[i]);
2070 }
2071 printf("\n");
2072 } else
2073 printf("RESET\n");
2074 }
2075
2076 void
2077 spc_print_acb(acb)
2078 struct spc_acb *acb;
2079 {
2080
2081 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags);
2082 printf(" dp=%p dleft=%d target_stat=%x\n",
2083 acb->data_addr, acb->data_length, acb->target_stat);
2084 spc_show_scsi_cmd(acb);
2085 }
2086
2087 void
2088 spc_print_active_acb()
2089 {
2090 struct spc_acb *acb;
2091 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */
2092
2093 printf("ready list:\n");
2094 for (acb = sc->ready_list.tqh_first; acb != NULL;
2095 acb = acb->chain.tqe_next)
2096 spc_print_acb(acb);
2097 printf("nexus:\n");
2098 if (sc->sc_nexus != NULL)
2099 spc_print_acb(sc->sc_nexus);
2100 printf("nexus list:\n");
2101 for (acb = sc->nexus_list.tqh_first; acb != NULL;
2102 acb = acb->chain.tqe_next)
2103 spc_print_acb(acb);
2104 }
2105
2106 void
2107 spc_dump89352(sc)
2108 struct spc_softc *sc;
2109 {
2110 bus_space_tag_t iot = sc->sc_iot;
2111 bus_space_handle_t ioh = sc->sc_ioh;
2112
2113 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n",
2114 bus_space_read_1(iot, ioh, BDID),
2115 bus_space_read_1(iot, ioh, SCTL),
2116 bus_space_read_1(iot, ioh, SCMD),
2117 bus_space_read_1(iot, ioh, TMOD));
2118 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n",
2119 bus_space_read_1(iot, ioh, INTS),
2120 bus_space_read_1(iot, ioh, PSNS),
2121 bus_space_read_1(iot, ioh, SSTS),
2122 bus_space_read_1(iot, ioh, SERR),
2123 bus_space_read_1(iot, ioh, PCTL));
2124 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n",
2125 bus_space_read_1(iot, ioh, MBC),
2126 #if 0
2127 bus_space_read_1(iot, ioh, DREG),
2128 #else
2129 0,
2130 #endif
2131 bus_space_read_1(iot, ioh, TEMP),
2132 bus_space_read_1(iot, ioh, TCH),
2133 bus_space_read_1(iot, ioh, TCM));
2134 printf(" TCL=%x EXBF=%x\n",
2135 bus_space_read_1(iot, ioh, TCL),
2136 bus_space_read_1(iot, ioh, EXBF));
2137 }
2138
2139 void
2140 spc_dump_driver(sc)
2141 struct spc_softc *sc;
2142 {
2143 struct spc_tinfo *ti;
2144 int i;
2145
2146 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase);
2147 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n",
2148 sc->sc_state, sc->sc_imess[0],
2149 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg);
2150 for (i = 0; i < 7; i++) {
2151 ti = &sc->sc_tinfo[i];
2152 printf("tinfo%d: %d cmds %d disconnects %d timeouts",
2153 i, ti->cmds, ti->dconns, ti->touts);
2154 printf(" %d senses flags=%x\n", ti->senses, ti->flags);
2155 }
2156 }
2157 #endif
2158