mb89352.c revision 1.9 1 /* $NetBSD: mb89352.c,v 1.9 2001/11/04 12:05:42 tsutsui Exp $ */
2 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */
3
4 #ifdef DDB
5 #define integrate
6 #else
7 #define integrate __inline static
8 #endif
9
10 /*-
11 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc.
12 * All rights reserved.
13 *
14 * This code is derived from software contributed to The NetBSD Foundation
15 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by Charles M. Hannum.
28 * 4. The name of the author may not be used to endorse or promote products
29 * derived from this software without specific prior written permission.
30 *
31 * Copyright (c) 1994 Jarle Greipsland
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
47 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
48 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
49 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
51 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
53 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
54 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
55 * POSSIBILITY OF SUCH DAMAGE.
56 */
57 /*
58 * [NetBSD for NEC PC-98 series]
59 * Copyright (c) 1996, 1997, 1998
60 * NetBSD/pc98 porting staff. All rights reserved.
61 * Copyright (c) 1996, 1997, 1998
62 * Kouichi Matsuda. All rights reserved.
63 */
64
65 /*
66 * Acknowledgements: Many of the algorithms used in this driver are
67 * inspired by the work of Julian Elischer (julian (at) tfs.com) and
68 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million!
69 */
70
71 /* TODO list:
72 * 1) Get the DMA stuff working.
73 * 2) Get the iov/uio stuff working. Is this a good thing ???
74 * 3) Get the synch stuff working.
75 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.?
76 */
77
78 /*
79 * A few customizable items:
80 */
81
82 /* Use doubleword transfers to/from SCSI chip. Note: This requires
83 * motherboard support. Basicly, some motherboard chipsets are able to
84 * split a 32 bit I/O operation into two 16 bit I/O operations,
85 * transparently to the processor. This speeds up some things, notably long
86 * data transfers.
87 */
88 #define SPC_USE_DWORDS 0
89
90 /* Synchronous data transfers? */
91 #define SPC_USE_SYNCHRONOUS 0
92 #define SPC_SYNC_REQ_ACK_OFS 8
93
94 /* Wide data transfers? */
95 #define SPC_USE_WIDE 0
96 #define SPC_MAX_WIDTH 0
97
98 /* Max attempts made to transmit a message */
99 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */
100
101 /*
102 * Some spin loop parameters (essentially how long to wait some places)
103 * The problem(?) is that sometimes we expect either to be able to transmit a
104 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid
105 * returning from the interrupt just to get yanked back for the next byte we
106 * may spin in the interrupt routine waiting for this byte to come. How long?
107 * This is really (SCSI) device and processor dependent. Tuneable, I guess.
108 */
109 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */
110 #define SPC_MSGOUT_SPIN 1
111
112 /* Include debug functions? At the end of this file there are a bunch of
113 * functions that will print out various information regarding queued SCSI
114 * commands, driver state and chip contents. You can call them from the
115 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the
116 * kernel uses less memory) but you lose the debugging facilities.
117 */
118 #define SPC_DEBUG 1
119
120 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */
121
122 /* End of customizable parameters */
123
124 /*
125 * MB89352 SCSI Protocol Controller (SPC) routines.
126 */
127
128 #include "opt_ddb.h"
129
130 #include <sys/types.h>
131 #include <sys/param.h>
132 #include <sys/systm.h>
133 #include <sys/kernel.h>
134 #include <sys/errno.h>
135 #include <sys/ioctl.h>
136 #include <sys/device.h>
137 #include <sys/buf.h>
138 #include <sys/proc.h>
139 #include <sys/user.h>
140 #include <sys/queue.h>
141
142 #include <machine/intr.h>
143 #include <machine/bus.h>
144
145 #include <dev/scsipi/scsi_all.h>
146 #include <dev/scsipi/scsipi_all.h>
147 #include <dev/scsipi/scsi_message.h>
148 #include <dev/scsipi/scsiconf.h>
149
150 #include <dev/ic/mb89352reg.h>
151 #include <dev/ic/mb89352var.h>
152
153 #ifndef DDB
155 #define Debugger() panic("should call debugger here (mb89352.c)")
156 #endif /* ! DDB */
157
158 #if SPC_DEBUG
159 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */
160 #endif
161
162 void spc_minphys __P((struct buf *));
163 void spc_done __P((struct spc_softc *, struct spc_acb *));
164 void spc_dequeue __P((struct spc_softc *, struct spc_acb *));
165 void spc_scsipi_request __P((struct scsipi_channel *,
166 scsipi_adapter_req_t, void *));
167 int spc_poll __P((struct spc_softc *, struct scsipi_xfer *, int));
168 integrate void spc_sched_msgout __P((struct spc_softc *, u_char));
169 integrate void spc_setsync __P((struct spc_softc *, struct spc_tinfo *));
170 void spc_select __P((struct spc_softc *, struct spc_acb *));
171 void spc_timeout __P((void *));
172 void spc_scsi_reset __P((struct spc_softc *));
173 void spc_reset __P((struct spc_softc *));
174 void spc_free_acb __P((struct spc_softc *, struct spc_acb *, int));
175 struct spc_acb* spc_get_acb __P((struct spc_softc *));
176 int spc_reselect __P((struct spc_softc *, int));
177 void spc_msgin __P((struct spc_softc *));
178 void spc_abort __P((struct spc_softc *, struct spc_acb *));
179 void spc_msgout __P((struct spc_softc *));
180 int spc_dataout_pio __P((struct spc_softc *, u_char *, int));
181 int spc_datain_pio __P((struct spc_softc *, u_char *, int));
182 #if SPC_DEBUG
183 void spc_print_acb __P((struct spc_acb *));
184 void spc_dump_driver __P((struct spc_softc *));
185 void spc_dump89352 __P((struct spc_softc *));
186 void spc_show_scsi_cmd __P((struct spc_acb *));
187 void spc_print_active_acb __P((void));
188 #endif
189
190 extern struct cfdriver spc_cd;
191
192
193 /*
195 * INITIALIZATION ROUTINES (probe, attach ++)
196 */
197
198 /*
199 * Do the real search-for-device.
200 * Prerequisite: sc->sc_iobase should be set to the proper value
201 */
202 int
203 spc_find(iot, ioh, bdid)
204 bus_space_tag_t iot;
205 bus_space_handle_t ioh;
206 int bdid;
207 {
208 long timeout = SPC_ABORT_TIMEOUT;
209
210 SPC_TRACE(("spc: probing for spc-chip\n"));
211 /*
212 * Disable interrupts then reset the FUJITSU chip.
213 */
214 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST);
215 bus_space_write_1(iot, ioh, SCMD, 0);
216 bus_space_write_1(iot, ioh, PCTL, 0);
217 bus_space_write_1(iot, ioh, TEMP, 0);
218 bus_space_write_1(iot, ioh, TCH, 0);
219 bus_space_write_1(iot, ioh, TCM, 0);
220 bus_space_write_1(iot, ioh, TCL, 0);
221 bus_space_write_1(iot, ioh, INTS, 0);
222 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB);
223 bus_space_write_1(iot, ioh, BDID, bdid);
224 delay(400);
225 bus_space_write_1(iot, ioh, SCTL, bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE);
226
227 /* The following detection is derived from spc.c
228 * (by Takahide Matsutsuka) in FreeBSD/pccard-test.
229 */
230 while (bus_space_read_1(iot, ioh, PSNS) && timeout)
231 timeout--;
232 if (!timeout) {
233 printf("spc: find failed\n");
234 return 0;
235 }
236
237 SPC_START(("SPC found"));
238 return 1;
239 }
240
241 void
242 spcattach(sc)
243 struct spc_softc *sc;
244 {
245
246 SPC_TRACE(("spcattach "));
247 sc->sc_state = SPC_INIT;
248
249 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */
250
251 #if SPC_USE_SYNCHRONOUS
252 /*
253 * These are the bounds of the sync period, based on the frequency of
254 * the chip's clock input and the size and offset of the sync period
255 * register.
256 *
257 * For a 20Mhz clock, this gives us 25, or 100nS, or 10MB/s, as a
258 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a
259 * minimum transfer rate.
260 */
261 sc->sc_minsync = (2 * 250) / sc->sc_freq;
262 sc->sc_maxsync = (9 * 250) / sc->sc_freq;
263 #endif
264
265 spc_init(sc); /* Init chip and driver */
266
267 /*
268 * Fill in the adapter.
269 */
270 sc->sc_adapter.adapt_dev = &sc->sc_dev;
271 sc->sc_adapter.adapt_nchannels = 1;
272 sc->sc_adapter.adapt_openings = 7;
273 sc->sc_adapter.adapt_max_periph = 1;
274 sc->sc_adapter.adapt_minphys = spc_minphys;
275 sc->sc_adapter.adapt_request = spc_scsipi_request;
276
277 sc->sc_channel.chan_adapter = &sc->sc_adapter;
278 sc->sc_channel.chan_bustype = &scsi_bustype;
279 sc->sc_channel.chan_channel = 0;
280 sc->sc_channel.chan_ntargets = 8;
281 sc->sc_channel.chan_nluns = 8;
282 sc->sc_channel.chan_id = sc->sc_initiator;
283
284 /*
285 * ask the adapter what subunits are present
286 */
287 config_found((struct device*)sc, &sc->sc_channel, scsiprint);
288 }
289
290 /*
291 * Initialize MB89352 chip itself
292 * The following conditions should hold:
293 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc
294 * must be valid.
295 */
296 void
297 spc_reset(sc)
298 struct spc_softc *sc;
299 {
300 bus_space_tag_t iot = sc->sc_iot;
301 bus_space_handle_t ioh = sc->sc_ioh;
302
303 SPC_TRACE(("spc_reset "));
304 /*
305 * Disable interrupts then reset the FUJITSU chip.
306 */
307 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST);
308 bus_space_write_1(iot, ioh, SCMD, 0);
309 bus_space_write_1(iot, ioh, PCTL, 0);
310 bus_space_write_1(iot, ioh, TEMP, 0);
311 bus_space_write_1(iot, ioh, TCH, 0);
312 bus_space_write_1(iot, ioh, TCM, 0);
313 bus_space_write_1(iot, ioh, TCL, 0);
314 bus_space_write_1(iot, ioh, INTS, 0);
315 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB);
316 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator);
317 delay(400);
318 bus_space_write_1(iot, ioh, SCTL, bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE);
319 }
320
321
322 /*
323 * Pull the SCSI RST line for 500us.
324 */
325 void
326 spc_scsi_reset(sc)
327 struct spc_softc *sc;
328 {
329 bus_space_tag_t iot = sc->sc_iot;
330 bus_space_handle_t ioh = sc->sc_ioh;
331
332 SPC_TRACE(("spc_scsi_reset "));
333 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) | SCMD_RST);
334 delay(500);
335 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST);
336 delay(50);
337 }
338
339 /*
340 * Initialize spc SCSI driver.
341 */
342 void
343 spc_init(sc)
344 struct spc_softc *sc;
345 {
346 struct spc_acb *acb;
347 int r;
348
349 SPC_TRACE(("spc_init "));
350 spc_reset(sc);
351 spc_scsi_reset(sc);
352 spc_reset(sc);
353
354 if (sc->sc_state == SPC_INIT) {
355 /* First time through; initialize. */
356 TAILQ_INIT(&sc->ready_list);
357 TAILQ_INIT(&sc->nexus_list);
358 TAILQ_INIT(&sc->free_list);
359 sc->sc_nexus = NULL;
360 acb = sc->sc_acb;
361 memset(acb, 0, sizeof(sc->sc_acb));
362 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) {
363 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain);
364 acb++;
365 }
366 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo));
367 } else {
368 /* Cancel any active commands. */
369 sc->sc_state = SPC_CLEANING;
370 if ((acb = sc->sc_nexus) != NULL) {
371 acb->xs->error = XS_DRIVER_STUFFUP;
372 callout_stop(&acb->xs->xs_callout);
373 spc_done(sc, acb);
374 }
375 while ((acb = sc->nexus_list.tqh_first) != NULL) {
376 acb->xs->error = XS_DRIVER_STUFFUP;
377 callout_stop(&acb->xs->xs_callout);
378 spc_done(sc, acb);
379 }
380 }
381
382 sc->sc_prevphase = PH_INVALID;
383 for (r = 0; r < 8; r++) {
384 struct spc_tinfo *ti = &sc->sc_tinfo[r];
385
386 ti->flags = 0;
387 #if SPC_USE_SYNCHRONOUS
388 ti->flags |= DO_SYNC;
389 ti->period = sc->sc_minsync;
390 ti->offset = SPC_SYNC_REQ_ACK_OFS;
391 #else
392 ti->period = ti->offset = 0;
393 #endif
394 #if SPC_USE_WIDE
395 ti->flags |= DO_WIDE;
396 ti->width = SPC_MAX_WIDTH;
397 #else
398 ti->width = 0;
399 #endif
400 }
401
402 sc->sc_state = SPC_IDLE;
403 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL,
404 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB);
405 }
406
407 void
408 spc_free_acb(sc, acb, flags)
409 struct spc_softc *sc;
410 struct spc_acb *acb;
411 int flags;
412 {
413 int s;
414
415 SPC_TRACE(("spc_free_acb "));
416 s = splbio();
417
418 acb->flags = 0;
419 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain);
420 splx(s);
421 }
422
423 struct spc_acb *
424 spc_get_acb(sc)
425 struct spc_softc *sc;
426 {
427 struct spc_acb *acb;
428 int s;
429
430 SPC_TRACE(("spc_get_acb "));
431 s = splbio();
432 acb = TAILQ_FIRST(&sc->free_list);
433 if (acb != NULL) {
434 TAILQ_REMOVE(&sc->free_list, acb, chain);
435 acb->flags |= ACB_ALLOC;
436 }
437 splx(s);
438 return acb;
439 }
440
441 /*
443 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
444 */
445
446 /*
447 * Expected sequence:
448 * 1) Command inserted into ready list
449 * 2) Command selected for execution
450 * 3) Command won arbitration and has selected target device
451 * 4) Send message out (identify message, eventually also sync.negotiations)
452 * 5) Send command
453 * 5a) Receive disconnect message, disconnect.
454 * 5b) Reselected by target
455 * 5c) Receive identify message from target.
456 * 6) Send or receive data
457 * 7) Receive status
458 * 8) Receive message (command complete etc.)
459 */
460
461 /*
462 * Start a SCSI-command
463 * This function is called by the higher level SCSI-driver to queue/run
464 * SCSI-commands.
465 */
466 void
467 spc_scsipi_request(chan, req, arg)
468 struct scsipi_channel *chan;
469 scsipi_adapter_req_t req;
470 void *arg;
471 {
472 struct scsipi_xfer *xs;
473 struct scsipi_periph *periph;
474 struct spc_softc *sc = (void *)chan->chan_adapter->adapt_dev;
475 struct spc_acb *acb;
476 int s, flags;
477
478 switch (req) {
479 case ADAPTER_REQ_RUN_XFER:
480 xs = arg;
481 periph = xs->xs_periph;
482 SPC_TRACE(("spc_scsipi_request "));
483 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen,
484 periph->periph_target));
485
486 flags = xs->xs_control;
487 if ((acb = spc_get_acb(sc)) == NULL) {
488 xs->error = XS_DRIVER_STUFFUP;
489 scsipi_done(xs);
490 return;
491 }
492
493 /* Initialize acb */
494 acb->xs = xs;
495 acb->timeout = xs->timeout;
496
497 if (xs->xs_control & XS_CTL_RESET) {
498 acb->flags |= ACB_RESET;
499 acb->scsipi_cmd_length = 0;
500 acb->data_length = 0;
501 } else {
502 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen);
503 #if 1
504 acb->scsipi_cmd.bytes[0] |= periph->periph_lun << 5; /* XXX? */
505 #endif
506 acb->scsipi_cmd_length = xs->cmdlen;
507 acb->data_addr = xs->data;
508 acb->data_length = xs->datalen;
509 }
510 acb->target_stat = 0;
511
512 s = splbio();
513
514 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain);
515 /*
516 * Start scheduling unless a queue process is in progress.
517 */
518 if (sc->sc_state == SPC_IDLE)
519 spc_sched(sc);
520 /*
521 * After successful sending, check if we should return just now.
522 * If so, return SUCCESSFULLY_QUEUED.
523 */
524
525 splx(s);
526
527 if ((flags & XS_CTL_POLL) == 0)
528 return;
529
530 /* Not allowed to use interrupts, use polling instead */
531 s = splbio();
532 if (spc_poll(sc, xs, acb->timeout)) {
533 spc_timeout(acb);
534 if (spc_poll(sc, xs, acb->timeout))
535 spc_timeout(acb);
536 }
537 splx(s);
538 return;
539 case ADAPTER_REQ_GROW_RESOURCES:
540 /* XXX Not supported. */
541 return;
542 case ADAPTER_REQ_SET_XFER_MODE:
543 /* XXX Not supported. */
544 return;
545 }
546 }
547
548 /*
549 * Adjust transfer size in buffer structure
550 */
551 void
552 spc_minphys(bp)
553 struct buf *bp;
554 {
555
556 SPC_TRACE(("spc_minphys "));
557 minphys(bp);
558 }
559
560 /*
561 * Used when interrupt driven I/O isn't allowed, e.g. during boot.
562 */
563 int
564 spc_poll(sc, xs, count)
565 struct spc_softc *sc;
566 struct scsipi_xfer *xs;
567 int count;
568 {
569 bus_space_tag_t iot = sc->sc_iot;
570 bus_space_handle_t ioh = sc->sc_ioh;
571
572 SPC_TRACE(("spc_poll "));
573 while (count) {
574 /*
575 * If we had interrupts enabled, would we
576 * have got an interrupt?
577 */
578 if (bus_space_read_1(iot, ioh, INTS) != 0)
579 spcintr(sc);
580 if ((xs->xs_status & XS_STS_DONE) != 0)
581 return 0;
582 delay(1000);
583 count--;
584 }
585 return 1;
586 }
587
588 /*
590 * LOW LEVEL SCSI UTILITIES
591 */
592
593 integrate void
594 spc_sched_msgout(sc, m)
595 struct spc_softc *sc;
596 u_char m;
597 {
598 bus_space_tag_t iot = sc->sc_iot;
599 bus_space_handle_t ioh = sc->sc_ioh;
600
601 SPC_TRACE(("spc_sched_msgout "));
602 if (sc->sc_msgpriq == 0)
603 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN);
604 sc->sc_msgpriq |= m;
605 }
606
607 /*
608 * Set synchronous transfer offset and period.
609 */
610 integrate void
611 spc_setsync(sc, ti)
612 struct spc_softc *sc;
613 struct spc_tinfo *ti;
614 {
615 #if SPC_USE_SYNCHRONOUS
616 bus_space_tag_t iot = sc->sc_iot;
617 bus_space_handle_t ioh = sc->sc_ioh;
618
619 SPC_TRACE(("spc_setsync "));
620 if (ti->offset != 0)
621 bus_space_write_1(iot, ioh, TMOD,
622 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset);
623 else
624 bus_space_write_1(iot, ioh, TMOD, 0);
625 #endif
626 }
627
628 /*
629 * Start a selection. This is used by spc_sched() to select an idle target.
630 */
631 void
632 spc_select(sc, acb)
633 struct spc_softc *sc;
634 struct spc_acb *acb;
635 {
636 struct scsipi_periph *periph = acb->xs->xs_periph;
637 int target = periph->periph_target;
638 struct spc_tinfo *ti = &sc->sc_tinfo[target];
639 bus_space_tag_t iot = sc->sc_iot;
640 bus_space_handle_t ioh = sc->sc_ioh;
641
642 SPC_TRACE(("spc_select "));
643 spc_setsync(sc, ti);
644
645 #if 0
646 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN);
647 #endif
648 #ifdef x68k /* XXX? */
649 do {
650 asm ("nop");
651 } while (bus_space_read_1(iot, ioh, SSTS) &
652 (SSTS_ACTIVE|SSTS_TARGET|SSTS_BUSY));
653 #endif
654
655 bus_space_write_1(iot, ioh, PCTL, 0);
656 bus_space_write_1(iot, ioh, TEMP, (1 << sc->sc_initiator) | (1 << target));
657 /*
658 * Setup BSY timeout (selection timeout).
659 * 250ms according to the SCSI specification.
660 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k)
661 * To setup 256ms timeout,
662 * 128000ns/200ns = X * 256 + 15
663 * 640 - 15 = X * 256
664 * X = 625 / 256
665 * X = 2 + 113 / 256
666 * ==> tch = 2, tcm = 113 (correct?)
667 */
668 bus_space_write_1(iot, ioh, TCH, 2);
669 bus_space_write_1(iot, ioh, TCM, 113);
670 /* Time to the information transfer phase start. */
671 bus_space_write_1(iot, ioh, TCL, 3);
672 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT);
673
674 sc->sc_state = SPC_SELECTING;
675 }
676
677 int
678 spc_reselect(sc, message)
679 struct spc_softc *sc;
680 int message;
681 {
682 u_char selid, target, lun;
683 struct spc_acb *acb;
684 struct scsipi_periph *periph;
685 struct spc_tinfo *ti;
686
687 SPC_TRACE(("spc_reselect "));
688 /*
689 * The SCSI chip made a snapshot of the data bus while the reselection
690 * was being negotiated. This enables us to determine which target did
691 * the reselect.
692 */
693 selid = sc->sc_selid & ~(1 << sc->sc_initiator);
694 if (selid & (selid - 1)) {
695 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n",
696 sc->sc_dev.dv_xname, selid);
697 SPC_BREAK();
698 goto reset;
699 }
700
701 /*
702 * Search wait queue for disconnected cmd
703 * The list should be short, so I haven't bothered with
704 * any more sophisticated structures than a simple
705 * singly linked list.
706 */
707 target = ffs(selid) - 1;
708 lun = message & 0x07;
709 for (acb = sc->nexus_list.tqh_first; acb != NULL;
710 acb = acb->chain.tqe_next) {
711 periph = acb->xs->xs_periph;
712 if (periph->periph_target == target &&
713 periph->periph_lun == lun)
714 break;
715 }
716 if (acb == NULL) {
717 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n",
718 sc->sc_dev.dv_xname, target, lun);
719 SPC_BREAK();
720 goto abort;
721 }
722
723 /* Make this nexus active again. */
724 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
725 sc->sc_state = SPC_CONNECTED;
726 sc->sc_nexus = acb;
727 ti = &sc->sc_tinfo[target];
728 ti->lubusy |= (1 << lun);
729 spc_setsync(sc, ti);
730
731 if (acb->flags & ACB_RESET)
732 spc_sched_msgout(sc, SEND_DEV_RESET);
733 else if (acb->flags & ACB_ABORT)
734 spc_sched_msgout(sc, SEND_ABORT);
735
736 /* Do an implicit RESTORE POINTERS. */
737 sc->sc_dp = acb->data_addr;
738 sc->sc_dleft = acb->data_length;
739 sc->sc_cp = (u_char *)&acb->scsipi_cmd;
740 sc->sc_cleft = acb->scsipi_cmd_length;
741
742 return (0);
743
744 reset:
745 spc_sched_msgout(sc, SEND_DEV_RESET);
746 return (1);
747
748 abort:
749 spc_sched_msgout(sc, SEND_ABORT);
750 return (1);
751 }
752
753 /*
755 * Schedule a SCSI operation. This has now been pulled out of the interrupt
756 * handler so that we may call it from spc_scsi_cmd and spc_done. This may
757 * save us an unecessary interrupt just to get things going. Should only be
758 * called when state == SPC_IDLE and at bio pl.
759 */
760 void
761 spc_sched(sc)
762 struct spc_softc *sc;
763 {
764 struct spc_acb *acb;
765 struct scsipi_periph *periph;
766 struct spc_tinfo *ti;
767
768 /* missing the hw, just return and wait for our hw */
769 if (sc->sc_flags & SPC_INACTIVE)
770 return;
771 SPC_TRACE(("spc_sched "));
772 /*
773 * Find first acb in ready queue that is for a target/lunit pair that
774 * is not busy.
775 */
776 for (acb = sc->ready_list.tqh_first; acb != NULL;
777 acb = acb->chain.tqe_next) {
778 periph = acb->xs->xs_periph;
779 ti = &sc->sc_tinfo[periph->periph_target];
780 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) {
781 SPC_MISC(("selecting %d:%d ",
782 periph->periph_target, periph->periph_lun));
783 TAILQ_REMOVE(&sc->ready_list, acb, chain);
784 sc->sc_nexus = acb;
785 spc_select(sc, acb);
786 return;
787 } else
788 SPC_MISC(("%d:%d busy\n",
789 periph->periph_target, periph->periph_lun));
790 }
791 SPC_MISC(("idle "));
792 /* Nothing to start; just enable reselections and wait. */
793 }
794
795 /*
797 * POST PROCESSING OF SCSI_CMD (usually current)
798 */
799 void
800 spc_done(sc, acb)
801 struct spc_softc *sc;
802 struct spc_acb *acb;
803 {
804 struct scsipi_xfer *xs = acb->xs;
805 struct scsipi_periph *periph = xs->xs_periph;
806 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target];
807
808 SPC_TRACE(("spc_done "));
809
810 if (xs->error == XS_NOERROR) {
811 if (acb->flags & ACB_ABORT) {
812 xs->error = XS_DRIVER_STUFFUP;
813 } else {
814 switch (acb->target_stat) {
815 case SCSI_CHECK:
816 /* First, save the return values */
817 xs->resid = acb->data_length;
818 /* FALLBACK */
819 case SCSI_BUSY:
820 xs->status = acb->target_stat;
821 xs->error = XS_BUSY;
822 break;
823 case SCSI_OK:
824 xs->resid = acb->data_length;
825 break;
826 default:
827 xs->error = XS_DRIVER_STUFFUP;
828 #if SPC_DEBUG
829 printf("%s: spc_done: bad stat 0x%x\n",
830 sc->sc_dev.dv_xname, acb->target_stat);
831 #endif
832 break;
833 }
834 }
835 }
836
837 #if SPC_DEBUG
838 if ((spc_debug & SPC_SHOWMISC) != 0) {
839 if (xs->resid != 0)
840 printf("resid=%d ", xs->resid);
841 else
842 printf("error=%d\n", xs->error);
843 }
844 #endif
845
846 /*
847 * Remove the ACB from whatever queue it happens to be on.
848 */
849 if (acb->flags & ACB_NEXUS)
850 ti->lubusy &= ~(1 << periph->periph_lun);
851 if (acb == sc->sc_nexus) {
852 sc->sc_nexus = NULL;
853 sc->sc_state = SPC_IDLE;
854 spc_sched(sc);
855 } else
856 spc_dequeue(sc, acb);
857
858 spc_free_acb(sc, acb, xs->xs_control);
859 ti->cmds++;
860 scsipi_done(xs);
861 }
862
863 void
864 spc_dequeue(sc, acb)
865 struct spc_softc *sc;
866 struct spc_acb *acb;
867 {
868
869 SPC_TRACE(("spc_dequeue "));
870 if (acb->flags & ACB_NEXUS) {
871 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
872 } else {
873 TAILQ_REMOVE(&sc->ready_list, acb, chain);
874 }
875 }
876
877 /*
879 * INTERRUPT/PROTOCOL ENGINE
880 */
881
882 /*
883 * Precondition:
884 * The SCSI bus is already in the MSGI phase and there is a message byte
885 * on the bus, along with an asserted REQ signal.
886 */
887 void
888 spc_msgin(sc)
889 struct spc_softc *sc;
890 {
891 bus_space_tag_t iot = sc->sc_iot;
892 bus_space_handle_t ioh = sc->sc_ioh;
893 int n;
894
895 SPC_TRACE(("spc_msgin "));
896
897 if (sc->sc_prevphase == PH_MSGIN) {
898 /* This is a continuation of the previous message. */
899 n = sc->sc_imp - sc->sc_imess;
900 goto nextbyte;
901 }
902
903 /* This is a new MESSAGE IN phase. Clean up our state. */
904 sc->sc_flags &= ~SPC_DROP_MSGIN;
905
906 nextmsg:
907 n = 0;
908 sc->sc_imp = &sc->sc_imess[n];
909
910 nextbyte:
911 /*
912 * Read a whole message, but don't ack the last byte. If we reject the
913 * message, we have to assert ATN during the message transfer phase
914 * itself.
915 */
916 for (;;) {
917 #if 0
918 for (;;) {
919 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0)
920 break;
921 /* Wait for REQINIT. XXX Need timeout. */
922 }
923 #endif
924 if (bus_space_read_1(iot, ioh, INTS) != 0) {
925 /*
926 * Target left MESSAGE IN, probably because it
927 * a) noticed our ATN signal, or
928 * b) ran out of messages.
929 */
930 goto out;
931 }
932
933 /* If parity error, just dump everything on the floor. */
934 if ((bus_space_read_1(iot, ioh, SERR) &
935 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) {
936 sc->sc_flags |= SPC_DROP_MSGIN;
937 spc_sched_msgout(sc, SEND_PARITY_ERROR);
938 }
939
940 /* send TRANSFER command. */
941 bus_space_write_1(iot, ioh, TCH, 0);
942 bus_space_write_1(iot, ioh, TCM, 0);
943 bus_space_write_1(iot, ioh, TCL, 1);
944 bus_space_write_1(iot, ioh, PCTL,
945 sc->sc_phase | PCTL_BFINT_ENAB);
946 #ifdef x68k
947 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* | SCMD_PROG_XFR */
948 #else
949 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); /* XXX */
950 #endif
951 for (;;) {
952 /*if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0
953 && (bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)*/
954 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) == 0)
955 break;
956 if (bus_space_read_1(iot, ioh, INTS) != 0)
957 goto out;
958 }
959
960 /* Gather incoming message bytes if needed. */
961 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) {
962 if (n >= SPC_MAX_MSG_LEN) {
963 (void) bus_space_read_1(iot, ioh, DREG);
964 sc->sc_flags |= SPC_DROP_MSGIN;
965 spc_sched_msgout(sc, SEND_REJECT);
966 } else {
967 *sc->sc_imp++ = bus_space_read_1(iot, ioh, DREG);
968 n++;
969 /*
970 * This testing is suboptimal, but most
971 * messages will be of the one byte variety, so
972 * it should not affect performance
973 * significantly.
974 */
975 if (n == 1 && MSG_IS1BYTE(sc->sc_imess[0]))
976 break;
977 if (n == 2 && MSG_IS2BYTE(sc->sc_imess[0]))
978 break;
979 if (n >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) &&
980 n == sc->sc_imess[1] + 2)
981 break;
982 }
983 } else
984 (void) bus_space_read_1(iot, ioh, DREG);
985
986 /*
987 * If we reach this spot we're either:
988 * a) in the middle of a multi-byte message, or
989 * b) dropping bytes.
990 */
991 #if 0
992 /* Ack the last byte read. */
993 /*(void) bus_space_read_1(iot, ioh, DREG);*/
994 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
995 ;
996 #endif
997 }
998
999 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0]));
1000
1001 /* We now have a complete message. Parse it. */
1002 switch (sc->sc_state) {
1003 struct spc_acb *acb;
1004 struct scsipi_periph *periph;
1005 struct spc_tinfo *ti;
1006
1007 case SPC_CONNECTED:
1008 SPC_ASSERT(sc->sc_nexus != NULL);
1009 acb = sc->sc_nexus;
1010 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target];
1011
1012 switch (sc->sc_imess[0]) {
1013 case MSG_CMDCOMPLETE:
1014 if (sc->sc_dleft < 0) {
1015 periph = acb->xs->xs_periph;
1016 printf("%s: %d extra bytes from %d:%d\n",
1017 sc->sc_dev.dv_xname, -sc->sc_dleft,
1018 periph->periph_target, periph->periph_lun);
1019 acb->data_length = 0;
1020 }
1021 acb->xs->resid = acb->data_length = sc->sc_dleft;
1022 sc->sc_state = SPC_CMDCOMPLETE;
1023 break;
1024
1025 case MSG_PARITY_ERROR:
1026 /* Resend the last message. */
1027 spc_sched_msgout(sc, sc->sc_lastmsg);
1028 break;
1029
1030 case MSG_MESSAGE_REJECT:
1031 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg));
1032 switch (sc->sc_lastmsg) {
1033 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE
1034 case SEND_IDENTIFY:
1035 ti->flags &= ~(DO_SYNC | DO_WIDE);
1036 ti->period = ti->offset = 0;
1037 spc_setsync(sc, ti);
1038 ti->width = 0;
1039 break;
1040 #endif
1041 #if SPC_USE_SYNCHRONOUS
1042 case SEND_SDTR:
1043 ti->flags &= ~DO_SYNC;
1044 ti->period = ti->offset = 0;
1045 spc_setsync(sc, ti);
1046 break;
1047 #endif
1048 #if SPC_USE_WIDE
1049 case SEND_WDTR:
1050 ti->flags &= ~DO_WIDE;
1051 ti->width = 0;
1052 break;
1053 #endif
1054 case SEND_INIT_DET_ERR:
1055 spc_sched_msgout(sc, SEND_ABORT);
1056 break;
1057 }
1058 break;
1059
1060 case MSG_NOOP:
1061 break;
1062
1063 case MSG_DISCONNECT:
1064 ti->dconns++;
1065 sc->sc_state = SPC_DISCONNECT;
1066 break;
1067
1068 case MSG_SAVEDATAPOINTER:
1069 acb->data_addr = sc->sc_dp;
1070 acb->data_length = sc->sc_dleft;
1071 break;
1072
1073 case MSG_RESTOREPOINTERS:
1074 sc->sc_dp = acb->data_addr;
1075 sc->sc_dleft = acb->data_length;
1076 sc->sc_cp = (u_char *)&acb->scsipi_cmd;
1077 sc->sc_cleft = acb->scsipi_cmd_length;
1078 break;
1079
1080 case MSG_EXTENDED:
1081 switch (sc->sc_imess[2]) {
1082 #if SPC_USE_SYNCHRONOUS
1083 case MSG_EXT_SDTR:
1084 if (sc->sc_imess[1] != 3)
1085 goto reject;
1086 ti->period = sc->sc_imess[3];
1087 ti->offset = sc->sc_imess[4];
1088 ti->flags &= ~DO_SYNC;
1089 if (ti->offset == 0) {
1090 } else if (ti->period < sc->sc_minsync ||
1091 ti->period > sc->sc_maxsync ||
1092 ti->offset > 8) {
1093 ti->period = ti->offset = 0;
1094 spc_sched_msgout(sc, SEND_SDTR);
1095 } else {
1096 scsipi_printaddr(acb->xs->xs_periph);
1097 printf("sync, offset %d, period %dnsec\n",
1098 ti->offset, ti->period * 4);
1099 }
1100 spc_setsync(sc, ti);
1101 break;
1102 #endif
1103
1104 #if SPC_USE_WIDE
1105 case MSG_EXT_WDTR:
1106 if (sc->sc_imess[1] != 2)
1107 goto reject;
1108 ti->width = sc->sc_imess[3];
1109 ti->flags &= ~DO_WIDE;
1110 if (ti->width == 0) {
1111 } else if (ti->width > SPC_MAX_WIDTH) {
1112 ti->width = 0;
1113 spc_sched_msgout(sc, SEND_WDTR);
1114 } else {
1115 scsipi_printaddr(acb->xs->xs_periph);
1116 printf("wide, width %d\n",
1117 1 << (3 + ti->width));
1118 }
1119 break;
1120 #endif
1121
1122 default:
1123 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n",
1124 sc->sc_dev.dv_xname);
1125 SPC_BREAK();
1126 goto reject;
1127 }
1128 break;
1129
1130 default:
1131 printf("%s: unrecognized MESSAGE; sending REJECT\n",
1132 sc->sc_dev.dv_xname);
1133 SPC_BREAK();
1134 reject:
1135 spc_sched_msgout(sc, SEND_REJECT);
1136 break;
1137 }
1138 break;
1139
1140 case SPC_RESELECTED:
1141 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) {
1142 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n",
1143 sc->sc_dev.dv_xname);
1144 SPC_BREAK();
1145 goto reset;
1146 }
1147
1148 (void) spc_reselect(sc, sc->sc_imess[0]);
1149 break;
1150
1151 default:
1152 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n",
1153 sc->sc_dev.dv_xname);
1154 SPC_BREAK();
1155 reset:
1156 spc_sched_msgout(sc, SEND_DEV_RESET);
1157 break;
1158
1159 #ifdef notdef
1160 abort:
1161 spc_sched_msgout(sc, SEND_ABORT);
1162 break;
1163 #endif
1164 }
1165
1166 /* Ack the last message byte. */
1167 #if 0 /* XXX? */
1168 (void) bus_space_read_1(iot, ioh, DREG);
1169 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
1170 ;
1171 #endif
1172
1173 /* Go get the next message, if any. */
1174 goto nextmsg;
1175
1176 out:
1177 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK);
1178 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0]));
1179 }
1180
1181 /*
1182 * Send the highest priority, scheduled message.
1183 */
1184 void
1185 spc_msgout(sc)
1186 struct spc_softc *sc;
1187 {
1188 bus_space_tag_t iot = sc->sc_iot;
1189 bus_space_handle_t ioh = sc->sc_ioh;
1190 #if SPC_USE_SYNCHRONOUS
1191 struct spc_tinfo *ti;
1192 #endif
1193 int n;
1194
1195 SPC_TRACE(("spc_msgout "));
1196
1197 if (sc->sc_prevphase == PH_MSGOUT) {
1198 if (sc->sc_omp == sc->sc_omess) {
1199 /*
1200 * This is a retransmission.
1201 *
1202 * We get here if the target stayed in MESSAGE OUT
1203 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates
1204 * that all of the previously transmitted messages must
1205 * be sent again, in the same order. Therefore, we
1206 * requeue all the previously transmitted messages, and
1207 * start again from the top. Our simple priority
1208 * scheme keeps the messages in the right order.
1209 */
1210 SPC_MISC(("retransmitting "));
1211 sc->sc_msgpriq |= sc->sc_msgoutq;
1212 /*
1213 * Set ATN. If we're just sending a trivial 1-byte
1214 * message, we'll clear ATN later on anyway.
1215 */
1216 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); /* XXX? */
1217 } else {
1218 /* This is a continuation of the previous message. */
1219 n = sc->sc_omp - sc->sc_omess;
1220 goto nextbyte;
1221 }
1222 }
1223
1224 /* No messages transmitted so far. */
1225 sc->sc_msgoutq = 0;
1226 sc->sc_lastmsg = 0;
1227
1228 nextmsg:
1229 /* Pick up highest priority message. */
1230 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq;
1231 sc->sc_msgpriq &= ~sc->sc_currmsg;
1232 sc->sc_msgoutq |= sc->sc_currmsg;
1233
1234 /* Build the outgoing message data. */
1235 switch (sc->sc_currmsg) {
1236 case SEND_IDENTIFY:
1237 SPC_ASSERT(sc->sc_nexus != NULL);
1238 sc->sc_omess[0] =
1239 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1);
1240 n = 1;
1241 break;
1242
1243 #if SPC_USE_SYNCHRONOUS
1244 case SEND_SDTR:
1245 SPC_ASSERT(sc->sc_nexus != NULL);
1246 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
1247 sc->sc_omess[4] = MSG_EXTENDED;
1248 sc->sc_omess[3] = 3;
1249 sc->sc_omess[2] = MSG_EXT_SDTR;
1250 sc->sc_omess[1] = ti->period >> 2;
1251 sc->sc_omess[0] = ti->offset;
1252 n = 5;
1253 break;
1254 #endif
1255
1256 #if SPC_USE_WIDE
1257 case SEND_WDTR:
1258 SPC_ASSERT(sc->sc_nexus != NULL);
1259 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
1260 sc->sc_omess[3] = MSG_EXTENDED;
1261 sc->sc_omess[2] = 2;
1262 sc->sc_omess[1] = MSG_EXT_WDTR;
1263 sc->sc_omess[0] = ti->width;
1264 n = 4;
1265 break;
1266 #endif
1267
1268 case SEND_DEV_RESET:
1269 sc->sc_flags |= SPC_ABORTING;
1270 sc->sc_omess[0] = MSG_BUS_DEV_RESET;
1271 n = 1;
1272 break;
1273
1274 case SEND_REJECT:
1275 sc->sc_omess[0] = MSG_MESSAGE_REJECT;
1276 n = 1;
1277 break;
1278
1279 case SEND_PARITY_ERROR:
1280 sc->sc_omess[0] = MSG_PARITY_ERROR;
1281 n = 1;
1282 break;
1283
1284 case SEND_INIT_DET_ERR:
1285 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
1286 n = 1;
1287 break;
1288
1289 case SEND_ABORT:
1290 sc->sc_flags |= SPC_ABORTING;
1291 sc->sc_omess[0] = MSG_ABORT;
1292 n = 1;
1293 break;
1294
1295 default:
1296 printf("%s: unexpected MESSAGE OUT; sending NOOP\n",
1297 sc->sc_dev.dv_xname);
1298 SPC_BREAK();
1299 sc->sc_omess[0] = MSG_NOOP;
1300 n = 1;
1301 break;
1302 }
1303 sc->sc_omp = &sc->sc_omess[n];
1304
1305 nextbyte:
1306 /* Send message bytes. */
1307 /* send TRANSFER command. */
1308 bus_space_write_1(iot, ioh, TCH, n >> 16);
1309 bus_space_write_1(iot, ioh, TCM, n >> 8);
1310 bus_space_write_1(iot, ioh, TCL, n);
1311 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1312 #ifdef x68k
1313 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1314 #else
1315 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR);
1316 #endif
1317 for (;;) {
1318 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1319 break;
1320 if (bus_space_read_1(iot, ioh, INTS) != 0)
1321 goto out;
1322 }
1323 for (;;) {
1324 #if 0
1325 for (;;) {
1326 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0)
1327 break;
1328 /* Wait for REQINIT. XXX Need timeout. */
1329 }
1330 #endif
1331 if (bus_space_read_1(iot, ioh, INTS) != 0) {
1332 /*
1333 * Target left MESSAGE OUT, possibly to reject
1334 * our message.
1335 *
1336 * If this is the last message being sent, then we
1337 * deassert ATN, since either the target is going to
1338 * ignore this message, or it's going to ask for a
1339 * retransmission via MESSAGE PARITY ERROR (in which
1340 * case we reassert ATN anyway).
1341 */
1342 #if 0
1343 if (sc->sc_msgpriq == 0)
1344 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN);
1345 #endif
1346 goto out;
1347 }
1348
1349 #if 0
1350 /* Clear ATN before last byte if this is the last message. */
1351 if (n == 1 && sc->sc_msgpriq == 0)
1352 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN);
1353 #endif
1354
1355 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0)
1356 ;
1357 /* Send message byte. */
1358 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp);
1359 --n;
1360 /* Keep track of the last message we've sent any bytes of. */
1361 sc->sc_lastmsg = sc->sc_currmsg;
1362 #if 0
1363 /* Wait for ACK to be negated. XXX Need timeout. */
1364 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
1365 ;
1366 #endif
1367
1368 if (n == 0)
1369 break;
1370 }
1371
1372 /* We get here only if the entire message has been transmitted. */
1373 if (sc->sc_msgpriq != 0) {
1374 /* There are more outgoing messages. */
1375 goto nextmsg;
1376 }
1377
1378 /*
1379 * The last message has been transmitted. We need to remember the last
1380 * message transmitted (in case the target switches to MESSAGE IN phase
1381 * and sends a MESSAGE REJECT), and the list of messages transmitted
1382 * this time around (in case the target stays in MESSAGE OUT phase to
1383 * request a retransmit).
1384 */
1385
1386 out:
1387 /* Disable REQ/ACK protocol. */
1388 }
1389
1390 /*
1392 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc
1393 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted
1394 * and ACK deasserted (i.e. waiting for a data byte)
1395 *
1396 * This new revision has been optimized (I tried) to make the common case fast,
1397 * and the rarer cases (as a result) somewhat more comlex
1398 */
1399 int
1400 spc_dataout_pio(sc, p, n)
1401 struct spc_softc *sc;
1402 u_char *p;
1403 int n;
1404 {
1405 bus_space_tag_t iot = sc->sc_iot;
1406 bus_space_handle_t ioh = sc->sc_ioh;
1407 u_char intstat = 0;
1408 int out = 0;
1409 #define DOUTAMOUNT 8 /* Full FIFO */
1410
1411 SPC_TRACE(("spc_dataout_pio "));
1412 /* send TRANSFER command. */
1413 bus_space_write_1(iot, ioh, TCH, n >> 16);
1414 bus_space_write_1(iot, ioh, TCM, n >> 8);
1415 bus_space_write_1(iot, ioh, TCL, n);
1416 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1417 #ifdef x68k
1418 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1419 #else
1420 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR); /* XXX */
1421 #endif
1422 for (;;) {
1423 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1424 break;
1425 if (bus_space_read_1(iot, ioh, INTS) != 0)
1426 break;
1427 }
1428
1429 /*
1430 * I have tried to make the main loop as tight as possible. This
1431 * means that some of the code following the loop is a bit more
1432 * complex than otherwise.
1433 */
1434 while (n > 0) {
1435 int xfer;
1436
1437 for (;;) {
1438 intstat = bus_space_read_1(iot, ioh, INTS);
1439 /* Wait till buffer is empty. */
1440 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)
1441 break;
1442 /* Break on interrupt. */
1443 if (intstat != 0)
1444 goto phasechange;
1445 }
1446
1447 xfer = min(DOUTAMOUNT, n);
1448
1449 SPC_MISC(("%d> ", xfer));
1450
1451 n -= xfer;
1452 out += xfer;
1453
1454 while (xfer-- > 0) {
1455 bus_space_write_1(iot, ioh, DREG, *p++);
1456 }
1457 }
1458
1459 if (out == 0) {
1460 for (;;) {
1461 if (bus_space_read_1(iot, ioh, INTS) != 0)
1462 break;
1463 }
1464 SPC_MISC(("extra data "));
1465 } else {
1466 /* See the bytes off chip */
1467 for (;;) {
1468 /* Wait till buffer is empty. */
1469 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)
1470 break;
1471 intstat = bus_space_read_1(iot, ioh, INTS);
1472 /* Break on interrupt. */
1473 if (intstat != 0)
1474 goto phasechange;
1475 }
1476 }
1477
1478 phasechange:
1479 /* Stop the FIFO data path. */
1480
1481 if (intstat != 0) {
1482 /* Some sort of phase change. */
1483 int amount;
1484
1485 amount = ((bus_space_read_1(iot, ioh, TCH) << 16) |
1486 (bus_space_read_1(iot, ioh, TCM) << 8) |
1487 bus_space_read_1(iot, ioh, TCL));
1488 if (amount > 0) {
1489 out -= amount;
1490 SPC_MISC(("+%d ", amount));
1491 }
1492 }
1493
1494 /* Turn on ENREQINIT again. */
1495
1496 return out;
1497 }
1498
1499 /*
1501 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc
1502 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted
1503 * and ACK deasserted (i.e. at least one byte is ready).
1504 *
1505 * For now, uses a pretty dumb algorithm, hangs around until all data has been
1506 * transferred. This, is OK for fast targets, but not so smart for slow
1507 * targets which don't disconnect or for huge transfers.
1508 */
1509 int
1510 spc_datain_pio(sc, p, n)
1511 struct spc_softc *sc;
1512 u_char *p;
1513 int n;
1514 {
1515 bus_space_tag_t iot = sc->sc_iot;
1516 bus_space_handle_t ioh = sc->sc_ioh;
1517 u_short intstat;
1518 int in = 0;
1519 #define DINAMOUNT 8 /* Full FIFO */
1520
1521 SPC_TRACE(("spc_datain_pio "));
1522 /* send TRANSFER command. */
1523 bus_space_write_1(iot, ioh, TCH, n >> 16);
1524 bus_space_write_1(iot, ioh, TCM, n >> 8);
1525 bus_space_write_1(iot, ioh, TCL, n);
1526 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1527 #ifdef x68k
1528 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1529 #else
1530 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); /* XXX */
1531 #endif
1532 for (;;) {
1533 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1534 break;
1535 if (bus_space_read_1(iot, ioh, INTS) != 0)
1536 goto phasechange;
1537 }
1538
1539 /*
1540 * We leave this loop if one or more of the following is true:
1541 * a) phase != PH_DATAIN && FIFOs are empty
1542 * b) reset has occurred or busfree is detected.
1543 */
1544 while (n > 0) {
1545 int xfer;
1546
1547 #define INTSMASK 0xff
1548 /* Wait for fifo half full or phase mismatch */
1549 for (;;) {
1550 intstat = ((bus_space_read_1(iot, ioh, SSTS) << 8) |
1551 bus_space_read_1(iot, ioh, INTS));
1552 if ((intstat & (INTSMASK | (SSTS_DREG_FULL << 8))) !=
1553 0)
1554 break;
1555 if ((intstat & (SSTS_DREG_EMPTY << 8)) == 0)
1556 break;
1557 }
1558
1559 #if 1
1560 if ((intstat & INTSMASK) != 0)
1561 goto phasechange;
1562 #else
1563 if ((intstat & INTSMASK) != 0 &&
1564 (intstat & (SSTS_DREG_EMPTY << 8)))
1565 goto phasechange;
1566 #endif
1567 if ((intstat & (SSTS_DREG_FULL << 8)) != 0)
1568 xfer = min(DINAMOUNT, n);
1569 else
1570 xfer = min(1, n);
1571
1572 SPC_MISC((">%d ", xfer));
1573
1574 n -= xfer;
1575 in += xfer;
1576
1577 while (xfer-- > 0) {
1578 *p++ = bus_space_read_1(iot, ioh, DREG);
1579 }
1580
1581 if ((intstat & INTSMASK) != 0)
1582 goto phasechange;
1583 }
1584
1585 /*
1586 * Some SCSI-devices are rude enough to transfer more data than what
1587 * was requested, e.g. 2048 bytes from a CD-ROM instead of the
1588 * requested 512. Test for progress, i.e. real transfers. If no real
1589 * transfers have been performed (n is probably already zero) and the
1590 * FIFO is not empty, waste some bytes....
1591 */
1592 if (in == 0) {
1593 for (;;) {
1594 if (bus_space_read_1(iot, ioh, INTS) != 0)
1595 break;
1596 }
1597 SPC_MISC(("extra data "));
1598 }
1599
1600 phasechange:
1601 /* Stop the FIFO data path. */
1602
1603 /* Turn on ENREQINIT again. */
1604
1605 return in;
1606 }
1607
1608 /*
1610 * Catch an interrupt from the adaptor
1611 */
1612 /*
1613 * This is the workhorse routine of the driver.
1614 * Deficiencies (for now):
1615 * 1) always uses programmed I/O
1616 */
1617 int
1618 spcintr(arg)
1619 void *arg;
1620 {
1621 struct spc_softc *sc = arg;
1622 bus_space_tag_t iot = sc->sc_iot;
1623 bus_space_handle_t ioh = sc->sc_ioh;
1624 u_char ints;
1625 struct spc_acb *acb;
1626 struct scsipi_periph *periph;
1627 struct spc_tinfo *ti;
1628 int n;
1629
1630 /*
1631 * Disable interrupt.
1632 */
1633 bus_space_write_1(iot, ioh, SCTL, bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB);
1634
1635 SPC_TRACE(("spcintr "));
1636
1637 loop:
1638 /*
1639 * Loop until transfer completion.
1640 */
1641 /*
1642 * First check for abnormal conditions, such as reset.
1643 */
1644 #ifdef x68k /* XXX? */
1645 while ((ints = bus_space_read_1(iot, ioh, INTS)) == 0)
1646 delay(1);
1647 SPC_MISC(("ints = 0x%x ", ints));
1648 #else
1649 ints = bus_space_read_1(iot, ioh, INTS);
1650 SPC_MISC(("ints = 0x%x ", ints));
1651 #endif
1652
1653 if ((ints & INTS_RST) != 0) {
1654 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname);
1655 goto reset;
1656 }
1657
1658 /*
1659 * Check for less serious errors.
1660 */
1661 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) {
1662 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname);
1663 if (sc->sc_prevphase == PH_MSGIN) {
1664 sc->sc_flags |= SPC_DROP_MSGIN;
1665 spc_sched_msgout(sc, SEND_PARITY_ERROR);
1666 } else
1667 spc_sched_msgout(sc, SEND_INIT_DET_ERR);
1668 }
1669
1670 /*
1671 * If we're not already busy doing something test for the following
1672 * conditions:
1673 * 1) We have been reselected by something
1674 * 2) We have selected something successfully
1675 * 3) Our selection process has timed out
1676 * 4) This is really a bus free interrupt just to get a new command
1677 * going?
1678 * 5) Spurious interrupt?
1679 */
1680 switch (sc->sc_state) {
1681 case SPC_IDLE:
1682 case SPC_SELECTING:
1683 SPC_MISC(("ints:0x%02x ", ints));
1684
1685 if ((ints & INTS_SEL) != 0) {
1686 /*
1687 * We don't currently support target mode.
1688 */
1689 printf("%s: target mode selected; going to BUS FREE\n",
1690 sc->sc_dev.dv_xname);
1691
1692 goto sched;
1693 } else if ((ints & INTS_RESEL) != 0) {
1694 SPC_MISC(("reselected "));
1695
1696 /*
1697 * If we're trying to select a target ourselves,
1698 * push our command back into the ready list.
1699 */
1700 if (sc->sc_state == SPC_SELECTING) {
1701 SPC_MISC(("backoff selector "));
1702 SPC_ASSERT(sc->sc_nexus != NULL);
1703 acb = sc->sc_nexus;
1704 sc->sc_nexus = NULL;
1705 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain);
1706 }
1707
1708 /* Save reselection ID. */
1709 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP);
1710
1711 sc->sc_state = SPC_RESELECTED;
1712 } else if ((ints & INTS_CMD_DONE) != 0) {
1713 SPC_MISC(("selected "));
1714
1715 /*
1716 * We have selected a target. Things to do:
1717 * a) Determine what message(s) to send.
1718 * b) Verify that we're still selecting the target.
1719 * c) Mark device as busy.
1720 */
1721 if (sc->sc_state != SPC_SELECTING) {
1722 printf("%s: selection out while idle; resetting\n",
1723 sc->sc_dev.dv_xname);
1724 SPC_BREAK();
1725 goto reset;
1726 }
1727 SPC_ASSERT(sc->sc_nexus != NULL);
1728 acb = sc->sc_nexus;
1729 periph = acb->xs->xs_periph;
1730 ti = &sc->sc_tinfo[periph->periph_target];
1731
1732 sc->sc_msgpriq = SEND_IDENTIFY;
1733 if (acb->flags & ACB_RESET)
1734 sc->sc_msgpriq |= SEND_DEV_RESET;
1735 else if (acb->flags & ACB_ABORT)
1736 sc->sc_msgpriq |= SEND_ABORT;
1737 else {
1738 #if SPC_USE_SYNCHRONOUS
1739 if ((ti->flags & DO_SYNC) != 0)
1740 sc->sc_msgpriq |= SEND_SDTR;
1741 #endif
1742 #if SPC_USE_WIDE
1743 if ((ti->flags & DO_WIDE) != 0)
1744 sc->sc_msgpriq |= SEND_WDTR;
1745 #endif
1746 }
1747
1748 acb->flags |= ACB_NEXUS;
1749 ti->lubusy |= (1 << periph->periph_lun);
1750
1751 /* Do an implicit RESTORE POINTERS. */
1752 sc->sc_dp = acb->data_addr;
1753 sc->sc_dleft = acb->data_length;
1754 sc->sc_cp = (u_char *)&acb->scsipi_cmd;
1755 sc->sc_cleft = acb->scsipi_cmd_length;
1756
1757 /* On our first connection, schedule a timeout. */
1758 if ((acb->xs->xs_control & XS_CTL_POLL) == 0)
1759 callout_reset(&acb->xs->xs_callout,
1760 (acb->timeout * hz) / 1000,
1761 spc_timeout, acb);
1762
1763 sc->sc_state = SPC_CONNECTED;
1764 } else if ((ints & INTS_TIMEOUT) != 0) {
1765 SPC_MISC(("selection timeout "));
1766
1767 if (sc->sc_state != SPC_SELECTING) {
1768 printf("%s: selection timeout while idle; resetting\n",
1769 sc->sc_dev.dv_xname);
1770 SPC_BREAK();
1771 goto reset;
1772 }
1773 SPC_ASSERT(sc->sc_nexus != NULL);
1774 acb = sc->sc_nexus;
1775
1776 delay(250);
1777
1778 acb->xs->error = XS_SELTIMEOUT;
1779 goto finish;
1780 } else {
1781 if (sc->sc_state != SPC_IDLE) {
1782 printf("%s: BUS FREE while not idle; state=%d\n",
1783 sc->sc_dev.dv_xname, sc->sc_state);
1784 SPC_BREAK();
1785 goto out;
1786 }
1787
1788 goto sched;
1789 }
1790
1791 /*
1792 * Turn off selection stuff, and prepare to catch bus free
1793 * interrupts, parity errors, and phase changes.
1794 */
1795
1796 sc->sc_flags = 0;
1797 sc->sc_prevphase = PH_INVALID;
1798 goto dophase;
1799 }
1800
1801 if ((ints & INTS_DISCON) != 0) {
1802 /* We've gone to BUS FREE phase. */
1803 bus_space_write_1(iot, ioh, PCTL,
1804 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB);
1805 /* disable disconnect interrupt */
1806 bus_space_write_1(iot, ioh, INTS, ints);
1807 /* XXX reset interrput */
1808
1809 switch (sc->sc_state) {
1810 case SPC_RESELECTED:
1811 goto sched;
1812
1813 case SPC_CONNECTED:
1814 SPC_ASSERT(sc->sc_nexus != NULL);
1815 acb = sc->sc_nexus;
1816
1817 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE
1818 if (sc->sc_prevphase == PH_MSGOUT) {
1819 /*
1820 * If the target went to BUS FREE phase during
1821 * or immediately after sending a SDTR or WDTR
1822 * message, disable negotiation.
1823 */
1824 periph = acb->xs->xs_periph;
1825 ti = &sc->sc_tinfo[periph->periph_target];
1826 switch (sc->sc_lastmsg) {
1827 #if SPC_USE_SYNCHRONOUS
1828 case SEND_SDTR:
1829 ti->flags &= ~DO_SYNC;
1830 ti->period = ti->offset = 0;
1831 break;
1832 #endif
1833 #if SPC_USE_WIDE
1834 case SEND_WDTR:
1835 ti->flags &= ~DO_WIDE;
1836 ti->width = 0;
1837 break;
1838 #endif
1839 }
1840 }
1841 #endif
1842
1843 if ((sc->sc_flags & SPC_ABORTING) == 0) {
1844 /*
1845 * Section 5.1.1 of the SCSI 2 spec suggests
1846 * issuing a REQUEST SENSE following an
1847 * unexpected disconnect. Some devices go into
1848 * a contingent allegiance condition when
1849 * disconnecting, and this is necessary to
1850 * clean up their state.
1851 */
1852 printf("%s: unexpected disconnect; sending REQUEST SENSE\n",
1853 sc->sc_dev.dv_xname);
1854 SPC_BREAK();
1855 acb->target_stat = SCSI_CHECK;
1856 acb->xs->error = XS_NOERROR;
1857 goto finish;
1858 }
1859
1860 acb->xs->error = XS_DRIVER_STUFFUP;
1861 goto finish;
1862
1863 case SPC_DISCONNECT:
1864 SPC_ASSERT(sc->sc_nexus != NULL);
1865 acb = sc->sc_nexus;
1866 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain);
1867 sc->sc_nexus = NULL;
1868 goto sched;
1869
1870 case SPC_CMDCOMPLETE:
1871 SPC_ASSERT(sc->sc_nexus != NULL);
1872 acb = sc->sc_nexus;
1873 goto finish;
1874 }
1875 }
1876 else if ((ints & INTS_CMD_DONE) != 0 &&
1877 sc->sc_prevphase == PH_MSGIN && sc->sc_state != SPC_CONNECTED)
1878 goto out;
1879
1880 dophase:
1881 #if 0
1882 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) {
1883 /* Wait for REQINIT. */
1884 goto out;
1885 }
1886 #else
1887 bus_space_write_1(iot, ioh, INTS, ints);
1888 ints = 0;
1889 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0)
1890 delay(1); /* need timeout XXX */
1891 #endif
1892
1893 /*
1894 * State transition.
1895 */
1896 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK;
1897 /* bus_space_write_1(iot, ioh, PCTL, sc->sc_phase);*/
1898
1899 SPC_MISC(("phase=%d\n", sc->sc_phase));
1900 switch (sc->sc_phase) {
1901 case PH_MSGOUT:
1902 if (sc->sc_state != SPC_CONNECTED &&
1903 sc->sc_state != SPC_RESELECTED)
1904 break;
1905 spc_msgout(sc);
1906 sc->sc_prevphase = PH_MSGOUT;
1907 goto loop;
1908
1909 case PH_MSGIN:
1910 if (sc->sc_state != SPC_CONNECTED &&
1911 sc->sc_state != SPC_RESELECTED)
1912 break;
1913 spc_msgin(sc);
1914 sc->sc_prevphase = PH_MSGIN;
1915 goto loop;
1916
1917 case PH_CMD:
1918 if (sc->sc_state != SPC_CONNECTED)
1919 break;
1920 #if SPC_DEBUG
1921 if ((spc_debug & SPC_SHOWMISC) != 0) {
1922 SPC_ASSERT(sc->sc_nexus != NULL);
1923 acb = sc->sc_nexus;
1924 printf("cmd=0x%02x+%d ",
1925 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length-1);
1926 }
1927 #endif
1928 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft);
1929 sc->sc_cp += n;
1930 sc->sc_cleft -= n;
1931 sc->sc_prevphase = PH_CMD;
1932 goto loop;
1933
1934 case PH_DATAOUT:
1935 if (sc->sc_state != SPC_CONNECTED)
1936 break;
1937 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft));
1938 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft);
1939 sc->sc_dp += n;
1940 sc->sc_dleft -= n;
1941 sc->sc_prevphase = PH_DATAOUT;
1942 goto loop;
1943
1944 case PH_DATAIN:
1945 if (sc->sc_state != SPC_CONNECTED)
1946 break;
1947 SPC_MISC(("datain "));
1948 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft);
1949 sc->sc_dp += n;
1950 sc->sc_dleft -= n;
1951 sc->sc_prevphase = PH_DATAIN;
1952 goto loop;
1953
1954 case PH_STAT:
1955 if (sc->sc_state != SPC_CONNECTED)
1956 break;
1957 SPC_ASSERT(sc->sc_nexus != NULL);
1958 acb = sc->sc_nexus;
1959 /*acb->target_stat = bus_space_read_1(iot, ioh, DREG);*/
1960 spc_datain_pio(sc, &acb->target_stat, 1);
1961 SPC_MISC(("target_stat=0x%02x ", acb->target_stat));
1962 sc->sc_prevphase = PH_STAT;
1963 goto loop;
1964 }
1965
1966 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname);
1967 SPC_BREAK();
1968 reset:
1969 spc_init(sc);
1970 return 1;
1971
1972 finish:
1973 callout_stop(&acb->xs->xs_callout);
1974 bus_space_write_1(iot, ioh, INTS, ints);
1975 ints = 0;
1976 spc_done(sc, acb);
1977 goto out;
1978
1979 sched:
1980 sc->sc_state = SPC_IDLE;
1981 spc_sched(sc);
1982 goto out;
1983
1984 out:
1985 if (ints)
1986 bus_space_write_1(iot, ioh, INTS, ints);
1987 bus_space_write_1(iot, ioh, SCTL,
1988 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB);
1989 return 1;
1990 }
1991
1992 void
1993 spc_abort(sc, acb)
1994 struct spc_softc *sc;
1995 struct spc_acb *acb;
1996 {
1997
1998 /* 2 secs for the abort */
1999 acb->timeout = SPC_ABORT_TIMEOUT;
2000 acb->flags |= ACB_ABORT;
2001
2002 if (acb == sc->sc_nexus) {
2003 /*
2004 * If we're still selecting, the message will be scheduled
2005 * after selection is complete.
2006 */
2007 if (sc->sc_state == SPC_CONNECTED)
2008 spc_sched_msgout(sc, SEND_ABORT);
2009 } else {
2010 spc_dequeue(sc, acb);
2011 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain);
2012 if (sc->sc_state == SPC_IDLE)
2013 spc_sched(sc);
2014 }
2015 }
2016
2017 void
2018 spc_timeout(arg)
2019 void *arg;
2020 {
2021 struct spc_acb *acb = arg;
2022 struct scsipi_xfer *xs = acb->xs;
2023 struct scsipi_periph *periph = xs->xs_periph;
2024 struct spc_softc *sc = (void*)periph->periph_channel->chan_adapter->adapt_dev;
2025 int s;
2026
2027 scsipi_printaddr(periph);
2028 printf("timed out");
2029
2030 s = splbio();
2031
2032 if (acb->flags & ACB_ABORT) {
2033 /* abort timed out */
2034 printf(" AGAIN\n");
2035 /* XXX Must reset! */
2036 } else {
2037 /* abort the operation that has timed out */
2038 printf("\n");
2039 acb->xs->error = XS_TIMEOUT;
2040 spc_abort(sc, acb);
2041 }
2042
2043 splx(s);
2044 }
2045
2046 #ifdef SPC_DEBUG
2048 /*
2049 * The following functions are mostly used for debugging purposes, either
2050 * directly called from the driver or from the kernel debugger.
2051 */
2052
2053 void
2054 spc_show_scsi_cmd(acb)
2055 struct spc_acb *acb;
2056 {
2057 u_char *b = (u_char *)&acb->scsipi_cmd;
2058 int i;
2059
2060 scsipi_printaddr(acb->xs->xs_periph);
2061 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) {
2062 for (i = 0; i < acb->scsipi_cmd_length; i++) {
2063 if (i)
2064 printf(",");
2065 printf("%x", b[i]);
2066 }
2067 printf("\n");
2068 } else
2069 printf("RESET\n");
2070 }
2071
2072 void
2073 spc_print_acb(acb)
2074 struct spc_acb *acb;
2075 {
2076
2077 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags);
2078 printf(" dp=%p dleft=%d target_stat=%x\n",
2079 acb->data_addr, acb->data_length, acb->target_stat);
2080 spc_show_scsi_cmd(acb);
2081 }
2082
2083 void
2084 spc_print_active_acb()
2085 {
2086 struct spc_acb *acb;
2087 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */
2088
2089 printf("ready list:\n");
2090 for (acb = sc->ready_list.tqh_first; acb != NULL;
2091 acb = acb->chain.tqe_next)
2092 spc_print_acb(acb);
2093 printf("nexus:\n");
2094 if (sc->sc_nexus != NULL)
2095 spc_print_acb(sc->sc_nexus);
2096 printf("nexus list:\n");
2097 for (acb = sc->nexus_list.tqh_first; acb != NULL;
2098 acb = acb->chain.tqe_next)
2099 spc_print_acb(acb);
2100 }
2101
2102 void
2103 spc_dump89352(sc)
2104 struct spc_softc *sc;
2105 {
2106 bus_space_tag_t iot = sc->sc_iot;
2107 bus_space_handle_t ioh = sc->sc_ioh;
2108
2109 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n",
2110 bus_space_read_1(iot, ioh, BDID),
2111 bus_space_read_1(iot, ioh, SCTL),
2112 bus_space_read_1(iot, ioh, SCMD),
2113 bus_space_read_1(iot, ioh, TMOD));
2114 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n",
2115 bus_space_read_1(iot, ioh, INTS),
2116 bus_space_read_1(iot, ioh, PSNS),
2117 bus_space_read_1(iot, ioh, SSTS),
2118 bus_space_read_1(iot, ioh, SERR),
2119 bus_space_read_1(iot, ioh, PCTL));
2120 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n",
2121 bus_space_read_1(iot, ioh, MBC),
2122 #if 0
2123 bus_space_read_1(iot, ioh, DREG),
2124 #else
2125 0,
2126 #endif
2127 bus_space_read_1(iot, ioh, TEMP),
2128 bus_space_read_1(iot, ioh, TCH),
2129 bus_space_read_1(iot, ioh, TCM));
2130 printf(" TCL=%x EXBF=%x\n",
2131 bus_space_read_1(iot, ioh, TCL),
2132 bus_space_read_1(iot, ioh, EXBF));
2133 }
2134
2135 void
2136 spc_dump_driver(sc)
2137 struct spc_softc *sc;
2138 {
2139 struct spc_tinfo *ti;
2140 int i;
2141
2142 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase);
2143 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n",
2144 sc->sc_state, sc->sc_imess[0],
2145 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg);
2146 for (i = 0; i < 7; i++) {
2147 ti = &sc->sc_tinfo[i];
2148 printf("tinfo%d: %d cmds %d disconnects %d timeouts",
2149 i, ti->cmds, ti->dconns, ti->touts);
2150 printf(" %d senses flags=%x\n", ti->senses, ti->flags);
2151 }
2152 }
2153 #endif
2154