mb89352reg.h revision 1.1
1 /* $NetBSD: mb89352reg.h,v 1.1 1999/02/13 17:33:14 minoura Exp $ */ 2 /* NecBSD: mb89352reg.h,v 1.3 1998/03/14 07:04:34 kmatsuda Exp */ 3 4 /*- 5 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * Copyright (c) 1990, 1993 9 * The Regents of the University of California. All rights reserved. 10 * 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 13 * 14 * This code is derived from software contributed to Berkeley by 15 * Van Jacobson of Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * @(#)scsireg.h 8.1 (Berkeley) 6/10/93 46 */ 47 /* 48 * [NetBSD for NEC PC-98 series] 49 * Copyright (c) 1996, 1997, 1998 50 * NetBSD/pc98 porting staff. All rights reserved. 51 * Copyright (c) 1996, 1997, 1998 52 * Kouichi Matsuda. All rights reserved. 53 */ 54 55 /* 56 * FUJITSU MB89352A SCSI Protocol Controler Hardware Description. 57 */ 58 59 /* Definitions, most of them has turned out to be unneccesary, but here they 60 * are anyway. 61 */ 62 63 #define BDID 0x00 /* Bus Device ID (R/W) */ 64 #define SCTL 0x01 /* SPC Control register (R/W) */ 65 #define SCMD 0x02 /* Command Register (R/W) */ 66 #define TMOD 0x03 /* Transmit Mode Register (synch models) */ 67 #define INTS 0x04 /* Interrupt sense (R); Interrupt Reset (W) */ 68 #define PSNS 0x05 /* Phase Sence (R); SPC Diagnostic Control (W) */ 69 #define SSTS 0x06 /* SPC status (R/O) */ 70 #define SERR 0x07 /* SPC error status (R/O) */ 71 #define PCTL 0x08 /* Phase Control (R/W) */ 72 #define MBC 0x09 /* Modified Byte Counter (R/O) */ 73 #define DREG 0x0a /* Data Register (R/W) */ 74 #define TEMP 0x0b /* Temporary Register (R/W) */ 75 #define TCH 0x0c /* Transfer Counter High (R/W) */ 76 #define TCM 0x0d /* Transfer Counter Middle (R/W) */ 77 #define TCL 0x0e /* Transfer Counter Low (R/W) */ 78 #define EXBF 0x0f /* External Buffer (synch models) */ 79 80 /* What all the bits do */ 81 82 /* SCSI_BDID */ 83 /* SCSI selection/reselection ID (both target *and* initiator) */ 84 #define SELID7 0x80 85 #define SELID6 0x40 86 #define SELID5 0x20 87 #define SELID4 0x10 88 #define SELID3 0x08 89 #define SELID2 0x04 90 #define SELID1 0x02 91 #define SELID0 0x01 92 93 /* SCSI_SCTL */ 94 #define SCTL_DISABLE 0x80 95 #define SCTL_CTRLRST 0x40 96 #define SCTL_DIAG 0x20 97 #define SCTL_ABRT_ENAB 0x10 98 #define SCTL_PARITY_ENAB 0x08 99 #define SCTL_SEL_ENAB 0x04 100 #define SCTL_RESEL_ENAB 0x02 101 #define SCTL_INTR_ENAB 0x01 102 103 /* SCSI_SCMD */ 104 #define SCMD_RST 0x10 105 #define SCMD_ICPT_XFR 0x08 106 #define SCMD_PROG_XFR 0x04 107 #define SCMD_PAD 0x01 /* if initiator */ 108 #define SCMD_PERR_STOP 0x01 /* if target */ 109 /* command codes */ 110 #define SCMD_BUS_REL 0x00 111 #define SCMD_SELECT 0x20 112 #define SCMD_RST_ATN 0x40 113 #define SCMD_SET_ATN 0x60 114 #define SCMD_XFR 0x80 115 #define SCMD_XFR_PAUSE 0xa0 116 #define SCMD_RST_ACK 0xc0 117 #define SCMD_SET_ACK 0xe0 118 119 /* SCSI_TMOD */ 120 #define TMOD_SYNC 0x80 121 122 /* SCSI_INTS */ 123 #define INTS_SEL 0x80 124 #define INTS_RESEL 0x40 125 #define INTS_DISCON 0x20 126 #define INTS_CMD_DONE 0x10 127 #define INTS_SRV_REQ 0x08 128 #define INTS_TIMEOUT 0x04 129 #define INTS_HARD_ERR 0x02 130 #define INTS_RST 0x01 131 132 /* SCSI_PSNS */ 133 #define PSNS_REQ 0x80 134 #define PSNS_ACK 0x40 135 #define PSNS_ATN 0x20 136 #define PSNS_SEL 0x10 137 #define PSNS_BSY 0x08 138 139 /* PSNS */ 140 #define REQI 0x80 141 #define ACKI 0x40 142 #define ATNI 0x20 143 #define SELI 0x10 144 #define BSYI 0x08 145 #define MSGI 0x04 146 #define CDI 0x02 147 #define IOI 0x01 148 149 /* Important! The 3 most significant bits of this register, in initiator mode, 150 * represents the "expected" SCSI bus phase and can be used to trigger phase 151 * mismatch and phase change interrupts. But more important: If there is a 152 * phase mismatch the chip will not transfer any data! This is actually a nice 153 * feature as it gives us a bit more control over what is happening when we are 154 * bursting data (in) through the FIFOs and the phase suddenly changes from 155 * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 156 * proper phase to be set in this register instead of dumping the bits into the 157 * FIFOs. 158 */ 159 #if 0 160 #define REQO 0x80 161 #define ACKO 0x40 162 #define ATNO 0x20 163 #define SELO 0x10 164 #define BSYO 0x08 165 #endif 166 /* PCTL */ 167 #define MSGO 0x04 168 #define CDO 0x02 169 #define IOO 0x01 170 171 /* Information transfer phases */ 172 #define PH_DATAOUT (0) 173 #define PH_DATAIN (IOI) 174 #define PH_CMD (CDI) 175 #define PH_STAT (CDI | IOI) 176 #define PH_MSGOUT (MSGI | CDI) 177 #define PH_MSGIN (MSGI | CDI | IOI) 178 179 #define PH_MASK (MSGI | CDI | IOI) 180 181 #define PH_INVALID 0xff 182 183 /* SCSI_SSTS */ 184 #define SSTS_INITIATOR 0x80 185 #define SSTS_TARGET 0x40 186 #define SSTS_BUSY 0x20 187 #define SSTS_XFR 0x10 188 #define SSTS_ACTIVE (SSTS_INITIATOR|SSTS_XFR) 189 #define SSTS_RST 0x08 190 #define SSTS_TCZERO 0x04 191 #define SSTS_DREG_FULL 0x02 192 #define SSTS_DREG_EMPTY 0x01 193 194 /* SCSI_SERR */ 195 #define SERR_SCSI_PAR 0x80 196 #define SERR_SPC_PAR 0x40 197 #define SERR_TC_PAR 0x08 198 #define SERR_PHASE_ERR 0x04 199 #define SERR_SHORT_XFR 0x02 200 #define SERR_OFFSET 0x01 201 202 /* SCSI_PCTL */ 203 #define PCTL_BFINT_ENAB 0x80 204
Indexes created Mon Sep 29 03:10:08 GMT 2025