mb89352reg.h revision 1.4
1 /* $NetBSD: mb89352reg.h,v 1.4 2004/01/04 16:19:44 wiz Exp $ */ 2 /* NecBSD: mb89352reg.h,v 1.3 1998/03/14 07:04:34 kmatsuda Exp */ 3 4 /*- 5 * Copyright (c) 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * Van Jacobson of Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)scsireg.h 8.1 (Berkeley) 6/10/93 39 */ 40 41 /*- 42 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. 43 * All rights reserved. 44 * 45 * This code is derived from software contributed to The NetBSD Foundation 46 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 47 * 48 * This code is derived from software contributed to Berkeley by 49 * Van Jacobson of Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. All advertising materials mentioning features or use of this software 60 * must display the following acknowledgement: 61 * This product includes software developed by the University of 62 * California, Berkeley and its contributors. 63 * 4. Neither the name of the University nor the names of its contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 71 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 72 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 73 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 74 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 75 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 76 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 77 * SUCH DAMAGE. 78 * 79 * @(#)scsireg.h 8.1 (Berkeley) 6/10/93 80 */ 81 /* 82 * [NetBSD for NEC PC-98 series] 83 * Copyright (c) 1996, 1997, 1998 84 * NetBSD/pc98 porting staff. All rights reserved. 85 * Copyright (c) 1996, 1997, 1998 86 * Kouichi Matsuda. All rights reserved. 87 */ 88 89 /* 90 * FUJITSU MB89352A SCSI Protocol Controller Hardware Description. 91 */ 92 93 /* Definitions, most of them has turned out to be unneccesary, but here they 94 * are anyway. 95 */ 96 97 #define BDID 0x00 /* Bus Device ID (R/W) */ 98 #define SCTL 0x01 /* SPC Control register (R/W) */ 99 #define SCMD 0x02 /* Command Register (R/W) */ 100 #define TMOD 0x03 /* Transmit Mode Register (synch models) */ 101 #define INTS 0x04 /* Interrupt sense (R); Interrupt Reset (W) */ 102 #define PSNS 0x05 /* Phase Sence (R); SPC Diagnostic Control (W) */ 103 #define SSTS 0x06 /* SPC status (R/O) */ 104 #define SERR 0x07 /* SPC error status (R/O) */ 105 #define PCTL 0x08 /* Phase Control (R/W) */ 106 #define MBC 0x09 /* Modified Byte Counter (R/O) */ 107 #define DREG 0x0a /* Data Register (R/W) */ 108 #define TEMP 0x0b /* Temporary Register (R/W) */ 109 #define TCH 0x0c /* Transfer Counter High (R/W) */ 110 #define TCM 0x0d /* Transfer Counter Middle (R/W) */ 111 #define TCL 0x0e /* Transfer Counter Low (R/W) */ 112 #define EXBF 0x0f /* External Buffer (synch models) */ 113 114 /* What all the bits do */ 115 116 /* SCSI_BDID */ 117 /* SCSI selection/reselection ID (both target *and* initiator) */ 118 #define SELID7 0x80 119 #define SELID6 0x40 120 #define SELID5 0x20 121 #define SELID4 0x10 122 #define SELID3 0x08 123 #define SELID2 0x04 124 #define SELID1 0x02 125 #define SELID0 0x01 126 127 /* SCSI_SCTL */ 128 #define SCTL_DISABLE 0x80 129 #define SCTL_CTRLRST 0x40 130 #define SCTL_DIAG 0x20 131 #define SCTL_ABRT_ENAB 0x10 132 #define SCTL_PARITY_ENAB 0x08 133 #define SCTL_SEL_ENAB 0x04 134 #define SCTL_RESEL_ENAB 0x02 135 #define SCTL_INTR_ENAB 0x01 136 137 /* SCSI_SCMD */ 138 #define SCMD_RST 0x10 139 #define SCMD_ICPT_XFR 0x08 140 #define SCMD_PROG_XFR 0x04 141 #define SCMD_PAD 0x01 /* if initiator */ 142 #define SCMD_PERR_STOP 0x01 /* if target */ 143 /* command codes */ 144 #define SCMD_BUS_REL 0x00 145 #define SCMD_SELECT 0x20 146 #define SCMD_RST_ATN 0x40 147 #define SCMD_SET_ATN 0x60 148 #define SCMD_XFR 0x80 149 #define SCMD_XFR_PAUSE 0xa0 150 #define SCMD_RST_ACK 0xc0 151 #define SCMD_SET_ACK 0xe0 152 153 /* SCSI_TMOD */ 154 #define TMOD_SYNC 0x80 155 156 /* SCSI_INTS */ 157 #define INTS_SEL 0x80 158 #define INTS_RESEL 0x40 159 #define INTS_DISCON 0x20 160 #define INTS_CMD_DONE 0x10 161 #define INTS_SRV_REQ 0x08 162 #define INTS_TIMEOUT 0x04 163 #define INTS_HARD_ERR 0x02 164 #define INTS_RST 0x01 165 166 /* SCSI_PSNS */ 167 #define PSNS_REQ 0x80 168 #define PSNS_ACK 0x40 169 #define PSNS_ATN 0x20 170 #define PSNS_SEL 0x10 171 #define PSNS_BSY 0x08 172 173 /* PSNS */ 174 #define REQI 0x80 175 #define ACKI 0x40 176 #define ATNI 0x20 177 #define SELI 0x10 178 #define BSYI 0x08 179 #define MSGI 0x04 180 #define CDI 0x02 181 #define IOI 0x01 182 183 /* Important! The 3 most significant bits of this register, in initiator mode, 184 * represents the "expected" SCSI bus phase and can be used to trigger phase 185 * mismatch and phase change interrupts. But more important: If there is a 186 * phase mismatch the chip will not transfer any data! This is actually a nice 187 * feature as it gives us a bit more control over what is happening when we are 188 * bursting data (in) through the FIFOs and the phase suddenly changes from 189 * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 190 * proper phase to be set in this register instead of dumping the bits into the 191 * FIFOs. 192 */ 193 #if 0 194 #define REQO 0x80 195 #define ACKO 0x40 196 #define ATNO 0x20 197 #define SELO 0x10 198 #define BSYO 0x08 199 #endif 200 /* PCTL */ 201 #define MSGO 0x04 202 #define CDO 0x02 203 #define IOO 0x01 204 205 /* Information transfer phases */ 206 #define PH_DATAOUT (0) 207 #define PH_DATAIN (IOI) 208 #define PH_CMD (CDI) 209 #define PH_STAT (CDI | IOI) 210 #define PH_MSGOUT (MSGI | CDI) 211 #define PH_MSGIN (MSGI | CDI | IOI) 212 213 #define PH_MASK (MSGI | CDI | IOI) 214 215 #define PH_INVALID 0xff 216 217 /* SCSI_SSTS */ 218 #define SSTS_INITIATOR 0x80 219 #define SSTS_TARGET 0x40 220 #define SSTS_BUSY 0x20 221 #define SSTS_XFR 0x10 222 #define SSTS_ACTIVE (SSTS_INITIATOR|SSTS_XFR) 223 #define SSTS_RST 0x08 224 #define SSTS_TCZERO 0x04 225 #define SSTS_DREG_FULL 0x02 226 #define SSTS_DREG_EMPTY 0x01 227 228 /* SCSI_SERR */ 229 #define SERR_SCSI_PAR 0x80 230 #define SERR_SPC_PAR 0x40 231 #define SERR_TC_PAR 0x08 232 #define SERR_PHASE_ERR 0x04 233 #define SERR_SHORT_XFR 0x02 234 #define SERR_OFFSET 0x01 235 236 /* SCSI_PCTL */ 237 #define PCTL_BFINT_ENAB 0x80 238
Indexes created Sun Sep 28 16:09:52 GMT 2025