mfi.c revision 1.44
1 /* $NetBSD: mfi.c,v 1.44 2012/08/23 12:24:33 bouyer Exp $ */ 2 /* $OpenBSD: mfi.c,v 1.66 2006/11/28 23:59:45 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2012 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 30 * 31 * Permission to use, copy, modify, and distribute this software for any 32 * purpose with or without fee is hereby granted, provided that the above 33 * copyright notice and this permission notice appear in all copies. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 36 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 37 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 38 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 39 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 40 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 41 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 42 */ 43 44 /*- 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 49 * Copyright 1994-2009 The FreeBSD Project. 50 * All rights reserved. 51 * 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE FREEBSD PROJECT``AS IS'' AND 59 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 60 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 61 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FREEBSD PROJECT OR 62 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 63 * EXEMPLARY,OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 64 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 65 * PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY THEORY 66 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 67 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 68 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * The views and conclusions contained in the software and documentation 71 * are those of the authors and should not be interpreted as representing 72 * official policies,either expressed or implied, of the FreeBSD Project. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: mfi.c,v 1.44 2012/08/23 12:24:33 bouyer Exp $"); 77 78 #include "bio.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/buf.h> 83 #include <sys/ioctl.h> 84 #include <sys/device.h> 85 #include <sys/kernel.h> 86 #include <sys/malloc.h> 87 #include <sys/proc.h> 88 #include <sys/cpu.h> 89 90 #include <uvm/uvm_param.h> 91 92 #include <sys/bus.h> 93 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsi_all.h> 96 #include <dev/scsipi/scsi_spc.h> 97 #include <dev/scsipi/scsipi_disk.h> 98 #include <dev/scsipi/scsi_disk.h> 99 #include <dev/scsipi/scsiconf.h> 100 101 #include <dev/ic/mfireg.h> 102 #include <dev/ic/mfivar.h> 103 104 #if NBIO > 0 105 #include <dev/biovar.h> 106 #endif /* NBIO > 0 */ 107 108 #ifdef MFI_DEBUG 109 uint32_t mfi_debug = 0 110 /* | MFI_D_CMD */ 111 /* | MFI_D_INTR */ 112 /* | MFI_D_MISC */ 113 /* | MFI_D_DMA */ 114 /* | MFI_D_IOCTL */ 115 /* | MFI_D_RW */ 116 /* | MFI_D_MEM */ 117 /* | MFI_D_CCB */ 118 /* | MFI_D_SYNC */ 119 ; 120 #endif 121 122 static void mfi_scsipi_request(struct scsipi_channel *, 123 scsipi_adapter_req_t, void *); 124 static void mfiminphys(struct buf *bp); 125 126 static struct mfi_ccb *mfi_get_ccb(struct mfi_softc *); 127 static void mfi_put_ccb(struct mfi_ccb *); 128 static int mfi_init_ccb(struct mfi_softc *); 129 130 static struct mfi_mem *mfi_allocmem(struct mfi_softc *, size_t); 131 static void mfi_freemem(struct mfi_softc *, struct mfi_mem **); 132 133 static int mfi_transition_firmware(struct mfi_softc *); 134 static int mfi_initialize_firmware(struct mfi_softc *); 135 static int mfi_get_info(struct mfi_softc *); 136 static uint32_t mfi_read(struct mfi_softc *, bus_size_t); 137 static void mfi_write(struct mfi_softc *, bus_size_t, uint32_t); 138 static int mfi_poll(struct mfi_ccb *); 139 static int mfi_create_sgl(struct mfi_ccb *, int); 140 141 /* commands */ 142 static int mfi_scsi_ld(struct mfi_ccb *, struct scsipi_xfer *); 143 static int mfi_scsi_ld_io(struct mfi_ccb *, struct scsipi_xfer *, 144 uint64_t, uint32_t); 145 static void mfi_scsi_ld_done(struct mfi_ccb *); 146 static void mfi_scsi_xs_done(struct mfi_ccb *, int, int); 147 static int mfi_mgmt_internal(struct mfi_softc *, 148 uint32_t, uint32_t, uint32_t, void *, uint8_t *); 149 static int mfi_mgmt(struct mfi_ccb *,struct scsipi_xfer *, 150 uint32_t, uint32_t, uint32_t, void *, uint8_t *); 151 static void mfi_mgmt_done(struct mfi_ccb *); 152 153 #if NBIO > 0 154 static int mfi_ioctl(device_t, u_long, void *); 155 static int mfi_ioctl_inq(struct mfi_softc *, struct bioc_inq *); 156 static int mfi_ioctl_vol(struct mfi_softc *, struct bioc_vol *); 157 static int mfi_ioctl_disk(struct mfi_softc *, struct bioc_disk *); 158 static int mfi_ioctl_alarm(struct mfi_softc *, 159 struct bioc_alarm *); 160 static int mfi_ioctl_blink(struct mfi_softc *sc, 161 struct bioc_blink *); 162 static int mfi_ioctl_setstate(struct mfi_softc *, 163 struct bioc_setstate *); 164 static int mfi_bio_hs(struct mfi_softc *, int, int, void *); 165 static int mfi_create_sensors(struct mfi_softc *); 166 static int mfi_destroy_sensors(struct mfi_softc *); 167 static void mfi_sensor_refresh(struct sysmon_envsys *, 168 envsys_data_t *); 169 #endif /* NBIO > 0 */ 170 171 static uint32_t mfi_xscale_fw_state(struct mfi_softc *sc); 172 static void mfi_xscale_intr_ena(struct mfi_softc *sc); 173 static void mfi_xscale_intr_dis(struct mfi_softc *sc); 174 static int mfi_xscale_intr(struct mfi_softc *sc); 175 static void mfi_xscale_post(struct mfi_softc *sc, struct mfi_ccb *ccb); 176 177 static const struct mfi_iop_ops mfi_iop_xscale = { 178 mfi_xscale_fw_state, 179 mfi_xscale_intr_dis, 180 mfi_xscale_intr_ena, 181 mfi_xscale_intr, 182 mfi_xscale_post, 183 mfi_scsi_ld_io, 184 }; 185 186 static uint32_t mfi_ppc_fw_state(struct mfi_softc *sc); 187 static void mfi_ppc_intr_ena(struct mfi_softc *sc); 188 static void mfi_ppc_intr_dis(struct mfi_softc *sc); 189 static int mfi_ppc_intr(struct mfi_softc *sc); 190 static void mfi_ppc_post(struct mfi_softc *sc, struct mfi_ccb *ccb); 191 192 static const struct mfi_iop_ops mfi_iop_ppc = { 193 mfi_ppc_fw_state, 194 mfi_ppc_intr_dis, 195 mfi_ppc_intr_ena, 196 mfi_ppc_intr, 197 mfi_ppc_post, 198 mfi_scsi_ld_io, 199 }; 200 201 uint32_t mfi_gen2_fw_state(struct mfi_softc *sc); 202 void mfi_gen2_intr_ena(struct mfi_softc *sc); 203 void mfi_gen2_intr_dis(struct mfi_softc *sc); 204 int mfi_gen2_intr(struct mfi_softc *sc); 205 void mfi_gen2_post(struct mfi_softc *sc, struct mfi_ccb *ccb); 206 207 static const struct mfi_iop_ops mfi_iop_gen2 = { 208 mfi_gen2_fw_state, 209 mfi_gen2_intr_dis, 210 mfi_gen2_intr_ena, 211 mfi_gen2_intr, 212 mfi_gen2_post, 213 mfi_scsi_ld_io, 214 }; 215 216 u_int32_t mfi_skinny_fw_state(struct mfi_softc *); 217 void mfi_skinny_intr_dis(struct mfi_softc *); 218 void mfi_skinny_intr_ena(struct mfi_softc *); 219 int mfi_skinny_intr(struct mfi_softc *); 220 void mfi_skinny_post(struct mfi_softc *, struct mfi_ccb *); 221 222 static const struct mfi_iop_ops mfi_iop_skinny = { 223 mfi_skinny_fw_state, 224 mfi_skinny_intr_dis, 225 mfi_skinny_intr_ena, 226 mfi_skinny_intr, 227 mfi_skinny_post, 228 mfi_scsi_ld_io, 229 }; 230 231 static int mfi_tbolt_init_desc_pool(struct mfi_softc *); 232 static int mfi_tbolt_init_MFI_queue(struct mfi_softc *); 233 static void mfi_tbolt_build_mpt_ccb(struct mfi_ccb *); 234 int mfi_tbolt_scsi_ld_io(struct mfi_ccb *, struct scsipi_xfer *, 235 uint64_t, uint32_t); 236 static void mfi_tbolt_scsi_ld_done(struct mfi_ccb *); 237 static int mfi_tbolt_create_sgl(struct mfi_ccb *, int); 238 void mfi_tbolt_sync_map_info(struct work *, void *); 239 static void mfi_sync_map_complete(struct mfi_ccb *); 240 241 u_int32_t mfi_tbolt_fw_state(struct mfi_softc *); 242 void mfi_tbolt_intr_dis(struct mfi_softc *); 243 void mfi_tbolt_intr_ena(struct mfi_softc *); 244 int mfi_tbolt_intr(struct mfi_softc *sc); 245 void mfi_tbolt_post(struct mfi_softc *, struct mfi_ccb *); 246 247 static const struct mfi_iop_ops mfi_iop_tbolt = { 248 mfi_tbolt_fw_state, 249 mfi_tbolt_intr_dis, 250 mfi_tbolt_intr_ena, 251 mfi_tbolt_intr, 252 mfi_tbolt_post, 253 mfi_tbolt_scsi_ld_io, 254 }; 255 256 #define mfi_fw_state(_s) ((_s)->sc_iop->mio_fw_state(_s)) 257 #define mfi_intr_enable(_s) ((_s)->sc_iop->mio_intr_ena(_s)) 258 #define mfi_intr_disable(_s) ((_s)->sc_iop->mio_intr_dis(_s)) 259 #define mfi_my_intr(_s) ((_s)->sc_iop->mio_intr(_s)) 260 #define mfi_post(_s, _c) ((_s)->sc_iop->mio_post((_s), (_c))) 261 262 static struct mfi_ccb * 263 mfi_get_ccb(struct mfi_softc *sc) 264 { 265 struct mfi_ccb *ccb; 266 int s; 267 268 s = splbio(); 269 ccb = TAILQ_FIRST(&sc->sc_ccb_freeq); 270 if (ccb) { 271 TAILQ_REMOVE(&sc->sc_ccb_freeq, ccb, ccb_link); 272 ccb->ccb_state = MFI_CCB_READY; 273 } 274 splx(s); 275 276 DNPRINTF(MFI_D_CCB, "%s: mfi_get_ccb: %p\n", DEVNAME(sc), ccb); 277 if (ccb == NULL) 278 aprint_error_dev(sc->sc_dev, "out of ccb\n"); 279 280 return ccb; 281 } 282 283 static void 284 mfi_put_ccb(struct mfi_ccb *ccb) 285 { 286 struct mfi_softc *sc = ccb->ccb_sc; 287 struct mfi_frame_header *hdr = &ccb->ccb_frame->mfr_header; 288 int s; 289 290 DNPRINTF(MFI_D_CCB, "%s: mfi_put_ccb: %p\n", DEVNAME(sc), ccb); 291 292 hdr->mfh_cmd_status = 0x0; 293 hdr->mfh_flags = 0x0; 294 ccb->ccb_state = MFI_CCB_FREE; 295 ccb->ccb_xs = NULL; 296 ccb->ccb_flags = 0; 297 ccb->ccb_done = NULL; 298 ccb->ccb_direction = 0; 299 ccb->ccb_frame_size = 0; 300 ccb->ccb_extra_frames = 0; 301 ccb->ccb_sgl = NULL; 302 ccb->ccb_data = NULL; 303 ccb->ccb_len = 0; 304 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 305 /* erase tb_request_desc but preserve SMID */ 306 int index = ccb->ccb_tb_request_desc.header.SMID; 307 ccb->ccb_tb_request_desc.words = 0; 308 ccb->ccb_tb_request_desc.header.SMID = index; 309 } 310 s = splbio(); 311 TAILQ_INSERT_TAIL(&sc->sc_ccb_freeq, ccb, ccb_link); 312 splx(s); 313 } 314 315 static int 316 mfi_destroy_ccb(struct mfi_softc *sc) 317 { 318 struct mfi_ccb *ccb; 319 uint32_t i; 320 321 DNPRINTF(MFI_D_CCB, "%s: mfi_destroy_ccb\n", DEVNAME(sc)); 322 323 324 for (i = 0; (ccb = mfi_get_ccb(sc)) != NULL; i++) { 325 /* create a dma map for transfer */ 326 bus_dmamap_destroy(sc->sc_datadmat, ccb->ccb_dmamap); 327 } 328 329 if (i < sc->sc_max_cmds) 330 return EBUSY; 331 332 free(sc->sc_ccb, M_DEVBUF); 333 334 return 0; 335 } 336 337 static int 338 mfi_init_ccb(struct mfi_softc *sc) 339 { 340 struct mfi_ccb *ccb; 341 uint32_t i; 342 int error; 343 bus_addr_t io_req_base_phys; 344 uint8_t *io_req_base; 345 int offset; 346 347 DNPRINTF(MFI_D_CCB, "%s: mfi_init_ccb\n", DEVNAME(sc)); 348 349 sc->sc_ccb = malloc(sizeof(struct mfi_ccb) * sc->sc_max_cmds, 350 M_DEVBUF, M_WAITOK|M_ZERO); 351 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 352 /* 353 * The first 256 bytes (SMID 0) is not used. 354 * Don't add to the cmd list. 355 */ 356 io_req_base = (uint8_t *)MFIMEM_KVA(sc->sc_tbolt_reqmsgpool) + 357 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE; 358 io_req_base_phys = MFIMEM_DVA(sc->sc_tbolt_reqmsgpool) + 359 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE; 360 } 361 362 for (i = 0; i < sc->sc_max_cmds; i++) { 363 ccb = &sc->sc_ccb[i]; 364 365 ccb->ccb_sc = sc; 366 367 /* select i'th frame */ 368 ccb->ccb_frame = (union mfi_frame *) 369 ((char*)MFIMEM_KVA(sc->sc_frames) + sc->sc_frames_size * i); 370 ccb->ccb_pframe = 371 MFIMEM_DVA(sc->sc_frames) + sc->sc_frames_size * i; 372 ccb->ccb_frame->mfr_header.mfh_context = i; 373 374 /* select i'th sense */ 375 ccb->ccb_sense = (struct mfi_sense *) 376 ((char*)MFIMEM_KVA(sc->sc_sense) + MFI_SENSE_SIZE * i); 377 ccb->ccb_psense = 378 (MFIMEM_DVA(sc->sc_sense) + MFI_SENSE_SIZE * i); 379 380 /* create a dma map for transfer */ 381 error = bus_dmamap_create(sc->sc_datadmat, 382 MAXPHYS, sc->sc_max_sgl, MAXPHYS, 0, 383 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->ccb_dmamap); 384 if (error) { 385 aprint_error_dev(sc->sc_dev, 386 "cannot create ccb dmamap (%d)\n", error); 387 goto destroy; 388 } 389 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 390 offset = MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * i; 391 ccb->ccb_tb_io_request = 392 (struct mfi_mpi2_request_raid_scsi_io *) 393 (io_req_base + offset); 394 ccb->ccb_tb_pio_request = 395 io_req_base_phys + offset; 396 offset = MEGASAS_MAX_SZ_CHAIN_FRAME * i; 397 ccb->ccb_tb_sg_frame = 398 (mpi2_sge_io_union *)(sc->sc_reply_pool_limit + 399 offset); 400 ccb->ccb_tb_psg_frame = sc->sc_sg_frame_busaddr + 401 offset; 402 /* SMID 0 is reserved. Set SMID/index from 1 */ 403 ccb->ccb_tb_request_desc.header.SMID = i + 1; 404 } 405 406 DNPRINTF(MFI_D_CCB, 407 "ccb(%d): %p frame: %#lx (%#lx) sense: %#lx (%#lx) map: %#lx\n", 408 ccb->ccb_frame->mfr_header.mfh_context, ccb, 409 (u_long)ccb->ccb_frame, (u_long)ccb->ccb_pframe, 410 (u_long)ccb->ccb_sense, (u_long)ccb->ccb_psense, 411 (u_long)ccb->ccb_dmamap); 412 413 /* add ccb to queue */ 414 mfi_put_ccb(ccb); 415 } 416 417 return 0; 418 destroy: 419 /* free dma maps and ccb memory */ 420 while (i) { 421 i--; 422 ccb = &sc->sc_ccb[i]; 423 bus_dmamap_destroy(sc->sc_datadmat, ccb->ccb_dmamap); 424 } 425 426 free(sc->sc_ccb, M_DEVBUF); 427 428 return 1; 429 } 430 431 static uint32_t 432 mfi_read(struct mfi_softc *sc, bus_size_t r) 433 { 434 uint32_t rv; 435 436 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 437 BUS_SPACE_BARRIER_READ); 438 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 439 440 DNPRINTF(MFI_D_RW, "%s: mr 0x%lx 0x08%x ", DEVNAME(sc), (u_long)r, rv); 441 return rv; 442 } 443 444 static void 445 mfi_write(struct mfi_softc *sc, bus_size_t r, uint32_t v) 446 { 447 DNPRINTF(MFI_D_RW, "%s: mw 0x%lx 0x%08x", DEVNAME(sc), (u_long)r, v); 448 449 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 450 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 451 BUS_SPACE_BARRIER_WRITE); 452 } 453 454 static struct mfi_mem * 455 mfi_allocmem(struct mfi_softc *sc, size_t size) 456 { 457 struct mfi_mem *mm; 458 int nsegs; 459 460 DNPRINTF(MFI_D_MEM, "%s: mfi_allocmem: %ld\n", DEVNAME(sc), 461 (long)size); 462 463 mm = malloc(sizeof(struct mfi_mem), M_DEVBUF, M_NOWAIT|M_ZERO); 464 if (mm == NULL) 465 return NULL; 466 467 mm->am_size = size; 468 469 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 470 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &mm->am_map) != 0) 471 goto amfree; 472 473 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &mm->am_seg, 1, 474 &nsegs, BUS_DMA_NOWAIT) != 0) 475 goto destroy; 476 477 if (bus_dmamem_map(sc->sc_dmat, &mm->am_seg, nsegs, size, &mm->am_kva, 478 BUS_DMA_NOWAIT) != 0) 479 goto free; 480 481 if (bus_dmamap_load(sc->sc_dmat, mm->am_map, mm->am_kva, size, NULL, 482 BUS_DMA_NOWAIT) != 0) 483 goto unmap; 484 485 DNPRINTF(MFI_D_MEM, " kva: %p dva: %p map: %p\n", 486 mm->am_kva, (void *)mm->am_map->dm_segs[0].ds_addr, mm->am_map); 487 488 memset(mm->am_kva, 0, size); 489 return mm; 490 491 unmap: 492 bus_dmamem_unmap(sc->sc_dmat, mm->am_kva, size); 493 free: 494 bus_dmamem_free(sc->sc_dmat, &mm->am_seg, 1); 495 destroy: 496 bus_dmamap_destroy(sc->sc_dmat, mm->am_map); 497 amfree: 498 free(mm, M_DEVBUF); 499 500 return NULL; 501 } 502 503 static void 504 mfi_freemem(struct mfi_softc *sc, struct mfi_mem **mmp) 505 { 506 struct mfi_mem *mm = *mmp; 507 508 if (mm == NULL) 509 return; 510 511 *mmp = NULL; 512 513 DNPRINTF(MFI_D_MEM, "%s: mfi_freemem: %p\n", DEVNAME(sc), mm); 514 515 bus_dmamap_unload(sc->sc_dmat, mm->am_map); 516 bus_dmamem_unmap(sc->sc_dmat, mm->am_kva, mm->am_size); 517 bus_dmamem_free(sc->sc_dmat, &mm->am_seg, 1); 518 bus_dmamap_destroy(sc->sc_dmat, mm->am_map); 519 free(mm, M_DEVBUF); 520 } 521 522 static int 523 mfi_transition_firmware(struct mfi_softc *sc) 524 { 525 uint32_t fw_state, cur_state; 526 int max_wait, i; 527 528 fw_state = mfi_fw_state(sc) & MFI_STATE_MASK; 529 530 DNPRINTF(MFI_D_CMD, "%s: mfi_transition_firmware: %#x\n", DEVNAME(sc), 531 fw_state); 532 533 while (fw_state != MFI_STATE_READY) { 534 DNPRINTF(MFI_D_MISC, 535 "%s: waiting for firmware to become ready\n", 536 DEVNAME(sc)); 537 cur_state = fw_state; 538 switch (fw_state) { 539 case MFI_STATE_FAULT: 540 aprint_error_dev(sc->sc_dev, "firmware fault\n"); 541 return 1; 542 case MFI_STATE_WAIT_HANDSHAKE: 543 if (sc->sc_ioptype == MFI_IOP_SKINNY || 544 sc->sc_ioptype == MFI_IOP_TBOLT) 545 mfi_write(sc, MFI_SKINNY_IDB, MFI_INIT_CLEAR_HANDSHAKE); 546 else 547 mfi_write(sc, MFI_IDB, MFI_INIT_CLEAR_HANDSHAKE); 548 max_wait = 2; 549 break; 550 case MFI_STATE_OPERATIONAL: 551 if (sc->sc_ioptype == MFI_IOP_SKINNY || 552 sc->sc_ioptype == MFI_IOP_TBOLT) 553 mfi_write(sc, MFI_SKINNY_IDB, MFI_INIT_READY); 554 else 555 mfi_write(sc, MFI_IDB, MFI_INIT_READY); 556 max_wait = 10; 557 break; 558 case MFI_STATE_UNDEFINED: 559 case MFI_STATE_BB_INIT: 560 max_wait = 2; 561 break; 562 case MFI_STATE_FW_INIT: 563 case MFI_STATE_DEVICE_SCAN: 564 case MFI_STATE_FLUSH_CACHE: 565 max_wait = 20; 566 break; 567 case MFI_STATE_BOOT_MESSAGE_PENDING: 568 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 569 mfi_write(sc, MFI_SKINNY_IDB, MFI_INIT_HOTPLUG); 570 max_wait = 180; 571 break; 572 } 573 /* FALLTHROUGH */ 574 default: 575 aprint_error_dev(sc->sc_dev, 576 "unknown firmware state %d\n", fw_state); 577 return 1; 578 } 579 for (i = 0; i < (max_wait * 10); i++) { 580 fw_state = mfi_fw_state(sc) & MFI_STATE_MASK; 581 if (fw_state == cur_state) 582 DELAY(100000); 583 else 584 break; 585 } 586 if (fw_state == cur_state) { 587 aprint_error_dev(sc->sc_dev, 588 "firmware stuck in state %#x\n", fw_state); 589 return 1; 590 } 591 } 592 593 return 0; 594 } 595 596 static int 597 mfi_initialize_firmware(struct mfi_softc *sc) 598 { 599 struct mfi_ccb *ccb; 600 struct mfi_init_frame *init; 601 struct mfi_init_qinfo *qinfo; 602 603 DNPRINTF(MFI_D_MISC, "%s: mfi_initialize_firmware\n", DEVNAME(sc)); 604 605 if ((ccb = mfi_get_ccb(sc)) == NULL) 606 return 1; 607 608 init = &ccb->ccb_frame->mfr_init; 609 qinfo = (struct mfi_init_qinfo *)((uint8_t *)init + MFI_FRAME_SIZE); 610 611 memset(qinfo, 0, sizeof *qinfo); 612 qinfo->miq_rq_entries = sc->sc_max_cmds + 1; 613 qinfo->miq_rq_addr_lo = htole32(MFIMEM_DVA(sc->sc_pcq) + 614 offsetof(struct mfi_prod_cons, mpc_reply_q)); 615 qinfo->miq_pi_addr_lo = htole32(MFIMEM_DVA(sc->sc_pcq) + 616 offsetof(struct mfi_prod_cons, mpc_producer)); 617 qinfo->miq_ci_addr_lo = htole32(MFIMEM_DVA(sc->sc_pcq) + 618 offsetof(struct mfi_prod_cons, mpc_consumer)); 619 620 init->mif_header.mfh_cmd = MFI_CMD_INIT; 621 init->mif_header.mfh_data_len = sizeof *qinfo; 622 init->mif_qinfo_new_addr_lo = htole32(ccb->ccb_pframe + MFI_FRAME_SIZE); 623 624 DNPRINTF(MFI_D_MISC, "%s: entries: %#x rq: %#x pi: %#x ci: %#x\n", 625 DEVNAME(sc), 626 qinfo->miq_rq_entries, qinfo->miq_rq_addr_lo, 627 qinfo->miq_pi_addr_lo, qinfo->miq_ci_addr_lo); 628 629 if (mfi_poll(ccb)) { 630 aprint_error_dev(sc->sc_dev, 631 "mfi_initialize_firmware failed\n"); 632 return 1; 633 } 634 635 mfi_put_ccb(ccb); 636 637 return 0; 638 } 639 640 static int 641 mfi_get_info(struct mfi_softc *sc) 642 { 643 #ifdef MFI_DEBUG 644 int i; 645 #endif 646 DNPRINTF(MFI_D_MISC, "%s: mfi_get_info\n", DEVNAME(sc)); 647 648 if (mfi_mgmt_internal(sc, MR_DCMD_CTRL_GET_INFO, MFI_DATA_IN, 649 sizeof(sc->sc_info), &sc->sc_info, NULL)) 650 return 1; 651 652 #ifdef MFI_DEBUG 653 654 for (i = 0; i < sc->sc_info.mci_image_component_count; i++) { 655 printf("%s: active FW %s Version %s date %s time %s\n", 656 DEVNAME(sc), 657 sc->sc_info.mci_image_component[i].mic_name, 658 sc->sc_info.mci_image_component[i].mic_version, 659 sc->sc_info.mci_image_component[i].mic_build_date, 660 sc->sc_info.mci_image_component[i].mic_build_time); 661 } 662 663 for (i = 0; i < sc->sc_info.mci_pending_image_component_count; i++) { 664 printf("%s: pending FW %s Version %s date %s time %s\n", 665 DEVNAME(sc), 666 sc->sc_info.mci_pending_image_component[i].mic_name, 667 sc->sc_info.mci_pending_image_component[i].mic_version, 668 sc->sc_info.mci_pending_image_component[i].mic_build_date, 669 sc->sc_info.mci_pending_image_component[i].mic_build_time); 670 } 671 672 printf("%s: max_arms %d max_spans %d max_arrs %d max_lds %d name %s\n", 673 DEVNAME(sc), 674 sc->sc_info.mci_max_arms, 675 sc->sc_info.mci_max_spans, 676 sc->sc_info.mci_max_arrays, 677 sc->sc_info.mci_max_lds, 678 sc->sc_info.mci_product_name); 679 680 printf("%s: serial %s present %#x fw time %d max_cmds %d max_sg %d\n", 681 DEVNAME(sc), 682 sc->sc_info.mci_serial_number, 683 sc->sc_info.mci_hw_present, 684 sc->sc_info.mci_current_fw_time, 685 sc->sc_info.mci_max_cmds, 686 sc->sc_info.mci_max_sg_elements); 687 688 printf("%s: max_rq %d lds_pres %d lds_deg %d lds_off %d pd_pres %d\n", 689 DEVNAME(sc), 690 sc->sc_info.mci_max_request_size, 691 sc->sc_info.mci_lds_present, 692 sc->sc_info.mci_lds_degraded, 693 sc->sc_info.mci_lds_offline, 694 sc->sc_info.mci_pd_present); 695 696 printf("%s: pd_dsk_prs %d pd_dsk_pred_fail %d pd_dsk_fail %d\n", 697 DEVNAME(sc), 698 sc->sc_info.mci_pd_disks_present, 699 sc->sc_info.mci_pd_disks_pred_failure, 700 sc->sc_info.mci_pd_disks_failed); 701 702 printf("%s: nvram %d mem %d flash %d\n", 703 DEVNAME(sc), 704 sc->sc_info.mci_nvram_size, 705 sc->sc_info.mci_memory_size, 706 sc->sc_info.mci_flash_size); 707 708 printf("%s: ram_cor %d ram_uncor %d clus_all %d clus_act %d\n", 709 DEVNAME(sc), 710 sc->sc_info.mci_ram_correctable_errors, 711 sc->sc_info.mci_ram_uncorrectable_errors, 712 sc->sc_info.mci_cluster_allowed, 713 sc->sc_info.mci_cluster_active); 714 715 printf("%s: max_strps_io %d raid_lvl %#x adapt_ops %#x ld_ops %#x\n", 716 DEVNAME(sc), 717 sc->sc_info.mci_max_strips_per_io, 718 sc->sc_info.mci_raid_levels, 719 sc->sc_info.mci_adapter_ops, 720 sc->sc_info.mci_ld_ops); 721 722 printf("%s: strp_sz_min %d strp_sz_max %d pd_ops %#x pd_mix %#x\n", 723 DEVNAME(sc), 724 sc->sc_info.mci_stripe_sz_ops.min, 725 sc->sc_info.mci_stripe_sz_ops.max, 726 sc->sc_info.mci_pd_ops, 727 sc->sc_info.mci_pd_mix_support); 728 729 printf("%s: ecc_bucket %d pckg_prop %s\n", 730 DEVNAME(sc), 731 sc->sc_info.mci_ecc_bucket_count, 732 sc->sc_info.mci_package_version); 733 734 printf("%s: sq_nm %d prd_fail_poll %d intr_thrtl %d intr_thrtl_to %d\n", 735 DEVNAME(sc), 736 sc->sc_info.mci_properties.mcp_seq_num, 737 sc->sc_info.mci_properties.mcp_pred_fail_poll_interval, 738 sc->sc_info.mci_properties.mcp_intr_throttle_cnt, 739 sc->sc_info.mci_properties.mcp_intr_throttle_timeout); 740 741 printf("%s: rbld_rate %d patr_rd_rate %d bgi_rate %d cc_rate %d\n", 742 DEVNAME(sc), 743 sc->sc_info.mci_properties.mcp_rebuild_rate, 744 sc->sc_info.mci_properties.mcp_patrol_read_rate, 745 sc->sc_info.mci_properties.mcp_bgi_rate, 746 sc->sc_info.mci_properties.mcp_cc_rate); 747 748 printf("%s: rc_rate %d ch_flsh %d spin_cnt %d spin_dly %d clus_en %d\n", 749 DEVNAME(sc), 750 sc->sc_info.mci_properties.mcp_recon_rate, 751 sc->sc_info.mci_properties.mcp_cache_flush_interval, 752 sc->sc_info.mci_properties.mcp_spinup_drv_cnt, 753 sc->sc_info.mci_properties.mcp_spinup_delay, 754 sc->sc_info.mci_properties.mcp_cluster_enable); 755 756 printf("%s: coerc %d alarm %d dis_auto_rbld %d dis_bat_wrn %d ecc %d\n", 757 DEVNAME(sc), 758 sc->sc_info.mci_properties.mcp_coercion_mode, 759 sc->sc_info.mci_properties.mcp_alarm_enable, 760 sc->sc_info.mci_properties.mcp_disable_auto_rebuild, 761 sc->sc_info.mci_properties.mcp_disable_battery_warn, 762 sc->sc_info.mci_properties.mcp_ecc_bucket_size); 763 764 printf("%s: ecc_leak %d rest_hs %d exp_encl_dev %d\n", 765 DEVNAME(sc), 766 sc->sc_info.mci_properties.mcp_ecc_bucket_leak_rate, 767 sc->sc_info.mci_properties.mcp_restore_hotspare_on_insertion, 768 sc->sc_info.mci_properties.mcp_expose_encl_devices); 769 770 printf("%s: vendor %#x device %#x subvendor %#x subdevice %#x\n", 771 DEVNAME(sc), 772 sc->sc_info.mci_pci.mip_vendor, 773 sc->sc_info.mci_pci.mip_device, 774 sc->sc_info.mci_pci.mip_subvendor, 775 sc->sc_info.mci_pci.mip_subdevice); 776 777 printf("%s: type %#x port_count %d port_addr ", 778 DEVNAME(sc), 779 sc->sc_info.mci_host.mih_type, 780 sc->sc_info.mci_host.mih_port_count); 781 782 for (i = 0; i < 8; i++) 783 printf("%.0lx ", sc->sc_info.mci_host.mih_port_addr[i]); 784 printf("\n"); 785 786 printf("%s: type %.x port_count %d port_addr ", 787 DEVNAME(sc), 788 sc->sc_info.mci_device.mid_type, 789 sc->sc_info.mci_device.mid_port_count); 790 791 for (i = 0; i < 8; i++) 792 printf("%.0lx ", sc->sc_info.mci_device.mid_port_addr[i]); 793 printf("\n"); 794 #endif /* MFI_DEBUG */ 795 796 return 0; 797 } 798 799 static void 800 mfiminphys(struct buf *bp) 801 { 802 DNPRINTF(MFI_D_MISC, "mfiminphys: %d\n", bp->b_bcount); 803 804 /* XXX currently using MFI_MAXFER = MAXPHYS */ 805 if (bp->b_bcount > MFI_MAXFER) 806 bp->b_bcount = MFI_MAXFER; 807 minphys(bp); 808 } 809 810 int 811 mfi_rescan(device_t self, const char *ifattr, const int *locators) 812 { 813 struct mfi_softc *sc = device_private(self); 814 815 if (sc->sc_child != NULL) 816 return 0; 817 818 sc->sc_child = config_found_sm_loc(self, ifattr, locators, &sc->sc_chan, 819 scsiprint, NULL); 820 821 return 0; 822 } 823 824 void 825 mfi_childdetached(device_t self, device_t child) 826 { 827 struct mfi_softc *sc = device_private(self); 828 829 KASSERT(self == sc->sc_dev); 830 KASSERT(child == sc->sc_child); 831 832 if (child == sc->sc_child) 833 sc->sc_child = NULL; 834 } 835 836 int 837 mfi_detach(struct mfi_softc *sc, int flags) 838 { 839 int error; 840 841 DNPRINTF(MFI_D_MISC, "%s: mfi_detach\n", DEVNAME(sc)); 842 843 if ((error = config_detach_children(sc->sc_dev, flags)) != 0) 844 return error; 845 846 #if NBIO > 0 847 mfi_destroy_sensors(sc); 848 bio_unregister(sc->sc_dev); 849 #endif /* NBIO > 0 */ 850 851 mfi_intr_disable(sc); 852 853 /* TBD: shutdown firmware */ 854 855 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 856 workqueue_destroy(sc->sc_ldsync_wq); 857 mfi_put_ccb(sc->sc_ldsync_ccb); 858 mfi_freemem(sc, &sc->sc_tbolt_reqmsgpool); 859 mfi_freemem(sc, &sc->sc_tbolt_ioc_init); 860 mfi_freemem(sc, &sc->sc_tbolt_verbuf); 861 } 862 863 if ((error = mfi_destroy_ccb(sc)) != 0) 864 return error; 865 866 mfi_freemem(sc, &sc->sc_sense); 867 868 mfi_freemem(sc, &sc->sc_frames); 869 870 mfi_freemem(sc, &sc->sc_pcq); 871 872 return 0; 873 } 874 875 int 876 mfi_attach(struct mfi_softc *sc, enum mfi_iop iop) 877 { 878 struct scsipi_adapter *adapt = &sc->sc_adapt; 879 struct scsipi_channel *chan = &sc->sc_chan; 880 uint32_t status, frames, max_sgl; 881 int i; 882 883 DNPRINTF(MFI_D_MISC, "%s: mfi_attach\n", DEVNAME(sc)); 884 885 sc->sc_ioptype = iop; 886 887 switch (iop) { 888 case MFI_IOP_XSCALE: 889 sc->sc_iop = &mfi_iop_xscale; 890 break; 891 case MFI_IOP_PPC: 892 sc->sc_iop = &mfi_iop_ppc; 893 break; 894 case MFI_IOP_GEN2: 895 sc->sc_iop = &mfi_iop_gen2; 896 break; 897 case MFI_IOP_SKINNY: 898 sc->sc_iop = &mfi_iop_skinny; 899 break; 900 case MFI_IOP_TBOLT: 901 sc->sc_iop = &mfi_iop_tbolt; 902 break; 903 default: 904 panic("%s: unknown iop %d", DEVNAME(sc), iop); 905 } 906 907 if (mfi_transition_firmware(sc)) 908 return 1; 909 910 TAILQ_INIT(&sc->sc_ccb_freeq); 911 912 status = mfi_fw_state(sc); 913 sc->sc_max_cmds = status & MFI_STATE_MAXCMD_MASK; 914 max_sgl = (status & MFI_STATE_MAXSGL_MASK) >> 16; 915 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 916 sc->sc_max_sgl = min(max_sgl, (128 * 1024) / PAGE_SIZE + 1); 917 sc->sc_sgl_size = sizeof(struct mfi_sg_ieee); 918 } else if (sc->sc_64bit_dma) { 919 sc->sc_max_sgl = min(max_sgl, (128 * 1024) / PAGE_SIZE + 1); 920 sc->sc_sgl_size = sizeof(struct mfi_sg64); 921 } else { 922 sc->sc_max_sgl = max_sgl; 923 sc->sc_sgl_size = sizeof(struct mfi_sg32); 924 } 925 DNPRINTF(MFI_D_MISC, "%s: max commands: %u, max sgl: %u\n", 926 DEVNAME(sc), sc->sc_max_cmds, sc->sc_max_sgl); 927 928 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 929 uint32_t tb_mem_size; 930 /* for Alignment */ 931 tb_mem_size = MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT; 932 933 tb_mem_size += 934 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1); 935 sc->sc_reply_pool_size = 936 ((sc->sc_max_cmds + 1 + 15) / 16) * 16; 937 tb_mem_size += 938 MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size; 939 940 /* this is for SGL's */ 941 tb_mem_size += MEGASAS_MAX_SZ_CHAIN_FRAME * sc->sc_max_cmds; 942 sc->sc_tbolt_reqmsgpool = mfi_allocmem(sc, tb_mem_size); 943 if (sc->sc_tbolt_reqmsgpool == NULL) { 944 aprint_error_dev(sc->sc_dev, 945 "unable to allocate thunderbolt " 946 "request message pool\n"); 947 goto nopcq; 948 } 949 if (mfi_tbolt_init_desc_pool(sc)) { 950 aprint_error_dev(sc->sc_dev, 951 "Thunderbolt pool preparation error\n"); 952 goto nopcq; 953 } 954 955 /* 956 * Allocate DMA memory mapping for MPI2 IOC Init descriptor, 957 * we are taking it diffrent from what we have allocated for 958 * Request and reply descriptors to avoid confusion later 959 */ 960 sc->sc_tbolt_ioc_init = mfi_allocmem(sc, 961 sizeof(struct mpi2_ioc_init_request)); 962 if (sc->sc_tbolt_ioc_init == NULL) { 963 aprint_error_dev(sc->sc_dev, 964 "unable to allocate thunderbolt IOC init memory"); 965 goto nopcq; 966 } 967 968 sc->sc_tbolt_verbuf = mfi_allocmem(sc, 969 MEGASAS_MAX_NAME*sizeof(bus_addr_t)); 970 if (sc->sc_tbolt_verbuf == NULL) { 971 aprint_error_dev(sc->sc_dev, 972 "unable to allocate thunderbolt version buffer\n"); 973 goto nopcq; 974 } 975 976 } 977 /* consumer/producer and reply queue memory */ 978 sc->sc_pcq = mfi_allocmem(sc, (sizeof(uint32_t) * sc->sc_max_cmds) + 979 sizeof(struct mfi_prod_cons)); 980 if (sc->sc_pcq == NULL) { 981 aprint_error_dev(sc->sc_dev, 982 "unable to allocate reply queue memory\n"); 983 goto nopcq; 984 } 985 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_pcq), 0, 986 sizeof(uint32_t) * sc->sc_max_cmds + sizeof(struct mfi_prod_cons), 987 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 988 989 /* frame memory */ 990 frames = (sc->sc_sgl_size * sc->sc_max_sgl + MFI_FRAME_SIZE - 1) / 991 MFI_FRAME_SIZE + 1; 992 sc->sc_frames_size = frames * MFI_FRAME_SIZE; 993 sc->sc_frames = mfi_allocmem(sc, sc->sc_frames_size * sc->sc_max_cmds); 994 if (sc->sc_frames == NULL) { 995 aprint_error_dev(sc->sc_dev, 996 "unable to allocate frame memory\n"); 997 goto noframe; 998 } 999 /* XXX hack, fix this */ 1000 if (MFIMEM_DVA(sc->sc_frames) & 0x3f) { 1001 aprint_error_dev(sc->sc_dev, 1002 "improper frame alignment (%#llx) FIXME\n", 1003 (long long int)MFIMEM_DVA(sc->sc_frames)); 1004 goto noframe; 1005 } 1006 1007 /* sense memory */ 1008 sc->sc_sense = mfi_allocmem(sc, sc->sc_max_cmds * MFI_SENSE_SIZE); 1009 if (sc->sc_sense == NULL) { 1010 aprint_error_dev(sc->sc_dev, 1011 "unable to allocate sense memory\n"); 1012 goto nosense; 1013 } 1014 1015 /* now that we have all memory bits go initialize ccbs */ 1016 if (mfi_init_ccb(sc)) { 1017 aprint_error_dev(sc->sc_dev, "could not init ccb list\n"); 1018 goto noinit; 1019 } 1020 1021 /* kickstart firmware with all addresses and pointers */ 1022 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 1023 if (mfi_tbolt_init_MFI_queue(sc)) { 1024 aprint_error_dev(sc->sc_dev, 1025 "could not initialize firmware\n"); 1026 goto noinit; 1027 } 1028 } else { 1029 if (mfi_initialize_firmware(sc)) { 1030 aprint_error_dev(sc->sc_dev, 1031 "could not initialize firmware\n"); 1032 goto noinit; 1033 } 1034 } 1035 1036 if (mfi_get_info(sc)) { 1037 aprint_error_dev(sc->sc_dev, 1038 "could not retrieve controller information\n"); 1039 goto noinit; 1040 } 1041 1042 aprint_normal_dev(sc->sc_dev, 1043 "logical drives %d, version %s, %dMB RAM\n", 1044 sc->sc_info.mci_lds_present, 1045 sc->sc_info.mci_package_version, 1046 sc->sc_info.mci_memory_size); 1047 1048 sc->sc_ld_cnt = sc->sc_info.mci_lds_present; 1049 sc->sc_max_ld = sc->sc_ld_cnt; 1050 for (i = 0; i < sc->sc_ld_cnt; i++) 1051 sc->sc_ld[i].ld_present = 1; 1052 1053 memset(adapt, 0, sizeof(*adapt)); 1054 adapt->adapt_dev = sc->sc_dev; 1055 adapt->adapt_nchannels = 1; 1056 /* keep a few commands for management */ 1057 if (sc->sc_max_cmds > 4) 1058 adapt->adapt_openings = sc->sc_max_cmds - 4; 1059 else 1060 adapt->adapt_openings = sc->sc_max_cmds; 1061 adapt->adapt_max_periph = adapt->adapt_openings; 1062 adapt->adapt_request = mfi_scsipi_request; 1063 adapt->adapt_minphys = mfiminphys; 1064 1065 memset(chan, 0, sizeof(*chan)); 1066 chan->chan_adapter = adapt; 1067 chan->chan_bustype = &scsi_sas_bustype; 1068 chan->chan_channel = 0; 1069 chan->chan_flags = 0; 1070 chan->chan_nluns = 8; 1071 chan->chan_ntargets = MFI_MAX_LD; 1072 chan->chan_id = MFI_MAX_LD; 1073 1074 mfi_rescan(sc->sc_dev, "scsi", NULL); 1075 1076 /* enable interrupts */ 1077 mfi_intr_enable(sc); 1078 1079 #if NBIO > 0 1080 if (bio_register(sc->sc_dev, mfi_ioctl) != 0) 1081 panic("%s: controller registration failed", DEVNAME(sc)); 1082 if (mfi_create_sensors(sc) != 0) 1083 aprint_error_dev(sc->sc_dev, "unable to create sensors\n"); 1084 #endif /* NBIO > 0 */ 1085 1086 return 0; 1087 noinit: 1088 mfi_freemem(sc, &sc->sc_sense); 1089 nosense: 1090 mfi_freemem(sc, &sc->sc_frames); 1091 noframe: 1092 mfi_freemem(sc, &sc->sc_pcq); 1093 nopcq: 1094 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 1095 if (sc->sc_tbolt_reqmsgpool) 1096 mfi_freemem(sc, &sc->sc_tbolt_reqmsgpool); 1097 if (sc->sc_tbolt_verbuf) 1098 mfi_freemem(sc, &sc->sc_tbolt_verbuf); 1099 } 1100 return 1; 1101 } 1102 1103 static int 1104 mfi_poll(struct mfi_ccb *ccb) 1105 { 1106 struct mfi_softc *sc = ccb->ccb_sc; 1107 struct mfi_frame_header *hdr; 1108 int to = 0; 1109 int rv = 0; 1110 1111 DNPRINTF(MFI_D_CMD, "%s: mfi_poll\n", DEVNAME(sc)); 1112 1113 hdr = &ccb->ccb_frame->mfr_header; 1114 hdr->mfh_cmd_status = 0xff; 1115 if (!sc->sc_MFA_enabled) 1116 hdr->mfh_flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 1117 1118 /* no callback, caller is supposed to do the cleanup */ 1119 ccb->ccb_done = NULL; 1120 1121 mfi_post(sc, ccb); 1122 if (sc->sc_MFA_enabled) { 1123 /* 1124 * depending on the command type, result may be posted 1125 * to *hdr, or not. In addition it seems there's 1126 * no way to avoid posting the SMID to the reply queue. 1127 * So pool using the interrupt routine. 1128 */ 1129 while (ccb->ccb_state != MFI_CCB_DONE) { 1130 delay(1000); 1131 if (to++ > 5000) { /* XXX 5 seconds busywait sucks */ 1132 rv = 1; 1133 break; 1134 } 1135 mfi_tbolt_intrh(sc); 1136 } 1137 } else { 1138 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1139 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1140 sc->sc_frames_size, BUS_DMASYNC_POSTREAD); 1141 1142 while (hdr->mfh_cmd_status == 0xff) { 1143 delay(1000); 1144 if (to++ > 5000) { /* XXX 5 seconds busywait sucks */ 1145 rv = 1; 1146 break; 1147 } 1148 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1149 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1150 sc->sc_frames_size, BUS_DMASYNC_POSTREAD); 1151 } 1152 } 1153 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1154 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1155 sc->sc_frames_size, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1156 1157 if (ccb->ccb_data != NULL) { 1158 DNPRINTF(MFI_D_INTR, "%s: mfi_mgmt_done sync\n", 1159 DEVNAME(sc)); 1160 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1161 ccb->ccb_dmamap->dm_mapsize, 1162 (ccb->ccb_direction & MFI_DATA_IN) ? 1163 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1164 1165 bus_dmamap_unload(sc->sc_datadmat, ccb->ccb_dmamap); 1166 } 1167 1168 if (rv != 0) { 1169 aprint_error_dev(sc->sc_dev, "timeout on ccb %d\n", 1170 hdr->mfh_context); 1171 ccb->ccb_flags |= MFI_CCB_F_ERR; 1172 return 1; 1173 } 1174 1175 return 0; 1176 } 1177 1178 int 1179 mfi_intr(void *arg) 1180 { 1181 struct mfi_softc *sc = arg; 1182 struct mfi_prod_cons *pcq; 1183 struct mfi_ccb *ccb; 1184 uint32_t producer, consumer, ctx; 1185 int claimed = 0; 1186 1187 if (!mfi_my_intr(sc)) 1188 return 0; 1189 1190 pcq = MFIMEM_KVA(sc->sc_pcq); 1191 1192 DNPRINTF(MFI_D_INTR, "%s: mfi_intr %#lx %#lx\n", DEVNAME(sc), 1193 (u_long)sc, (u_long)pcq); 1194 1195 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_pcq), 0, 1196 sizeof(uint32_t) * sc->sc_max_cmds + sizeof(struct mfi_prod_cons), 1197 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1198 1199 producer = pcq->mpc_producer; 1200 consumer = pcq->mpc_consumer; 1201 1202 while (consumer != producer) { 1203 DNPRINTF(MFI_D_INTR, "%s: mfi_intr pi %#x ci %#x\n", 1204 DEVNAME(sc), producer, consumer); 1205 1206 ctx = pcq->mpc_reply_q[consumer]; 1207 pcq->mpc_reply_q[consumer] = MFI_INVALID_CTX; 1208 if (ctx == MFI_INVALID_CTX) 1209 aprint_error_dev(sc->sc_dev, 1210 "invalid context, p: %d c: %d\n", 1211 producer, consumer); 1212 else { 1213 /* XXX remove from queue and call scsi_done */ 1214 ccb = &sc->sc_ccb[ctx]; 1215 DNPRINTF(MFI_D_INTR, "%s: mfi_intr context %#x\n", 1216 DEVNAME(sc), ctx); 1217 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1218 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1219 sc->sc_frames_size, 1220 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1221 ccb->ccb_done(ccb); 1222 1223 claimed = 1; 1224 } 1225 consumer++; 1226 if (consumer == (sc->sc_max_cmds + 1)) 1227 consumer = 0; 1228 } 1229 1230 pcq->mpc_consumer = consumer; 1231 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_pcq), 0, 1232 sizeof(uint32_t) * sc->sc_max_cmds + sizeof(struct mfi_prod_cons), 1233 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1234 1235 return claimed; 1236 } 1237 1238 static int 1239 mfi_scsi_ld_io(struct mfi_ccb *ccb, struct scsipi_xfer *xs, uint64_t blockno, 1240 uint32_t blockcnt) 1241 { 1242 struct scsipi_periph *periph = xs->xs_periph; 1243 struct mfi_io_frame *io; 1244 1245 DNPRINTF(MFI_D_CMD, "%s: mfi_scsi_ld_io: %d\n", 1246 device_xname(periph->periph_channel->chan_adapter->adapt_dev), 1247 periph->periph_target); 1248 1249 if (!xs->data) 1250 return 1; 1251 1252 io = &ccb->ccb_frame->mfr_io; 1253 if (xs->xs_control & XS_CTL_DATA_IN) { 1254 io->mif_header.mfh_cmd = MFI_CMD_LD_READ; 1255 ccb->ccb_direction = MFI_DATA_IN; 1256 } else { 1257 io->mif_header.mfh_cmd = MFI_CMD_LD_WRITE; 1258 ccb->ccb_direction = MFI_DATA_OUT; 1259 } 1260 io->mif_header.mfh_target_id = periph->periph_target; 1261 io->mif_header.mfh_timeout = 0; 1262 io->mif_header.mfh_flags = 0; 1263 io->mif_header.mfh_sense_len = MFI_SENSE_SIZE; 1264 io->mif_header.mfh_data_len= blockcnt; 1265 io->mif_lba_hi = (blockno >> 32); 1266 io->mif_lba_lo = (blockno & 0xffffffff); 1267 io->mif_sense_addr_lo = htole32(ccb->ccb_psense); 1268 io->mif_sense_addr_hi = 0; 1269 1270 ccb->ccb_done = mfi_scsi_ld_done; 1271 ccb->ccb_xs = xs; 1272 ccb->ccb_frame_size = MFI_IO_FRAME_SIZE; 1273 ccb->ccb_sgl = &io->mif_sgl; 1274 ccb->ccb_data = xs->data; 1275 ccb->ccb_len = xs->datalen; 1276 1277 if (mfi_create_sgl(ccb, (xs->xs_control & XS_CTL_NOSLEEP) ? 1278 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)) 1279 return 1; 1280 1281 return 0; 1282 } 1283 1284 static void 1285 mfi_scsi_ld_done(struct mfi_ccb *ccb) 1286 { 1287 struct mfi_frame_header *hdr = &ccb->ccb_frame->mfr_header; 1288 mfi_scsi_xs_done(ccb, hdr->mfh_cmd_status, hdr->mfh_scsi_status); 1289 } 1290 1291 static void 1292 mfi_scsi_xs_done(struct mfi_ccb *ccb, int status, int scsi_status) 1293 { 1294 struct scsipi_xfer *xs = ccb->ccb_xs; 1295 struct mfi_softc *sc = ccb->ccb_sc; 1296 1297 DNPRINTF(MFI_D_INTR, "%s: mfi_scsi_xs_done %#lx %#lx\n", 1298 DEVNAME(sc), (u_long)ccb, (u_long)ccb->ccb_frame); 1299 1300 if (xs->data != NULL) { 1301 DNPRINTF(MFI_D_INTR, "%s: mfi_scsi_xs_done sync\n", 1302 DEVNAME(sc)); 1303 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1304 ccb->ccb_dmamap->dm_mapsize, 1305 (xs->xs_control & XS_CTL_DATA_IN) ? 1306 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1307 1308 bus_dmamap_unload(sc->sc_datadmat, ccb->ccb_dmamap); 1309 } 1310 1311 if (status != MFI_STAT_OK) { 1312 xs->error = XS_DRIVER_STUFFUP; 1313 DNPRINTF(MFI_D_INTR, "%s: mfi_scsi_xs_done stuffup %#x\n", 1314 DEVNAME(sc), status); 1315 1316 if (scsi_status != 0) { 1317 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_sense), 1318 ccb->ccb_psense - MFIMEM_DVA(sc->sc_sense), 1319 MFI_SENSE_SIZE, BUS_DMASYNC_POSTREAD); 1320 DNPRINTF(MFI_D_INTR, 1321 "%s: mfi_scsi_xs_done sense %#x %lx %lx\n", 1322 DEVNAME(sc), scsi_status, 1323 (u_long)&xs->sense, (u_long)ccb->ccb_sense); 1324 memset(&xs->sense, 0, sizeof(xs->sense)); 1325 memcpy(&xs->sense, ccb->ccb_sense, 1326 sizeof(struct scsi_sense_data)); 1327 xs->error = XS_SENSE; 1328 } 1329 } else { 1330 xs->error = XS_NOERROR; 1331 xs->status = SCSI_OK; 1332 xs->resid = 0; 1333 } 1334 1335 mfi_put_ccb(ccb); 1336 scsipi_done(xs); 1337 } 1338 1339 static int 1340 mfi_scsi_ld(struct mfi_ccb *ccb, struct scsipi_xfer *xs) 1341 { 1342 struct mfi_pass_frame *pf; 1343 struct scsipi_periph *periph = xs->xs_periph; 1344 1345 DNPRINTF(MFI_D_CMD, "%s: mfi_scsi_ld: %d\n", 1346 device_xname(periph->periph_channel->chan_adapter->adapt_dev), 1347 periph->periph_target); 1348 1349 pf = &ccb->ccb_frame->mfr_pass; 1350 pf->mpf_header.mfh_cmd = MFI_CMD_LD_SCSI_IO; 1351 pf->mpf_header.mfh_target_id = periph->periph_target; 1352 pf->mpf_header.mfh_lun_id = 0; 1353 pf->mpf_header.mfh_cdb_len = xs->cmdlen; 1354 pf->mpf_header.mfh_timeout = 0; 1355 pf->mpf_header.mfh_data_len= xs->datalen; /* XXX */ 1356 pf->mpf_header.mfh_sense_len = MFI_SENSE_SIZE; 1357 1358 pf->mpf_sense_addr_hi = 0; 1359 pf->mpf_sense_addr_lo = htole32(ccb->ccb_psense); 1360 1361 memset(pf->mpf_cdb, 0, 16); 1362 memcpy(pf->mpf_cdb, &xs->cmdstore, xs->cmdlen); 1363 1364 ccb->ccb_done = mfi_scsi_ld_done; 1365 ccb->ccb_xs = xs; 1366 ccb->ccb_frame_size = MFI_PASS_FRAME_SIZE; 1367 ccb->ccb_sgl = &pf->mpf_sgl; 1368 1369 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) 1370 ccb->ccb_direction = (xs->xs_control & XS_CTL_DATA_IN) ? 1371 MFI_DATA_IN : MFI_DATA_OUT; 1372 else 1373 ccb->ccb_direction = MFI_DATA_NONE; 1374 1375 if (xs->data) { 1376 ccb->ccb_data = xs->data; 1377 ccb->ccb_len = xs->datalen; 1378 1379 if (mfi_create_sgl(ccb, (xs->xs_control & XS_CTL_NOSLEEP) ? 1380 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)) 1381 return 1; 1382 } 1383 1384 return 0; 1385 } 1386 1387 static void 1388 mfi_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1389 void *arg) 1390 { 1391 struct scsipi_periph *periph; 1392 struct scsipi_xfer *xs; 1393 struct scsipi_adapter *adapt = chan->chan_adapter; 1394 struct mfi_softc *sc = device_private(adapt->adapt_dev); 1395 struct mfi_ccb *ccb; 1396 struct scsi_rw_6 *rw; 1397 struct scsipi_rw_10 *rwb; 1398 struct scsipi_rw_12 *rw12; 1399 struct scsipi_rw_16 *rw16; 1400 uint64_t blockno; 1401 uint32_t blockcnt; 1402 uint8_t target; 1403 uint8_t mbox[MFI_MBOX_SIZE]; 1404 int s; 1405 1406 switch (req) { 1407 case ADAPTER_REQ_GROW_RESOURCES: 1408 /* Not supported. */ 1409 return; 1410 case ADAPTER_REQ_SET_XFER_MODE: 1411 { 1412 struct scsipi_xfer_mode *xm = arg; 1413 xm->xm_mode = PERIPH_CAP_TQING; 1414 xm->xm_period = 0; 1415 xm->xm_offset = 0; 1416 scsipi_async_event(&sc->sc_chan, ASYNC_EVENT_XFER_MODE, xm); 1417 return; 1418 } 1419 case ADAPTER_REQ_RUN_XFER: 1420 break; 1421 } 1422 1423 xs = arg; 1424 1425 periph = xs->xs_periph; 1426 target = periph->periph_target; 1427 1428 DNPRINTF(MFI_D_CMD, "%s: mfi_scsipi_request req %d opcode: %#x " 1429 "target %d lun %d\n", DEVNAME(sc), req, xs->cmd->opcode, 1430 periph->periph_target, periph->periph_lun); 1431 1432 s = splbio(); 1433 if (target >= MFI_MAX_LD || !sc->sc_ld[target].ld_present || 1434 periph->periph_lun != 0) { 1435 DNPRINTF(MFI_D_CMD, "%s: invalid target %d\n", 1436 DEVNAME(sc), target); 1437 xs->error = XS_SELTIMEOUT; 1438 scsipi_done(xs); 1439 splx(s); 1440 return; 1441 } 1442 1443 if ((ccb = mfi_get_ccb(sc)) == NULL) { 1444 DNPRINTF(MFI_D_CMD, "%s: mfi_scsipi_request no ccb\n", DEVNAME(sc)); 1445 xs->error = XS_RESOURCE_SHORTAGE; 1446 scsipi_done(xs); 1447 splx(s); 1448 return; 1449 } 1450 1451 switch (xs->cmd->opcode) { 1452 /* IO path */ 1453 case READ_16: 1454 case WRITE_16: 1455 rw16 = (struct scsipi_rw_16 *)xs->cmd; 1456 blockno = _8btol(rw16->addr); 1457 blockcnt = _4btol(rw16->length); 1458 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1459 goto stuffup; 1460 } 1461 break; 1462 1463 case READ_12: 1464 case WRITE_12: 1465 rw12 = (struct scsipi_rw_12 *)xs->cmd; 1466 blockno = _4btol(rw12->addr); 1467 blockcnt = _4btol(rw12->length); 1468 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1469 goto stuffup; 1470 } 1471 break; 1472 1473 case READ_10: 1474 case WRITE_10: 1475 rwb = (struct scsipi_rw_10 *)xs->cmd; 1476 blockno = _4btol(rwb->addr); 1477 blockcnt = _2btol(rwb->length); 1478 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1479 goto stuffup; 1480 } 1481 break; 1482 1483 case SCSI_READ_6_COMMAND: 1484 case SCSI_WRITE_6_COMMAND: 1485 rw = (struct scsi_rw_6 *)xs->cmd; 1486 blockno = _3btol(rw->addr) & (SRW_TOPADDR << 16 | 0xffff); 1487 blockcnt = rw->length ? rw->length : 0x100; 1488 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1489 goto stuffup; 1490 } 1491 break; 1492 1493 case SCSI_SYNCHRONIZE_CACHE_10: 1494 mbox[0] = MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE; 1495 if (mfi_mgmt(ccb, xs, 1496 MR_DCMD_CTRL_CACHE_FLUSH, MFI_DATA_NONE, 0, NULL, mbox)) { 1497 goto stuffup; 1498 } 1499 break; 1500 1501 /* hand it of to the firmware and let it deal with it */ 1502 case SCSI_TEST_UNIT_READY: 1503 /* save off sd? after autoconf */ 1504 if (!cold) /* XXX bogus */ 1505 strlcpy(sc->sc_ld[target].ld_dev, device_xname(sc->sc_dev), 1506 sizeof(sc->sc_ld[target].ld_dev)); 1507 /* FALLTHROUGH */ 1508 1509 default: 1510 if (mfi_scsi_ld(ccb, xs)) { 1511 goto stuffup; 1512 } 1513 break; 1514 } 1515 1516 DNPRINTF(MFI_D_CMD, "%s: start io %d\n", DEVNAME(sc), target); 1517 1518 if (xs->xs_control & XS_CTL_POLL) { 1519 if (mfi_poll(ccb)) { 1520 /* XXX check for sense in ccb->ccb_sense? */ 1521 aprint_error_dev(sc->sc_dev, 1522 "mfi_scsipi_request poll failed\n"); 1523 memset(&xs->sense, 0, sizeof(xs->sense)); 1524 xs->sense.scsi_sense.response_code = 1525 SSD_RCODE_VALID | SSD_RCODE_CURRENT; 1526 xs->sense.scsi_sense.flags = SKEY_ILLEGAL_REQUEST; 1527 xs->sense.scsi_sense.asc = 0x20; /* invalid opcode */ 1528 xs->error = XS_SENSE; 1529 xs->status = SCSI_CHECK; 1530 } else { 1531 DNPRINTF(MFI_D_DMA, 1532 "%s: mfi_scsipi_request poll complete %d\n", 1533 DEVNAME(sc), ccb->ccb_dmamap->dm_nsegs); 1534 xs->error = XS_NOERROR; 1535 xs->status = SCSI_OK; 1536 xs->resid = 0; 1537 } 1538 mfi_put_ccb(ccb); 1539 scsipi_done(xs); 1540 splx(s); 1541 return; 1542 } 1543 1544 mfi_post(sc, ccb); 1545 1546 DNPRINTF(MFI_D_DMA, "%s: mfi_scsipi_request queued %d\n", DEVNAME(sc), 1547 ccb->ccb_dmamap->dm_nsegs); 1548 1549 splx(s); 1550 return; 1551 1552 stuffup: 1553 mfi_put_ccb(ccb); 1554 xs->error = XS_DRIVER_STUFFUP; 1555 scsipi_done(xs); 1556 splx(s); 1557 } 1558 1559 static int 1560 mfi_create_sgl(struct mfi_ccb *ccb, int flags) 1561 { 1562 struct mfi_softc *sc = ccb->ccb_sc; 1563 struct mfi_frame_header *hdr; 1564 bus_dma_segment_t *sgd; 1565 union mfi_sgl *sgl; 1566 int error, i; 1567 1568 DNPRINTF(MFI_D_DMA, "%s: mfi_create_sgl %#lx\n", DEVNAME(sc), 1569 (u_long)ccb->ccb_data); 1570 1571 if (!ccb->ccb_data) 1572 return 1; 1573 1574 KASSERT(flags == BUS_DMA_NOWAIT || !cpu_intr_p()); 1575 error = bus_dmamap_load(sc->sc_datadmat, ccb->ccb_dmamap, 1576 ccb->ccb_data, ccb->ccb_len, NULL, flags); 1577 if (error) { 1578 if (error == EFBIG) { 1579 aprint_error_dev(sc->sc_dev, "more than %d dma segs\n", 1580 sc->sc_max_sgl); 1581 } else { 1582 aprint_error_dev(sc->sc_dev, 1583 "error %d loading dma map\n", error); 1584 } 1585 return 1; 1586 } 1587 1588 hdr = &ccb->ccb_frame->mfr_header; 1589 sgl = ccb->ccb_sgl; 1590 sgd = ccb->ccb_dmamap->dm_segs; 1591 for (i = 0; i < ccb->ccb_dmamap->dm_nsegs; i++) { 1592 if (sc->sc_ioptype == MFI_IOP_TBOLT && 1593 (hdr->mfh_cmd == MFI_CMD_PD_SCSI_IO || 1594 hdr->mfh_cmd == MFI_CMD_LD_READ || 1595 hdr->mfh_cmd == MFI_CMD_LD_WRITE)) { 1596 sgl->sg_ieee[i].addr = htole64(sgd[i].ds_addr); 1597 sgl->sg_ieee[i].len = htole32(sgd[i].ds_len); 1598 sgl->sg_ieee[i].flags = 0; 1599 DNPRINTF(MFI_D_DMA, "%s: addr: %#" PRIx64 " len: %#" 1600 PRIx32 "\n", 1601 DEVNAME(sc), sgl->sg64[i].addr, sgl->sg64[i].len); 1602 hdr->mfh_flags |= MFI_FRAME_IEEE_SGL | MFI_FRAME_SGL64; 1603 } else if (sc->sc_64bit_dma) { 1604 sgl->sg64[i].addr = htole64(sgd[i].ds_addr); 1605 sgl->sg64[i].len = htole32(sgd[i].ds_len); 1606 DNPRINTF(MFI_D_DMA, "%s: addr: %#" PRIx64 " len: %#" 1607 PRIx32 "\n", 1608 DEVNAME(sc), sgl->sg64[i].addr, sgl->sg64[i].len); 1609 hdr->mfh_flags |= MFI_FRAME_SGL64; 1610 } else { 1611 sgl->sg32[i].addr = htole32(sgd[i].ds_addr); 1612 sgl->sg32[i].len = htole32(sgd[i].ds_len); 1613 DNPRINTF(MFI_D_DMA, "%s: addr: %#x len: %#x\n", 1614 DEVNAME(sc), sgl->sg32[i].addr, sgl->sg32[i].len); 1615 hdr->mfh_flags |= MFI_FRAME_SGL32; 1616 } 1617 } 1618 1619 if (ccb->ccb_direction == MFI_DATA_IN) { 1620 hdr->mfh_flags |= MFI_FRAME_DIR_READ; 1621 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1622 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1623 } else { 1624 hdr->mfh_flags |= MFI_FRAME_DIR_WRITE; 1625 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1626 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1627 } 1628 1629 hdr->mfh_sg_count = ccb->ccb_dmamap->dm_nsegs; 1630 ccb->ccb_frame_size += sc->sc_sgl_size * ccb->ccb_dmamap->dm_nsegs; 1631 ccb->ccb_extra_frames = (ccb->ccb_frame_size - 1) / MFI_FRAME_SIZE; 1632 1633 DNPRINTF(MFI_D_DMA, "%s: sg_count: %d frame_size: %d frames_size: %d" 1634 " dm_nsegs: %d extra_frames: %d\n", 1635 DEVNAME(sc), 1636 hdr->mfh_sg_count, 1637 ccb->ccb_frame_size, 1638 sc->sc_frames_size, 1639 ccb->ccb_dmamap->dm_nsegs, 1640 ccb->ccb_extra_frames); 1641 1642 return 0; 1643 } 1644 1645 static int 1646 mfi_mgmt_internal(struct mfi_softc *sc, uint32_t opc, uint32_t dir, 1647 uint32_t len, void *buf, uint8_t *mbox) 1648 { 1649 struct mfi_ccb *ccb; 1650 int rv = 1; 1651 1652 if ((ccb = mfi_get_ccb(sc)) == NULL) 1653 return rv; 1654 rv = mfi_mgmt(ccb, NULL, opc, dir, len, buf, mbox); 1655 if (rv) 1656 return rv; 1657 1658 if (cold) { 1659 rv = 1; 1660 if (mfi_poll(ccb)) 1661 goto done; 1662 } else { 1663 mfi_post(sc, ccb); 1664 1665 DNPRINTF(MFI_D_MISC, "%s: mfi_mgmt_internal sleeping\n", 1666 DEVNAME(sc)); 1667 while (ccb->ccb_state != MFI_CCB_DONE) 1668 tsleep(ccb, PRIBIO, "mfi_mgmt", 0); 1669 1670 if (ccb->ccb_flags & MFI_CCB_F_ERR) 1671 goto done; 1672 } 1673 rv = 0; 1674 1675 done: 1676 mfi_put_ccb(ccb); 1677 return rv; 1678 } 1679 1680 static int 1681 mfi_mgmt(struct mfi_ccb *ccb, struct scsipi_xfer *xs, 1682 uint32_t opc, uint32_t dir, uint32_t len, void *buf, uint8_t *mbox) 1683 { 1684 struct mfi_dcmd_frame *dcmd; 1685 1686 DNPRINTF(MFI_D_MISC, "%s: mfi_mgmt %#x\n", DEVNAME(ccb->ccb_sc), opc); 1687 1688 dcmd = &ccb->ccb_frame->mfr_dcmd; 1689 memset(dcmd->mdf_mbox, 0, MFI_MBOX_SIZE); 1690 dcmd->mdf_header.mfh_cmd = MFI_CMD_DCMD; 1691 dcmd->mdf_header.mfh_timeout = 0; 1692 1693 dcmd->mdf_opcode = opc; 1694 dcmd->mdf_header.mfh_data_len = 0; 1695 ccb->ccb_direction = dir; 1696 ccb->ccb_xs = xs; 1697 ccb->ccb_done = mfi_mgmt_done; 1698 1699 ccb->ccb_frame_size = MFI_DCMD_FRAME_SIZE; 1700 1701 /* handle special opcodes */ 1702 if (mbox) 1703 memcpy(dcmd->mdf_mbox, mbox, MFI_MBOX_SIZE); 1704 1705 if (dir != MFI_DATA_NONE) { 1706 dcmd->mdf_header.mfh_data_len = len; 1707 ccb->ccb_data = buf; 1708 ccb->ccb_len = len; 1709 ccb->ccb_sgl = &dcmd->mdf_sgl; 1710 1711 if (mfi_create_sgl(ccb, BUS_DMA_WAITOK)) 1712 return 1; 1713 } 1714 return 0; 1715 } 1716 1717 static void 1718 mfi_mgmt_done(struct mfi_ccb *ccb) 1719 { 1720 struct scsipi_xfer *xs = ccb->ccb_xs; 1721 struct mfi_softc *sc = ccb->ccb_sc; 1722 struct mfi_frame_header *hdr = &ccb->ccb_frame->mfr_header; 1723 1724 DNPRINTF(MFI_D_INTR, "%s: mfi_mgmt_done %#lx %#lx\n", 1725 DEVNAME(sc), (u_long)ccb, (u_long)ccb->ccb_frame); 1726 1727 if (ccb->ccb_data != NULL) { 1728 DNPRINTF(MFI_D_INTR, "%s: mfi_mgmt_done sync\n", 1729 DEVNAME(sc)); 1730 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1731 ccb->ccb_dmamap->dm_mapsize, 1732 (ccb->ccb_direction & MFI_DATA_IN) ? 1733 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1734 1735 bus_dmamap_unload(sc->sc_datadmat, ccb->ccb_dmamap); 1736 } 1737 1738 if (hdr->mfh_cmd_status != MFI_STAT_OK) 1739 ccb->ccb_flags |= MFI_CCB_F_ERR; 1740 1741 ccb->ccb_state = MFI_CCB_DONE; 1742 if (xs) { 1743 if (hdr->mfh_cmd_status != MFI_STAT_OK) { 1744 xs->error = XS_DRIVER_STUFFUP; 1745 } else { 1746 xs->error = XS_NOERROR; 1747 xs->status = SCSI_OK; 1748 xs->resid = 0; 1749 } 1750 mfi_put_ccb(ccb); 1751 scsipi_done(xs); 1752 } else 1753 wakeup(ccb); 1754 } 1755 1756 #if NBIO > 0 1757 int 1758 mfi_ioctl(device_t dev, u_long cmd, void *addr) 1759 { 1760 struct mfi_softc *sc = device_private(dev); 1761 int error = 0; 1762 int s; 1763 1764 KERNEL_LOCK(1, curlwp); 1765 s = splbio(); 1766 1767 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl ", DEVNAME(sc)); 1768 1769 switch (cmd) { 1770 case BIOCINQ: 1771 DNPRINTF(MFI_D_IOCTL, "inq\n"); 1772 error = mfi_ioctl_inq(sc, (struct bioc_inq *)addr); 1773 break; 1774 1775 case BIOCVOL: 1776 DNPRINTF(MFI_D_IOCTL, "vol\n"); 1777 error = mfi_ioctl_vol(sc, (struct bioc_vol *)addr); 1778 break; 1779 1780 case BIOCDISK: 1781 DNPRINTF(MFI_D_IOCTL, "disk\n"); 1782 error = mfi_ioctl_disk(sc, (struct bioc_disk *)addr); 1783 break; 1784 1785 case BIOCALARM: 1786 DNPRINTF(MFI_D_IOCTL, "alarm\n"); 1787 error = mfi_ioctl_alarm(sc, (struct bioc_alarm *)addr); 1788 break; 1789 1790 case BIOCBLINK: 1791 DNPRINTF(MFI_D_IOCTL, "blink\n"); 1792 error = mfi_ioctl_blink(sc, (struct bioc_blink *)addr); 1793 break; 1794 1795 case BIOCSETSTATE: 1796 DNPRINTF(MFI_D_IOCTL, "setstate\n"); 1797 error = mfi_ioctl_setstate(sc, (struct bioc_setstate *)addr); 1798 break; 1799 1800 default: 1801 DNPRINTF(MFI_D_IOCTL, " invalid ioctl\n"); 1802 error = EINVAL; 1803 } 1804 splx(s); 1805 KERNEL_UNLOCK_ONE(curlwp); 1806 1807 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl return %x\n", DEVNAME(sc), error); 1808 return error; 1809 } 1810 1811 static int 1812 mfi_ioctl_inq(struct mfi_softc *sc, struct bioc_inq *bi) 1813 { 1814 struct mfi_conf *cfg; 1815 int rv = EINVAL; 1816 1817 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_inq\n", DEVNAME(sc)); 1818 1819 if (mfi_get_info(sc)) { 1820 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_inq failed\n", 1821 DEVNAME(sc)); 1822 return EIO; 1823 } 1824 1825 /* get figures */ 1826 cfg = malloc(sizeof *cfg, M_DEVBUF, M_WAITOK); 1827 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 1828 sizeof *cfg, cfg, NULL)) 1829 goto freeme; 1830 1831 strlcpy(bi->bi_dev, DEVNAME(sc), sizeof(bi->bi_dev)); 1832 bi->bi_novol = cfg->mfc_no_ld + cfg->mfc_no_hs; 1833 bi->bi_nodisk = sc->sc_info.mci_pd_disks_present; 1834 1835 rv = 0; 1836 freeme: 1837 free(cfg, M_DEVBUF); 1838 return rv; 1839 } 1840 1841 static int 1842 mfi_ioctl_vol(struct mfi_softc *sc, struct bioc_vol *bv) 1843 { 1844 int i, per, rv = EINVAL; 1845 uint8_t mbox[MFI_MBOX_SIZE]; 1846 1847 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_vol %#x\n", 1848 DEVNAME(sc), bv->bv_volid); 1849 1850 if (mfi_mgmt_internal(sc, MR_DCMD_LD_GET_LIST, MFI_DATA_IN, 1851 sizeof(sc->sc_ld_list), &sc->sc_ld_list, NULL)) 1852 goto done; 1853 1854 i = bv->bv_volid; 1855 mbox[0] = sc->sc_ld_list.mll_list[i].mll_ld.mld_target; 1856 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_vol target %#x\n", 1857 DEVNAME(sc), mbox[0]); 1858 1859 if (mfi_mgmt_internal(sc, MR_DCMD_LD_GET_INFO, MFI_DATA_IN, 1860 sizeof(sc->sc_ld_details), &sc->sc_ld_details, mbox)) 1861 goto done; 1862 1863 if (bv->bv_volid >= sc->sc_ld_list.mll_no_ld) { 1864 /* go do hotspares */ 1865 rv = mfi_bio_hs(sc, bv->bv_volid, MFI_MGMT_VD, bv); 1866 goto done; 1867 } 1868 1869 strlcpy(bv->bv_dev, sc->sc_ld[i].ld_dev, sizeof(bv->bv_dev)); 1870 1871 switch(sc->sc_ld_list.mll_list[i].mll_state) { 1872 case MFI_LD_OFFLINE: 1873 bv->bv_status = BIOC_SVOFFLINE; 1874 break; 1875 1876 case MFI_LD_PART_DEGRADED: 1877 case MFI_LD_DEGRADED: 1878 bv->bv_status = BIOC_SVDEGRADED; 1879 break; 1880 1881 case MFI_LD_ONLINE: 1882 bv->bv_status = BIOC_SVONLINE; 1883 break; 1884 1885 default: 1886 bv->bv_status = BIOC_SVINVALID; 1887 DNPRINTF(MFI_D_IOCTL, "%s: invalid logical disk state %#x\n", 1888 DEVNAME(sc), 1889 sc->sc_ld_list.mll_list[i].mll_state); 1890 } 1891 1892 /* additional status can modify MFI status */ 1893 switch (sc->sc_ld_details.mld_progress.mlp_in_prog) { 1894 case MFI_LD_PROG_CC: 1895 case MFI_LD_PROG_BGI: 1896 bv->bv_status = BIOC_SVSCRUB; 1897 per = (int)sc->sc_ld_details.mld_progress.mlp_cc.mp_progress; 1898 bv->bv_percent = (per * 100) / 0xffff; 1899 bv->bv_seconds = 1900 sc->sc_ld_details.mld_progress.mlp_cc.mp_elapsed_seconds; 1901 break; 1902 1903 case MFI_LD_PROG_FGI: 1904 case MFI_LD_PROG_RECONSTRUCT: 1905 /* nothing yet */ 1906 break; 1907 } 1908 1909 /* 1910 * The RAID levels are determined per the SNIA DDF spec, this is only 1911 * a subset that is valid for the MFI contrller. 1912 */ 1913 bv->bv_level = sc->sc_ld_details.mld_cfg.mlc_parm.mpa_pri_raid; 1914 if (sc->sc_ld_details.mld_cfg.mlc_parm.mpa_sec_raid == 1915 MFI_DDF_SRL_SPANNED) 1916 bv->bv_level *= 10; 1917 1918 bv->bv_nodisk = sc->sc_ld_details.mld_cfg.mlc_parm.mpa_no_drv_per_span * 1919 sc->sc_ld_details.mld_cfg.mlc_parm.mpa_span_depth; 1920 1921 bv->bv_size = sc->sc_ld_details.mld_size * 512; /* bytes per block */ 1922 1923 rv = 0; 1924 done: 1925 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_vol done %x\n", 1926 DEVNAME(sc), rv); 1927 return rv; 1928 } 1929 1930 static int 1931 mfi_ioctl_disk(struct mfi_softc *sc, struct bioc_disk *bd) 1932 { 1933 struct mfi_conf *cfg; 1934 struct mfi_array *ar; 1935 struct mfi_ld_cfg *ld; 1936 struct mfi_pd_details *pd; 1937 struct scsipi_inquiry_data *inqbuf; 1938 char vend[8+16+4+1]; 1939 int i, rv = EINVAL; 1940 int arr, vol, disk; 1941 uint32_t size; 1942 uint8_t mbox[MFI_MBOX_SIZE]; 1943 1944 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_disk %#x\n", 1945 DEVNAME(sc), bd->bd_diskid); 1946 1947 pd = malloc(sizeof *pd, M_DEVBUF, M_WAITOK | M_ZERO); 1948 1949 /* send single element command to retrieve size for full structure */ 1950 cfg = malloc(sizeof *cfg, M_DEVBUF, M_WAITOK); 1951 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 1952 sizeof *cfg, cfg, NULL)) 1953 goto freeme; 1954 1955 size = cfg->mfc_size; 1956 free(cfg, M_DEVBUF); 1957 1958 /* memory for read config */ 1959 cfg = malloc(size, M_DEVBUF, M_WAITOK|M_ZERO); 1960 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 1961 size, cfg, NULL)) 1962 goto freeme; 1963 1964 ar = cfg->mfc_array; 1965 1966 /* calculate offset to ld structure */ 1967 ld = (struct mfi_ld_cfg *)( 1968 ((uint8_t *)cfg) + offsetof(struct mfi_conf, mfc_array) + 1969 cfg->mfc_array_size * cfg->mfc_no_array); 1970 1971 vol = bd->bd_volid; 1972 1973 if (vol >= cfg->mfc_no_ld) { 1974 /* do hotspares */ 1975 rv = mfi_bio_hs(sc, bd->bd_volid, MFI_MGMT_SD, bd); 1976 goto freeme; 1977 } 1978 1979 /* find corresponding array for ld */ 1980 for (i = 0, arr = 0; i < vol; i++) 1981 arr += ld[i].mlc_parm.mpa_span_depth; 1982 1983 /* offset disk into pd list */ 1984 disk = bd->bd_diskid % ld[vol].mlc_parm.mpa_no_drv_per_span; 1985 1986 /* offset array index into the next spans */ 1987 arr += bd->bd_diskid / ld[vol].mlc_parm.mpa_no_drv_per_span; 1988 1989 bd->bd_target = ar[arr].pd[disk].mar_enc_slot; 1990 switch (ar[arr].pd[disk].mar_pd_state){ 1991 case MFI_PD_UNCONFIG_GOOD: 1992 bd->bd_status = BIOC_SDUNUSED; 1993 break; 1994 1995 case MFI_PD_HOTSPARE: /* XXX dedicated hotspare part of array? */ 1996 bd->bd_status = BIOC_SDHOTSPARE; 1997 break; 1998 1999 case MFI_PD_OFFLINE: 2000 bd->bd_status = BIOC_SDOFFLINE; 2001 break; 2002 2003 case MFI_PD_FAILED: 2004 bd->bd_status = BIOC_SDFAILED; 2005 break; 2006 2007 case MFI_PD_REBUILD: 2008 bd->bd_status = BIOC_SDREBUILD; 2009 break; 2010 2011 case MFI_PD_ONLINE: 2012 bd->bd_status = BIOC_SDONLINE; 2013 break; 2014 2015 case MFI_PD_UNCONFIG_BAD: /* XXX define new state in bio */ 2016 default: 2017 bd->bd_status = BIOC_SDINVALID; 2018 break; 2019 2020 } 2021 2022 /* get the remaining fields */ 2023 *((uint16_t *)&mbox) = ar[arr].pd[disk].mar_pd.mfp_id; 2024 memset(pd, 0, sizeof(*pd)); 2025 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_INFO, MFI_DATA_IN, 2026 sizeof *pd, pd, mbox)) 2027 goto freeme; 2028 2029 bd->bd_size = pd->mpd_size * 512; /* bytes per block */ 2030 2031 /* if pd->mpd_enc_idx is 0 then it is not in an enclosure */ 2032 bd->bd_channel = pd->mpd_enc_idx; 2033 2034 inqbuf = (struct scsipi_inquiry_data *)&pd->mpd_inq_data; 2035 memcpy(vend, inqbuf->vendor, sizeof vend - 1); 2036 vend[sizeof vend - 1] = '\0'; 2037 strlcpy(bd->bd_vendor, vend, sizeof(bd->bd_vendor)); 2038 2039 /* XXX find a way to retrieve serial nr from drive */ 2040 /* XXX find a way to get bd_procdev */ 2041 2042 rv = 0; 2043 freeme: 2044 free(pd, M_DEVBUF); 2045 free(cfg, M_DEVBUF); 2046 2047 return rv; 2048 } 2049 2050 static int 2051 mfi_ioctl_alarm(struct mfi_softc *sc, struct bioc_alarm *ba) 2052 { 2053 uint32_t opc, dir = MFI_DATA_NONE; 2054 int rv = 0; 2055 int8_t ret; 2056 2057 switch(ba->ba_opcode) { 2058 case BIOC_SADISABLE: 2059 opc = MR_DCMD_SPEAKER_DISABLE; 2060 break; 2061 2062 case BIOC_SAENABLE: 2063 opc = MR_DCMD_SPEAKER_ENABLE; 2064 break; 2065 2066 case BIOC_SASILENCE: 2067 opc = MR_DCMD_SPEAKER_SILENCE; 2068 break; 2069 2070 case BIOC_GASTATUS: 2071 opc = MR_DCMD_SPEAKER_GET; 2072 dir = MFI_DATA_IN; 2073 break; 2074 2075 case BIOC_SATEST: 2076 opc = MR_DCMD_SPEAKER_TEST; 2077 break; 2078 2079 default: 2080 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_alarm biocalarm invalid " 2081 "opcode %x\n", DEVNAME(sc), ba->ba_opcode); 2082 return EINVAL; 2083 } 2084 2085 if (mfi_mgmt_internal(sc, opc, dir, sizeof(ret), &ret, NULL)) 2086 rv = EINVAL; 2087 else 2088 if (ba->ba_opcode == BIOC_GASTATUS) 2089 ba->ba_status = ret; 2090 else 2091 ba->ba_status = 0; 2092 2093 return rv; 2094 } 2095 2096 static int 2097 mfi_ioctl_blink(struct mfi_softc *sc, struct bioc_blink *bb) 2098 { 2099 int i, found, rv = EINVAL; 2100 uint8_t mbox[MFI_MBOX_SIZE]; 2101 uint32_t cmd; 2102 struct mfi_pd_list *pd; 2103 2104 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_blink %x\n", DEVNAME(sc), 2105 bb->bb_status); 2106 2107 /* channel 0 means not in an enclosure so can't be blinked */ 2108 if (bb->bb_channel == 0) 2109 return EINVAL; 2110 2111 pd = malloc(MFI_PD_LIST_SIZE, M_DEVBUF, M_WAITOK); 2112 2113 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_LIST, MFI_DATA_IN, 2114 MFI_PD_LIST_SIZE, pd, NULL)) 2115 goto done; 2116 2117 for (i = 0, found = 0; i < pd->mpl_no_pd; i++) 2118 if (bb->bb_channel == pd->mpl_address[i].mpa_enc_index && 2119 bb->bb_target == pd->mpl_address[i].mpa_enc_slot) { 2120 found = 1; 2121 break; 2122 } 2123 2124 if (!found) 2125 goto done; 2126 2127 memset(mbox, 0, sizeof mbox); 2128 2129 *((uint16_t *)&mbox) = pd->mpl_address[i].mpa_pd_id; 2130 2131 switch (bb->bb_status) { 2132 case BIOC_SBUNBLINK: 2133 cmd = MR_DCMD_PD_UNBLINK; 2134 break; 2135 2136 case BIOC_SBBLINK: 2137 cmd = MR_DCMD_PD_BLINK; 2138 break; 2139 2140 case BIOC_SBALARM: 2141 default: 2142 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_blink biocblink invalid " 2143 "opcode %x\n", DEVNAME(sc), bb->bb_status); 2144 goto done; 2145 } 2146 2147 2148 if (mfi_mgmt_internal(sc, cmd, MFI_DATA_NONE, 0, NULL, mbox)) 2149 goto done; 2150 2151 rv = 0; 2152 done: 2153 free(pd, M_DEVBUF); 2154 return rv; 2155 } 2156 2157 static int 2158 mfi_ioctl_setstate(struct mfi_softc *sc, struct bioc_setstate *bs) 2159 { 2160 struct mfi_pd_list *pd; 2161 int i, found, rv = EINVAL; 2162 uint8_t mbox[MFI_MBOX_SIZE]; 2163 uint32_t cmd; 2164 2165 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_setstate %x\n", DEVNAME(sc), 2166 bs->bs_status); 2167 2168 pd = malloc(MFI_PD_LIST_SIZE, M_DEVBUF, M_WAITOK); 2169 2170 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_LIST, MFI_DATA_IN, 2171 MFI_PD_LIST_SIZE, pd, NULL)) 2172 goto done; 2173 2174 for (i = 0, found = 0; i < pd->mpl_no_pd; i++) 2175 if (bs->bs_channel == pd->mpl_address[i].mpa_enc_index && 2176 bs->bs_target == pd->mpl_address[i].mpa_enc_slot) { 2177 found = 1; 2178 break; 2179 } 2180 2181 if (!found) 2182 goto done; 2183 2184 memset(mbox, 0, sizeof mbox); 2185 2186 *((uint16_t *)&mbox) = pd->mpl_address[i].mpa_pd_id; 2187 2188 switch (bs->bs_status) { 2189 case BIOC_SSONLINE: 2190 mbox[2] = MFI_PD_ONLINE; 2191 cmd = MD_DCMD_PD_SET_STATE; 2192 break; 2193 2194 case BIOC_SSOFFLINE: 2195 mbox[2] = MFI_PD_OFFLINE; 2196 cmd = MD_DCMD_PD_SET_STATE; 2197 break; 2198 2199 case BIOC_SSHOTSPARE: 2200 mbox[2] = MFI_PD_HOTSPARE; 2201 cmd = MD_DCMD_PD_SET_STATE; 2202 break; 2203 /* 2204 case BIOC_SSREBUILD: 2205 cmd = MD_DCMD_PD_REBUILD; 2206 break; 2207 */ 2208 default: 2209 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_setstate invalid " 2210 "opcode %x\n", DEVNAME(sc), bs->bs_status); 2211 goto done; 2212 } 2213 2214 2215 if (mfi_mgmt_internal(sc, MD_DCMD_PD_SET_STATE, MFI_DATA_NONE, 2216 0, NULL, mbox)) 2217 goto done; 2218 2219 rv = 0; 2220 done: 2221 free(pd, M_DEVBUF); 2222 return rv; 2223 } 2224 2225 static int 2226 mfi_bio_hs(struct mfi_softc *sc, int volid, int type, void *bio_hs) 2227 { 2228 struct mfi_conf *cfg; 2229 struct mfi_hotspare *hs; 2230 struct mfi_pd_details *pd; 2231 struct bioc_disk *sdhs; 2232 struct bioc_vol *vdhs; 2233 struct scsipi_inquiry_data *inqbuf; 2234 char vend[8+16+4+1]; 2235 int i, rv = EINVAL; 2236 uint32_t size; 2237 uint8_t mbox[MFI_MBOX_SIZE]; 2238 2239 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs %d\n", DEVNAME(sc), volid); 2240 2241 if (!bio_hs) 2242 return EINVAL; 2243 2244 pd = malloc(sizeof *pd, M_DEVBUF, M_WAITOK | M_ZERO); 2245 2246 /* send single element command to retrieve size for full structure */ 2247 cfg = malloc(sizeof *cfg, M_DEVBUF, M_WAITOK); 2248 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 2249 sizeof *cfg, cfg, NULL)) 2250 goto freeme; 2251 2252 size = cfg->mfc_size; 2253 free(cfg, M_DEVBUF); 2254 2255 /* memory for read config */ 2256 cfg = malloc(size, M_DEVBUF, M_WAITOK|M_ZERO); 2257 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 2258 size, cfg, NULL)) 2259 goto freeme; 2260 2261 /* calculate offset to hs structure */ 2262 hs = (struct mfi_hotspare *)( 2263 ((uint8_t *)cfg) + offsetof(struct mfi_conf, mfc_array) + 2264 cfg->mfc_array_size * cfg->mfc_no_array + 2265 cfg->mfc_ld_size * cfg->mfc_no_ld); 2266 2267 if (volid < cfg->mfc_no_ld) 2268 goto freeme; /* not a hotspare */ 2269 2270 if (volid > (cfg->mfc_no_ld + cfg->mfc_no_hs)) 2271 goto freeme; /* not a hotspare */ 2272 2273 /* offset into hotspare structure */ 2274 i = volid - cfg->mfc_no_ld; 2275 2276 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs i %d volid %d no_ld %d no_hs %d " 2277 "hs %p cfg %p id %02x\n", DEVNAME(sc), i, volid, cfg->mfc_no_ld, 2278 cfg->mfc_no_hs, hs, cfg, hs[i].mhs_pd.mfp_id); 2279 2280 /* get pd fields */ 2281 memset(mbox, 0, sizeof mbox); 2282 *((uint16_t *)&mbox) = hs[i].mhs_pd.mfp_id; 2283 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_INFO, MFI_DATA_IN, 2284 sizeof *pd, pd, mbox)) { 2285 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs illegal PD\n", 2286 DEVNAME(sc)); 2287 goto freeme; 2288 } 2289 2290 switch (type) { 2291 case MFI_MGMT_VD: 2292 vdhs = bio_hs; 2293 vdhs->bv_status = BIOC_SVONLINE; 2294 vdhs->bv_size = pd->mpd_size * 512; /* bytes per block */ 2295 vdhs->bv_level = -1; /* hotspare */ 2296 vdhs->bv_nodisk = 1; 2297 break; 2298 2299 case MFI_MGMT_SD: 2300 sdhs = bio_hs; 2301 sdhs->bd_status = BIOC_SDHOTSPARE; 2302 sdhs->bd_size = pd->mpd_size * 512; /* bytes per block */ 2303 sdhs->bd_channel = pd->mpd_enc_idx; 2304 sdhs->bd_target = pd->mpd_enc_slot; 2305 inqbuf = (struct scsipi_inquiry_data *)&pd->mpd_inq_data; 2306 memcpy(vend, inqbuf->vendor, sizeof(vend) - 1); 2307 vend[sizeof vend - 1] = '\0'; 2308 strlcpy(sdhs->bd_vendor, vend, sizeof(sdhs->bd_vendor)); 2309 break; 2310 2311 default: 2312 goto freeme; 2313 } 2314 2315 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs 6\n", DEVNAME(sc)); 2316 rv = 0; 2317 freeme: 2318 free(pd, M_DEVBUF); 2319 free(cfg, M_DEVBUF); 2320 2321 return rv; 2322 } 2323 2324 static int 2325 mfi_destroy_sensors(struct mfi_softc *sc) 2326 { 2327 if (sc->sc_sme == NULL) 2328 return 0; 2329 sysmon_envsys_unregister(sc->sc_sme); 2330 sc->sc_sme = NULL; 2331 free(sc->sc_sensor, M_DEVBUF); 2332 return 0; 2333 } 2334 2335 static int 2336 mfi_create_sensors(struct mfi_softc *sc) 2337 { 2338 int i; 2339 int nsensors = sc->sc_ld_cnt; 2340 int rv; 2341 2342 sc->sc_sme = sysmon_envsys_create(); 2343 sc->sc_sensor = malloc(sizeof(envsys_data_t) * nsensors, 2344 M_DEVBUF, M_NOWAIT | M_ZERO); 2345 if (sc->sc_sensor == NULL) { 2346 aprint_error_dev(sc->sc_dev, "can't allocate envsys_data_t\n"); 2347 return ENOMEM; 2348 } 2349 2350 for (i = 0; i < nsensors; i++) { 2351 sc->sc_sensor[i].units = ENVSYS_DRIVE; 2352 sc->sc_sensor[i].state = ENVSYS_SINVALID; 2353 sc->sc_sensor[i].value_cur = ENVSYS_DRIVE_EMPTY; 2354 /* Enable monitoring for drive state changes */ 2355 sc->sc_sensor[i].flags |= ENVSYS_FMONSTCHANGED; 2356 /* logical drives */ 2357 snprintf(sc->sc_sensor[i].desc, 2358 sizeof(sc->sc_sensor[i].desc), "%s:%d", 2359 DEVNAME(sc), i); 2360 if (sysmon_envsys_sensor_attach(sc->sc_sme, 2361 &sc->sc_sensor[i])) 2362 goto out; 2363 } 2364 2365 sc->sc_sme->sme_name = DEVNAME(sc); 2366 sc->sc_sme->sme_cookie = sc; 2367 sc->sc_sme->sme_refresh = mfi_sensor_refresh; 2368 rv = sysmon_envsys_register(sc->sc_sme); 2369 if (rv != 0) { 2370 aprint_error_dev(sc->sc_dev, 2371 "unable to register with sysmon (rv = %d)\n", rv); 2372 goto out; 2373 } 2374 return 0; 2375 2376 out: 2377 free(sc->sc_sensor, M_DEVBUF); 2378 sysmon_envsys_destroy(sc->sc_sme); 2379 sc->sc_sme = NULL; 2380 return EINVAL; 2381 } 2382 2383 static void 2384 mfi_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 2385 { 2386 struct mfi_softc *sc = sme->sme_cookie; 2387 struct bioc_vol bv; 2388 int s; 2389 int error; 2390 2391 if (edata->sensor >= sc->sc_ld_cnt) 2392 return; 2393 2394 memset(&bv, 0, sizeof(bv)); 2395 bv.bv_volid = edata->sensor; 2396 KERNEL_LOCK(1, curlwp); 2397 s = splbio(); 2398 error = mfi_ioctl_vol(sc, &bv); 2399 splx(s); 2400 KERNEL_UNLOCK_ONE(curlwp); 2401 if (error) 2402 return; 2403 2404 switch(bv.bv_status) { 2405 case BIOC_SVOFFLINE: 2406 edata->value_cur = ENVSYS_DRIVE_FAIL; 2407 edata->state = ENVSYS_SCRITICAL; 2408 break; 2409 2410 case BIOC_SVDEGRADED: 2411 edata->value_cur = ENVSYS_DRIVE_PFAIL; 2412 edata->state = ENVSYS_SCRITICAL; 2413 break; 2414 2415 case BIOC_SVSCRUB: 2416 case BIOC_SVONLINE: 2417 edata->value_cur = ENVSYS_DRIVE_ONLINE; 2418 edata->state = ENVSYS_SVALID; 2419 break; 2420 2421 case BIOC_SVINVALID: 2422 /* FALLTRHOUGH */ 2423 default: 2424 edata->value_cur = 0; /* unknown */ 2425 edata->state = ENVSYS_SINVALID; 2426 } 2427 } 2428 2429 #endif /* NBIO > 0 */ 2430 2431 static uint32_t 2432 mfi_xscale_fw_state(struct mfi_softc *sc) 2433 { 2434 return mfi_read(sc, MFI_OMSG0); 2435 } 2436 2437 static void 2438 mfi_xscale_intr_dis(struct mfi_softc *sc) 2439 { 2440 mfi_write(sc, MFI_OMSK, 0); 2441 } 2442 2443 static void 2444 mfi_xscale_intr_ena(struct mfi_softc *sc) 2445 { 2446 mfi_write(sc, MFI_OMSK, MFI_ENABLE_INTR); 2447 } 2448 2449 static int 2450 mfi_xscale_intr(struct mfi_softc *sc) 2451 { 2452 uint32_t status; 2453 2454 status = mfi_read(sc, MFI_OSTS); 2455 if (!ISSET(status, MFI_OSTS_INTR_VALID)) 2456 return 0; 2457 2458 /* write status back to acknowledge interrupt */ 2459 mfi_write(sc, MFI_OSTS, status); 2460 return 1; 2461 } 2462 2463 static void 2464 mfi_xscale_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2465 { 2466 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 2467 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 2468 sc->sc_frames_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2469 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_sense), 2470 ccb->ccb_psense - MFIMEM_DVA(sc->sc_sense), 2471 MFI_SENSE_SIZE, BUS_DMASYNC_PREREAD); 2472 2473 mfi_write(sc, MFI_IQP, (ccb->ccb_pframe >> 3) | 2474 ccb->ccb_extra_frames); 2475 ccb->ccb_state = MFI_CCB_RUNNING; 2476 } 2477 2478 static uint32_t 2479 mfi_ppc_fw_state(struct mfi_softc *sc) 2480 { 2481 return mfi_read(sc, MFI_OSP); 2482 } 2483 2484 static void 2485 mfi_ppc_intr_dis(struct mfi_softc *sc) 2486 { 2487 /* Taking a wild guess --dyoung */ 2488 mfi_write(sc, MFI_OMSK, ~(uint32_t)0x0); 2489 mfi_write(sc, MFI_ODC, 0xffffffff); 2490 } 2491 2492 static void 2493 mfi_ppc_intr_ena(struct mfi_softc *sc) 2494 { 2495 mfi_write(sc, MFI_ODC, 0xffffffff); 2496 mfi_write(sc, MFI_OMSK, ~0x80000004); 2497 } 2498 2499 static int 2500 mfi_ppc_intr(struct mfi_softc *sc) 2501 { 2502 uint32_t status; 2503 2504 status = mfi_read(sc, MFI_OSTS); 2505 if (!ISSET(status, MFI_OSTS_PPC_INTR_VALID)) 2506 return 0; 2507 2508 /* write status back to acknowledge interrupt */ 2509 mfi_write(sc, MFI_ODC, status); 2510 return 1; 2511 } 2512 2513 static void 2514 mfi_ppc_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2515 { 2516 mfi_write(sc, MFI_IQP, 0x1 | ccb->ccb_pframe | 2517 (ccb->ccb_extra_frames << 1)); 2518 ccb->ccb_state = MFI_CCB_RUNNING; 2519 } 2520 2521 u_int32_t 2522 mfi_gen2_fw_state(struct mfi_softc *sc) 2523 { 2524 return (mfi_read(sc, MFI_OSP)); 2525 } 2526 2527 void 2528 mfi_gen2_intr_dis(struct mfi_softc *sc) 2529 { 2530 mfi_write(sc, MFI_OMSK, 0xffffffff); 2531 mfi_write(sc, MFI_ODC, 0xffffffff); 2532 } 2533 2534 void 2535 mfi_gen2_intr_ena(struct mfi_softc *sc) 2536 { 2537 mfi_write(sc, MFI_ODC, 0xffffffff); 2538 mfi_write(sc, MFI_OMSK, ~MFI_OSTS_GEN2_INTR_VALID); 2539 } 2540 2541 int 2542 mfi_gen2_intr(struct mfi_softc *sc) 2543 { 2544 u_int32_t status; 2545 2546 status = mfi_read(sc, MFI_OSTS); 2547 if (!ISSET(status, MFI_OSTS_GEN2_INTR_VALID)) 2548 return (0); 2549 2550 /* write status back to acknowledge interrupt */ 2551 mfi_write(sc, MFI_ODC, status); 2552 2553 return (1); 2554 } 2555 2556 void 2557 mfi_gen2_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2558 { 2559 mfi_write(sc, MFI_IQP, 0x1 | ccb->ccb_pframe | 2560 (ccb->ccb_extra_frames << 1)); 2561 ccb->ccb_state = MFI_CCB_RUNNING; 2562 } 2563 2564 u_int32_t 2565 mfi_skinny_fw_state(struct mfi_softc *sc) 2566 { 2567 return (mfi_read(sc, MFI_OSP)); 2568 } 2569 2570 void 2571 mfi_skinny_intr_dis(struct mfi_softc *sc) 2572 { 2573 mfi_write(sc, MFI_OMSK, 0); 2574 } 2575 2576 void 2577 mfi_skinny_intr_ena(struct mfi_softc *sc) 2578 { 2579 mfi_write(sc, MFI_OMSK, ~0x00000001); 2580 } 2581 2582 int 2583 mfi_skinny_intr(struct mfi_softc *sc) 2584 { 2585 u_int32_t status; 2586 2587 status = mfi_read(sc, MFI_OSTS); 2588 if (!ISSET(status, MFI_OSTS_SKINNY_INTR_VALID)) 2589 return (0); 2590 2591 /* write status back to acknowledge interrupt */ 2592 mfi_write(sc, MFI_OSTS, status); 2593 2594 return (1); 2595 } 2596 2597 void 2598 mfi_skinny_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2599 { 2600 mfi_write(sc, MFI_IQPL, 0x1 | ccb->ccb_pframe | 2601 (ccb->ccb_extra_frames << 1)); 2602 mfi_write(sc, MFI_IQPH, 0x00000000); 2603 ccb->ccb_state = MFI_CCB_RUNNING; 2604 } 2605 2606 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008) 2607 2608 void 2609 mfi_tbolt_intr_ena(struct mfi_softc *sc) 2610 { 2611 mfi_write(sc, MFI_OMSK, ~MFI_FUSION_ENABLE_INTERRUPT_MASK); 2612 mfi_read(sc, MFI_OMSK); 2613 } 2614 2615 void 2616 mfi_tbolt_intr_dis(struct mfi_softc *sc) 2617 { 2618 mfi_write(sc, MFI_OMSK, 0xFFFFFFFF); 2619 mfi_read(sc, MFI_OMSK); 2620 } 2621 2622 int 2623 mfi_tbolt_intr(struct mfi_softc *sc) 2624 { 2625 int32_t status; 2626 2627 status = mfi_read(sc, MFI_OSTS); 2628 2629 if (ISSET(status, 0x1)) { 2630 mfi_write(sc, MFI_OSTS, status); 2631 mfi_read(sc, MFI_OSTS); 2632 if (ISSET(status, MFI_STATE_CHANGE_INTERRUPT)) 2633 return 0; 2634 return 1; 2635 } 2636 if (!ISSET(status, MFI_FUSION_ENABLE_INTERRUPT_MASK)) 2637 return 0; 2638 mfi_read(sc, MFI_OSTS); 2639 return 1; 2640 } 2641 2642 u_int32_t 2643 mfi_tbolt_fw_state(struct mfi_softc *sc) 2644 { 2645 return mfi_read(sc, MFI_OSP); 2646 } 2647 2648 void 2649 mfi_tbolt_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2650 { 2651 if (sc->sc_MFA_enabled) { 2652 if ((ccb->ccb_flags & MFI_CCB_F_TBOLT) == 0) 2653 mfi_tbolt_build_mpt_ccb(ccb); 2654 mfi_write(sc, MFI_IQPL, 2655 ccb->ccb_tb_request_desc.words & 0xFFFFFFFF); 2656 mfi_write(sc, MFI_IQPH, 2657 ccb->ccb_tb_request_desc.words >> 32); 2658 ccb->ccb_state = MFI_CCB_RUNNING; 2659 return; 2660 } 2661 uint64_t bus_add = ccb->ccb_pframe; 2662 bus_add |= (MFI_REQ_DESCRIPT_FLAGS_MFA 2663 << MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2664 mfi_write(sc, MFI_IQPL, bus_add); 2665 mfi_write(sc, MFI_IQPH, bus_add >> 32); 2666 ccb->ccb_state = MFI_CCB_RUNNING; 2667 } 2668 2669 static void 2670 mfi_tbolt_build_mpt_ccb(struct mfi_ccb *ccb) 2671 { 2672 union mfi_mpi2_request_descriptor *req_desc = &ccb->ccb_tb_request_desc; 2673 struct mfi_mpi2_request_raid_scsi_io *io_req = ccb->ccb_tb_io_request; 2674 struct mpi25_ieee_sge_chain64 *mpi25_ieee_chain; 2675 2676 io_req->Function = MPI2_FUNCTION_PASSTHRU_IO_REQUEST; 2677 io_req->SGLOffset0 = 2678 offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 4; 2679 io_req->ChainOffset = 2680 offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16; 2681 2682 mpi25_ieee_chain = 2683 (struct mpi25_ieee_sge_chain64 *)&io_req->SGL.IeeeChain; 2684 mpi25_ieee_chain->Address = ccb->ccb_pframe; 2685 2686 /* 2687 In MFI pass thru, nextChainOffset will always be zero to 2688 indicate the end of the chain. 2689 */ 2690 mpi25_ieee_chain->Flags= MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT 2691 | MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR; 2692 2693 /* setting the length to the maximum length */ 2694 mpi25_ieee_chain->Length = 1024; 2695 2696 req_desc->header.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << 2697 MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2698 ccb->ccb_flags |= MFI_CCB_F_TBOLT; 2699 bus_dmamap_sync(ccb->ccb_sc->sc_dmat, 2700 MFIMEM_MAP(ccb->ccb_sc->sc_tbolt_reqmsgpool), 2701 ccb->ccb_tb_pio_request - 2702 MFIMEM_DVA(ccb->ccb_sc->sc_tbolt_reqmsgpool), 2703 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE, 2704 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2705 } 2706 2707 /* 2708 * Description: 2709 * This function will prepare message pools for the Thunderbolt controller 2710 */ 2711 static int 2712 mfi_tbolt_init_desc_pool(struct mfi_softc *sc) 2713 { 2714 uint32_t offset = 0; 2715 uint8_t *addr = MFIMEM_KVA(sc->sc_tbolt_reqmsgpool); 2716 2717 /* Request Decriptors alignement restrictions */ 2718 KASSERT(((uintptr_t)addr & 0xFF) == 0); 2719 2720 /* Skip request message pool */ 2721 addr = &addr[MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1)]; 2722 2723 /* Reply Frame Pool is initialized */ 2724 sc->sc_reply_frame_pool = (struct mfi_mpi2_reply_header *) addr; 2725 KASSERT(((uintptr_t)addr & 0xFF) == 0); 2726 2727 offset = (uintptr_t)sc->sc_reply_frame_pool 2728 - (uintptr_t)MFIMEM_KVA(sc->sc_tbolt_reqmsgpool); 2729 sc->sc_reply_frame_busaddr = 2730 MFIMEM_DVA(sc->sc_tbolt_reqmsgpool) + offset; 2731 2732 /* initializing reply address to 0xFFFFFFFF */ 2733 memset((uint8_t *)sc->sc_reply_frame_pool, 0xFF, 2734 (MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size)); 2735 2736 /* Skip Reply Frame Pool */ 2737 addr += MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size; 2738 sc->sc_reply_pool_limit = (void *)addr; 2739 2740 offset = MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size; 2741 sc->sc_sg_frame_busaddr = sc->sc_reply_frame_busaddr + offset; 2742 2743 /* initialize the last_reply_idx to 0 */ 2744 sc->sc_last_reply_idx = 0; 2745 offset = (sc->sc_sg_frame_busaddr + (MEGASAS_MAX_SZ_CHAIN_FRAME * 2746 sc->sc_max_cmds)) - MFIMEM_DVA(sc->sc_tbolt_reqmsgpool); 2747 KASSERT(offset <= sc->sc_tbolt_reqmsgpool->am_size); 2748 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 0, 2749 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool)->dm_mapsize, 2750 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2751 return 0; 2752 } 2753 2754 /* 2755 * This routine prepare and issue INIT2 frame to the Firmware 2756 */ 2757 2758 static int 2759 mfi_tbolt_init_MFI_queue(struct mfi_softc *sc) 2760 { 2761 struct mpi2_ioc_init_request *mpi2IocInit; 2762 struct mfi_init_frame *mfi_init; 2763 struct mfi_ccb *ccb; 2764 bus_addr_t phyAddress; 2765 mfi_address *mfiAddressTemp; 2766 int s; 2767 char *verbuf; 2768 char wqbuf[10]; 2769 2770 /* Check if initialization is already completed */ 2771 if (sc->sc_MFA_enabled) { 2772 return 1; 2773 } 2774 2775 mpi2IocInit = 2776 (struct mpi2_ioc_init_request *)MFIMEM_KVA(sc->sc_tbolt_ioc_init); 2777 2778 s = splbio(); 2779 if ((ccb = mfi_get_ccb(sc)) == NULL) { 2780 splx(s); 2781 return (EBUSY); 2782 } 2783 2784 2785 mfi_init = &ccb->ccb_frame->mfr_init; 2786 2787 memset(mpi2IocInit, 0, sizeof(struct mpi2_ioc_init_request)); 2788 mpi2IocInit->Function = MPI2_FUNCTION_IOC_INIT; 2789 mpi2IocInit->WhoInit = MPI2_WHOINIT_HOST_DRIVER; 2790 2791 /* set MsgVersion and HeaderVersion host driver was built with */ 2792 mpi2IocInit->MsgVersion = MPI2_VERSION; 2793 mpi2IocInit->HeaderVersion = MPI2_HEADER_VERSION; 2794 mpi2IocInit->SystemRequestFrameSize = MEGASAS_THUNDERBOLT_NEW_MSG_SIZE/4; 2795 mpi2IocInit->ReplyDescriptorPostQueueDepth = 2796 (uint16_t)sc->sc_reply_pool_size; 2797 mpi2IocInit->ReplyFreeQueueDepth = 0; /* Not supported by MR. */ 2798 2799 /* Get physical address of reply frame pool */ 2800 phyAddress = sc->sc_reply_frame_busaddr; 2801 mfiAddressTemp = 2802 (mfi_address *)&mpi2IocInit->ReplyDescriptorPostQueueAddress; 2803 mfiAddressTemp->u.addressLow = (uint32_t)phyAddress; 2804 mfiAddressTemp->u.addressHigh = (uint32_t)((uint64_t)phyAddress >> 32); 2805 2806 /* Get physical address of request message pool */ 2807 phyAddress = MFIMEM_DVA(sc->sc_tbolt_reqmsgpool); 2808 mfiAddressTemp = (mfi_address *)&mpi2IocInit->SystemRequestFrameBaseAddress; 2809 mfiAddressTemp->u.addressLow = (uint32_t)phyAddress; 2810 mfiAddressTemp->u.addressHigh = (uint32_t)((uint64_t)phyAddress >> 32); 2811 2812 mpi2IocInit->ReplyFreeQueueAddress = 0; /* Not supported by MR. */ 2813 mpi2IocInit->TimeStamp = time_uptime; 2814 2815 verbuf = MFIMEM_KVA(sc->sc_tbolt_verbuf); 2816 snprintf(verbuf, strlen(MEGASAS_VERSION) + 2, "%s\n", 2817 MEGASAS_VERSION); 2818 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_verbuf), 0, 2819 MFIMEM_MAP(sc->sc_tbolt_verbuf)->dm_mapsize, BUS_DMASYNC_PREWRITE); 2820 mfi_init->driver_ver_lo = htole32(MFIMEM_DVA(sc->sc_tbolt_verbuf)); 2821 mfi_init->driver_ver_hi = 2822 htole32((uint64_t)MFIMEM_DVA(sc->sc_tbolt_verbuf) >> 32); 2823 2824 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_ioc_init), 0, 2825 MFIMEM_MAP(sc->sc_tbolt_ioc_init)->dm_mapsize, 2826 BUS_DMASYNC_PREWRITE); 2827 /* Get the physical address of the mpi2 ioc init command */ 2828 phyAddress = MFIMEM_DVA(sc->sc_tbolt_ioc_init); 2829 mfi_init->mif_qinfo_new_addr_lo = htole32(phyAddress); 2830 mfi_init->mif_qinfo_new_addr_hi = htole32((uint64_t)phyAddress >> 32); 2831 2832 mfi_init->mif_header.mfh_cmd = MFI_CMD_INIT; 2833 mfi_init->mif_header.mfh_data_len = sizeof(struct mpi2_ioc_init_request); 2834 if (mfi_poll(ccb) != 0) { 2835 aprint_error_dev(sc->sc_dev, "failed to send IOC init2 " 2836 "command at 0x%" PRIx64 "\n", 2837 (uint64_t)ccb->ccb_pframe); 2838 splx(s); 2839 return 1; 2840 } 2841 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_verbuf), 0, 2842 MFIMEM_MAP(sc->sc_tbolt_verbuf)->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2843 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_ioc_init), 0, 2844 MFIMEM_MAP(sc->sc_tbolt_ioc_init)->dm_mapsize, 2845 BUS_DMASYNC_POSTWRITE); 2846 mfi_put_ccb(ccb); 2847 splx(s); 2848 2849 if (mfi_init->mif_header.mfh_cmd_status == 0) { 2850 sc->sc_MFA_enabled = 1; 2851 } 2852 else { 2853 aprint_error_dev(sc->sc_dev, "Init command Failed %x\n", 2854 mfi_init->mif_header.mfh_cmd_status); 2855 return 1; 2856 } 2857 2858 snprintf(wqbuf, sizeof(wqbuf), "%swq", DEVNAME(sc)); 2859 if (workqueue_create(&sc->sc_ldsync_wq, wqbuf, mfi_tbolt_sync_map_info, 2860 sc, PRIBIO, IPL_BIO, 0) != 0) { 2861 aprint_error_dev(sc->sc_dev, "workqueue_create failed\n"); 2862 return 1; 2863 } 2864 workqueue_enqueue(sc->sc_ldsync_wq, &sc->sc_ldsync_wk, NULL); 2865 return 0; 2866 } 2867 2868 int 2869 mfi_tbolt_intrh(void *arg) 2870 { 2871 struct mfi_softc *sc = arg; 2872 struct mfi_ccb *ccb; 2873 union mfi_mpi2_reply_descriptor *desc; 2874 int smid, num_completed; 2875 2876 if (!mfi_tbolt_intr(sc)) 2877 return 0; 2878 2879 DNPRINTF(MFI_D_INTR, "%s: mfi_tbolt_intrh %#lx %#lx\n", DEVNAME(sc), 2880 (u_long)sc, (u_long)sc->sc_last_reply_idx); 2881 2882 KASSERT(sc->sc_last_reply_idx < sc->sc_reply_pool_size); 2883 2884 desc = (union mfi_mpi2_reply_descriptor *) 2885 ((uintptr_t)sc->sc_reply_frame_pool + 2886 sc->sc_last_reply_idx * MEGASAS_THUNDERBOLT_REPLY_SIZE); 2887 2888 bus_dmamap_sync(sc->sc_dmat, 2889 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 2890 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1), 2891 MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size, 2892 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2893 num_completed = 0; 2894 while ((desc->header.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK) != 2895 MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 2896 smid = desc->header.SMID; 2897 KASSERT(smid > 0 && smid <= sc->sc_max_cmds); 2898 ccb = &sc->sc_ccb[smid - 1]; 2899 DNPRINTF(MFI_D_INTR, 2900 "%s: mfi_tbolt_intr SMID %#x reply_idx %#x " 2901 "desc %#" PRIx64 " ccb %p\n", DEVNAME(sc), smid, 2902 sc->sc_last_reply_idx, desc->words, ccb); 2903 KASSERT(ccb->ccb_state == MFI_CCB_RUNNING); 2904 if (ccb->ccb_flags & MFI_CCB_F_TBOLT_IO && 2905 ccb->ccb_tb_io_request->ChainOffset != 0) { 2906 bus_dmamap_sync(sc->sc_dmat, 2907 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 2908 ccb->ccb_tb_psg_frame - 2909 MFIMEM_DVA(sc->sc_tbolt_reqmsgpool), 2910 MEGASAS_MAX_SZ_CHAIN_FRAME, BUS_DMASYNC_POSTREAD); 2911 } 2912 if (ccb->ccb_flags & MFI_CCB_F_TBOLT_IO) { 2913 bus_dmamap_sync(sc->sc_dmat, 2914 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 2915 ccb->ccb_tb_pio_request - 2916 MFIMEM_DVA(sc->sc_tbolt_reqmsgpool), 2917 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE, 2918 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2919 } 2920 if (ccb->ccb_done) 2921 ccb->ccb_done(ccb); 2922 else 2923 ccb->ccb_state = MFI_CCB_DONE; 2924 sc->sc_last_reply_idx++; 2925 if (sc->sc_last_reply_idx >= sc->sc_reply_pool_size) { 2926 sc->sc_last_reply_idx = 0; 2927 } 2928 desc->words = ~0x0; 2929 /* Get the next reply descriptor */ 2930 desc = (union mfi_mpi2_reply_descriptor *) 2931 ((uintptr_t)sc->sc_reply_frame_pool + 2932 sc->sc_last_reply_idx * MEGASAS_THUNDERBOLT_REPLY_SIZE); 2933 num_completed++; 2934 } 2935 if (num_completed == 0) 2936 return 0; 2937 2938 bus_dmamap_sync(sc->sc_dmat, 2939 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 2940 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1), 2941 MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size, 2942 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2943 mfi_write(sc, MFI_RPI, sc->sc_last_reply_idx); 2944 return 1; 2945 } 2946 2947 2948 int 2949 mfi_tbolt_scsi_ld_io(struct mfi_ccb *ccb, struct scsipi_xfer *xs, 2950 uint64_t blockno, uint32_t blockcnt) 2951 { 2952 struct scsipi_periph *periph = xs->xs_periph; 2953 struct mfi_mpi2_request_raid_scsi_io *io_req; 2954 int sge_count; 2955 2956 DNPRINTF(MFI_D_CMD, "%s: mfi_tbolt_scsi_ld_io: %d\n", 2957 device_xname(periph->periph_channel->chan_adapter->adapt_dev), 2958 periph->periph_target); 2959 2960 if (!xs->data) 2961 return 1; 2962 2963 ccb->ccb_done = mfi_tbolt_scsi_ld_done; 2964 ccb->ccb_xs = xs; 2965 ccb->ccb_data = xs->data; 2966 ccb->ccb_len = xs->datalen; 2967 2968 io_req = ccb->ccb_tb_io_request; 2969 2970 /* Just the CDB length,rest of the Flags are zero */ 2971 io_req->IoFlags = xs->cmdlen; 2972 memset(io_req->CDB.CDB32, 0, 32); 2973 memcpy(io_req->CDB.CDB32, &xs->cmdstore, xs->cmdlen); 2974 2975 io_req->RaidContext.TargetID = periph->periph_target; 2976 io_req->RaidContext.Status = 0; 2977 io_req->RaidContext.exStatus = 0; 2978 io_req->RaidContext.timeoutValue = MFI_FUSION_FP_DEFAULT_TIMEOUT; 2979 io_req->Function = MPI2_FUNCTION_LD_IO_REQUEST; 2980 io_req->DevHandle = periph->periph_target; 2981 2982 ccb->ccb_tb_request_desc.header.RequestFlags = 2983 (MFI_REQ_DESCRIPT_FLAGS_LD_IO << MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2984 io_req->DataLength = blockcnt * MFI_SECTOR_LEN; 2985 2986 if (xs->xs_control & XS_CTL_DATA_IN) { 2987 io_req->Control = MPI2_SCSIIO_CONTROL_READ; 2988 ccb->ccb_direction = MFI_DATA_IN; 2989 } else { 2990 io_req->Control = MPI2_SCSIIO_CONTROL_WRITE; 2991 ccb->ccb_direction = MFI_DATA_OUT; 2992 } 2993 2994 sge_count = mfi_tbolt_create_sgl(ccb, 2995 (xs->xs_control & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK 2996 ); 2997 if (sge_count < 0) 2998 return 1; 2999 KASSERT(sge_count <= ccb->ccb_sc->sc_max_sgl); 3000 io_req->RaidContext.numSGE = sge_count; 3001 io_req->SGLFlags = MPI2_SGE_FLAGS_64_BIT_ADDRESSING; 3002 io_req->SGLOffset0 = 3003 offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 4; 3004 3005 io_req->SenseBufferLowAddress = htole32(ccb->ccb_psense); 3006 io_req->SenseBufferLength = MFI_SENSE_SIZE; 3007 3008 ccb->ccb_flags |= MFI_CCB_F_TBOLT | MFI_CCB_F_TBOLT_IO; 3009 bus_dmamap_sync(ccb->ccb_sc->sc_dmat, 3010 MFIMEM_MAP(ccb->ccb_sc->sc_tbolt_reqmsgpool), 3011 ccb->ccb_tb_pio_request - 3012 MFIMEM_DVA(ccb->ccb_sc->sc_tbolt_reqmsgpool), 3013 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE, 3014 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3015 3016 return 0; 3017 } 3018 3019 3020 static void 3021 mfi_tbolt_scsi_ld_done(struct mfi_ccb *ccb) 3022 { 3023 struct mfi_mpi2_request_raid_scsi_io *io_req = ccb->ccb_tb_io_request; 3024 mfi_scsi_xs_done(ccb, io_req->RaidContext.Status, 3025 io_req->RaidContext.exStatus); 3026 } 3027 3028 static int 3029 mfi_tbolt_create_sgl(struct mfi_ccb *ccb, int flags) 3030 { 3031 struct mfi_softc *sc = ccb->ccb_sc; 3032 bus_dma_segment_t *sgd; 3033 int error, i, sge_idx, sge_count; 3034 struct mfi_mpi2_request_raid_scsi_io *io_req; 3035 struct mpi25_ieee_sge_chain64 *sgl_ptr; 3036 3037 DNPRINTF(MFI_D_DMA, "%s: mfi_tbolt_create_sgl %#lx\n", DEVNAME(sc), 3038 (u_long)ccb->ccb_data); 3039 3040 if (!ccb->ccb_data) 3041 return -1; 3042 3043 KASSERT(flags == BUS_DMA_NOWAIT || !cpu_intr_p()); 3044 error = bus_dmamap_load(sc->sc_datadmat, ccb->ccb_dmamap, 3045 ccb->ccb_data, ccb->ccb_len, NULL, flags); 3046 if (error) { 3047 if (error == EFBIG) 3048 aprint_error_dev(sc->sc_dev, "more than %d dma segs\n", 3049 sc->sc_max_sgl); 3050 else 3051 aprint_error_dev(sc->sc_dev, 3052 "error %d loading dma map\n", error); 3053 return -1; 3054 } 3055 3056 io_req = ccb->ccb_tb_io_request; 3057 sgl_ptr = &io_req->SGL.IeeeChain.Chain64; 3058 sge_count = ccb->ccb_dmamap->dm_nsegs; 3059 sgd = ccb->ccb_dmamap->dm_segs; 3060 KASSERT(sge_count <= sc->sc_max_sgl); 3061 KASSERT(sge_count <= 3062 (MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG - 1 + 3063 MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG)); 3064 3065 if (sge_count > MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG) { 3066 /* One element to store the chain info */ 3067 sge_idx = MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG - 1; 3068 DNPRINTF(MFI_D_DMA, 3069 "mfi sge_idx %d sge_count %d io_req paddr 0x%" PRIx64 "\n", 3070 sge_idx, sge_count, ccb->ccb_tb_pio_request); 3071 } else { 3072 sge_idx = sge_count; 3073 } 3074 3075 for (i = 0; i < sge_idx; i++) { 3076 sgl_ptr->Address = htole64(sgd[i].ds_addr); 3077 sgl_ptr->Length = htole32(sgd[i].ds_len); 3078 sgl_ptr->Flags = 0; 3079 if (sge_idx < sge_count) { 3080 DNPRINTF(MFI_D_DMA, 3081 "sgl %p %d 0x%" PRIx64 " len 0x%" PRIx32 3082 " flags 0x%x\n", sgl_ptr, i, 3083 sgl_ptr->Address, sgl_ptr->Length, 3084 sgl_ptr->Flags); 3085 } 3086 sgl_ptr++; 3087 } 3088 io_req->ChainOffset = 0; 3089 if (sge_idx < sge_count) { 3090 struct mpi25_ieee_sge_chain64 *sg_chain; 3091 io_req->ChainOffset = MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG; 3092 sg_chain = sgl_ptr; 3093 /* Prepare chain element */ 3094 sg_chain->NextChainOffset = 0; 3095 sg_chain->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3096 MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR); 3097 sg_chain->Length = (sizeof(mpi2_sge_io_union) * 3098 (sge_count - sge_idx)); 3099 sg_chain->Address = ccb->ccb_tb_psg_frame; 3100 DNPRINTF(MFI_D_DMA, 3101 "sgl %p chain 0x%" PRIx64 " len 0x%" PRIx32 3102 " flags 0x%x\n", sg_chain, sg_chain->Address, 3103 sg_chain->Length, sg_chain->Flags); 3104 sgl_ptr = &ccb->ccb_tb_sg_frame->IeeeChain.Chain64; 3105 for (; i < sge_count; i++) { 3106 sgl_ptr->Address = htole64(sgd[i].ds_addr); 3107 sgl_ptr->Length = htole32(sgd[i].ds_len); 3108 sgl_ptr->Flags = 0; 3109 DNPRINTF(MFI_D_DMA, 3110 "sgl %p %d 0x%" PRIx64 " len 0x%" PRIx32 3111 " flags 0x%x\n", sgl_ptr, i, sgl_ptr->Address, 3112 sgl_ptr->Length, sgl_ptr->Flags); 3113 sgl_ptr++; 3114 } 3115 bus_dmamap_sync(sc->sc_dmat, 3116 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 3117 ccb->ccb_tb_psg_frame - MFIMEM_DVA(sc->sc_tbolt_reqmsgpool), 3118 MEGASAS_MAX_SZ_CHAIN_FRAME, BUS_DMASYNC_PREREAD); 3119 } 3120 3121 if (ccb->ccb_direction == MFI_DATA_IN) { 3122 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 3123 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3124 } else { 3125 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 3126 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3127 } 3128 return sge_count; 3129 } 3130 3131 /* 3132 * The ThunderBolt HW has an option for the driver to directly 3133 * access the underlying disks and operate on the RAID. To 3134 * do this there needs to be a capability to keep the RAID controller 3135 * and driver in sync. The FreeBSD driver does not take advantage 3136 * of this feature since it adds a lot of complexity and slows down 3137 * performance. Performance is gained by using the controller's 3138 * cache etc. 3139 * 3140 * Even though this driver doesn't access the disks directly, an 3141 * AEN like command is used to inform the RAID firmware to "sync" 3142 * with all LD's via the MFI_DCMD_LD_MAP_GET_INFO command. This 3143 * command in write mode will return when the RAID firmware has 3144 * detected a change to the RAID state. Examples of this type 3145 * of change are removing a disk. Once the command returns then 3146 * the driver needs to acknowledge this and "sync" all LD's again. 3147 * This repeats until we shutdown. Then we need to cancel this 3148 * pending command. 3149 * 3150 * If this is not done right the RAID firmware will not remove a 3151 * pulled drive and the RAID won't go degraded etc. Effectively, 3152 * stopping any RAID mangement to functions. 3153 * 3154 * Doing another LD sync, requires the use of an event since the 3155 * driver needs to do a mfi_wait_command and can't do that in an 3156 * interrupt thread. 3157 * 3158 * The driver could get the RAID state via the MFI_DCMD_LD_MAP_GET_INFO 3159 * That requires a bunch of structure and it is simplier to just do 3160 * the MFI_DCMD_LD_GET_LIST versus walking the RAID map. 3161 */ 3162 3163 void 3164 mfi_tbolt_sync_map_info(struct work *w, void *v) 3165 { 3166 struct mfi_softc *sc = v; 3167 int i; 3168 struct mfi_ccb *ccb = NULL; 3169 uint8_t mbox[MFI_MBOX_SIZE]; 3170 struct mfi_ld *ld_sync = NULL; 3171 size_t ld_size; 3172 int s; 3173 3174 DNPRINTF(MFI_D_SYNC, "%s: mfi_tbolt_sync_map_info\n", DEVNAME(sc)); 3175 again: 3176 s = splbio(); 3177 if (sc->sc_ldsync_ccb != NULL) { 3178 splx(s); 3179 return; 3180 } 3181 3182 if (mfi_mgmt_internal(sc, MR_DCMD_LD_GET_LIST, MFI_DATA_IN, 3183 sizeof(sc->sc_ld_list), &sc->sc_ld_list, NULL)) { 3184 aprint_error_dev(sc->sc_dev, "MR_DCMD_LD_GET_LIST failed\n"); 3185 goto err; 3186 } 3187 3188 ld_size = sizeof(*ld_sync) * sc->sc_ld_list.mll_no_ld; 3189 3190 ld_sync = (struct mfi_ld *) malloc(ld_size, M_DEVBUF, 3191 M_WAITOK | M_ZERO); 3192 if (ld_sync == NULL) { 3193 aprint_error_dev(sc->sc_dev, "Failed to allocate sync\n"); 3194 goto err; 3195 } 3196 for (i = 0; i < sc->sc_ld_list.mll_no_ld; i++) { 3197 ld_sync[i] = sc->sc_ld_list.mll_list[i].mll_ld; 3198 } 3199 3200 if ((ccb = mfi_get_ccb(sc)) == NULL) { 3201 aprint_error_dev(sc->sc_dev, "Failed to get sync command\n"); 3202 free(ld_sync, M_DEVBUF); 3203 goto err; 3204 } 3205 sc->sc_ldsync_ccb = ccb; 3206 3207 memset(mbox, 0, MFI_MBOX_SIZE); 3208 mbox[0] = sc->sc_ld_list.mll_no_ld; 3209 mbox[1] = MFI_DCMD_MBOX_PEND_FLAG; 3210 if (mfi_mgmt(ccb, NULL, MR_DCMD_LD_MAP_GET_INFO, MFI_DATA_OUT, 3211 ld_size, ld_sync, mbox)) { 3212 aprint_error_dev(sc->sc_dev, "Failed to create sync command\n"); 3213 goto err; 3214 } 3215 /* 3216 * we won't sleep on this command, so we have to override 3217 * the callback set up by mfi_mgmt() 3218 */ 3219 ccb->ccb_done = mfi_sync_map_complete; 3220 3221 mfi_post(sc, ccb); 3222 splx(s); 3223 return; 3224 3225 err: 3226 if (ld_sync) 3227 free(ld_sync, M_DEVBUF); 3228 if (ccb) 3229 mfi_put_ccb(ccb); 3230 sc->sc_ldsync_ccb = NULL; 3231 splx(s); 3232 kpause("ldsyncp", 0, hz, NULL); 3233 goto again; 3234 } 3235 3236 static void 3237 mfi_sync_map_complete(struct mfi_ccb *ccb) 3238 { 3239 struct mfi_softc *sc = ccb->ccb_sc; 3240 int aborted = 0; 3241 3242 DNPRINTF(MFI_D_SYNC, "%s: mfi_sync_map_complete\n", 3243 DEVNAME(ccb->ccb_sc)); 3244 KASSERT(sc->sc_ldsync_ccb == ccb); 3245 mfi_mgmt_done(ccb); 3246 free(ccb->ccb_data, M_DEVBUF); 3247 if (ccb->ccb_flags & MFI_CCB_F_ERR) { 3248 aprint_error_dev(sc->sc_dev, "sync command failed\n"); 3249 aborted = 1; 3250 } 3251 mfi_put_ccb(ccb); 3252 sc->sc_ldsync_ccb = NULL; 3253 3254 /* set it up again so the driver can catch more events */ 3255 if (!aborted) { 3256 workqueue_enqueue(sc->sc_ldsync_wq, &sc->sc_ldsync_wk, NULL); 3257 } 3258 } 3259
Indexes created Fri Sep 26 08:10:20 GMT 2025