mfi.c revision 1.53
1 /* $NetBSD: mfi.c,v 1.53 2014/07/25 08:10:37 dholland Exp $ */ 2 /* $OpenBSD: mfi.c,v 1.66 2006/11/28 23:59:45 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2012 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 30 * 31 * Permission to use, copy, modify, and distribute this software for any 32 * purpose with or without fee is hereby granted, provided that the above 33 * copyright notice and this permission notice appear in all copies. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 36 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 37 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 38 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 39 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 40 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 41 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 42 */ 43 44 /*- 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 49 * Copyright 1994-2009 The FreeBSD Project. 50 * All rights reserved. 51 * 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE FREEBSD PROJECT``AS IS'' AND 59 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 60 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 61 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FREEBSD PROJECT OR 62 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 63 * EXEMPLARY,OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 64 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 65 * PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY THEORY 66 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 67 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 68 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * The views and conclusions contained in the software and documentation 71 * are those of the authors and should not be interpreted as representing 72 * official policies,either expressed or implied, of the FreeBSD Project. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: mfi.c,v 1.53 2014/07/25 08:10:37 dholland Exp $"); 77 78 #include "bio.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/buf.h> 83 #include <sys/ioctl.h> 84 #include <sys/device.h> 85 #include <sys/kernel.h> 86 #include <sys/malloc.h> 87 #include <sys/proc.h> 88 #include <sys/cpu.h> 89 #include <sys/conf.h> 90 #include <sys/kauth.h> 91 92 #include <uvm/uvm_param.h> 93 94 #include <sys/bus.h> 95 96 #include <dev/scsipi/scsipi_all.h> 97 #include <dev/scsipi/scsi_all.h> 98 #include <dev/scsipi/scsi_spc.h> 99 #include <dev/scsipi/scsipi_disk.h> 100 #include <dev/scsipi/scsi_disk.h> 101 #include <dev/scsipi/scsiconf.h> 102 103 #include <dev/ic/mfireg.h> 104 #include <dev/ic/mfivar.h> 105 #include <dev/ic/mfiio.h> 106 107 #if NBIO > 0 108 #include <dev/biovar.h> 109 #endif /* NBIO > 0 */ 110 111 #ifdef MFI_DEBUG 112 uint32_t mfi_debug = 0 113 /* | MFI_D_CMD */ 114 /* | MFI_D_INTR */ 115 /* | MFI_D_MISC */ 116 /* | MFI_D_DMA */ 117 /* | MFI_D_IOCTL */ 118 /* | MFI_D_RW */ 119 /* | MFI_D_MEM */ 120 /* | MFI_D_CCB */ 121 /* | MFI_D_SYNC */ 122 ; 123 #endif 124 125 static void mfi_scsipi_request(struct scsipi_channel *, 126 scsipi_adapter_req_t, void *); 127 static void mfiminphys(struct buf *bp); 128 129 static struct mfi_ccb *mfi_get_ccb(struct mfi_softc *); 130 static void mfi_put_ccb(struct mfi_ccb *); 131 static int mfi_init_ccb(struct mfi_softc *); 132 133 static struct mfi_mem *mfi_allocmem(struct mfi_softc *, size_t); 134 static void mfi_freemem(struct mfi_softc *, struct mfi_mem **); 135 136 static int mfi_transition_firmware(struct mfi_softc *); 137 static int mfi_initialize_firmware(struct mfi_softc *); 138 static int mfi_get_info(struct mfi_softc *); 139 static int mfi_get_bbu(struct mfi_softc *, 140 struct mfi_bbu_status *); 141 /* return codes for mfi_get_bbu */ 142 #define MFI_BBU_GOOD 0 143 #define MFI_BBU_BAD 1 144 #define MFI_BBU_UNKNOWN 2 145 static uint32_t mfi_read(struct mfi_softc *, bus_size_t); 146 static void mfi_write(struct mfi_softc *, bus_size_t, uint32_t); 147 static int mfi_poll(struct mfi_ccb *); 148 static int mfi_create_sgl(struct mfi_ccb *, int); 149 150 /* commands */ 151 static int mfi_scsi_ld(struct mfi_ccb *, struct scsipi_xfer *); 152 static int mfi_scsi_ld_io(struct mfi_ccb *, struct scsipi_xfer *, 153 uint64_t, uint32_t); 154 static void mfi_scsi_ld_done(struct mfi_ccb *); 155 static void mfi_scsi_xs_done(struct mfi_ccb *, int, int); 156 static int mfi_mgmt_internal(struct mfi_softc *, uint32_t, 157 uint32_t, uint32_t, void *, uint8_t *, bool); 158 static int mfi_mgmt(struct mfi_ccb *,struct scsipi_xfer *, 159 uint32_t, uint32_t, uint32_t, void *, uint8_t *); 160 static void mfi_mgmt_done(struct mfi_ccb *); 161 162 #if NBIO > 0 163 static int mfi_ioctl(device_t, u_long, void *); 164 static int mfi_ioctl_inq(struct mfi_softc *, struct bioc_inq *); 165 static int mfi_ioctl_vol(struct mfi_softc *, struct bioc_vol *); 166 static int mfi_ioctl_disk(struct mfi_softc *, struct bioc_disk *); 167 static int mfi_ioctl_alarm(struct mfi_softc *, 168 struct bioc_alarm *); 169 static int mfi_ioctl_blink(struct mfi_softc *sc, 170 struct bioc_blink *); 171 static int mfi_ioctl_setstate(struct mfi_softc *, 172 struct bioc_setstate *); 173 static int mfi_bio_hs(struct mfi_softc *, int, int, void *); 174 static int mfi_create_sensors(struct mfi_softc *); 175 static int mfi_destroy_sensors(struct mfi_softc *); 176 static void mfi_sensor_refresh(struct sysmon_envsys *, 177 envsys_data_t *); 178 #endif /* NBIO > 0 */ 179 static bool mfi_shutdown(device_t, int); 180 static bool mfi_suspend(device_t, const pmf_qual_t *); 181 static bool mfi_resume(device_t, const pmf_qual_t *); 182 183 static dev_type_open(mfifopen); 184 static dev_type_close(mfifclose); 185 static dev_type_ioctl(mfifioctl); 186 const struct cdevsw mfi_cdevsw = { 187 .d_open = mfifopen, 188 .d_close = mfifclose, 189 .d_read = noread, 190 .d_write = nowrite, 191 .d_ioctl = mfifioctl, 192 .d_stop = nostop, 193 .d_tty = notty, 194 .d_poll = nopoll, 195 .d_mmap = nommap, 196 .d_kqfilter = nokqfilter, 197 .d_discard = nodiscard, 198 .d_flag = D_OTHER 199 }; 200 201 extern struct cfdriver mfi_cd; 202 203 static uint32_t mfi_xscale_fw_state(struct mfi_softc *sc); 204 static void mfi_xscale_intr_ena(struct mfi_softc *sc); 205 static void mfi_xscale_intr_dis(struct mfi_softc *sc); 206 static int mfi_xscale_intr(struct mfi_softc *sc); 207 static void mfi_xscale_post(struct mfi_softc *sc, struct mfi_ccb *ccb); 208 209 static const struct mfi_iop_ops mfi_iop_xscale = { 210 mfi_xscale_fw_state, 211 mfi_xscale_intr_dis, 212 mfi_xscale_intr_ena, 213 mfi_xscale_intr, 214 mfi_xscale_post, 215 mfi_scsi_ld_io, 216 }; 217 218 static uint32_t mfi_ppc_fw_state(struct mfi_softc *sc); 219 static void mfi_ppc_intr_ena(struct mfi_softc *sc); 220 static void mfi_ppc_intr_dis(struct mfi_softc *sc); 221 static int mfi_ppc_intr(struct mfi_softc *sc); 222 static void mfi_ppc_post(struct mfi_softc *sc, struct mfi_ccb *ccb); 223 224 static const struct mfi_iop_ops mfi_iop_ppc = { 225 mfi_ppc_fw_state, 226 mfi_ppc_intr_dis, 227 mfi_ppc_intr_ena, 228 mfi_ppc_intr, 229 mfi_ppc_post, 230 mfi_scsi_ld_io, 231 }; 232 233 uint32_t mfi_gen2_fw_state(struct mfi_softc *sc); 234 void mfi_gen2_intr_ena(struct mfi_softc *sc); 235 void mfi_gen2_intr_dis(struct mfi_softc *sc); 236 int mfi_gen2_intr(struct mfi_softc *sc); 237 void mfi_gen2_post(struct mfi_softc *sc, struct mfi_ccb *ccb); 238 239 static const struct mfi_iop_ops mfi_iop_gen2 = { 240 mfi_gen2_fw_state, 241 mfi_gen2_intr_dis, 242 mfi_gen2_intr_ena, 243 mfi_gen2_intr, 244 mfi_gen2_post, 245 mfi_scsi_ld_io, 246 }; 247 248 u_int32_t mfi_skinny_fw_state(struct mfi_softc *); 249 void mfi_skinny_intr_dis(struct mfi_softc *); 250 void mfi_skinny_intr_ena(struct mfi_softc *); 251 int mfi_skinny_intr(struct mfi_softc *); 252 void mfi_skinny_post(struct mfi_softc *, struct mfi_ccb *); 253 254 static const struct mfi_iop_ops mfi_iop_skinny = { 255 mfi_skinny_fw_state, 256 mfi_skinny_intr_dis, 257 mfi_skinny_intr_ena, 258 mfi_skinny_intr, 259 mfi_skinny_post, 260 mfi_scsi_ld_io, 261 }; 262 263 static int mfi_tbolt_init_desc_pool(struct mfi_softc *); 264 static int mfi_tbolt_init_MFI_queue(struct mfi_softc *); 265 static void mfi_tbolt_build_mpt_ccb(struct mfi_ccb *); 266 int mfi_tbolt_scsi_ld_io(struct mfi_ccb *, struct scsipi_xfer *, 267 uint64_t, uint32_t); 268 static void mfi_tbolt_scsi_ld_done(struct mfi_ccb *); 269 static int mfi_tbolt_create_sgl(struct mfi_ccb *, int); 270 void mfi_tbolt_sync_map_info(struct work *, void *); 271 static void mfi_sync_map_complete(struct mfi_ccb *); 272 273 u_int32_t mfi_tbolt_fw_state(struct mfi_softc *); 274 void mfi_tbolt_intr_dis(struct mfi_softc *); 275 void mfi_tbolt_intr_ena(struct mfi_softc *); 276 int mfi_tbolt_intr(struct mfi_softc *sc); 277 void mfi_tbolt_post(struct mfi_softc *, struct mfi_ccb *); 278 279 static const struct mfi_iop_ops mfi_iop_tbolt = { 280 mfi_tbolt_fw_state, 281 mfi_tbolt_intr_dis, 282 mfi_tbolt_intr_ena, 283 mfi_tbolt_intr, 284 mfi_tbolt_post, 285 mfi_tbolt_scsi_ld_io, 286 }; 287 288 #define mfi_fw_state(_s) ((_s)->sc_iop->mio_fw_state(_s)) 289 #define mfi_intr_enable(_s) ((_s)->sc_iop->mio_intr_ena(_s)) 290 #define mfi_intr_disable(_s) ((_s)->sc_iop->mio_intr_dis(_s)) 291 #define mfi_my_intr(_s) ((_s)->sc_iop->mio_intr(_s)) 292 #define mfi_post(_s, _c) ((_s)->sc_iop->mio_post((_s), (_c))) 293 294 static struct mfi_ccb * 295 mfi_get_ccb(struct mfi_softc *sc) 296 { 297 struct mfi_ccb *ccb; 298 int s; 299 300 s = splbio(); 301 ccb = TAILQ_FIRST(&sc->sc_ccb_freeq); 302 if (ccb) { 303 TAILQ_REMOVE(&sc->sc_ccb_freeq, ccb, ccb_link); 304 ccb->ccb_state = MFI_CCB_READY; 305 } 306 splx(s); 307 308 DNPRINTF(MFI_D_CCB, "%s: mfi_get_ccb: %p\n", DEVNAME(sc), ccb); 309 if (__predict_false(ccb == NULL && sc->sc_running)) 310 aprint_error_dev(sc->sc_dev, "out of ccb\n"); 311 312 return ccb; 313 } 314 315 static void 316 mfi_put_ccb(struct mfi_ccb *ccb) 317 { 318 struct mfi_softc *sc = ccb->ccb_sc; 319 struct mfi_frame_header *hdr = &ccb->ccb_frame->mfr_header; 320 int s; 321 322 DNPRINTF(MFI_D_CCB, "%s: mfi_put_ccb: %p\n", DEVNAME(sc), ccb); 323 324 hdr->mfh_cmd_status = 0x0; 325 hdr->mfh_flags = 0x0; 326 ccb->ccb_state = MFI_CCB_FREE; 327 ccb->ccb_xs = NULL; 328 ccb->ccb_flags = 0; 329 ccb->ccb_done = NULL; 330 ccb->ccb_direction = 0; 331 ccb->ccb_frame_size = 0; 332 ccb->ccb_extra_frames = 0; 333 ccb->ccb_sgl = NULL; 334 ccb->ccb_data = NULL; 335 ccb->ccb_len = 0; 336 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 337 /* erase tb_request_desc but preserve SMID */ 338 int index = ccb->ccb_tb_request_desc.header.SMID; 339 ccb->ccb_tb_request_desc.words = 0; 340 ccb->ccb_tb_request_desc.header.SMID = index; 341 } 342 s = splbio(); 343 TAILQ_INSERT_TAIL(&sc->sc_ccb_freeq, ccb, ccb_link); 344 splx(s); 345 } 346 347 static int 348 mfi_destroy_ccb(struct mfi_softc *sc) 349 { 350 struct mfi_ccb *ccb; 351 uint32_t i; 352 353 DNPRINTF(MFI_D_CCB, "%s: mfi_destroy_ccb\n", DEVNAME(sc)); 354 355 356 for (i = 0; (ccb = mfi_get_ccb(sc)) != NULL; i++) { 357 /* create a dma map for transfer */ 358 bus_dmamap_destroy(sc->sc_datadmat, ccb->ccb_dmamap); 359 } 360 361 if (i < sc->sc_max_cmds) 362 return EBUSY; 363 364 free(sc->sc_ccb, M_DEVBUF); 365 366 return 0; 367 } 368 369 static int 370 mfi_init_ccb(struct mfi_softc *sc) 371 { 372 struct mfi_ccb *ccb; 373 uint32_t i; 374 int error; 375 bus_addr_t io_req_base_phys; 376 uint8_t *io_req_base; 377 int offset; 378 379 DNPRINTF(MFI_D_CCB, "%s: mfi_init_ccb\n", DEVNAME(sc)); 380 381 sc->sc_ccb = malloc(sizeof(struct mfi_ccb) * sc->sc_max_cmds, 382 M_DEVBUF, M_WAITOK|M_ZERO); 383 io_req_base = (uint8_t *)MFIMEM_KVA(sc->sc_tbolt_reqmsgpool); 384 io_req_base_phys = MFIMEM_DVA(sc->sc_tbolt_reqmsgpool); 385 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 386 /* 387 * The first 256 bytes (SMID 0) is not used. 388 * Don't add to the cmd list. 389 */ 390 io_req_base += MEGASAS_THUNDERBOLT_NEW_MSG_SIZE; 391 io_req_base_phys += MEGASAS_THUNDERBOLT_NEW_MSG_SIZE; 392 } 393 394 for (i = 0; i < sc->sc_max_cmds; i++) { 395 ccb = &sc->sc_ccb[i]; 396 397 ccb->ccb_sc = sc; 398 399 /* select i'th frame */ 400 ccb->ccb_frame = (union mfi_frame *) 401 ((char*)MFIMEM_KVA(sc->sc_frames) + sc->sc_frames_size * i); 402 ccb->ccb_pframe = 403 MFIMEM_DVA(sc->sc_frames) + sc->sc_frames_size * i; 404 ccb->ccb_frame->mfr_header.mfh_context = i; 405 406 /* select i'th sense */ 407 ccb->ccb_sense = (struct mfi_sense *) 408 ((char*)MFIMEM_KVA(sc->sc_sense) + MFI_SENSE_SIZE * i); 409 ccb->ccb_psense = 410 (MFIMEM_DVA(sc->sc_sense) + MFI_SENSE_SIZE * i); 411 412 /* create a dma map for transfer */ 413 error = bus_dmamap_create(sc->sc_datadmat, 414 MAXPHYS, sc->sc_max_sgl, MAXPHYS, 0, 415 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->ccb_dmamap); 416 if (error) { 417 aprint_error_dev(sc->sc_dev, 418 "cannot create ccb dmamap (%d)\n", error); 419 goto destroy; 420 } 421 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 422 offset = MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * i; 423 ccb->ccb_tb_io_request = 424 (struct mfi_mpi2_request_raid_scsi_io *) 425 (io_req_base + offset); 426 ccb->ccb_tb_pio_request = 427 io_req_base_phys + offset; 428 offset = MEGASAS_MAX_SZ_CHAIN_FRAME * i; 429 ccb->ccb_tb_sg_frame = 430 (mpi2_sge_io_union *)(sc->sc_reply_pool_limit + 431 offset); 432 ccb->ccb_tb_psg_frame = sc->sc_sg_frame_busaddr + 433 offset; 434 /* SMID 0 is reserved. Set SMID/index from 1 */ 435 ccb->ccb_tb_request_desc.header.SMID = i + 1; 436 } 437 438 DNPRINTF(MFI_D_CCB, 439 "ccb(%d): %p frame: %#lx (%#lx) sense: %#lx (%#lx) map: %#lx\n", 440 ccb->ccb_frame->mfr_header.mfh_context, ccb, 441 (u_long)ccb->ccb_frame, (u_long)ccb->ccb_pframe, 442 (u_long)ccb->ccb_sense, (u_long)ccb->ccb_psense, 443 (u_long)ccb->ccb_dmamap); 444 445 /* add ccb to queue */ 446 mfi_put_ccb(ccb); 447 } 448 449 return 0; 450 destroy: 451 /* free dma maps and ccb memory */ 452 while (i) { 453 i--; 454 ccb = &sc->sc_ccb[i]; 455 bus_dmamap_destroy(sc->sc_datadmat, ccb->ccb_dmamap); 456 } 457 458 free(sc->sc_ccb, M_DEVBUF); 459 460 return 1; 461 } 462 463 static uint32_t 464 mfi_read(struct mfi_softc *sc, bus_size_t r) 465 { 466 uint32_t rv; 467 468 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 469 BUS_SPACE_BARRIER_READ); 470 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 471 472 DNPRINTF(MFI_D_RW, "%s: mr 0x%lx 0x08%x ", DEVNAME(sc), (u_long)r, rv); 473 return rv; 474 } 475 476 static void 477 mfi_write(struct mfi_softc *sc, bus_size_t r, uint32_t v) 478 { 479 DNPRINTF(MFI_D_RW, "%s: mw 0x%lx 0x%08x", DEVNAME(sc), (u_long)r, v); 480 481 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 482 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 483 BUS_SPACE_BARRIER_WRITE); 484 } 485 486 static struct mfi_mem * 487 mfi_allocmem(struct mfi_softc *sc, size_t size) 488 { 489 struct mfi_mem *mm; 490 int nsegs; 491 492 DNPRINTF(MFI_D_MEM, "%s: mfi_allocmem: %ld\n", DEVNAME(sc), 493 (long)size); 494 495 mm = malloc(sizeof(struct mfi_mem), M_DEVBUF, M_NOWAIT|M_ZERO); 496 if (mm == NULL) 497 return NULL; 498 499 mm->am_size = size; 500 501 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 502 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &mm->am_map) != 0) 503 goto amfree; 504 505 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &mm->am_seg, 1, 506 &nsegs, BUS_DMA_NOWAIT) != 0) 507 goto destroy; 508 509 if (bus_dmamem_map(sc->sc_dmat, &mm->am_seg, nsegs, size, &mm->am_kva, 510 BUS_DMA_NOWAIT) != 0) 511 goto free; 512 513 if (bus_dmamap_load(sc->sc_dmat, mm->am_map, mm->am_kva, size, NULL, 514 BUS_DMA_NOWAIT) != 0) 515 goto unmap; 516 517 DNPRINTF(MFI_D_MEM, " kva: %p dva: %p map: %p\n", 518 mm->am_kva, (void *)mm->am_map->dm_segs[0].ds_addr, mm->am_map); 519 520 memset(mm->am_kva, 0, size); 521 return mm; 522 523 unmap: 524 bus_dmamem_unmap(sc->sc_dmat, mm->am_kva, size); 525 free: 526 bus_dmamem_free(sc->sc_dmat, &mm->am_seg, 1); 527 destroy: 528 bus_dmamap_destroy(sc->sc_dmat, mm->am_map); 529 amfree: 530 free(mm, M_DEVBUF); 531 532 return NULL; 533 } 534 535 static void 536 mfi_freemem(struct mfi_softc *sc, struct mfi_mem **mmp) 537 { 538 struct mfi_mem *mm = *mmp; 539 540 if (mm == NULL) 541 return; 542 543 *mmp = NULL; 544 545 DNPRINTF(MFI_D_MEM, "%s: mfi_freemem: %p\n", DEVNAME(sc), mm); 546 547 bus_dmamap_unload(sc->sc_dmat, mm->am_map); 548 bus_dmamem_unmap(sc->sc_dmat, mm->am_kva, mm->am_size); 549 bus_dmamem_free(sc->sc_dmat, &mm->am_seg, 1); 550 bus_dmamap_destroy(sc->sc_dmat, mm->am_map); 551 free(mm, M_DEVBUF); 552 } 553 554 static int 555 mfi_transition_firmware(struct mfi_softc *sc) 556 { 557 uint32_t fw_state, cur_state; 558 int max_wait, i; 559 560 fw_state = mfi_fw_state(sc) & MFI_STATE_MASK; 561 562 DNPRINTF(MFI_D_CMD, "%s: mfi_transition_firmware: %#x\n", DEVNAME(sc), 563 fw_state); 564 565 while (fw_state != MFI_STATE_READY) { 566 DNPRINTF(MFI_D_MISC, 567 "%s: waiting for firmware to become ready\n", 568 DEVNAME(sc)); 569 cur_state = fw_state; 570 switch (fw_state) { 571 case MFI_STATE_FAULT: 572 aprint_error_dev(sc->sc_dev, "firmware fault\n"); 573 return 1; 574 case MFI_STATE_WAIT_HANDSHAKE: 575 if (sc->sc_ioptype == MFI_IOP_SKINNY || 576 sc->sc_ioptype == MFI_IOP_TBOLT) 577 mfi_write(sc, MFI_SKINNY_IDB, MFI_INIT_CLEAR_HANDSHAKE); 578 else 579 mfi_write(sc, MFI_IDB, MFI_INIT_CLEAR_HANDSHAKE); 580 max_wait = 2; 581 break; 582 case MFI_STATE_OPERATIONAL: 583 if (sc->sc_ioptype == MFI_IOP_SKINNY || 584 sc->sc_ioptype == MFI_IOP_TBOLT) 585 mfi_write(sc, MFI_SKINNY_IDB, MFI_INIT_READY); 586 else 587 mfi_write(sc, MFI_IDB, MFI_INIT_READY); 588 max_wait = 10; 589 break; 590 case MFI_STATE_UNDEFINED: 591 case MFI_STATE_BB_INIT: 592 max_wait = 2; 593 break; 594 case MFI_STATE_FW_INIT: 595 case MFI_STATE_DEVICE_SCAN: 596 case MFI_STATE_FLUSH_CACHE: 597 max_wait = 20; 598 break; 599 case MFI_STATE_BOOT_MESSAGE_PENDING: 600 if (sc->sc_ioptype == MFI_IOP_SKINNY || 601 sc->sc_ioptype == MFI_IOP_TBOLT) { 602 mfi_write(sc, MFI_SKINNY_IDB, MFI_INIT_HOTPLUG); 603 } else { 604 mfi_write(sc, MFI_IDB, MFI_INIT_HOTPLUG); 605 } 606 max_wait = 180; 607 break; 608 default: 609 aprint_error_dev(sc->sc_dev, 610 "unknown firmware state %d\n", fw_state); 611 return 1; 612 } 613 for (i = 0; i < (max_wait * 10); i++) { 614 fw_state = mfi_fw_state(sc) & MFI_STATE_MASK; 615 if (fw_state == cur_state) 616 DELAY(100000); 617 else 618 break; 619 } 620 if (fw_state == cur_state) { 621 aprint_error_dev(sc->sc_dev, 622 "firmware stuck in state %#x\n", fw_state); 623 return 1; 624 } 625 } 626 627 return 0; 628 } 629 630 static int 631 mfi_initialize_firmware(struct mfi_softc *sc) 632 { 633 struct mfi_ccb *ccb; 634 struct mfi_init_frame *init; 635 struct mfi_init_qinfo *qinfo; 636 637 DNPRINTF(MFI_D_MISC, "%s: mfi_initialize_firmware\n", DEVNAME(sc)); 638 639 if ((ccb = mfi_get_ccb(sc)) == NULL) 640 return 1; 641 642 init = &ccb->ccb_frame->mfr_init; 643 qinfo = (struct mfi_init_qinfo *)((uint8_t *)init + MFI_FRAME_SIZE); 644 645 memset(qinfo, 0, sizeof *qinfo); 646 qinfo->miq_rq_entries = sc->sc_max_cmds + 1; 647 qinfo->miq_rq_addr_lo = htole32(MFIMEM_DVA(sc->sc_pcq) + 648 offsetof(struct mfi_prod_cons, mpc_reply_q)); 649 qinfo->miq_pi_addr_lo = htole32(MFIMEM_DVA(sc->sc_pcq) + 650 offsetof(struct mfi_prod_cons, mpc_producer)); 651 qinfo->miq_ci_addr_lo = htole32(MFIMEM_DVA(sc->sc_pcq) + 652 offsetof(struct mfi_prod_cons, mpc_consumer)); 653 654 init->mif_header.mfh_cmd = MFI_CMD_INIT; 655 init->mif_header.mfh_data_len = sizeof *qinfo; 656 init->mif_qinfo_new_addr_lo = htole32(ccb->ccb_pframe + MFI_FRAME_SIZE); 657 658 DNPRINTF(MFI_D_MISC, "%s: entries: %#x rq: %#x pi: %#x ci: %#x\n", 659 DEVNAME(sc), 660 qinfo->miq_rq_entries, qinfo->miq_rq_addr_lo, 661 qinfo->miq_pi_addr_lo, qinfo->miq_ci_addr_lo); 662 663 if (mfi_poll(ccb)) { 664 aprint_error_dev(sc->sc_dev, 665 "mfi_initialize_firmware failed\n"); 666 return 1; 667 } 668 669 mfi_put_ccb(ccb); 670 671 return 0; 672 } 673 674 static int 675 mfi_get_info(struct mfi_softc *sc) 676 { 677 #ifdef MFI_DEBUG 678 int i; 679 #endif 680 DNPRINTF(MFI_D_MISC, "%s: mfi_get_info\n", DEVNAME(sc)); 681 682 if (mfi_mgmt_internal(sc, MR_DCMD_CTRL_GET_INFO, MFI_DATA_IN, 683 sizeof(sc->sc_info), &sc->sc_info, NULL, cold ? true : false)) 684 return 1; 685 686 #ifdef MFI_DEBUG 687 688 for (i = 0; i < sc->sc_info.mci_image_component_count; i++) { 689 printf("%s: active FW %s Version %s date %s time %s\n", 690 DEVNAME(sc), 691 sc->sc_info.mci_image_component[i].mic_name, 692 sc->sc_info.mci_image_component[i].mic_version, 693 sc->sc_info.mci_image_component[i].mic_build_date, 694 sc->sc_info.mci_image_component[i].mic_build_time); 695 } 696 697 for (i = 0; i < sc->sc_info.mci_pending_image_component_count; i++) { 698 printf("%s: pending FW %s Version %s date %s time %s\n", 699 DEVNAME(sc), 700 sc->sc_info.mci_pending_image_component[i].mic_name, 701 sc->sc_info.mci_pending_image_component[i].mic_version, 702 sc->sc_info.mci_pending_image_component[i].mic_build_date, 703 sc->sc_info.mci_pending_image_component[i].mic_build_time); 704 } 705 706 printf("%s: max_arms %d max_spans %d max_arrs %d max_lds %d name %s\n", 707 DEVNAME(sc), 708 sc->sc_info.mci_max_arms, 709 sc->sc_info.mci_max_spans, 710 sc->sc_info.mci_max_arrays, 711 sc->sc_info.mci_max_lds, 712 sc->sc_info.mci_product_name); 713 714 printf("%s: serial %s present %#x fw time %d max_cmds %d max_sg %d\n", 715 DEVNAME(sc), 716 sc->sc_info.mci_serial_number, 717 sc->sc_info.mci_hw_present, 718 sc->sc_info.mci_current_fw_time, 719 sc->sc_info.mci_max_cmds, 720 sc->sc_info.mci_max_sg_elements); 721 722 printf("%s: max_rq %d lds_pres %d lds_deg %d lds_off %d pd_pres %d\n", 723 DEVNAME(sc), 724 sc->sc_info.mci_max_request_size, 725 sc->sc_info.mci_lds_present, 726 sc->sc_info.mci_lds_degraded, 727 sc->sc_info.mci_lds_offline, 728 sc->sc_info.mci_pd_present); 729 730 printf("%s: pd_dsk_prs %d pd_dsk_pred_fail %d pd_dsk_fail %d\n", 731 DEVNAME(sc), 732 sc->sc_info.mci_pd_disks_present, 733 sc->sc_info.mci_pd_disks_pred_failure, 734 sc->sc_info.mci_pd_disks_failed); 735 736 printf("%s: nvram %d mem %d flash %d\n", 737 DEVNAME(sc), 738 sc->sc_info.mci_nvram_size, 739 sc->sc_info.mci_memory_size, 740 sc->sc_info.mci_flash_size); 741 742 printf("%s: ram_cor %d ram_uncor %d clus_all %d clus_act %d\n", 743 DEVNAME(sc), 744 sc->sc_info.mci_ram_correctable_errors, 745 sc->sc_info.mci_ram_uncorrectable_errors, 746 sc->sc_info.mci_cluster_allowed, 747 sc->sc_info.mci_cluster_active); 748 749 printf("%s: max_strps_io %d raid_lvl %#x adapt_ops %#x ld_ops %#x\n", 750 DEVNAME(sc), 751 sc->sc_info.mci_max_strips_per_io, 752 sc->sc_info.mci_raid_levels, 753 sc->sc_info.mci_adapter_ops, 754 sc->sc_info.mci_ld_ops); 755 756 printf("%s: strp_sz_min %d strp_sz_max %d pd_ops %#x pd_mix %#x\n", 757 DEVNAME(sc), 758 sc->sc_info.mci_stripe_sz_ops.min, 759 sc->sc_info.mci_stripe_sz_ops.max, 760 sc->sc_info.mci_pd_ops, 761 sc->sc_info.mci_pd_mix_support); 762 763 printf("%s: ecc_bucket %d pckg_prop %s\n", 764 DEVNAME(sc), 765 sc->sc_info.mci_ecc_bucket_count, 766 sc->sc_info.mci_package_version); 767 768 printf("%s: sq_nm %d prd_fail_poll %d intr_thrtl %d intr_thrtl_to %d\n", 769 DEVNAME(sc), 770 sc->sc_info.mci_properties.mcp_seq_num, 771 sc->sc_info.mci_properties.mcp_pred_fail_poll_interval, 772 sc->sc_info.mci_properties.mcp_intr_throttle_cnt, 773 sc->sc_info.mci_properties.mcp_intr_throttle_timeout); 774 775 printf("%s: rbld_rate %d patr_rd_rate %d bgi_rate %d cc_rate %d\n", 776 DEVNAME(sc), 777 sc->sc_info.mci_properties.mcp_rebuild_rate, 778 sc->sc_info.mci_properties.mcp_patrol_read_rate, 779 sc->sc_info.mci_properties.mcp_bgi_rate, 780 sc->sc_info.mci_properties.mcp_cc_rate); 781 782 printf("%s: rc_rate %d ch_flsh %d spin_cnt %d spin_dly %d clus_en %d\n", 783 DEVNAME(sc), 784 sc->sc_info.mci_properties.mcp_recon_rate, 785 sc->sc_info.mci_properties.mcp_cache_flush_interval, 786 sc->sc_info.mci_properties.mcp_spinup_drv_cnt, 787 sc->sc_info.mci_properties.mcp_spinup_delay, 788 sc->sc_info.mci_properties.mcp_cluster_enable); 789 790 printf("%s: coerc %d alarm %d dis_auto_rbld %d dis_bat_wrn %d ecc %d\n", 791 DEVNAME(sc), 792 sc->sc_info.mci_properties.mcp_coercion_mode, 793 sc->sc_info.mci_properties.mcp_alarm_enable, 794 sc->sc_info.mci_properties.mcp_disable_auto_rebuild, 795 sc->sc_info.mci_properties.mcp_disable_battery_warn, 796 sc->sc_info.mci_properties.mcp_ecc_bucket_size); 797 798 printf("%s: ecc_leak %d rest_hs %d exp_encl_dev %d\n", 799 DEVNAME(sc), 800 sc->sc_info.mci_properties.mcp_ecc_bucket_leak_rate, 801 sc->sc_info.mci_properties.mcp_restore_hotspare_on_insertion, 802 sc->sc_info.mci_properties.mcp_expose_encl_devices); 803 804 printf("%s: vendor %#x device %#x subvendor %#x subdevice %#x\n", 805 DEVNAME(sc), 806 sc->sc_info.mci_pci.mip_vendor, 807 sc->sc_info.mci_pci.mip_device, 808 sc->sc_info.mci_pci.mip_subvendor, 809 sc->sc_info.mci_pci.mip_subdevice); 810 811 printf("%s: type %#x port_count %d port_addr ", 812 DEVNAME(sc), 813 sc->sc_info.mci_host.mih_type, 814 sc->sc_info.mci_host.mih_port_count); 815 816 for (i = 0; i < 8; i++) 817 printf("%.0" PRIx64 " ", sc->sc_info.mci_host.mih_port_addr[i]); 818 printf("\n"); 819 820 printf("%s: type %.x port_count %d port_addr ", 821 DEVNAME(sc), 822 sc->sc_info.mci_device.mid_type, 823 sc->sc_info.mci_device.mid_port_count); 824 825 for (i = 0; i < 8; i++) { 826 printf("%.0" PRIx64 " ", 827 sc->sc_info.mci_device.mid_port_addr[i]); 828 } 829 printf("\n"); 830 #endif /* MFI_DEBUG */ 831 832 return 0; 833 } 834 835 static int 836 mfi_get_bbu(struct mfi_softc *sc, struct mfi_bbu_status *stat) 837 { 838 DNPRINTF(MFI_D_MISC, "%s: mfi_get_bbu\n", DEVNAME(sc)); 839 840 if (mfi_mgmt_internal(sc, MR_DCMD_BBU_GET_STATUS, MFI_DATA_IN, 841 sizeof(*stat), stat, NULL, cold ? true : false)) 842 return MFI_BBU_UNKNOWN; 843 #ifdef MFI_DEBUG 844 printf("bbu type %d, voltage %d, current %d, temperature %d, " 845 "status 0x%x\n", stat->battery_type, stat->voltage, stat->current, 846 stat->temperature, stat->fw_status); 847 printf("details: "); 848 switch(stat->battery_type) { 849 case MFI_BBU_TYPE_IBBU: 850 printf("guage %d relative charge %d charger state %d " 851 "charger ctrl %d\n", stat->detail.ibbu.gas_guage_status, 852 stat->detail.ibbu.relative_charge , 853 stat->detail.ibbu.charger_system_state , 854 stat->detail.ibbu.charger_system_ctrl); 855 printf("\tcurrent %d abs charge %d max error %d\n", 856 stat->detail.ibbu.charging_current , 857 stat->detail.ibbu.absolute_charge , 858 stat->detail.ibbu.max_error); 859 break; 860 case MFI_BBU_TYPE_BBU: 861 printf("guage %d relative charge %d charger state %d\n", 862 stat->detail.ibbu.gas_guage_status, 863 stat->detail.bbu.relative_charge , 864 stat->detail.bbu.charger_status ); 865 printf("\trem capacity %d fyll capacity %d SOH %d\n", 866 stat->detail.bbu.remaining_capacity , 867 stat->detail.bbu.full_charge_capacity , 868 stat->detail.bbu.is_SOH_good); 869 default: 870 printf("\n"); 871 } 872 #endif 873 switch(stat->battery_type) { 874 case MFI_BBU_TYPE_BBU: 875 return (stat->detail.bbu.is_SOH_good ? 876 MFI_BBU_GOOD : MFI_BBU_BAD); 877 case MFI_BBU_TYPE_NONE: 878 return MFI_BBU_UNKNOWN; 879 default: 880 if (stat->fw_status & 881 (MFI_BBU_STATE_PACK_MISSING | 882 MFI_BBU_STATE_VOLTAGE_LOW | 883 MFI_BBU_STATE_TEMPERATURE_HIGH | 884 MFI_BBU_STATE_LEARN_CYC_FAIL | 885 MFI_BBU_STATE_LEARN_CYC_TIMEOUT | 886 MFI_BBU_STATE_I2C_ERR_DETECT)) 887 return MFI_BBU_BAD; 888 return MFI_BBU_GOOD; 889 } 890 } 891 892 static void 893 mfiminphys(struct buf *bp) 894 { 895 DNPRINTF(MFI_D_MISC, "mfiminphys: %d\n", bp->b_bcount); 896 897 /* XXX currently using MFI_MAXFER = MAXPHYS */ 898 if (bp->b_bcount > MFI_MAXFER) 899 bp->b_bcount = MFI_MAXFER; 900 minphys(bp); 901 } 902 903 int 904 mfi_rescan(device_t self, const char *ifattr, const int *locators) 905 { 906 struct mfi_softc *sc = device_private(self); 907 908 if (sc->sc_child != NULL) 909 return 0; 910 911 sc->sc_child = config_found_sm_loc(self, ifattr, locators, &sc->sc_chan, 912 scsiprint, NULL); 913 914 return 0; 915 } 916 917 void 918 mfi_childdetached(device_t self, device_t child) 919 { 920 struct mfi_softc *sc = device_private(self); 921 922 KASSERT(self == sc->sc_dev); 923 KASSERT(child == sc->sc_child); 924 925 if (child == sc->sc_child) 926 sc->sc_child = NULL; 927 } 928 929 int 930 mfi_detach(struct mfi_softc *sc, int flags) 931 { 932 int error; 933 934 DNPRINTF(MFI_D_MISC, "%s: mfi_detach\n", DEVNAME(sc)); 935 936 if ((error = config_detach_children(sc->sc_dev, flags)) != 0) 937 return error; 938 939 #if NBIO > 0 940 mfi_destroy_sensors(sc); 941 bio_unregister(sc->sc_dev); 942 #endif /* NBIO > 0 */ 943 944 mfi_intr_disable(sc); 945 mfi_shutdown(sc->sc_dev, 0); 946 947 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 948 workqueue_destroy(sc->sc_ldsync_wq); 949 mfi_put_ccb(sc->sc_ldsync_ccb); 950 mfi_freemem(sc, &sc->sc_tbolt_reqmsgpool); 951 mfi_freemem(sc, &sc->sc_tbolt_ioc_init); 952 mfi_freemem(sc, &sc->sc_tbolt_verbuf); 953 } 954 955 if ((error = mfi_destroy_ccb(sc)) != 0) 956 return error; 957 958 mfi_freemem(sc, &sc->sc_sense); 959 960 mfi_freemem(sc, &sc->sc_frames); 961 962 mfi_freemem(sc, &sc->sc_pcq); 963 964 return 0; 965 } 966 967 static bool 968 mfi_shutdown(device_t dev, int how) 969 { 970 struct mfi_softc *sc = device_private(dev); 971 uint8_t mbox[MFI_MBOX_SIZE]; 972 int s = splbio(); 973 DNPRINTF(MFI_D_MISC, "%s: mfi_shutdown\n", DEVNAME(sc)); 974 if (sc->sc_running) { 975 mbox[0] = MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE; 976 if (mfi_mgmt_internal(sc, MR_DCMD_CTRL_CACHE_FLUSH, 977 MFI_DATA_NONE, 0, NULL, mbox, true)) { 978 aprint_error_dev(dev, "shutdown: cache flush failed\n"); 979 goto fail; 980 } 981 982 mbox[0] = 0; 983 if (mfi_mgmt_internal(sc, MR_DCMD_CTRL_SHUTDOWN, 984 MFI_DATA_NONE, 0, NULL, mbox, true)) { 985 aprint_error_dev(dev, "shutdown: " 986 "firmware shutdown failed\n"); 987 goto fail; 988 } 989 sc->sc_running = false; 990 } 991 splx(s); 992 return true; 993 fail: 994 splx(s); 995 return false; 996 } 997 998 static bool 999 mfi_suspend(device_t dev, const pmf_qual_t *q) 1000 { 1001 /* XXX to be implemented */ 1002 return false; 1003 } 1004 1005 static bool 1006 mfi_resume(device_t dev, const pmf_qual_t *q) 1007 { 1008 /* XXX to be implemented */ 1009 return false; 1010 } 1011 1012 int 1013 mfi_attach(struct mfi_softc *sc, enum mfi_iop iop) 1014 { 1015 struct scsipi_adapter *adapt = &sc->sc_adapt; 1016 struct scsipi_channel *chan = &sc->sc_chan; 1017 uint32_t status, frames, max_sgl; 1018 int i; 1019 1020 DNPRINTF(MFI_D_MISC, "%s: mfi_attach\n", DEVNAME(sc)); 1021 1022 sc->sc_ioptype = iop; 1023 1024 switch (iop) { 1025 case MFI_IOP_XSCALE: 1026 sc->sc_iop = &mfi_iop_xscale; 1027 break; 1028 case MFI_IOP_PPC: 1029 sc->sc_iop = &mfi_iop_ppc; 1030 break; 1031 case MFI_IOP_GEN2: 1032 sc->sc_iop = &mfi_iop_gen2; 1033 break; 1034 case MFI_IOP_SKINNY: 1035 sc->sc_iop = &mfi_iop_skinny; 1036 break; 1037 case MFI_IOP_TBOLT: 1038 sc->sc_iop = &mfi_iop_tbolt; 1039 break; 1040 default: 1041 panic("%s: unknown iop %d", DEVNAME(sc), iop); 1042 } 1043 1044 if (mfi_transition_firmware(sc)) 1045 return 1; 1046 1047 TAILQ_INIT(&sc->sc_ccb_freeq); 1048 1049 status = mfi_fw_state(sc); 1050 sc->sc_max_cmds = status & MFI_STATE_MAXCMD_MASK; 1051 max_sgl = (status & MFI_STATE_MAXSGL_MASK) >> 16; 1052 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 1053 sc->sc_max_sgl = min(max_sgl, (128 * 1024) / PAGE_SIZE + 1); 1054 sc->sc_sgl_size = sizeof(struct mfi_sg_ieee); 1055 } else if (sc->sc_64bit_dma) { 1056 sc->sc_max_sgl = min(max_sgl, (128 * 1024) / PAGE_SIZE + 1); 1057 sc->sc_sgl_size = sizeof(struct mfi_sg64); 1058 } else { 1059 sc->sc_max_sgl = max_sgl; 1060 sc->sc_sgl_size = sizeof(struct mfi_sg32); 1061 } 1062 DNPRINTF(MFI_D_MISC, "%s: max commands: %u, max sgl: %u\n", 1063 DEVNAME(sc), sc->sc_max_cmds, sc->sc_max_sgl); 1064 1065 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 1066 uint32_t tb_mem_size; 1067 /* for Alignment */ 1068 tb_mem_size = MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT; 1069 1070 tb_mem_size += 1071 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1); 1072 sc->sc_reply_pool_size = 1073 ((sc->sc_max_cmds + 1 + 15) / 16) * 16; 1074 tb_mem_size += 1075 MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size; 1076 1077 /* this is for SGL's */ 1078 tb_mem_size += MEGASAS_MAX_SZ_CHAIN_FRAME * sc->sc_max_cmds; 1079 sc->sc_tbolt_reqmsgpool = mfi_allocmem(sc, tb_mem_size); 1080 if (sc->sc_tbolt_reqmsgpool == NULL) { 1081 aprint_error_dev(sc->sc_dev, 1082 "unable to allocate thunderbolt " 1083 "request message pool\n"); 1084 goto nopcq; 1085 } 1086 if (mfi_tbolt_init_desc_pool(sc)) { 1087 aprint_error_dev(sc->sc_dev, 1088 "Thunderbolt pool preparation error\n"); 1089 goto nopcq; 1090 } 1091 1092 /* 1093 * Allocate DMA memory mapping for MPI2 IOC Init descriptor, 1094 * we are taking it diffrent from what we have allocated for 1095 * Request and reply descriptors to avoid confusion later 1096 */ 1097 sc->sc_tbolt_ioc_init = mfi_allocmem(sc, 1098 sizeof(struct mpi2_ioc_init_request)); 1099 if (sc->sc_tbolt_ioc_init == NULL) { 1100 aprint_error_dev(sc->sc_dev, 1101 "unable to allocate thunderbolt IOC init memory"); 1102 goto nopcq; 1103 } 1104 1105 sc->sc_tbolt_verbuf = mfi_allocmem(sc, 1106 MEGASAS_MAX_NAME*sizeof(bus_addr_t)); 1107 if (sc->sc_tbolt_verbuf == NULL) { 1108 aprint_error_dev(sc->sc_dev, 1109 "unable to allocate thunderbolt version buffer\n"); 1110 goto nopcq; 1111 } 1112 1113 } 1114 /* consumer/producer and reply queue memory */ 1115 sc->sc_pcq = mfi_allocmem(sc, (sizeof(uint32_t) * sc->sc_max_cmds) + 1116 sizeof(struct mfi_prod_cons)); 1117 if (sc->sc_pcq == NULL) { 1118 aprint_error_dev(sc->sc_dev, 1119 "unable to allocate reply queue memory\n"); 1120 goto nopcq; 1121 } 1122 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_pcq), 0, 1123 sizeof(uint32_t) * sc->sc_max_cmds + sizeof(struct mfi_prod_cons), 1124 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1125 1126 /* frame memory */ 1127 frames = (sc->sc_sgl_size * sc->sc_max_sgl + MFI_FRAME_SIZE - 1) / 1128 MFI_FRAME_SIZE + 1; 1129 sc->sc_frames_size = frames * MFI_FRAME_SIZE; 1130 sc->sc_frames = mfi_allocmem(sc, sc->sc_frames_size * sc->sc_max_cmds); 1131 if (sc->sc_frames == NULL) { 1132 aprint_error_dev(sc->sc_dev, 1133 "unable to allocate frame memory\n"); 1134 goto noframe; 1135 } 1136 /* XXX hack, fix this */ 1137 if (MFIMEM_DVA(sc->sc_frames) & 0x3f) { 1138 aprint_error_dev(sc->sc_dev, 1139 "improper frame alignment (%#llx) FIXME\n", 1140 (long long int)MFIMEM_DVA(sc->sc_frames)); 1141 goto noframe; 1142 } 1143 1144 /* sense memory */ 1145 sc->sc_sense = mfi_allocmem(sc, sc->sc_max_cmds * MFI_SENSE_SIZE); 1146 if (sc->sc_sense == NULL) { 1147 aprint_error_dev(sc->sc_dev, 1148 "unable to allocate sense memory\n"); 1149 goto nosense; 1150 } 1151 1152 /* now that we have all memory bits go initialize ccbs */ 1153 if (mfi_init_ccb(sc)) { 1154 aprint_error_dev(sc->sc_dev, "could not init ccb list\n"); 1155 goto noinit; 1156 } 1157 1158 /* kickstart firmware with all addresses and pointers */ 1159 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 1160 if (mfi_tbolt_init_MFI_queue(sc)) { 1161 aprint_error_dev(sc->sc_dev, 1162 "could not initialize firmware\n"); 1163 goto noinit; 1164 } 1165 } else { 1166 if (mfi_initialize_firmware(sc)) { 1167 aprint_error_dev(sc->sc_dev, 1168 "could not initialize firmware\n"); 1169 goto noinit; 1170 } 1171 } 1172 sc->sc_running = true; 1173 1174 if (mfi_get_info(sc)) { 1175 aprint_error_dev(sc->sc_dev, 1176 "could not retrieve controller information\n"); 1177 goto noinit; 1178 } 1179 aprint_normal_dev(sc->sc_dev, 1180 "%s version %s\n", 1181 sc->sc_info.mci_product_name, 1182 sc->sc_info.mci_package_version); 1183 1184 1185 aprint_normal_dev(sc->sc_dev, "logical drives %d, %dMB RAM, ", 1186 sc->sc_info.mci_lds_present, 1187 sc->sc_info.mci_memory_size); 1188 sc->sc_bbuok = false; 1189 if (sc->sc_info.mci_hw_present & MFI_INFO_HW_BBU) { 1190 struct mfi_bbu_status bbu_stat; 1191 int mfi_bbu_status = mfi_get_bbu(sc, &bbu_stat); 1192 aprint_normal("BBU type "); 1193 switch (bbu_stat.battery_type) { 1194 case MFI_BBU_TYPE_BBU: 1195 aprint_normal("BBU"); 1196 break; 1197 case MFI_BBU_TYPE_IBBU: 1198 aprint_normal("IBBU"); 1199 break; 1200 default: 1201 aprint_normal("unknown type %d", bbu_stat.battery_type); 1202 } 1203 aprint_normal(", status "); 1204 switch(mfi_bbu_status) { 1205 case MFI_BBU_GOOD: 1206 aprint_normal("good\n"); 1207 sc->sc_bbuok = true; 1208 break; 1209 case MFI_BBU_BAD: 1210 aprint_normal("bad\n"); 1211 break; 1212 case MFI_BBU_UNKNOWN: 1213 aprint_normal("unknown\n"); 1214 break; 1215 default: 1216 panic("mfi_bbu_status"); 1217 } 1218 } else { 1219 aprint_normal("BBU not present\n"); 1220 } 1221 1222 sc->sc_ld_cnt = sc->sc_info.mci_lds_present; 1223 sc->sc_max_ld = sc->sc_ld_cnt; 1224 for (i = 0; i < sc->sc_ld_cnt; i++) 1225 sc->sc_ld[i].ld_present = 1; 1226 1227 memset(adapt, 0, sizeof(*adapt)); 1228 adapt->adapt_dev = sc->sc_dev; 1229 adapt->adapt_nchannels = 1; 1230 /* keep a few commands for management */ 1231 if (sc->sc_max_cmds > 4) 1232 adapt->adapt_openings = sc->sc_max_cmds - 4; 1233 else 1234 adapt->adapt_openings = sc->sc_max_cmds; 1235 adapt->adapt_max_periph = adapt->adapt_openings; 1236 adapt->adapt_request = mfi_scsipi_request; 1237 adapt->adapt_minphys = mfiminphys; 1238 1239 memset(chan, 0, sizeof(*chan)); 1240 chan->chan_adapter = adapt; 1241 chan->chan_bustype = &scsi_sas_bustype; 1242 chan->chan_channel = 0; 1243 chan->chan_flags = 0; 1244 chan->chan_nluns = 8; 1245 chan->chan_ntargets = MFI_MAX_LD; 1246 chan->chan_id = MFI_MAX_LD; 1247 1248 mfi_rescan(sc->sc_dev, "scsi", NULL); 1249 1250 /* enable interrupts */ 1251 mfi_intr_enable(sc); 1252 1253 #if NBIO > 0 1254 if (bio_register(sc->sc_dev, mfi_ioctl) != 0) 1255 panic("%s: controller registration failed", DEVNAME(sc)); 1256 if (mfi_create_sensors(sc) != 0) 1257 aprint_error_dev(sc->sc_dev, "unable to create sensors\n"); 1258 #endif /* NBIO > 0 */ 1259 if (!pmf_device_register1(sc->sc_dev, mfi_suspend, mfi_resume, 1260 mfi_shutdown)) { 1261 aprint_error_dev(sc->sc_dev, 1262 "couldn't establish power handler\n"); 1263 } 1264 1265 return 0; 1266 noinit: 1267 mfi_freemem(sc, &sc->sc_sense); 1268 nosense: 1269 mfi_freemem(sc, &sc->sc_frames); 1270 noframe: 1271 mfi_freemem(sc, &sc->sc_pcq); 1272 nopcq: 1273 if (sc->sc_ioptype == MFI_IOP_TBOLT) { 1274 if (sc->sc_tbolt_reqmsgpool) 1275 mfi_freemem(sc, &sc->sc_tbolt_reqmsgpool); 1276 if (sc->sc_tbolt_verbuf) 1277 mfi_freemem(sc, &sc->sc_tbolt_verbuf); 1278 } 1279 return 1; 1280 } 1281 1282 static int 1283 mfi_poll(struct mfi_ccb *ccb) 1284 { 1285 struct mfi_softc *sc = ccb->ccb_sc; 1286 struct mfi_frame_header *hdr; 1287 int to = 0; 1288 int rv = 0; 1289 1290 DNPRINTF(MFI_D_CMD, "%s: mfi_poll\n", DEVNAME(sc)); 1291 1292 hdr = &ccb->ccb_frame->mfr_header; 1293 hdr->mfh_cmd_status = 0xff; 1294 if (!sc->sc_MFA_enabled) 1295 hdr->mfh_flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 1296 1297 /* no callback, caller is supposed to do the cleanup */ 1298 ccb->ccb_done = NULL; 1299 1300 mfi_post(sc, ccb); 1301 if (sc->sc_MFA_enabled) { 1302 /* 1303 * depending on the command type, result may be posted 1304 * to *hdr, or not. In addition it seems there's 1305 * no way to avoid posting the SMID to the reply queue. 1306 * So pool using the interrupt routine. 1307 */ 1308 while (ccb->ccb_state != MFI_CCB_DONE) { 1309 delay(1000); 1310 if (to++ > 5000) { /* XXX 5 seconds busywait sucks */ 1311 rv = 1; 1312 break; 1313 } 1314 mfi_tbolt_intrh(sc); 1315 } 1316 } else { 1317 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1318 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1319 sc->sc_frames_size, BUS_DMASYNC_POSTREAD); 1320 1321 while (hdr->mfh_cmd_status == 0xff) { 1322 delay(1000); 1323 if (to++ > 5000) { /* XXX 5 seconds busywait sucks */ 1324 rv = 1; 1325 break; 1326 } 1327 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1328 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1329 sc->sc_frames_size, BUS_DMASYNC_POSTREAD); 1330 } 1331 } 1332 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1333 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1334 sc->sc_frames_size, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1335 1336 if (ccb->ccb_data != NULL) { 1337 DNPRINTF(MFI_D_INTR, "%s: mfi_mgmt_done sync\n", 1338 DEVNAME(sc)); 1339 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1340 ccb->ccb_dmamap->dm_mapsize, 1341 (ccb->ccb_direction & MFI_DATA_IN) ? 1342 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1343 1344 bus_dmamap_unload(sc->sc_datadmat, ccb->ccb_dmamap); 1345 } 1346 1347 if (rv != 0) { 1348 aprint_error_dev(sc->sc_dev, "timeout on ccb %d\n", 1349 hdr->mfh_context); 1350 ccb->ccb_flags |= MFI_CCB_F_ERR; 1351 return 1; 1352 } 1353 1354 return 0; 1355 } 1356 1357 int 1358 mfi_intr(void *arg) 1359 { 1360 struct mfi_softc *sc = arg; 1361 struct mfi_prod_cons *pcq; 1362 struct mfi_ccb *ccb; 1363 uint32_t producer, consumer, ctx; 1364 int claimed = 0; 1365 1366 if (!mfi_my_intr(sc)) 1367 return 0; 1368 1369 pcq = MFIMEM_KVA(sc->sc_pcq); 1370 1371 DNPRINTF(MFI_D_INTR, "%s: mfi_intr %#lx %#lx\n", DEVNAME(sc), 1372 (u_long)sc, (u_long)pcq); 1373 1374 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_pcq), 0, 1375 sizeof(uint32_t) * sc->sc_max_cmds + sizeof(struct mfi_prod_cons), 1376 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1377 1378 producer = pcq->mpc_producer; 1379 consumer = pcq->mpc_consumer; 1380 1381 while (consumer != producer) { 1382 DNPRINTF(MFI_D_INTR, "%s: mfi_intr pi %#x ci %#x\n", 1383 DEVNAME(sc), producer, consumer); 1384 1385 ctx = pcq->mpc_reply_q[consumer]; 1386 pcq->mpc_reply_q[consumer] = MFI_INVALID_CTX; 1387 if (ctx == MFI_INVALID_CTX) 1388 aprint_error_dev(sc->sc_dev, 1389 "invalid context, p: %d c: %d\n", 1390 producer, consumer); 1391 else { 1392 /* XXX remove from queue and call scsi_done */ 1393 ccb = &sc->sc_ccb[ctx]; 1394 DNPRINTF(MFI_D_INTR, "%s: mfi_intr context %#x\n", 1395 DEVNAME(sc), ctx); 1396 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 1397 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 1398 sc->sc_frames_size, 1399 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1400 ccb->ccb_done(ccb); 1401 1402 claimed = 1; 1403 } 1404 consumer++; 1405 if (consumer == (sc->sc_max_cmds + 1)) 1406 consumer = 0; 1407 } 1408 1409 pcq->mpc_consumer = consumer; 1410 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_pcq), 0, 1411 sizeof(uint32_t) * sc->sc_max_cmds + sizeof(struct mfi_prod_cons), 1412 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1413 1414 return claimed; 1415 } 1416 1417 static int 1418 mfi_scsi_ld_io(struct mfi_ccb *ccb, struct scsipi_xfer *xs, uint64_t blockno, 1419 uint32_t blockcnt) 1420 { 1421 struct scsipi_periph *periph = xs->xs_periph; 1422 struct mfi_io_frame *io; 1423 1424 DNPRINTF(MFI_D_CMD, "%s: mfi_scsi_ld_io: %d\n", 1425 device_xname(periph->periph_channel->chan_adapter->adapt_dev), 1426 periph->periph_target); 1427 1428 if (!xs->data) 1429 return 1; 1430 1431 io = &ccb->ccb_frame->mfr_io; 1432 if (xs->xs_control & XS_CTL_DATA_IN) { 1433 io->mif_header.mfh_cmd = MFI_CMD_LD_READ; 1434 ccb->ccb_direction = MFI_DATA_IN; 1435 } else { 1436 io->mif_header.mfh_cmd = MFI_CMD_LD_WRITE; 1437 ccb->ccb_direction = MFI_DATA_OUT; 1438 } 1439 io->mif_header.mfh_target_id = periph->periph_target; 1440 io->mif_header.mfh_timeout = 0; 1441 io->mif_header.mfh_flags = 0; 1442 io->mif_header.mfh_sense_len = MFI_SENSE_SIZE; 1443 io->mif_header.mfh_data_len= blockcnt; 1444 io->mif_lba_hi = (blockno >> 32); 1445 io->mif_lba_lo = (blockno & 0xffffffff); 1446 io->mif_sense_addr_lo = htole32(ccb->ccb_psense); 1447 io->mif_sense_addr_hi = 0; 1448 1449 ccb->ccb_done = mfi_scsi_ld_done; 1450 ccb->ccb_xs = xs; 1451 ccb->ccb_frame_size = MFI_IO_FRAME_SIZE; 1452 ccb->ccb_sgl = &io->mif_sgl; 1453 ccb->ccb_data = xs->data; 1454 ccb->ccb_len = xs->datalen; 1455 1456 if (mfi_create_sgl(ccb, (xs->xs_control & XS_CTL_NOSLEEP) ? 1457 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)) 1458 return 1; 1459 1460 return 0; 1461 } 1462 1463 static void 1464 mfi_scsi_ld_done(struct mfi_ccb *ccb) 1465 { 1466 struct mfi_frame_header *hdr = &ccb->ccb_frame->mfr_header; 1467 mfi_scsi_xs_done(ccb, hdr->mfh_cmd_status, hdr->mfh_scsi_status); 1468 } 1469 1470 static void 1471 mfi_scsi_xs_done(struct mfi_ccb *ccb, int status, int scsi_status) 1472 { 1473 struct scsipi_xfer *xs = ccb->ccb_xs; 1474 struct mfi_softc *sc = ccb->ccb_sc; 1475 1476 DNPRINTF(MFI_D_INTR, "%s: mfi_scsi_xs_done %#lx %#lx\n", 1477 DEVNAME(sc), (u_long)ccb, (u_long)ccb->ccb_frame); 1478 1479 if (xs->data != NULL) { 1480 DNPRINTF(MFI_D_INTR, "%s: mfi_scsi_xs_done sync\n", 1481 DEVNAME(sc)); 1482 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1483 ccb->ccb_dmamap->dm_mapsize, 1484 (xs->xs_control & XS_CTL_DATA_IN) ? 1485 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1486 1487 bus_dmamap_unload(sc->sc_datadmat, ccb->ccb_dmamap); 1488 } 1489 1490 if (status != MFI_STAT_OK) { 1491 xs->error = XS_DRIVER_STUFFUP; 1492 DNPRINTF(MFI_D_INTR, "%s: mfi_scsi_xs_done stuffup %#x\n", 1493 DEVNAME(sc), status); 1494 1495 if (scsi_status != 0) { 1496 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_sense), 1497 ccb->ccb_psense - MFIMEM_DVA(sc->sc_sense), 1498 MFI_SENSE_SIZE, BUS_DMASYNC_POSTREAD); 1499 DNPRINTF(MFI_D_INTR, 1500 "%s: mfi_scsi_xs_done sense %#x %lx %lx\n", 1501 DEVNAME(sc), scsi_status, 1502 (u_long)&xs->sense, (u_long)ccb->ccb_sense); 1503 memset(&xs->sense, 0, sizeof(xs->sense)); 1504 memcpy(&xs->sense, ccb->ccb_sense, 1505 sizeof(struct scsi_sense_data)); 1506 xs->error = XS_SENSE; 1507 } 1508 } else { 1509 xs->error = XS_NOERROR; 1510 xs->status = SCSI_OK; 1511 xs->resid = 0; 1512 } 1513 1514 mfi_put_ccb(ccb); 1515 scsipi_done(xs); 1516 } 1517 1518 static int 1519 mfi_scsi_ld(struct mfi_ccb *ccb, struct scsipi_xfer *xs) 1520 { 1521 struct mfi_pass_frame *pf; 1522 struct scsipi_periph *periph = xs->xs_periph; 1523 1524 DNPRINTF(MFI_D_CMD, "%s: mfi_scsi_ld: %d\n", 1525 device_xname(periph->periph_channel->chan_adapter->adapt_dev), 1526 periph->periph_target); 1527 1528 pf = &ccb->ccb_frame->mfr_pass; 1529 pf->mpf_header.mfh_cmd = MFI_CMD_LD_SCSI_IO; 1530 pf->mpf_header.mfh_target_id = periph->periph_target; 1531 pf->mpf_header.mfh_lun_id = 0; 1532 pf->mpf_header.mfh_cdb_len = xs->cmdlen; 1533 pf->mpf_header.mfh_timeout = 0; 1534 pf->mpf_header.mfh_data_len= xs->datalen; /* XXX */ 1535 pf->mpf_header.mfh_sense_len = MFI_SENSE_SIZE; 1536 1537 pf->mpf_sense_addr_hi = 0; 1538 pf->mpf_sense_addr_lo = htole32(ccb->ccb_psense); 1539 1540 memset(pf->mpf_cdb, 0, 16); 1541 memcpy(pf->mpf_cdb, &xs->cmdstore, xs->cmdlen); 1542 1543 ccb->ccb_done = mfi_scsi_ld_done; 1544 ccb->ccb_xs = xs; 1545 ccb->ccb_frame_size = MFI_PASS_FRAME_SIZE; 1546 ccb->ccb_sgl = &pf->mpf_sgl; 1547 1548 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) 1549 ccb->ccb_direction = (xs->xs_control & XS_CTL_DATA_IN) ? 1550 MFI_DATA_IN : MFI_DATA_OUT; 1551 else 1552 ccb->ccb_direction = MFI_DATA_NONE; 1553 1554 if (xs->data) { 1555 ccb->ccb_data = xs->data; 1556 ccb->ccb_len = xs->datalen; 1557 1558 if (mfi_create_sgl(ccb, (xs->xs_control & XS_CTL_NOSLEEP) ? 1559 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)) 1560 return 1; 1561 } 1562 1563 return 0; 1564 } 1565 1566 static void 1567 mfi_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1568 void *arg) 1569 { 1570 struct scsipi_periph *periph; 1571 struct scsipi_xfer *xs; 1572 struct scsipi_adapter *adapt = chan->chan_adapter; 1573 struct mfi_softc *sc = device_private(adapt->adapt_dev); 1574 struct mfi_ccb *ccb; 1575 struct scsi_rw_6 *rw; 1576 struct scsipi_rw_10 *rwb; 1577 struct scsipi_rw_12 *rw12; 1578 struct scsipi_rw_16 *rw16; 1579 uint64_t blockno; 1580 uint32_t blockcnt; 1581 uint8_t target; 1582 uint8_t mbox[MFI_MBOX_SIZE]; 1583 int s; 1584 1585 switch (req) { 1586 case ADAPTER_REQ_GROW_RESOURCES: 1587 /* Not supported. */ 1588 return; 1589 case ADAPTER_REQ_SET_XFER_MODE: 1590 { 1591 struct scsipi_xfer_mode *xm = arg; 1592 xm->xm_mode = PERIPH_CAP_TQING; 1593 xm->xm_period = 0; 1594 xm->xm_offset = 0; 1595 scsipi_async_event(&sc->sc_chan, ASYNC_EVENT_XFER_MODE, xm); 1596 return; 1597 } 1598 case ADAPTER_REQ_RUN_XFER: 1599 break; 1600 } 1601 1602 xs = arg; 1603 1604 periph = xs->xs_periph; 1605 target = periph->periph_target; 1606 1607 DNPRINTF(MFI_D_CMD, "%s: mfi_scsipi_request req %d opcode: %#x " 1608 "target %d lun %d\n", DEVNAME(sc), req, xs->cmd->opcode, 1609 periph->periph_target, periph->periph_lun); 1610 1611 s = splbio(); 1612 if (target >= MFI_MAX_LD || !sc->sc_ld[target].ld_present || 1613 periph->periph_lun != 0) { 1614 DNPRINTF(MFI_D_CMD, "%s: invalid target %d\n", 1615 DEVNAME(sc), target); 1616 xs->error = XS_SELTIMEOUT; 1617 scsipi_done(xs); 1618 splx(s); 1619 return; 1620 } 1621 if ((xs->cmd->opcode == SCSI_SYNCHRONIZE_CACHE_10 || 1622 xs->cmd->opcode == SCSI_SYNCHRONIZE_CACHE_16) && sc->sc_bbuok) { 1623 /* the cache is stable storage, don't flush */ 1624 xs->error = XS_NOERROR; 1625 xs->status = SCSI_OK; 1626 xs->resid = 0; 1627 scsipi_done(xs); 1628 splx(s); 1629 return; 1630 } 1631 1632 if ((ccb = mfi_get_ccb(sc)) == NULL) { 1633 DNPRINTF(MFI_D_CMD, "%s: mfi_scsipi_request no ccb\n", DEVNAME(sc)); 1634 xs->error = XS_RESOURCE_SHORTAGE; 1635 scsipi_done(xs); 1636 splx(s); 1637 return; 1638 } 1639 1640 switch (xs->cmd->opcode) { 1641 /* IO path */ 1642 case READ_16: 1643 case WRITE_16: 1644 rw16 = (struct scsipi_rw_16 *)xs->cmd; 1645 blockno = _8btol(rw16->addr); 1646 blockcnt = _4btol(rw16->length); 1647 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1648 goto stuffup; 1649 } 1650 break; 1651 1652 case READ_12: 1653 case WRITE_12: 1654 rw12 = (struct scsipi_rw_12 *)xs->cmd; 1655 blockno = _4btol(rw12->addr); 1656 blockcnt = _4btol(rw12->length); 1657 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1658 goto stuffup; 1659 } 1660 break; 1661 1662 case READ_10: 1663 case WRITE_10: 1664 rwb = (struct scsipi_rw_10 *)xs->cmd; 1665 blockno = _4btol(rwb->addr); 1666 blockcnt = _2btol(rwb->length); 1667 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1668 goto stuffup; 1669 } 1670 break; 1671 1672 case SCSI_READ_6_COMMAND: 1673 case SCSI_WRITE_6_COMMAND: 1674 rw = (struct scsi_rw_6 *)xs->cmd; 1675 blockno = _3btol(rw->addr) & (SRW_TOPADDR << 16 | 0xffff); 1676 blockcnt = rw->length ? rw->length : 0x100; 1677 if (sc->sc_iop->mio_ld_io(ccb, xs, blockno, blockcnt)) { 1678 goto stuffup; 1679 } 1680 break; 1681 1682 case SCSI_SYNCHRONIZE_CACHE_10: 1683 case SCSI_SYNCHRONIZE_CACHE_16: 1684 mbox[0] = MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE; 1685 if (mfi_mgmt(ccb, xs, 1686 MR_DCMD_CTRL_CACHE_FLUSH, MFI_DATA_NONE, 0, NULL, mbox)) { 1687 goto stuffup; 1688 } 1689 break; 1690 1691 /* hand it of to the firmware and let it deal with it */ 1692 case SCSI_TEST_UNIT_READY: 1693 /* save off sd? after autoconf */ 1694 if (!cold) /* XXX bogus */ 1695 strlcpy(sc->sc_ld[target].ld_dev, device_xname(sc->sc_dev), 1696 sizeof(sc->sc_ld[target].ld_dev)); 1697 /* FALLTHROUGH */ 1698 1699 default: 1700 if (mfi_scsi_ld(ccb, xs)) { 1701 goto stuffup; 1702 } 1703 break; 1704 } 1705 1706 DNPRINTF(MFI_D_CMD, "%s: start io %d\n", DEVNAME(sc), target); 1707 1708 if (xs->xs_control & XS_CTL_POLL) { 1709 if (mfi_poll(ccb)) { 1710 /* XXX check for sense in ccb->ccb_sense? */ 1711 aprint_error_dev(sc->sc_dev, 1712 "mfi_scsipi_request poll failed\n"); 1713 memset(&xs->sense, 0, sizeof(xs->sense)); 1714 xs->sense.scsi_sense.response_code = 1715 SSD_RCODE_VALID | SSD_RCODE_CURRENT; 1716 xs->sense.scsi_sense.flags = SKEY_ILLEGAL_REQUEST; 1717 xs->sense.scsi_sense.asc = 0x20; /* invalid opcode */ 1718 xs->error = XS_SENSE; 1719 xs->status = SCSI_CHECK; 1720 } else { 1721 DNPRINTF(MFI_D_DMA, 1722 "%s: mfi_scsipi_request poll complete %d\n", 1723 DEVNAME(sc), ccb->ccb_dmamap->dm_nsegs); 1724 xs->error = XS_NOERROR; 1725 xs->status = SCSI_OK; 1726 xs->resid = 0; 1727 } 1728 mfi_put_ccb(ccb); 1729 scsipi_done(xs); 1730 splx(s); 1731 return; 1732 } 1733 1734 mfi_post(sc, ccb); 1735 1736 DNPRINTF(MFI_D_DMA, "%s: mfi_scsipi_request queued %d\n", DEVNAME(sc), 1737 ccb->ccb_dmamap->dm_nsegs); 1738 1739 splx(s); 1740 return; 1741 1742 stuffup: 1743 mfi_put_ccb(ccb); 1744 xs->error = XS_DRIVER_STUFFUP; 1745 scsipi_done(xs); 1746 splx(s); 1747 } 1748 1749 static int 1750 mfi_create_sgl(struct mfi_ccb *ccb, int flags) 1751 { 1752 struct mfi_softc *sc = ccb->ccb_sc; 1753 struct mfi_frame_header *hdr; 1754 bus_dma_segment_t *sgd; 1755 union mfi_sgl *sgl; 1756 int error, i; 1757 1758 DNPRINTF(MFI_D_DMA, "%s: mfi_create_sgl %#lx\n", DEVNAME(sc), 1759 (u_long)ccb->ccb_data); 1760 1761 if (!ccb->ccb_data) 1762 return 1; 1763 1764 KASSERT(flags == BUS_DMA_NOWAIT || !cpu_intr_p()); 1765 error = bus_dmamap_load(sc->sc_datadmat, ccb->ccb_dmamap, 1766 ccb->ccb_data, ccb->ccb_len, NULL, flags); 1767 if (error) { 1768 if (error == EFBIG) { 1769 aprint_error_dev(sc->sc_dev, "more than %d dma segs\n", 1770 sc->sc_max_sgl); 1771 } else { 1772 aprint_error_dev(sc->sc_dev, 1773 "error %d loading dma map\n", error); 1774 } 1775 return 1; 1776 } 1777 1778 hdr = &ccb->ccb_frame->mfr_header; 1779 sgl = ccb->ccb_sgl; 1780 sgd = ccb->ccb_dmamap->dm_segs; 1781 for (i = 0; i < ccb->ccb_dmamap->dm_nsegs; i++) { 1782 if (sc->sc_ioptype == MFI_IOP_TBOLT && 1783 (hdr->mfh_cmd == MFI_CMD_PD_SCSI_IO || 1784 hdr->mfh_cmd == MFI_CMD_LD_READ || 1785 hdr->mfh_cmd == MFI_CMD_LD_WRITE)) { 1786 sgl->sg_ieee[i].addr = htole64(sgd[i].ds_addr); 1787 sgl->sg_ieee[i].len = htole32(sgd[i].ds_len); 1788 sgl->sg_ieee[i].flags = 0; 1789 DNPRINTF(MFI_D_DMA, "%s: addr: %#" PRIx64 " len: %#" 1790 PRIx32 "\n", 1791 DEVNAME(sc), sgl->sg64[i].addr, sgl->sg64[i].len); 1792 hdr->mfh_flags |= MFI_FRAME_IEEE_SGL | MFI_FRAME_SGL64; 1793 } else if (sc->sc_64bit_dma) { 1794 sgl->sg64[i].addr = htole64(sgd[i].ds_addr); 1795 sgl->sg64[i].len = htole32(sgd[i].ds_len); 1796 DNPRINTF(MFI_D_DMA, "%s: addr: %#" PRIx64 " len: %#" 1797 PRIx32 "\n", 1798 DEVNAME(sc), sgl->sg64[i].addr, sgl->sg64[i].len); 1799 hdr->mfh_flags |= MFI_FRAME_SGL64; 1800 } else { 1801 sgl->sg32[i].addr = htole32(sgd[i].ds_addr); 1802 sgl->sg32[i].len = htole32(sgd[i].ds_len); 1803 DNPRINTF(MFI_D_DMA, "%s: addr: %#x len: %#x\n", 1804 DEVNAME(sc), sgl->sg32[i].addr, sgl->sg32[i].len); 1805 hdr->mfh_flags |= MFI_FRAME_SGL32; 1806 } 1807 } 1808 1809 if (ccb->ccb_direction == MFI_DATA_IN) { 1810 hdr->mfh_flags |= MFI_FRAME_DIR_READ; 1811 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1812 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1813 } else { 1814 hdr->mfh_flags |= MFI_FRAME_DIR_WRITE; 1815 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1816 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1817 } 1818 1819 hdr->mfh_sg_count = ccb->ccb_dmamap->dm_nsegs; 1820 ccb->ccb_frame_size += sc->sc_sgl_size * ccb->ccb_dmamap->dm_nsegs; 1821 ccb->ccb_extra_frames = (ccb->ccb_frame_size - 1) / MFI_FRAME_SIZE; 1822 1823 DNPRINTF(MFI_D_DMA, "%s: sg_count: %d frame_size: %d frames_size: %d" 1824 " dm_nsegs: %d extra_frames: %d\n", 1825 DEVNAME(sc), 1826 hdr->mfh_sg_count, 1827 ccb->ccb_frame_size, 1828 sc->sc_frames_size, 1829 ccb->ccb_dmamap->dm_nsegs, 1830 ccb->ccb_extra_frames); 1831 1832 return 0; 1833 } 1834 1835 static int 1836 mfi_mgmt_internal(struct mfi_softc *sc, uint32_t opc, uint32_t dir, 1837 uint32_t len, void *buf, uint8_t *mbox, bool poll) 1838 { 1839 struct mfi_ccb *ccb; 1840 int rv = 1; 1841 1842 if ((ccb = mfi_get_ccb(sc)) == NULL) 1843 return rv; 1844 rv = mfi_mgmt(ccb, NULL, opc, dir, len, buf, mbox); 1845 if (rv) 1846 return rv; 1847 1848 if (poll) { 1849 rv = 1; 1850 if (mfi_poll(ccb)) 1851 goto done; 1852 } else { 1853 mfi_post(sc, ccb); 1854 1855 DNPRINTF(MFI_D_MISC, "%s: mfi_mgmt_internal sleeping\n", 1856 DEVNAME(sc)); 1857 while (ccb->ccb_state != MFI_CCB_DONE) 1858 tsleep(ccb, PRIBIO, "mfi_mgmt", 0); 1859 1860 if (ccb->ccb_flags & MFI_CCB_F_ERR) 1861 goto done; 1862 } 1863 rv = 0; 1864 1865 done: 1866 mfi_put_ccb(ccb); 1867 return rv; 1868 } 1869 1870 static int 1871 mfi_mgmt(struct mfi_ccb *ccb, struct scsipi_xfer *xs, 1872 uint32_t opc, uint32_t dir, uint32_t len, void *buf, uint8_t *mbox) 1873 { 1874 struct mfi_dcmd_frame *dcmd; 1875 1876 DNPRINTF(MFI_D_MISC, "%s: mfi_mgmt %#x\n", DEVNAME(ccb->ccb_sc), opc); 1877 1878 dcmd = &ccb->ccb_frame->mfr_dcmd; 1879 memset(dcmd->mdf_mbox, 0, MFI_MBOX_SIZE); 1880 dcmd->mdf_header.mfh_cmd = MFI_CMD_DCMD; 1881 dcmd->mdf_header.mfh_timeout = 0; 1882 1883 dcmd->mdf_opcode = opc; 1884 dcmd->mdf_header.mfh_data_len = 0; 1885 ccb->ccb_direction = dir; 1886 ccb->ccb_xs = xs; 1887 ccb->ccb_done = mfi_mgmt_done; 1888 1889 ccb->ccb_frame_size = MFI_DCMD_FRAME_SIZE; 1890 1891 /* handle special opcodes */ 1892 if (mbox) 1893 memcpy(dcmd->mdf_mbox, mbox, MFI_MBOX_SIZE); 1894 1895 if (dir != MFI_DATA_NONE) { 1896 dcmd->mdf_header.mfh_data_len = len; 1897 ccb->ccb_data = buf; 1898 ccb->ccb_len = len; 1899 ccb->ccb_sgl = &dcmd->mdf_sgl; 1900 1901 if (mfi_create_sgl(ccb, BUS_DMA_WAITOK)) 1902 return 1; 1903 } 1904 return 0; 1905 } 1906 1907 static void 1908 mfi_mgmt_done(struct mfi_ccb *ccb) 1909 { 1910 struct scsipi_xfer *xs = ccb->ccb_xs; 1911 struct mfi_softc *sc = ccb->ccb_sc; 1912 struct mfi_frame_header *hdr = &ccb->ccb_frame->mfr_header; 1913 1914 DNPRINTF(MFI_D_INTR, "%s: mfi_mgmt_done %#lx %#lx\n", 1915 DEVNAME(sc), (u_long)ccb, (u_long)ccb->ccb_frame); 1916 1917 if (ccb->ccb_data != NULL) { 1918 DNPRINTF(MFI_D_INTR, "%s: mfi_mgmt_done sync\n", 1919 DEVNAME(sc)); 1920 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 1921 ccb->ccb_dmamap->dm_mapsize, 1922 (ccb->ccb_direction & MFI_DATA_IN) ? 1923 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1924 1925 bus_dmamap_unload(sc->sc_datadmat, ccb->ccb_dmamap); 1926 } 1927 1928 if (hdr->mfh_cmd_status != MFI_STAT_OK) 1929 ccb->ccb_flags |= MFI_CCB_F_ERR; 1930 1931 ccb->ccb_state = MFI_CCB_DONE; 1932 if (xs) { 1933 if (hdr->mfh_cmd_status != MFI_STAT_OK) { 1934 xs->error = XS_DRIVER_STUFFUP; 1935 } else { 1936 xs->error = XS_NOERROR; 1937 xs->status = SCSI_OK; 1938 xs->resid = 0; 1939 } 1940 mfi_put_ccb(ccb); 1941 scsipi_done(xs); 1942 } else 1943 wakeup(ccb); 1944 } 1945 1946 #if NBIO > 0 1947 int 1948 mfi_ioctl(device_t dev, u_long cmd, void *addr) 1949 { 1950 struct mfi_softc *sc = device_private(dev); 1951 int error = 0; 1952 int s; 1953 1954 KERNEL_LOCK(1, curlwp); 1955 s = splbio(); 1956 1957 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl ", DEVNAME(sc)); 1958 1959 switch (cmd) { 1960 case BIOCINQ: 1961 DNPRINTF(MFI_D_IOCTL, "inq\n"); 1962 error = mfi_ioctl_inq(sc, (struct bioc_inq *)addr); 1963 break; 1964 1965 case BIOCVOL: 1966 DNPRINTF(MFI_D_IOCTL, "vol\n"); 1967 error = mfi_ioctl_vol(sc, (struct bioc_vol *)addr); 1968 break; 1969 1970 case BIOCDISK: 1971 DNPRINTF(MFI_D_IOCTL, "disk\n"); 1972 error = mfi_ioctl_disk(sc, (struct bioc_disk *)addr); 1973 break; 1974 1975 case BIOCALARM: 1976 DNPRINTF(MFI_D_IOCTL, "alarm\n"); 1977 error = mfi_ioctl_alarm(sc, (struct bioc_alarm *)addr); 1978 break; 1979 1980 case BIOCBLINK: 1981 DNPRINTF(MFI_D_IOCTL, "blink\n"); 1982 error = mfi_ioctl_blink(sc, (struct bioc_blink *)addr); 1983 break; 1984 1985 case BIOCSETSTATE: 1986 DNPRINTF(MFI_D_IOCTL, "setstate\n"); 1987 error = mfi_ioctl_setstate(sc, (struct bioc_setstate *)addr); 1988 break; 1989 1990 default: 1991 DNPRINTF(MFI_D_IOCTL, " invalid ioctl\n"); 1992 error = EINVAL; 1993 } 1994 splx(s); 1995 KERNEL_UNLOCK_ONE(curlwp); 1996 1997 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl return %x\n", DEVNAME(sc), error); 1998 return error; 1999 } 2000 2001 static int 2002 mfi_ioctl_inq(struct mfi_softc *sc, struct bioc_inq *bi) 2003 { 2004 struct mfi_conf *cfg; 2005 int rv = EINVAL; 2006 2007 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_inq\n", DEVNAME(sc)); 2008 2009 if (mfi_get_info(sc)) { 2010 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_inq failed\n", 2011 DEVNAME(sc)); 2012 return EIO; 2013 } 2014 2015 /* get figures */ 2016 cfg = malloc(sizeof *cfg, M_DEVBUF, M_WAITOK); 2017 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 2018 sizeof *cfg, cfg, NULL, false)) 2019 goto freeme; 2020 2021 strlcpy(bi->bi_dev, DEVNAME(sc), sizeof(bi->bi_dev)); 2022 bi->bi_novol = cfg->mfc_no_ld + cfg->mfc_no_hs; 2023 bi->bi_nodisk = sc->sc_info.mci_pd_disks_present; 2024 2025 rv = 0; 2026 freeme: 2027 free(cfg, M_DEVBUF); 2028 return rv; 2029 } 2030 2031 static int 2032 mfi_ioctl_vol(struct mfi_softc *sc, struct bioc_vol *bv) 2033 { 2034 int i, per, rv = EINVAL; 2035 uint8_t mbox[MFI_MBOX_SIZE]; 2036 2037 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_vol %#x\n", 2038 DEVNAME(sc), bv->bv_volid); 2039 2040 if (mfi_mgmt_internal(sc, MR_DCMD_LD_GET_LIST, MFI_DATA_IN, 2041 sizeof(sc->sc_ld_list), &sc->sc_ld_list, NULL, false)) 2042 goto done; 2043 2044 i = bv->bv_volid; 2045 mbox[0] = sc->sc_ld_list.mll_list[i].mll_ld.mld_target; 2046 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_vol target %#x\n", 2047 DEVNAME(sc), mbox[0]); 2048 2049 if (mfi_mgmt_internal(sc, MR_DCMD_LD_GET_INFO, MFI_DATA_IN, 2050 sizeof(sc->sc_ld_details), &sc->sc_ld_details, mbox, false)) 2051 goto done; 2052 2053 if (bv->bv_volid >= sc->sc_ld_list.mll_no_ld) { 2054 /* go do hotspares */ 2055 rv = mfi_bio_hs(sc, bv->bv_volid, MFI_MGMT_VD, bv); 2056 goto done; 2057 } 2058 2059 strlcpy(bv->bv_dev, sc->sc_ld[i].ld_dev, sizeof(bv->bv_dev)); 2060 2061 switch(sc->sc_ld_list.mll_list[i].mll_state) { 2062 case MFI_LD_OFFLINE: 2063 bv->bv_status = BIOC_SVOFFLINE; 2064 break; 2065 2066 case MFI_LD_PART_DEGRADED: 2067 case MFI_LD_DEGRADED: 2068 bv->bv_status = BIOC_SVDEGRADED; 2069 break; 2070 2071 case MFI_LD_ONLINE: 2072 bv->bv_status = BIOC_SVONLINE; 2073 break; 2074 2075 default: 2076 bv->bv_status = BIOC_SVINVALID; 2077 DNPRINTF(MFI_D_IOCTL, "%s: invalid logical disk state %#x\n", 2078 DEVNAME(sc), 2079 sc->sc_ld_list.mll_list[i].mll_state); 2080 } 2081 2082 /* additional status can modify MFI status */ 2083 switch (sc->sc_ld_details.mld_progress.mlp_in_prog) { 2084 case MFI_LD_PROG_CC: 2085 case MFI_LD_PROG_BGI: 2086 bv->bv_status = BIOC_SVSCRUB; 2087 per = (int)sc->sc_ld_details.mld_progress.mlp_cc.mp_progress; 2088 bv->bv_percent = (per * 100) / 0xffff; 2089 bv->bv_seconds = 2090 sc->sc_ld_details.mld_progress.mlp_cc.mp_elapsed_seconds; 2091 break; 2092 2093 case MFI_LD_PROG_FGI: 2094 case MFI_LD_PROG_RECONSTRUCT: 2095 /* nothing yet */ 2096 break; 2097 } 2098 2099 /* 2100 * The RAID levels are determined per the SNIA DDF spec, this is only 2101 * a subset that is valid for the MFI contrller. 2102 */ 2103 bv->bv_level = sc->sc_ld_details.mld_cfg.mlc_parm.mpa_pri_raid; 2104 if (sc->sc_ld_details.mld_cfg.mlc_parm.mpa_sec_raid == 2105 MFI_DDF_SRL_SPANNED) 2106 bv->bv_level *= 10; 2107 2108 bv->bv_nodisk = sc->sc_ld_details.mld_cfg.mlc_parm.mpa_no_drv_per_span * 2109 sc->sc_ld_details.mld_cfg.mlc_parm.mpa_span_depth; 2110 2111 bv->bv_size = sc->sc_ld_details.mld_size * 512; /* bytes per block */ 2112 2113 rv = 0; 2114 done: 2115 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_vol done %x\n", 2116 DEVNAME(sc), rv); 2117 return rv; 2118 } 2119 2120 static int 2121 mfi_ioctl_disk(struct mfi_softc *sc, struct bioc_disk *bd) 2122 { 2123 struct mfi_conf *cfg; 2124 struct mfi_array *ar; 2125 struct mfi_ld_cfg *ld; 2126 struct mfi_pd_details *pd; 2127 struct scsipi_inquiry_data *inqbuf; 2128 char vend[8+16+4+1]; 2129 int i, rv = EINVAL; 2130 int arr, vol, disk; 2131 uint32_t size; 2132 uint8_t mbox[MFI_MBOX_SIZE]; 2133 2134 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_disk %#x\n", 2135 DEVNAME(sc), bd->bd_diskid); 2136 2137 pd = malloc(sizeof *pd, M_DEVBUF, M_WAITOK | M_ZERO); 2138 2139 /* send single element command to retrieve size for full structure */ 2140 cfg = malloc(sizeof *cfg, M_DEVBUF, M_WAITOK); 2141 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 2142 sizeof *cfg, cfg, NULL, false)) 2143 goto freeme; 2144 2145 size = cfg->mfc_size; 2146 free(cfg, M_DEVBUF); 2147 2148 /* memory for read config */ 2149 cfg = malloc(size, M_DEVBUF, M_WAITOK|M_ZERO); 2150 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 2151 size, cfg, NULL, false)) 2152 goto freeme; 2153 2154 ar = cfg->mfc_array; 2155 2156 /* calculate offset to ld structure */ 2157 ld = (struct mfi_ld_cfg *)( 2158 ((uint8_t *)cfg) + offsetof(struct mfi_conf, mfc_array) + 2159 cfg->mfc_array_size * cfg->mfc_no_array); 2160 2161 vol = bd->bd_volid; 2162 2163 if (vol >= cfg->mfc_no_ld) { 2164 /* do hotspares */ 2165 rv = mfi_bio_hs(sc, bd->bd_volid, MFI_MGMT_SD, bd); 2166 goto freeme; 2167 } 2168 2169 /* find corresponding array for ld */ 2170 for (i = 0, arr = 0; i < vol; i++) 2171 arr += ld[i].mlc_parm.mpa_span_depth; 2172 2173 /* offset disk into pd list */ 2174 disk = bd->bd_diskid % ld[vol].mlc_parm.mpa_no_drv_per_span; 2175 2176 /* offset array index into the next spans */ 2177 arr += bd->bd_diskid / ld[vol].mlc_parm.mpa_no_drv_per_span; 2178 2179 bd->bd_target = ar[arr].pd[disk].mar_enc_slot; 2180 switch (ar[arr].pd[disk].mar_pd_state){ 2181 case MFI_PD_UNCONFIG_GOOD: 2182 bd->bd_status = BIOC_SDUNUSED; 2183 break; 2184 2185 case MFI_PD_HOTSPARE: /* XXX dedicated hotspare part of array? */ 2186 bd->bd_status = BIOC_SDHOTSPARE; 2187 break; 2188 2189 case MFI_PD_OFFLINE: 2190 bd->bd_status = BIOC_SDOFFLINE; 2191 break; 2192 2193 case MFI_PD_FAILED: 2194 bd->bd_status = BIOC_SDFAILED; 2195 break; 2196 2197 case MFI_PD_REBUILD: 2198 bd->bd_status = BIOC_SDREBUILD; 2199 break; 2200 2201 case MFI_PD_ONLINE: 2202 bd->bd_status = BIOC_SDONLINE; 2203 break; 2204 2205 case MFI_PD_UNCONFIG_BAD: /* XXX define new state in bio */ 2206 default: 2207 bd->bd_status = BIOC_SDINVALID; 2208 break; 2209 2210 } 2211 2212 /* get the remaining fields */ 2213 *((uint16_t *)&mbox) = ar[arr].pd[disk].mar_pd.mfp_id; 2214 memset(pd, 0, sizeof(*pd)); 2215 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_INFO, MFI_DATA_IN, 2216 sizeof *pd, pd, mbox, false)) 2217 goto freeme; 2218 2219 bd->bd_size = pd->mpd_size * 512; /* bytes per block */ 2220 2221 /* if pd->mpd_enc_idx is 0 then it is not in an enclosure */ 2222 bd->bd_channel = pd->mpd_enc_idx; 2223 2224 inqbuf = (struct scsipi_inquiry_data *)&pd->mpd_inq_data; 2225 memcpy(vend, inqbuf->vendor, sizeof vend - 1); 2226 vend[sizeof vend - 1] = '\0'; 2227 strlcpy(bd->bd_vendor, vend, sizeof(bd->bd_vendor)); 2228 2229 /* XXX find a way to retrieve serial nr from drive */ 2230 /* XXX find a way to get bd_procdev */ 2231 2232 rv = 0; 2233 freeme: 2234 free(pd, M_DEVBUF); 2235 free(cfg, M_DEVBUF); 2236 2237 return rv; 2238 } 2239 2240 static int 2241 mfi_ioctl_alarm(struct mfi_softc *sc, struct bioc_alarm *ba) 2242 { 2243 uint32_t opc, dir = MFI_DATA_NONE; 2244 int rv = 0; 2245 int8_t ret; 2246 2247 switch(ba->ba_opcode) { 2248 case BIOC_SADISABLE: 2249 opc = MR_DCMD_SPEAKER_DISABLE; 2250 break; 2251 2252 case BIOC_SAENABLE: 2253 opc = MR_DCMD_SPEAKER_ENABLE; 2254 break; 2255 2256 case BIOC_SASILENCE: 2257 opc = MR_DCMD_SPEAKER_SILENCE; 2258 break; 2259 2260 case BIOC_GASTATUS: 2261 opc = MR_DCMD_SPEAKER_GET; 2262 dir = MFI_DATA_IN; 2263 break; 2264 2265 case BIOC_SATEST: 2266 opc = MR_DCMD_SPEAKER_TEST; 2267 break; 2268 2269 default: 2270 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_alarm biocalarm invalid " 2271 "opcode %x\n", DEVNAME(sc), ba->ba_opcode); 2272 return EINVAL; 2273 } 2274 2275 if (mfi_mgmt_internal(sc, opc, dir, sizeof(ret), &ret, NULL, false)) 2276 rv = EINVAL; 2277 else 2278 if (ba->ba_opcode == BIOC_GASTATUS) 2279 ba->ba_status = ret; 2280 else 2281 ba->ba_status = 0; 2282 2283 return rv; 2284 } 2285 2286 static int 2287 mfi_ioctl_blink(struct mfi_softc *sc, struct bioc_blink *bb) 2288 { 2289 int i, found, rv = EINVAL; 2290 uint8_t mbox[MFI_MBOX_SIZE]; 2291 uint32_t cmd; 2292 struct mfi_pd_list *pd; 2293 2294 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_blink %x\n", DEVNAME(sc), 2295 bb->bb_status); 2296 2297 /* channel 0 means not in an enclosure so can't be blinked */ 2298 if (bb->bb_channel == 0) 2299 return EINVAL; 2300 2301 pd = malloc(MFI_PD_LIST_SIZE, M_DEVBUF, M_WAITOK); 2302 2303 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_LIST, MFI_DATA_IN, 2304 MFI_PD_LIST_SIZE, pd, NULL, false)) 2305 goto done; 2306 2307 for (i = 0, found = 0; i < pd->mpl_no_pd; i++) 2308 if (bb->bb_channel == pd->mpl_address[i].mpa_enc_index && 2309 bb->bb_target == pd->mpl_address[i].mpa_enc_slot) { 2310 found = 1; 2311 break; 2312 } 2313 2314 if (!found) 2315 goto done; 2316 2317 memset(mbox, 0, sizeof mbox); 2318 2319 *((uint16_t *)&mbox) = pd->mpl_address[i].mpa_pd_id; 2320 2321 switch (bb->bb_status) { 2322 case BIOC_SBUNBLINK: 2323 cmd = MR_DCMD_PD_UNBLINK; 2324 break; 2325 2326 case BIOC_SBBLINK: 2327 cmd = MR_DCMD_PD_BLINK; 2328 break; 2329 2330 case BIOC_SBALARM: 2331 default: 2332 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_blink biocblink invalid " 2333 "opcode %x\n", DEVNAME(sc), bb->bb_status); 2334 goto done; 2335 } 2336 2337 2338 if (mfi_mgmt_internal(sc, cmd, MFI_DATA_NONE, 0, NULL, mbox, false)) 2339 goto done; 2340 2341 rv = 0; 2342 done: 2343 free(pd, M_DEVBUF); 2344 return rv; 2345 } 2346 2347 static int 2348 mfi_ioctl_setstate(struct mfi_softc *sc, struct bioc_setstate *bs) 2349 { 2350 struct mfi_pd_list *pd; 2351 int i, found, rv = EINVAL; 2352 uint8_t mbox[MFI_MBOX_SIZE]; 2353 2354 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_setstate %x\n", DEVNAME(sc), 2355 bs->bs_status); 2356 2357 pd = malloc(MFI_PD_LIST_SIZE, M_DEVBUF, M_WAITOK); 2358 2359 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_LIST, MFI_DATA_IN, 2360 MFI_PD_LIST_SIZE, pd, NULL, false)) 2361 goto done; 2362 2363 for (i = 0, found = 0; i < pd->mpl_no_pd; i++) 2364 if (bs->bs_channel == pd->mpl_address[i].mpa_enc_index && 2365 bs->bs_target == pd->mpl_address[i].mpa_enc_slot) { 2366 found = 1; 2367 break; 2368 } 2369 2370 if (!found) 2371 goto done; 2372 2373 memset(mbox, 0, sizeof mbox); 2374 2375 *((uint16_t *)&mbox) = pd->mpl_address[i].mpa_pd_id; 2376 2377 switch (bs->bs_status) { 2378 case BIOC_SSONLINE: 2379 mbox[2] = MFI_PD_ONLINE; 2380 break; 2381 2382 case BIOC_SSOFFLINE: 2383 mbox[2] = MFI_PD_OFFLINE; 2384 break; 2385 2386 case BIOC_SSHOTSPARE: 2387 mbox[2] = MFI_PD_HOTSPARE; 2388 break; 2389 /* 2390 case BIOC_SSREBUILD: 2391 break; 2392 */ 2393 default: 2394 DNPRINTF(MFI_D_IOCTL, "%s: mfi_ioctl_setstate invalid " 2395 "opcode %x\n", DEVNAME(sc), bs->bs_status); 2396 goto done; 2397 } 2398 2399 2400 if (mfi_mgmt_internal(sc, MD_DCMD_PD_SET_STATE, MFI_DATA_NONE, 2401 0, NULL, mbox, false)) 2402 goto done; 2403 2404 rv = 0; 2405 done: 2406 free(pd, M_DEVBUF); 2407 return rv; 2408 } 2409 2410 static int 2411 mfi_bio_hs(struct mfi_softc *sc, int volid, int type, void *bio_hs) 2412 { 2413 struct mfi_conf *cfg; 2414 struct mfi_hotspare *hs; 2415 struct mfi_pd_details *pd; 2416 struct bioc_disk *sdhs; 2417 struct bioc_vol *vdhs; 2418 struct scsipi_inquiry_data *inqbuf; 2419 char vend[8+16+4+1]; 2420 int i, rv = EINVAL; 2421 uint32_t size; 2422 uint8_t mbox[MFI_MBOX_SIZE]; 2423 2424 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs %d\n", DEVNAME(sc), volid); 2425 2426 if (!bio_hs) 2427 return EINVAL; 2428 2429 pd = malloc(sizeof *pd, M_DEVBUF, M_WAITOK | M_ZERO); 2430 2431 /* send single element command to retrieve size for full structure */ 2432 cfg = malloc(sizeof *cfg, M_DEVBUF, M_WAITOK); 2433 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 2434 sizeof *cfg, cfg, NULL, false)) 2435 goto freeme; 2436 2437 size = cfg->mfc_size; 2438 free(cfg, M_DEVBUF); 2439 2440 /* memory for read config */ 2441 cfg = malloc(size, M_DEVBUF, M_WAITOK|M_ZERO); 2442 if (mfi_mgmt_internal(sc, MD_DCMD_CONF_GET, MFI_DATA_IN, 2443 size, cfg, NULL, false)) 2444 goto freeme; 2445 2446 /* calculate offset to hs structure */ 2447 hs = (struct mfi_hotspare *)( 2448 ((uint8_t *)cfg) + offsetof(struct mfi_conf, mfc_array) + 2449 cfg->mfc_array_size * cfg->mfc_no_array + 2450 cfg->mfc_ld_size * cfg->mfc_no_ld); 2451 2452 if (volid < cfg->mfc_no_ld) 2453 goto freeme; /* not a hotspare */ 2454 2455 if (volid > (cfg->mfc_no_ld + cfg->mfc_no_hs)) 2456 goto freeme; /* not a hotspare */ 2457 2458 /* offset into hotspare structure */ 2459 i = volid - cfg->mfc_no_ld; 2460 2461 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs i %d volid %d no_ld %d no_hs %d " 2462 "hs %p cfg %p id %02x\n", DEVNAME(sc), i, volid, cfg->mfc_no_ld, 2463 cfg->mfc_no_hs, hs, cfg, hs[i].mhs_pd.mfp_id); 2464 2465 /* get pd fields */ 2466 memset(mbox, 0, sizeof mbox); 2467 *((uint16_t *)&mbox) = hs[i].mhs_pd.mfp_id; 2468 if (mfi_mgmt_internal(sc, MR_DCMD_PD_GET_INFO, MFI_DATA_IN, 2469 sizeof *pd, pd, mbox, false)) { 2470 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs illegal PD\n", 2471 DEVNAME(sc)); 2472 goto freeme; 2473 } 2474 2475 switch (type) { 2476 case MFI_MGMT_VD: 2477 vdhs = bio_hs; 2478 vdhs->bv_status = BIOC_SVONLINE; 2479 vdhs->bv_size = pd->mpd_size * 512; /* bytes per block */ 2480 vdhs->bv_level = -1; /* hotspare */ 2481 vdhs->bv_nodisk = 1; 2482 break; 2483 2484 case MFI_MGMT_SD: 2485 sdhs = bio_hs; 2486 sdhs->bd_status = BIOC_SDHOTSPARE; 2487 sdhs->bd_size = pd->mpd_size * 512; /* bytes per block */ 2488 sdhs->bd_channel = pd->mpd_enc_idx; 2489 sdhs->bd_target = pd->mpd_enc_slot; 2490 inqbuf = (struct scsipi_inquiry_data *)&pd->mpd_inq_data; 2491 memcpy(vend, inqbuf->vendor, sizeof(vend) - 1); 2492 vend[sizeof vend - 1] = '\0'; 2493 strlcpy(sdhs->bd_vendor, vend, sizeof(sdhs->bd_vendor)); 2494 break; 2495 2496 default: 2497 goto freeme; 2498 } 2499 2500 DNPRINTF(MFI_D_IOCTL, "%s: mfi_vol_hs 6\n", DEVNAME(sc)); 2501 rv = 0; 2502 freeme: 2503 free(pd, M_DEVBUF); 2504 free(cfg, M_DEVBUF); 2505 2506 return rv; 2507 } 2508 2509 static int 2510 mfi_destroy_sensors(struct mfi_softc *sc) 2511 { 2512 if (sc->sc_sme == NULL) 2513 return 0; 2514 sysmon_envsys_unregister(sc->sc_sme); 2515 sc->sc_sme = NULL; 2516 free(sc->sc_sensor, M_DEVBUF); 2517 return 0; 2518 } 2519 2520 static int 2521 mfi_create_sensors(struct mfi_softc *sc) 2522 { 2523 int i; 2524 int nsensors = sc->sc_ld_cnt + 1; 2525 int rv; 2526 2527 sc->sc_sme = sysmon_envsys_create(); 2528 sc->sc_sensor = malloc(sizeof(envsys_data_t) * nsensors, 2529 M_DEVBUF, M_NOWAIT | M_ZERO); 2530 if (sc->sc_sensor == NULL) { 2531 aprint_error_dev(sc->sc_dev, "can't allocate envsys_data_t\n"); 2532 return ENOMEM; 2533 } 2534 2535 /* BBU */ 2536 sc->sc_sensor[0].units = ENVSYS_INDICATOR; 2537 sc->sc_sensor[0].state = ENVSYS_SINVALID; 2538 sc->sc_sensor[0].value_cur = 0; 2539 /* Enable monitoring for BBU state changes, if present */ 2540 if (sc->sc_info.mci_hw_present & MFI_INFO_HW_BBU) 2541 sc->sc_sensor[0].flags |= ENVSYS_FMONCRITICAL; 2542 snprintf(sc->sc_sensor[0].desc, 2543 sizeof(sc->sc_sensor[0].desc), "%s BBU", DEVNAME(sc)); 2544 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[0])) 2545 goto out; 2546 2547 for (i = 1; i < nsensors; i++) { 2548 sc->sc_sensor[i].units = ENVSYS_DRIVE; 2549 sc->sc_sensor[i].state = ENVSYS_SINVALID; 2550 sc->sc_sensor[i].value_cur = ENVSYS_DRIVE_EMPTY; 2551 /* Enable monitoring for drive state changes */ 2552 sc->sc_sensor[i].flags |= ENVSYS_FMONSTCHANGED; 2553 /* logical drives */ 2554 snprintf(sc->sc_sensor[i].desc, 2555 sizeof(sc->sc_sensor[i].desc), "%s:%d", 2556 DEVNAME(sc), i - 1); 2557 if (sysmon_envsys_sensor_attach(sc->sc_sme, 2558 &sc->sc_sensor[i])) 2559 goto out; 2560 } 2561 2562 sc->sc_sme->sme_name = DEVNAME(sc); 2563 sc->sc_sme->sme_cookie = sc; 2564 sc->sc_sme->sme_refresh = mfi_sensor_refresh; 2565 rv = sysmon_envsys_register(sc->sc_sme); 2566 if (rv != 0) { 2567 aprint_error_dev(sc->sc_dev, 2568 "unable to register with sysmon (rv = %d)\n", rv); 2569 goto out; 2570 } 2571 return 0; 2572 2573 out: 2574 free(sc->sc_sensor, M_DEVBUF); 2575 sysmon_envsys_destroy(sc->sc_sme); 2576 sc->sc_sme = NULL; 2577 return EINVAL; 2578 } 2579 2580 static void 2581 mfi_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 2582 { 2583 struct mfi_softc *sc = sme->sme_cookie; 2584 struct bioc_vol bv; 2585 int s; 2586 int error; 2587 2588 if (edata->sensor >= sc->sc_ld_cnt + 1) 2589 return; 2590 2591 if (edata->sensor == 0) { 2592 /* BBU */ 2593 struct mfi_bbu_status bbu_stat; 2594 int bbu_status; 2595 if ((sc->sc_info.mci_hw_present & MFI_INFO_HW_BBU) == 0) 2596 return; 2597 2598 KERNEL_LOCK(1, curlwp); 2599 s = splbio(); 2600 bbu_status = mfi_get_bbu(sc, &bbu_stat); 2601 splx(s); 2602 KERNEL_UNLOCK_ONE(curlwp); 2603 switch(bbu_status) { 2604 case MFI_BBU_GOOD: 2605 edata->value_cur = 1; 2606 edata->state = ENVSYS_SVALID; 2607 if (!sc->sc_bbuok) 2608 aprint_normal_dev(sc->sc_dev, 2609 "BBU state changed to good\n"); 2610 sc->sc_bbuok = true; 2611 break; 2612 case MFI_BBU_BAD: 2613 edata->value_cur = 0; 2614 edata->state = ENVSYS_SCRITICAL; 2615 if (sc->sc_bbuok) 2616 aprint_normal_dev(sc->sc_dev, 2617 "BBU state changed to bad\n"); 2618 sc->sc_bbuok = false; 2619 break; 2620 case MFI_BBU_UNKNOWN: 2621 default: 2622 edata->value_cur = 0; 2623 edata->state = ENVSYS_SINVALID; 2624 sc->sc_bbuok = false; 2625 break; 2626 } 2627 return; 2628 } 2629 2630 memset(&bv, 0, sizeof(bv)); 2631 bv.bv_volid = edata->sensor - 1; 2632 KERNEL_LOCK(1, curlwp); 2633 s = splbio(); 2634 error = mfi_ioctl_vol(sc, &bv); 2635 splx(s); 2636 KERNEL_UNLOCK_ONE(curlwp); 2637 if (error) 2638 return; 2639 2640 switch(bv.bv_status) { 2641 case BIOC_SVOFFLINE: 2642 edata->value_cur = ENVSYS_DRIVE_FAIL; 2643 edata->state = ENVSYS_SCRITICAL; 2644 break; 2645 2646 case BIOC_SVDEGRADED: 2647 edata->value_cur = ENVSYS_DRIVE_PFAIL; 2648 edata->state = ENVSYS_SCRITICAL; 2649 break; 2650 2651 case BIOC_SVSCRUB: 2652 case BIOC_SVONLINE: 2653 edata->value_cur = ENVSYS_DRIVE_ONLINE; 2654 edata->state = ENVSYS_SVALID; 2655 break; 2656 2657 case BIOC_SVINVALID: 2658 /* FALLTRHOUGH */ 2659 default: 2660 edata->value_cur = 0; /* unknown */ 2661 edata->state = ENVSYS_SINVALID; 2662 } 2663 } 2664 2665 #endif /* NBIO > 0 */ 2666 2667 static uint32_t 2668 mfi_xscale_fw_state(struct mfi_softc *sc) 2669 { 2670 return mfi_read(sc, MFI_OMSG0); 2671 } 2672 2673 static void 2674 mfi_xscale_intr_dis(struct mfi_softc *sc) 2675 { 2676 mfi_write(sc, MFI_OMSK, 0); 2677 } 2678 2679 static void 2680 mfi_xscale_intr_ena(struct mfi_softc *sc) 2681 { 2682 mfi_write(sc, MFI_OMSK, MFI_ENABLE_INTR); 2683 } 2684 2685 static int 2686 mfi_xscale_intr(struct mfi_softc *sc) 2687 { 2688 uint32_t status; 2689 2690 status = mfi_read(sc, MFI_OSTS); 2691 if (!ISSET(status, MFI_OSTS_INTR_VALID)) 2692 return 0; 2693 2694 /* write status back to acknowledge interrupt */ 2695 mfi_write(sc, MFI_OSTS, status); 2696 return 1; 2697 } 2698 2699 static void 2700 mfi_xscale_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2701 { 2702 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_frames), 2703 ccb->ccb_pframe - MFIMEM_DVA(sc->sc_frames), 2704 sc->sc_frames_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2705 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_sense), 2706 ccb->ccb_psense - MFIMEM_DVA(sc->sc_sense), 2707 MFI_SENSE_SIZE, BUS_DMASYNC_PREREAD); 2708 2709 mfi_write(sc, MFI_IQP, (ccb->ccb_pframe >> 3) | 2710 ccb->ccb_extra_frames); 2711 ccb->ccb_state = MFI_CCB_RUNNING; 2712 } 2713 2714 static uint32_t 2715 mfi_ppc_fw_state(struct mfi_softc *sc) 2716 { 2717 return mfi_read(sc, MFI_OSP); 2718 } 2719 2720 static void 2721 mfi_ppc_intr_dis(struct mfi_softc *sc) 2722 { 2723 /* Taking a wild guess --dyoung */ 2724 mfi_write(sc, MFI_OMSK, ~(uint32_t)0x0); 2725 mfi_write(sc, MFI_ODC, 0xffffffff); 2726 } 2727 2728 static void 2729 mfi_ppc_intr_ena(struct mfi_softc *sc) 2730 { 2731 mfi_write(sc, MFI_ODC, 0xffffffff); 2732 mfi_write(sc, MFI_OMSK, ~0x80000004); 2733 } 2734 2735 static int 2736 mfi_ppc_intr(struct mfi_softc *sc) 2737 { 2738 uint32_t status; 2739 2740 status = mfi_read(sc, MFI_OSTS); 2741 if (!ISSET(status, MFI_OSTS_PPC_INTR_VALID)) 2742 return 0; 2743 2744 /* write status back to acknowledge interrupt */ 2745 mfi_write(sc, MFI_ODC, status); 2746 return 1; 2747 } 2748 2749 static void 2750 mfi_ppc_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2751 { 2752 mfi_write(sc, MFI_IQP, 0x1 | ccb->ccb_pframe | 2753 (ccb->ccb_extra_frames << 1)); 2754 ccb->ccb_state = MFI_CCB_RUNNING; 2755 } 2756 2757 u_int32_t 2758 mfi_gen2_fw_state(struct mfi_softc *sc) 2759 { 2760 return (mfi_read(sc, MFI_OSP)); 2761 } 2762 2763 void 2764 mfi_gen2_intr_dis(struct mfi_softc *sc) 2765 { 2766 mfi_write(sc, MFI_OMSK, 0xffffffff); 2767 mfi_write(sc, MFI_ODC, 0xffffffff); 2768 } 2769 2770 void 2771 mfi_gen2_intr_ena(struct mfi_softc *sc) 2772 { 2773 mfi_write(sc, MFI_ODC, 0xffffffff); 2774 mfi_write(sc, MFI_OMSK, ~MFI_OSTS_GEN2_INTR_VALID); 2775 } 2776 2777 int 2778 mfi_gen2_intr(struct mfi_softc *sc) 2779 { 2780 u_int32_t status; 2781 2782 status = mfi_read(sc, MFI_OSTS); 2783 if (!ISSET(status, MFI_OSTS_GEN2_INTR_VALID)) 2784 return (0); 2785 2786 /* write status back to acknowledge interrupt */ 2787 mfi_write(sc, MFI_ODC, status); 2788 2789 return (1); 2790 } 2791 2792 void 2793 mfi_gen2_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2794 { 2795 mfi_write(sc, MFI_IQP, 0x1 | ccb->ccb_pframe | 2796 (ccb->ccb_extra_frames << 1)); 2797 ccb->ccb_state = MFI_CCB_RUNNING; 2798 } 2799 2800 u_int32_t 2801 mfi_skinny_fw_state(struct mfi_softc *sc) 2802 { 2803 return (mfi_read(sc, MFI_OSP)); 2804 } 2805 2806 void 2807 mfi_skinny_intr_dis(struct mfi_softc *sc) 2808 { 2809 mfi_write(sc, MFI_OMSK, 0); 2810 } 2811 2812 void 2813 mfi_skinny_intr_ena(struct mfi_softc *sc) 2814 { 2815 mfi_write(sc, MFI_OMSK, ~0x00000001); 2816 } 2817 2818 int 2819 mfi_skinny_intr(struct mfi_softc *sc) 2820 { 2821 u_int32_t status; 2822 2823 status = mfi_read(sc, MFI_OSTS); 2824 if (!ISSET(status, MFI_OSTS_SKINNY_INTR_VALID)) 2825 return (0); 2826 2827 /* write status back to acknowledge interrupt */ 2828 mfi_write(sc, MFI_OSTS, status); 2829 2830 return (1); 2831 } 2832 2833 void 2834 mfi_skinny_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2835 { 2836 mfi_write(sc, MFI_IQPL, 0x1 | ccb->ccb_pframe | 2837 (ccb->ccb_extra_frames << 1)); 2838 mfi_write(sc, MFI_IQPH, 0x00000000); 2839 ccb->ccb_state = MFI_CCB_RUNNING; 2840 } 2841 2842 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008) 2843 2844 void 2845 mfi_tbolt_intr_ena(struct mfi_softc *sc) 2846 { 2847 mfi_write(sc, MFI_OMSK, ~MFI_FUSION_ENABLE_INTERRUPT_MASK); 2848 mfi_read(sc, MFI_OMSK); 2849 } 2850 2851 void 2852 mfi_tbolt_intr_dis(struct mfi_softc *sc) 2853 { 2854 mfi_write(sc, MFI_OMSK, 0xFFFFFFFF); 2855 mfi_read(sc, MFI_OMSK); 2856 } 2857 2858 int 2859 mfi_tbolt_intr(struct mfi_softc *sc) 2860 { 2861 int32_t status; 2862 2863 status = mfi_read(sc, MFI_OSTS); 2864 2865 if (ISSET(status, 0x1)) { 2866 mfi_write(sc, MFI_OSTS, status); 2867 mfi_read(sc, MFI_OSTS); 2868 if (ISSET(status, MFI_STATE_CHANGE_INTERRUPT)) 2869 return 0; 2870 return 1; 2871 } 2872 if (!ISSET(status, MFI_FUSION_ENABLE_INTERRUPT_MASK)) 2873 return 0; 2874 mfi_read(sc, MFI_OSTS); 2875 return 1; 2876 } 2877 2878 u_int32_t 2879 mfi_tbolt_fw_state(struct mfi_softc *sc) 2880 { 2881 return mfi_read(sc, MFI_OSP); 2882 } 2883 2884 void 2885 mfi_tbolt_post(struct mfi_softc *sc, struct mfi_ccb *ccb) 2886 { 2887 if (sc->sc_MFA_enabled) { 2888 if ((ccb->ccb_flags & MFI_CCB_F_TBOLT) == 0) 2889 mfi_tbolt_build_mpt_ccb(ccb); 2890 mfi_write(sc, MFI_IQPL, 2891 ccb->ccb_tb_request_desc.words & 0xFFFFFFFF); 2892 mfi_write(sc, MFI_IQPH, 2893 ccb->ccb_tb_request_desc.words >> 32); 2894 ccb->ccb_state = MFI_CCB_RUNNING; 2895 return; 2896 } 2897 uint64_t bus_add = ccb->ccb_pframe; 2898 bus_add |= (MFI_REQ_DESCRIPT_FLAGS_MFA 2899 << MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2900 mfi_write(sc, MFI_IQPL, bus_add); 2901 mfi_write(sc, MFI_IQPH, bus_add >> 32); 2902 ccb->ccb_state = MFI_CCB_RUNNING; 2903 } 2904 2905 static void 2906 mfi_tbolt_build_mpt_ccb(struct mfi_ccb *ccb) 2907 { 2908 union mfi_mpi2_request_descriptor *req_desc = &ccb->ccb_tb_request_desc; 2909 struct mfi_mpi2_request_raid_scsi_io *io_req = ccb->ccb_tb_io_request; 2910 struct mpi25_ieee_sge_chain64 *mpi25_ieee_chain; 2911 2912 io_req->Function = MPI2_FUNCTION_PASSTHRU_IO_REQUEST; 2913 io_req->SGLOffset0 = 2914 offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 4; 2915 io_req->ChainOffset = 2916 offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16; 2917 2918 mpi25_ieee_chain = 2919 (struct mpi25_ieee_sge_chain64 *)&io_req->SGL.IeeeChain; 2920 mpi25_ieee_chain->Address = ccb->ccb_pframe; 2921 2922 /* 2923 In MFI pass thru, nextChainOffset will always be zero to 2924 indicate the end of the chain. 2925 */ 2926 mpi25_ieee_chain->Flags= MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT 2927 | MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR; 2928 2929 /* setting the length to the maximum length */ 2930 mpi25_ieee_chain->Length = 1024; 2931 2932 req_desc->header.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << 2933 MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2934 ccb->ccb_flags |= MFI_CCB_F_TBOLT; 2935 bus_dmamap_sync(ccb->ccb_sc->sc_dmat, 2936 MFIMEM_MAP(ccb->ccb_sc->sc_tbolt_reqmsgpool), 2937 ccb->ccb_tb_pio_request - 2938 MFIMEM_DVA(ccb->ccb_sc->sc_tbolt_reqmsgpool), 2939 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE, 2940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2941 } 2942 2943 /* 2944 * Description: 2945 * This function will prepare message pools for the Thunderbolt controller 2946 */ 2947 static int 2948 mfi_tbolt_init_desc_pool(struct mfi_softc *sc) 2949 { 2950 uint32_t offset = 0; 2951 uint8_t *addr = MFIMEM_KVA(sc->sc_tbolt_reqmsgpool); 2952 2953 /* Request Decriptors alignment restrictions */ 2954 KASSERT(((uintptr_t)addr & 0xFF) == 0); 2955 2956 /* Skip request message pool */ 2957 addr = &addr[MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1)]; 2958 2959 /* Reply Frame Pool is initialized */ 2960 sc->sc_reply_frame_pool = (struct mfi_mpi2_reply_header *) addr; 2961 KASSERT(((uintptr_t)addr & 0xFF) == 0); 2962 2963 offset = (uintptr_t)sc->sc_reply_frame_pool 2964 - (uintptr_t)MFIMEM_KVA(sc->sc_tbolt_reqmsgpool); 2965 sc->sc_reply_frame_busaddr = 2966 MFIMEM_DVA(sc->sc_tbolt_reqmsgpool) + offset; 2967 2968 /* initializing reply address to 0xFFFFFFFF */ 2969 memset((uint8_t *)sc->sc_reply_frame_pool, 0xFF, 2970 (MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size)); 2971 2972 /* Skip Reply Frame Pool */ 2973 addr += MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size; 2974 sc->sc_reply_pool_limit = (void *)addr; 2975 2976 offset = MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size; 2977 sc->sc_sg_frame_busaddr = sc->sc_reply_frame_busaddr + offset; 2978 2979 /* initialize the last_reply_idx to 0 */ 2980 sc->sc_last_reply_idx = 0; 2981 offset = (sc->sc_sg_frame_busaddr + (MEGASAS_MAX_SZ_CHAIN_FRAME * 2982 sc->sc_max_cmds)) - MFIMEM_DVA(sc->sc_tbolt_reqmsgpool); 2983 KASSERT(offset <= sc->sc_tbolt_reqmsgpool->am_size); 2984 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 0, 2985 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool)->dm_mapsize, 2986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2987 return 0; 2988 } 2989 2990 /* 2991 * This routine prepare and issue INIT2 frame to the Firmware 2992 */ 2993 2994 static int 2995 mfi_tbolt_init_MFI_queue(struct mfi_softc *sc) 2996 { 2997 struct mpi2_ioc_init_request *mpi2IocInit; 2998 struct mfi_init_frame *mfi_init; 2999 struct mfi_ccb *ccb; 3000 bus_addr_t phyAddress; 3001 mfi_address *mfiAddressTemp; 3002 int s; 3003 char *verbuf; 3004 char wqbuf[10]; 3005 3006 /* Check if initialization is already completed */ 3007 if (sc->sc_MFA_enabled) { 3008 return 1; 3009 } 3010 3011 mpi2IocInit = 3012 (struct mpi2_ioc_init_request *)MFIMEM_KVA(sc->sc_tbolt_ioc_init); 3013 3014 s = splbio(); 3015 if ((ccb = mfi_get_ccb(sc)) == NULL) { 3016 splx(s); 3017 return (EBUSY); 3018 } 3019 3020 3021 mfi_init = &ccb->ccb_frame->mfr_init; 3022 3023 memset(mpi2IocInit, 0, sizeof(struct mpi2_ioc_init_request)); 3024 mpi2IocInit->Function = MPI2_FUNCTION_IOC_INIT; 3025 mpi2IocInit->WhoInit = MPI2_WHOINIT_HOST_DRIVER; 3026 3027 /* set MsgVersion and HeaderVersion host driver was built with */ 3028 mpi2IocInit->MsgVersion = MPI2_VERSION; 3029 mpi2IocInit->HeaderVersion = MPI2_HEADER_VERSION; 3030 mpi2IocInit->SystemRequestFrameSize = MEGASAS_THUNDERBOLT_NEW_MSG_SIZE/4; 3031 mpi2IocInit->ReplyDescriptorPostQueueDepth = 3032 (uint16_t)sc->sc_reply_pool_size; 3033 mpi2IocInit->ReplyFreeQueueDepth = 0; /* Not supported by MR. */ 3034 3035 /* Get physical address of reply frame pool */ 3036 phyAddress = sc->sc_reply_frame_busaddr; 3037 mfiAddressTemp = 3038 (mfi_address *)&mpi2IocInit->ReplyDescriptorPostQueueAddress; 3039 mfiAddressTemp->u.addressLow = (uint32_t)phyAddress; 3040 mfiAddressTemp->u.addressHigh = (uint32_t)((uint64_t)phyAddress >> 32); 3041 3042 /* Get physical address of request message pool */ 3043 phyAddress = MFIMEM_DVA(sc->sc_tbolt_reqmsgpool); 3044 mfiAddressTemp = (mfi_address *)&mpi2IocInit->SystemRequestFrameBaseAddress; 3045 mfiAddressTemp->u.addressLow = (uint32_t)phyAddress; 3046 mfiAddressTemp->u.addressHigh = (uint32_t)((uint64_t)phyAddress >> 32); 3047 3048 mpi2IocInit->ReplyFreeQueueAddress = 0; /* Not supported by MR. */ 3049 mpi2IocInit->TimeStamp = time_uptime; 3050 3051 verbuf = MFIMEM_KVA(sc->sc_tbolt_verbuf); 3052 snprintf(verbuf, strlen(MEGASAS_VERSION) + 2, "%s\n", 3053 MEGASAS_VERSION); 3054 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_verbuf), 0, 3055 MFIMEM_MAP(sc->sc_tbolt_verbuf)->dm_mapsize, BUS_DMASYNC_PREWRITE); 3056 mfi_init->driver_ver_lo = htole32(MFIMEM_DVA(sc->sc_tbolt_verbuf)); 3057 mfi_init->driver_ver_hi = 3058 htole32((uint64_t)MFIMEM_DVA(sc->sc_tbolt_verbuf) >> 32); 3059 3060 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_ioc_init), 0, 3061 MFIMEM_MAP(sc->sc_tbolt_ioc_init)->dm_mapsize, 3062 BUS_DMASYNC_PREWRITE); 3063 /* Get the physical address of the mpi2 ioc init command */ 3064 phyAddress = MFIMEM_DVA(sc->sc_tbolt_ioc_init); 3065 mfi_init->mif_qinfo_new_addr_lo = htole32(phyAddress); 3066 mfi_init->mif_qinfo_new_addr_hi = htole32((uint64_t)phyAddress >> 32); 3067 3068 mfi_init->mif_header.mfh_cmd = MFI_CMD_INIT; 3069 mfi_init->mif_header.mfh_data_len = sizeof(struct mpi2_ioc_init_request); 3070 if (mfi_poll(ccb) != 0) { 3071 aprint_error_dev(sc->sc_dev, "failed to send IOC init2 " 3072 "command at 0x%" PRIx64 "\n", 3073 (uint64_t)ccb->ccb_pframe); 3074 splx(s); 3075 return 1; 3076 } 3077 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_verbuf), 0, 3078 MFIMEM_MAP(sc->sc_tbolt_verbuf)->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3079 bus_dmamap_sync(sc->sc_dmat, MFIMEM_MAP(sc->sc_tbolt_ioc_init), 0, 3080 MFIMEM_MAP(sc->sc_tbolt_ioc_init)->dm_mapsize, 3081 BUS_DMASYNC_POSTWRITE); 3082 mfi_put_ccb(ccb); 3083 splx(s); 3084 3085 if (mfi_init->mif_header.mfh_cmd_status == 0) { 3086 sc->sc_MFA_enabled = 1; 3087 } 3088 else { 3089 aprint_error_dev(sc->sc_dev, "Init command Failed %x\n", 3090 mfi_init->mif_header.mfh_cmd_status); 3091 return 1; 3092 } 3093 3094 snprintf(wqbuf, sizeof(wqbuf), "%swq", DEVNAME(sc)); 3095 if (workqueue_create(&sc->sc_ldsync_wq, wqbuf, mfi_tbolt_sync_map_info, 3096 sc, PRIBIO, IPL_BIO, 0) != 0) { 3097 aprint_error_dev(sc->sc_dev, "workqueue_create failed\n"); 3098 return 1; 3099 } 3100 workqueue_enqueue(sc->sc_ldsync_wq, &sc->sc_ldsync_wk, NULL); 3101 return 0; 3102 } 3103 3104 int 3105 mfi_tbolt_intrh(void *arg) 3106 { 3107 struct mfi_softc *sc = arg; 3108 struct mfi_ccb *ccb; 3109 union mfi_mpi2_reply_descriptor *desc; 3110 int smid, num_completed; 3111 3112 if (!mfi_tbolt_intr(sc)) 3113 return 0; 3114 3115 DNPRINTF(MFI_D_INTR, "%s: mfi_tbolt_intrh %#lx %#lx\n", DEVNAME(sc), 3116 (u_long)sc, (u_long)sc->sc_last_reply_idx); 3117 3118 KASSERT(sc->sc_last_reply_idx < sc->sc_reply_pool_size); 3119 3120 desc = (union mfi_mpi2_reply_descriptor *) 3121 ((uintptr_t)sc->sc_reply_frame_pool + 3122 sc->sc_last_reply_idx * MEGASAS_THUNDERBOLT_REPLY_SIZE); 3123 3124 bus_dmamap_sync(sc->sc_dmat, 3125 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 3126 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1), 3127 MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size, 3128 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3129 num_completed = 0; 3130 while ((desc->header.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK) != 3131 MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 3132 smid = desc->header.SMID; 3133 KASSERT(smid > 0 && smid <= sc->sc_max_cmds); 3134 ccb = &sc->sc_ccb[smid - 1]; 3135 DNPRINTF(MFI_D_INTR, 3136 "%s: mfi_tbolt_intr SMID %#x reply_idx %#x " 3137 "desc %#" PRIx64 " ccb %p\n", DEVNAME(sc), smid, 3138 sc->sc_last_reply_idx, desc->words, ccb); 3139 KASSERT(ccb->ccb_state == MFI_CCB_RUNNING); 3140 if (ccb->ccb_flags & MFI_CCB_F_TBOLT_IO && 3141 ccb->ccb_tb_io_request->ChainOffset != 0) { 3142 bus_dmamap_sync(sc->sc_dmat, 3143 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 3144 ccb->ccb_tb_psg_frame - 3145 MFIMEM_DVA(sc->sc_tbolt_reqmsgpool), 3146 MEGASAS_MAX_SZ_CHAIN_FRAME, BUS_DMASYNC_POSTREAD); 3147 } 3148 if (ccb->ccb_flags & MFI_CCB_F_TBOLT_IO) { 3149 bus_dmamap_sync(sc->sc_dmat, 3150 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 3151 ccb->ccb_tb_pio_request - 3152 MFIMEM_DVA(sc->sc_tbolt_reqmsgpool), 3153 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE, 3154 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3155 } 3156 if (ccb->ccb_done) 3157 ccb->ccb_done(ccb); 3158 else 3159 ccb->ccb_state = MFI_CCB_DONE; 3160 sc->sc_last_reply_idx++; 3161 if (sc->sc_last_reply_idx >= sc->sc_reply_pool_size) { 3162 sc->sc_last_reply_idx = 0; 3163 } 3164 desc->words = ~0x0; 3165 /* Get the next reply descriptor */ 3166 desc = (union mfi_mpi2_reply_descriptor *) 3167 ((uintptr_t)sc->sc_reply_frame_pool + 3168 sc->sc_last_reply_idx * MEGASAS_THUNDERBOLT_REPLY_SIZE); 3169 num_completed++; 3170 } 3171 if (num_completed == 0) 3172 return 0; 3173 3174 bus_dmamap_sync(sc->sc_dmat, 3175 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 3176 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * (sc->sc_max_cmds + 1), 3177 MEGASAS_THUNDERBOLT_REPLY_SIZE * sc->sc_reply_pool_size, 3178 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3179 mfi_write(sc, MFI_RPI, sc->sc_last_reply_idx); 3180 return 1; 3181 } 3182 3183 3184 int 3185 mfi_tbolt_scsi_ld_io(struct mfi_ccb *ccb, struct scsipi_xfer *xs, 3186 uint64_t blockno, uint32_t blockcnt) 3187 { 3188 struct scsipi_periph *periph = xs->xs_periph; 3189 struct mfi_mpi2_request_raid_scsi_io *io_req; 3190 int sge_count; 3191 3192 DNPRINTF(MFI_D_CMD, "%s: mfi_tbolt_scsi_ld_io: %d\n", 3193 device_xname(periph->periph_channel->chan_adapter->adapt_dev), 3194 periph->periph_target); 3195 3196 if (!xs->data) 3197 return 1; 3198 3199 ccb->ccb_done = mfi_tbolt_scsi_ld_done; 3200 ccb->ccb_xs = xs; 3201 ccb->ccb_data = xs->data; 3202 ccb->ccb_len = xs->datalen; 3203 3204 io_req = ccb->ccb_tb_io_request; 3205 3206 /* Just the CDB length,rest of the Flags are zero */ 3207 io_req->IoFlags = xs->cmdlen; 3208 memset(io_req->CDB.CDB32, 0, 32); 3209 memcpy(io_req->CDB.CDB32, &xs->cmdstore, xs->cmdlen); 3210 3211 io_req->RaidContext.TargetID = periph->periph_target; 3212 io_req->RaidContext.Status = 0; 3213 io_req->RaidContext.exStatus = 0; 3214 io_req->RaidContext.timeoutValue = MFI_FUSION_FP_DEFAULT_TIMEOUT; 3215 io_req->Function = MPI2_FUNCTION_LD_IO_REQUEST; 3216 io_req->DevHandle = periph->periph_target; 3217 3218 ccb->ccb_tb_request_desc.header.RequestFlags = 3219 (MFI_REQ_DESCRIPT_FLAGS_LD_IO << MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 3220 io_req->DataLength = blockcnt * MFI_SECTOR_LEN; 3221 3222 if (xs->xs_control & XS_CTL_DATA_IN) { 3223 io_req->Control = MPI2_SCSIIO_CONTROL_READ; 3224 ccb->ccb_direction = MFI_DATA_IN; 3225 } else { 3226 io_req->Control = MPI2_SCSIIO_CONTROL_WRITE; 3227 ccb->ccb_direction = MFI_DATA_OUT; 3228 } 3229 3230 sge_count = mfi_tbolt_create_sgl(ccb, 3231 (xs->xs_control & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK 3232 ); 3233 if (sge_count < 0) 3234 return 1; 3235 KASSERT(sge_count <= ccb->ccb_sc->sc_max_sgl); 3236 io_req->RaidContext.numSGE = sge_count; 3237 io_req->SGLFlags = MPI2_SGE_FLAGS_64_BIT_ADDRESSING; 3238 io_req->SGLOffset0 = 3239 offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 4; 3240 3241 io_req->SenseBufferLowAddress = htole32(ccb->ccb_psense); 3242 io_req->SenseBufferLength = MFI_SENSE_SIZE; 3243 3244 ccb->ccb_flags |= MFI_CCB_F_TBOLT | MFI_CCB_F_TBOLT_IO; 3245 bus_dmamap_sync(ccb->ccb_sc->sc_dmat, 3246 MFIMEM_MAP(ccb->ccb_sc->sc_tbolt_reqmsgpool), 3247 ccb->ccb_tb_pio_request - 3248 MFIMEM_DVA(ccb->ccb_sc->sc_tbolt_reqmsgpool), 3249 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE, 3250 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3251 3252 return 0; 3253 } 3254 3255 3256 static void 3257 mfi_tbolt_scsi_ld_done(struct mfi_ccb *ccb) 3258 { 3259 struct mfi_mpi2_request_raid_scsi_io *io_req = ccb->ccb_tb_io_request; 3260 mfi_scsi_xs_done(ccb, io_req->RaidContext.Status, 3261 io_req->RaidContext.exStatus); 3262 } 3263 3264 static int 3265 mfi_tbolt_create_sgl(struct mfi_ccb *ccb, int flags) 3266 { 3267 struct mfi_softc *sc = ccb->ccb_sc; 3268 bus_dma_segment_t *sgd; 3269 int error, i, sge_idx, sge_count; 3270 struct mfi_mpi2_request_raid_scsi_io *io_req; 3271 struct mpi25_ieee_sge_chain64 *sgl_ptr; 3272 3273 DNPRINTF(MFI_D_DMA, "%s: mfi_tbolt_create_sgl %#lx\n", DEVNAME(sc), 3274 (u_long)ccb->ccb_data); 3275 3276 if (!ccb->ccb_data) 3277 return -1; 3278 3279 KASSERT(flags == BUS_DMA_NOWAIT || !cpu_intr_p()); 3280 error = bus_dmamap_load(sc->sc_datadmat, ccb->ccb_dmamap, 3281 ccb->ccb_data, ccb->ccb_len, NULL, flags); 3282 if (error) { 3283 if (error == EFBIG) 3284 aprint_error_dev(sc->sc_dev, "more than %d dma segs\n", 3285 sc->sc_max_sgl); 3286 else 3287 aprint_error_dev(sc->sc_dev, 3288 "error %d loading dma map\n", error); 3289 return -1; 3290 } 3291 3292 io_req = ccb->ccb_tb_io_request; 3293 sgl_ptr = &io_req->SGL.IeeeChain.Chain64; 3294 sge_count = ccb->ccb_dmamap->dm_nsegs; 3295 sgd = ccb->ccb_dmamap->dm_segs; 3296 KASSERT(sge_count <= sc->sc_max_sgl); 3297 KASSERT(sge_count <= 3298 (MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG - 1 + 3299 MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG)); 3300 3301 if (sge_count > MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG) { 3302 /* One element to store the chain info */ 3303 sge_idx = MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG - 1; 3304 DNPRINTF(MFI_D_DMA, 3305 "mfi sge_idx %d sge_count %d io_req paddr 0x%" PRIx64 "\n", 3306 sge_idx, sge_count, ccb->ccb_tb_pio_request); 3307 } else { 3308 sge_idx = sge_count; 3309 } 3310 3311 for (i = 0; i < sge_idx; i++) { 3312 sgl_ptr->Address = htole64(sgd[i].ds_addr); 3313 sgl_ptr->Length = htole32(sgd[i].ds_len); 3314 sgl_ptr->Flags = 0; 3315 if (sge_idx < sge_count) { 3316 DNPRINTF(MFI_D_DMA, 3317 "sgl %p %d 0x%" PRIx64 " len 0x%" PRIx32 3318 " flags 0x%x\n", sgl_ptr, i, 3319 sgl_ptr->Address, sgl_ptr->Length, 3320 sgl_ptr->Flags); 3321 } 3322 sgl_ptr++; 3323 } 3324 io_req->ChainOffset = 0; 3325 if (sge_idx < sge_count) { 3326 struct mpi25_ieee_sge_chain64 *sg_chain; 3327 io_req->ChainOffset = MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG; 3328 sg_chain = sgl_ptr; 3329 /* Prepare chain element */ 3330 sg_chain->NextChainOffset = 0; 3331 sg_chain->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3332 MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR); 3333 sg_chain->Length = (sizeof(mpi2_sge_io_union) * 3334 (sge_count - sge_idx)); 3335 sg_chain->Address = ccb->ccb_tb_psg_frame; 3336 DNPRINTF(MFI_D_DMA, 3337 "sgl %p chain 0x%" PRIx64 " len 0x%" PRIx32 3338 " flags 0x%x\n", sg_chain, sg_chain->Address, 3339 sg_chain->Length, sg_chain->Flags); 3340 sgl_ptr = &ccb->ccb_tb_sg_frame->IeeeChain.Chain64; 3341 for (; i < sge_count; i++) { 3342 sgl_ptr->Address = htole64(sgd[i].ds_addr); 3343 sgl_ptr->Length = htole32(sgd[i].ds_len); 3344 sgl_ptr->Flags = 0; 3345 DNPRINTF(MFI_D_DMA, 3346 "sgl %p %d 0x%" PRIx64 " len 0x%" PRIx32 3347 " flags 0x%x\n", sgl_ptr, i, sgl_ptr->Address, 3348 sgl_ptr->Length, sgl_ptr->Flags); 3349 sgl_ptr++; 3350 } 3351 bus_dmamap_sync(sc->sc_dmat, 3352 MFIMEM_MAP(sc->sc_tbolt_reqmsgpool), 3353 ccb->ccb_tb_psg_frame - MFIMEM_DVA(sc->sc_tbolt_reqmsgpool), 3354 MEGASAS_MAX_SZ_CHAIN_FRAME, BUS_DMASYNC_PREREAD); 3355 } 3356 3357 if (ccb->ccb_direction == MFI_DATA_IN) { 3358 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 3359 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3360 } else { 3361 bus_dmamap_sync(sc->sc_datadmat, ccb->ccb_dmamap, 0, 3362 ccb->ccb_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3363 } 3364 return sge_count; 3365 } 3366 3367 /* 3368 * The ThunderBolt HW has an option for the driver to directly 3369 * access the underlying disks and operate on the RAID. To 3370 * do this there needs to be a capability to keep the RAID controller 3371 * and driver in sync. The FreeBSD driver does not take advantage 3372 * of this feature since it adds a lot of complexity and slows down 3373 * performance. Performance is gained by using the controller's 3374 * cache etc. 3375 * 3376 * Even though this driver doesn't access the disks directly, an 3377 * AEN like command is used to inform the RAID firmware to "sync" 3378 * with all LD's via the MFI_DCMD_LD_MAP_GET_INFO command. This 3379 * command in write mode will return when the RAID firmware has 3380 * detected a change to the RAID state. Examples of this type 3381 * of change are removing a disk. Once the command returns then 3382 * the driver needs to acknowledge this and "sync" all LD's again. 3383 * This repeats until we shutdown. Then we need to cancel this 3384 * pending command. 3385 * 3386 * If this is not done right the RAID firmware will not remove a 3387 * pulled drive and the RAID won't go degraded etc. Effectively, 3388 * stopping any RAID mangement to functions. 3389 * 3390 * Doing another LD sync, requires the use of an event since the 3391 * driver needs to do a mfi_wait_command and can't do that in an 3392 * interrupt thread. 3393 * 3394 * The driver could get the RAID state via the MFI_DCMD_LD_MAP_GET_INFO 3395 * That requires a bunch of structure and it is simplier to just do 3396 * the MFI_DCMD_LD_GET_LIST versus walking the RAID map. 3397 */ 3398 3399 void 3400 mfi_tbolt_sync_map_info(struct work *w, void *v) 3401 { 3402 struct mfi_softc *sc = v; 3403 int i; 3404 struct mfi_ccb *ccb = NULL; 3405 uint8_t mbox[MFI_MBOX_SIZE]; 3406 struct mfi_ld *ld_sync = NULL; 3407 size_t ld_size; 3408 int s; 3409 3410 DNPRINTF(MFI_D_SYNC, "%s: mfi_tbolt_sync_map_info\n", DEVNAME(sc)); 3411 again: 3412 s = splbio(); 3413 if (sc->sc_ldsync_ccb != NULL) { 3414 splx(s); 3415 return; 3416 } 3417 3418 if (mfi_mgmt_internal(sc, MR_DCMD_LD_GET_LIST, MFI_DATA_IN, 3419 sizeof(sc->sc_ld_list), &sc->sc_ld_list, NULL, false)) { 3420 aprint_error_dev(sc->sc_dev, "MR_DCMD_LD_GET_LIST failed\n"); 3421 goto err; 3422 } 3423 3424 ld_size = sizeof(*ld_sync) * sc->sc_ld_list.mll_no_ld; 3425 3426 ld_sync = (struct mfi_ld *) malloc(ld_size, M_DEVBUF, 3427 M_WAITOK | M_ZERO); 3428 if (ld_sync == NULL) { 3429 aprint_error_dev(sc->sc_dev, "Failed to allocate sync\n"); 3430 goto err; 3431 } 3432 for (i = 0; i < sc->sc_ld_list.mll_no_ld; i++) { 3433 ld_sync[i] = sc->sc_ld_list.mll_list[i].mll_ld; 3434 } 3435 3436 if ((ccb = mfi_get_ccb(sc)) == NULL) { 3437 aprint_error_dev(sc->sc_dev, "Failed to get sync command\n"); 3438 free(ld_sync, M_DEVBUF); 3439 goto err; 3440 } 3441 sc->sc_ldsync_ccb = ccb; 3442 3443 memset(mbox, 0, MFI_MBOX_SIZE); 3444 mbox[0] = sc->sc_ld_list.mll_no_ld; 3445 mbox[1] = MFI_DCMD_MBOX_PEND_FLAG; 3446 if (mfi_mgmt(ccb, NULL, MR_DCMD_LD_MAP_GET_INFO, MFI_DATA_OUT, 3447 ld_size, ld_sync, mbox)) { 3448 aprint_error_dev(sc->sc_dev, "Failed to create sync command\n"); 3449 goto err; 3450 } 3451 /* 3452 * we won't sleep on this command, so we have to override 3453 * the callback set up by mfi_mgmt() 3454 */ 3455 ccb->ccb_done = mfi_sync_map_complete; 3456 3457 mfi_post(sc, ccb); 3458 splx(s); 3459 return; 3460 3461 err: 3462 if (ld_sync) 3463 free(ld_sync, M_DEVBUF); 3464 if (ccb) 3465 mfi_put_ccb(ccb); 3466 sc->sc_ldsync_ccb = NULL; 3467 splx(s); 3468 kpause("ldsyncp", 0, hz, NULL); 3469 goto again; 3470 } 3471 3472 static void 3473 mfi_sync_map_complete(struct mfi_ccb *ccb) 3474 { 3475 struct mfi_softc *sc = ccb->ccb_sc; 3476 bool aborted = !sc->sc_running; 3477 3478 DNPRINTF(MFI_D_SYNC, "%s: mfi_sync_map_complete\n", 3479 DEVNAME(ccb->ccb_sc)); 3480 KASSERT(sc->sc_ldsync_ccb == ccb); 3481 mfi_mgmt_done(ccb); 3482 free(ccb->ccb_data, M_DEVBUF); 3483 if (ccb->ccb_flags & MFI_CCB_F_ERR) { 3484 aprint_error_dev(sc->sc_dev, "sync command failed\n"); 3485 aborted = true; 3486 } 3487 mfi_put_ccb(ccb); 3488 sc->sc_ldsync_ccb = NULL; 3489 3490 /* set it up again so the driver can catch more events */ 3491 if (!aborted) { 3492 workqueue_enqueue(sc->sc_ldsync_wq, &sc->sc_ldsync_wk, NULL); 3493 } 3494 } 3495 3496 static int 3497 mfifopen(dev_t dev, int flag, int mode, struct lwp *l) 3498 { 3499 struct mfi_softc *sc; 3500 3501 if ((sc = device_lookup_private(&mfi_cd, minor(dev))) == NULL) 3502 return (ENXIO); 3503 return (0); 3504 } 3505 3506 static int 3507 mfifclose(dev_t dev, int flag, int mode, struct lwp *l) 3508 { 3509 return (0); 3510 } 3511 3512 static int 3513 mfifioctl(dev_t dev, u_long cmd, void *data, int flag, 3514 struct lwp *l) 3515 { 3516 struct mfi_softc *sc; 3517 struct mfi_ioc_packet *ioc = data; 3518 uint8_t *udata; 3519 struct mfi_ccb *ccb = NULL; 3520 int ctx, i, s, error; 3521 union mfi_sense_ptr sense_ptr; 3522 3523 switch(cmd) { 3524 case MFI_CMD: 3525 sc = device_lookup_private(&mfi_cd, ioc->mfi_adapter_no); 3526 break; 3527 default: 3528 return ENOTTY; 3529 } 3530 if (sc == NULL) 3531 return (ENXIO); 3532 if (sc->sc_opened) 3533 return (EBUSY); 3534 3535 switch(cmd) { 3536 case MFI_CMD: 3537 error = kauth_authorize_device_passthru(l->l_cred, dev, 3538 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 3539 if (error) 3540 return error; 3541 if (ioc->mfi_sge_count > MAX_IOCTL_SGE) 3542 return EINVAL; 3543 s = splbio(); 3544 if ((ccb = mfi_get_ccb(sc)) == NULL) 3545 return ENOMEM; 3546 ccb->ccb_data = NULL; 3547 ctx = ccb->ccb_frame->mfr_header.mfh_context; 3548 memcpy(ccb->ccb_frame, ioc->mfi_frame.raw, 3549 sizeof(*ccb->ccb_frame)); 3550 ccb->ccb_frame->mfr_header.mfh_context = ctx; 3551 ccb->ccb_frame->mfr_header.mfh_scsi_status = 0; 3552 ccb->ccb_frame->mfr_header.mfh_pad0 = 0; 3553 ccb->ccb_frame_size = 3554 (sizeof(union mfi_sgl) * ioc->mfi_sge_count) + 3555 ioc->mfi_sgl_off; 3556 if (ioc->mfi_sge_count > 0) { 3557 ccb->ccb_sgl = (union mfi_sgl *) 3558 &ccb->ccb_frame->mfr_bytes[ioc->mfi_sgl_off]; 3559 } 3560 if (ccb->ccb_frame->mfr_header.mfh_flags & MFI_FRAME_DIR_READ) 3561 ccb->ccb_direction = MFI_DATA_IN; 3562 if (ccb->ccb_frame->mfr_header.mfh_flags & MFI_FRAME_DIR_WRITE) 3563 ccb->ccb_direction = MFI_DATA_OUT; 3564 ccb->ccb_len = ccb->ccb_frame->mfr_header.mfh_data_len; 3565 if (ccb->ccb_len > MAXPHYS) { 3566 error = ENOMEM; 3567 goto out; 3568 } 3569 if (ccb->ccb_len && 3570 (ccb->ccb_direction & (MFI_DATA_IN | MFI_DATA_OUT)) != 0) { 3571 udata = malloc(ccb->ccb_len, M_DEVBUF, M_WAITOK|M_ZERO); 3572 if (udata == NULL) { 3573 error = ENOMEM; 3574 goto out; 3575 } 3576 ccb->ccb_data = udata; 3577 if (ccb->ccb_direction & MFI_DATA_OUT) { 3578 for (i = 0; i < ioc->mfi_sge_count; i++) { 3579 error = copyin(ioc->mfi_sgl[i].iov_base, 3580 udata, ioc->mfi_sgl[i].iov_len); 3581 if (error) 3582 goto out; 3583 udata = &udata[ 3584 ioc->mfi_sgl[i].iov_len]; 3585 } 3586 } 3587 if (mfi_create_sgl(ccb, BUS_DMA_WAITOK)) { 3588 error = EIO; 3589 goto out; 3590 } 3591 } 3592 if (ccb->ccb_frame->mfr_header.mfh_cmd == MFI_CMD_PD_SCSI_IO) { 3593 ccb->ccb_frame->mfr_io.mif_sense_addr_lo = 3594 htole32(ccb->ccb_psense); 3595 ccb->ccb_frame->mfr_io.mif_sense_addr_hi = 0; 3596 } 3597 ccb->ccb_done = mfi_mgmt_done; 3598 mfi_post(sc, ccb); 3599 while (ccb->ccb_state != MFI_CCB_DONE) 3600 tsleep(ccb, PRIBIO, "mfi_fioc", 0); 3601 3602 if (ccb->ccb_direction & MFI_DATA_IN) { 3603 udata = ccb->ccb_data; 3604 for (i = 0; i < ioc->mfi_sge_count; i++) { 3605 error = copyout(udata, 3606 ioc->mfi_sgl[i].iov_base, 3607 ioc->mfi_sgl[i].iov_len); 3608 if (error) 3609 goto out; 3610 udata = &udata[ 3611 ioc->mfi_sgl[i].iov_len]; 3612 } 3613 } 3614 if (ioc->mfi_sense_len) { 3615 memcpy(&sense_ptr.sense_ptr_data[0], 3616 &ioc->mfi_frame.raw[ioc->mfi_sense_off], 3617 sizeof(sense_ptr.sense_ptr_data)); 3618 error = copyout(ccb->ccb_sense, 3619 sense_ptr.user_space, 3620 sizeof(sense_ptr.sense_ptr_data)); 3621 if (error) 3622 goto out; 3623 } 3624 memcpy(ioc->mfi_frame.raw, ccb->ccb_frame, 3625 sizeof(*ccb->ccb_frame)); 3626 break; 3627 default: 3628 printf("mfifioctl unhandled cmd 0x%lx\n", cmd); 3629 return ENOTTY; 3630 } 3631 3632 out: 3633 if (ccb->ccb_data) 3634 free(ccb->ccb_data, M_DEVBUF); 3635 if (ccb) 3636 mfi_put_ccb(ccb); 3637 splx(s); 3638 return error; 3639 } 3640
Indexes created Fri Sep 26 20:09:58 GMT 2025