mfireg.h revision 1.19
1 /* $NetBSD: mfireg.h,v 1.19 2022/05/12 11:56:29 msaitoh Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Copyright (c) 2007 LSI Corp. 21 * Copyright (c) 2007 Rajesh Prabhakaran. 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 #ifndef _DEV_IC_MFIREG_H_ 47 #define _DEV_IC_MFIREG_H_ 48 49 /* management interface constants */ 50 #define MFI_MGMT_VD 0x01 51 #define MFI_MGMT_SD 0x02 52 53 /* generic constants */ 54 #define MFI_FRAME_SIZE 64 55 #define MFI_SENSE_SIZE 128 56 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 57 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 58 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 59 #define MFI_INVALID_CTX 0xffffffff 60 #define MFI_ENABLE_INTR 0x01 61 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 62 #define MFI_SECTOR_LEN 512 63 64 /* register offsets */ 65 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 66 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 67 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 68 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 69 #define MFI_IDB 0x20 /* inbound doorbell */ 70 #define MFI_ISTS 0x24 /* inbound intr stat */ 71 #define MFI_IMSK 0x28 /* inbound intr mask */ 72 #define MFI_ODB 0x2c /* outbound doorbell */ 73 #define MFI_OSTS 0x30 /* outbound intr stat */ 74 #define MFI_OMSK 0x34 /* outbound inter mask */ 75 #define MFI_IQP 0x40 /* inbound queue port */ 76 #define MFI_OQP 0x44 /* outbound queue port */ 77 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 78 #define MFI_OSP 0xb0 /* outbound scratch pad */ 79 80 /* ThunderBolt specific Register */ 81 #define MFI_RPI 0x6c /* reply_post_host_index */ 82 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 83 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 84 85 /* OCR registers */ 86 #define MFI_WSR 0x004 /* write sequence register */ 87 #define MFI_HDR 0x008 /* host diagnostic register */ 88 #define MFI_RSR 0x3c3 /* Reset Status Register */ 89 90 /* OCR specific flags */ 91 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 92 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 93 94 /* 95 * skinny specific changes 96 */ 97 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 98 #define MFI_IQPL 0x000000c0 99 #define MFI_IQPH 0x000000c4 100 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 101 102 /* * firmware states */ 103 #define MFI_STATE_MASK 0xf0000000 104 #define MFI_STATE_UNDEFINED 0x00000000 105 #define MFI_STATE_BB_INIT 0x10000000 106 #define MFI_STATE_FW_INIT 0x40000000 107 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 108 #define MFI_STATE_FW_INIT_2 0x70000000 109 #define MFI_STATE_DEVICE_SCAN 0x80000000 110 #define MFI_STATE_FLUSH_CACHE 0xa0000000 111 #define MFI_STATE_READY 0xb0000000 112 #define MFI_STATE_OPERATIONAL 0xc0000000 113 #define MFI_STATE_FAULT 0xf0000000 114 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 115 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 116 #define MFI_STATE_HOSTMEMREQD_MASK 0x08000000 117 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 118 #define MFI_RESET_REQUIRED 0x00000001 119 120 /* ThunderBolt Support */ 121 #define MFI_STATE_TB_MASK 0xf0000000 122 #define MFI_STATE_TB_RESET 0x00000000 123 #define MFI_STATE_TB_READY 0x10000000 124 #define MFI_STATE_TB_OPERATIONAL 0x20000000 125 #define MFI_STATE_TB_FAULT 0x40000000 126 127 /* command reset register */ 128 #define MFI_INIT_ABORT 0x00000001 129 #define MFI_INIT_READY 0x00000002 130 #define MFI_INIT_MFIMODE 0x00000004 131 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 132 #define MFI_RESET_FLAGS MFI_INIT_READY | MFI_INIT_MFIMODE | \ 133 MFI_INIT_ABORT 134 #define MFI_INIT_HOTPLUG 0x00000010 135 136 /* ADP reset flags */ 137 #define MFI_STOP_ADP 0x00000020 138 #define MFI_ADP_RESET 0x00000040 139 #define DIAG_WRITE_ENABLE 0x00000080 140 #define DIAG_RESET_ADAPTER 0x00000004 141 142 /* mfi Frame flags */ 143 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 144 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 145 #define MFI_FRAME_SGL32 0x0000 146 #define MFI_FRAME_SGL64 0x0002 147 #define MFI_FRAME_SENSE32 0x0000 148 #define MFI_FRAME_SENSE64 0x0004 149 #define MFI_FRAME_DIR_NONE 0x0000 150 #define MFI_FRAME_DIR_WRITE 0x0008 151 #define MFI_FRAME_DIR_READ 0x0010 152 #define MFI_FRAME_DIR_BOTH 0x0018 153 #define MFI_FRAME_IEEE_SGL 0x0020 154 155 /* ThunderBolt Specific */ 156 157 /* 158 * Pre-TB command size and TB command size. 159 * We will be checking it at the load time for the time being 160 */ 161 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 162 163 #define MEGASAS_THUNDERBOLT_MSG_ALIGNMENT 256 164 /* 165 * We are defining only 128 byte message to reduce memory move over head 166 * and also it will reduce the SRB extension size by 128byte compared with 167 * 256 message size 168 */ 169 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 170 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 171 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 172 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 173 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 174 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 175 176 /* 177 * Calculating how many SGEs allowed in an allocated main message 178 * (size of the Message - Raid SCSI IO message size(except SGE)) 179 * / size of SGE 180 * (0x100 - (0x90 - 0x10)) / 0x10 = 8 181 */ 182 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG \ 183 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - \ 184 (sizeof(struct mfi_mpi2_request_raid_scsi_io) - sizeof(mpi2_sge_io_union))\ 185 ) / sizeof(mpi2_sge_io_union)) 186 187 /* 188 * (Command frame size allocated in SRB ext - Raid SCSI IO message size) 189 * / size of SGL ; 190 * (1280 - 256) / 16 = 64 191 */ 192 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG \ 193 ((MR_COMMAND_SIZE - MEGASAS_THUNDERBOLT_NEW_MSG_SIZE) / \ 194 sizeof(mpi2_sge_io_union)) 195 196 /* 197 * This is the offset in number of 4 * 32bit words to the next chain 198 * (0x100 - 0x10)/0x10 = 0xF(15) 199 */ 200 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG \ 201 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - sizeof(mpi2_sge_io_union)) / 16) 202 203 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MPT_PTMSG \ 204 (offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16) 205 206 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 207 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 208 209 #define MR_INTERNAL_MFI_FRAMES_SMID 1 210 #define MR_CTRL_EVENT_WAIT_SMID 2 211 #define MR_INTERNAL_DRIVER_RESET_SMID 3 212 213 /* mfi command opcodes */ 214 #define MFI_CMD_INIT 0x00 215 #define MFI_CMD_LD_READ 0x01 216 #define MFI_CMD_LD_WRITE 0x02 217 #define MFI_CMD_LD_SCSI_IO 0x03 218 #define MFI_CMD_PD_SCSI_IO 0x04 219 #define MFI_CMD_DCMD 0x05 220 #define MFI_CMD_ABORT 0x06 221 #define MFI_CMD_SMP 0x07 222 #define MFI_CMD_STP 0x08 223 224 /* direct commands */ 225 #define MR_DCMD_CTRL_GET_INFO 0x01010000 226 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 227 #define MR_FLUSH_CTRL_CACHE 0x01 228 #define MR_FLUSH_DISK_CACHE 0x02 229 #define MR_DCMD_CTRL_HOST_MEM_ALLOC 0x0100e100 230 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 231 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 232 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 233 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 234 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 235 #define MR_DCMD_PD_GET_LIST 0x02010000 236 #define MR_DCMD_PD_LIST_QUERY 0x02010100 237 #define MR_DCMD_PD_GET_INFO 0x02020000 238 #define MR_DCMD_PD_SET_STATE 0x02030100 239 #define MR_DCMD_PD_REBUILD 0x02040100 240 #define MR_DCMD_PD_BLINK 0x02070100 241 #define MR_DCMD_PD_UNBLINK 0x02070200 242 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 243 #define MR_DCMD_LD_SYNC 0x0300e102 244 #define MR_DCMD_LD_GET_LIST 0x03010000 245 #define MR_DCMD_LD_GET_INFO 0x03020000 246 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 247 #define MR_DCMD_CONF_GET 0x04010000 248 #define MR_DCMD_CFG_ADD 0x04020000 249 #define MR_DCMD_CFG_CLEAR 0x04030000 250 #define MR_DCMD_CFG_MAKE_SPARE 0x04040000 251 #define MR_DCMD_CFG_FOREIGN_SCAN 0x04060100 252 #define MR_DCMD_CFG_FOREIGN_CLEAR 0x04060500 253 #define MR_DCMD_BBU_GET_STATUS 0x05010000 254 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 255 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 256 #define MR_DCMD_CLUSTER 0x08000000 257 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 258 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 259 260 #define MR_DCMD_SPEAKER_GET 0x01030100 261 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 262 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 263 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 264 #define MR_DCMD_SPEAKER_TEST 0x01030500 265 266 /* mailbox bytes in direct command */ 267 #define MFI_MBOX_SIZE 12 268 269 union mfi_mbox { 270 uint8_t b[MFI_MBOX_SIZE]; 271 uint16_t s[6]; 272 uint32_t w[3]; 273 }; 274 275 /* mfi completion codes */ 276 typedef enum { 277 MFI_STAT_OK = 0x00, 278 MFI_STAT_INVALID_CMD = 0x01, 279 MFI_STAT_INVALID_DCMD = 0x02, 280 MFI_STAT_INVALID_PARAMETER = 0x03, 281 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 282 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 283 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 284 MFI_STAT_APP_IN_USE = 0x07, 285 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 286 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 287 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 288 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 289 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 290 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 291 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 292 MFI_STAT_FLASH_BUSY = 0x0f, 293 MFI_STAT_FLASH_ERROR = 0x10, 294 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 295 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 296 MFI_STAT_FLASH_NOT_OPEN = 0x13, 297 MFI_STAT_FLASH_NOT_STARTED = 0x14, 298 MFI_STAT_FLUSH_FAILED = 0x15, 299 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 300 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 301 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 302 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 303 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 304 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 305 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 306 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 307 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 308 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 309 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 310 MFI_STAT_MFC_HW_ERROR = 0x21, 311 MFI_STAT_NO_HW_PRESENT = 0x22, 312 MFI_STAT_NOT_FOUND = 0x23, 313 MFI_STAT_NOT_IN_ENCL = 0x24, 314 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 315 MFI_STAT_PD_TYPE_WRONG = 0x26, 316 MFI_STAT_PR_DISABLED = 0x27, 317 MFI_STAT_ROW_INDEX_INVALID = 0x28, 318 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 319 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 320 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 321 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 322 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 323 MFI_STAT_SCSI_IO_FAILED = 0x2e, 324 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 325 MFI_STAT_SHUTDOWN_FAILED = 0x30, 326 MFI_STAT_TIME_NOT_SET = 0x31, 327 MFI_STAT_WRONG_STATE = 0x32, 328 MFI_STAT_LD_OFFLINE = 0x33, 329 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 330 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 331 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 332 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 333 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 334 MFI_STAT_INVALID_STATUS = 0xff 335 } mfi_status_t; 336 337 typedef enum { 338 MFI_EVT_CLASS_DEBUG = -2, 339 MFI_EVT_CLASS_PROGRESS = -1, 340 MFI_EVT_CLASS_INFO = 0, 341 MFI_EVT_CLASS_WARNING = 1, 342 MFI_EVT_CLASS_CRITICAL = 2, 343 MFI_EVT_CLASS_FATAL = 3, 344 MFI_EVT_CLASS_DEAD = 4 345 } mfi_evt_class_t; 346 347 typedef enum { 348 MFI_EVT_LOCALE_LD = 0x0001, 349 MFI_EVT_LOCALE_PD = 0x0002, 350 MFI_EVT_LOCALE_ENCL = 0x0004, 351 MFI_EVT_LOCALE_BBU = 0x0008, 352 MFI_EVT_LOCALE_SAS = 0x0010, 353 MFI_EVT_LOCALE_CTRL = 0x0020, 354 MFI_EVT_LOCALE_CONFIG = 0x0040, 355 MFI_EVT_LOCALE_CLUSTER = 0x0080, 356 MFI_EVT_LOCALE_ALL = 0xffff 357 } mfi_evt_locale_t; 358 359 typedef enum { 360 MR_EVT_ARGS_NONE = 0x00, 361 MR_EVT_ARGS_CDB_SENSE, 362 MR_EVT_ARGS_LD, 363 MR_EVT_ARGS_LD_COUNT, 364 MR_EVT_ARGS_LD_LBA, 365 MR_EVT_ARGS_LD_OWNER, 366 MR_EVT_ARGS_LD_LBA_PD_LBA, 367 MR_EVT_ARGS_LD_PROG, 368 MR_EVT_ARGS_LD_STATE, 369 MR_EVT_ARGS_LD_STRIP, 370 MR_EVT_ARGS_PD, 371 MR_EVT_ARGS_PD_ERR, 372 MR_EVT_ARGS_PD_LBA, 373 MR_EVT_ARGS_PD_LBA_LD, 374 MR_EVT_ARGS_PD_PROG, 375 MR_EVT_ARGS_PD_STATE, 376 MR_EVT_ARGS_PCI, 377 MR_EVT_ARGS_RATE, 378 MR_EVT_ARGS_STR, 379 MR_EVT_ARGS_TIME, 380 MR_EVT_ARGS_ECC 381 } mfi_evt_args; 382 383 /* XXX should be in mfi_evt_args ? */ 384 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 385 #define MR_EVT_ARGS_PD_ADDRESS 0x1d 386 #define MR_EVT_PD_INSERTED 0x005b 387 #define MR_EVT_PD_REMOVED 0x0070 388 #define MR_EVT_PD_STATE_CHANGE 0x0072 389 #define MR_EVT_LD_CHANGE 0x0051 390 #define MR_EVT_LD_CREATED 0x008a 391 #define MR_EVT_LD_DELETED 0x008b 392 #define MR_EVT_PD_REMOVED_EXT 0x00f8 393 #define MR_EVT_PD_INSERTED_EXT 0x00f7 394 395 396 397 typedef enum { 398 MR_PD_QUERY_TYPE_ALL = 0, 399 MR_PD_QUERY_TYPE_STATE = 1, 400 MR_PD_QUERY_TYPE_POWER_STATE = 2, 401 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 402 MR_PD_QUERY_TYPE_SPEED = 4, 403 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 404 } mfi_pd_query_type; 405 406 /* driver definitions */ 407 #define MFI_MAX_PD_CHANNELS 2 408 #define MFI_MAX_PD_ARRAY 32 409 #define MFI_MAX_LD_CHANNELS 2 410 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 411 #define MFI_MAX_CHANNEL_DEVS 128 412 #define MFI_DEFAULT_ID -1 413 #define MFI_MAX_LUN 8 414 #define MFI_MAX_LD 64 415 #define MFI_MAX_SPAN 8 416 #define MFI_MAX_ARRAY_DEDICATED 16 417 418 /* sense buffer */ 419 struct mfi_sense { 420 uint8_t mse_data[MFI_SENSE_SIZE]; 421 }; 422 423 /* scatter gather elements */ 424 struct mfi_sg32 { 425 uint32_t addr; 426 uint32_t len; 427 }; 428 429 struct mfi_sg64 { 430 uint64_t addr; 431 uint32_t len; 432 } __packed; 433 434 struct mfi_sg_ieee { 435 uint64_t addr; 436 uint32_t len; 437 uint32_t flags; 438 }; 439 440 441 union mfi_sgl { 442 struct mfi_sg32 sg32[1]; 443 struct mfi_sg64 sg64[1]; 444 struct mfi_sg_ieee sg_ieee[1]; 445 }; 446 447 /* message frame */ 448 struct mfi_frame_header { 449 uint8_t mfh_cmd; 450 uint8_t mfh_sense_len; 451 uint8_t mfh_cmd_status; 452 uint8_t mfh_scsi_status; 453 uint8_t mfh_target_id; 454 uint8_t mfh_lun_id; 455 uint8_t mfh_cdb_len; 456 uint8_t mfh_sg_count; 457 uint32_t mfh_context; 458 uint32_t mfh_pad0; 459 uint16_t mfh_flags; 460 uint16_t mfh_timeout; 461 uint32_t mfh_data_len; 462 }; 463 464 union mfi_sgl_frame { 465 struct mfi_sg32 sge32[8]; 466 struct mfi_sg64 sge64[5]; 467 468 } __packed; 469 470 struct mfi_init_frame { 471 struct mfi_frame_header mif_header; 472 uint32_t mif_qinfo_new_addr_lo; 473 uint32_t mif_qinfo_new_addr_hi; 474 uint32_t mif_qinfo_old_addr_lo; 475 uint32_t mif_qinfo_old_addr_hi; 476 uint32_t driver_ver_lo; /* 0x28 */ 477 uint32_t driver_ver_hi; /* 0x2c */ 478 uint32_t reserved[4]; 479 } __packed; 480 481 /* queue init structure */ 482 struct mfi_init_qinfo { 483 uint32_t miq_flags; 484 uint32_t miq_rq_entries; 485 uint32_t miq_rq_addr_lo; 486 uint32_t miq_rq_addr_hi; 487 uint32_t miq_pi_addr_lo; 488 uint32_t miq_pi_addr_hi; 489 uint32_t miq_ci_addr_lo; 490 uint32_t miq_ci_addr_hi; 491 } __packed; 492 493 #define MFI_IO_FRAME_SIZE 40 494 struct mfi_io_frame { 495 struct mfi_frame_header mif_header; 496 uint32_t mif_sense_addr_lo; 497 uint32_t mif_sense_addr_hi; 498 uint32_t mif_lba_lo; 499 uint32_t mif_lba_hi; 500 union mfi_sgl mif_sgl; 501 } __packed; 502 503 #define MFI_PASS_FRAME_SIZE 48 504 struct mfi_pass_frame { 505 struct mfi_frame_header mpf_header; 506 uint32_t mpf_sense_addr_lo; 507 uint32_t mpf_sense_addr_hi; 508 uint8_t mpf_cdb[16]; 509 union mfi_sgl mpf_sgl; 510 } __packed; 511 512 #define MFI_DCMD_FRAME_SIZE 40 513 struct mfi_dcmd_frame { 514 struct mfi_frame_header mdf_header; 515 uint32_t mdf_opcode; 516 union mfi_mbox mdf_mbox; 517 union mfi_sgl mdf_sgl; 518 }; 519 #define MFI_DCMD_MBOX_PEND_FLAG 0x1 520 521 struct mfi_abort_frame { 522 struct mfi_frame_header maf_header; 523 uint32_t maf_abort_context; 524 uint32_t maf_pad; 525 uint32_t maf_abort_mfi_addr_lo; 526 uint32_t maf_abort_mfi_addr_hi; 527 uint32_t maf_reserved[6]; 528 }; 529 530 struct mfi_smp_frame { 531 struct mfi_frame_header msf_header; 532 uint64_t msf_sas_addr; 533 union { 534 struct mfi_sg32 sg32[2]; 535 struct mfi_sg64 sg64[2]; 536 } msf_sgl; 537 } __packed; 538 539 struct mfi_stp_frame { 540 struct mfi_frame_header msf_header; 541 uint16_t msf_fis[10]; 542 uint32_t msf_stp_flags; 543 union { 544 struct mfi_sg32 sg32[2]; 545 struct mfi_sg64 sg64[2]; 546 } msf_sgl; 547 } __packed; 548 549 union mfi_frame { 550 struct mfi_frame_header mfr_header; 551 struct mfi_init_frame mfr_init; 552 struct mfi_io_frame mfr_io; 553 struct mfi_pass_frame mfr_pass; 554 struct mfi_dcmd_frame mfr_dcmd; 555 struct mfi_abort_frame mfr_abort; 556 struct mfi_smp_frame mfr_smp; 557 struct mfi_stp_frame mfr_stp; 558 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 559 }; 560 561 union mfi_evt_class_locale { 562 struct { 563 uint16_t locale; 564 uint8_t reserved; 565 int8_t class; 566 } mec_members; 567 uint32_t mec_word; 568 }; 569 570 struct mfi_evt_log_info { 571 uint32_t mel_newest_seq_num; 572 uint32_t mel_oldest_seq_num; 573 uint32_t mel_clear_seq_num; 574 uint32_t mel_shutdown_seq_num; 575 uint32_t mel_boot_seq_num; 576 }; 577 578 struct mfi_progress { 579 uint16_t mp_progress; 580 uint16_t mp_elapsed_seconds; 581 }; 582 583 struct mfi_evtarg_ld { 584 uint16_t mel_target_id; 585 uint8_t mel_ld_index; 586 uint8_t mel_reserved; 587 }; 588 589 struct mfi_evtarg_pd { 590 uint16_t mep_device_id; 591 uint8_t mep_encl_index; 592 uint8_t mep_slot_number; 593 }; 594 595 struct mfi_evtarg_pd_state { 596 struct mfi_evtarg_pd pd; 597 uint32_t prev_state; 598 uint32_t new_state; 599 }; 600 601 struct mfi_evtarg_pd_address { 602 uint16_t device_id; 603 uint16_t encl_id; 604 605 union { 606 struct { 607 uint8_t encl_index; 608 uint8_t slot_number; 609 } pd_address; 610 struct { 611 uint8_t encl_position; 612 uint8_t encl_connector_index; 613 } encl_address; 614 } address; 615 616 uint8_t scsi_dev_type; 617 618 union { 619 uint8_t port_bitmap; 620 uint8_t port_numbers; 621 } connected; 622 623 uint64_t sas_addr[2]; 624 }; 625 626 struct mfi_evt_detail { 627 uint32_t med_seq_num; 628 uint32_t med_time_stamp; 629 uint32_t med_code; 630 union mfi_evt_class_locale med_cl; 631 uint8_t med_arg_type; 632 uint8_t med_reserved1[15]; 633 634 union { 635 struct { 636 struct mfi_evtarg_pd pd; 637 uint8_t cdb_length; 638 uint8_t sense_length; 639 uint8_t reserved[2]; 640 uint8_t cdb[16]; 641 uint8_t sense[64]; 642 } __packed cdb_sense; 643 644 struct mfi_evtarg_ld ld; 645 646 struct { 647 struct mfi_evtarg_ld ld; 648 uint64_t count; 649 } __packed ld_count; 650 651 struct { 652 uint64_t lba; 653 struct mfi_evtarg_ld ld; 654 } __packed ld_lba; 655 656 struct { 657 struct mfi_evtarg_ld ld; 658 uint32_t prev_owner; 659 uint32_t new_owner; 660 } __packed ld_owner; 661 662 struct { 663 uint64_t ld_lba; 664 uint64_t pd_lba; 665 struct mfi_evtarg_ld ld; 666 struct mfi_evtarg_pd pd; 667 } __packed ld_lba_pd_lba; 668 669 struct { 670 struct mfi_evtarg_ld ld; 671 struct mfi_progress prog; 672 } __packed ld_prog; 673 674 struct { 675 struct mfi_evtarg_ld ld; 676 uint32_t prev_state; 677 uint32_t new_state; 678 } __packed ld_state; 679 680 struct { 681 uint64_t strip; 682 struct mfi_evtarg_ld ld; 683 } __packed ld_strip; 684 685 struct mfi_evtarg_pd pd; 686 687 struct { 688 struct mfi_evtarg_pd pd; 689 uint32_t err; 690 } __packed pd_err; 691 692 struct { 693 uint64_t lba; 694 struct mfi_evtarg_pd pd; 695 } __packed pd_lba; 696 697 struct { 698 uint64_t lba; 699 struct mfi_evtarg_pd pd; 700 struct mfi_evtarg_ld ld; 701 } __packed pd_lba_ld; 702 703 struct { 704 struct mfi_evtarg_pd pd; 705 struct mfi_progress prog; 706 } __packed pd_prog; 707 708 struct mfi_evtarg_pd_state pd_state; 709 710 struct { 711 uint16_t vendor_id; 712 uint16_t device_id; 713 uint16_t subvendor_id; 714 uint16_t subdevice_id; 715 } __packed pci; 716 717 uint32_t rate; 718 char str[96]; 719 720 struct { 721 uint32_t rtc; 722 uint32_t elapsed_seconds; 723 } __packed time; 724 725 struct { 726 uint32_t ecar; 727 uint32_t elog; 728 char str[64]; 729 } __packed ecc; 730 731 struct mfi_evtarg_pd_address pd_address; 732 733 uint8_t b[96]; 734 uint16_t s[48]; 735 uint32_t w[24]; 736 uint64_t d[12]; 737 } args; 738 739 char med_description[128]; 740 } __packed; 741 742 /* controller properties from mfi_ctrl_info */ 743 struct mfi_ctrl_props { 744 uint16_t mcp_seq_num; 745 uint16_t mcp_pred_fail_poll_interval; 746 uint16_t mcp_intr_throttle_cnt; 747 uint16_t mcp_intr_throttle_timeout; 748 uint8_t mcp_rebuild_rate; 749 uint8_t mcp_patrol_read_rate; 750 uint8_t mcp_bgi_rate; 751 uint8_t mcp_cc_rate; 752 uint8_t mcp_recon_rate; 753 uint8_t mcp_cache_flush_interval; 754 uint8_t mcp_spinup_drv_cnt; 755 uint8_t mcp_spinup_delay; 756 uint8_t mcp_cluster_enable; 757 uint8_t mcp_coercion_mode; 758 uint8_t mcp_alarm_enable; 759 uint8_t mcp_disable_auto_rebuild; 760 uint8_t mcp_disable_battery_warn; 761 uint8_t mcp_ecc_bucket_size; 762 uint16_t mcp_ecc_bucket_leak_rate; 763 uint8_t mcp_restore_hotspare_on_insertion; 764 uint8_t mcp_expose_encl_devices; 765 uint8_t maintainPdFailHistory; 766 uint8_t disallowHostRequestReordering; 767 /* set TRUE to abort CC on detecting an inconsistency */ 768 uint8_t abortCCOnError; 769 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 770 uint8_t loadBalanceMode; 771 /* 772 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 773 * h/w mechanism like GPIO pins 774 * 1 - disable auto detect SGPIO, 775 * 2 - disable i2c SEP auto detect 776 * 3 - disable both auto detect 777 */ 778 uint8_t disableAutoDetectBackplane; 779 /* 780 * % of source LD to be reserved for a VDs snapshot in snapshot 781 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 782 */ 783 uint8_t snapVDSpace; 784 785 /* 786 * Add properties that can be controlled by a bit in the following 787 * structure. 788 */ 789 struct { 790 /* set TRUE to disable copyBack (0=copback enabled) */ 791 uint32_t copyBackDisabled :1; 792 uint32_t SMARTerEnabled :1; 793 uint32_t prCorrectUnconfiguredAreas :1; 794 uint32_t useFdeOnly :1; 795 uint32_t disableNCQ :1; 796 uint32_t SSDSMARTerEnabled :1; 797 uint32_t SSDPatrolReadEnabled :1; 798 uint32_t enableSpinDownUnconfigured :1; 799 uint32_t autoEnhancedImport :1; 800 uint32_t enableSecretKeyControl :1; 801 uint32_t disableOnlineCtrlReset :1; 802 uint32_t allowBootWithPinnedCache :1; 803 uint32_t disableSpinDownHS :1; 804 uint32_t enableJBOD :1; 805 uint32_t reserved :18; 806 } OnOffProperties; 807 /* 808 * % of source LD to be reserved for auto snapshot in snapshot 809 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so 810 * on. 811 */ 812 uint8_t autoSnapVDSpace; 813 /* 814 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 815 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 816 */ 817 uint8_t viewSpace; 818 /* # of idle minutes before device is spun down (0=use FW defaults) */ 819 uint16_t spinDownTime; 820 uint8_t reserved[24]; 821 } __packed; 822 823 /* pci info */ 824 struct mfi_info_pci { 825 uint16_t mip_vendor; 826 uint16_t mip_device; 827 uint16_t mip_subvendor; 828 uint16_t mip_subdevice; 829 uint8_t mip_reserved[24]; 830 } __packed; 831 832 /* host interface info */ 833 struct mfi_info_host { 834 uint8_t mih_type; 835 #define MFI_INFO_HOST_PCIX 0x01 836 #define MFI_INFO_HOST_PCIE 0x02 837 #define MFI_INFO_HOST_ISCSI 0x04 838 #define MFI_INFO_HOST_SAS3G 0x08 839 uint8_t mih_reserved[6]; 840 uint8_t mih_port_count; 841 uint64_t mih_port_addr[8]; 842 } __packed; 843 844 /* device interface info */ 845 struct mfi_info_device { 846 uint8_t mid_type; 847 #define MFI_INFO_DEV_SPI 0x01 848 #define MFI_INFO_DEV_SAS3G 0x02 849 #define MFI_INFO_DEV_SATA1 0x04 850 #define MFI_INFO_DEV_SATA3G 0x08 851 uint8_t mid_reserved[6]; 852 uint8_t mid_port_count; 853 uint64_t mid_port_addr[8]; 854 } __packed; 855 856 /* firmware component info */ 857 struct mfi_info_component { 858 char mic_name[8]; 859 char mic_version[32]; 860 char mic_build_date[16]; 861 char mic_build_time[16]; 862 } __packed; 863 864 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 865 struct mfi_ctrl_info { 866 struct mfi_info_pci mci_pci; 867 struct mfi_info_host mci_host; 868 struct mfi_info_device mci_device; 869 870 /* Firmware components that are present and active. */ 871 uint32_t mci_image_check_word; 872 uint32_t mci_image_component_count; 873 struct mfi_info_component mci_image_component[8]; 874 875 /* Firmware components that have been flashed but are inactive */ 876 uint32_t mci_pending_image_component_count; 877 struct mfi_info_component mci_pending_image_component[8]; 878 879 uint8_t mci_max_arms; 880 uint8_t mci_max_spans; 881 uint8_t mci_max_arrays; 882 uint8_t mci_max_lds; 883 char mci_product_name[80]; 884 char mci_serial_number[32]; 885 uint32_t mci_hw_present; 886 #define MFI_INFO_HW_BBU 0x01 887 #define MFI_INFO_HW_ALARM 0x02 888 #define MFI_INFO_HW_NVRAM 0x04 889 #define MFI_INFO_HW_UART 0x08 890 uint32_t mci_current_fw_time; 891 uint16_t mci_max_cmds; 892 uint16_t mci_max_sg_elements; 893 uint32_t mci_max_request_size; 894 uint16_t mci_lds_present; 895 uint16_t mci_lds_degraded; 896 uint16_t mci_lds_offline; 897 uint16_t mci_pd_present; 898 uint16_t mci_pd_disks_present; 899 uint16_t mci_pd_disks_pred_failure; 900 uint16_t mci_pd_disks_failed; 901 uint16_t mci_nvram_size; 902 uint16_t mci_memory_size; 903 uint16_t mci_flash_size; 904 uint16_t mci_ram_correctable_errors; 905 uint16_t mci_ram_uncorrectable_errors; 906 uint8_t mci_cluster_allowed; 907 uint8_t mci_cluster_active; 908 uint16_t mci_max_strips_per_io; 909 910 uint32_t mci_raid_levels; 911 #define MFI_INFO_RAID_0 0x01 912 #define MFI_INFO_RAID_1 0x02 913 #define MFI_INFO_RAID_5 0x04 914 #define MFI_INFO_RAID_1E 0x08 915 #define MFI_INFO_RAID_6 0x10 916 917 uint32_t mci_adapter_ops; 918 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 919 #define MFI_INFO_AOPS_CC_RATE 0x0002 920 #define MFI_INFO_AOPS_BGI_RATE 0x0004 921 #define MFI_INFO_AOPS_RECON_RATE 0x0008 922 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 923 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 924 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 925 #define MFI_INFO_AOPS_BBU 0x0080 926 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 927 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 928 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 929 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 930 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 931 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 932 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 933 934 uint32_t mci_ld_ops; 935 #define MFI_INFO_LDOPS_READ_POLICY 0x01 936 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 937 #define MFI_INFO_LDOPS_IO_POLICY 0x04 938 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 939 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 940 941 struct { 942 uint8_t min; 943 uint8_t max; 944 uint8_t reserved[2]; 945 } __packed mci_stripe_sz_ops; 946 947 uint32_t mci_pd_ops; 948 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 949 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 950 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 951 952 uint32_t mci_pd_mix_support; 953 #define MFI_INFO_PDMIX_SAS 0x01 954 #define MFI_INFO_PDMIX_SATA 0x02 955 #define MFI_INFO_PDMIX_ENCL 0x04 956 #define MFI_INFO_PDMIX_LD 0x08 957 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 958 959 uint8_t mci_ecc_bucket_count; 960 uint8_t mci_reserved2[11]; 961 struct mfi_ctrl_props mci_properties; 962 char mci_package_version[0x60]; 963 uint8_t mci_pad[0x800 - 0x6a0]; 964 } __packed; 965 966 /* logical disk info from MR_DCMD_LD_GET_LIST */ 967 struct mfi_ld { 968 uint8_t mld_target; 969 uint8_t mld_res; 970 uint16_t mld_seq; 971 } __packed; 972 973 struct mfi_ld_list { 974 uint32_t mll_no_ld; 975 uint32_t mll_res; 976 struct { 977 struct mfi_ld mll_ld; 978 uint8_t mll_state; 979 #define MFI_LD_OFFLINE 0x00 980 #define MFI_LD_PART_DEGRADED 0x01 981 #define MFI_LD_DEGRADED 0x02 982 #define MFI_LD_ONLINE 0x03 983 uint8_t mll_res2; 984 uint8_t mll_res3; 985 uint8_t mll_res4; 986 uint64_t mll_size; 987 } mll_list[MFI_MAX_LD]; 988 } __packed; 989 990 /* logical disk details from MR_DCMD_LD_GET_INFO */ 991 struct mfi_ld_prop { 992 struct mfi_ld mlp_ld; 993 char mlp_name[16]; 994 uint8_t mlp_cache_policy; 995 uint8_t mlp_acces_policy; 996 uint8_t mlp_diskcache_policy; 997 uint8_t mlp_cur_cache_policy; 998 uint8_t mlp_disable_bgi; 999 uint8_t mlp_res[7]; 1000 } __packed; 1001 1002 struct mfi_ld_parm { 1003 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 1004 #define MFI_DDF_PRL_RAID0 0x00 1005 #define MFI_DDF_PRL_RAID1 0x01 1006 #define MFI_DDF_PRL_RAID3 0x03 1007 #define MFI_DDF_PRL_RAID4 0x04 1008 #define MFI_DDF_PRL_RAID5 0x05 1009 #define MFI_DDF_PRL_RAID1E 0x11 1010 #define MFI_DDF_PRL_JBOD 0x0f 1011 #define MFI_DDF_PRL_CONCAT 0x1f 1012 #define MFI_DDF_PRL_RAID5E 0x15 1013 #define MFI_DDF_PRL_RAID5EE 0x25 1014 #define MFI_DDF_PRL_RAID6 0x16 1015 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 1016 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 1017 #define MFI_DDF_SRL_STRIPED 0x00 1018 #define MFI_DDF_SRL_MIRRORED 0x01 1019 #define MFI_DDF_SRL_CONCAT 0x02 1020 #define MFI_DDF_SRL_SPANNED 0x03 1021 uint8_t mpa_stripe_size; 1022 uint8_t mpa_no_drv_per_span; 1023 uint8_t mpa_span_depth; 1024 uint8_t mpa_state; 1025 uint8_t mpa_init_state; 1026 uint8_t mpa_is_consistent; 1027 uint8_t mpa_res1[6]; 1028 uint8_t mpa_isSSCD; 1029 uint8_t mpa_res[16]; 1030 } __packed; 1031 1032 struct mfi_ld_span { 1033 uint64_t mls_start_block; 1034 uint64_t mls_no_blocks; 1035 uint16_t mls_index; 1036 uint8_t mls_res[6]; 1037 } __packed; 1038 1039 struct mfi_ld_cfg { 1040 struct mfi_ld_prop mlc_prop; 1041 struct mfi_ld_parm mlc_parm; 1042 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 1043 } __packed; 1044 1045 struct mfi_ld_progress { 1046 uint32_t mlp_in_prog; 1047 #define MFI_LD_PROG_CC 0x01 1048 #define MFI_LD_PROG_BGI 0x02 1049 #define MFI_LD_PROG_FGI 0x04 1050 #define MFI_LD_PROG_RECONSTRUCT 0x08 1051 struct mfi_progress mlp_cc; 1052 struct mfi_progress mlp_bgi; 1053 struct mfi_progress mlp_fgi; 1054 struct mfi_progress mlp_reconstruct; 1055 struct mfi_progress mlp_res[4]; 1056 } __packed; 1057 1058 struct mfi_ld_details { 1059 struct mfi_ld_cfg mld_cfg; 1060 uint64_t mld_size; 1061 struct mfi_ld_progress mld_progress; 1062 uint16_t mld_clust_own_id; 1063 uint8_t mld_res1; 1064 uint8_t mld_res2; 1065 uint8_t mld_inq_page83[64]; 1066 uint8_t mld_res[16]; 1067 } __packed; 1068 1069 /* physical disk info from MR_DCMD_PD_GET_LIST */ 1070 struct mfi_pd_address { 1071 uint16_t mpa_pd_id; 1072 uint16_t mpa_enc_id; 1073 uint8_t mpa_enc_index; 1074 uint8_t mpa_enc_slot; 1075 uint8_t mpa_scsi_type; 1076 uint8_t mpa_port; 1077 uint64_t mpa_sas_address[2]; 1078 } __packed; 1079 1080 #define MFI_MAX_PD 256 1081 struct mfi_pd_list { 1082 uint32_t mpl_size; 1083 uint32_t mpl_no_pd; 1084 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 1085 } __packed; 1086 1087 struct mfi_pd { 1088 uint16_t mfp_id; 1089 uint16_t mfp_seq; 1090 } __packed; 1091 1092 struct mfi_pd_progress { 1093 uint32_t mfp_in_prog; 1094 #define MFI_PD_PROG_RBLD 0x01 1095 #define MFI_PD_PROG_PR 0x02 1096 #define MFI_PD_PROG_CLEAR 0x04 1097 struct mfi_progress mfp_rebuild; 1098 struct mfi_progress mfp_patrol_read; 1099 struct mfi_progress mfp_clear; 1100 struct mfi_progress mfp_res[4]; 1101 } __packed; 1102 1103 struct mfi_pd_details { 1104 struct mfi_pd mpd_pd; 1105 uint8_t mpd_inq_data[96]; 1106 uint8_t mpd_inq_page83[64]; 1107 uint8_t mpd_no_support; 1108 uint8_t mpd_scsi_type; 1109 uint8_t mpd_port; 1110 uint8_t mpd_speed; 1111 uint32_t mpd_mediaerr_cnt; 1112 uint32_t mpd_othererr_cnt; 1113 uint32_t mpd_predfail_cnt; 1114 uint32_t mpd_last_pred_event; 1115 uint16_t mpd_fw_state; 1116 uint8_t mpd_rdy_for_remove; 1117 uint8_t mpd_link_speed; 1118 uint32_t mpd_ddf_state; 1119 #define MFI_DDF_GUID_FORCED 0x01 1120 #define MFI_DDF_PART_OF_VD 0x02 1121 #define MFI_DDF_GLOB_HOTSPARE 0x04 1122 #define MFI_DDF_HOTSPARE 0x08 1123 #define MFI_DDF_FOREIGN 0x10 1124 #define MFI_DDF_TYPE_MASK 0xf000 1125 #define MFI_DDF_TYPE_UNKNOWN 0x0000 1126 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 1127 #define MFI_DDF_TYPE_SAS 0x2000 1128 #define MFI_DDF_TYPE_SATA 0x3000 1129 #define MFI_DDF_TYPE_FC 0x4000 1130 struct { 1131 uint8_t mpp_cnt; 1132 uint8_t mpp_severed; 1133 uint8_t mpp_res[6]; 1134 uint64_t mpp_sas_addr[4]; 1135 } __packed mpd_path; 1136 uint64_t mpd_size; 1137 uint64_t mpd_no_coerce_size; 1138 uint64_t mpd_coerce_size; 1139 uint16_t mpd_enc_id; 1140 uint8_t mpd_enc_idx; 1141 uint8_t mpd_enc_slot; 1142 struct mfi_pd_progress mpd_progress; 1143 uint8_t mpd_bblock_full; 1144 uint8_t mpd_unusable; 1145 uint8_t mpd_res[218]; /* size is 512 */ 1146 } __packed; 1147 1148 /* array configuration from MR_DCMD_CONF_GET */ 1149 struct mfi_array { 1150 uint64_t mar_smallest_pd; 1151 uint8_t mar_no_disk; 1152 uint8_t mar_res1; 1153 uint16_t mar_array_ref; 1154 uint8_t mar_res2[20]; 1155 struct { 1156 struct mfi_pd mar_pd; 1157 uint16_t mar_pd_state; 1158 #define MFI_PD_UNCONFIG_GOOD 0x00 1159 #define MFI_PD_UNCONFIG_BAD 0x01 1160 #define MFI_PD_HOTSPARE 0x02 1161 #define MFI_PD_OFFLINE 0x10 1162 #define MFI_PD_FAILED 0x11 1163 #define MFI_PD_REBUILD 0x14 1164 #define MFI_PD_ONLINE 0x18 1165 #define MFI_PD_COPYBACK 0x20 1166 #define MFI_PD_SYSTEM 0x40 1167 #define MFI_PD_JBOD MFI_PD_SYSTEM 1168 uint8_t mar_enc_pd; 1169 uint8_t mar_enc_slot; 1170 } pd[MFI_MAX_PD_ARRAY]; 1171 } __packed; 1172 1173 /* informations from MR_DCMD_BBU_GET_CAPACITY_INFO */ 1174 struct mfi_bbu_capacity_info { 1175 uint16_t relative_charge; 1176 uint16_t absolute_charge; 1177 uint16_t remaining_capacity; 1178 uint16_t full_charge_capacity; 1179 uint16_t run_time_to_empty; 1180 uint16_t average_time_to_empty; 1181 uint16_t average_time_to_full; 1182 uint16_t cycle_count; 1183 uint16_t max_error; 1184 uint16_t remaining_capacity_alarm; 1185 uint16_t remaining_time_alarm; 1186 uint8_t reserved[26]; 1187 } __packed; 1188 1189 /* informations from MR_DCMD_BBU_GET_DESIGN_INFO */ 1190 struct mfi_bbu_design_info { 1191 uint32_t mfg_date; 1192 uint16_t design_capacity; 1193 uint16_t design_voltage; 1194 uint16_t spec_info; 1195 uint16_t serial_number; 1196 uint16_t pack_stat_config; 1197 uint8_t mfg_name[12]; 1198 uint8_t device_name[8]; 1199 uint8_t device_chemistry[8]; 1200 uint8_t mfg_data[8]; 1201 uint8_t reserved[17]; 1202 } __packed; 1203 1204 struct mfi_ibbu_state { 1205 uint16_t gas_guage_status; 1206 uint16_t relative_charge; 1207 uint16_t charger_system_state; 1208 uint16_t charger_system_ctrl; 1209 uint16_t charging_current; 1210 uint16_t absolute_charge; 1211 uint16_t max_error; 1212 uint8_t reserved[18]; 1213 } __packed; 1214 1215 struct mfi_bbu_state { 1216 uint16_t gas_guage_status; 1217 uint16_t relative_charge; 1218 uint16_t charger_status; 1219 uint16_t remaining_capacity; 1220 uint16_t full_charge_capacity; 1221 uint8_t is_SOH_good; 1222 uint8_t reserved[21]; 1223 } __packed; 1224 1225 union mfi_bbu_status_detail { 1226 struct mfi_ibbu_state ibbu; 1227 struct mfi_bbu_state bbu; 1228 }; 1229 1230 /* informations from MR_DCMD_BBU_GET_STATUS */ 1231 struct mfi_bbu_status { 1232 uint8_t battery_type; 1233 #define MFI_BBU_TYPE_NONE 0 1234 #define MFI_BBU_TYPE_IBBU 1 1235 #define MFI_BBU_TYPE_BBU 2 1236 #define MFI_BBU_TYPE_IBBU09 5 1237 uint8_t reserved; 1238 uint16_t voltage; 1239 int16_t current; 1240 uint16_t temperature; 1241 uint32_t fw_status; 1242 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1243 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1244 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1245 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1246 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1247 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1248 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1249 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1250 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1251 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1252 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1253 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1254 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1255 #define MFI_BBU_STATE_BAD_IBBU ( \ 1256 MFI_BBU_STATE_PACK_MISSING | \ 1257 MFI_BBU_STATE_VOLTAGE_LOW | \ 1258 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1259 MFI_BBU_STATE_LEARN_CYC_REQ | \ 1260 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1261 MFI_BBU_STATE_REPLACE_PACK | \ 1262 MFI_BBU_STATE_CAPACITY_LOW) 1263 #define MFI_BBU_STATE_BAD_BBU ( \ 1264 MFI_BBU_STATE_PACK_MISSING | \ 1265 MFI_BBU_STATE_REPLACE_PACK | \ 1266 MFI_BBU_STATE_CAPACITY_LOW) 1267 uint8_t pad[20]; 1268 union mfi_bbu_status_detail detail; 1269 } __packed; 1270 1271 struct mfi_hotspare { 1272 struct mfi_pd mhs_pd; 1273 uint8_t mhs_type; 1274 #define MFI_PD_HS_DEDICATED 0x01 1275 #define MFI_PD_HS_REVERTIBLE 0x02 1276 #define MFI_PD_HS_ENC_AFFINITY 0x04 1277 uint8_t mhs_res[2]; 1278 uint8_t mhs_array_max; 1279 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1280 } __packed; 1281 1282 struct mfi_conf { 1283 uint32_t mfc_size; 1284 uint16_t mfc_no_array; 1285 uint16_t mfc_array_size; 1286 uint16_t mfc_no_ld; 1287 uint16_t mfc_ld_size; 1288 uint16_t mfc_no_hs; 1289 uint16_t mfc_hs_size; 1290 uint8_t mfc_res[16]; 1291 /* 1292 * XXX this is a ridiculous hack and does not reflect reality 1293 * Structures are actually indexed and therefore need pointer 1294 * math to reach. We need the size of this structure first so 1295 * call it with the size of this structure and then use the returned 1296 * values to allocate memory and do the transfer of the whole structure 1297 * then calculate pointers to each of these structures. 1298 */ 1299 struct mfi_array mfc_array[1]; 1300 struct mfi_ld_cfg mfc_ld[1]; 1301 struct mfi_hotspare mfc_hs[1]; 1302 } __packed; 1303 1304 /* ThunderBolt support */ 1305 1306 /* 1307 * Raid Context structure which describes MegaRAID specific IO Parameters 1308 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1309 */ 1310 typedef struct _mpi2_scsi_io_vendor_unique { 1311 uint16_t resvd0; /* 0x00 - 0x01 */ 1312 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1313 uint8_t regLockFlags; 1314 uint8_t armId; 1315 uint16_t TargetID; /* 0x06 - 0x07 */ 1316 1317 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1318 1319 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1320 1321 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1322 uint8_t exStatus; /* 0x16 */ 1323 uint8_t Status; /* 0x17 status */ 1324 1325 uint8_t RAIDFlags; /* 0x18 */ 1326 uint8_t numSGE; /* 0x19 numSge */ 1327 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1328 uint8_t spanArm; /* 0x1C */ 1329 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1330 } mpi2_scsi_io_vendor_unique, mpi25_scsi_io_vendor_unique; 1331 1332 /***************************************************************************** 1333 * 1334 * Message Functions 1335 * 1336 *****************************************************************************/ 1337 1338 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1339 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1340 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1341 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1342 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1343 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1344 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1345 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1346 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1347 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1348 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1349 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1350 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1351 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1352 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1353 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1354 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1355 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1356 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1357 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1358 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1359 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1360 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1361 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1362 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1363 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1364 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1365 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1366 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1367 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1368 1369 /* Doorbell functions */ 1370 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1371 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1372 1373 /***************************************************************************** 1374 * 1375 * MPI Version Definitions 1376 * 1377 *****************************************************************************/ 1378 1379 #define MPI2_VERSION_MAJOR (0x02) 1380 #define MPI2_VERSION_MINOR (0x00) 1381 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1382 #define MPI2_VERSION_MAJOR_SHIFT (8) 1383 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1384 #define MPI2_VERSION_MINOR_SHIFT (0) 1385 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1386 MPI2_VERSION_MINOR) 1387 1388 #define MPI2_VERSION_02_00 (0x0200) 1389 1390 /* versioning for this MPI header set */ 1391 #define MPI2_HEADER_VERSION_UNIT (0x10) 1392 #define MPI2_HEADER_VERSION_DEV (0x00) 1393 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1394 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1395 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1396 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1397 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1398 MPI2_HEADER_VERSION_DEV) 1399 1400 1401 /* IOCInit Request message */ 1402 struct mpi2_ioc_init_request { 1403 uint8_t WhoInit; /* 0x00 */ 1404 uint8_t Reserved1; /* 0x01 */ 1405 uint8_t ChainOffset; /* 0x02 */ 1406 uint8_t Function; /* 0x03 */ 1407 uint16_t Reserved2; /* 0x04 */ 1408 uint8_t Reserved3; /* 0x06 */ 1409 uint8_t MsgFlags; /* 0x07 */ 1410 uint8_t VP_ID; /* 0x08 */ 1411 uint8_t VF_ID; /* 0x09 */ 1412 uint16_t Reserved4; /* 0x0A */ 1413 uint16_t MsgVersion; /* 0x0C */ 1414 uint16_t HeaderVersion; /* 0x0E */ 1415 uint32_t Reserved5; /* 0x10 */ 1416 uint16_t Reserved6; /* 0x14 */ 1417 uint8_t Reserved7; /* 0x16 */ 1418 uint8_t HostMSIxVectors; /* 0x17 */ 1419 uint16_t Reserved8; /* 0x18 */ 1420 uint16_t SystemRequestFrameSize; /* 0x1A */ 1421 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1422 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1423 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1424 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1425 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1426 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1427 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1428 uint64_t TimeStamp; /* 0x40 */ 1429 }; 1430 1431 /* WhoInit values */ 1432 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1433 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1434 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1435 #define MPI2_WHOINIT_PCI_PEER (0x03) 1436 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1437 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1438 1439 struct mpi2_sge_chain_union { 1440 uint16_t Length; 1441 uint8_t NextChainOffset; 1442 uint8_t Flags; 1443 union { 1444 uint32_t Address32; 1445 uint64_t Address64; 1446 } u; 1447 }; 1448 1449 struct mpi2_ieee_sge_simple32 { 1450 uint32_t Address; 1451 uint32_t FlagsLength; 1452 }; 1453 1454 struct mpi2_ieee_sge_simple64 { 1455 uint64_t Address; 1456 uint32_t Length; 1457 uint16_t Reserved1; 1458 uint8_t Reserved2; 1459 uint8_t Flags; 1460 }; 1461 1462 typedef union _mpi2_ieee_simple_union { 1463 struct mpi2_ieee_sge_simple32 Simple32; 1464 struct mpi2_ieee_sge_simple64 Simple64; 1465 } mpi2_ieee_simple_union; 1466 1467 typedef struct _mpi2_sge_simple_union { 1468 uint32_t FlagsLength; 1469 union { 1470 uint32_t Address32; 1471 uint64_t Address64; 1472 } u; 1473 } mpi2_sge_simple_union; 1474 1475 /* MPI 2.5 SGLs */ 1476 1477 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1478 1479 struct mpi25_ieee_sge_chain64 { 1480 uint64_t Address; 1481 uint32_t Length; 1482 uint16_t Reserved1; 1483 uint8_t NextChainOffset; 1484 uint8_t Flags; 1485 }; 1486 1487 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1488 1489 /**************************************************************************** 1490 * IEEE SGE field definitions and masks 1491 ****************************************************************************/ 1492 1493 /* Flags field bit definitions */ 1494 1495 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1496 1497 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1498 1499 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1500 1501 /* Element Type */ 1502 1503 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1504 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1505 1506 /* Data Location Address Space */ 1507 1508 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1509 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1510 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1511 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1512 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1513 1514 /* Address Size */ 1515 1516 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1517 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1518 1519 /*******************/ 1520 /* SCSI IO Control bits */ 1521 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1522 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1523 1524 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1525 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1526 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1527 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1528 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1529 1530 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1531 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1532 1533 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1534 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1535 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1536 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1537 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1538 1539 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1540 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1541 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1542 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1543 1544 /*******************/ 1545 1546 typedef struct { 1547 uint8_t CDB[20]; /* 0x00 */ 1548 uint32_t PrimaryReferenceTag; /* 0x14 */ 1549 uint16_t PrimaryApplicationTag; /* 0x18 */ 1550 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1551 uint32_t TransferLength; /* 0x1C */ 1552 } mpi2_scsi_io_cdb_eedp32; 1553 1554 1555 typedef union _mpi2_ieee_sge_chain_union { 1556 struct mpi2_ieee_sge_simple32 Chain32; 1557 struct mpi25_ieee_sge_chain64 Chain64; 1558 } mpi2_ieee_sge_chain_union; 1559 1560 typedef union _mpi2_simple_sge_union { 1561 mpi2_sge_simple_union MpiSimple; 1562 mpi2_ieee_simple_union IeeeSimple; 1563 } mpi2_simple_sge_union; 1564 1565 typedef union _mpi2_sge_io_union { 1566 mpi2_sge_simple_union MpiSimple; 1567 struct mpi2_sge_chain_union MpiChain; 1568 mpi2_ieee_simple_union IeeeSimple; 1569 mpi2_ieee_sge_chain_union IeeeChain; 1570 } mpi2_sge_io_union; 1571 1572 typedef union { 1573 uint8_t CDB32[32]; 1574 mpi2_scsi_io_cdb_eedp32 EEDP32; 1575 mpi2_sge_simple_union SGE; 1576 } mpi2_scsi_io_cdb_union; 1577 1578 1579 1580 /********/ 1581 1582 /* 1583 * RAID SCSI IO Request Message 1584 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1585 */ 1586 struct mfi_mpi2_request_raid_scsi_io { 1587 uint16_t DevHandle; /* 0x00 */ 1588 uint8_t ChainOffset; /* 0x02 */ 1589 uint8_t Function; /* 0x03 */ 1590 uint16_t Reserved1; /* 0x04 */ 1591 uint8_t Reserved2; /* 0x06 */ 1592 uint8_t MsgFlags; /* 0x07 */ 1593 uint8_t VP_ID; /* 0x08 */ 1594 uint8_t VF_ID; /* 0x09 */ 1595 uint16_t Reserved3; /* 0x0A */ 1596 uint32_t SenseBufferLowAddress; /* 0x0C */ 1597 uint16_t SGLFlags; /* 0x10 */ 1598 uint8_t SenseBufferLength; /* 0x12 */ 1599 uint8_t Reserved4; /* 0x13 */ 1600 uint8_t SGLOffset0; /* 0x14 */ 1601 uint8_t SGLOffset1; /* 0x15 */ 1602 uint8_t SGLOffset2; /* 0x16 */ 1603 uint8_t SGLOffset3; /* 0x17 */ 1604 uint32_t SkipCount; /* 0x18 */ 1605 uint32_t DataLength; /* 0x1C */ 1606 uint32_t BidirectionalDataLength; /* 0x20 */ 1607 uint16_t IoFlags; /* 0x24 */ 1608 uint16_t EEDPFlags; /* 0x26 */ 1609 uint32_t EEDPBlockSize; /* 0x28 */ 1610 uint32_t SecondaryReferenceTag; /* 0x2C */ 1611 uint16_t SecondaryApplicationTag; /* 0x30 */ 1612 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1613 uint8_t LUN[8]; /* 0x34 */ 1614 uint32_t Control; /* 0x3C */ 1615 mpi2_scsi_io_cdb_union CDB; /* 0x40 */ 1616 mpi2_scsi_io_vendor_unique RaidContext; /* 0x60 */ 1617 mpi2_sge_io_union SGL; /* 0x80 */ 1618 } __packed; 1619 1620 /* 1621 * MPT RAID MFA IO Descriptor. 1622 */ 1623 typedef struct _mfi_raid_mfa_io_descriptor { 1624 uint32_t RequestFlags : 8; 1625 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1626 uint32_t MessageAddress2; /* bits 61:32 */ 1627 } mfi_raid_mfa_io_request_descriptor; 1628 1629 struct mfi_mpi2_request_header { 1630 uint8_t RequestFlags; /* 0x00 */ 1631 uint8_t MSIxIndex; /* 0x01 */ 1632 uint16_t SMID; /* 0x02 */ 1633 uint16_t LMID; /* 0x04 */ 1634 }; 1635 1636 /* defines for the RequestFlags field */ 1637 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1638 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1639 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1640 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1641 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1642 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1643 1644 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1645 1646 struct mfi_mpi2_request_high_priority { 1647 struct mfi_mpi2_request_header header; 1648 uint16_t reserved; 1649 }; 1650 1651 struct mfi_mpi2_request_scsi_io { 1652 struct mfi_mpi2_request_header header; 1653 uint16_t scsi_io_dev_handle; 1654 }; 1655 1656 struct mfi_mpi2_request_scsi_target { 1657 struct mfi_mpi2_request_header header; 1658 uint16_t scsi_target_io_index; 1659 }; 1660 1661 /* Request Descriptors */ 1662 union mfi_mpi2_request_descriptor { 1663 struct mfi_mpi2_request_header header; 1664 struct mfi_mpi2_request_high_priority high_priority; 1665 struct mfi_mpi2_request_scsi_io scsi_io; 1666 struct mfi_mpi2_request_scsi_target scsi_target; 1667 uint64_t words; 1668 }; 1669 1670 /* 1671 * Request descriptor types 1672 */ 1673 #define MFI_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1674 #define MFI_REQ_DESCRIPT_FLAGS_MFA 0x1 1675 #define MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 0x1 1676 1677 #define MFI_FUSION_FP_DEFAULT_TIMEOUT 0x14 1678 1679 struct mfi_mpi2_reply_header { 1680 uint8_t ReplyFlags; /* 0x00 */ 1681 uint8_t MSIxIndex; /* 0x01 */ 1682 uint16_t SMID; /* 0x02 */ 1683 }; 1684 1685 /* defines for the ReplyFlags field */ 1686 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1687 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1688 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1689 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1690 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1691 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1692 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1693 1694 /* values for marking a reply descriptor as unused */ 1695 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1696 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1697 1698 struct mfi_mpi2_reply_default { 1699 struct mfi_mpi2_reply_header header; 1700 uint32_t DescriptorTypeDependent2; 1701 }; 1702 1703 struct mfi_mpi2_reply_address { 1704 struct mfi_mpi2_reply_header header; 1705 uint32_t ReplyFrameAddress; 1706 }; 1707 1708 struct mfi_mpi2_reply_scsi_io { 1709 struct mfi_mpi2_reply_header header; 1710 uint16_t TaskTag; /* 0x04 */ 1711 uint16_t Reserved1; /* 0x06 */ 1712 }; 1713 1714 struct mfi_mpi2_reply_target_assist { 1715 struct mfi_mpi2_reply_header header; 1716 uint8_t SequenceNumber; /* 0x04 */ 1717 uint8_t Reserved1; /* 0x04 */ 1718 uint16_t IoIndex; /* 0x06 */ 1719 }; 1720 1721 struct mfi_mpi2_reply_target_cmd_buffer { 1722 struct mfi_mpi2_reply_header header; 1723 uint8_t SequenceNumber; /* 0x04 */ 1724 uint8_t Flags; /* 0x04 */ 1725 uint16_t InitiatorDevHandle; /* 0x06 */ 1726 uint16_t IoIndex; /* 0x06 */ 1727 }; 1728 1729 struct mfi_mpi2_reply_raid_accel { 1730 struct mfi_mpi2_reply_header header; 1731 uint8_t SequenceNumber; /* 0x04 */ 1732 uint32_t Reserved; /* 0x04 */ 1733 }; 1734 1735 /* union of Reply Descriptors */ 1736 union mfi_mpi2_reply_descriptor { 1737 struct mfi_mpi2_reply_header header; 1738 struct mfi_mpi2_reply_scsi_io scsi_io; 1739 struct mfi_mpi2_reply_target_assist target_assist; 1740 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1741 struct mfi_mpi2_reply_raid_accel raid_accel; 1742 struct mfi_mpi2_reply_default reply_default; 1743 uint64_t words; 1744 }; 1745 1746 struct io_request_info { 1747 uint64_t ldStartBlock; 1748 uint32_t numBlocks; 1749 uint16_t ldTgtId; 1750 uint8_t isRead; 1751 uint16_t devHandle; 1752 uint64_t pdBlock; 1753 uint8_t fpOkForIo; 1754 }; 1755 1756 /* 1757 * Define MFI Address Context union. 1758 */ 1759 #ifdef MFI_ADDRESS_IS_uint64_t 1760 typedef uint64_t mfi_address; 1761 #else 1762 typedef union _mfi_address { 1763 struct { 1764 uint32_t addressLow; 1765 uint32_t addressHigh; 1766 } u; 1767 uint64_t address; 1768 } mfi_address; 1769 #endif 1770 1771 #define MEGASAS_MAX_NAME 32 1772 #define MEGASAS_VERSION "4.23" 1773 1774 #endif /* _DEV_IC_MFIREG_H_ */ 1775
Indexes created Thu Oct 23 18:09:57 GMT 2025