mfireg.h revision 1.2.44.1
1 /* $NetBSD: mfireg.h,v 1.2.44.1 2008/03/24 07:15:17 keiichi Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* management interface constants */ 20 #define MFI_MGMT_VD 0x01 21 #define MFI_MGMT_SD 0x02 22 23 /* generic constants */ 24 #define MFI_FRAME_SIZE 64 25 #define MFI_SENSE_SIZE 128 26 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 27 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 28 #define MFI_INVALID_CTX 0xffffffff 29 #define MFI_ENABLE_INTR 0x01 30 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 31 32 /* register offsets */ 33 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 34 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 35 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 36 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 37 #define MFI_IDB 0x20 /* inbound doorbell */ 38 #define MFI_ISTS 0x24 /* inbound intr stat */ 39 #define MFI_IMSK 0x28 /* inbound intr mask */ 40 #define MFI_ODB 0x2c /* outbound doorbell */ 41 #define MFI_OSTS 0x30 /* outbound intr stat */ 42 #define MFI_OMSK 0x34 /* outbound inter mask */ 43 #define MFI_IQP 0x40 /* inbound queue port */ 44 #define MFI_OQP 0x44 /* outbound queue port */ 45 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 46 #define MFI_OSP 0xb0 /* outbound scratch pad */ 47 48 /* * firmware states */ 49 #define MFI_STATE_MASK 0xf0000000 50 #define MFI_STATE_UNDEFINED 0x00000000 51 #define MFI_STATE_BB_INIT 0x10000000 52 #define MFI_STATE_FW_INIT 0x40000000 53 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 54 #define MFI_STATE_FW_INIT_2 0x70000000 55 #define MFI_STATE_DEVICE_SCAN 0x80000000 56 #define MFI_STATE_FLUSH_CACHE 0xa0000000 57 #define MFI_STATE_READY 0xb0000000 58 #define MFI_STATE_OPERATIONAL 0xc0000000 59 #define MFI_STATE_FAULT 0xf0000000 60 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 61 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 62 63 /* command reset register */ 64 #define MFI_INIT_ABORT 0x00000000 65 #define MFI_INIT_READY 0x00000002 66 #define MFI_INIT_MFIMODE 0x00000004 67 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 68 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 69 70 /* mfi Frame flags */ 71 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 72 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 73 #define MFI_FRAME_SGL32 0x0000 74 #define MFI_FRAME_SGL64 0x0002 75 #define MFI_FRAME_SENSE32 0x0000 76 #define MFI_FRAME_SENSE64 0x0004 77 #define MFI_FRAME_DIR_NONE 0x0000 78 #define MFI_FRAME_DIR_WRITE 0x0008 79 #define MFI_FRAME_DIR_READ 0x0010 80 #define MFI_FRAME_DIR_BOTH 0x0018 81 82 /* mfi command opcodes */ 83 #define MFI_CMD_INIT 0x00 84 #define MFI_CMD_LD_READ 0x01 85 #define MFI_CMD_LD_WRITE 0x02 86 #define MFI_CMD_LD_SCSI_IO 0x03 87 #define MFI_CMD_PD_SCSI_IO 0x04 88 #define MFI_CMD_DCMD 0x05 89 #define MFI_CMD_ABORT 0x06 90 #define MFI_CMD_SMP 0x07 91 #define MFI_CMD_STP 0x08 92 93 /* direct commands */ 94 #define MR_DCMD_CTRL_GET_INFO 0x01010000 95 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 96 #define MR_FLUSH_CTRL_CACHE 0x01 97 #define MR_FLUSH_DISK_CACHE 0x02 98 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 99 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 100 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 101 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 102 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 103 #define MR_DCMD_PD_GET_LIST 0x02010000 104 #define MR_DCMD_PD_GET_INFO 0x02020000 105 #define MD_DCMD_PD_SET_STATE 0x02030100 106 #define MD_DCMD_PD_REBUILD 0x02040100 107 #define MR_DCMD_PD_BLINK 0x02070100 108 #define MR_DCMD_PD_UNBLINK 0x02070200 109 #define MR_DCMD_LD_GET_LIST 0x03010000 110 #define MR_DCMD_LD_GET_INFO 0x03020000 111 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 112 #define MD_DCMD_CONF_GET 0x04010000 113 #define MR_DCMD_CLUSTER 0x08000000 114 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 115 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 116 117 #define MR_DCMD_SPEAKER_GET 0x01030100 118 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 119 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 120 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 121 #define MR_DCMD_SPEAKER_TEST 0x01030500 122 123 /* mailbox bytes in direct command */ 124 #define MFI_MBOX_SIZE 12 125 126 /* mfi completion codes */ 127 typedef enum { 128 MFI_STAT_OK = 0x00, 129 MFI_STAT_INVALID_CMD = 0x01, 130 MFI_STAT_INVALID_DCMD = 0x02, 131 MFI_STAT_INVALID_PARAMETER = 0x03, 132 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 133 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 134 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 135 MFI_STAT_APP_IN_USE = 0x07, 136 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 137 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 138 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 139 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 140 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 141 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 142 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 143 MFI_STAT_FLASH_BUSY = 0x0f, 144 MFI_STAT_FLASH_ERROR = 0x10, 145 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 146 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 147 MFI_STAT_FLASH_NOT_OPEN = 0x13, 148 MFI_STAT_FLASH_NOT_STARTED = 0x14, 149 MFI_STAT_FLUSH_FAILED = 0x15, 150 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 151 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 152 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 153 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 154 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 155 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 156 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 157 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 158 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 159 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 160 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 161 MFI_STAT_MFC_HW_ERROR = 0x21, 162 MFI_STAT_NO_HW_PRESENT = 0x22, 163 MFI_STAT_NOT_FOUND = 0x23, 164 MFI_STAT_NOT_IN_ENCL = 0x24, 165 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 166 MFI_STAT_PD_TYPE_WRONG = 0x26, 167 MFI_STAT_PR_DISABLED = 0x27, 168 MFI_STAT_ROW_INDEX_INVALID = 0x28, 169 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 170 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 171 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 172 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 173 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 174 MFI_STAT_SCSI_IO_FAILED = 0x2e, 175 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 176 MFI_STAT_SHUTDOWN_FAILED = 0x30, 177 MFI_STAT_TIME_NOT_SET = 0x31, 178 MFI_STAT_WRONG_STATE = 0x32, 179 MFI_STAT_LD_OFFLINE = 0x33, 180 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 181 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 182 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 183 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 184 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 185 MFI_STAT_INVALID_STATUS = 0xff 186 } mfi_status_t; 187 188 typedef enum { 189 MFI_EVT_CLASS_DEBUG = -2, 190 MFI_EVT_CLASS_PROGRESS = -1, 191 MFI_EVT_CLASS_INFO = 0, 192 MFI_EVT_CLASS_WARNING = 1, 193 MFI_EVT_CLASS_CRITICAL = 2, 194 MFI_EVT_CLASS_FATAL = 3, 195 MFI_EVT_CLASS_DEAD = 4 196 } mfi_evt_class_t; 197 198 typedef enum { 199 MFI_EVT_LOCALE_LD = 0x0001, 200 MFI_EVT_LOCALE_PD = 0x0002, 201 MFI_EVT_LOCALE_ENCL = 0x0004, 202 MFI_EVT_LOCALE_BBU = 0x0008, 203 MFI_EVT_LOCALE_SAS = 0x0010, 204 MFI_EVT_LOCALE_CTRL = 0x0020, 205 MFI_EVT_LOCALE_CONFIG = 0x0040, 206 MFI_EVT_LOCALE_CLUSTER = 0x0080, 207 MFI_EVT_LOCALE_ALL = 0xffff 208 } mfi_evt_locale_t; 209 210 typedef enum { 211 MR_EVT_ARGS_NONE = 0x00, 212 MR_EVT_ARGS_CDB_SENSE, 213 MR_EVT_ARGS_LD, 214 MR_EVT_ARGS_LD_COUNT, 215 MR_EVT_ARGS_LD_LBA, 216 MR_EVT_ARGS_LD_OWNER, 217 MR_EVT_ARGS_LD_LBA_PD_LBA, 218 MR_EVT_ARGS_LD_PROG, 219 MR_EVT_ARGS_LD_STATE, 220 MR_EVT_ARGS_LD_STRIP, 221 MR_EVT_ARGS_PD, 222 MR_EVT_ARGS_PD_ERR, 223 MR_EVT_ARGS_PD_LBA, 224 MR_EVT_ARGS_PD_LBA_LD, 225 MR_EVT_ARGS_PD_PROG, 226 MR_EVT_ARGS_PD_STATE, 227 MR_EVT_ARGS_PCI, 228 MR_EVT_ARGS_RATE, 229 MR_EVT_ARGS_STR, 230 MR_EVT_ARGS_TIME, 231 MR_EVT_ARGS_ECC 232 } mfi_evt_args; 233 234 /* driver definitions */ 235 #define MFI_MAX_PD_CHANNELS 2 236 #define MFI_MAX_PD_ARRAY 32 237 #define MFI_MAX_LD_CHANNELS 2 238 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 239 #define MFI_MAX_CHANNEL_DEVS 128 240 #define MFI_DEFAULT_ID -1 241 #define MFI_MAX_LUN 8 242 #define MFI_MAX_LD 64 243 #define MFI_MAX_SPAN 8 244 #define MFI_MAX_ARRAY_DEDICATED 16 245 246 /* sense buffer */ 247 struct mfi_sense { 248 uint8_t mse_data[MFI_SENSE_SIZE]; 249 } __packed; 250 251 /* scatter gather elements */ 252 struct mfi_sg32 { 253 uint32_t addr; 254 uint32_t len; 255 } __packed; 256 257 struct mfi_sg64 { 258 uint64_t addr; 259 uint32_t len; 260 } __packed; 261 262 union mfi_sgl { 263 struct mfi_sg32 sg32[1]; 264 struct mfi_sg64 sg64[1]; 265 } __packed; 266 267 /* message frame */ 268 struct mfi_frame_header { 269 uint8_t mfh_cmd; 270 uint8_t mfh_sense_len; 271 uint8_t mfh_cmd_status; 272 uint8_t mfh_scsi_status; 273 uint8_t mfh_target_id; 274 uint8_t mfh_lun_id; 275 uint8_t mfh_cdb_len; 276 uint8_t mfh_sg_count; 277 uint32_t mfh_context; 278 uint32_t mfh_pad0; 279 uint16_t mfh_flags; 280 uint16_t mfh_timeout; 281 uint32_t mfh_data_len; 282 } __packed; 283 284 union mfi_sgl_frame { 285 struct mfi_sg32 sge32[8]; 286 struct mfi_sg64 sge64[5]; 287 288 } __packed; 289 290 struct mfi_init_frame { 291 struct mfi_frame_header mif_header; 292 uint32_t mif_qinfo_new_addr_lo; 293 uint32_t mif_qinfo_new_addr_hi; 294 uint32_t mif_qinfo_old_addr_lo; 295 uint32_t mif_qinfo_old_addr_hi; 296 uint32_t mif_reserved[6]; 297 } __packed; 298 299 /* queue init structure */ 300 struct mfi_init_qinfo { 301 uint32_t miq_flags; 302 uint32_t miq_rq_entries; 303 uint32_t miq_rq_addr_lo; 304 uint32_t miq_rq_addr_hi; 305 uint32_t miq_pi_addr_lo; 306 uint32_t miq_pi_addr_hi; 307 uint32_t miq_ci_addr_lo; 308 uint32_t miq_ci_addr_hi; 309 } __packed; 310 311 #define MFI_IO_FRAME_SIZE 40 312 struct mfi_io_frame { 313 struct mfi_frame_header mif_header; 314 uint32_t mif_sense_addr_lo; 315 uint32_t mif_sense_addr_hi; 316 uint32_t mif_lba_lo; 317 uint32_t mif_lba_hi; 318 union mfi_sgl mif_sgl; 319 } __packed; 320 321 #define MFI_PASS_FRAME_SIZE 48 322 struct mfi_pass_frame { 323 struct mfi_frame_header mpf_header; 324 uint32_t mpf_sense_addr_lo; 325 uint32_t mpf_sense_addr_hi; 326 uint8_t mpf_cdb[16]; 327 union mfi_sgl mpf_sgl; 328 } __packed; 329 330 #define MFI_DCMD_FRAME_SIZE 40 331 struct mfi_dcmd_frame { 332 struct mfi_frame_header mdf_header; 333 uint32_t mdf_opcode; 334 uint8_t mdf_mbox[MFI_MBOX_SIZE]; 335 union mfi_sgl mdf_sgl; 336 } __packed; 337 338 struct mfi_abort_frame { 339 struct mfi_frame_header maf_header; 340 uint32_t maf_abort_context; 341 uint32_t maf_pad; 342 uint32_t maf_abort_mfi_addr_lo; 343 uint32_t maf_abort_mfi_addr_hi; 344 uint32_t maf_reserved[6]; 345 } __packed; 346 347 struct mfi_smp_frame { 348 struct mfi_frame_header msf_header; 349 uint64_t msf_sas_addr; 350 union { 351 struct mfi_sg32 sg32[2]; 352 struct mfi_sg64 sg64[2]; 353 } msf_sgl; 354 } __packed; 355 356 struct mfi_stp_frame { 357 struct mfi_frame_header msf_header; 358 uint16_t msf_fis[10]; 359 uint32_t msf_stp_flags; 360 union { 361 struct mfi_sg32 sg32[2]; 362 struct mfi_sg64 sg64[2]; 363 } msf_sgl; 364 } __packed; 365 366 union mfi_frame { 367 struct mfi_frame_header mfr_header; 368 struct mfi_init_frame mfr_init; 369 struct mfi_io_frame mfr_io; 370 struct mfi_pass_frame mfr_pass; 371 struct mfi_dcmd_frame mfr_dcmd; 372 struct mfi_abort_frame mfr_abort; 373 struct mfi_smp_frame mfr_smp; 374 struct mfi_stp_frame mfr_stp; 375 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 376 }; 377 378 union mfi_evt_class_locale { 379 struct { 380 uint16_t locale; 381 uint8_t reserved; 382 int8_t class; 383 } __packed mec_members; 384 385 uint32_t mec_word; 386 } __packed; 387 388 struct mfi_evt_log_info { 389 uint32_t mel_newest_seq_num; 390 uint32_t mel_oldest_seq_num; 391 uint32_t mel_clear_seq_num; 392 uint32_t mel_shutdown_seq_num; 393 uint32_t mel_boot_seq_num; 394 } __packed; 395 396 struct mfi_progress { 397 uint16_t mp_progress; 398 uint16_t mp_elapsed_seconds; 399 } __packed; 400 401 struct mfi_evtarg_ld { 402 uint16_t mel_target_id; 403 uint8_t mel_ld_index; 404 uint8_t mel_reserved; 405 } __packed; 406 407 struct mfi_evtarg_pd { 408 uint16_t mep_device_id; 409 uint8_t mep_encl_index; 410 uint8_t mep_slot_number; 411 } __packed; 412 413 struct mfi_evt_detail { 414 uint32_t med_seq_num; 415 uint32_t med_time_stamp; 416 uint32_t med_code; 417 union mfi_evt_class_locale med_cl; 418 uint8_t med_arg_type; 419 uint8_t med_reserved1[15]; 420 421 union { 422 struct { 423 struct mfi_evtarg_pd pd; 424 uint8_t cdb_length; 425 uint8_t sense_length; 426 uint8_t reserved[2]; 427 uint8_t cdb[16]; 428 uint8_t sense[64]; 429 } __packed cdb_sense; 430 431 struct mfi_evtarg_ld ld; 432 433 struct { 434 struct mfi_evtarg_ld ld; 435 uint64_t count; 436 } __packed ld_count; 437 438 struct { 439 uint64_t lba; 440 struct mfi_evtarg_ld ld; 441 } __packed ld_lba; 442 443 struct { 444 struct mfi_evtarg_ld ld; 445 uint32_t prev_owner; 446 uint32_t new_owner; 447 } __packed ld_owner; 448 449 struct { 450 uint64_t ld_lba; 451 uint64_t pd_lba; 452 struct mfi_evtarg_ld ld; 453 struct mfi_evtarg_pd pd; 454 } __packed ld_lba_pd_lba; 455 456 struct { 457 struct mfi_evtarg_ld ld; 458 struct mfi_progress prog; 459 } __packed ld_prog; 460 461 struct { 462 struct mfi_evtarg_ld ld; 463 uint32_t prev_state; 464 uint32_t new_state; 465 } __packed ld_state; 466 467 struct { 468 uint64_t strip; 469 struct mfi_evtarg_ld ld; 470 } __packed ld_strip; 471 472 struct mfi_evtarg_pd pd; 473 474 struct { 475 struct mfi_evtarg_pd pd; 476 uint32_t err; 477 } __packed pd_err; 478 479 struct { 480 uint64_t lba; 481 struct mfi_evtarg_pd pd; 482 } __packed pd_lba; 483 484 struct { 485 uint64_t lba; 486 struct mfi_evtarg_pd pd; 487 struct mfi_evtarg_ld ld; 488 } __packed pd_lba_ld; 489 490 struct { 491 struct mfi_evtarg_pd pd; 492 struct mfi_progress prog; 493 } __packed pd_prog; 494 495 struct { 496 struct mfi_evtarg_pd pd; 497 uint32_t prev_state; 498 uint32_t new_state; 499 } __packed pd_state; 500 501 struct { 502 uint16_t vendor_id; 503 uint16_t device_id; 504 uint16_t subvendor_id; 505 uint16_t subdevice_id; 506 } __packed pci; 507 508 uint32_t rate; 509 char str[96]; 510 511 struct { 512 uint32_t rtc; 513 uint32_t elapsed_seconds; 514 } __packed time; 515 516 struct { 517 uint32_t ecar; 518 uint32_t elog; 519 char str[64]; 520 } __packed ecc; 521 522 uint8_t b[96]; 523 uint16_t s[48]; 524 uint32_t w[24]; 525 uint64_t d[12]; 526 } args; 527 528 char med_description[128]; 529 } __packed; 530 531 /* controller properties from mfi_ctrl_info */ 532 struct mfi_ctrl_props { 533 uint16_t mcp_seq_num; 534 uint16_t mcp_pred_fail_poll_interval; 535 uint16_t mcp_intr_throttle_cnt; 536 uint16_t mcp_intr_throttle_timeout; 537 uint8_t mcp_rebuild_rate; 538 uint8_t mcp_patrol_read_rate; 539 uint8_t mcp_bgi_rate; 540 uint8_t mcp_cc_rate; 541 uint8_t mcp_recon_rate; 542 uint8_t mcp_cache_flush_interval; 543 uint8_t mcp_spinup_drv_cnt; 544 uint8_t mcp_spinup_delay; 545 uint8_t mcp_cluster_enable; 546 uint8_t mcp_coercion_mode; 547 uint8_t mcp_alarm_enable; 548 uint8_t mcp_disable_auto_rebuild; 549 uint8_t mcp_disable_battery_warn; 550 uint8_t mcp_ecc_bucket_size; 551 uint16_t mcp_ecc_bucket_leak_rate; 552 uint8_t mcp_restore_hotspare_on_insertion; 553 uint8_t mcp_expose_encl_devices; 554 uint8_t mcp_reserved[38]; 555 } __packed; 556 557 /* pci info */ 558 struct mfi_info_pci { 559 uint16_t mip_vendor; 560 uint16_t mip_device; 561 uint16_t mip_subvendor; 562 uint16_t mip_subdevice; 563 uint8_t mip_reserved[24]; 564 } __packed; 565 566 /* host interface infor */ 567 struct mfi_info_host { 568 uint8_t mih_type; 569 #define MFI_INFO_HOST_PCIX 0x01 570 #define MFI_INFO_HOST_PCIE 0x02 571 #define MFI_INFO_HOST_ISCSI 0x04 572 #define MFI_INFO_HOST_SAS3G 0x08 573 uint8_t mih_reserved[6]; 574 uint8_t mih_port_count; 575 uint64_t mih_port_addr[8]; 576 } __packed; 577 578 /* device interface info */ 579 struct mfi_info_device { 580 uint8_t mid_type; 581 #define MFI_INFO_DEV_SPI 0x01 582 #define MFI_INFO_DEV_SAS3G 0x02 583 #define MFI_INFO_DEV_SATA1 0x04 584 #define MFI_INFO_DEV_SATA3G 0x08 585 uint8_t mid_reserved[6]; 586 uint8_t mid_port_count; 587 uint64_t mid_port_addr[8]; 588 } __packed; 589 590 /* firmware component info */ 591 struct mfi_info_component { 592 char mic_name[8]; 593 char mic_version[32]; 594 char mic_build_date[16]; 595 char mic_build_time[16]; 596 } __packed; 597 598 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 599 struct mfi_ctrl_info { 600 struct mfi_info_pci mci_pci; 601 struct mfi_info_host mci_host; 602 struct mfi_info_device mci_device; 603 604 /* Firmware components that are present and active. */ 605 uint32_t mci_image_check_word; 606 uint32_t mci_image_component_count; 607 struct mfi_info_component mci_image_component[8]; 608 609 /* Firmware components that have been flashed but are inactive */ 610 uint32_t mci_pending_image_component_count; 611 struct mfi_info_component mci_pending_image_component[8]; 612 613 uint8_t mci_max_arms; 614 uint8_t mci_max_spans; 615 uint8_t mci_max_arrays; 616 uint8_t mci_max_lds; 617 char mci_product_name[80]; 618 char mci_serial_number[32]; 619 uint32_t mci_hw_present; 620 #define MFI_INFO_HW_BBU 0x01 621 #define MFI_INFO_HW_ALARM 0x02 622 #define MFI_INFO_HW_NVRAM 0x04 623 #define MFI_INFO_HW_UART 0x08 624 uint32_t mci_current_fw_time; 625 uint16_t mci_max_cmds; 626 uint16_t mci_max_sg_elements; 627 uint32_t mci_max_request_size; 628 uint16_t mci_lds_present; 629 uint16_t mci_lds_degraded; 630 uint16_t mci_lds_offline; 631 uint16_t mci_pd_present; 632 uint16_t mci_pd_disks_present; 633 uint16_t mci_pd_disks_pred_failure; 634 uint16_t mci_pd_disks_failed; 635 uint16_t mci_nvram_size; 636 uint16_t mci_memory_size; 637 uint16_t mci_flash_size; 638 uint16_t mci_ram_correctable_errors; 639 uint16_t mci_ram_uncorrectable_errors; 640 uint8_t mci_cluster_allowed; 641 uint8_t mci_cluster_active; 642 uint16_t mci_max_strips_per_io; 643 644 uint32_t mci_raid_levels; 645 #define MFI_INFO_RAID_0 0x01 646 #define MFI_INFO_RAID_1 0x02 647 #define MFI_INFO_RAID_5 0x04 648 #define MFI_INFO_RAID_1E 0x08 649 #define MFI_INFO_RAID_6 0x10 650 651 uint32_t mci_adapter_ops; 652 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 653 #define MFI_INFO_AOPS_CC_RATE 0x0002 654 #define MFI_INFO_AOPS_BGI_RATE 0x0004 655 #define MFI_INFO_AOPS_RECON_RATE 0x0008 656 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 657 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 658 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 659 #define MFI_INFO_AOPS_BBU 0x0080 660 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 661 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 662 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 663 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 664 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 665 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 666 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 667 668 uint32_t mci_ld_ops; 669 #define MFI_INFO_LDOPS_READ_POLICY 0x01 670 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 671 #define MFI_INFO_LDOPS_IO_POLICY 0x04 672 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 673 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 674 675 struct { 676 uint8_t min; 677 uint8_t max; 678 uint8_t reserved[2]; 679 } __packed mci_stripe_sz_ops; 680 681 uint32_t mci_pd_ops; 682 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 683 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 684 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 685 686 uint32_t mci_pd_mix_support; 687 #define MFI_INFO_PDMIX_SAS 0x01 688 #define MFI_INFO_PDMIX_SATA 0x02 689 #define MFI_INFO_PDMIX_ENCL 0x04 690 #define MFI_INFO_PDMIX_LD 0x08 691 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 692 693 uint8_t mci_ecc_bucket_count; 694 uint8_t mci_reserved2[11]; 695 struct mfi_ctrl_props mci_properties; 696 char mci_package_version[0x60]; 697 uint8_t mci_pad[0x800 - 0x6a0]; 698 } __packed; 699 700 /* logical disk info from MR_DCMD_LD_GET_LIST */ 701 struct mfi_ld { 702 uint8_t mld_target; 703 uint8_t mld_res; 704 uint16_t mld_seq; 705 } __packed; 706 707 struct mfi_ld_list { 708 uint32_t mll_no_ld; 709 uint32_t mll_res; 710 struct { 711 struct mfi_ld mll_ld; 712 uint8_t mll_state; 713 #define MFI_LD_OFFLINE 0x00 714 #define MFI_LD_PART_DEGRADED 0x01 715 #define MFI_LD_DEGRADED 0x02 716 #define MFI_LD_ONLINE 0x03 717 uint8_t mll_res2; 718 uint8_t mll_res3; 719 uint8_t mll_res4; 720 u_quad_t mll_size; 721 } mll_list[MFI_MAX_LD]; 722 } __packed; 723 724 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 725 struct mfi_ld_prop { 726 struct mfi_ld mlp_ld; 727 char mlp_name[16]; 728 uint8_t mlp_cache_policy; 729 uint8_t mlp_acces_policy; 730 uint8_t mlp_diskcache_policy; 731 uint8_t mlp_cur_cache_policy; 732 uint8_t mlp_disable_bgi; 733 uint8_t mlp_res[7]; 734 } __packed; 735 736 struct mfi_ld_parm { 737 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 738 #define MFI_DDF_PRL_RAID0 0x00 739 #define MFI_DDF_PRL_RAID1 0x01 740 #define MFI_DDF_PRL_RAID3 0x03 741 #define MFI_DDF_PRL_RAID4 0x04 742 #define MFI_DDF_PRL_RAID5 0x05 743 #define MFI_DDF_PRL_RAID1E 0x11 744 #define MFI_DDF_PRL_JBOD 0x0f 745 #define MFI_DDF_PRL_CONCAT 0x1f 746 #define MFI_DDF_PRL_RAID5E 0x15 747 #define MFI_DDF_PRL_RAID5EE 0x25 748 #define MFI_DDF_PRL_RAID6 0x16 749 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 750 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 751 #define MFI_DDF_SRL_STRIPED 0x00 752 #define MFI_DDF_SRL_MIRRORED 0x01 753 #define MFI_DDF_SRL_CONCAT 0x02 754 #define MFI_DDF_SRL_SPANNED 0x03 755 uint8_t mpa_stripe_size; 756 uint8_t mpa_no_drv_per_span; 757 uint8_t mpa_span_depth; 758 uint8_t mpa_state; 759 uint8_t mpa_init_state; 760 uint8_t mpa_res[24]; 761 } __packed; 762 763 struct mfi_ld_span { 764 u_quad_t mls_start_block; 765 u_quad_t mls_no_blocks; 766 uint16_t mls_index; 767 uint8_t mls_res[6]; 768 } __packed; 769 770 struct mfi_ld_cfg { 771 struct mfi_ld_prop mlc_prop; 772 struct mfi_ld_parm mlc_parm; 773 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 774 } __packed; 775 776 struct mfi_ld_progress { 777 uint32_t mlp_in_prog; 778 #define MFI_LD_PROG_CC 0x01 779 #define MFI_LD_PROG_BGI 0x02 780 #define MFI_LD_PROG_FGI 0x04 781 #define MFI_LD_PROG_RECONSTRUCT 0x08 782 struct mfi_progress mlp_cc; 783 struct mfi_progress mlp_bgi; 784 struct mfi_progress mlp_fgi; 785 struct mfi_progress mlp_reconstruct; 786 struct mfi_progress mlp_res[4]; 787 } __packed; 788 789 struct mfi_ld_details { 790 struct mfi_ld_cfg mld_cfg; 791 u_quad_t mld_size; 792 struct mfi_ld_progress mld_progress; 793 uint16_t mld_clust_own_id; 794 uint8_t mld_res1; 795 uint8_t mld_res2; 796 uint8_t mld_inq_page83[64]; 797 uint8_t mld_res[16]; 798 } __packed; 799 800 /* physical disk info from MR_DCMD_PD_GET_LIST */ 801 struct mfi_pd_address { 802 uint16_t mpa_pd_id; 803 uint16_t mpa_enc_id; 804 uint8_t mpa_enc_index; 805 uint8_t mpa_enc_slot; 806 uint8_t mpa_scsi_type; 807 uint8_t mpa_port; 808 u_quad_t mpa_sas_address[2]; 809 } __packed; 810 811 struct mfi_pd_list { 812 uint32_t mpl_size; 813 uint32_t mpl_no_pd; 814 struct mfi_pd_address mpl_address[1]; 815 } __packed; 816 #define MFI_PD_LIST_SIZE (256 * sizeof(struct mfi_pd_address) + 8) 817 818 struct mfi_pd { 819 uint16_t mfp_id; 820 uint16_t mfp_seq; 821 } __packed; 822 823 struct mfi_pd_progress { 824 uint32_t mfp_in_prog; 825 #define MFI_PD_PROG_RBLD 0x01 826 #define MFI_PD_PROG_PR 0x02 827 #define MFI_PD_PROG_CLEAR 0x04 828 struct mfi_progress mfp_rebuild; 829 struct mfi_progress mfp_patrol_read; 830 struct mfi_progress mfp_clear; 831 struct mfi_progress mfp_res[4]; 832 } __packed; 833 834 struct mfi_pd_details { 835 struct mfi_pd mpd_pd; 836 uint8_t mpd_inq_data[96]; 837 uint8_t mpd_inq_page83[64]; 838 uint8_t mpd_no_support; 839 uint8_t mpd_scsy_type; 840 uint8_t mpd_port; 841 uint8_t mpd_speed; 842 uint32_t mpd_mediaerr_cnt; 843 uint32_t mpd_othererr_cnt; 844 uint32_t mpd_predfail_cnt; 845 uint32_t mpd_last_pred_event; 846 uint16_t mpd_fw_state; 847 uint8_t mpd_rdy_for_remove; 848 uint8_t mpd_link_speed; 849 uint32_t mpd_ddf_state; 850 #define MFI_DDF_GUID_FORCED 0x01 851 #define MFI_DDF_PART_OF_VD 0x02 852 #define MFI_DDF_GLOB_HOTSPARE 0x04 853 #define MFI_DDF_HOTSPARE 0x08 854 #define MFI_DDF_FOREIGN 0x10 855 #define MFI_DDF_TYPE_MASK 0xf000 856 #define MFI_DDF_TYPE_UNKNOWN 0x0000 857 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 858 #define MFI_DDF_TYPE_SAS 0x2000 859 #define MFI_DDF_TYPE_SATA 0x3000 860 #define MFI_DDF_TYPE_FC 0x4000 861 struct { 862 uint8_t mpp_cnt; 863 uint8_t mpp_severed; 864 uint8_t mpp_res[6]; 865 u_quad_t mpp_sas_addr[4]; 866 } __packed mpd_path; 867 u_quad_t mpd_size; 868 u_quad_t mpd_no_coerce_size; 869 u_quad_t mpd_coerce_size; 870 uint16_t mpd_enc_id; 871 uint8_t mpd_enc_idx; 872 uint8_t mpd_enc_slot; 873 struct mfi_pd_progress mpd_progress; 874 uint8_t mpd_bblock_full; 875 uint8_t mpd_unusable; 876 uint8_t mpd_res[218]; /* size is 512 */ 877 } __packed; 878 879 /* array configuration from MD_DCMD_CONF_GET */ 880 struct mfi_array { 881 u_quad_t mar_smallest_pd; 882 uint8_t mar_no_disk; 883 uint8_t mar_res1; 884 uint16_t mar_array_ref; 885 uint8_t mar_res2[20]; 886 struct { 887 struct mfi_pd mar_pd; 888 uint16_t mar_pd_state; 889 #define MFI_PD_UNCONFIG_GOOD 0x00 890 #define MFI_PD_UNCONFIG_BAD 0x01 891 #define MFI_PD_HOTSPARE 0x02 892 #define MFI_PD_OFFLINE 0x10 893 #define MFI_PD_FAILED 0x11 894 #define MFI_PD_REBUILD 0x14 895 #define MFI_PD_ONLINE 0x18 896 uint8_t mar_enc_pd; 897 uint8_t mar_enc_slot; 898 } pd[MFI_MAX_PD_ARRAY]; 899 } __packed; 900 901 struct mfi_hotspare { 902 struct mfi_pd mhs_pd; 903 uint8_t mhs_type; 904 #define MFI_PD_HS_DEDICATED 0x01 905 #define MFI_PD_HS_REVERTIBLE 0x02 906 #define MFI_PD_HS_ENC_AFFINITY 0x04 907 uint8_t mhs_res[2]; 908 uint8_t mhs_array_max; 909 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 910 } __packed; 911 912 struct mfi_conf { 913 uint32_t mfc_size; 914 uint16_t mfc_no_array; 915 uint16_t mfc_array_size; 916 uint16_t mfc_no_ld; 917 uint16_t mfc_ld_size; 918 uint16_t mfc_no_hs; 919 uint16_t mfc_hs_size; 920 uint8_t mfc_res[16]; 921 /* 922 * XXX this is a ridiculous hack and does not reflect reality 923 * Structures are actually indexed and therefore need pointer 924 * math to reach. We need the size of this structure first so 925 * call it with the size of this structure and then use the returned 926 * values to allocate memory and do the transfer of the whole structure 927 * then calculate pointers to each of these structures. 928 */ 929 struct mfi_array mfc_array[1]; 930 struct mfi_ld_cfg mfc_ld[1]; 931 struct mfi_hotspare mfc_hs[1]; 932 } __packed; 933
Indexes created Sun Oct 19 18:09:56 GMT 2025