mfireg.h revision 1.5
1 /* $NetBSD: mfireg.h,v 1.5 2012/03/21 14:22:36 sborrill Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* management interface constants */ 20 #define MFI_MGMT_VD 0x01 21 #define MFI_MGMT_SD 0x02 22 23 /* generic constants */ 24 #define MFI_FRAME_SIZE 64 25 #define MFI_SENSE_SIZE 128 26 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 27 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 28 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 29 #define MFI_INVALID_CTX 0xffffffff 30 #define MFI_ENABLE_INTR 0x01 31 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 32 33 /* register offsets */ 34 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 35 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 36 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 37 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 38 #define MFI_IDB 0x20 /* inbound doorbell */ 39 #define MFI_ISTS 0x24 /* inbound intr stat */ 40 #define MFI_IMSK 0x28 /* inbound intr mask */ 41 #define MFI_ODB 0x2c /* outbound doorbell */ 42 #define MFI_OSTS 0x30 /* outbound intr stat */ 43 #define MFI_OMSK 0x34 /* outbound inter mask */ 44 #define MFI_IQP 0x40 /* inbound queue port */ 45 #define MFI_OQP 0x44 /* outbound queue port */ 46 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 47 #define MFI_OSP 0xb0 /* outbound scratch pad */ 48 49 /* 50 * skinny specific changes 51 */ 52 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 53 #define MFI_IQPL 0x000000c0 54 #define MFI_IQPH 0x000000c4 55 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 56 57 /* * firmware states */ 58 #define MFI_STATE_MASK 0xf0000000 59 #define MFI_STATE_UNDEFINED 0x00000000 60 #define MFI_STATE_BB_INIT 0x10000000 61 #define MFI_STATE_FW_INIT 0x40000000 62 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 63 #define MFI_STATE_FW_INIT_2 0x70000000 64 #define MFI_STATE_DEVICE_SCAN 0x80000000 65 #define MFI_STATE_FLUSH_CACHE 0xa0000000 66 #define MFI_STATE_READY 0xb0000000 67 #define MFI_STATE_OPERATIONAL 0xc0000000 68 #define MFI_STATE_FAULT 0xf0000000 69 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 70 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 71 72 /* command reset register */ 73 #define MFI_INIT_ABORT 0x00000000 74 #define MFI_INIT_READY 0x00000002 75 #define MFI_INIT_MFIMODE 0x00000004 76 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 77 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 78 79 /* mfi Frame flags */ 80 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 81 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 82 #define MFI_FRAME_SGL32 0x0000 83 #define MFI_FRAME_SGL64 0x0002 84 #define MFI_FRAME_SENSE32 0x0000 85 #define MFI_FRAME_SENSE64 0x0004 86 #define MFI_FRAME_DIR_NONE 0x0000 87 #define MFI_FRAME_DIR_WRITE 0x0008 88 #define MFI_FRAME_DIR_READ 0x0010 89 #define MFI_FRAME_DIR_BOTH 0x0018 90 91 /* mfi command opcodes */ 92 #define MFI_CMD_INIT 0x00 93 #define MFI_CMD_LD_READ 0x01 94 #define MFI_CMD_LD_WRITE 0x02 95 #define MFI_CMD_LD_SCSI_IO 0x03 96 #define MFI_CMD_PD_SCSI_IO 0x04 97 #define MFI_CMD_DCMD 0x05 98 #define MFI_CMD_ABORT 0x06 99 #define MFI_CMD_SMP 0x07 100 #define MFI_CMD_STP 0x08 101 102 /* direct commands */ 103 #define MR_DCMD_CTRL_GET_INFO 0x01010000 104 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 105 #define MR_FLUSH_CTRL_CACHE 0x01 106 #define MR_FLUSH_DISK_CACHE 0x02 107 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 108 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 109 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 110 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 111 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 112 #define MR_DCMD_PD_GET_LIST 0x02010000 113 #define MR_DCMD_PD_GET_INFO 0x02020000 114 #define MD_DCMD_PD_SET_STATE 0x02030100 115 #define MD_DCMD_PD_REBUILD 0x02040100 116 #define MR_DCMD_PD_BLINK 0x02070100 117 #define MR_DCMD_PD_UNBLINK 0x02070200 118 #define MR_DCMD_LD_GET_LIST 0x03010000 119 #define MR_DCMD_LD_GET_INFO 0x03020000 120 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 121 #define MD_DCMD_CONF_GET 0x04010000 122 #define MR_DCMD_CLUSTER 0x08000000 123 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 124 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 125 126 #define MR_DCMD_SPEAKER_GET 0x01030100 127 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 128 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 129 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 130 #define MR_DCMD_SPEAKER_TEST 0x01030500 131 132 /* mailbox bytes in direct command */ 133 #define MFI_MBOX_SIZE 12 134 135 /* mfi completion codes */ 136 typedef enum { 137 MFI_STAT_OK = 0x00, 138 MFI_STAT_INVALID_CMD = 0x01, 139 MFI_STAT_INVALID_DCMD = 0x02, 140 MFI_STAT_INVALID_PARAMETER = 0x03, 141 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 142 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 143 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 144 MFI_STAT_APP_IN_USE = 0x07, 145 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 146 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 147 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 148 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 149 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 150 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 151 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 152 MFI_STAT_FLASH_BUSY = 0x0f, 153 MFI_STAT_FLASH_ERROR = 0x10, 154 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 155 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 156 MFI_STAT_FLASH_NOT_OPEN = 0x13, 157 MFI_STAT_FLASH_NOT_STARTED = 0x14, 158 MFI_STAT_FLUSH_FAILED = 0x15, 159 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 160 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 161 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 162 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 163 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 164 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 165 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 166 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 167 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 168 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 169 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 170 MFI_STAT_MFC_HW_ERROR = 0x21, 171 MFI_STAT_NO_HW_PRESENT = 0x22, 172 MFI_STAT_NOT_FOUND = 0x23, 173 MFI_STAT_NOT_IN_ENCL = 0x24, 174 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 175 MFI_STAT_PD_TYPE_WRONG = 0x26, 176 MFI_STAT_PR_DISABLED = 0x27, 177 MFI_STAT_ROW_INDEX_INVALID = 0x28, 178 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 179 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 180 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 181 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 182 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 183 MFI_STAT_SCSI_IO_FAILED = 0x2e, 184 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 185 MFI_STAT_SHUTDOWN_FAILED = 0x30, 186 MFI_STAT_TIME_NOT_SET = 0x31, 187 MFI_STAT_WRONG_STATE = 0x32, 188 MFI_STAT_LD_OFFLINE = 0x33, 189 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 190 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 191 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 192 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 193 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 194 MFI_STAT_INVALID_STATUS = 0xff 195 } mfi_status_t; 196 197 typedef enum { 198 MFI_EVT_CLASS_DEBUG = -2, 199 MFI_EVT_CLASS_PROGRESS = -1, 200 MFI_EVT_CLASS_INFO = 0, 201 MFI_EVT_CLASS_WARNING = 1, 202 MFI_EVT_CLASS_CRITICAL = 2, 203 MFI_EVT_CLASS_FATAL = 3, 204 MFI_EVT_CLASS_DEAD = 4 205 } mfi_evt_class_t; 206 207 typedef enum { 208 MFI_EVT_LOCALE_LD = 0x0001, 209 MFI_EVT_LOCALE_PD = 0x0002, 210 MFI_EVT_LOCALE_ENCL = 0x0004, 211 MFI_EVT_LOCALE_BBU = 0x0008, 212 MFI_EVT_LOCALE_SAS = 0x0010, 213 MFI_EVT_LOCALE_CTRL = 0x0020, 214 MFI_EVT_LOCALE_CONFIG = 0x0040, 215 MFI_EVT_LOCALE_CLUSTER = 0x0080, 216 MFI_EVT_LOCALE_ALL = 0xffff 217 } mfi_evt_locale_t; 218 219 typedef enum { 220 MR_EVT_ARGS_NONE = 0x00, 221 MR_EVT_ARGS_CDB_SENSE, 222 MR_EVT_ARGS_LD, 223 MR_EVT_ARGS_LD_COUNT, 224 MR_EVT_ARGS_LD_LBA, 225 MR_EVT_ARGS_LD_OWNER, 226 MR_EVT_ARGS_LD_LBA_PD_LBA, 227 MR_EVT_ARGS_LD_PROG, 228 MR_EVT_ARGS_LD_STATE, 229 MR_EVT_ARGS_LD_STRIP, 230 MR_EVT_ARGS_PD, 231 MR_EVT_ARGS_PD_ERR, 232 MR_EVT_ARGS_PD_LBA, 233 MR_EVT_ARGS_PD_LBA_LD, 234 MR_EVT_ARGS_PD_PROG, 235 MR_EVT_ARGS_PD_STATE, 236 MR_EVT_ARGS_PCI, 237 MR_EVT_ARGS_RATE, 238 MR_EVT_ARGS_STR, 239 MR_EVT_ARGS_TIME, 240 MR_EVT_ARGS_ECC 241 } mfi_evt_args; 242 243 /* driver definitions */ 244 #define MFI_MAX_PD_CHANNELS 2 245 #define MFI_MAX_PD_ARRAY 32 246 #define MFI_MAX_LD_CHANNELS 2 247 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 248 #define MFI_MAX_CHANNEL_DEVS 128 249 #define MFI_DEFAULT_ID -1 250 #define MFI_MAX_LUN 8 251 #define MFI_MAX_LD 64 252 #define MFI_MAX_SPAN 8 253 #define MFI_MAX_ARRAY_DEDICATED 16 254 255 /* sense buffer */ 256 struct mfi_sense { 257 uint8_t mse_data[MFI_SENSE_SIZE]; 258 } __packed; 259 260 /* scatter gather elements */ 261 struct mfi_sg32 { 262 uint32_t addr; 263 uint32_t len; 264 } __packed; 265 266 struct mfi_sg64 { 267 uint64_t addr; 268 uint32_t len; 269 } __packed; 270 271 union mfi_sgl { 272 struct mfi_sg32 sg32[1]; 273 struct mfi_sg64 sg64[1]; 274 } __packed; 275 276 /* message frame */ 277 struct mfi_frame_header { 278 uint8_t mfh_cmd; 279 uint8_t mfh_sense_len; 280 uint8_t mfh_cmd_status; 281 uint8_t mfh_scsi_status; 282 uint8_t mfh_target_id; 283 uint8_t mfh_lun_id; 284 uint8_t mfh_cdb_len; 285 uint8_t mfh_sg_count; 286 uint32_t mfh_context; 287 uint32_t mfh_pad0; 288 uint16_t mfh_flags; 289 uint16_t mfh_timeout; 290 uint32_t mfh_data_len; 291 } __packed; 292 293 union mfi_sgl_frame { 294 struct mfi_sg32 sge32[8]; 295 struct mfi_sg64 sge64[5]; 296 297 } __packed; 298 299 struct mfi_init_frame { 300 struct mfi_frame_header mif_header; 301 uint32_t mif_qinfo_new_addr_lo; 302 uint32_t mif_qinfo_new_addr_hi; 303 uint32_t mif_qinfo_old_addr_lo; 304 uint32_t mif_qinfo_old_addr_hi; 305 uint32_t mif_reserved[6]; 306 } __packed; 307 308 /* queue init structure */ 309 struct mfi_init_qinfo { 310 uint32_t miq_flags; 311 uint32_t miq_rq_entries; 312 uint32_t miq_rq_addr_lo; 313 uint32_t miq_rq_addr_hi; 314 uint32_t miq_pi_addr_lo; 315 uint32_t miq_pi_addr_hi; 316 uint32_t miq_ci_addr_lo; 317 uint32_t miq_ci_addr_hi; 318 } __packed; 319 320 #define MFI_IO_FRAME_SIZE 40 321 struct mfi_io_frame { 322 struct mfi_frame_header mif_header; 323 uint32_t mif_sense_addr_lo; 324 uint32_t mif_sense_addr_hi; 325 uint32_t mif_lba_lo; 326 uint32_t mif_lba_hi; 327 union mfi_sgl mif_sgl; 328 } __packed; 329 330 #define MFI_PASS_FRAME_SIZE 48 331 struct mfi_pass_frame { 332 struct mfi_frame_header mpf_header; 333 uint32_t mpf_sense_addr_lo; 334 uint32_t mpf_sense_addr_hi; 335 uint8_t mpf_cdb[16]; 336 union mfi_sgl mpf_sgl; 337 } __packed; 338 339 #define MFI_DCMD_FRAME_SIZE 40 340 struct mfi_dcmd_frame { 341 struct mfi_frame_header mdf_header; 342 uint32_t mdf_opcode; 343 uint8_t mdf_mbox[MFI_MBOX_SIZE]; 344 union mfi_sgl mdf_sgl; 345 } __packed; 346 347 struct mfi_abort_frame { 348 struct mfi_frame_header maf_header; 349 uint32_t maf_abort_context; 350 uint32_t maf_pad; 351 uint32_t maf_abort_mfi_addr_lo; 352 uint32_t maf_abort_mfi_addr_hi; 353 uint32_t maf_reserved[6]; 354 } __packed; 355 356 struct mfi_smp_frame { 357 struct mfi_frame_header msf_header; 358 uint64_t msf_sas_addr; 359 union { 360 struct mfi_sg32 sg32[2]; 361 struct mfi_sg64 sg64[2]; 362 } msf_sgl; 363 } __packed; 364 365 struct mfi_stp_frame { 366 struct mfi_frame_header msf_header; 367 uint16_t msf_fis[10]; 368 uint32_t msf_stp_flags; 369 union { 370 struct mfi_sg32 sg32[2]; 371 struct mfi_sg64 sg64[2]; 372 } msf_sgl; 373 } __packed; 374 375 union mfi_frame { 376 struct mfi_frame_header mfr_header; 377 struct mfi_init_frame mfr_init; 378 struct mfi_io_frame mfr_io; 379 struct mfi_pass_frame mfr_pass; 380 struct mfi_dcmd_frame mfr_dcmd; 381 struct mfi_abort_frame mfr_abort; 382 struct mfi_smp_frame mfr_smp; 383 struct mfi_stp_frame mfr_stp; 384 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 385 }; 386 387 union mfi_evt_class_locale { 388 struct { 389 uint16_t locale; 390 uint8_t reserved; 391 int8_t class; 392 } __packed mec_members; 393 394 uint32_t mec_word; 395 } __packed; 396 397 struct mfi_evt_log_info { 398 uint32_t mel_newest_seq_num; 399 uint32_t mel_oldest_seq_num; 400 uint32_t mel_clear_seq_num; 401 uint32_t mel_shutdown_seq_num; 402 uint32_t mel_boot_seq_num; 403 } __packed; 404 405 struct mfi_progress { 406 uint16_t mp_progress; 407 uint16_t mp_elapsed_seconds; 408 } __packed; 409 410 struct mfi_evtarg_ld { 411 uint16_t mel_target_id; 412 uint8_t mel_ld_index; 413 uint8_t mel_reserved; 414 } __packed; 415 416 struct mfi_evtarg_pd { 417 uint16_t mep_device_id; 418 uint8_t mep_encl_index; 419 uint8_t mep_slot_number; 420 } __packed; 421 422 struct mfi_evt_detail { 423 uint32_t med_seq_num; 424 uint32_t med_time_stamp; 425 uint32_t med_code; 426 union mfi_evt_class_locale med_cl; 427 uint8_t med_arg_type; 428 uint8_t med_reserved1[15]; 429 430 union { 431 struct { 432 struct mfi_evtarg_pd pd; 433 uint8_t cdb_length; 434 uint8_t sense_length; 435 uint8_t reserved[2]; 436 uint8_t cdb[16]; 437 uint8_t sense[64]; 438 } __packed cdb_sense; 439 440 struct mfi_evtarg_ld ld; 441 442 struct { 443 struct mfi_evtarg_ld ld; 444 uint64_t count; 445 } __packed ld_count; 446 447 struct { 448 uint64_t lba; 449 struct mfi_evtarg_ld ld; 450 } __packed ld_lba; 451 452 struct { 453 struct mfi_evtarg_ld ld; 454 uint32_t prev_owner; 455 uint32_t new_owner; 456 } __packed ld_owner; 457 458 struct { 459 uint64_t ld_lba; 460 uint64_t pd_lba; 461 struct mfi_evtarg_ld ld; 462 struct mfi_evtarg_pd pd; 463 } __packed ld_lba_pd_lba; 464 465 struct { 466 struct mfi_evtarg_ld ld; 467 struct mfi_progress prog; 468 } __packed ld_prog; 469 470 struct { 471 struct mfi_evtarg_ld ld; 472 uint32_t prev_state; 473 uint32_t new_state; 474 } __packed ld_state; 475 476 struct { 477 uint64_t strip; 478 struct mfi_evtarg_ld ld; 479 } __packed ld_strip; 480 481 struct mfi_evtarg_pd pd; 482 483 struct { 484 struct mfi_evtarg_pd pd; 485 uint32_t err; 486 } __packed pd_err; 487 488 struct { 489 uint64_t lba; 490 struct mfi_evtarg_pd pd; 491 } __packed pd_lba; 492 493 struct { 494 uint64_t lba; 495 struct mfi_evtarg_pd pd; 496 struct mfi_evtarg_ld ld; 497 } __packed pd_lba_ld; 498 499 struct { 500 struct mfi_evtarg_pd pd; 501 struct mfi_progress prog; 502 } __packed pd_prog; 503 504 struct { 505 struct mfi_evtarg_pd pd; 506 uint32_t prev_state; 507 uint32_t new_state; 508 } __packed pd_state; 509 510 struct { 511 uint16_t vendor_id; 512 uint16_t device_id; 513 uint16_t subvendor_id; 514 uint16_t subdevice_id; 515 } __packed pci; 516 517 uint32_t rate; 518 char str[96]; 519 520 struct { 521 uint32_t rtc; 522 uint32_t elapsed_seconds; 523 } __packed time; 524 525 struct { 526 uint32_t ecar; 527 uint32_t elog; 528 char str[64]; 529 } __packed ecc; 530 531 uint8_t b[96]; 532 uint16_t s[48]; 533 uint32_t w[24]; 534 uint64_t d[12]; 535 } args; 536 537 char med_description[128]; 538 } __packed; 539 540 /* controller properties from mfi_ctrl_info */ 541 struct mfi_ctrl_props { 542 uint16_t mcp_seq_num; 543 uint16_t mcp_pred_fail_poll_interval; 544 uint16_t mcp_intr_throttle_cnt; 545 uint16_t mcp_intr_throttle_timeout; 546 uint8_t mcp_rebuild_rate; 547 uint8_t mcp_patrol_read_rate; 548 uint8_t mcp_bgi_rate; 549 uint8_t mcp_cc_rate; 550 uint8_t mcp_recon_rate; 551 uint8_t mcp_cache_flush_interval; 552 uint8_t mcp_spinup_drv_cnt; 553 uint8_t mcp_spinup_delay; 554 uint8_t mcp_cluster_enable; 555 uint8_t mcp_coercion_mode; 556 uint8_t mcp_alarm_enable; 557 uint8_t mcp_disable_auto_rebuild; 558 uint8_t mcp_disable_battery_warn; 559 uint8_t mcp_ecc_bucket_size; 560 uint16_t mcp_ecc_bucket_leak_rate; 561 uint8_t mcp_restore_hotspare_on_insertion; 562 uint8_t mcp_expose_encl_devices; 563 uint8_t mcp_reserved[38]; 564 } __packed; 565 566 /* pci info */ 567 struct mfi_info_pci { 568 uint16_t mip_vendor; 569 uint16_t mip_device; 570 uint16_t mip_subvendor; 571 uint16_t mip_subdevice; 572 uint8_t mip_reserved[24]; 573 } __packed; 574 575 /* host interface infor */ 576 struct mfi_info_host { 577 uint8_t mih_type; 578 #define MFI_INFO_HOST_PCIX 0x01 579 #define MFI_INFO_HOST_PCIE 0x02 580 #define MFI_INFO_HOST_ISCSI 0x04 581 #define MFI_INFO_HOST_SAS3G 0x08 582 uint8_t mih_reserved[6]; 583 uint8_t mih_port_count; 584 uint64_t mih_port_addr[8]; 585 } __packed; 586 587 /* device interface info */ 588 struct mfi_info_device { 589 uint8_t mid_type; 590 #define MFI_INFO_DEV_SPI 0x01 591 #define MFI_INFO_DEV_SAS3G 0x02 592 #define MFI_INFO_DEV_SATA1 0x04 593 #define MFI_INFO_DEV_SATA3G 0x08 594 uint8_t mid_reserved[6]; 595 uint8_t mid_port_count; 596 uint64_t mid_port_addr[8]; 597 } __packed; 598 599 /* firmware component info */ 600 struct mfi_info_component { 601 char mic_name[8]; 602 char mic_version[32]; 603 char mic_build_date[16]; 604 char mic_build_time[16]; 605 } __packed; 606 607 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 608 struct mfi_ctrl_info { 609 struct mfi_info_pci mci_pci; 610 struct mfi_info_host mci_host; 611 struct mfi_info_device mci_device; 612 613 /* Firmware components that are present and active. */ 614 uint32_t mci_image_check_word; 615 uint32_t mci_image_component_count; 616 struct mfi_info_component mci_image_component[8]; 617 618 /* Firmware components that have been flashed but are inactive */ 619 uint32_t mci_pending_image_component_count; 620 struct mfi_info_component mci_pending_image_component[8]; 621 622 uint8_t mci_max_arms; 623 uint8_t mci_max_spans; 624 uint8_t mci_max_arrays; 625 uint8_t mci_max_lds; 626 char mci_product_name[80]; 627 char mci_serial_number[32]; 628 uint32_t mci_hw_present; 629 #define MFI_INFO_HW_BBU 0x01 630 #define MFI_INFO_HW_ALARM 0x02 631 #define MFI_INFO_HW_NVRAM 0x04 632 #define MFI_INFO_HW_UART 0x08 633 uint32_t mci_current_fw_time; 634 uint16_t mci_max_cmds; 635 uint16_t mci_max_sg_elements; 636 uint32_t mci_max_request_size; 637 uint16_t mci_lds_present; 638 uint16_t mci_lds_degraded; 639 uint16_t mci_lds_offline; 640 uint16_t mci_pd_present; 641 uint16_t mci_pd_disks_present; 642 uint16_t mci_pd_disks_pred_failure; 643 uint16_t mci_pd_disks_failed; 644 uint16_t mci_nvram_size; 645 uint16_t mci_memory_size; 646 uint16_t mci_flash_size; 647 uint16_t mci_ram_correctable_errors; 648 uint16_t mci_ram_uncorrectable_errors; 649 uint8_t mci_cluster_allowed; 650 uint8_t mci_cluster_active; 651 uint16_t mci_max_strips_per_io; 652 653 uint32_t mci_raid_levels; 654 #define MFI_INFO_RAID_0 0x01 655 #define MFI_INFO_RAID_1 0x02 656 #define MFI_INFO_RAID_5 0x04 657 #define MFI_INFO_RAID_1E 0x08 658 #define MFI_INFO_RAID_6 0x10 659 660 uint32_t mci_adapter_ops; 661 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 662 #define MFI_INFO_AOPS_CC_RATE 0x0002 663 #define MFI_INFO_AOPS_BGI_RATE 0x0004 664 #define MFI_INFO_AOPS_RECON_RATE 0x0008 665 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 666 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 667 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 668 #define MFI_INFO_AOPS_BBU 0x0080 669 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 670 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 671 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 672 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 673 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 674 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 675 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 676 677 uint32_t mci_ld_ops; 678 #define MFI_INFO_LDOPS_READ_POLICY 0x01 679 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 680 #define MFI_INFO_LDOPS_IO_POLICY 0x04 681 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 682 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 683 684 struct { 685 uint8_t min; 686 uint8_t max; 687 uint8_t reserved[2]; 688 } __packed mci_stripe_sz_ops; 689 690 uint32_t mci_pd_ops; 691 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 692 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 693 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 694 695 uint32_t mci_pd_mix_support; 696 #define MFI_INFO_PDMIX_SAS 0x01 697 #define MFI_INFO_PDMIX_SATA 0x02 698 #define MFI_INFO_PDMIX_ENCL 0x04 699 #define MFI_INFO_PDMIX_LD 0x08 700 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 701 702 uint8_t mci_ecc_bucket_count; 703 uint8_t mci_reserved2[11]; 704 struct mfi_ctrl_props mci_properties; 705 char mci_package_version[0x60]; 706 uint8_t mci_pad[0x800 - 0x6a0]; 707 } __packed; 708 709 /* logical disk info from MR_DCMD_LD_GET_LIST */ 710 struct mfi_ld { 711 uint8_t mld_target; 712 uint8_t mld_res; 713 uint16_t mld_seq; 714 } __packed; 715 716 struct mfi_ld_list { 717 uint32_t mll_no_ld; 718 uint32_t mll_res; 719 struct { 720 struct mfi_ld mll_ld; 721 uint8_t mll_state; 722 #define MFI_LD_OFFLINE 0x00 723 #define MFI_LD_PART_DEGRADED 0x01 724 #define MFI_LD_DEGRADED 0x02 725 #define MFI_LD_ONLINE 0x03 726 uint8_t mll_res2; 727 uint8_t mll_res3; 728 uint8_t mll_res4; 729 u_quad_t mll_size; 730 } mll_list[MFI_MAX_LD]; 731 } __packed; 732 733 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 734 struct mfi_ld_prop { 735 struct mfi_ld mlp_ld; 736 char mlp_name[16]; 737 uint8_t mlp_cache_policy; 738 uint8_t mlp_acces_policy; 739 uint8_t mlp_diskcache_policy; 740 uint8_t mlp_cur_cache_policy; 741 uint8_t mlp_disable_bgi; 742 uint8_t mlp_res[7]; 743 } __packed; 744 745 struct mfi_ld_parm { 746 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 747 #define MFI_DDF_PRL_RAID0 0x00 748 #define MFI_DDF_PRL_RAID1 0x01 749 #define MFI_DDF_PRL_RAID3 0x03 750 #define MFI_DDF_PRL_RAID4 0x04 751 #define MFI_DDF_PRL_RAID5 0x05 752 #define MFI_DDF_PRL_RAID1E 0x11 753 #define MFI_DDF_PRL_JBOD 0x0f 754 #define MFI_DDF_PRL_CONCAT 0x1f 755 #define MFI_DDF_PRL_RAID5E 0x15 756 #define MFI_DDF_PRL_RAID5EE 0x25 757 #define MFI_DDF_PRL_RAID6 0x16 758 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 759 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 760 #define MFI_DDF_SRL_STRIPED 0x00 761 #define MFI_DDF_SRL_MIRRORED 0x01 762 #define MFI_DDF_SRL_CONCAT 0x02 763 #define MFI_DDF_SRL_SPANNED 0x03 764 uint8_t mpa_stripe_size; 765 uint8_t mpa_no_drv_per_span; 766 uint8_t mpa_span_depth; 767 uint8_t mpa_state; 768 uint8_t mpa_init_state; 769 uint8_t mpa_res[24]; 770 } __packed; 771 772 struct mfi_ld_span { 773 u_quad_t mls_start_block; 774 u_quad_t mls_no_blocks; 775 uint16_t mls_index; 776 uint8_t mls_res[6]; 777 } __packed; 778 779 struct mfi_ld_cfg { 780 struct mfi_ld_prop mlc_prop; 781 struct mfi_ld_parm mlc_parm; 782 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 783 } __packed; 784 785 struct mfi_ld_progress { 786 uint32_t mlp_in_prog; 787 #define MFI_LD_PROG_CC 0x01 788 #define MFI_LD_PROG_BGI 0x02 789 #define MFI_LD_PROG_FGI 0x04 790 #define MFI_LD_PROG_RECONSTRUCT 0x08 791 struct mfi_progress mlp_cc; 792 struct mfi_progress mlp_bgi; 793 struct mfi_progress mlp_fgi; 794 struct mfi_progress mlp_reconstruct; 795 struct mfi_progress mlp_res[4]; 796 } __packed; 797 798 struct mfi_ld_details { 799 struct mfi_ld_cfg mld_cfg; 800 u_quad_t mld_size; 801 struct mfi_ld_progress mld_progress; 802 uint16_t mld_clust_own_id; 803 uint8_t mld_res1; 804 uint8_t mld_res2; 805 uint8_t mld_inq_page83[64]; 806 uint8_t mld_res[16]; 807 } __packed; 808 809 /* physical disk info from MR_DCMD_PD_GET_LIST */ 810 struct mfi_pd_address { 811 uint16_t mpa_pd_id; 812 uint16_t mpa_enc_id; 813 uint8_t mpa_enc_index; 814 uint8_t mpa_enc_slot; 815 uint8_t mpa_scsi_type; 816 uint8_t mpa_port; 817 u_quad_t mpa_sas_address[2]; 818 } __packed; 819 820 struct mfi_pd_list { 821 uint32_t mpl_size; 822 uint32_t mpl_no_pd; 823 struct mfi_pd_address mpl_address[1]; 824 } __packed; 825 #define MFI_PD_LIST_SIZE (256 * sizeof(struct mfi_pd_address) + 8) 826 827 struct mfi_pd { 828 uint16_t mfp_id; 829 uint16_t mfp_seq; 830 } __packed; 831 832 struct mfi_pd_progress { 833 uint32_t mfp_in_prog; 834 #define MFI_PD_PROG_RBLD 0x01 835 #define MFI_PD_PROG_PR 0x02 836 #define MFI_PD_PROG_CLEAR 0x04 837 struct mfi_progress mfp_rebuild; 838 struct mfi_progress mfp_patrol_read; 839 struct mfi_progress mfp_clear; 840 struct mfi_progress mfp_res[4]; 841 } __packed; 842 843 struct mfi_pd_details { 844 struct mfi_pd mpd_pd; 845 uint8_t mpd_inq_data[96]; 846 uint8_t mpd_inq_page83[64]; 847 uint8_t mpd_no_support; 848 uint8_t mpd_scsy_type; 849 uint8_t mpd_port; 850 uint8_t mpd_speed; 851 uint32_t mpd_mediaerr_cnt; 852 uint32_t mpd_othererr_cnt; 853 uint32_t mpd_predfail_cnt; 854 uint32_t mpd_last_pred_event; 855 uint16_t mpd_fw_state; 856 uint8_t mpd_rdy_for_remove; 857 uint8_t mpd_link_speed; 858 uint32_t mpd_ddf_state; 859 #define MFI_DDF_GUID_FORCED 0x01 860 #define MFI_DDF_PART_OF_VD 0x02 861 #define MFI_DDF_GLOB_HOTSPARE 0x04 862 #define MFI_DDF_HOTSPARE 0x08 863 #define MFI_DDF_FOREIGN 0x10 864 #define MFI_DDF_TYPE_MASK 0xf000 865 #define MFI_DDF_TYPE_UNKNOWN 0x0000 866 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 867 #define MFI_DDF_TYPE_SAS 0x2000 868 #define MFI_DDF_TYPE_SATA 0x3000 869 #define MFI_DDF_TYPE_FC 0x4000 870 struct { 871 uint8_t mpp_cnt; 872 uint8_t mpp_severed; 873 uint8_t mpp_res[6]; 874 u_quad_t mpp_sas_addr[4]; 875 } __packed mpd_path; 876 u_quad_t mpd_size; 877 u_quad_t mpd_no_coerce_size; 878 u_quad_t mpd_coerce_size; 879 uint16_t mpd_enc_id; 880 uint8_t mpd_enc_idx; 881 uint8_t mpd_enc_slot; 882 struct mfi_pd_progress mpd_progress; 883 uint8_t mpd_bblock_full; 884 uint8_t mpd_unusable; 885 uint8_t mpd_res[218]; /* size is 512 */ 886 } __packed; 887 888 /* array configuration from MD_DCMD_CONF_GET */ 889 struct mfi_array { 890 u_quad_t mar_smallest_pd; 891 uint8_t mar_no_disk; 892 uint8_t mar_res1; 893 uint16_t mar_array_ref; 894 uint8_t mar_res2[20]; 895 struct { 896 struct mfi_pd mar_pd; 897 uint16_t mar_pd_state; 898 #define MFI_PD_UNCONFIG_GOOD 0x00 899 #define MFI_PD_UNCONFIG_BAD 0x01 900 #define MFI_PD_HOTSPARE 0x02 901 #define MFI_PD_OFFLINE 0x10 902 #define MFI_PD_FAILED 0x11 903 #define MFI_PD_REBUILD 0x14 904 #define MFI_PD_ONLINE 0x18 905 uint8_t mar_enc_pd; 906 uint8_t mar_enc_slot; 907 } pd[MFI_MAX_PD_ARRAY]; 908 } __packed; 909 910 struct mfi_hotspare { 911 struct mfi_pd mhs_pd; 912 uint8_t mhs_type; 913 #define MFI_PD_HS_DEDICATED 0x01 914 #define MFI_PD_HS_REVERTIBLE 0x02 915 #define MFI_PD_HS_ENC_AFFINITY 0x04 916 uint8_t mhs_res[2]; 917 uint8_t mhs_array_max; 918 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 919 } __packed; 920 921 struct mfi_conf { 922 uint32_t mfc_size; 923 uint16_t mfc_no_array; 924 uint16_t mfc_array_size; 925 uint16_t mfc_no_ld; 926 uint16_t mfc_ld_size; 927 uint16_t mfc_no_hs; 928 uint16_t mfc_hs_size; 929 uint8_t mfc_res[16]; 930 /* 931 * XXX this is a ridiculous hack and does not reflect reality 932 * Structures are actually indexed and therefore need pointer 933 * math to reach. We need the size of this structure first so 934 * call it with the size of this structure and then use the returned 935 * values to allocate memory and do the transfer of the whole structure 936 * then calculate pointers to each of these structures. 937 */ 938 struct mfi_array mfc_array[1]; 939 struct mfi_ld_cfg mfc_ld[1]; 940 struct mfi_hotspare mfc_hs[1]; 941 } __packed; 942
Indexes created Mon Oct 20 01:09:56 GMT 2025