mfireg.h revision 1.7.2.1
1 /* $NetBSD: mfireg.h,v 1.7.2.1 2012/11/20 03:02:06 tls Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Copyright (c) 2007 LSI Corp. 21 * Copyright (c) 2007 Rajesh Prabhakaran. 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 #ifndef _DEV_IC_MFIREG_H_ 47 #define _DEV_IC_MFIREG_H_ 48 49 /* management interface constants */ 50 #define MFI_MGMT_VD 0x01 51 #define MFI_MGMT_SD 0x02 52 53 /* generic constants */ 54 #define MFI_FRAME_SIZE 64 55 #define MFI_SENSE_SIZE 128 56 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 57 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 58 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 59 #define MFI_INVALID_CTX 0xffffffff 60 #define MFI_ENABLE_INTR 0x01 61 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 62 #define MFI_SECTOR_LEN 512 63 64 /* register offsets */ 65 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 66 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 67 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 68 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 69 #define MFI_IDB 0x20 /* inbound doorbell */ 70 #define MFI_ISTS 0x24 /* inbound intr stat */ 71 #define MFI_IMSK 0x28 /* inbound intr mask */ 72 #define MFI_ODB 0x2c /* outbound doorbell */ 73 #define MFI_OSTS 0x30 /* outbound intr stat */ 74 #define MFI_OMSK 0x34 /* outbound inter mask */ 75 #define MFI_IQP 0x40 /* inbound queue port */ 76 #define MFI_OQP 0x44 /* outbound queue port */ 77 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 78 #define MFI_OSP 0xb0 /* outbound scratch pad */ 79 80 /* ThunderBolt specific Register */ 81 #define MFI_RPI 0x6c /* reply_post_host_index */ 82 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 83 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 84 85 /* OCR registers */ 86 #define MFI_WSR 0x004 /* write sequence register */ 87 #define MFI_HDR 0x008 /* host diagnostic register */ 88 #define MFI_RSR 0x3c3 /* Reset Status Register */ 89 90 /* OCR specific flags */ 91 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 92 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 93 94 /* 95 * skinny specific changes 96 */ 97 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 98 #define MFI_IQPL 0x000000c0 99 #define MFI_IQPH 0x000000c4 100 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 101 102 /* * firmware states */ 103 #define MFI_STATE_MASK 0xf0000000 104 #define MFI_STATE_UNDEFINED 0x00000000 105 #define MFI_STATE_BB_INIT 0x10000000 106 #define MFI_STATE_FW_INIT 0x40000000 107 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 108 #define MFI_STATE_FW_INIT_2 0x70000000 109 #define MFI_STATE_DEVICE_SCAN 0x80000000 110 #define MFI_STATE_FLUSH_CACHE 0xa0000000 111 #define MFI_STATE_READY 0xb0000000 112 #define MFI_STATE_OPERATIONAL 0xc0000000 113 #define MFI_STATE_FAULT 0xf0000000 114 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 115 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 116 #define MFI_STATE_HOSTMEMREQD_MASK 0x08000000 117 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 118 #define MFI_RESET_REQUIRED 0x00000001 119 120 /* ThunderBolt Support */ 121 #define MFI_STATE_TB_MASK 0xf0000000 122 #define MFI_STATE_TB_RESET 0x00000000 123 #define MFI_STATE_TB_READY 0x10000000 124 #define MFI_STATE_TB_OPERATIONAL 0x20000000 125 #define MFI_STATE_TB_FAULT 0x40000000 126 127 /* command reset register */ 128 #define MFI_INIT_ABORT 0x00000000 129 #define MFI_INIT_READY 0x00000002 130 #define MFI_INIT_MFIMODE 0x00000004 131 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 132 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 133 #define MFI_INIT_HOTPLUG 0x00000010 134 135 /* ADP reset flags */ 136 #define MFI_STOP_ADP 0x00000020 137 #define MFI_ADP_RESET 0x00000040 138 #define DIAG_WRITE_ENABLE 0x00000080 139 #define DIAG_RESET_ADAPTER 0x00000004 140 141 /* mfi Frame flags */ 142 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 143 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 144 #define MFI_FRAME_SGL32 0x0000 145 #define MFI_FRAME_SGL64 0x0002 146 #define MFI_FRAME_SENSE32 0x0000 147 #define MFI_FRAME_SENSE64 0x0004 148 #define MFI_FRAME_DIR_NONE 0x0000 149 #define MFI_FRAME_DIR_WRITE 0x0008 150 #define MFI_FRAME_DIR_READ 0x0010 151 #define MFI_FRAME_DIR_BOTH 0x0018 152 #define MFI_FRAME_IEEE_SGL 0x0020 153 154 /* ThunderBolt Specific */ 155 156 /* 157 * Pre-TB command size and TB command size. 158 * We will be checking it at the load time for the time being 159 */ 160 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 161 162 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 163 /* 164 * We are defining only 128 byte message to reduce memory move over head 165 * and also it will reduce the SRB extension size by 128byte compared with 166 * 256 message size 167 */ 168 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 169 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 170 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 171 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 172 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 173 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 174 175 /* 176 * Calculating how many SGEs allowed in a allocated main message 177 * (size of the Message - Raid SCSI IO message size(except SGE)) 178 * / size of SGE 179 * (0x100 - (0x90 - 0x10)) / 0x10 = 8 180 */ 181 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG \ 182 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - \ 183 (sizeof(struct mfi_mpi2_request_raid_scsi_io) - sizeof(mpi2_sge_io_union))\ 184 ) / sizeof(mpi2_sge_io_union)) 185 186 /* 187 * (Command frame size allocaed in SRB ext - Raid SCSI IO message size) 188 * / size of SGL ; 189 * (1280 - 256) / 16 = 64 190 */ 191 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG \ 192 ((MR_COMMAND_SIZE - MEGASAS_THUNDERBOLT_NEW_MSG_SIZE) / \ 193 sizeof(mpi2_sge_io_union)) 194 195 /* 196 * This is the offset in number of 4 * 32bit words to the next chain 197 * (0x100 - 0x10)/0x10 = 0xF(15) 198 */ 199 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG \ 200 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - sizeof(mpi2_sge_io_union)) / 16) 201 202 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MPT_PTMSG \ 203 (offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16) 204 205 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 206 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 207 208 #define MR_INTERNAL_MFI_FRAMES_SMID 1 209 #define MR_CTRL_EVENT_WAIT_SMID 2 210 #define MR_INTERNAL_DRIVER_RESET_SMID 3 211 212 /* mfi command opcodes */ 213 #define MFI_CMD_INIT 0x00 214 #define MFI_CMD_LD_READ 0x01 215 #define MFI_CMD_LD_WRITE 0x02 216 #define MFI_CMD_LD_SCSI_IO 0x03 217 #define MFI_CMD_PD_SCSI_IO 0x04 218 #define MFI_CMD_DCMD 0x05 219 #define MFI_CMD_ABORT 0x06 220 #define MFI_CMD_SMP 0x07 221 #define MFI_CMD_STP 0x08 222 223 /* direct commands */ 224 #define MR_DCMD_CTRL_GET_INFO 0x01010000 225 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 226 #define MR_FLUSH_CTRL_CACHE 0x01 227 #define MR_FLUSH_DISK_CACHE 0x02 228 #define MR_DCMD_CTRL_HOST_MEM_ALLOC 0x0100e100 229 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 230 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 231 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 232 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 233 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 234 #define MR_DCMD_PD_GET_LIST 0x02010000 235 #define MR_DCMD_PD_LIST_QUERY 0x02010100 236 #define MR_DCMD_PD_GET_INFO 0x02020000 237 #define MD_DCMD_PD_SET_STATE 0x02030100 238 #define MD_DCMD_PD_REBUILD 0x02040100 239 #define MR_DCMD_PD_BLINK 0x02070100 240 #define MR_DCMD_PD_UNBLINK 0x02070200 241 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 242 #define MR_DCMD_LD_SYNC 0x0300e102 243 #define MR_DCMD_LD_GET_LIST 0x03010000 244 #define MR_DCMD_LD_GET_INFO 0x03020000 245 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 246 #define MD_DCMD_CONF_GET 0x04010000 247 #define MR_DCMD_BBU_GET_STATUS 0x05010000 248 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 249 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 250 #define MR_DCMD_CLUSTER 0x08000000 251 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 252 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 253 254 #define MR_DCMD_SPEAKER_GET 0x01030100 255 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 256 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 257 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 258 #define MR_DCMD_SPEAKER_TEST 0x01030500 259 260 /* mailbox bytes in direct command */ 261 #define MFI_MBOX_SIZE 12 262 263 /* mfi completion codes */ 264 typedef enum { 265 MFI_STAT_OK = 0x00, 266 MFI_STAT_INVALID_CMD = 0x01, 267 MFI_STAT_INVALID_DCMD = 0x02, 268 MFI_STAT_INVALID_PARAMETER = 0x03, 269 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 270 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 271 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 272 MFI_STAT_APP_IN_USE = 0x07, 273 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 274 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 275 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 276 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 277 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 278 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 279 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 280 MFI_STAT_FLASH_BUSY = 0x0f, 281 MFI_STAT_FLASH_ERROR = 0x10, 282 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 283 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 284 MFI_STAT_FLASH_NOT_OPEN = 0x13, 285 MFI_STAT_FLASH_NOT_STARTED = 0x14, 286 MFI_STAT_FLUSH_FAILED = 0x15, 287 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 288 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 289 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 290 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 291 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 292 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 293 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 294 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 295 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 296 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 297 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 298 MFI_STAT_MFC_HW_ERROR = 0x21, 299 MFI_STAT_NO_HW_PRESENT = 0x22, 300 MFI_STAT_NOT_FOUND = 0x23, 301 MFI_STAT_NOT_IN_ENCL = 0x24, 302 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 303 MFI_STAT_PD_TYPE_WRONG = 0x26, 304 MFI_STAT_PR_DISABLED = 0x27, 305 MFI_STAT_ROW_INDEX_INVALID = 0x28, 306 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 307 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 308 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 309 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 310 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 311 MFI_STAT_SCSI_IO_FAILED = 0x2e, 312 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 313 MFI_STAT_SHUTDOWN_FAILED = 0x30, 314 MFI_STAT_TIME_NOT_SET = 0x31, 315 MFI_STAT_WRONG_STATE = 0x32, 316 MFI_STAT_LD_OFFLINE = 0x33, 317 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 318 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 319 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 320 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 321 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 322 MFI_STAT_INVALID_STATUS = 0xff 323 } mfi_status_t; 324 325 typedef enum { 326 MFI_EVT_CLASS_DEBUG = -2, 327 MFI_EVT_CLASS_PROGRESS = -1, 328 MFI_EVT_CLASS_INFO = 0, 329 MFI_EVT_CLASS_WARNING = 1, 330 MFI_EVT_CLASS_CRITICAL = 2, 331 MFI_EVT_CLASS_FATAL = 3, 332 MFI_EVT_CLASS_DEAD = 4 333 } mfi_evt_class_t; 334 335 typedef enum { 336 MFI_EVT_LOCALE_LD = 0x0001, 337 MFI_EVT_LOCALE_PD = 0x0002, 338 MFI_EVT_LOCALE_ENCL = 0x0004, 339 MFI_EVT_LOCALE_BBU = 0x0008, 340 MFI_EVT_LOCALE_SAS = 0x0010, 341 MFI_EVT_LOCALE_CTRL = 0x0020, 342 MFI_EVT_LOCALE_CONFIG = 0x0040, 343 MFI_EVT_LOCALE_CLUSTER = 0x0080, 344 MFI_EVT_LOCALE_ALL = 0xffff 345 } mfi_evt_locale_t; 346 347 typedef enum { 348 MR_EVT_ARGS_NONE = 0x00, 349 MR_EVT_ARGS_CDB_SENSE, 350 MR_EVT_ARGS_LD, 351 MR_EVT_ARGS_LD_COUNT, 352 MR_EVT_ARGS_LD_LBA, 353 MR_EVT_ARGS_LD_OWNER, 354 MR_EVT_ARGS_LD_LBA_PD_LBA, 355 MR_EVT_ARGS_LD_PROG, 356 MR_EVT_ARGS_LD_STATE, 357 MR_EVT_ARGS_LD_STRIP, 358 MR_EVT_ARGS_PD, 359 MR_EVT_ARGS_PD_ERR, 360 MR_EVT_ARGS_PD_LBA, 361 MR_EVT_ARGS_PD_LBA_LD, 362 MR_EVT_ARGS_PD_PROG, 363 MR_EVT_ARGS_PD_STATE, 364 MR_EVT_ARGS_PCI, 365 MR_EVT_ARGS_RATE, 366 MR_EVT_ARGS_STR, 367 MR_EVT_ARGS_TIME, 368 MR_EVT_ARGS_ECC 369 } mfi_evt_args; 370 371 /* XXX should be in mfi_evt_args ? */ 372 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 373 #define MR_EVT_PD_REMOVED 0x0070 374 #define MR_EVT_PD_INSERTED 0x005b 375 #define MR_EVT_LD_CHANGE 0x0051 376 377 typedef enum { 378 MR_PD_QUERY_TYPE_ALL = 0, 379 MR_PD_QUERY_TYPE_STATE = 1, 380 MR_PD_QUERY_TYPE_POWER_STATE = 2, 381 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 382 MR_PD_QUERY_TYPE_SPEED = 4, 383 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 384 } mfi_pd_query_type; 385 386 /* driver definitions */ 387 #define MFI_MAX_PD_CHANNELS 2 388 #define MFI_MAX_PD_ARRAY 32 389 #define MFI_MAX_LD_CHANNELS 2 390 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 391 #define MFI_MAX_CHANNEL_DEVS 128 392 #define MFI_DEFAULT_ID -1 393 #define MFI_MAX_LUN 8 394 #define MFI_MAX_LD 64 395 #define MFI_MAX_SPAN 8 396 #define MFI_MAX_ARRAY_DEDICATED 16 397 398 /* sense buffer */ 399 struct mfi_sense { 400 uint8_t mse_data[MFI_SENSE_SIZE]; 401 } __packed; 402 403 /* scatter gather elements */ 404 struct mfi_sg32 { 405 uint32_t addr; 406 uint32_t len; 407 } __packed; 408 409 struct mfi_sg64 { 410 uint64_t addr; 411 uint32_t len; 412 } __packed; 413 414 struct mfi_sg_ieee { 415 uint64_t addr; 416 uint32_t len; 417 uint32_t flags; 418 } __packed; 419 420 421 union mfi_sgl { 422 struct mfi_sg32 sg32[1]; 423 struct mfi_sg64 sg64[1]; 424 struct mfi_sg_ieee sg_ieee[1]; 425 } __packed; 426 427 /* message frame */ 428 struct mfi_frame_header { 429 uint8_t mfh_cmd; 430 uint8_t mfh_sense_len; 431 uint8_t mfh_cmd_status; 432 uint8_t mfh_scsi_status; 433 uint8_t mfh_target_id; 434 uint8_t mfh_lun_id; 435 uint8_t mfh_cdb_len; 436 uint8_t mfh_sg_count; 437 uint32_t mfh_context; 438 uint32_t mfh_pad0; 439 uint16_t mfh_flags; 440 uint16_t mfh_timeout; 441 uint32_t mfh_data_len; 442 } __packed; 443 444 union mfi_sgl_frame { 445 struct mfi_sg32 sge32[8]; 446 struct mfi_sg64 sge64[5]; 447 448 } __packed; 449 450 struct mfi_init_frame { 451 struct mfi_frame_header mif_header; 452 uint32_t mif_qinfo_new_addr_lo; 453 uint32_t mif_qinfo_new_addr_hi; 454 uint32_t mif_qinfo_old_addr_lo; 455 uint32_t mif_qinfo_old_addr_hi; 456 uint32_t driver_ver_lo; /* 0x28 */ 457 uint32_t driver_ver_hi; /* 0x2c */ 458 uint32_t reserved[4]; 459 } __packed; 460 461 /* queue init structure */ 462 struct mfi_init_qinfo { 463 uint32_t miq_flags; 464 uint32_t miq_rq_entries; 465 uint32_t miq_rq_addr_lo; 466 uint32_t miq_rq_addr_hi; 467 uint32_t miq_pi_addr_lo; 468 uint32_t miq_pi_addr_hi; 469 uint32_t miq_ci_addr_lo; 470 uint32_t miq_ci_addr_hi; 471 } __packed; 472 473 #define MFI_IO_FRAME_SIZE 40 474 struct mfi_io_frame { 475 struct mfi_frame_header mif_header; 476 uint32_t mif_sense_addr_lo; 477 uint32_t mif_sense_addr_hi; 478 uint32_t mif_lba_lo; 479 uint32_t mif_lba_hi; 480 union mfi_sgl mif_sgl; 481 } __packed; 482 483 #define MFI_PASS_FRAME_SIZE 48 484 struct mfi_pass_frame { 485 struct mfi_frame_header mpf_header; 486 uint32_t mpf_sense_addr_lo; 487 uint32_t mpf_sense_addr_hi; 488 uint8_t mpf_cdb[16]; 489 union mfi_sgl mpf_sgl; 490 } __packed; 491 492 #define MFI_DCMD_FRAME_SIZE 40 493 struct mfi_dcmd_frame { 494 struct mfi_frame_header mdf_header; 495 uint32_t mdf_opcode; 496 uint8_t mdf_mbox[MFI_MBOX_SIZE]; 497 union mfi_sgl mdf_sgl; 498 } __packed; 499 #define MFI_DCMD_MBOX_PEND_FLAG 0x1 500 501 struct mfi_abort_frame { 502 struct mfi_frame_header maf_header; 503 uint32_t maf_abort_context; 504 uint32_t maf_pad; 505 uint32_t maf_abort_mfi_addr_lo; 506 uint32_t maf_abort_mfi_addr_hi; 507 uint32_t maf_reserved[6]; 508 } __packed; 509 510 struct mfi_smp_frame { 511 struct mfi_frame_header msf_header; 512 uint64_t msf_sas_addr; 513 union { 514 struct mfi_sg32 sg32[2]; 515 struct mfi_sg64 sg64[2]; 516 } msf_sgl; 517 } __packed; 518 519 struct mfi_stp_frame { 520 struct mfi_frame_header msf_header; 521 uint16_t msf_fis[10]; 522 uint32_t msf_stp_flags; 523 union { 524 struct mfi_sg32 sg32[2]; 525 struct mfi_sg64 sg64[2]; 526 } msf_sgl; 527 } __packed; 528 529 union mfi_frame { 530 struct mfi_frame_header mfr_header; 531 struct mfi_init_frame mfr_init; 532 struct mfi_io_frame mfr_io; 533 struct mfi_pass_frame mfr_pass; 534 struct mfi_dcmd_frame mfr_dcmd; 535 struct mfi_abort_frame mfr_abort; 536 struct mfi_smp_frame mfr_smp; 537 struct mfi_stp_frame mfr_stp; 538 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 539 }; 540 541 union mfi_evt_class_locale { 542 struct { 543 uint16_t locale; 544 uint8_t reserved; 545 int8_t class; 546 } __packed mec_members; 547 548 uint32_t mec_word; 549 } __packed; 550 551 struct mfi_evt_log_info { 552 uint32_t mel_newest_seq_num; 553 uint32_t mel_oldest_seq_num; 554 uint32_t mel_clear_seq_num; 555 uint32_t mel_shutdown_seq_num; 556 uint32_t mel_boot_seq_num; 557 } __packed; 558 559 struct mfi_progress { 560 uint16_t mp_progress; 561 uint16_t mp_elapsed_seconds; 562 } __packed; 563 564 struct mfi_evtarg_ld { 565 uint16_t mel_target_id; 566 uint8_t mel_ld_index; 567 uint8_t mel_reserved; 568 } __packed; 569 570 struct mfi_evtarg_pd { 571 uint16_t mep_device_id; 572 uint8_t mep_encl_index; 573 uint8_t mep_slot_number; 574 } __packed; 575 576 struct mfi_evt_detail { 577 uint32_t med_seq_num; 578 uint32_t med_time_stamp; 579 uint32_t med_code; 580 union mfi_evt_class_locale med_cl; 581 uint8_t med_arg_type; 582 uint8_t med_reserved1[15]; 583 584 union { 585 struct { 586 struct mfi_evtarg_pd pd; 587 uint8_t cdb_length; 588 uint8_t sense_length; 589 uint8_t reserved[2]; 590 uint8_t cdb[16]; 591 uint8_t sense[64]; 592 } __packed cdb_sense; 593 594 struct mfi_evtarg_ld ld; 595 596 struct { 597 struct mfi_evtarg_ld ld; 598 uint64_t count; 599 } __packed ld_count; 600 601 struct { 602 uint64_t lba; 603 struct mfi_evtarg_ld ld; 604 } __packed ld_lba; 605 606 struct { 607 struct mfi_evtarg_ld ld; 608 uint32_t prev_owner; 609 uint32_t new_owner; 610 } __packed ld_owner; 611 612 struct { 613 uint64_t ld_lba; 614 uint64_t pd_lba; 615 struct mfi_evtarg_ld ld; 616 struct mfi_evtarg_pd pd; 617 } __packed ld_lba_pd_lba; 618 619 struct { 620 struct mfi_evtarg_ld ld; 621 struct mfi_progress prog; 622 } __packed ld_prog; 623 624 struct { 625 struct mfi_evtarg_ld ld; 626 uint32_t prev_state; 627 uint32_t new_state; 628 } __packed ld_state; 629 630 struct { 631 uint64_t strip; 632 struct mfi_evtarg_ld ld; 633 } __packed ld_strip; 634 635 struct mfi_evtarg_pd pd; 636 637 struct { 638 struct mfi_evtarg_pd pd; 639 uint32_t err; 640 } __packed pd_err; 641 642 struct { 643 uint64_t lba; 644 struct mfi_evtarg_pd pd; 645 } __packed pd_lba; 646 647 struct { 648 uint64_t lba; 649 struct mfi_evtarg_pd pd; 650 struct mfi_evtarg_ld ld; 651 } __packed pd_lba_ld; 652 653 struct { 654 struct mfi_evtarg_pd pd; 655 struct mfi_progress prog; 656 } __packed pd_prog; 657 658 struct { 659 struct mfi_evtarg_pd pd; 660 uint32_t prev_state; 661 uint32_t new_state; 662 } __packed pd_state; 663 664 struct { 665 uint16_t vendor_id; 666 uint16_t device_id; 667 uint16_t subvendor_id; 668 uint16_t subdevice_id; 669 } __packed pci; 670 671 uint32_t rate; 672 char str[96]; 673 674 struct { 675 uint32_t rtc; 676 uint32_t elapsed_seconds; 677 } __packed time; 678 679 struct { 680 uint32_t ecar; 681 uint32_t elog; 682 char str[64]; 683 } __packed ecc; 684 685 uint8_t b[96]; 686 uint16_t s[48]; 687 uint32_t w[24]; 688 uint64_t d[12]; 689 } args; 690 691 char med_description[128]; 692 } __packed; 693 694 /* controller properties from mfi_ctrl_info */ 695 struct mfi_ctrl_props { 696 uint16_t mcp_seq_num; 697 uint16_t mcp_pred_fail_poll_interval; 698 uint16_t mcp_intr_throttle_cnt; 699 uint16_t mcp_intr_throttle_timeout; 700 uint8_t mcp_rebuild_rate; 701 uint8_t mcp_patrol_read_rate; 702 uint8_t mcp_bgi_rate; 703 uint8_t mcp_cc_rate; 704 uint8_t mcp_recon_rate; 705 uint8_t mcp_cache_flush_interval; 706 uint8_t mcp_spinup_drv_cnt; 707 uint8_t mcp_spinup_delay; 708 uint8_t mcp_cluster_enable; 709 uint8_t mcp_coercion_mode; 710 uint8_t mcp_alarm_enable; 711 uint8_t mcp_disable_auto_rebuild; 712 uint8_t mcp_disable_battery_warn; 713 uint8_t mcp_ecc_bucket_size; 714 uint16_t mcp_ecc_bucket_leak_rate; 715 uint8_t mcp_restore_hotspare_on_insertion; 716 uint8_t mcp_expose_encl_devices; 717 uint8_t maintainPdFailHistory; 718 uint8_t disallowHostRequestReordering; 719 /* set TRUE to abort CC on detecting an inconsistency */ 720 uint8_t abortCCOnError; 721 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 722 uint8_t loadBalanceMode; 723 /* 724 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 725 * h/w mechansim like GPIO pins 726 * 1 - disable auto detect SGPIO, 727 * 2 - disable i2c SEP auto detect 728 * 3 - disable both auto detect 729 */ 730 uint8_t disableAutoDetectBackplane; 731 /* 732 * % of source LD to be reserved for a VDs snapshot in snapshot 733 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 734 */ 735 uint8_t snapVDSpace; 736 737 /* 738 * Add properties that can be controlled by a bit in the following 739 * structure. 740 */ 741 struct { 742 /* set TRUE to disable copyBack (0=copback enabled) */ 743 uint32_t copyBackDisabled :1; 744 uint32_t SMARTerEnabled :1; 745 uint32_t prCorrectUnconfiguredAreas :1; 746 uint32_t useFdeOnly :1; 747 uint32_t disableNCQ :1; 748 uint32_t SSDSMARTerEnabled :1; 749 uint32_t SSDPatrolReadEnabled :1; 750 uint32_t enableSpinDownUnconfigured :1; 751 uint32_t autoEnhancedImport :1; 752 uint32_t enableSecretKeyControl :1; 753 uint32_t disableOnlineCtrlReset :1; 754 uint32_t allowBootWithPinnedCache :1; 755 uint32_t disableSpinDownHS :1; 756 uint32_t enableJBOD :1; 757 uint32_t reserved :18; 758 } OnOffProperties; 759 /* 760 * % of source LD to be reserved for auto snapshot in snapshot 761 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 762 */ 763 uint8_t autoSnapVDSpace; 764 /* 765 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 766 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 767 */ 768 uint8_t viewSpace; 769 /* # of idle minutes before device is spun down (0=use FW defaults) */ 770 uint16_t spinDownTime; 771 uint8_t reserved[24]; 772 } __packed; 773 774 /* pci info */ 775 struct mfi_info_pci { 776 uint16_t mip_vendor; 777 uint16_t mip_device; 778 uint16_t mip_subvendor; 779 uint16_t mip_subdevice; 780 uint8_t mip_reserved[24]; 781 } __packed; 782 783 /* host interface infor */ 784 struct mfi_info_host { 785 uint8_t mih_type; 786 #define MFI_INFO_HOST_PCIX 0x01 787 #define MFI_INFO_HOST_PCIE 0x02 788 #define MFI_INFO_HOST_ISCSI 0x04 789 #define MFI_INFO_HOST_SAS3G 0x08 790 uint8_t mih_reserved[6]; 791 uint8_t mih_port_count; 792 uint64_t mih_port_addr[8]; 793 } __packed; 794 795 /* device interface info */ 796 struct mfi_info_device { 797 uint8_t mid_type; 798 #define MFI_INFO_DEV_SPI 0x01 799 #define MFI_INFO_DEV_SAS3G 0x02 800 #define MFI_INFO_DEV_SATA1 0x04 801 #define MFI_INFO_DEV_SATA3G 0x08 802 uint8_t mid_reserved[6]; 803 uint8_t mid_port_count; 804 uint64_t mid_port_addr[8]; 805 } __packed; 806 807 /* firmware component info */ 808 struct mfi_info_component { 809 char mic_name[8]; 810 char mic_version[32]; 811 char mic_build_date[16]; 812 char mic_build_time[16]; 813 } __packed; 814 815 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 816 struct mfi_ctrl_info { 817 struct mfi_info_pci mci_pci; 818 struct mfi_info_host mci_host; 819 struct mfi_info_device mci_device; 820 821 /* Firmware components that are present and active. */ 822 uint32_t mci_image_check_word; 823 uint32_t mci_image_component_count; 824 struct mfi_info_component mci_image_component[8]; 825 826 /* Firmware components that have been flashed but are inactive */ 827 uint32_t mci_pending_image_component_count; 828 struct mfi_info_component mci_pending_image_component[8]; 829 830 uint8_t mci_max_arms; 831 uint8_t mci_max_spans; 832 uint8_t mci_max_arrays; 833 uint8_t mci_max_lds; 834 char mci_product_name[80]; 835 char mci_serial_number[32]; 836 uint32_t mci_hw_present; 837 #define MFI_INFO_HW_BBU 0x01 838 #define MFI_INFO_HW_ALARM 0x02 839 #define MFI_INFO_HW_NVRAM 0x04 840 #define MFI_INFO_HW_UART 0x08 841 uint32_t mci_current_fw_time; 842 uint16_t mci_max_cmds; 843 uint16_t mci_max_sg_elements; 844 uint32_t mci_max_request_size; 845 uint16_t mci_lds_present; 846 uint16_t mci_lds_degraded; 847 uint16_t mci_lds_offline; 848 uint16_t mci_pd_present; 849 uint16_t mci_pd_disks_present; 850 uint16_t mci_pd_disks_pred_failure; 851 uint16_t mci_pd_disks_failed; 852 uint16_t mci_nvram_size; 853 uint16_t mci_memory_size; 854 uint16_t mci_flash_size; 855 uint16_t mci_ram_correctable_errors; 856 uint16_t mci_ram_uncorrectable_errors; 857 uint8_t mci_cluster_allowed; 858 uint8_t mci_cluster_active; 859 uint16_t mci_max_strips_per_io; 860 861 uint32_t mci_raid_levels; 862 #define MFI_INFO_RAID_0 0x01 863 #define MFI_INFO_RAID_1 0x02 864 #define MFI_INFO_RAID_5 0x04 865 #define MFI_INFO_RAID_1E 0x08 866 #define MFI_INFO_RAID_6 0x10 867 868 uint32_t mci_adapter_ops; 869 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 870 #define MFI_INFO_AOPS_CC_RATE 0x0002 871 #define MFI_INFO_AOPS_BGI_RATE 0x0004 872 #define MFI_INFO_AOPS_RECON_RATE 0x0008 873 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 874 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 875 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 876 #define MFI_INFO_AOPS_BBU 0x0080 877 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 878 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 879 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 880 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 881 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 882 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 883 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 884 885 uint32_t mci_ld_ops; 886 #define MFI_INFO_LDOPS_READ_POLICY 0x01 887 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 888 #define MFI_INFO_LDOPS_IO_POLICY 0x04 889 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 890 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 891 892 struct { 893 uint8_t min; 894 uint8_t max; 895 uint8_t reserved[2]; 896 } __packed mci_stripe_sz_ops; 897 898 uint32_t mci_pd_ops; 899 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 900 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 901 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 902 903 uint32_t mci_pd_mix_support; 904 #define MFI_INFO_PDMIX_SAS 0x01 905 #define MFI_INFO_PDMIX_SATA 0x02 906 #define MFI_INFO_PDMIX_ENCL 0x04 907 #define MFI_INFO_PDMIX_LD 0x08 908 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 909 910 uint8_t mci_ecc_bucket_count; 911 uint8_t mci_reserved2[11]; 912 struct mfi_ctrl_props mci_properties; 913 char mci_package_version[0x60]; 914 uint8_t mci_pad[0x800 - 0x6a0]; 915 } __packed; 916 917 /* logical disk info from MR_DCMD_LD_GET_LIST */ 918 struct mfi_ld { 919 uint8_t mld_target; 920 uint8_t mld_res; 921 uint16_t mld_seq; 922 } __packed; 923 924 struct mfi_ld_list { 925 uint32_t mll_no_ld; 926 uint32_t mll_res; 927 struct { 928 struct mfi_ld mll_ld; 929 uint8_t mll_state; 930 #define MFI_LD_OFFLINE 0x00 931 #define MFI_LD_PART_DEGRADED 0x01 932 #define MFI_LD_DEGRADED 0x02 933 #define MFI_LD_ONLINE 0x03 934 uint8_t mll_res2; 935 uint8_t mll_res3; 936 uint8_t mll_res4; 937 u_quad_t mll_size; 938 } mll_list[MFI_MAX_LD]; 939 } __packed; 940 941 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 942 struct mfi_ld_prop { 943 struct mfi_ld mlp_ld; 944 char mlp_name[16]; 945 uint8_t mlp_cache_policy; 946 uint8_t mlp_acces_policy; 947 uint8_t mlp_diskcache_policy; 948 uint8_t mlp_cur_cache_policy; 949 uint8_t mlp_disable_bgi; 950 uint8_t mlp_res[7]; 951 } __packed; 952 953 struct mfi_ld_parm { 954 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 955 #define MFI_DDF_PRL_RAID0 0x00 956 #define MFI_DDF_PRL_RAID1 0x01 957 #define MFI_DDF_PRL_RAID3 0x03 958 #define MFI_DDF_PRL_RAID4 0x04 959 #define MFI_DDF_PRL_RAID5 0x05 960 #define MFI_DDF_PRL_RAID1E 0x11 961 #define MFI_DDF_PRL_JBOD 0x0f 962 #define MFI_DDF_PRL_CONCAT 0x1f 963 #define MFI_DDF_PRL_RAID5E 0x15 964 #define MFI_DDF_PRL_RAID5EE 0x25 965 #define MFI_DDF_PRL_RAID6 0x16 966 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 967 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 968 #define MFI_DDF_SRL_STRIPED 0x00 969 #define MFI_DDF_SRL_MIRRORED 0x01 970 #define MFI_DDF_SRL_CONCAT 0x02 971 #define MFI_DDF_SRL_SPANNED 0x03 972 uint8_t mpa_stripe_size; 973 uint8_t mpa_no_drv_per_span; 974 uint8_t mpa_span_depth; 975 uint8_t mpa_state; 976 uint8_t mpa_init_state; 977 uint8_t mpa_is_consistent; 978 uint8_t mpa_res1[6]; 979 uint8_t mpa_isSSCD; 980 uint8_t mpa_res[16]; 981 } __packed; 982 983 struct mfi_ld_span { 984 u_quad_t mls_start_block; 985 u_quad_t mls_no_blocks; 986 uint16_t mls_index; 987 uint8_t mls_res[6]; 988 } __packed; 989 990 struct mfi_ld_cfg { 991 struct mfi_ld_prop mlc_prop; 992 struct mfi_ld_parm mlc_parm; 993 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 994 } __packed; 995 996 struct mfi_ld_progress { 997 uint32_t mlp_in_prog; 998 #define MFI_LD_PROG_CC 0x01 999 #define MFI_LD_PROG_BGI 0x02 1000 #define MFI_LD_PROG_FGI 0x04 1001 #define MFI_LD_PROG_RECONSTRUCT 0x08 1002 struct mfi_progress mlp_cc; 1003 struct mfi_progress mlp_bgi; 1004 struct mfi_progress mlp_fgi; 1005 struct mfi_progress mlp_reconstruct; 1006 struct mfi_progress mlp_res[4]; 1007 } __packed; 1008 1009 struct mfi_ld_details { 1010 struct mfi_ld_cfg mld_cfg; 1011 u_quad_t mld_size; 1012 struct mfi_ld_progress mld_progress; 1013 uint16_t mld_clust_own_id; 1014 uint8_t mld_res1; 1015 uint8_t mld_res2; 1016 uint8_t mld_inq_page83[64]; 1017 uint8_t mld_res[16]; 1018 } __packed; 1019 1020 /* physical disk info from MR_DCMD_PD_GET_LIST */ 1021 struct mfi_pd_address { 1022 uint16_t mpa_pd_id; 1023 uint16_t mpa_enc_id; 1024 uint8_t mpa_enc_index; 1025 uint8_t mpa_enc_slot; 1026 uint8_t mpa_scsi_type; 1027 uint8_t mpa_port; 1028 u_quad_t mpa_sas_address[2]; 1029 } __packed; 1030 1031 #define MAX_SYS_PDS 240 1032 struct mfi_pd_list { 1033 uint32_t mpl_size; 1034 uint32_t mpl_no_pd; 1035 struct mfi_pd_address mpl_address[MAX_SYS_PDS]; 1036 } __packed; 1037 #define MFI_PD_LIST_SIZE (256 * sizeof(struct mfi_pd_address) + 8) 1038 1039 struct mfi_pd { 1040 uint16_t mfp_id; 1041 uint16_t mfp_seq; 1042 } __packed; 1043 1044 struct mfi_pd_progress { 1045 uint32_t mfp_in_prog; 1046 #define MFI_PD_PROG_RBLD 0x01 1047 #define MFI_PD_PROG_PR 0x02 1048 #define MFI_PD_PROG_CLEAR 0x04 1049 struct mfi_progress mfp_rebuild; 1050 struct mfi_progress mfp_patrol_read; 1051 struct mfi_progress mfp_clear; 1052 struct mfi_progress mfp_res[4]; 1053 } __packed; 1054 1055 struct mfi_pd_details { 1056 struct mfi_pd mpd_pd; 1057 uint8_t mpd_inq_data[96]; 1058 uint8_t mpd_inq_page83[64]; 1059 uint8_t mpd_no_support; 1060 uint8_t mpd_scsy_type; 1061 uint8_t mpd_port; 1062 uint8_t mpd_speed; 1063 uint32_t mpd_mediaerr_cnt; 1064 uint32_t mpd_othererr_cnt; 1065 uint32_t mpd_predfail_cnt; 1066 uint32_t mpd_last_pred_event; 1067 uint16_t mpd_fw_state; 1068 uint8_t mpd_rdy_for_remove; 1069 uint8_t mpd_link_speed; 1070 uint32_t mpd_ddf_state; 1071 #define MFI_DDF_GUID_FORCED 0x01 1072 #define MFI_DDF_PART_OF_VD 0x02 1073 #define MFI_DDF_GLOB_HOTSPARE 0x04 1074 #define MFI_DDF_HOTSPARE 0x08 1075 #define MFI_DDF_FOREIGN 0x10 1076 #define MFI_DDF_TYPE_MASK 0xf000 1077 #define MFI_DDF_TYPE_UNKNOWN 0x0000 1078 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 1079 #define MFI_DDF_TYPE_SAS 0x2000 1080 #define MFI_DDF_TYPE_SATA 0x3000 1081 #define MFI_DDF_TYPE_FC 0x4000 1082 struct { 1083 uint8_t mpp_cnt; 1084 uint8_t mpp_severed; 1085 uint8_t mpp_res[6]; 1086 u_quad_t mpp_sas_addr[4]; 1087 } __packed mpd_path; 1088 u_quad_t mpd_size; 1089 u_quad_t mpd_no_coerce_size; 1090 u_quad_t mpd_coerce_size; 1091 uint16_t mpd_enc_id; 1092 uint8_t mpd_enc_idx; 1093 uint8_t mpd_enc_slot; 1094 struct mfi_pd_progress mpd_progress; 1095 uint8_t mpd_bblock_full; 1096 uint8_t mpd_unusable; 1097 uint8_t mpd_res[218]; /* size is 512 */ 1098 } __packed; 1099 1100 /* array configuration from MD_DCMD_CONF_GET */ 1101 struct mfi_array { 1102 u_quad_t mar_smallest_pd; 1103 uint8_t mar_no_disk; 1104 uint8_t mar_res1; 1105 uint16_t mar_array_ref; 1106 uint8_t mar_res2[20]; 1107 struct { 1108 struct mfi_pd mar_pd; 1109 uint16_t mar_pd_state; 1110 #define MFI_PD_UNCONFIG_GOOD 0x00 1111 #define MFI_PD_UNCONFIG_BAD 0x01 1112 #define MFI_PD_HOTSPARE 0x02 1113 #define MFI_PD_OFFLINE 0x10 1114 #define MFI_PD_FAILED 0x11 1115 #define MFI_PD_REBUILD 0x14 1116 #define MFI_PD_ONLINE 0x18 1117 #define MFI_PD_COPYBACK 0x20 1118 #define MFI_PD_SYSTEM 0x40 1119 #define MFI_PD_JBOD MFI_PD_SYSTEM 1120 uint8_t mar_enc_pd; 1121 uint8_t mar_enc_slot; 1122 } pd[MFI_MAX_PD_ARRAY]; 1123 } __packed; 1124 1125 /* informations from MR_DCMD_BBU_GET_CAPACITY_INFO */ 1126 struct mfi_bbu_capacity_info { 1127 uint16_t relative_charge; 1128 uint16_t absolute_charge; 1129 uint16_t remaining_capacity; 1130 uint16_t full_charge_capacity; 1131 uint16_t run_time_to_empty; 1132 uint16_t average_time_to_empty; 1133 uint16_t average_time_to_full; 1134 uint16_t cycle_count; 1135 uint16_t max_error; 1136 uint16_t remaining_capacity_alarm; 1137 uint16_t remaining_time_alarm; 1138 uint8_t reserved[26]; 1139 } __packed; 1140 1141 /* informations from MR_DCMD_BBU_GET_DESIGN_INFO */ 1142 struct mfi_bbu_design_info { 1143 uint32_t mfg_date; 1144 uint16_t design_capacity; 1145 uint16_t design_voltage; 1146 uint16_t spec_info; 1147 uint16_t serial_number; 1148 uint16_t pack_stat_config; 1149 uint8_t mfg_name[12]; 1150 uint8_t device_name[8]; 1151 uint8_t device_chemistry[8]; 1152 uint8_t mfg_data[8]; 1153 uint8_t reserved[17]; 1154 } __packed; 1155 1156 struct mfi_ibbu_state { 1157 uint16_t gas_guage_status; 1158 uint16_t relative_charge; 1159 uint16_t charger_system_state; 1160 uint16_t charger_system_ctrl; 1161 uint16_t charging_current; 1162 uint16_t absolute_charge; 1163 uint16_t max_error; 1164 uint8_t reserved[18]; 1165 } __packed; 1166 1167 struct mfi_bbu_state { 1168 uint16_t gas_guage_status; 1169 uint16_t relative_charge; 1170 uint16_t charger_status; 1171 uint16_t remaining_capacity; 1172 uint16_t full_charge_capacity; 1173 uint8_t is_SOH_good; 1174 uint8_t reserved[21]; 1175 } __packed; 1176 1177 union mfi_bbu_status_detail { 1178 struct mfi_ibbu_state ibbu; 1179 struct mfi_bbu_state bbu; 1180 }; 1181 1182 /* informations from MR_DCMD_BBU_GET_STATUS */ 1183 struct mfi_bbu_status { 1184 uint8_t battery_type; 1185 #define MFI_BBU_TYPE_NONE 0 1186 #define MFI_BBU_TYPE_IBBU 1 1187 #define MFI_BBU_TYPE_BBU 2 1188 uint8_t reserved; 1189 uint16_t voltage; 1190 int16_t current; 1191 uint16_t temperature; 1192 uint32_t fw_status; 1193 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1194 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1195 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1196 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1197 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1198 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1199 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1200 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1201 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1202 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1203 uint8_t pad[20]; 1204 union mfi_bbu_status_detail detail; 1205 } __packed; 1206 1207 struct mfi_hotspare { 1208 struct mfi_pd mhs_pd; 1209 uint8_t mhs_type; 1210 #define MFI_PD_HS_DEDICATED 0x01 1211 #define MFI_PD_HS_REVERTIBLE 0x02 1212 #define MFI_PD_HS_ENC_AFFINITY 0x04 1213 uint8_t mhs_res[2]; 1214 uint8_t mhs_array_max; 1215 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1216 } __packed; 1217 1218 struct mfi_conf { 1219 uint32_t mfc_size; 1220 uint16_t mfc_no_array; 1221 uint16_t mfc_array_size; 1222 uint16_t mfc_no_ld; 1223 uint16_t mfc_ld_size; 1224 uint16_t mfc_no_hs; 1225 uint16_t mfc_hs_size; 1226 uint8_t mfc_res[16]; 1227 /* 1228 * XXX this is a ridiculous hack and does not reflect reality 1229 * Structures are actually indexed and therefore need pointer 1230 * math to reach. We need the size of this structure first so 1231 * call it with the size of this structure and then use the returned 1232 * values to allocate memory and do the transfer of the whole structure 1233 * then calculate pointers to each of these structures. 1234 */ 1235 struct mfi_array mfc_array[1]; 1236 struct mfi_ld_cfg mfc_ld[1]; 1237 struct mfi_hotspare mfc_hs[1]; 1238 } __packed; 1239 1240 /* ThunderBolt support */ 1241 1242 /* 1243 * Raid Context structure which describes MegaRAID specific IO Paramenters 1244 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1245 */ 1246 typedef struct _mpi2_scsi_io_vendor_unique { 1247 uint16_t resvd0; /* 0x00 - 0x01 */ 1248 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1249 uint8_t regLockFlags; 1250 uint8_t armId; 1251 uint16_t TargetID; /* 0x06 - 0x07 */ 1252 1253 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1254 1255 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1256 1257 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1258 uint8_t exStatus; /* 0x16 */ 1259 uint8_t Status; /* 0x17 status */ 1260 1261 uint8_t RAIDFlags; /* 0x18 */ 1262 uint8_t numSGE; /* 0x19 numSge */ 1263 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1264 uint8_t spanArm; /* 0x1C */ 1265 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1266 } mpi2_scsi_io_vendor_unique, mpi25_scsi_io_vendor_unique; 1267 1268 /***************************************************************************** 1269 * 1270 * Message Functions 1271 * 1272 *****************************************************************************/ 1273 1274 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1275 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1276 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1277 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1278 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1279 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1280 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1281 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1282 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1283 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1284 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1285 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1286 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1287 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1288 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1289 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1290 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1291 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1292 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1293 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1294 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1295 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1296 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1297 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1298 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1299 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1300 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1301 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1302 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1303 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1304 1305 /* Doorbell functions */ 1306 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1307 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1308 1309 /***************************************************************************** 1310 * 1311 * MPI Version Definitions 1312 * 1313 *****************************************************************************/ 1314 1315 #define MPI2_VERSION_MAJOR (0x02) 1316 #define MPI2_VERSION_MINOR (0x00) 1317 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1318 #define MPI2_VERSION_MAJOR_SHIFT (8) 1319 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1320 #define MPI2_VERSION_MINOR_SHIFT (0) 1321 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1322 MPI2_VERSION_MINOR) 1323 1324 #define MPI2_VERSION_02_00 (0x0200) 1325 1326 /* versioning for this MPI header set */ 1327 #define MPI2_HEADER_VERSION_UNIT (0x10) 1328 #define MPI2_HEADER_VERSION_DEV (0x00) 1329 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1330 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1331 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1332 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1333 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1334 MPI2_HEADER_VERSION_DEV) 1335 1336 1337 /* IOCInit Request message */ 1338 struct mpi2_ioc_init_request { 1339 uint8_t WhoInit; /* 0x00 */ 1340 uint8_t Reserved1; /* 0x01 */ 1341 uint8_t ChainOffset; /* 0x02 */ 1342 uint8_t Function; /* 0x03 */ 1343 uint16_t Reserved2; /* 0x04 */ 1344 uint8_t Reserved3; /* 0x06 */ 1345 uint8_t MsgFlags; /* 0x07 */ 1346 uint8_t VP_ID; /* 0x08 */ 1347 uint8_t VF_ID; /* 0x09 */ 1348 uint16_t Reserved4; /* 0x0A */ 1349 uint16_t MsgVersion; /* 0x0C */ 1350 uint16_t HeaderVersion; /* 0x0E */ 1351 uint32_t Reserved5; /* 0x10 */ 1352 uint16_t Reserved6; /* 0x14 */ 1353 uint8_t Reserved7; /* 0x16 */ 1354 uint8_t HostMSIxVectors; /* 0x17 */ 1355 uint16_t Reserved8; /* 0x18 */ 1356 uint16_t SystemRequestFrameSize; /* 0x1A */ 1357 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1358 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1359 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1360 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1361 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1362 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1363 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1364 uint64_t TimeStamp; /* 0x40 */ 1365 }; 1366 1367 /* WhoInit values */ 1368 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1369 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1370 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1371 #define MPI2_WHOINIT_PCI_PEER (0x03) 1372 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1373 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1374 1375 struct mpi2_sge_chain_union { 1376 uint16_t Length; 1377 uint8_t NextChainOffset; 1378 uint8_t Flags; 1379 union { 1380 uint32_t Address32; 1381 uint64_t Address64; 1382 } u; 1383 }; 1384 1385 struct mpi2_ieee_sge_simple32 { 1386 uint32_t Address; 1387 uint32_t FlagsLength; 1388 }; 1389 1390 struct mpi2_ieee_sge_simple64 { 1391 uint64_t Address; 1392 uint32_t Length; 1393 uint16_t Reserved1; 1394 uint8_t Reserved2; 1395 uint8_t Flags; 1396 }; 1397 1398 typedef union _mpi2_ieee_simple_union { 1399 struct mpi2_ieee_sge_simple32 Simple32; 1400 struct mpi2_ieee_sge_simple64 Simple64; 1401 } mpi2_ieee_simple_union; 1402 1403 typedef struct _mpi2_sge_simple_union { 1404 uint32_t FlagsLength; 1405 union { 1406 uint32_t Address32; 1407 uint64_t Address64; 1408 } u; 1409 } mpi2_sge_simple_union; 1410 1411 /* MPI 2.5 SGLs */ 1412 1413 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1414 1415 struct mpi25_ieee_sge_chain64 { 1416 uint64_t Address; 1417 uint32_t Length; 1418 uint16_t Reserved1; 1419 uint8_t NextChainOffset; 1420 uint8_t Flags; 1421 }; 1422 1423 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1424 1425 /**************************************************************************** 1426 * IEEE SGE field definitions and masks 1427 ****************************************************************************/ 1428 1429 /* Flags field bit definitions */ 1430 1431 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1432 1433 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1434 1435 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1436 1437 /* Element Type */ 1438 1439 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1440 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1441 1442 /* Data Location Address Space */ 1443 1444 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1445 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1446 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1447 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1448 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1449 1450 /* Address Size */ 1451 1452 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1453 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1454 1455 /*******************/ 1456 /* SCSI IO Control bits */ 1457 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1458 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1459 1460 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1461 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1462 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1463 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1464 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1465 1466 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1467 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1468 1469 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1470 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1471 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1472 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1473 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1474 1475 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1476 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1477 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1478 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1479 1480 /*******************/ 1481 1482 typedef struct { 1483 uint8_t CDB[20]; /* 0x00 */ 1484 uint32_t PrimaryReferenceTag; /* 0x14 */ 1485 uint16_t PrimaryApplicationTag; /* 0x18 */ 1486 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1487 uint32_t TransferLength; /* 0x1C */ 1488 } mpi2_scsi_io_cdb_eedp32; 1489 1490 1491 typedef union _mpi2_ieee_sge_chain_union { 1492 struct mpi2_ieee_sge_simple32 Chain32; 1493 struct mpi25_ieee_sge_chain64 Chain64; 1494 } mpi2_ieee_sge_chain_union; 1495 1496 typedef union _mpi2_simple_sge_union { 1497 mpi2_sge_simple_union MpiSimple; 1498 mpi2_ieee_simple_union IeeeSimple; 1499 } mpi2_simple_sge_union; 1500 1501 typedef union _mpi2_sge_io_union { 1502 mpi2_sge_simple_union MpiSimple; 1503 struct mpi2_sge_chain_union MpiChain; 1504 mpi2_ieee_simple_union IeeeSimple; 1505 mpi2_ieee_sge_chain_union IeeeChain; 1506 } mpi2_sge_io_union; 1507 1508 typedef union { 1509 uint8_t CDB32[32]; 1510 mpi2_scsi_io_cdb_eedp32 EEDP32; 1511 mpi2_sge_simple_union SGE; 1512 } mpi2_scsi_io_cdb_union; 1513 1514 1515 1516 /********/ 1517 1518 /* 1519 * RAID SCSI IO Request Message 1520 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1521 */ 1522 struct mfi_mpi2_request_raid_scsi_io { 1523 uint16_t DevHandle; /* 0x00 */ 1524 uint8_t ChainOffset; /* 0x02 */ 1525 uint8_t Function; /* 0x03 */ 1526 uint16_t Reserved1; /* 0x04 */ 1527 uint8_t Reserved2; /* 0x06 */ 1528 uint8_t MsgFlags; /* 0x07 */ 1529 uint8_t VP_ID; /* 0x08 */ 1530 uint8_t VF_ID; /* 0x09 */ 1531 uint16_t Reserved3; /* 0x0A */ 1532 uint32_t SenseBufferLowAddress; /* 0x0C */ 1533 uint16_t SGLFlags; /* 0x10 */ 1534 uint8_t SenseBufferLength; /* 0x12 */ 1535 uint8_t Reserved4; /* 0x13 */ 1536 uint8_t SGLOffset0; /* 0x14 */ 1537 uint8_t SGLOffset1; /* 0x15 */ 1538 uint8_t SGLOffset2; /* 0x16 */ 1539 uint8_t SGLOffset3; /* 0x17 */ 1540 uint32_t SkipCount; /* 0x18 */ 1541 uint32_t DataLength; /* 0x1C */ 1542 uint32_t BidirectionalDataLength; /* 0x20 */ 1543 uint16_t IoFlags; /* 0x24 */ 1544 uint16_t EEDPFlags; /* 0x26 */ 1545 uint32_t EEDPBlockSize; /* 0x28 */ 1546 uint32_t SecondaryReferenceTag; /* 0x2C */ 1547 uint16_t SecondaryApplicationTag; /* 0x30 */ 1548 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1549 uint8_t LUN[8]; /* 0x34 */ 1550 uint32_t Control; /* 0x3C */ 1551 mpi2_scsi_io_cdb_union CDB; /* 0x40 */ 1552 mpi2_scsi_io_vendor_unique RaidContext; /* 0x60 */ 1553 mpi2_sge_io_union SGL; /* 0x80 */ 1554 } __packed; 1555 1556 /* 1557 * MPT RAID MFA IO Descriptor. 1558 */ 1559 typedef struct _mfi_raid_mfa_io_descriptor { 1560 uint32_t RequestFlags : 8; 1561 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1562 uint32_t MessageAddress2; /* bits 61:32 */ 1563 } mfi_raid_mfa_io_request_descriptor; 1564 1565 struct mfi_mpi2_request_header { 1566 uint8_t RequestFlags; /* 0x00 */ 1567 uint8_t MSIxIndex; /* 0x01 */ 1568 uint16_t SMID; /* 0x02 */ 1569 uint16_t LMID; /* 0x04 */ 1570 }; 1571 1572 /* defines for the RequestFlags field */ 1573 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1574 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1575 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1576 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1577 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1578 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1579 1580 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1581 1582 struct mfi_mpi2_request_high_priority { 1583 struct mfi_mpi2_request_header header; 1584 uint16_t reserved; 1585 }; 1586 1587 struct mfi_mpi2_request_scsi_io { 1588 struct mfi_mpi2_request_header header; 1589 uint16_t scsi_io_dev_handle; 1590 }; 1591 1592 struct mfi_mpi2_request_scsi_target { 1593 struct mfi_mpi2_request_header header; 1594 uint16_t scsi_target_io_index; 1595 }; 1596 1597 /* Request Descriptors */ 1598 union mfi_mpi2_request_descriptor { 1599 struct mfi_mpi2_request_header header; 1600 struct mfi_mpi2_request_high_priority high_priority; 1601 struct mfi_mpi2_request_scsi_io scsi_io; 1602 struct mfi_mpi2_request_scsi_target scsi_target; 1603 uint64_t words; 1604 }; 1605 1606 /* 1607 * Request descriptor types 1608 */ 1609 #define MFI_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1610 #define MFI_REQ_DESCRIPT_FLAGS_MFA 0x1 1611 #define MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 0x1 1612 1613 #define MFI_FUSION_FP_DEFAULT_TIMEOUT 0x14 1614 1615 struct mfi_mpi2_reply_header { 1616 uint8_t ReplyFlags; /* 0x00 */ 1617 uint8_t MSIxIndex; /* 0x01 */ 1618 uint16_t SMID; /* 0x02 */ 1619 }; 1620 1621 /* defines for the ReplyFlags field */ 1622 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1623 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1624 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1625 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1626 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1627 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1628 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1629 1630 /* values for marking a reply descriptor as unused */ 1631 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1632 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1633 1634 struct mfi_mpi2_reply_default { 1635 struct mfi_mpi2_reply_header header; 1636 uint32_t DescriptorTypeDependent2; 1637 }; 1638 1639 struct mfi_mpi2_reply_address { 1640 struct mfi_mpi2_reply_header header; 1641 uint32_t ReplyFrameAddress; 1642 }; 1643 1644 struct mfi_mpi2_reply_scsi_io { 1645 struct mfi_mpi2_reply_header header; 1646 uint16_t TaskTag; /* 0x04 */ 1647 uint16_t Reserved1; /* 0x06 */ 1648 }; 1649 1650 struct mfi_mpi2_reply_target_assist { 1651 struct mfi_mpi2_reply_header header; 1652 uint8_t SequenceNumber; /* 0x04 */ 1653 uint8_t Reserved1; /* 0x04 */ 1654 uint16_t IoIndex; /* 0x06 */ 1655 }; 1656 1657 struct mfi_mpi2_reply_target_cmd_buffer { 1658 struct mfi_mpi2_reply_header header; 1659 uint8_t SequenceNumber; /* 0x04 */ 1660 uint8_t Flags; /* 0x04 */ 1661 uint16_t InitiatorDevHandle; /* 0x06 */ 1662 uint16_t IoIndex; /* 0x06 */ 1663 }; 1664 1665 struct mfi_mpi2_reply_raid_accel { 1666 struct mfi_mpi2_reply_header header; 1667 uint8_t SequenceNumber; /* 0x04 */ 1668 uint32_t Reserved; /* 0x04 */ 1669 }; 1670 1671 /* union of Reply Descriptors */ 1672 union mfi_mpi2_reply_descriptor { 1673 struct mfi_mpi2_reply_header header; 1674 struct mfi_mpi2_reply_scsi_io scsi_io; 1675 struct mfi_mpi2_reply_target_assist target_assist; 1676 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1677 struct mfi_mpi2_reply_raid_accel raid_accel; 1678 struct mfi_mpi2_reply_default reply_default; 1679 uint64_t words; 1680 }; 1681 1682 struct io_request_info { 1683 uint64_t ldStartBlock; 1684 uint32_t numBlocks; 1685 uint16_t ldTgtId; 1686 uint8_t isRead; 1687 uint16_t devHandle; 1688 uint64_t pdBlock; 1689 uint8_t fpOkForIo; 1690 }; 1691 1692 /* 1693 * Define MFI Address Context union. 1694 */ 1695 #ifdef MFI_ADDRESS_IS_uint64_t 1696 typedef uint64_t mfi_address; 1697 #else 1698 typedef union _mfi_address { 1699 struct { 1700 uint32_t addressLow; 1701 uint32_t addressHigh; 1702 } u; 1703 uint64_t address; 1704 } mfi_address; 1705 #endif 1706 1707 #define MEGASAS_MAX_NAME 32 1708 #define MEGASAS_VERSION "4.23" 1709 1710 #endif /* _DEV_IC_MFIREG_H_ */ 1711
Indexes created Mon Oct 20 01:09:56 GMT 2025