mfireg.h revision 1.8.30.3
1 /* $NetBSD: mfireg.h,v 1.8.30.3 2022/09/16 18:30:15 martin Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Copyright (c) 2007 LSI Corp. 21 * Copyright (c) 2007 Rajesh Prabhakaran. 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 #ifndef _DEV_IC_MFIREG_H_ 47 #define _DEV_IC_MFIREG_H_ 48 49 /* management interface constants */ 50 #define MFI_MGMT_VD 0x01 51 #define MFI_MGMT_SD 0x02 52 53 /* generic constants */ 54 #define MFI_FRAME_SIZE 64 55 #define MFI_SENSE_SIZE 128 56 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 57 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 58 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 59 #define MFI_INVALID_CTX 0xffffffff 60 #define MFI_ENABLE_INTR 0x01 61 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 62 #define MFI_SECTOR_LEN 512 63 64 /* register offsets */ 65 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 66 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 67 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 68 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 69 #define MFI_IDB 0x20 /* inbound doorbell */ 70 #define MFI_ISTS 0x24 /* inbound intr stat */ 71 #define MFI_IMSK 0x28 /* inbound intr mask */ 72 #define MFI_ODB 0x2c /* outbound doorbell */ 73 #define MFI_OSTS 0x30 /* outbound intr stat */ 74 #define MFI_OMSK 0x34 /* outbound inter mask */ 75 #define MFI_IQP 0x40 /* inbound queue port */ 76 #define MFI_OQP 0x44 /* outbound queue port */ 77 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 78 #define MFI_OSP 0xb0 /* outbound scratch pad */ 79 80 /* ThunderBolt specific Register */ 81 #define MFI_RPI 0x6c /* reply_post_host_index */ 82 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 83 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 84 85 /* OCR registers */ 86 #define MFI_WSR 0x004 /* write sequence register */ 87 #define MFI_HDR 0x008 /* host diagnostic register */ 88 #define MFI_RSR 0x3c3 /* Reset Status Register */ 89 90 /* OCR specific flags */ 91 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 92 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 93 94 /* 95 * skinny specific changes 96 */ 97 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 98 #define MFI_IQPL 0x000000c0 99 #define MFI_IQPH 0x000000c4 100 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 101 102 /* * firmware states */ 103 #define MFI_STATE_MASK 0xf0000000 104 #define MFI_STATE_UNDEFINED 0x00000000 105 #define MFI_STATE_BB_INIT 0x10000000 106 #define MFI_STATE_FW_INIT 0x40000000 107 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 108 #define MFI_STATE_FW_INIT_2 0x70000000 109 #define MFI_STATE_DEVICE_SCAN 0x80000000 110 #define MFI_STATE_FLUSH_CACHE 0xa0000000 111 #define MFI_STATE_READY 0xb0000000 112 #define MFI_STATE_OPERATIONAL 0xc0000000 113 #define MFI_STATE_FAULT 0xf0000000 114 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 115 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 116 #define MFI_STATE_HOSTMEMREQD_MASK 0x08000000 117 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 118 #define MFI_RESET_REQUIRED 0x00000001 119 120 /* ThunderBolt Support */ 121 #define MFI_STATE_TB_MASK 0xf0000000 122 #define MFI_STATE_TB_RESET 0x00000000 123 #define MFI_STATE_TB_READY 0x10000000 124 #define MFI_STATE_TB_OPERATIONAL 0x20000000 125 #define MFI_STATE_TB_FAULT 0x40000000 126 127 /* command reset register */ 128 #define MFI_INIT_ABORT 0x00000001 129 #define MFI_INIT_READY 0x00000002 130 #define MFI_INIT_MFIMODE 0x00000004 131 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 132 #define MFI_RESET_FLAGS MFI_INIT_READY | MFI_INIT_MFIMODE | \ 133 MFI_INIT_ABORT 134 #define MFI_INIT_HOTPLUG 0x00000010 135 136 /* ADP reset flags */ 137 #define MFI_STOP_ADP 0x00000020 138 #define MFI_ADP_RESET 0x00000040 139 #define DIAG_WRITE_ENABLE 0x00000080 140 #define DIAG_RESET_ADAPTER 0x00000004 141 142 /* mfi Frame flags */ 143 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 144 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 145 #define MFI_FRAME_SGL32 0x0000 146 #define MFI_FRAME_SGL64 0x0002 147 #define MFI_FRAME_SENSE32 0x0000 148 #define MFI_FRAME_SENSE64 0x0004 149 #define MFI_FRAME_DIR_NONE 0x0000 150 #define MFI_FRAME_DIR_WRITE 0x0008 151 #define MFI_FRAME_DIR_READ 0x0010 152 #define MFI_FRAME_DIR_BOTH 0x0018 153 #define MFI_FRAME_IEEE_SGL 0x0020 154 155 /* ThunderBolt Specific */ 156 157 /* 158 * Pre-TB command size and TB command size. 159 * We will be checking it at the load time for the time being 160 */ 161 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 162 163 #define MEGASAS_THUNDERBOLT_MSG_ALIGNMENT 256 164 /* 165 * We are defining only 128 byte message to reduce memory move over head 166 * and also it will reduce the SRB extension size by 128byte compared with 167 * 256 message size 168 */ 169 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 170 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 171 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 172 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 173 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 174 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 175 176 /* 177 * Calculating how many SGEs allowed in an allocated main message 178 * (size of the Message - Raid SCSI IO message size(except SGE)) 179 * / size of SGE 180 * (0x100 - (0x90 - 0x10)) / 0x10 = 8 181 */ 182 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG \ 183 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - \ 184 (sizeof(struct mfi_mpi2_request_raid_scsi_io) - sizeof(mpi2_sge_io_union))\ 185 ) / sizeof(mpi2_sge_io_union)) 186 187 /* 188 * (Command frame size allocated in SRB ext - Raid SCSI IO message size) 189 * / size of SGL ; 190 * (1280 - 256) / 16 = 64 191 */ 192 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG \ 193 ((MR_COMMAND_SIZE - MEGASAS_THUNDERBOLT_NEW_MSG_SIZE) / \ 194 sizeof(mpi2_sge_io_union)) 195 196 /* 197 * This is the offset in number of 4 * 32bit words to the next chain 198 * (0x100 - 0x10)/0x10 = 0xF(15) 199 */ 200 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG \ 201 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - sizeof(mpi2_sge_io_union)) / 16) 202 203 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MPT_PTMSG \ 204 (offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16) 205 206 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 207 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 208 209 #define MR_INTERNAL_MFI_FRAMES_SMID 1 210 #define MR_CTRL_EVENT_WAIT_SMID 2 211 #define MR_INTERNAL_DRIVER_RESET_SMID 3 212 213 /* mfi command opcodes */ 214 #define MFI_CMD_INIT 0x00 215 #define MFI_CMD_LD_READ 0x01 216 #define MFI_CMD_LD_WRITE 0x02 217 #define MFI_CMD_LD_SCSI_IO 0x03 218 #define MFI_CMD_PD_SCSI_IO 0x04 219 #define MFI_CMD_DCMD 0x05 220 #define MFI_CMD_ABORT 0x06 221 #define MFI_CMD_SMP 0x07 222 #define MFI_CMD_STP 0x08 223 224 /* direct commands */ 225 #define MR_DCMD_CTRL_GET_INFO 0x01010000 226 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 227 #define MR_FLUSH_CTRL_CACHE 0x01 228 #define MR_FLUSH_DISK_CACHE 0x02 229 #define MR_DCMD_CTRL_HOST_MEM_ALLOC 0x0100e100 230 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 231 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 232 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 233 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 234 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 235 #define MR_DCMD_PD_GET_LIST 0x02010000 236 #define MR_DCMD_PD_LIST_QUERY 0x02010100 237 #define MR_DCMD_PD_GET_INFO 0x02020000 238 #define MR_DCMD_PD_SET_STATE 0x02030100 239 #define MR_DCMD_PD_REBUILD 0x02040100 240 #define MR_DCMD_PD_BLINK 0x02070100 241 #define MR_DCMD_PD_UNBLINK 0x02070200 242 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 243 #define MR_DCMD_LD_SYNC 0x0300e102 244 #define MR_DCMD_LD_GET_LIST 0x03010000 245 #define MR_DCMD_LD_GET_INFO 0x03020000 246 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 247 #define MR_DCMD_CONF_GET 0x04010000 248 #define MR_DCMD_CFG_ADD 0x04020000 249 #define MR_DCMD_CFG_CLEAR 0x04030000 250 #define MR_DCMD_CFG_MAKE_SPARE 0x04040000 251 #define MR_DCMD_CFG_FOREIGN_SCAN 0x04060100 252 #define MR_DCMD_CFG_FOREIGN_CLEAR 0x04060500 253 #define MR_DCMD_BBU_GET_STATUS 0x05010000 254 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 255 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 256 #define MR_DCMD_CLUSTER 0x08000000 257 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 258 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 259 260 #define MR_DCMD_SPEAKER_GET 0x01030100 261 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 262 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 263 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 264 #define MR_DCMD_SPEAKER_TEST 0x01030500 265 266 /* mailbox bytes in direct command */ 267 #define MFI_MBOX_SIZE 12 268 269 union mfi_mbox { 270 uint8_t b[MFI_MBOX_SIZE]; 271 uint16_t s[6]; 272 uint32_t w[3]; 273 } __packed __aligned(4); 274 275 /* mfi completion codes */ 276 typedef enum { 277 MFI_STAT_OK = 0x00, 278 MFI_STAT_INVALID_CMD = 0x01, 279 MFI_STAT_INVALID_DCMD = 0x02, 280 MFI_STAT_INVALID_PARAMETER = 0x03, 281 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 282 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 283 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 284 MFI_STAT_APP_IN_USE = 0x07, 285 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 286 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 287 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 288 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 289 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 290 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 291 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 292 MFI_STAT_FLASH_BUSY = 0x0f, 293 MFI_STAT_FLASH_ERROR = 0x10, 294 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 295 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 296 MFI_STAT_FLASH_NOT_OPEN = 0x13, 297 MFI_STAT_FLASH_NOT_STARTED = 0x14, 298 MFI_STAT_FLUSH_FAILED = 0x15, 299 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 300 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 301 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 302 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 303 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 304 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 305 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 306 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 307 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 308 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 309 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 310 MFI_STAT_MFC_HW_ERROR = 0x21, 311 MFI_STAT_NO_HW_PRESENT = 0x22, 312 MFI_STAT_NOT_FOUND = 0x23, 313 MFI_STAT_NOT_IN_ENCL = 0x24, 314 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 315 MFI_STAT_PD_TYPE_WRONG = 0x26, 316 MFI_STAT_PR_DISABLED = 0x27, 317 MFI_STAT_ROW_INDEX_INVALID = 0x28, 318 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 319 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 320 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 321 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 322 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 323 MFI_STAT_SCSI_IO_FAILED = 0x2e, 324 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 325 MFI_STAT_SHUTDOWN_FAILED = 0x30, 326 MFI_STAT_TIME_NOT_SET = 0x31, 327 MFI_STAT_WRONG_STATE = 0x32, 328 MFI_STAT_LD_OFFLINE = 0x33, 329 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 330 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 331 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 332 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 333 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 334 MFI_STAT_INVALID_STATUS = 0xff 335 } mfi_status_t; 336 337 typedef enum { 338 MFI_EVT_CLASS_DEBUG = -2, 339 MFI_EVT_CLASS_PROGRESS = -1, 340 MFI_EVT_CLASS_INFO = 0, 341 MFI_EVT_CLASS_WARNING = 1, 342 MFI_EVT_CLASS_CRITICAL = 2, 343 MFI_EVT_CLASS_FATAL = 3, 344 MFI_EVT_CLASS_DEAD = 4 345 } mfi_evt_class_t; 346 347 typedef enum { 348 MFI_EVT_LOCALE_LD = 0x0001, 349 MFI_EVT_LOCALE_PD = 0x0002, 350 MFI_EVT_LOCALE_ENCL = 0x0004, 351 MFI_EVT_LOCALE_BBU = 0x0008, 352 MFI_EVT_LOCALE_SAS = 0x0010, 353 MFI_EVT_LOCALE_CTRL = 0x0020, 354 MFI_EVT_LOCALE_CONFIG = 0x0040, 355 MFI_EVT_LOCALE_CLUSTER = 0x0080, 356 MFI_EVT_LOCALE_ALL = 0xffff 357 } mfi_evt_locale_t; 358 359 typedef enum { 360 MR_EVT_ARGS_NONE = 0x00, 361 MR_EVT_ARGS_CDB_SENSE, 362 MR_EVT_ARGS_LD, 363 MR_EVT_ARGS_LD_COUNT, 364 MR_EVT_ARGS_LD_LBA, 365 MR_EVT_ARGS_LD_OWNER, 366 MR_EVT_ARGS_LD_LBA_PD_LBA, 367 MR_EVT_ARGS_LD_PROG, 368 MR_EVT_ARGS_LD_STATE, 369 MR_EVT_ARGS_LD_STRIP, 370 MR_EVT_ARGS_PD, 371 MR_EVT_ARGS_PD_ERR, 372 MR_EVT_ARGS_PD_LBA, 373 MR_EVT_ARGS_PD_LBA_LD, 374 MR_EVT_ARGS_PD_PROG, 375 MR_EVT_ARGS_PD_STATE, 376 MR_EVT_ARGS_PCI, 377 MR_EVT_ARGS_RATE, 378 MR_EVT_ARGS_STR, 379 MR_EVT_ARGS_TIME, 380 MR_EVT_ARGS_ECC 381 } mfi_evt_args; 382 383 /* XXX should be in mfi_evt_args ? */ 384 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 385 #define MR_EVT_ARGS_PD_ADDRESS 0x1d 386 #define MR_EVT_PD_INSERTED 0x005b 387 #define MR_EVT_PD_REMOVED 0x0070 388 #define MR_EVT_PD_STATE_CHANGE 0x0072 389 #define MR_EVT_LD_CHANGE 0x0051 390 #define MR_EVT_LD_CREATED 0x008a 391 #define MR_EVT_LD_DELETED 0x008b 392 #define MR_EVT_PD_REMOVED_EXT 0x00f8 393 #define MR_EVT_PD_INSERTED_EXT 0x00f7 394 395 396 397 typedef enum { 398 MR_PD_QUERY_TYPE_ALL = 0, 399 MR_PD_QUERY_TYPE_STATE = 1, 400 MR_PD_QUERY_TYPE_POWER_STATE = 2, 401 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 402 MR_PD_QUERY_TYPE_SPEED = 4, 403 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 404 } mfi_pd_query_type; 405 406 /* driver definitions */ 407 #define MFI_MAX_PD_CHANNELS 2 408 #define MFI_MAX_PD_ARRAY 32 409 #define MFI_MAX_LD_CHANNELS 2 410 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 411 #define MFI_MAX_CHANNEL_DEVS 128 412 #define MFI_DEFAULT_ID -1 413 #define MFI_MAX_LUN 8 414 #define MFI_MAX_LD 64 415 #define MFI_MAX_SPAN 8 416 #define MFI_MAX_ARRAY_DEDICATED 16 417 #define MFI_MAX_PD 256 418 419 /* sense buffer */ 420 struct mfi_sense { 421 uint8_t mse_data[MFI_SENSE_SIZE]; 422 } __packed; 423 424 /* scatter gather elements */ 425 struct mfi_sg32 { 426 uint32_t addr; 427 uint32_t len; 428 } __packed; 429 430 struct mfi_sg64 { 431 uint64_t addr; 432 uint32_t len; 433 } __packed; 434 435 struct mfi_sg_ieee { 436 uint64_t addr; 437 uint32_t len; 438 uint32_t flags; 439 } __packed; 440 441 442 union mfi_sgl { 443 struct mfi_sg32 sg32[1]; 444 struct mfi_sg64 sg64[1]; 445 struct mfi_sg_ieee sg_ieee[1]; 446 } __packed; 447 448 /* message frame */ 449 struct mfi_frame_header { 450 uint8_t mfh_cmd; 451 uint8_t mfh_sense_len; 452 uint8_t mfh_cmd_status; 453 uint8_t mfh_scsi_status; 454 uint8_t mfh_target_id; 455 uint8_t mfh_lun_id; 456 uint8_t mfh_cdb_len; 457 uint8_t mfh_sg_count; 458 uint32_t mfh_context; 459 uint32_t mfh_pad0; 460 uint16_t mfh_flags; 461 uint16_t mfh_timeout; 462 uint32_t mfh_data_len; 463 } __packed; 464 465 union mfi_sgl_frame { 466 struct mfi_sg32 sge32[8]; 467 struct mfi_sg64 sge64[5]; 468 469 } __packed; 470 471 struct mfi_init_frame { 472 struct mfi_frame_header mif_header; 473 uint32_t mif_qinfo_new_addr_lo; 474 uint32_t mif_qinfo_new_addr_hi; 475 uint32_t mif_qinfo_old_addr_lo; 476 uint32_t mif_qinfo_old_addr_hi; 477 uint32_t driver_ver_lo; /* 0x28 */ 478 uint32_t driver_ver_hi; /* 0x2c */ 479 uint32_t reserved[4]; 480 } __packed; 481 482 /* queue init structure */ 483 struct mfi_init_qinfo { 484 uint32_t miq_flags; 485 uint32_t miq_rq_entries; 486 uint32_t miq_rq_addr_lo; 487 uint32_t miq_rq_addr_hi; 488 uint32_t miq_pi_addr_lo; 489 uint32_t miq_pi_addr_hi; 490 uint32_t miq_ci_addr_lo; 491 uint32_t miq_ci_addr_hi; 492 } __packed; 493 494 #define MFI_IO_FRAME_SIZE 40 495 struct mfi_io_frame { 496 struct mfi_frame_header mif_header; 497 uint32_t mif_sense_addr_lo; 498 uint32_t mif_sense_addr_hi; 499 uint32_t mif_lba_lo; 500 uint32_t mif_lba_hi; 501 union mfi_sgl mif_sgl; 502 } __packed; 503 504 #define MFI_PASS_FRAME_SIZE 48 505 struct mfi_pass_frame { 506 struct mfi_frame_header mpf_header; 507 uint32_t mpf_sense_addr_lo; 508 uint32_t mpf_sense_addr_hi; 509 uint8_t mpf_cdb[16]; 510 union mfi_sgl mpf_sgl; 511 } __packed; 512 513 #define MFI_DCMD_FRAME_SIZE 40 514 struct mfi_dcmd_frame { 515 struct mfi_frame_header mdf_header; 516 uint32_t mdf_opcode; 517 union mfi_mbox mdf_mbox; 518 union mfi_sgl mdf_sgl; 519 } __packed; 520 #define MFI_DCMD_MBOX_PEND_FLAG 0x1 521 522 struct mfi_abort_frame { 523 struct mfi_frame_header maf_header; 524 uint32_t maf_abort_context; 525 uint32_t maf_pad; 526 uint32_t maf_abort_mfi_addr_lo; 527 uint32_t maf_abort_mfi_addr_hi; 528 uint32_t maf_reserved[6]; 529 } __packed; 530 531 struct mfi_smp_frame { 532 struct mfi_frame_header msf_header; 533 uint64_t msf_sas_addr; 534 union { 535 struct mfi_sg32 sg32[2]; 536 struct mfi_sg64 sg64[2]; 537 } msf_sgl; 538 } __packed; 539 540 struct mfi_stp_frame { 541 struct mfi_frame_header msf_header; 542 uint16_t msf_fis[10]; 543 uint32_t msf_stp_flags; 544 union { 545 struct mfi_sg32 sg32[2]; 546 struct mfi_sg64 sg64[2]; 547 } msf_sgl; 548 } __packed; 549 550 union mfi_frame { 551 struct mfi_frame_header mfr_header; 552 struct mfi_init_frame mfr_init; 553 struct mfi_io_frame mfr_io; 554 struct mfi_pass_frame mfr_pass; 555 struct mfi_dcmd_frame mfr_dcmd; 556 struct mfi_abort_frame mfr_abort; 557 struct mfi_smp_frame mfr_smp; 558 struct mfi_stp_frame mfr_stp; 559 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 560 }; 561 562 union mfi_evt_class_locale { 563 struct { 564 uint16_t locale; 565 uint8_t reserved; 566 int8_t class; 567 } __packed mec_members; 568 569 uint32_t mec_word; 570 } __packed; 571 572 struct mfi_evt_log_info { 573 uint32_t mel_newest_seq_num; 574 uint32_t mel_oldest_seq_num; 575 uint32_t mel_clear_seq_num; 576 uint32_t mel_shutdown_seq_num; 577 uint32_t mel_boot_seq_num; 578 } __packed; 579 580 struct mfi_progress { 581 uint16_t mp_progress; 582 uint16_t mp_elapsed_seconds; 583 } __packed; 584 585 struct mfi_evtarg_ld { 586 uint16_t mel_target_id; 587 uint8_t mel_ld_index; 588 uint8_t mel_reserved; 589 } __packed; 590 591 struct mfi_evtarg_pd { 592 uint16_t mep_device_id; 593 uint8_t mep_encl_index; 594 uint8_t mep_slot_number; 595 } __packed; 596 597 struct mfi_evtarg_pd_state { 598 struct mfi_evtarg_pd pd; 599 uint32_t prev_state; 600 uint32_t new_state; 601 } __packed; 602 603 struct mfi_evtarg_pd_address { 604 uint16_t device_id; 605 uint16_t encl_id; 606 607 union { 608 struct { 609 uint8_t encl_index; 610 uint8_t slot_number; 611 } __packed pd_address; 612 struct { 613 uint8_t encl_position; 614 uint8_t encl_connector_index; 615 } __packed encl_address; 616 } __packed address; 617 618 uint8_t scsi_dev_type; 619 620 union { 621 uint8_t port_bitmap; 622 uint8_t port_numbers; 623 } __packed connected; 624 625 uint64_t sas_addr[2]; 626 } __packed __aligned(8); 627 628 struct mfi_evt_detail { 629 uint32_t med_seq_num; 630 uint32_t med_time_stamp; 631 uint32_t med_code; 632 union mfi_evt_class_locale med_cl; 633 uint8_t med_arg_type; 634 uint8_t med_reserved1[15]; 635 636 union { 637 struct { 638 struct mfi_evtarg_pd pd; 639 uint8_t cdb_length; 640 uint8_t sense_length; 641 uint8_t reserved[2]; 642 uint8_t cdb[16]; 643 uint8_t sense[64]; 644 } __packed cdb_sense; 645 646 struct mfi_evtarg_ld ld; 647 648 struct { 649 struct mfi_evtarg_ld ld; 650 uint64_t count; 651 } __packed ld_count; 652 653 struct { 654 uint64_t lba; 655 struct mfi_evtarg_ld ld; 656 } __packed ld_lba; 657 658 struct { 659 struct mfi_evtarg_ld ld; 660 uint32_t prev_owner; 661 uint32_t new_owner; 662 } __packed ld_owner; 663 664 struct { 665 uint64_t ld_lba; 666 uint64_t pd_lba; 667 struct mfi_evtarg_ld ld; 668 struct mfi_evtarg_pd pd; 669 } __packed ld_lba_pd_lba; 670 671 struct { 672 struct mfi_evtarg_ld ld; 673 struct mfi_progress prog; 674 } __packed ld_prog; 675 676 struct { 677 struct mfi_evtarg_ld ld; 678 uint32_t prev_state; 679 uint32_t new_state; 680 } __packed ld_state; 681 682 struct { 683 uint64_t strip; 684 struct mfi_evtarg_ld ld; 685 } __packed ld_strip; 686 687 struct mfi_evtarg_pd pd; 688 689 struct { 690 struct mfi_evtarg_pd pd; 691 uint32_t err; 692 } __packed pd_err; 693 694 struct { 695 uint64_t lba; 696 struct mfi_evtarg_pd pd; 697 } __packed pd_lba; 698 699 struct { 700 uint64_t lba; 701 struct mfi_evtarg_pd pd; 702 struct mfi_evtarg_ld ld; 703 } __packed pd_lba_ld; 704 705 struct { 706 struct mfi_evtarg_pd pd; 707 struct mfi_progress prog; 708 } __packed pd_prog; 709 710 struct mfi_evtarg_pd_state pd_state; 711 712 struct { 713 uint16_t vendor_id; 714 uint16_t device_id; 715 uint16_t subvendor_id; 716 uint16_t subdevice_id; 717 } __packed pci; 718 719 uint32_t rate; 720 char str[96]; 721 722 struct { 723 uint32_t rtc; 724 uint32_t elapsed_seconds; 725 } __packed time; 726 727 struct { 728 uint32_t ecar; 729 uint32_t elog; 730 char str[64]; 731 } __packed ecc; 732 733 struct mfi_evtarg_pd_address pd_address; 734 735 uint8_t b[96]; 736 uint16_t s[48]; 737 uint32_t w[24]; 738 uint64_t d[12]; 739 } args; 740 741 char med_description[128]; 742 } __packed; 743 744 /* controller properties from mfi_ctrl_info */ 745 struct mfi_ctrl_props { 746 uint16_t mcp_seq_num; 747 uint16_t mcp_pred_fail_poll_interval; 748 uint16_t mcp_intr_throttle_cnt; 749 uint16_t mcp_intr_throttle_timeout; 750 uint8_t mcp_rebuild_rate; 751 uint8_t mcp_patrol_read_rate; 752 uint8_t mcp_bgi_rate; 753 uint8_t mcp_cc_rate; 754 uint8_t mcp_recon_rate; 755 uint8_t mcp_cache_flush_interval; 756 uint8_t mcp_spinup_drv_cnt; 757 uint8_t mcp_spinup_delay; 758 uint8_t mcp_cluster_enable; 759 uint8_t mcp_coercion_mode; 760 uint8_t mcp_alarm_enable; 761 uint8_t mcp_disable_auto_rebuild; 762 uint8_t mcp_disable_battery_warn; 763 uint8_t mcp_ecc_bucket_size; 764 uint16_t mcp_ecc_bucket_leak_rate; 765 uint8_t mcp_restore_hotspare_on_insertion; 766 uint8_t mcp_expose_encl_devices; 767 uint8_t maintainPdFailHistory; 768 uint8_t disallowHostRequestReordering; 769 /* set TRUE to abort CC on detecting an inconsistency */ 770 uint8_t abortCCOnError; 771 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 772 uint8_t loadBalanceMode; 773 /* 774 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 775 * h/w mechanism like GPIO pins 776 * 1 - disable auto detect SGPIO, 777 * 2 - disable i2c SEP auto detect 778 * 3 - disable both auto detect 779 */ 780 uint8_t disableAutoDetectBackplane; 781 /* 782 * % of source LD to be reserved for a VDs snapshot in snapshot 783 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 784 */ 785 uint8_t snapVDSpace; 786 787 /* 788 * Add properties that can be controlled by a bit in the following 789 * structure. 790 */ 791 struct { 792 /* set TRUE to disable copyBack (0=copback enabled) */ 793 uint32_t copyBackDisabled :1; 794 uint32_t SMARTerEnabled :1; 795 uint32_t prCorrectUnconfiguredAreas :1; 796 uint32_t useFdeOnly :1; 797 uint32_t disableNCQ :1; 798 uint32_t SSDSMARTerEnabled :1; 799 uint32_t SSDPatrolReadEnabled :1; 800 uint32_t enableSpinDownUnconfigured :1; 801 uint32_t autoEnhancedImport :1; 802 uint32_t enableSecretKeyControl :1; 803 uint32_t disableOnlineCtrlReset :1; 804 uint32_t allowBootWithPinnedCache :1; 805 uint32_t disableSpinDownHS :1; 806 uint32_t enableJBOD :1; 807 uint32_t reserved :18; 808 } OnOffProperties; 809 /* 810 * % of source LD to be reserved for auto snapshot in snapshot 811 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so 812 * on. 813 */ 814 uint8_t autoSnapVDSpace; 815 /* 816 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 817 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 818 */ 819 uint8_t viewSpace; 820 /* # of idle minutes before device is spun down (0=use FW defaults) */ 821 uint16_t spinDownTime; 822 uint8_t reserved[24]; 823 } __packed; 824 825 /* pci info */ 826 struct mfi_info_pci { 827 uint16_t mip_vendor; 828 uint16_t mip_device; 829 uint16_t mip_subvendor; 830 uint16_t mip_subdevice; 831 uint8_t mip_reserved[24]; 832 } __packed; 833 834 /* host interface info */ 835 struct mfi_info_host { 836 uint8_t mih_type; 837 #define MFI_INFO_HOST_PCIX 0x01 838 #define MFI_INFO_HOST_PCIE 0x02 839 #define MFI_INFO_HOST_ISCSI 0x04 840 #define MFI_INFO_HOST_SAS3G 0x08 841 uint8_t mih_reserved[6]; 842 uint8_t mih_port_count; 843 uint64_t mih_port_addr[8]; 844 } __packed; 845 846 /* device interface info */ 847 struct mfi_info_device { 848 uint8_t mid_type; 849 #define MFI_INFO_DEV_SPI 0x01 850 #define MFI_INFO_DEV_SAS3G 0x02 851 #define MFI_INFO_DEV_SATA1 0x04 852 #define MFI_INFO_DEV_SATA3G 0x08 853 uint8_t mid_reserved[6]; 854 uint8_t mid_port_count; 855 uint64_t mid_port_addr[8]; 856 } __packed; 857 858 /* firmware component info */ 859 struct mfi_info_component { 860 char mic_name[8]; 861 char mic_version[32]; 862 char mic_build_date[16]; 863 char mic_build_time[16]; 864 } __packed; 865 866 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 867 struct mfi_ctrl_info { 868 struct mfi_info_pci mci_pci; 869 struct mfi_info_host mci_host; 870 struct mfi_info_device mci_device; 871 872 /* Firmware components that are present and active. */ 873 uint32_t mci_image_check_word; 874 uint32_t mci_image_component_count; 875 struct mfi_info_component mci_image_component[8]; 876 877 /* Firmware components that have been flashed but are inactive */ 878 uint32_t mci_pending_image_component_count; 879 struct mfi_info_component mci_pending_image_component[8]; 880 881 uint8_t mci_max_arms; 882 uint8_t mci_max_spans; 883 uint8_t mci_max_arrays; 884 uint8_t mci_max_lds; 885 char mci_product_name[80]; 886 char mci_serial_number[32]; 887 uint32_t mci_hw_present; 888 #define MFI_INFO_HW_BBU 0x01 889 #define MFI_INFO_HW_ALARM 0x02 890 #define MFI_INFO_HW_NVRAM 0x04 891 #define MFI_INFO_HW_UART 0x08 892 uint32_t mci_current_fw_time; 893 uint16_t mci_max_cmds; 894 uint16_t mci_max_sg_elements; 895 uint32_t mci_max_request_size; 896 uint16_t mci_lds_present; 897 uint16_t mci_lds_degraded; 898 uint16_t mci_lds_offline; 899 uint16_t mci_pd_present; 900 uint16_t mci_pd_disks_present; 901 uint16_t mci_pd_disks_pred_failure; 902 uint16_t mci_pd_disks_failed; 903 uint16_t mci_nvram_size; 904 uint16_t mci_memory_size; 905 uint16_t mci_flash_size; 906 uint16_t mci_ram_correctable_errors; 907 uint16_t mci_ram_uncorrectable_errors; 908 uint8_t mci_cluster_allowed; 909 uint8_t mci_cluster_active; 910 uint16_t mci_max_strips_per_io; 911 912 uint32_t mci_raid_levels; 913 #define MFI_INFO_RAID_0 0x01 914 #define MFI_INFO_RAID_1 0x02 915 #define MFI_INFO_RAID_5 0x04 916 #define MFI_INFO_RAID_1E 0x08 917 #define MFI_INFO_RAID_6 0x10 918 919 uint32_t mci_adapter_ops; 920 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 921 #define MFI_INFO_AOPS_CC_RATE 0x0002 922 #define MFI_INFO_AOPS_BGI_RATE 0x0004 923 #define MFI_INFO_AOPS_RECON_RATE 0x0008 924 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 925 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 926 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 927 #define MFI_INFO_AOPS_BBU 0x0080 928 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 929 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 930 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 931 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 932 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 933 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 934 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 935 936 uint32_t mci_ld_ops; 937 #define MFI_INFO_LDOPS_READ_POLICY 0x01 938 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 939 #define MFI_INFO_LDOPS_IO_POLICY 0x04 940 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 941 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 942 943 struct { 944 uint8_t min; 945 uint8_t max; 946 uint8_t reserved[2]; 947 } __packed mci_stripe_sz_ops; 948 949 uint32_t mci_pd_ops; 950 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 951 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 952 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 953 954 uint32_t mci_pd_mix_support; 955 #define MFI_INFO_PDMIX_SAS 0x01 956 #define MFI_INFO_PDMIX_SATA 0x02 957 #define MFI_INFO_PDMIX_ENCL 0x04 958 #define MFI_INFO_PDMIX_LD 0x08 959 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 960 961 uint8_t mci_ecc_bucket_count; 962 uint8_t mci_reserved2[11]; 963 struct mfi_ctrl_props mci_properties; 964 char mci_package_version[0x60]; 965 uint8_t mci_pad[0x800 - 0x6a0]; 966 } __packed; 967 968 /* logical disk info from MR_DCMD_LD_GET_LIST */ 969 struct mfi_ld { 970 uint8_t mld_target; 971 uint8_t mld_res; 972 uint16_t mld_seq; 973 } __packed; 974 975 struct mfi_ld_list { 976 uint32_t mll_no_ld; 977 uint32_t mll_res; 978 struct { 979 struct mfi_ld mll_ld; 980 uint8_t mll_state; 981 #define MFI_LD_OFFLINE 0x00 982 #define MFI_LD_PART_DEGRADED 0x01 983 #define MFI_LD_DEGRADED 0x02 984 #define MFI_LD_ONLINE 0x03 985 uint8_t mll_res2; 986 uint8_t mll_res3; 987 uint8_t mll_res4; 988 uint64_t mll_size; 989 } mll_list[MFI_MAX_LD]; 990 } __packed; 991 992 /* logical disk details from MR_DCMD_LD_GET_INFO */ 993 struct mfi_ld_prop { 994 struct mfi_ld mlp_ld; 995 char mlp_name[16]; 996 uint8_t mlp_cache_policy; 997 uint8_t mlp_acces_policy; 998 uint8_t mlp_diskcache_policy; 999 uint8_t mlp_cur_cache_policy; 1000 uint8_t mlp_disable_bgi; 1001 uint8_t mlp_res[7]; 1002 } __packed; 1003 1004 struct mfi_ld_parm { 1005 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 1006 #define MFI_DDF_PRL_RAID0 0x00 1007 #define MFI_DDF_PRL_RAID1 0x01 1008 #define MFI_DDF_PRL_RAID3 0x03 1009 #define MFI_DDF_PRL_RAID4 0x04 1010 #define MFI_DDF_PRL_RAID5 0x05 1011 #define MFI_DDF_PRL_RAID1E 0x11 1012 #define MFI_DDF_PRL_JBOD 0x0f 1013 #define MFI_DDF_PRL_CONCAT 0x1f 1014 #define MFI_DDF_PRL_RAID5E 0x15 1015 #define MFI_DDF_PRL_RAID5EE 0x25 1016 #define MFI_DDF_PRL_RAID6 0x16 1017 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 1018 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 1019 #define MFI_DDF_SRL_STRIPED 0x00 1020 #define MFI_DDF_SRL_MIRRORED 0x01 1021 #define MFI_DDF_SRL_CONCAT 0x02 1022 #define MFI_DDF_SRL_SPANNED 0x03 1023 uint8_t mpa_stripe_size; 1024 uint8_t mpa_no_drv_per_span; 1025 uint8_t mpa_span_depth; 1026 uint8_t mpa_state; 1027 uint8_t mpa_init_state; 1028 uint8_t mpa_is_consistent; 1029 uint8_t mpa_res1[6]; 1030 uint8_t mpa_isSSCD; 1031 uint8_t mpa_res[16]; 1032 } __packed; 1033 1034 struct mfi_ld_span { 1035 uint64_t mls_start_block; 1036 uint64_t mls_no_blocks; 1037 uint16_t mls_index; 1038 uint8_t mls_res[6]; 1039 } __packed; 1040 1041 struct mfi_ld_cfg { 1042 struct mfi_ld_prop mlc_prop; 1043 struct mfi_ld_parm mlc_parm; 1044 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 1045 } __packed; 1046 1047 struct mfi_ld_progress { 1048 uint32_t mlp_in_prog; 1049 #define MFI_LD_PROG_CC 0x01 1050 #define MFI_LD_PROG_BGI 0x02 1051 #define MFI_LD_PROG_FGI 0x04 1052 #define MFI_LD_PROG_RECONSTRUCT 0x08 1053 struct mfi_progress mlp_cc; 1054 struct mfi_progress mlp_bgi; 1055 struct mfi_progress mlp_fgi; 1056 struct mfi_progress mlp_reconstruct; 1057 struct mfi_progress mlp_res[4]; 1058 } __packed; 1059 1060 struct mfi_ld_details { 1061 struct mfi_ld_cfg mld_cfg; 1062 uint64_t mld_size; 1063 struct mfi_ld_progress mld_progress; 1064 uint16_t mld_clust_own_id; 1065 uint8_t mld_res1; 1066 uint8_t mld_res2; 1067 uint8_t mld_inq_page83[64]; 1068 uint8_t mld_res[16]; 1069 } __packed; 1070 1071 /* physical disk info from MR_DCMD_PD_GET_LIST */ 1072 struct mfi_pd_address { 1073 uint16_t mpa_pd_id; 1074 uint16_t mpa_enc_id; 1075 uint8_t mpa_enc_index; 1076 uint8_t mpa_enc_slot; 1077 uint8_t mpa_scsi_type; 1078 uint8_t mpa_port; 1079 uint64_t mpa_sas_address[2]; 1080 } __packed; 1081 1082 struct mfi_pd_list { 1083 uint32_t mpl_size; 1084 uint32_t mpl_no_pd; 1085 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 1086 } __packed; 1087 1088 struct mfi_pd { 1089 uint16_t mfp_id; 1090 uint16_t mfp_seq; 1091 } __packed; 1092 1093 struct mfi_pd_progress { 1094 uint32_t mfp_in_prog; 1095 #define MFI_PD_PROG_RBLD 0x01 1096 #define MFI_PD_PROG_PR 0x02 1097 #define MFI_PD_PROG_CLEAR 0x04 1098 struct mfi_progress mfp_rebuild; 1099 struct mfi_progress mfp_patrol_read; 1100 struct mfi_progress mfp_clear; 1101 struct mfi_progress mfp_res[4]; 1102 } __packed; 1103 1104 struct mfi_pd_details { 1105 struct mfi_pd mpd_pd; 1106 uint8_t mpd_inq_data[96]; 1107 uint8_t mpd_inq_page83[64]; 1108 uint8_t mpd_no_support; 1109 uint8_t mpd_scsi_type; 1110 uint8_t mpd_port; 1111 uint8_t mpd_speed; 1112 uint32_t mpd_mediaerr_cnt; 1113 uint32_t mpd_othererr_cnt; 1114 uint32_t mpd_predfail_cnt; 1115 uint32_t mpd_last_pred_event; 1116 uint16_t mpd_fw_state; 1117 uint8_t mpd_rdy_for_remove; 1118 uint8_t mpd_link_speed; 1119 uint32_t mpd_ddf_state; 1120 #define MFI_DDF_GUID_FORCED 0x01 1121 #define MFI_DDF_PART_OF_VD 0x02 1122 #define MFI_DDF_GLOB_HOTSPARE 0x04 1123 #define MFI_DDF_HOTSPARE 0x08 1124 #define MFI_DDF_FOREIGN 0x10 1125 #define MFI_DDF_TYPE_MASK 0xf000 1126 #define MFI_DDF_TYPE_UNKNOWN 0x0000 1127 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 1128 #define MFI_DDF_TYPE_SAS 0x2000 1129 #define MFI_DDF_TYPE_SATA 0x3000 1130 #define MFI_DDF_TYPE_FC 0x4000 1131 struct { 1132 uint8_t mpp_cnt; 1133 uint8_t mpp_severed; 1134 uint8_t mpp_res[6]; 1135 uint64_t mpp_sas_addr[4]; 1136 } __packed mpd_path; 1137 uint64_t mpd_size; 1138 uint64_t mpd_no_coerce_size; 1139 uint64_t mpd_coerce_size; 1140 uint16_t mpd_enc_id; 1141 uint8_t mpd_enc_idx; 1142 uint8_t mpd_enc_slot; 1143 struct mfi_pd_progress mpd_progress; 1144 uint8_t mpd_bblock_full; 1145 uint8_t mpd_unusable; 1146 uint8_t mpd_res[218]; /* size is 512 */ 1147 } __packed; 1148 1149 /* array configuration from MR_DCMD_CONF_GET */ 1150 struct mfi_array { 1151 uint64_t mar_smallest_pd; 1152 uint8_t mar_no_disk; 1153 uint8_t mar_res1; 1154 uint16_t mar_array_ref; 1155 uint8_t mar_res2[20]; 1156 struct { 1157 struct mfi_pd mar_pd; 1158 uint16_t mar_pd_state; 1159 #define MFI_PD_UNCONFIG_GOOD 0x00 1160 #define MFI_PD_UNCONFIG_BAD 0x01 1161 #define MFI_PD_HOTSPARE 0x02 1162 #define MFI_PD_OFFLINE 0x10 1163 #define MFI_PD_FAILED 0x11 1164 #define MFI_PD_REBUILD 0x14 1165 #define MFI_PD_ONLINE 0x18 1166 #define MFI_PD_COPYBACK 0x20 1167 #define MFI_PD_SYSTEM 0x40 1168 #define MFI_PD_JBOD MFI_PD_SYSTEM 1169 uint8_t mar_enc_pd; 1170 uint8_t mar_enc_slot; 1171 } pd[MFI_MAX_PD_ARRAY]; 1172 } __packed; 1173 1174 struct mfi_hotspare { 1175 struct mfi_pd mhs_pd; 1176 uint8_t mhs_type; 1177 #define MFI_PD_HS_DEDICATED 0x01 1178 #define MFI_PD_HS_REVERTIBLE 0x02 1179 #define MFI_PD_HS_ENC_AFFINITY 0x04 1180 uint8_t mhs_res[2]; 1181 uint8_t mhs_array_max; 1182 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1183 } __packed; 1184 1185 struct mfi_conf { 1186 uint32_t mfc_size; 1187 uint16_t mfc_no_array; 1188 uint16_t mfc_array_size; 1189 uint16_t mfc_no_ld; 1190 uint16_t mfc_ld_size; 1191 uint16_t mfc_no_hs; 1192 uint16_t mfc_hs_size; 1193 uint8_t mfc_res[16]; 1194 /* 1195 * XXX this is a ridiculous hack and does not reflect reality 1196 * Structures are actually indexed and therefore need pointer 1197 * math to reach. We need the size of this structure first so 1198 * call it with the size of this structure and then use the returned 1199 * values to allocate memory and do the transfer of the whole structure 1200 * then calculate pointers to each of these structures. 1201 */ 1202 struct mfi_array mfc_array[1]; 1203 struct mfi_ld_cfg mfc_ld[1]; 1204 struct mfi_hotspare mfc_hs[1]; 1205 } __packed; 1206 1207 /* informations from MR_DCMD_BBU_GET_CAPACITY_INFO */ 1208 struct mfi_bbu_capacity_info { 1209 uint16_t relative_charge; 1210 uint16_t absolute_charge; 1211 uint16_t remaining_capacity; 1212 uint16_t full_charge_capacity; 1213 uint16_t run_time_to_empty; 1214 uint16_t average_time_to_empty; 1215 uint16_t average_time_to_full; 1216 uint16_t cycle_count; 1217 uint16_t max_error; 1218 uint16_t remaining_capacity_alarm; 1219 uint16_t remaining_time_alarm; 1220 uint8_t reserved[26]; 1221 } __packed; 1222 1223 /* informations from MR_DCMD_BBU_GET_DESIGN_INFO */ 1224 struct mfi_bbu_design_info { 1225 uint32_t mfg_date; 1226 uint16_t design_capacity; 1227 uint16_t design_voltage; 1228 uint16_t spec_info; 1229 uint16_t serial_number; 1230 uint16_t pack_stat_config; 1231 uint8_t mfg_name[12]; 1232 uint8_t device_name[8]; 1233 uint8_t device_chemistry[8]; 1234 uint8_t mfg_data[8]; 1235 uint8_t reserved[17]; 1236 } __packed; 1237 1238 struct mfi_ibbu_state { 1239 uint16_t gas_guage_status; 1240 uint16_t relative_charge; 1241 uint16_t charger_system_state; 1242 uint16_t charger_system_ctrl; 1243 uint16_t charging_current; 1244 uint16_t absolute_charge; 1245 uint16_t max_error; 1246 uint8_t reserved[18]; 1247 } __packed; 1248 1249 struct mfi_bbu_state { 1250 uint16_t gas_guage_status; 1251 uint16_t relative_charge; 1252 uint16_t charger_status; 1253 uint16_t remaining_capacity; 1254 uint16_t full_charge_capacity; 1255 uint8_t is_SOH_good; 1256 uint8_t reserved[21]; 1257 } __packed; 1258 1259 union mfi_bbu_status_detail { 1260 struct mfi_ibbu_state ibbu; 1261 struct mfi_bbu_state bbu; 1262 }; 1263 1264 /* informations from MR_DCMD_BBU_GET_STATUS */ 1265 struct mfi_bbu_status { 1266 uint8_t battery_type; 1267 #define MFI_BBU_TYPE_NONE 0 1268 #define MFI_BBU_TYPE_IBBU 1 1269 #define MFI_BBU_TYPE_BBU 2 1270 #define MFI_BBU_TYPE_IBBU09 5 1271 #define MFI_BBU_TYPE_CVPM02 6 1272 uint8_t reserved; 1273 uint16_t voltage; /* mV */ 1274 int16_t current; /* mA */ 1275 uint16_t temperature; /* degC */ 1276 uint32_t fw_status; 1277 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1278 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1279 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1280 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1281 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1282 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1283 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1284 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1285 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1286 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1287 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1288 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1289 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1290 #define MFI_BBU_STATE_BAD_IBBU ( \ 1291 MFI_BBU_STATE_PACK_MISSING | \ 1292 MFI_BBU_STATE_VOLTAGE_LOW | \ 1293 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1294 MFI_BBU_STATE_LEARN_CYC_REQ | \ 1295 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1296 MFI_BBU_STATE_REPLACE_PACK | \ 1297 MFI_BBU_STATE_CAPACITY_LOW) 1298 #define MFI_BBU_STATE_BAD_BBU ( \ 1299 MFI_BBU_STATE_PACK_MISSING | \ 1300 MFI_BBU_STATE_REPLACE_PACK | \ 1301 MFI_BBU_STATE_CAPACITY_LOW) 1302 uint8_t pad[20]; 1303 union mfi_bbu_status_detail detail; 1304 } __packed; 1305 1306 /* ThunderBolt support */ 1307 1308 /* 1309 * Raid Context structure which describes MegaRAID specific IO Parameters 1310 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1311 */ 1312 typedef struct _mpi2_scsi_io_vendor_unique { 1313 uint16_t resvd0; /* 0x00 - 0x01 */ 1314 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1315 uint8_t regLockFlags; 1316 uint8_t armId; 1317 uint16_t TargetID; /* 0x06 - 0x07 */ 1318 1319 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1320 1321 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1322 1323 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1324 uint8_t exStatus; /* 0x16 */ 1325 uint8_t Status; /* 0x17 status */ 1326 1327 uint8_t RAIDFlags; /* 0x18 */ 1328 uint8_t numSGE; /* 0x19 numSge */ 1329 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1330 uint8_t spanArm; /* 0x1C */ 1331 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1332 } mpi2_scsi_io_vendor_unique, mpi25_scsi_io_vendor_unique; 1333 1334 /***************************************************************************** 1335 * 1336 * Message Functions 1337 * 1338 *****************************************************************************/ 1339 1340 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1341 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1342 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1343 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1344 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1345 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1346 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1347 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1348 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1349 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1350 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1351 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1352 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1353 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1354 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1355 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1356 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1357 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1358 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1359 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1360 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1361 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1362 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1363 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1364 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1365 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1366 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1367 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1368 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1369 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1370 1371 /* Doorbell functions */ 1372 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1373 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1374 1375 /***************************************************************************** 1376 * 1377 * MPI Version Definitions 1378 * 1379 *****************************************************************************/ 1380 1381 #define MPI2_VERSION_MAJOR (0x02) 1382 #define MPI2_VERSION_MINOR (0x00) 1383 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1384 #define MPI2_VERSION_MAJOR_SHIFT (8) 1385 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1386 #define MPI2_VERSION_MINOR_SHIFT (0) 1387 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1388 MPI2_VERSION_MINOR) 1389 1390 #define MPI2_VERSION_02_00 (0x0200) 1391 1392 /* versioning for this MPI header set */ 1393 #define MPI2_HEADER_VERSION_UNIT (0x10) 1394 #define MPI2_HEADER_VERSION_DEV (0x00) 1395 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1396 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1397 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1398 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1399 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1400 MPI2_HEADER_VERSION_DEV) 1401 1402 1403 /* IOCInit Request message */ 1404 struct mpi2_ioc_init_request { 1405 uint8_t WhoInit; /* 0x00 */ 1406 uint8_t Reserved1; /* 0x01 */ 1407 uint8_t ChainOffset; /* 0x02 */ 1408 uint8_t Function; /* 0x03 */ 1409 uint16_t Reserved2; /* 0x04 */ 1410 uint8_t Reserved3; /* 0x06 */ 1411 uint8_t MsgFlags; /* 0x07 */ 1412 uint8_t VP_ID; /* 0x08 */ 1413 uint8_t VF_ID; /* 0x09 */ 1414 uint16_t Reserved4; /* 0x0A */ 1415 uint16_t MsgVersion; /* 0x0C */ 1416 uint16_t HeaderVersion; /* 0x0E */ 1417 uint32_t Reserved5; /* 0x10 */ 1418 uint16_t Reserved6; /* 0x14 */ 1419 uint8_t Reserved7; /* 0x16 */ 1420 uint8_t HostMSIxVectors; /* 0x17 */ 1421 uint16_t Reserved8; /* 0x18 */ 1422 uint16_t SystemRequestFrameSize; /* 0x1A */ 1423 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1424 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1425 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1426 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1427 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1428 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1429 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1430 uint64_t TimeStamp; /* 0x40 */ 1431 }; 1432 1433 /* WhoInit values */ 1434 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1435 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1436 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1437 #define MPI2_WHOINIT_PCI_PEER (0x03) 1438 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1439 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1440 1441 struct mpi2_sge_chain_union { 1442 uint16_t Length; 1443 uint8_t NextChainOffset; 1444 uint8_t Flags; 1445 union { 1446 uint32_t Address32; 1447 uint64_t Address64; 1448 } u; 1449 }; 1450 1451 struct mpi2_ieee_sge_simple32 { 1452 uint32_t Address; 1453 uint32_t FlagsLength; 1454 }; 1455 1456 struct mpi2_ieee_sge_simple64 { 1457 uint64_t Address; 1458 uint32_t Length; 1459 uint16_t Reserved1; 1460 uint8_t Reserved2; 1461 uint8_t Flags; 1462 }; 1463 1464 typedef union _mpi2_ieee_simple_union { 1465 struct mpi2_ieee_sge_simple32 Simple32; 1466 struct mpi2_ieee_sge_simple64 Simple64; 1467 } mpi2_ieee_simple_union; 1468 1469 typedef struct _mpi2_sge_simple_union { 1470 uint32_t FlagsLength; 1471 union { 1472 uint32_t Address32; 1473 uint64_t Address64; 1474 } u; 1475 } mpi2_sge_simple_union; 1476 1477 /* MPI 2.5 SGLs */ 1478 1479 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1480 1481 struct mpi25_ieee_sge_chain64 { 1482 uint64_t Address; 1483 uint32_t Length; 1484 uint16_t Reserved1; 1485 uint8_t NextChainOffset; 1486 uint8_t Flags; 1487 }; 1488 1489 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1490 1491 /**************************************************************************** 1492 * IEEE SGE field definitions and masks 1493 ****************************************************************************/ 1494 1495 /* Flags field bit definitions */ 1496 1497 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1498 1499 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1500 1501 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1502 1503 /* Element Type */ 1504 1505 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1506 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1507 1508 /* Data Location Address Space */ 1509 1510 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1511 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1512 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1513 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1514 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1515 1516 /* Address Size */ 1517 1518 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1519 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1520 1521 /*******************/ 1522 /* SCSI IO Control bits */ 1523 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1524 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1525 1526 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1527 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1528 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1529 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1530 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1531 1532 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1533 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1534 1535 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1536 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1537 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1538 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1539 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1540 1541 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1542 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1543 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1544 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1545 1546 /*******************/ 1547 1548 typedef struct { 1549 uint8_t CDB[20]; /* 0x00 */ 1550 uint32_t PrimaryReferenceTag; /* 0x14 */ 1551 uint16_t PrimaryApplicationTag; /* 0x18 */ 1552 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1553 uint32_t TransferLength; /* 0x1C */ 1554 } mpi2_scsi_io_cdb_eedp32; 1555 1556 1557 typedef union _mpi2_ieee_sge_chain_union { 1558 struct mpi2_ieee_sge_simple32 Chain32; 1559 struct mpi25_ieee_sge_chain64 Chain64; 1560 } mpi2_ieee_sge_chain_union; 1561 1562 typedef union _mpi2_simple_sge_union { 1563 mpi2_sge_simple_union MpiSimple; 1564 mpi2_ieee_simple_union IeeeSimple; 1565 } mpi2_simple_sge_union; 1566 1567 typedef union _mpi2_sge_io_union { 1568 mpi2_sge_simple_union MpiSimple; 1569 struct mpi2_sge_chain_union MpiChain; 1570 mpi2_ieee_simple_union IeeeSimple; 1571 mpi2_ieee_sge_chain_union IeeeChain; 1572 } mpi2_sge_io_union; 1573 1574 typedef union { 1575 uint8_t CDB32[32]; 1576 mpi2_scsi_io_cdb_eedp32 EEDP32; 1577 mpi2_sge_simple_union SGE; 1578 } mpi2_scsi_io_cdb_union; 1579 1580 1581 1582 /********/ 1583 1584 /* 1585 * RAID SCSI IO Request Message 1586 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1587 */ 1588 struct mfi_mpi2_request_raid_scsi_io { 1589 uint16_t DevHandle; /* 0x00 */ 1590 uint8_t ChainOffset; /* 0x02 */ 1591 uint8_t Function; /* 0x03 */ 1592 uint16_t Reserved1; /* 0x04 */ 1593 uint8_t Reserved2; /* 0x06 */ 1594 uint8_t MsgFlags; /* 0x07 */ 1595 uint8_t VP_ID; /* 0x08 */ 1596 uint8_t VF_ID; /* 0x09 */ 1597 uint16_t Reserved3; /* 0x0A */ 1598 uint32_t SenseBufferLowAddress; /* 0x0C */ 1599 uint16_t SGLFlags; /* 0x10 */ 1600 uint8_t SenseBufferLength; /* 0x12 */ 1601 uint8_t Reserved4; /* 0x13 */ 1602 uint8_t SGLOffset0; /* 0x14 */ 1603 uint8_t SGLOffset1; /* 0x15 */ 1604 uint8_t SGLOffset2; /* 0x16 */ 1605 uint8_t SGLOffset3; /* 0x17 */ 1606 uint32_t SkipCount; /* 0x18 */ 1607 uint32_t DataLength; /* 0x1C */ 1608 uint32_t BidirectionalDataLength; /* 0x20 */ 1609 uint16_t IoFlags; /* 0x24 */ 1610 uint16_t EEDPFlags; /* 0x26 */ 1611 uint32_t EEDPBlockSize; /* 0x28 */ 1612 uint32_t SecondaryReferenceTag; /* 0x2C */ 1613 uint16_t SecondaryApplicationTag; /* 0x30 */ 1614 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1615 uint8_t LUN[8]; /* 0x34 */ 1616 uint32_t Control; /* 0x3C */ 1617 mpi2_scsi_io_cdb_union CDB; /* 0x40 */ 1618 mpi2_scsi_io_vendor_unique RaidContext; /* 0x60 */ 1619 mpi2_sge_io_union SGL; /* 0x80 */ 1620 } __packed; 1621 1622 /* 1623 * MPT RAID MFA IO Descriptor. 1624 */ 1625 typedef struct _mfi_raid_mfa_io_descriptor { 1626 uint32_t RequestFlags : 8; 1627 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1628 uint32_t MessageAddress2; /* bits 61:32 */ 1629 } mfi_raid_mfa_io_request_descriptor; 1630 1631 struct mfi_mpi2_request_header { 1632 uint8_t RequestFlags; /* 0x00 */ 1633 uint8_t MSIxIndex; /* 0x01 */ 1634 uint16_t SMID; /* 0x02 */ 1635 uint16_t LMID; /* 0x04 */ 1636 }; 1637 1638 /* defines for the RequestFlags field */ 1639 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1640 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1641 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1642 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1643 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1644 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1645 1646 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1647 1648 struct mfi_mpi2_request_high_priority { 1649 struct mfi_mpi2_request_header header; 1650 uint16_t reserved; 1651 }; 1652 1653 struct mfi_mpi2_request_scsi_io { 1654 struct mfi_mpi2_request_header header; 1655 uint16_t scsi_io_dev_handle; 1656 }; 1657 1658 struct mfi_mpi2_request_scsi_target { 1659 struct mfi_mpi2_request_header header; 1660 uint16_t scsi_target_io_index; 1661 }; 1662 1663 /* Request Descriptors */ 1664 union mfi_mpi2_request_descriptor { 1665 struct mfi_mpi2_request_header header; 1666 struct mfi_mpi2_request_high_priority high_priority; 1667 struct mfi_mpi2_request_scsi_io scsi_io; 1668 struct mfi_mpi2_request_scsi_target scsi_target; 1669 uint64_t words; 1670 }; 1671 1672 /* 1673 * Request descriptor types 1674 */ 1675 #define MFI_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1676 #define MFI_REQ_DESCRIPT_FLAGS_MFA 0x1 1677 #define MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 0x1 1678 1679 #define MFI_FUSION_FP_DEFAULT_TIMEOUT 0x14 1680 1681 struct mfi_mpi2_reply_header { 1682 uint8_t ReplyFlags; /* 0x00 */ 1683 uint8_t MSIxIndex; /* 0x01 */ 1684 uint16_t SMID; /* 0x02 */ 1685 }; 1686 1687 /* defines for the ReplyFlags field */ 1688 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1689 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1690 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1691 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1692 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1693 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1694 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1695 1696 /* values for marking a reply descriptor as unused */ 1697 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1698 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1699 1700 struct mfi_mpi2_reply_default { 1701 struct mfi_mpi2_reply_header header; 1702 uint32_t DescriptorTypeDependent2; 1703 }; 1704 1705 struct mfi_mpi2_reply_address { 1706 struct mfi_mpi2_reply_header header; 1707 uint32_t ReplyFrameAddress; 1708 }; 1709 1710 struct mfi_mpi2_reply_scsi_io { 1711 struct mfi_mpi2_reply_header header; 1712 uint16_t TaskTag; /* 0x04 */ 1713 uint16_t Reserved1; /* 0x06 */ 1714 }; 1715 1716 struct mfi_mpi2_reply_target_assist { 1717 struct mfi_mpi2_reply_header header; 1718 uint8_t SequenceNumber; /* 0x04 */ 1719 uint8_t Reserved1; /* 0x04 */ 1720 uint16_t IoIndex; /* 0x06 */ 1721 }; 1722 1723 struct mfi_mpi2_reply_target_cmd_buffer { 1724 struct mfi_mpi2_reply_header header; 1725 uint8_t SequenceNumber; /* 0x04 */ 1726 uint8_t Flags; /* 0x04 */ 1727 uint16_t InitiatorDevHandle; /* 0x06 */ 1728 uint16_t IoIndex; /* 0x06 */ 1729 }; 1730 1731 struct mfi_mpi2_reply_raid_accel { 1732 struct mfi_mpi2_reply_header header; 1733 uint8_t SequenceNumber; /* 0x04 */ 1734 uint32_t Reserved; /* 0x04 */ 1735 }; 1736 1737 /* union of Reply Descriptors */ 1738 union mfi_mpi2_reply_descriptor { 1739 struct mfi_mpi2_reply_header header; 1740 struct mfi_mpi2_reply_scsi_io scsi_io; 1741 struct mfi_mpi2_reply_target_assist target_assist; 1742 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1743 struct mfi_mpi2_reply_raid_accel raid_accel; 1744 struct mfi_mpi2_reply_default reply_default; 1745 uint64_t words; 1746 }; 1747 1748 struct io_request_info { 1749 uint64_t ldStartBlock; 1750 uint32_t numBlocks; 1751 uint16_t ldTgtId; 1752 uint8_t isRead; 1753 uint16_t devHandle; 1754 uint64_t pdBlock; 1755 uint8_t fpOkForIo; 1756 }; 1757 1758 /* 1759 * Define MFI Address Context union. 1760 */ 1761 #ifdef MFI_ADDRESS_IS_uint64_t 1762 typedef uint64_t mfi_address; 1763 #else 1764 typedef union _mfi_address { 1765 struct { 1766 uint32_t addressLow; 1767 uint32_t addressHigh; 1768 } u; 1769 uint64_t address; 1770 } mfi_address; 1771 #endif 1772 1773 #define MEGASAS_MAX_NAME 32 1774 #define MEGASAS_VERSION "4.23" 1775 1776 #endif /* _DEV_IC_MFIREG_H_ */ 1777
Indexes created Wed Oct 22 13:09:56 GMT 2025