mfireg.h revision 1.8.38.2
1 /* $NetBSD: mfireg.h,v 1.8.38.2 2020/04/13 08:04:21 martin Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco (at) peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Copyright (c) 2007 LSI Corp. 21 * Copyright (c) 2007 Rajesh Prabhakaran. 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46 #ifndef _DEV_IC_MFIREG_H_ 47 #define _DEV_IC_MFIREG_H_ 48 49 /* management interface constants */ 50 #define MFI_MGMT_VD 0x01 51 #define MFI_MGMT_SD 0x02 52 53 /* generic constants */ 54 #define MFI_FRAME_SIZE 64 55 #define MFI_SENSE_SIZE 128 56 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 57 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 58 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 59 #define MFI_INVALID_CTX 0xffffffff 60 #define MFI_ENABLE_INTR 0x01 61 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 62 #define MFI_SECTOR_LEN 512 63 64 /* register offsets */ 65 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 66 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 67 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 68 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 69 #define MFI_IDB 0x20 /* inbound doorbell */ 70 #define MFI_ISTS 0x24 /* inbound intr stat */ 71 #define MFI_IMSK 0x28 /* inbound intr mask */ 72 #define MFI_ODB 0x2c /* outbound doorbell */ 73 #define MFI_OSTS 0x30 /* outbound intr stat */ 74 #define MFI_OMSK 0x34 /* outbound inter mask */ 75 #define MFI_IQP 0x40 /* inbound queue port */ 76 #define MFI_OQP 0x44 /* outbound queue port */ 77 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 78 #define MFI_OSP 0xb0 /* outbound scratch pad */ 79 80 /* ThunderBolt specific Register */ 81 #define MFI_RPI 0x6c /* reply_post_host_index */ 82 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 83 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 84 85 /* OCR registers */ 86 #define MFI_WSR 0x004 /* write sequence register */ 87 #define MFI_HDR 0x008 /* host diagnostic register */ 88 #define MFI_RSR 0x3c3 /* Reset Status Register */ 89 90 /* OCR specific flags */ 91 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 92 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 93 94 /* 95 * skinny specific changes 96 */ 97 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 98 #define MFI_IQPL 0x000000c0 99 #define MFI_IQPH 0x000000c4 100 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 101 102 /* * firmware states */ 103 #define MFI_STATE_MASK 0xf0000000 104 #define MFI_STATE_UNDEFINED 0x00000000 105 #define MFI_STATE_BB_INIT 0x10000000 106 #define MFI_STATE_FW_INIT 0x40000000 107 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 108 #define MFI_STATE_FW_INIT_2 0x70000000 109 #define MFI_STATE_DEVICE_SCAN 0x80000000 110 #define MFI_STATE_FLUSH_CACHE 0xa0000000 111 #define MFI_STATE_READY 0xb0000000 112 #define MFI_STATE_OPERATIONAL 0xc0000000 113 #define MFI_STATE_FAULT 0xf0000000 114 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 115 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 116 #define MFI_STATE_HOSTMEMREQD_MASK 0x08000000 117 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 118 #define MFI_RESET_REQUIRED 0x00000001 119 120 /* ThunderBolt Support */ 121 #define MFI_STATE_TB_MASK 0xf0000000 122 #define MFI_STATE_TB_RESET 0x00000000 123 #define MFI_STATE_TB_READY 0x10000000 124 #define MFI_STATE_TB_OPERATIONAL 0x20000000 125 #define MFI_STATE_TB_FAULT 0x40000000 126 127 /* command reset register */ 128 #define MFI_INIT_ABORT 0x00000000 129 #define MFI_INIT_READY 0x00000002 130 #define MFI_INIT_MFIMODE 0x00000004 131 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 132 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 133 #define MFI_INIT_HOTPLUG 0x00000010 134 135 /* ADP reset flags */ 136 #define MFI_STOP_ADP 0x00000020 137 #define MFI_ADP_RESET 0x00000040 138 #define DIAG_WRITE_ENABLE 0x00000080 139 #define DIAG_RESET_ADAPTER 0x00000004 140 141 /* mfi Frame flags */ 142 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 143 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 144 #define MFI_FRAME_SGL32 0x0000 145 #define MFI_FRAME_SGL64 0x0002 146 #define MFI_FRAME_SENSE32 0x0000 147 #define MFI_FRAME_SENSE64 0x0004 148 #define MFI_FRAME_DIR_NONE 0x0000 149 #define MFI_FRAME_DIR_WRITE 0x0008 150 #define MFI_FRAME_DIR_READ 0x0010 151 #define MFI_FRAME_DIR_BOTH 0x0018 152 #define MFI_FRAME_IEEE_SGL 0x0020 153 154 /* ThunderBolt Specific */ 155 156 /* 157 * Pre-TB command size and TB command size. 158 * We will be checking it at the load time for the time being 159 */ 160 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 161 162 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 163 /* 164 * We are defining only 128 byte message to reduce memory move over head 165 * and also it will reduce the SRB extension size by 128byte compared with 166 * 256 message size 167 */ 168 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 169 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 170 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 171 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 172 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 173 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 174 175 /* 176 * Calculating how many SGEs allowed in a allocated main message 177 * (size of the Message - Raid SCSI IO message size(except SGE)) 178 * / size of SGE 179 * (0x100 - (0x90 - 0x10)) / 0x10 = 8 180 */ 181 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG \ 182 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - \ 183 (sizeof(struct mfi_mpi2_request_raid_scsi_io) - sizeof(mpi2_sge_io_union))\ 184 ) / sizeof(mpi2_sge_io_union)) 185 186 /* 187 * (Command frame size allocaed in SRB ext - Raid SCSI IO message size) 188 * / size of SGL ; 189 * (1280 - 256) / 16 = 64 190 */ 191 #define MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG \ 192 ((MR_COMMAND_SIZE - MEGASAS_THUNDERBOLT_NEW_MSG_SIZE) / \ 193 sizeof(mpi2_sge_io_union)) 194 195 /* 196 * This is the offset in number of 4 * 32bit words to the next chain 197 * (0x100 - 0x10)/0x10 = 0xF(15) 198 */ 199 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG \ 200 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - sizeof(mpi2_sge_io_union)) / 16) 201 202 #define MEGASAS_THUNDERBOLT_CHAIN_OFF_MPT_PTMSG \ 203 (offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16) 204 205 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 206 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 207 208 #define MR_INTERNAL_MFI_FRAMES_SMID 1 209 #define MR_CTRL_EVENT_WAIT_SMID 2 210 #define MR_INTERNAL_DRIVER_RESET_SMID 3 211 212 /* mfi command opcodes */ 213 #define MFI_CMD_INIT 0x00 214 #define MFI_CMD_LD_READ 0x01 215 #define MFI_CMD_LD_WRITE 0x02 216 #define MFI_CMD_LD_SCSI_IO 0x03 217 #define MFI_CMD_PD_SCSI_IO 0x04 218 #define MFI_CMD_DCMD 0x05 219 #define MFI_CMD_ABORT 0x06 220 #define MFI_CMD_SMP 0x07 221 #define MFI_CMD_STP 0x08 222 223 /* direct commands */ 224 #define MR_DCMD_CTRL_GET_INFO 0x01010000 225 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 226 #define MR_FLUSH_CTRL_CACHE 0x01 227 #define MR_FLUSH_DISK_CACHE 0x02 228 #define MR_DCMD_CTRL_HOST_MEM_ALLOC 0x0100e100 229 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 230 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 231 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 232 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 233 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 234 #define MR_DCMD_PD_GET_LIST 0x02010000 235 #define MR_DCMD_PD_LIST_QUERY 0x02010100 236 #define MR_DCMD_PD_GET_INFO 0x02020000 237 #define MR_DCMD_PD_SET_STATE 0x02030100 238 #define MR_DCMD_PD_REBUILD 0x02040100 239 #define MR_DCMD_PD_BLINK 0x02070100 240 #define MR_DCMD_PD_UNBLINK 0x02070200 241 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 242 #define MR_DCMD_LD_SYNC 0x0300e102 243 #define MR_DCMD_LD_GET_LIST 0x03010000 244 #define MR_DCMD_LD_GET_INFO 0x03020000 245 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 246 #define MR_DCMD_CONF_GET 0x04010000 247 #define MR_DCMD_CFG_ADD 0x04020000 248 #define MR_DCMD_CFG_CLEAR 0x04030000 249 #define MR_DCMD_CFG_MAKE_SPARE 0x04040000 250 #define MR_DCMD_CFG_FOREIGN_SCAN 0x04060100 251 #define MR_DCMD_CFG_FOREIGN_CLEAR 0x04060500 252 #define MR_DCMD_BBU_GET_STATUS 0x05010000 253 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 254 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 255 #define MR_DCMD_CLUSTER 0x08000000 256 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 257 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 258 259 #define MR_DCMD_SPEAKER_GET 0x01030100 260 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 261 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 262 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 263 #define MR_DCMD_SPEAKER_TEST 0x01030500 264 265 /* mailbox bytes in direct command */ 266 #define MFI_MBOX_SIZE 12 267 268 union mfi_mbox { 269 uint8_t b[MFI_MBOX_SIZE]; 270 uint16_t s[6]; 271 uint32_t w[3]; 272 }; 273 274 /* mfi completion codes */ 275 typedef enum { 276 MFI_STAT_OK = 0x00, 277 MFI_STAT_INVALID_CMD = 0x01, 278 MFI_STAT_INVALID_DCMD = 0x02, 279 MFI_STAT_INVALID_PARAMETER = 0x03, 280 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 281 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 282 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 283 MFI_STAT_APP_IN_USE = 0x07, 284 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 285 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 286 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 287 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 288 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 289 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 290 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 291 MFI_STAT_FLASH_BUSY = 0x0f, 292 MFI_STAT_FLASH_ERROR = 0x10, 293 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 294 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 295 MFI_STAT_FLASH_NOT_OPEN = 0x13, 296 MFI_STAT_FLASH_NOT_STARTED = 0x14, 297 MFI_STAT_FLUSH_FAILED = 0x15, 298 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 299 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 300 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 301 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 302 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 303 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 304 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 305 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 306 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 307 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 308 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 309 MFI_STAT_MFC_HW_ERROR = 0x21, 310 MFI_STAT_NO_HW_PRESENT = 0x22, 311 MFI_STAT_NOT_FOUND = 0x23, 312 MFI_STAT_NOT_IN_ENCL = 0x24, 313 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 314 MFI_STAT_PD_TYPE_WRONG = 0x26, 315 MFI_STAT_PR_DISABLED = 0x27, 316 MFI_STAT_ROW_INDEX_INVALID = 0x28, 317 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 318 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 319 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 320 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 321 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 322 MFI_STAT_SCSI_IO_FAILED = 0x2e, 323 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 324 MFI_STAT_SHUTDOWN_FAILED = 0x30, 325 MFI_STAT_TIME_NOT_SET = 0x31, 326 MFI_STAT_WRONG_STATE = 0x32, 327 MFI_STAT_LD_OFFLINE = 0x33, 328 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 329 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 330 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 331 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 332 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 333 MFI_STAT_INVALID_STATUS = 0xff 334 } mfi_status_t; 335 336 typedef enum { 337 MFI_EVT_CLASS_DEBUG = -2, 338 MFI_EVT_CLASS_PROGRESS = -1, 339 MFI_EVT_CLASS_INFO = 0, 340 MFI_EVT_CLASS_WARNING = 1, 341 MFI_EVT_CLASS_CRITICAL = 2, 342 MFI_EVT_CLASS_FATAL = 3, 343 MFI_EVT_CLASS_DEAD = 4 344 } mfi_evt_class_t; 345 346 typedef enum { 347 MFI_EVT_LOCALE_LD = 0x0001, 348 MFI_EVT_LOCALE_PD = 0x0002, 349 MFI_EVT_LOCALE_ENCL = 0x0004, 350 MFI_EVT_LOCALE_BBU = 0x0008, 351 MFI_EVT_LOCALE_SAS = 0x0010, 352 MFI_EVT_LOCALE_CTRL = 0x0020, 353 MFI_EVT_LOCALE_CONFIG = 0x0040, 354 MFI_EVT_LOCALE_CLUSTER = 0x0080, 355 MFI_EVT_LOCALE_ALL = 0xffff 356 } mfi_evt_locale_t; 357 358 typedef enum { 359 MR_EVT_ARGS_NONE = 0x00, 360 MR_EVT_ARGS_CDB_SENSE, 361 MR_EVT_ARGS_LD, 362 MR_EVT_ARGS_LD_COUNT, 363 MR_EVT_ARGS_LD_LBA, 364 MR_EVT_ARGS_LD_OWNER, 365 MR_EVT_ARGS_LD_LBA_PD_LBA, 366 MR_EVT_ARGS_LD_PROG, 367 MR_EVT_ARGS_LD_STATE, 368 MR_EVT_ARGS_LD_STRIP, 369 MR_EVT_ARGS_PD, 370 MR_EVT_ARGS_PD_ERR, 371 MR_EVT_ARGS_PD_LBA, 372 MR_EVT_ARGS_PD_LBA_LD, 373 MR_EVT_ARGS_PD_PROG, 374 MR_EVT_ARGS_PD_STATE, 375 MR_EVT_ARGS_PCI, 376 MR_EVT_ARGS_RATE, 377 MR_EVT_ARGS_STR, 378 MR_EVT_ARGS_TIME, 379 MR_EVT_ARGS_ECC 380 } mfi_evt_args; 381 382 /* XXX should be in mfi_evt_args ? */ 383 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 384 #define MR_EVT_ARGS_PD_ADDRESS 0x1d 385 #define MR_EVT_PD_INSERTED 0x005b 386 #define MR_EVT_PD_REMOVED 0x0070 387 #define MR_EVT_PD_STATE_CHANGE 0x0072 388 #define MR_EVT_LD_CHANGE 0x0051 389 #define MR_EVT_LD_CREATED 0x008a 390 #define MR_EVT_LD_DELETED 0x008b 391 #define MR_EVT_PD_REMOVED_EXT 0x00f8 392 #define MR_EVT_PD_INSERTED_EXT 0x00f7 393 394 395 396 typedef enum { 397 MR_PD_QUERY_TYPE_ALL = 0, 398 MR_PD_QUERY_TYPE_STATE = 1, 399 MR_PD_QUERY_TYPE_POWER_STATE = 2, 400 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 401 MR_PD_QUERY_TYPE_SPEED = 4, 402 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 403 } mfi_pd_query_type; 404 405 /* driver definitions */ 406 #define MFI_MAX_PD_CHANNELS 2 407 #define MFI_MAX_PD_ARRAY 32 408 #define MFI_MAX_LD_CHANNELS 2 409 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 410 #define MFI_MAX_CHANNEL_DEVS 128 411 #define MFI_DEFAULT_ID -1 412 #define MFI_MAX_LUN 8 413 #define MFI_MAX_LD 64 414 #define MFI_MAX_SPAN 8 415 #define MFI_MAX_ARRAY_DEDICATED 16 416 417 /* sense buffer */ 418 struct mfi_sense { 419 uint8_t mse_data[MFI_SENSE_SIZE]; 420 }; 421 422 /* scatter gather elements */ 423 struct mfi_sg32 { 424 uint32_t addr; 425 uint32_t len; 426 }; 427 428 struct mfi_sg64 { 429 uint64_t addr; 430 uint32_t len; 431 } __packed; 432 433 struct mfi_sg_ieee { 434 uint64_t addr; 435 uint32_t len; 436 uint32_t flags; 437 }; 438 439 440 union mfi_sgl { 441 struct mfi_sg32 sg32[1]; 442 struct mfi_sg64 sg64[1]; 443 struct mfi_sg_ieee sg_ieee[1]; 444 }; 445 446 /* message frame */ 447 struct mfi_frame_header { 448 uint8_t mfh_cmd; 449 uint8_t mfh_sense_len; 450 uint8_t mfh_cmd_status; 451 uint8_t mfh_scsi_status; 452 uint8_t mfh_target_id; 453 uint8_t mfh_lun_id; 454 uint8_t mfh_cdb_len; 455 uint8_t mfh_sg_count; 456 uint32_t mfh_context; 457 uint32_t mfh_pad0; 458 uint16_t mfh_flags; 459 uint16_t mfh_timeout; 460 uint32_t mfh_data_len; 461 }; 462 463 union mfi_sgl_frame { 464 struct mfi_sg32 sge32[8]; 465 struct mfi_sg64 sge64[5]; 466 467 } __packed; 468 469 struct mfi_init_frame { 470 struct mfi_frame_header mif_header; 471 uint32_t mif_qinfo_new_addr_lo; 472 uint32_t mif_qinfo_new_addr_hi; 473 uint32_t mif_qinfo_old_addr_lo; 474 uint32_t mif_qinfo_old_addr_hi; 475 uint32_t driver_ver_lo; /* 0x28 */ 476 uint32_t driver_ver_hi; /* 0x2c */ 477 uint32_t reserved[4]; 478 } __packed; 479 480 /* queue init structure */ 481 struct mfi_init_qinfo { 482 uint32_t miq_flags; 483 uint32_t miq_rq_entries; 484 uint32_t miq_rq_addr_lo; 485 uint32_t miq_rq_addr_hi; 486 uint32_t miq_pi_addr_lo; 487 uint32_t miq_pi_addr_hi; 488 uint32_t miq_ci_addr_lo; 489 uint32_t miq_ci_addr_hi; 490 } __packed; 491 492 #define MFI_IO_FRAME_SIZE 40 493 struct mfi_io_frame { 494 struct mfi_frame_header mif_header; 495 uint32_t mif_sense_addr_lo; 496 uint32_t mif_sense_addr_hi; 497 uint32_t mif_lba_lo; 498 uint32_t mif_lba_hi; 499 union mfi_sgl mif_sgl; 500 } __packed; 501 502 #define MFI_PASS_FRAME_SIZE 48 503 struct mfi_pass_frame { 504 struct mfi_frame_header mpf_header; 505 uint32_t mpf_sense_addr_lo; 506 uint32_t mpf_sense_addr_hi; 507 uint8_t mpf_cdb[16]; 508 union mfi_sgl mpf_sgl; 509 } __packed; 510 511 #define MFI_DCMD_FRAME_SIZE 40 512 struct mfi_dcmd_frame { 513 struct mfi_frame_header mdf_header; 514 uint32_t mdf_opcode; 515 union mfi_mbox mdf_mbox; 516 union mfi_sgl mdf_sgl; 517 }; 518 #define MFI_DCMD_MBOX_PEND_FLAG 0x1 519 520 struct mfi_abort_frame { 521 struct mfi_frame_header maf_header; 522 uint32_t maf_abort_context; 523 uint32_t maf_pad; 524 uint32_t maf_abort_mfi_addr_lo; 525 uint32_t maf_abort_mfi_addr_hi; 526 uint32_t maf_reserved[6]; 527 }; 528 529 struct mfi_smp_frame { 530 struct mfi_frame_header msf_header; 531 uint64_t msf_sas_addr; 532 union { 533 struct mfi_sg32 sg32[2]; 534 struct mfi_sg64 sg64[2]; 535 } msf_sgl; 536 } __packed; 537 538 struct mfi_stp_frame { 539 struct mfi_frame_header msf_header; 540 uint16_t msf_fis[10]; 541 uint32_t msf_stp_flags; 542 union { 543 struct mfi_sg32 sg32[2]; 544 struct mfi_sg64 sg64[2]; 545 } msf_sgl; 546 } __packed; 547 548 union mfi_frame { 549 struct mfi_frame_header mfr_header; 550 struct mfi_init_frame mfr_init; 551 struct mfi_io_frame mfr_io; 552 struct mfi_pass_frame mfr_pass; 553 struct mfi_dcmd_frame mfr_dcmd; 554 struct mfi_abort_frame mfr_abort; 555 struct mfi_smp_frame mfr_smp; 556 struct mfi_stp_frame mfr_stp; 557 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 558 }; 559 560 union mfi_evt_class_locale { 561 struct { 562 uint16_t locale; 563 uint8_t reserved; 564 int8_t class; 565 } mec_members; 566 uint32_t mec_word; 567 }; 568 569 struct mfi_evt_log_info { 570 uint32_t mel_newest_seq_num; 571 uint32_t mel_oldest_seq_num; 572 uint32_t mel_clear_seq_num; 573 uint32_t mel_shutdown_seq_num; 574 uint32_t mel_boot_seq_num; 575 }; 576 577 struct mfi_progress { 578 uint16_t mp_progress; 579 uint16_t mp_elapsed_seconds; 580 }; 581 582 struct mfi_evtarg_ld { 583 uint16_t mel_target_id; 584 uint8_t mel_ld_index; 585 uint8_t mel_reserved; 586 }; 587 588 struct mfi_evtarg_pd { 589 uint16_t mep_device_id; 590 uint8_t mep_encl_index; 591 uint8_t mep_slot_number; 592 }; 593 594 struct mfi_evtarg_pd_state { 595 struct mfi_evtarg_pd pd; 596 uint32_t prev_state; 597 uint32_t new_state; 598 }; 599 600 struct mfi_evtarg_pd_address { 601 uint16_t device_id; 602 uint16_t encl_id; 603 604 union { 605 struct { 606 uint8_t encl_index; 607 uint8_t slot_number; 608 } pd_address; 609 struct { 610 uint8_t encl_position; 611 uint8_t encl_connector_index; 612 } encl_address; 613 } address; 614 615 uint8_t scsi_dev_type; 616 617 union { 618 uint8_t port_bitmap; 619 uint8_t port_numbers; 620 } connected; 621 622 uint64_t sas_addr[2]; 623 }; 624 625 struct mfi_evt_detail { 626 uint32_t med_seq_num; 627 uint32_t med_time_stamp; 628 uint32_t med_code; 629 union mfi_evt_class_locale med_cl; 630 uint8_t med_arg_type; 631 uint8_t med_reserved1[15]; 632 633 union { 634 struct { 635 struct mfi_evtarg_pd pd; 636 uint8_t cdb_length; 637 uint8_t sense_length; 638 uint8_t reserved[2]; 639 uint8_t cdb[16]; 640 uint8_t sense[64]; 641 } __packed cdb_sense; 642 643 struct mfi_evtarg_ld ld; 644 645 struct { 646 struct mfi_evtarg_ld ld; 647 uint64_t count; 648 } __packed ld_count; 649 650 struct { 651 uint64_t lba; 652 struct mfi_evtarg_ld ld; 653 } __packed ld_lba; 654 655 struct { 656 struct mfi_evtarg_ld ld; 657 uint32_t prev_owner; 658 uint32_t new_owner; 659 } __packed ld_owner; 660 661 struct { 662 uint64_t ld_lba; 663 uint64_t pd_lba; 664 struct mfi_evtarg_ld ld; 665 struct mfi_evtarg_pd pd; 666 } __packed ld_lba_pd_lba; 667 668 struct { 669 struct mfi_evtarg_ld ld; 670 struct mfi_progress prog; 671 } __packed ld_prog; 672 673 struct { 674 struct mfi_evtarg_ld ld; 675 uint32_t prev_state; 676 uint32_t new_state; 677 } __packed ld_state; 678 679 struct { 680 uint64_t strip; 681 struct mfi_evtarg_ld ld; 682 } __packed ld_strip; 683 684 struct mfi_evtarg_pd pd; 685 686 struct { 687 struct mfi_evtarg_pd pd; 688 uint32_t err; 689 } __packed pd_err; 690 691 struct { 692 uint64_t lba; 693 struct mfi_evtarg_pd pd; 694 } __packed pd_lba; 695 696 struct { 697 uint64_t lba; 698 struct mfi_evtarg_pd pd; 699 struct mfi_evtarg_ld ld; 700 } __packed pd_lba_ld; 701 702 struct { 703 struct mfi_evtarg_pd pd; 704 struct mfi_progress prog; 705 } __packed pd_prog; 706 707 struct mfi_evtarg_pd_state pd_state; 708 709 struct { 710 uint16_t vendor_id; 711 uint16_t device_id; 712 uint16_t subvendor_id; 713 uint16_t subdevice_id; 714 } __packed pci; 715 716 uint32_t rate; 717 char str[96]; 718 719 struct { 720 uint32_t rtc; 721 uint32_t elapsed_seconds; 722 } __packed time; 723 724 struct { 725 uint32_t ecar; 726 uint32_t elog; 727 char str[64]; 728 } __packed ecc; 729 730 struct mfi_evtarg_pd_address pd_address; 731 732 uint8_t b[96]; 733 uint16_t s[48]; 734 uint32_t w[24]; 735 uint64_t d[12]; 736 } args; 737 738 char med_description[128]; 739 } __packed; 740 741 /* controller properties from mfi_ctrl_info */ 742 struct mfi_ctrl_props { 743 uint16_t mcp_seq_num; 744 uint16_t mcp_pred_fail_poll_interval; 745 uint16_t mcp_intr_throttle_cnt; 746 uint16_t mcp_intr_throttle_timeout; 747 uint8_t mcp_rebuild_rate; 748 uint8_t mcp_patrol_read_rate; 749 uint8_t mcp_bgi_rate; 750 uint8_t mcp_cc_rate; 751 uint8_t mcp_recon_rate; 752 uint8_t mcp_cache_flush_interval; 753 uint8_t mcp_spinup_drv_cnt; 754 uint8_t mcp_spinup_delay; 755 uint8_t mcp_cluster_enable; 756 uint8_t mcp_coercion_mode; 757 uint8_t mcp_alarm_enable; 758 uint8_t mcp_disable_auto_rebuild; 759 uint8_t mcp_disable_battery_warn; 760 uint8_t mcp_ecc_bucket_size; 761 uint16_t mcp_ecc_bucket_leak_rate; 762 uint8_t mcp_restore_hotspare_on_insertion; 763 uint8_t mcp_expose_encl_devices; 764 uint8_t maintainPdFailHistory; 765 uint8_t disallowHostRequestReordering; 766 /* set TRUE to abort CC on detecting an inconsistency */ 767 uint8_t abortCCOnError; 768 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 769 uint8_t loadBalanceMode; 770 /* 771 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 772 * h/w mechansim like GPIO pins 773 * 1 - disable auto detect SGPIO, 774 * 2 - disable i2c SEP auto detect 775 * 3 - disable both auto detect 776 */ 777 uint8_t disableAutoDetectBackplane; 778 /* 779 * % of source LD to be reserved for a VDs snapshot in snapshot 780 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 781 */ 782 uint8_t snapVDSpace; 783 784 /* 785 * Add properties that can be controlled by a bit in the following 786 * structure. 787 */ 788 struct { 789 /* set TRUE to disable copyBack (0=copback enabled) */ 790 uint32_t copyBackDisabled :1; 791 uint32_t SMARTerEnabled :1; 792 uint32_t prCorrectUnconfiguredAreas :1; 793 uint32_t useFdeOnly :1; 794 uint32_t disableNCQ :1; 795 uint32_t SSDSMARTerEnabled :1; 796 uint32_t SSDPatrolReadEnabled :1; 797 uint32_t enableSpinDownUnconfigured :1; 798 uint32_t autoEnhancedImport :1; 799 uint32_t enableSecretKeyControl :1; 800 uint32_t disableOnlineCtrlReset :1; 801 uint32_t allowBootWithPinnedCache :1; 802 uint32_t disableSpinDownHS :1; 803 uint32_t enableJBOD :1; 804 uint32_t reserved :18; 805 } OnOffProperties; 806 /* 807 * % of source LD to be reserved for auto snapshot in snapshot 808 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 809 */ 810 uint8_t autoSnapVDSpace; 811 /* 812 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 813 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 814 */ 815 uint8_t viewSpace; 816 /* # of idle minutes before device is spun down (0=use FW defaults) */ 817 uint16_t spinDownTime; 818 uint8_t reserved[24]; 819 } __packed; 820 821 /* pci info */ 822 struct mfi_info_pci { 823 uint16_t mip_vendor; 824 uint16_t mip_device; 825 uint16_t mip_subvendor; 826 uint16_t mip_subdevice; 827 uint8_t mip_reserved[24]; 828 } __packed; 829 830 /* host interface infor */ 831 struct mfi_info_host { 832 uint8_t mih_type; 833 #define MFI_INFO_HOST_PCIX 0x01 834 #define MFI_INFO_HOST_PCIE 0x02 835 #define MFI_INFO_HOST_ISCSI 0x04 836 #define MFI_INFO_HOST_SAS3G 0x08 837 uint8_t mih_reserved[6]; 838 uint8_t mih_port_count; 839 uint64_t mih_port_addr[8]; 840 } __packed; 841 842 /* device interface info */ 843 struct mfi_info_device { 844 uint8_t mid_type; 845 #define MFI_INFO_DEV_SPI 0x01 846 #define MFI_INFO_DEV_SAS3G 0x02 847 #define MFI_INFO_DEV_SATA1 0x04 848 #define MFI_INFO_DEV_SATA3G 0x08 849 uint8_t mid_reserved[6]; 850 uint8_t mid_port_count; 851 uint64_t mid_port_addr[8]; 852 } __packed; 853 854 /* firmware component info */ 855 struct mfi_info_component { 856 char mic_name[8]; 857 char mic_version[32]; 858 char mic_build_date[16]; 859 char mic_build_time[16]; 860 } __packed; 861 862 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 863 struct mfi_ctrl_info { 864 struct mfi_info_pci mci_pci; 865 struct mfi_info_host mci_host; 866 struct mfi_info_device mci_device; 867 868 /* Firmware components that are present and active. */ 869 uint32_t mci_image_check_word; 870 uint32_t mci_image_component_count; 871 struct mfi_info_component mci_image_component[8]; 872 873 /* Firmware components that have been flashed but are inactive */ 874 uint32_t mci_pending_image_component_count; 875 struct mfi_info_component mci_pending_image_component[8]; 876 877 uint8_t mci_max_arms; 878 uint8_t mci_max_spans; 879 uint8_t mci_max_arrays; 880 uint8_t mci_max_lds; 881 char mci_product_name[80]; 882 char mci_serial_number[32]; 883 uint32_t mci_hw_present; 884 #define MFI_INFO_HW_BBU 0x01 885 #define MFI_INFO_HW_ALARM 0x02 886 #define MFI_INFO_HW_NVRAM 0x04 887 #define MFI_INFO_HW_UART 0x08 888 uint32_t mci_current_fw_time; 889 uint16_t mci_max_cmds; 890 uint16_t mci_max_sg_elements; 891 uint32_t mci_max_request_size; 892 uint16_t mci_lds_present; 893 uint16_t mci_lds_degraded; 894 uint16_t mci_lds_offline; 895 uint16_t mci_pd_present; 896 uint16_t mci_pd_disks_present; 897 uint16_t mci_pd_disks_pred_failure; 898 uint16_t mci_pd_disks_failed; 899 uint16_t mci_nvram_size; 900 uint16_t mci_memory_size; 901 uint16_t mci_flash_size; 902 uint16_t mci_ram_correctable_errors; 903 uint16_t mci_ram_uncorrectable_errors; 904 uint8_t mci_cluster_allowed; 905 uint8_t mci_cluster_active; 906 uint16_t mci_max_strips_per_io; 907 908 uint32_t mci_raid_levels; 909 #define MFI_INFO_RAID_0 0x01 910 #define MFI_INFO_RAID_1 0x02 911 #define MFI_INFO_RAID_5 0x04 912 #define MFI_INFO_RAID_1E 0x08 913 #define MFI_INFO_RAID_6 0x10 914 915 uint32_t mci_adapter_ops; 916 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 917 #define MFI_INFO_AOPS_CC_RATE 0x0002 918 #define MFI_INFO_AOPS_BGI_RATE 0x0004 919 #define MFI_INFO_AOPS_RECON_RATE 0x0008 920 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 921 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 922 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 923 #define MFI_INFO_AOPS_BBU 0x0080 924 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 925 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 926 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 927 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 928 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 929 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 930 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 931 932 uint32_t mci_ld_ops; 933 #define MFI_INFO_LDOPS_READ_POLICY 0x01 934 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 935 #define MFI_INFO_LDOPS_IO_POLICY 0x04 936 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 937 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 938 939 struct { 940 uint8_t min; 941 uint8_t max; 942 uint8_t reserved[2]; 943 } __packed mci_stripe_sz_ops; 944 945 uint32_t mci_pd_ops; 946 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 947 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 948 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 949 950 uint32_t mci_pd_mix_support; 951 #define MFI_INFO_PDMIX_SAS 0x01 952 #define MFI_INFO_PDMIX_SATA 0x02 953 #define MFI_INFO_PDMIX_ENCL 0x04 954 #define MFI_INFO_PDMIX_LD 0x08 955 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 956 957 uint8_t mci_ecc_bucket_count; 958 uint8_t mci_reserved2[11]; 959 struct mfi_ctrl_props mci_properties; 960 char mci_package_version[0x60]; 961 uint8_t mci_pad[0x800 - 0x6a0]; 962 } __packed; 963 964 /* logical disk info from MR_DCMD_LD_GET_LIST */ 965 struct mfi_ld { 966 uint8_t mld_target; 967 uint8_t mld_res; 968 uint16_t mld_seq; 969 } __packed; 970 971 struct mfi_ld_list { 972 uint32_t mll_no_ld; 973 uint32_t mll_res; 974 struct { 975 struct mfi_ld mll_ld; 976 uint8_t mll_state; 977 #define MFI_LD_OFFLINE 0x00 978 #define MFI_LD_PART_DEGRADED 0x01 979 #define MFI_LD_DEGRADED 0x02 980 #define MFI_LD_ONLINE 0x03 981 uint8_t mll_res2; 982 uint8_t mll_res3; 983 uint8_t mll_res4; 984 u_quad_t mll_size; 985 } mll_list[MFI_MAX_LD]; 986 } __packed; 987 988 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 989 struct mfi_ld_prop { 990 struct mfi_ld mlp_ld; 991 char mlp_name[16]; 992 uint8_t mlp_cache_policy; 993 uint8_t mlp_acces_policy; 994 uint8_t mlp_diskcache_policy; 995 uint8_t mlp_cur_cache_policy; 996 uint8_t mlp_disable_bgi; 997 uint8_t mlp_res[7]; 998 } __packed; 999 1000 struct mfi_ld_parm { 1001 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 1002 #define MFI_DDF_PRL_RAID0 0x00 1003 #define MFI_DDF_PRL_RAID1 0x01 1004 #define MFI_DDF_PRL_RAID3 0x03 1005 #define MFI_DDF_PRL_RAID4 0x04 1006 #define MFI_DDF_PRL_RAID5 0x05 1007 #define MFI_DDF_PRL_RAID1E 0x11 1008 #define MFI_DDF_PRL_JBOD 0x0f 1009 #define MFI_DDF_PRL_CONCAT 0x1f 1010 #define MFI_DDF_PRL_RAID5E 0x15 1011 #define MFI_DDF_PRL_RAID5EE 0x25 1012 #define MFI_DDF_PRL_RAID6 0x16 1013 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 1014 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 1015 #define MFI_DDF_SRL_STRIPED 0x00 1016 #define MFI_DDF_SRL_MIRRORED 0x01 1017 #define MFI_DDF_SRL_CONCAT 0x02 1018 #define MFI_DDF_SRL_SPANNED 0x03 1019 uint8_t mpa_stripe_size; 1020 uint8_t mpa_no_drv_per_span; 1021 uint8_t mpa_span_depth; 1022 uint8_t mpa_state; 1023 uint8_t mpa_init_state; 1024 uint8_t mpa_is_consistent; 1025 uint8_t mpa_res1[6]; 1026 uint8_t mpa_isSSCD; 1027 uint8_t mpa_res[16]; 1028 } __packed; 1029 1030 struct mfi_ld_span { 1031 u_quad_t mls_start_block; 1032 u_quad_t mls_no_blocks; 1033 uint16_t mls_index; 1034 uint8_t mls_res[6]; 1035 } __packed; 1036 1037 struct mfi_ld_cfg { 1038 struct mfi_ld_prop mlc_prop; 1039 struct mfi_ld_parm mlc_parm; 1040 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 1041 } __packed; 1042 1043 struct mfi_ld_progress { 1044 uint32_t mlp_in_prog; 1045 #define MFI_LD_PROG_CC 0x01 1046 #define MFI_LD_PROG_BGI 0x02 1047 #define MFI_LD_PROG_FGI 0x04 1048 #define MFI_LD_PROG_RECONSTRUCT 0x08 1049 struct mfi_progress mlp_cc; 1050 struct mfi_progress mlp_bgi; 1051 struct mfi_progress mlp_fgi; 1052 struct mfi_progress mlp_reconstruct; 1053 struct mfi_progress mlp_res[4]; 1054 } __packed; 1055 1056 struct mfi_ld_details { 1057 struct mfi_ld_cfg mld_cfg; 1058 u_quad_t mld_size; 1059 struct mfi_ld_progress mld_progress; 1060 uint16_t mld_clust_own_id; 1061 uint8_t mld_res1; 1062 uint8_t mld_res2; 1063 uint8_t mld_inq_page83[64]; 1064 uint8_t mld_res[16]; 1065 } __packed; 1066 1067 /* physical disk info from MR_DCMD_PD_GET_LIST */ 1068 struct mfi_pd_address { 1069 uint16_t mpa_pd_id; 1070 uint16_t mpa_enc_id; 1071 uint8_t mpa_enc_index; 1072 uint8_t mpa_enc_slot; 1073 uint8_t mpa_scsi_type; 1074 uint8_t mpa_port; 1075 u_quad_t mpa_sas_address[2]; 1076 } __packed; 1077 1078 #define MFI_MAX_PD 256 1079 struct mfi_pd_list { 1080 uint32_t mpl_size; 1081 uint32_t mpl_no_pd; 1082 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 1083 } __packed; 1084 #define MFI_PD_LIST_SIZE (sizeof(struct mfi_pd_list)) 1085 1086 struct mfi_pd { 1087 uint16_t mfp_id; 1088 uint16_t mfp_seq; 1089 } __packed; 1090 1091 struct mfi_pd_progress { 1092 uint32_t mfp_in_prog; 1093 #define MFI_PD_PROG_RBLD 0x01 1094 #define MFI_PD_PROG_PR 0x02 1095 #define MFI_PD_PROG_CLEAR 0x04 1096 struct mfi_progress mfp_rebuild; 1097 struct mfi_progress mfp_patrol_read; 1098 struct mfi_progress mfp_clear; 1099 struct mfi_progress mfp_res[4]; 1100 } __packed; 1101 1102 struct mfi_pd_details { 1103 struct mfi_pd mpd_pd; 1104 uint8_t mpd_inq_data[96]; 1105 uint8_t mpd_inq_page83[64]; 1106 uint8_t mpd_no_support; 1107 uint8_t mpd_scsy_type; 1108 uint8_t mpd_port; 1109 uint8_t mpd_speed; 1110 uint32_t mpd_mediaerr_cnt; 1111 uint32_t mpd_othererr_cnt; 1112 uint32_t mpd_predfail_cnt; 1113 uint32_t mpd_last_pred_event; 1114 uint16_t mpd_fw_state; 1115 uint8_t mpd_rdy_for_remove; 1116 uint8_t mpd_link_speed; 1117 uint32_t mpd_ddf_state; 1118 #define MFI_DDF_GUID_FORCED 0x01 1119 #define MFI_DDF_PART_OF_VD 0x02 1120 #define MFI_DDF_GLOB_HOTSPARE 0x04 1121 #define MFI_DDF_HOTSPARE 0x08 1122 #define MFI_DDF_FOREIGN 0x10 1123 #define MFI_DDF_TYPE_MASK 0xf000 1124 #define MFI_DDF_TYPE_UNKNOWN 0x0000 1125 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 1126 #define MFI_DDF_TYPE_SAS 0x2000 1127 #define MFI_DDF_TYPE_SATA 0x3000 1128 #define MFI_DDF_TYPE_FC 0x4000 1129 struct { 1130 uint8_t mpp_cnt; 1131 uint8_t mpp_severed; 1132 uint8_t mpp_res[6]; 1133 u_quad_t mpp_sas_addr[4]; 1134 } __packed mpd_path; 1135 u_quad_t mpd_size; 1136 u_quad_t mpd_no_coerce_size; 1137 u_quad_t mpd_coerce_size; 1138 uint16_t mpd_enc_id; 1139 uint8_t mpd_enc_idx; 1140 uint8_t mpd_enc_slot; 1141 struct mfi_pd_progress mpd_progress; 1142 uint8_t mpd_bblock_full; 1143 uint8_t mpd_unusable; 1144 uint8_t mpd_res[218]; /* size is 512 */ 1145 } __packed; 1146 1147 /* array configuration from MD_DCMD_CONF_GET */ 1148 struct mfi_array { 1149 u_quad_t mar_smallest_pd; 1150 uint8_t mar_no_disk; 1151 uint8_t mar_res1; 1152 uint16_t mar_array_ref; 1153 uint8_t mar_res2[20]; 1154 struct { 1155 struct mfi_pd mar_pd; 1156 uint16_t mar_pd_state; 1157 #define MFI_PD_UNCONFIG_GOOD 0x00 1158 #define MFI_PD_UNCONFIG_BAD 0x01 1159 #define MFI_PD_HOTSPARE 0x02 1160 #define MFI_PD_OFFLINE 0x10 1161 #define MFI_PD_FAILED 0x11 1162 #define MFI_PD_REBUILD 0x14 1163 #define MFI_PD_ONLINE 0x18 1164 #define MFI_PD_COPYBACK 0x20 1165 #define MFI_PD_SYSTEM 0x40 1166 #define MFI_PD_JBOD MFI_PD_SYSTEM 1167 uint8_t mar_enc_pd; 1168 uint8_t mar_enc_slot; 1169 } pd[MFI_MAX_PD_ARRAY]; 1170 } __packed; 1171 1172 /* informations from MR_DCMD_BBU_GET_CAPACITY_INFO */ 1173 struct mfi_bbu_capacity_info { 1174 uint16_t relative_charge; 1175 uint16_t absolute_charge; 1176 uint16_t remaining_capacity; 1177 uint16_t full_charge_capacity; 1178 uint16_t run_time_to_empty; 1179 uint16_t average_time_to_empty; 1180 uint16_t average_time_to_full; 1181 uint16_t cycle_count; 1182 uint16_t max_error; 1183 uint16_t remaining_capacity_alarm; 1184 uint16_t remaining_time_alarm; 1185 uint8_t reserved[26]; 1186 } __packed; 1187 1188 /* informations from MR_DCMD_BBU_GET_DESIGN_INFO */ 1189 struct mfi_bbu_design_info { 1190 uint32_t mfg_date; 1191 uint16_t design_capacity; 1192 uint16_t design_voltage; 1193 uint16_t spec_info; 1194 uint16_t serial_number; 1195 uint16_t pack_stat_config; 1196 uint8_t mfg_name[12]; 1197 uint8_t device_name[8]; 1198 uint8_t device_chemistry[8]; 1199 uint8_t mfg_data[8]; 1200 uint8_t reserved[17]; 1201 } __packed; 1202 1203 struct mfi_ibbu_state { 1204 uint16_t gas_guage_status; 1205 uint16_t relative_charge; 1206 uint16_t charger_system_state; 1207 uint16_t charger_system_ctrl; 1208 uint16_t charging_current; 1209 uint16_t absolute_charge; 1210 uint16_t max_error; 1211 uint8_t reserved[18]; 1212 } __packed; 1213 1214 struct mfi_bbu_state { 1215 uint16_t gas_guage_status; 1216 uint16_t relative_charge; 1217 uint16_t charger_status; 1218 uint16_t remaining_capacity; 1219 uint16_t full_charge_capacity; 1220 uint8_t is_SOH_good; 1221 uint8_t reserved[21]; 1222 } __packed; 1223 1224 union mfi_bbu_status_detail { 1225 struct mfi_ibbu_state ibbu; 1226 struct mfi_bbu_state bbu; 1227 }; 1228 1229 /* informations from MR_DCMD_BBU_GET_STATUS */ 1230 struct mfi_bbu_status { 1231 uint8_t battery_type; 1232 #define MFI_BBU_TYPE_NONE 0 1233 #define MFI_BBU_TYPE_IBBU 1 1234 #define MFI_BBU_TYPE_BBU 2 1235 uint8_t reserved; 1236 uint16_t voltage; 1237 int16_t current; 1238 uint16_t temperature; 1239 uint32_t fw_status; 1240 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1241 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1242 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1243 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1244 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1245 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1246 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1247 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1248 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1249 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1250 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1251 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1252 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1253 #define MFI_BBU_STATE_BAD_IBBU ( \ 1254 MFI_BBU_STATE_PACK_MISSING | \ 1255 MFI_BBU_STATE_VOLTAGE_LOW | \ 1256 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1257 MFI_BBU_STATE_LEARN_CYC_REQ | \ 1258 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1259 MFI_BBU_STATE_REPLACE_PACK | \ 1260 MFI_BBU_STATE_CAPACITY_LOW) 1261 #define MFI_BBU_STATE_BAD_BBU ( \ 1262 MFI_BBU_STATE_PACK_MISSING | \ 1263 MFI_BBU_STATE_REPLACE_PACK | \ 1264 MFI_BBU_STATE_CAPACITY_LOW) 1265 uint8_t pad[20]; 1266 union mfi_bbu_status_detail detail; 1267 } __packed; 1268 1269 struct mfi_hotspare { 1270 struct mfi_pd mhs_pd; 1271 uint8_t mhs_type; 1272 #define MFI_PD_HS_DEDICATED 0x01 1273 #define MFI_PD_HS_REVERTIBLE 0x02 1274 #define MFI_PD_HS_ENC_AFFINITY 0x04 1275 uint8_t mhs_res[2]; 1276 uint8_t mhs_array_max; 1277 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1278 } __packed; 1279 1280 struct mfi_conf { 1281 uint32_t mfc_size; 1282 uint16_t mfc_no_array; 1283 uint16_t mfc_array_size; 1284 uint16_t mfc_no_ld; 1285 uint16_t mfc_ld_size; 1286 uint16_t mfc_no_hs; 1287 uint16_t mfc_hs_size; 1288 uint8_t mfc_res[16]; 1289 /* 1290 * XXX this is a ridiculous hack and does not reflect reality 1291 * Structures are actually indexed and therefore need pointer 1292 * math to reach. We need the size of this structure first so 1293 * call it with the size of this structure and then use the returned 1294 * values to allocate memory and do the transfer of the whole structure 1295 * then calculate pointers to each of these structures. 1296 */ 1297 struct mfi_array mfc_array[1]; 1298 struct mfi_ld_cfg mfc_ld[1]; 1299 struct mfi_hotspare mfc_hs[1]; 1300 } __packed; 1301 1302 /* ThunderBolt support */ 1303 1304 /* 1305 * Raid Context structure which describes MegaRAID specific IO Paramenters 1306 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1307 */ 1308 typedef struct _mpi2_scsi_io_vendor_unique { 1309 uint16_t resvd0; /* 0x00 - 0x01 */ 1310 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1311 uint8_t regLockFlags; 1312 uint8_t armId; 1313 uint16_t TargetID; /* 0x06 - 0x07 */ 1314 1315 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1316 1317 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1318 1319 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1320 uint8_t exStatus; /* 0x16 */ 1321 uint8_t Status; /* 0x17 status */ 1322 1323 uint8_t RAIDFlags; /* 0x18 */ 1324 uint8_t numSGE; /* 0x19 numSge */ 1325 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1326 uint8_t spanArm; /* 0x1C */ 1327 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1328 } mpi2_scsi_io_vendor_unique, mpi25_scsi_io_vendor_unique; 1329 1330 /***************************************************************************** 1331 * 1332 * Message Functions 1333 * 1334 *****************************************************************************/ 1335 1336 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1337 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1338 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1339 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1340 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1341 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1342 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1343 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1344 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1345 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1346 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1347 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1348 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1349 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1350 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1351 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1352 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1353 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1354 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1355 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1356 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1357 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1358 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1359 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1360 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1361 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1362 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1363 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1364 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1365 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1366 1367 /* Doorbell functions */ 1368 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1369 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1370 1371 /***************************************************************************** 1372 * 1373 * MPI Version Definitions 1374 * 1375 *****************************************************************************/ 1376 1377 #define MPI2_VERSION_MAJOR (0x02) 1378 #define MPI2_VERSION_MINOR (0x00) 1379 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1380 #define MPI2_VERSION_MAJOR_SHIFT (8) 1381 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1382 #define MPI2_VERSION_MINOR_SHIFT (0) 1383 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1384 MPI2_VERSION_MINOR) 1385 1386 #define MPI2_VERSION_02_00 (0x0200) 1387 1388 /* versioning for this MPI header set */ 1389 #define MPI2_HEADER_VERSION_UNIT (0x10) 1390 #define MPI2_HEADER_VERSION_DEV (0x00) 1391 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1392 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1393 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1394 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1395 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1396 MPI2_HEADER_VERSION_DEV) 1397 1398 1399 /* IOCInit Request message */ 1400 struct mpi2_ioc_init_request { 1401 uint8_t WhoInit; /* 0x00 */ 1402 uint8_t Reserved1; /* 0x01 */ 1403 uint8_t ChainOffset; /* 0x02 */ 1404 uint8_t Function; /* 0x03 */ 1405 uint16_t Reserved2; /* 0x04 */ 1406 uint8_t Reserved3; /* 0x06 */ 1407 uint8_t MsgFlags; /* 0x07 */ 1408 uint8_t VP_ID; /* 0x08 */ 1409 uint8_t VF_ID; /* 0x09 */ 1410 uint16_t Reserved4; /* 0x0A */ 1411 uint16_t MsgVersion; /* 0x0C */ 1412 uint16_t HeaderVersion; /* 0x0E */ 1413 uint32_t Reserved5; /* 0x10 */ 1414 uint16_t Reserved6; /* 0x14 */ 1415 uint8_t Reserved7; /* 0x16 */ 1416 uint8_t HostMSIxVectors; /* 0x17 */ 1417 uint16_t Reserved8; /* 0x18 */ 1418 uint16_t SystemRequestFrameSize; /* 0x1A */ 1419 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1420 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1421 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1422 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1423 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1424 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1425 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1426 uint64_t TimeStamp; /* 0x40 */ 1427 }; 1428 1429 /* WhoInit values */ 1430 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1431 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1432 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1433 #define MPI2_WHOINIT_PCI_PEER (0x03) 1434 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1435 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1436 1437 struct mpi2_sge_chain_union { 1438 uint16_t Length; 1439 uint8_t NextChainOffset; 1440 uint8_t Flags; 1441 union { 1442 uint32_t Address32; 1443 uint64_t Address64; 1444 } u; 1445 }; 1446 1447 struct mpi2_ieee_sge_simple32 { 1448 uint32_t Address; 1449 uint32_t FlagsLength; 1450 }; 1451 1452 struct mpi2_ieee_sge_simple64 { 1453 uint64_t Address; 1454 uint32_t Length; 1455 uint16_t Reserved1; 1456 uint8_t Reserved2; 1457 uint8_t Flags; 1458 }; 1459 1460 typedef union _mpi2_ieee_simple_union { 1461 struct mpi2_ieee_sge_simple32 Simple32; 1462 struct mpi2_ieee_sge_simple64 Simple64; 1463 } mpi2_ieee_simple_union; 1464 1465 typedef struct _mpi2_sge_simple_union { 1466 uint32_t FlagsLength; 1467 union { 1468 uint32_t Address32; 1469 uint64_t Address64; 1470 } u; 1471 } mpi2_sge_simple_union; 1472 1473 /* MPI 2.5 SGLs */ 1474 1475 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1476 1477 struct mpi25_ieee_sge_chain64 { 1478 uint64_t Address; 1479 uint32_t Length; 1480 uint16_t Reserved1; 1481 uint8_t NextChainOffset; 1482 uint8_t Flags; 1483 }; 1484 1485 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1486 1487 /**************************************************************************** 1488 * IEEE SGE field definitions and masks 1489 ****************************************************************************/ 1490 1491 /* Flags field bit definitions */ 1492 1493 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1494 1495 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1496 1497 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1498 1499 /* Element Type */ 1500 1501 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1502 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1503 1504 /* Data Location Address Space */ 1505 1506 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1507 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1508 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1509 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1510 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1511 1512 /* Address Size */ 1513 1514 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1515 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1516 1517 /*******************/ 1518 /* SCSI IO Control bits */ 1519 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1520 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1521 1522 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1523 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1524 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1525 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1526 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1527 1528 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1529 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1530 1531 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1532 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1533 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1534 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1535 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1536 1537 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1538 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1539 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1540 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1541 1542 /*******************/ 1543 1544 typedef struct { 1545 uint8_t CDB[20]; /* 0x00 */ 1546 uint32_t PrimaryReferenceTag; /* 0x14 */ 1547 uint16_t PrimaryApplicationTag; /* 0x18 */ 1548 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1549 uint32_t TransferLength; /* 0x1C */ 1550 } mpi2_scsi_io_cdb_eedp32; 1551 1552 1553 typedef union _mpi2_ieee_sge_chain_union { 1554 struct mpi2_ieee_sge_simple32 Chain32; 1555 struct mpi25_ieee_sge_chain64 Chain64; 1556 } mpi2_ieee_sge_chain_union; 1557 1558 typedef union _mpi2_simple_sge_union { 1559 mpi2_sge_simple_union MpiSimple; 1560 mpi2_ieee_simple_union IeeeSimple; 1561 } mpi2_simple_sge_union; 1562 1563 typedef union _mpi2_sge_io_union { 1564 mpi2_sge_simple_union MpiSimple; 1565 struct mpi2_sge_chain_union MpiChain; 1566 mpi2_ieee_simple_union IeeeSimple; 1567 mpi2_ieee_sge_chain_union IeeeChain; 1568 } mpi2_sge_io_union; 1569 1570 typedef union { 1571 uint8_t CDB32[32]; 1572 mpi2_scsi_io_cdb_eedp32 EEDP32; 1573 mpi2_sge_simple_union SGE; 1574 } mpi2_scsi_io_cdb_union; 1575 1576 1577 1578 /********/ 1579 1580 /* 1581 * RAID SCSI IO Request Message 1582 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1583 */ 1584 struct mfi_mpi2_request_raid_scsi_io { 1585 uint16_t DevHandle; /* 0x00 */ 1586 uint8_t ChainOffset; /* 0x02 */ 1587 uint8_t Function; /* 0x03 */ 1588 uint16_t Reserved1; /* 0x04 */ 1589 uint8_t Reserved2; /* 0x06 */ 1590 uint8_t MsgFlags; /* 0x07 */ 1591 uint8_t VP_ID; /* 0x08 */ 1592 uint8_t VF_ID; /* 0x09 */ 1593 uint16_t Reserved3; /* 0x0A */ 1594 uint32_t SenseBufferLowAddress; /* 0x0C */ 1595 uint16_t SGLFlags; /* 0x10 */ 1596 uint8_t SenseBufferLength; /* 0x12 */ 1597 uint8_t Reserved4; /* 0x13 */ 1598 uint8_t SGLOffset0; /* 0x14 */ 1599 uint8_t SGLOffset1; /* 0x15 */ 1600 uint8_t SGLOffset2; /* 0x16 */ 1601 uint8_t SGLOffset3; /* 0x17 */ 1602 uint32_t SkipCount; /* 0x18 */ 1603 uint32_t DataLength; /* 0x1C */ 1604 uint32_t BidirectionalDataLength; /* 0x20 */ 1605 uint16_t IoFlags; /* 0x24 */ 1606 uint16_t EEDPFlags; /* 0x26 */ 1607 uint32_t EEDPBlockSize; /* 0x28 */ 1608 uint32_t SecondaryReferenceTag; /* 0x2C */ 1609 uint16_t SecondaryApplicationTag; /* 0x30 */ 1610 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1611 uint8_t LUN[8]; /* 0x34 */ 1612 uint32_t Control; /* 0x3C */ 1613 mpi2_scsi_io_cdb_union CDB; /* 0x40 */ 1614 mpi2_scsi_io_vendor_unique RaidContext; /* 0x60 */ 1615 mpi2_sge_io_union SGL; /* 0x80 */ 1616 } __packed; 1617 1618 /* 1619 * MPT RAID MFA IO Descriptor. 1620 */ 1621 typedef struct _mfi_raid_mfa_io_descriptor { 1622 uint32_t RequestFlags : 8; 1623 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1624 uint32_t MessageAddress2; /* bits 61:32 */ 1625 } mfi_raid_mfa_io_request_descriptor; 1626 1627 struct mfi_mpi2_request_header { 1628 uint8_t RequestFlags; /* 0x00 */ 1629 uint8_t MSIxIndex; /* 0x01 */ 1630 uint16_t SMID; /* 0x02 */ 1631 uint16_t LMID; /* 0x04 */ 1632 }; 1633 1634 /* defines for the RequestFlags field */ 1635 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1636 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1637 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1638 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1639 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1640 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1641 1642 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1643 1644 struct mfi_mpi2_request_high_priority { 1645 struct mfi_mpi2_request_header header; 1646 uint16_t reserved; 1647 }; 1648 1649 struct mfi_mpi2_request_scsi_io { 1650 struct mfi_mpi2_request_header header; 1651 uint16_t scsi_io_dev_handle; 1652 }; 1653 1654 struct mfi_mpi2_request_scsi_target { 1655 struct mfi_mpi2_request_header header; 1656 uint16_t scsi_target_io_index; 1657 }; 1658 1659 /* Request Descriptors */ 1660 union mfi_mpi2_request_descriptor { 1661 struct mfi_mpi2_request_header header; 1662 struct mfi_mpi2_request_high_priority high_priority; 1663 struct mfi_mpi2_request_scsi_io scsi_io; 1664 struct mfi_mpi2_request_scsi_target scsi_target; 1665 uint64_t words; 1666 }; 1667 1668 /* 1669 * Request descriptor types 1670 */ 1671 #define MFI_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1672 #define MFI_REQ_DESCRIPT_FLAGS_MFA 0x1 1673 #define MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 0x1 1674 1675 #define MFI_FUSION_FP_DEFAULT_TIMEOUT 0x14 1676 1677 struct mfi_mpi2_reply_header { 1678 uint8_t ReplyFlags; /* 0x00 */ 1679 uint8_t MSIxIndex; /* 0x01 */ 1680 uint16_t SMID; /* 0x02 */ 1681 }; 1682 1683 /* defines for the ReplyFlags field */ 1684 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1685 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1686 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1687 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1688 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1689 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1690 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1691 1692 /* values for marking a reply descriptor as unused */ 1693 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1694 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1695 1696 struct mfi_mpi2_reply_default { 1697 struct mfi_mpi2_reply_header header; 1698 uint32_t DescriptorTypeDependent2; 1699 }; 1700 1701 struct mfi_mpi2_reply_address { 1702 struct mfi_mpi2_reply_header header; 1703 uint32_t ReplyFrameAddress; 1704 }; 1705 1706 struct mfi_mpi2_reply_scsi_io { 1707 struct mfi_mpi2_reply_header header; 1708 uint16_t TaskTag; /* 0x04 */ 1709 uint16_t Reserved1; /* 0x06 */ 1710 }; 1711 1712 struct mfi_mpi2_reply_target_assist { 1713 struct mfi_mpi2_reply_header header; 1714 uint8_t SequenceNumber; /* 0x04 */ 1715 uint8_t Reserved1; /* 0x04 */ 1716 uint16_t IoIndex; /* 0x06 */ 1717 }; 1718 1719 struct mfi_mpi2_reply_target_cmd_buffer { 1720 struct mfi_mpi2_reply_header header; 1721 uint8_t SequenceNumber; /* 0x04 */ 1722 uint8_t Flags; /* 0x04 */ 1723 uint16_t InitiatorDevHandle; /* 0x06 */ 1724 uint16_t IoIndex; /* 0x06 */ 1725 }; 1726 1727 struct mfi_mpi2_reply_raid_accel { 1728 struct mfi_mpi2_reply_header header; 1729 uint8_t SequenceNumber; /* 0x04 */ 1730 uint32_t Reserved; /* 0x04 */ 1731 }; 1732 1733 /* union of Reply Descriptors */ 1734 union mfi_mpi2_reply_descriptor { 1735 struct mfi_mpi2_reply_header header; 1736 struct mfi_mpi2_reply_scsi_io scsi_io; 1737 struct mfi_mpi2_reply_target_assist target_assist; 1738 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1739 struct mfi_mpi2_reply_raid_accel raid_accel; 1740 struct mfi_mpi2_reply_default reply_default; 1741 uint64_t words; 1742 }; 1743 1744 struct io_request_info { 1745 uint64_t ldStartBlock; 1746 uint32_t numBlocks; 1747 uint16_t ldTgtId; 1748 uint8_t isRead; 1749 uint16_t devHandle; 1750 uint64_t pdBlock; 1751 uint8_t fpOkForIo; 1752 }; 1753 1754 /* 1755 * Define MFI Address Context union. 1756 */ 1757 #ifdef MFI_ADDRESS_IS_uint64_t 1758 typedef uint64_t mfi_address; 1759 #else 1760 typedef union _mfi_address { 1761 struct { 1762 uint32_t addressLow; 1763 uint32_t addressHigh; 1764 } u; 1765 uint64_t address; 1766 } mfi_address; 1767 #endif 1768 1769 #define MEGASAS_MAX_NAME 32 1770 #define MEGASAS_VERSION "4.23" 1771 1772 #endif /* _DEV_IC_MFIREG_H_ */ 1773
Indexes created Mon Oct 20 11:09:49 GMT 2025