mlxreg.h revision 1.1
1 /* $NetBSD: mlxreg.h,v 1.1 2001/02/04 17:05:12 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Michael Smith 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * from FreeBSD: mlxreg.h,v 1.5.2.2 2000/04/24 19:40:50 msmith Exp 65 */ 66 67 #ifndef _IC_MLXREG_H_ 68 #define _IC_MLXREG_H_ 69 70 #define MLX_SECTOR_SIZE 512 71 72 /* 73 * Selected command codes. 74 */ 75 #define MLX_CMD_ENQUIRY_OLD 0x05 76 #define MLX_CMD_ENQUIRY 0x53 77 #define MLX_CMD_ENQUIRY2 0x1c 78 #define MLX_CMD_ENQSYSDRIVE 0x19 79 #define MLX_CMD_READSG 0xb6 80 #define MLX_CMD_WRITESG 0xb7 81 #define MLX_CMD_READSG_OLD 0x82 82 #define MLX_CMD_WRITESG_OLD 0x83 83 #define MLX_CMD_FLUSH 0x0a 84 #define MLX_CMD_LOGOP 0x72 85 #define MLX_CMD_REBUILDASYNC 0x16 86 #define MLX_CMD_CHECKASYNC 0x1e 87 #define MLX_CMD_REBUILDSTAT 0x0c 88 #define MLX_CMD_STOPCHANNEL 0x13 89 #define MLX_CMD_STARTCHANNEL 0x12 90 #define MLX_CMD_READ_CONFIG 0x4e 91 #define MLX_CMD_WRITE_CONFIG 0x4f 92 #define MLX_CMD_READ_DK_CONFIG 0x4a 93 #define MLX_CMD_WRITE_DK_CONFIG 0x4b 94 #define MLX_CMD_DIRECT_CDB 0x04 95 #define MLX_CMD_DEVICE_STATE 0x50 96 #define MLX_CMD_READ_CONFIG2 0x3d 97 #define MLX_CMD_WRITE_CONFIG2 0x3c 98 99 #ifdef _KERNEL 100 101 /* 102 * Status values. 103 */ 104 #define MLX_STATUS_OK 0x0000 105 #define MLX_STATUS_RDWROFFLINE 0x0002 /* read/write claims drive is offline */ 106 #define MLX_STATUS_WEDGED 0xdeaf /* controller not listening */ 107 #define MLX_STATUS_LOST 0xdead /* never came back */ 108 #define MLX_STATUS_BUSY 0xdeed /* command is in controller */ 109 110 /* 111 * V1 (EISA) interface. 112 */ 113 #define MLX_V1REG_IE 0x09 114 #define MLX_V1REG_IDB 0x0d 115 #define MLX_V1REG_ODB_EN 0x0e 116 #define MLX_V1REG_ODB 0x0f 117 #define MLX_V1REG_MAILBOX 0x10 118 119 #define MLX_V1_IDB_FULL 0x01 /* mailbox is full */ 120 #define MLX_V1_IDB_INIT_BUSY 0x02 /* init in progress */ 121 122 #define MLX_V1_IDB_SACK 0x02 /* acknowledge status read */ 123 124 #define MLX_V1_ODB_SAVAIL 0x01 /* status is available */ 125 126 #define MLX_V1_FWERROR_PEND 0x04 /* firmware error pending */ 127 128 #define MLX_V1_MAILBOX_LEN 13 129 130 /* 131 * V2/V3 interface. 132 */ 133 #define MLX_V3REG_MAILBOX 0x00 134 #define MLX_V3REG_STATUS_IDENT 0x0d 135 #define MLX_V3REG_STATUS 0x0e 136 #define MLX_V3REG_IDB 0x40 137 #define MLX_V3REG_ODB 0x41 138 #define MLX_V3REG_IE 0x43 139 #define MLX_V3REG_FWERROR 0x3f 140 #define MLX_V3REG_FWERROR_PARAM1 0x00 141 #define MLX_V3REG_FWERROR_PARAM2 0x01 142 143 #define MLX_V3_IDB_FULL 0x01 /* mailbox is full */ 144 #define MLX_V3_IDB_INIT_BUSY 0x02 /* init in progress */ 145 146 #define MLX_V3_IDB_SACK 0x02 /* acknowledge status read */ 147 148 #define MLX_V3_ODB_SAVAIL 0x01 /* status is available */ 149 150 #define MLX_V3_FWERROR_PEND 0x04 /* firmware error pending */ 151 152 #define MLX_V3_MAILBOX_LEN 13 153 154 /* 155 * V4 interface. 156 */ 157 #define MLX_V4REG_MAILBOX 0x1000 158 #define MLX_V4REG_STATUS_IDENT 0x1018 159 #define MLX_V4REG_STATUS 0x101a 160 #define MLX_V4REG_IDB 0x0020 161 #define MLX_V4REG_ODB 0x002c 162 #define MLX_V4REG_IE 0x0034 163 #define MLX_V4REG_FWERROR 0x103f 164 #define MLX_V4REG_FWERROR_PARAM1 0x1000 165 #define MLX_V4REG_FWERROR_PARAM2 0x1001 166 167 #define MLX_V4_IDB_FULL 0x01 /* mailbox is full */ 168 #define MLX_V4_IDB_INIT_BUSY 0x02 /* initialisation in progress */ 169 170 #define MLX_V4_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */ 171 #define MLX_V4_IDB_SACK 0x02 /* acknowledge status read */ 172 #define MLX_V4_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */ 173 174 #define MLX_V4_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */ 175 #define MLX_V4_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */ 176 177 #define MLX_V4_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */ 178 #define MLX_V4_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */ 179 180 #define MLX_V4_IE_MASK 0xfb /* message unit interrupt mask */ 181 #define MLX_V4_IE_DISINT 0x04 /* interrupt disable bit */ 182 183 #define MLX_V4_FWERROR_PEND 0x04 /* firmware error pending */ 184 185 #define MLX_V4_MAILBOX_LEN 16 186 187 /* 188 * V5 interface. 189 */ 190 #define MLX_V5REG_MAILBOX 0x50 191 #define MLX_V5REG_STATUS_IDENT 0x5d 192 #define MLX_V5REG_STATUS 0x5e 193 #define MLX_V5REG_IDB 0x60 194 #define MLX_V5REG_ODB 0x61 195 #define MLX_V5REG_IE 0x34 196 #define MLX_V5REG_FWERROR 0x63 197 #define MLX_V5REG_FWERROR_PARAM1 0x50 198 #define MLX_V5REG_FWERROR_PARAM2 0x51 199 200 #define MLX_V5_IDB_EMPTY 0x01 /* mailbox is empty */ 201 #define MLX_V5_IDB_INIT_DONE 0x02 /* initialisation has completed */ 202 203 #define MLX_V5_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */ 204 #define MLX_V5_IDB_SACK 0x02 /* acknowledge status read */ 205 #define MLX_V5_IDB_RESET 0x08 /* reset request */ 206 #define MLX_V5_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */ 207 208 #define MLX_V5_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */ 209 #define MLX_V5_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */ 210 211 #define MLX_V5_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */ 212 #define MLX_V5_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */ 213 214 #define MLX_V5_IE_DISINT 0x04 /* interrupt disable bit */ 215 216 #define MLX_V5_FWERROR_PEND 0x04 /* firmware error pending */ 217 218 #define MLX_V5_MAILBOX_LEN 16 219 220 #endif /* _KERNEL */ 221 222 /* 223 * Scatter-gather list format, type 1, kind 00. 224 */ 225 struct mlx_sgentry { 226 u_int32_t sge_addr; 227 u_int32_t sge_count; 228 } __attribute__ ((packed)); 229 230 /* 231 * Command result buffers, as placed in system memory by the controller. 232 */ 233 struct mlx_enquiry_old { 234 u_int8_t me_num_sys_drvs; 235 u_int8_t me_res1[3]; 236 u_int32_t me_drvsize[8]; 237 u_int16_t me_flash_age; 238 u_int8_t me_status_flags; 239 u_int8_t me_free_state_change_count; 240 u_int8_t me_fwminor; 241 u_int8_t me_fwmajor; 242 u_int8_t me_rebuild_flag; 243 u_int8_t me_max_commands; 244 u_int8_t me_offline_sd_count; 245 u_int8_t me_res3; 246 u_int8_t me_critical_sd_count; 247 u_int8_t me_res4[3]; 248 u_int8_t me_dead_count; 249 u_int8_t me_res5; 250 u_int8_t me_rebuild_count; 251 u_int8_t me_misc_flags; 252 struct { 253 u_int8_t dd_targ; 254 u_int8_t dd_chan; 255 } __attribute__ ((packed)) me_dead[20]; 256 } __attribute__ ((packed)); 257 258 struct mlx_enquiry { 259 u_int8_t me_num_sys_drvs; 260 u_int8_t me_res1[3]; 261 u_int32_t me_drvsize[32]; 262 u_int16_t me_flash_age; 263 u_int8_t me_status_flags; 264 #define MLX_ENQ_SFLAG_DEFWRERR 0x01 /* deferred write error indicator */ 265 #define MLX_ENQ_SFLAG_BATTLOW 0x02 /* battery low */ 266 u_int8_t me_res2; 267 u_int8_t me_fwminor; 268 u_int8_t me_fwmajor; 269 u_int8_t me_rebuild_flag; 270 u_int8_t me_max_commands; 271 u_int8_t me_offline_sd_count; 272 u_int8_t me_res3; 273 u_int16_t me_event_log_seq_num; 274 u_int8_t me_critical_sd_count; 275 u_int8_t me_res4[3]; 276 u_int8_t me_dead_count; 277 u_int8_t me_res5; 278 u_int8_t me_rebuild_count; 279 u_int8_t me_misc_flags; 280 #define MLX_ENQ_MISC_BBU 0x08 /* battery backup present */ 281 struct { 282 u_int8_t dd_targ; 283 u_int8_t dd_chan; 284 } __attribute__ ((packed)) me_dead[20]; 285 } __attribute__ ((packed)); 286 287 struct mlx_enquiry2 { 288 u_int8_t me_hardware_id[4]; 289 u_int8_t me_firmware_id[4]; 290 u_int32_t me_res1; 291 u_int8_t me_configured_channels; 292 u_int8_t me_actual_channels; 293 u_int8_t me_max_targets; 294 u_int8_t me_max_tags; 295 u_int8_t me_max_sys_drives; 296 u_int8_t me_max_arms; 297 u_int8_t me_max_spans; 298 u_int8_t me_res2; 299 u_int32_t me_res3; 300 u_int32_t me_mem_size; 301 u_int32_t me_cache_size; 302 u_int32_t me_flash_size; 303 u_int32_t me_nvram_size; 304 u_int16_t me_mem_type; 305 u_int16_t me_clock_speed; 306 u_int16_t me_mem_speed; 307 u_int16_t me_hardware_speed; 308 u_int8_t me_res4[12]; 309 u_int16_t me_max_commands; 310 u_int16_t me_max_sg; 311 u_int16_t me_max_dp; 312 u_int16_t me_max_iod; 313 u_int16_t me_max_comb; 314 u_int8_t me_latency; 315 u_int8_t me_res5; 316 u_int8_t me_scsi_timeout; 317 u_int8_t me_res6; 318 u_int16_t me_min_freelines; 319 u_int8_t me_res7[8]; 320 u_int8_t me_rate_const; 321 u_int8_t me_res8[11]; 322 u_int16_t me_physblk; 323 u_int16_t me_logblk; 324 u_int16_t me_maxblk; 325 u_int16_t me_blocking_factor; 326 u_int16_t me_cacheline; 327 u_int8_t me_scsi_cap; 328 u_int8_t me_res9[5]; 329 u_int16_t me_firmware_build; 330 u_int8_t me_fault_mgmt_type; 331 u_int8_t me_res10; 332 u_int32_t me_firmware_features; 333 u_int8_t me_res11[8]; 334 } __attribute__ ((packed)); 335 336 /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these. */ 337 struct mlx_enq_sys_drive { 338 u_int32_t sd_size; 339 u_int8_t sd_state; 340 u_int8_t sd_raidlevel; 341 u_int16_t sd_res1; 342 } __attribute__ ((packed)); 343 344 /* 345 * MLX_CMD_LOGOP/MLX_LOGOP_GET 346 * 347 * Bitfields: 348 * 349 * 0-4 el_target SCSI target 350 * 5-7 el_target SCSI channel 351 * 0-6 el_errorcode error code 352 * 7-7 el_errorcode validity (?) 353 * 0-3 el_sense sense key 354 * 4-4 el_sense reserved 355 * 5-5 el_sense ILI 356 * 6-6 el_sense EOM 357 * 7-7 el_sense filemark 358 */ 359 struct mlx_eventlog_entry { 360 u_int8_t el_type; 361 u_int8_t el_length; 362 u_int8_t el_target; 363 u_int8_t el_lun; 364 u_int16_t el_seqno; 365 u_int8_t el_errorcode; 366 u_int8_t el_segment; 367 u_int8_t el_sense; 368 u_int8_t el_information[4]; 369 u_int8_t el_addsense; 370 u_int8_t el_csi[4]; 371 u_int8_t el_asc; 372 u_int8_t el_asq; 373 u_int8_t el_res3[12]; 374 } __attribute__ ((packed)); 375 376 #define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */ 377 #define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */ 378 379 struct mlx_rebuild_stat { 380 u_int32_t rb_drive; 381 u_int32_t rb_size; 382 u_int32_t rb_remaining; 383 } __attribute__ ((packed)); 384 385 struct mlx_config { 386 u_int16_t cf_flags1; 387 #define MLX_CF2_ACTV_NEG 0x0002 388 #define MLX_CF2_NORSTRTRY 0x0080 389 #define MLX_CF2_STRGWRK 0x0100 390 #define MLX_CF2_HPSUPP 0x0200 391 #define MLX_CF2_NODISCN 0x0400 392 #define MLX_CF2_ARM 0x2000 393 #define MLX_CF2_OFM 0x8000 394 #define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM) 395 u_int8_t cf_oemid; 396 u_int8_t cf_oem_model; 397 u_int8_t cf_physical_sector; 398 u_int8_t cf_logical_sector; 399 u_int8_t cf_blockfactor; 400 u_int8_t cf_flags2; 401 #define MLX_CF2_READAH 0x01 402 #define MLX_CF2_BIOSDLY 0x02 403 #define MLX_CF2_REASS1S 0x10 404 #define MLX_CF2_FUAENABL 0x40 405 #define MLX_CF2_R5ALLS 0x80 406 u_int8_t cf_rcrate; 407 u_int8_t cf_res1; 408 u_int8_t cf_blocks_per_cache_line; 409 u_int8_t cf_blocks_per_stripe; 410 u_int8_t cf_scsi_param_0; 411 u_int8_t cf_scsi_param_1; 412 u_int8_t cf_scsi_param_2; 413 u_int8_t cf_scsi_param_3; 414 u_int8_t cf_scsi_param_4; 415 u_int8_t cf_scsi_param_5; 416 u_int8_t cf_scsi_initiator_id; 417 u_int8_t cf_res2; 418 u_int8_t cf_startup_mode; 419 u_int8_t cf_simultaneous_spinup_devices; 420 u_int8_t cf_delay_between_spinups; 421 u_int8_t cf_res3; 422 u_int16_t cf_checksum; 423 } __attribute__ ((packed)); 424 425 struct mlx_config2 { 426 struct mlx_config cf2_cf; 427 u_int8_t cf2_reserved0[26]; 428 u_int8_t cf2_flags; 429 #define MLX_CF2_BIOS_DIS 0x01 430 #define MLX_CF2_CDROM_DIS 0x02 431 #define MLX_CF2_GEOM_255 0x20 432 u_int8_t cf2_reserved1[9]; 433 u_int16_t cf2_checksum; 434 } __attribute__ ((__packed__)); 435 436 struct mlx_sys_drv_span { 437 u_int32_t sp_start_lba; 438 u_int32_t sp_nblks; 439 u_int8_t sp_arm[8]; 440 } __attribute__ ((packed)); 441 442 struct mlx_sys_drv { 443 u_int8_t sd_status; 444 u_int8_t sd_ext_status; 445 u_int8_t sd_mod1; 446 u_int8_t sd_mod2; 447 u_int8_t sd_raidlevel; 448 #define MLX_SYS_DRV_WRITEBACK (1<<7) 449 #define MLX_SYS_DRV_RAID0 0 450 #define MLX_SYS_DRV_RAID1 1 451 #define MLX_SYS_DRV_RAID3 3 452 #define MLX_SYS_DRV_RAID5 5 453 #define MLX_SYS_DRV_RAID6 6 454 #define MLX_SYS_DRV_JBOD 7 455 u_int8_t sd_valid_arms; 456 u_int8_t sd_valid_spans; 457 u_int8_t sd_init_state; 458 #define MLX_SYS_DRV_INITTED 0x81; 459 struct mlx_sys_drv_span sd_span[4]; 460 } __attribute__ ((packed)); 461 462 struct mlx_phys_drv { 463 u_int8_t pd_flags1; 464 #define MLX_PHYS_DRV_PRESENT 0x01 465 u_int8_t pd_flags2; 466 #define MLX_PHYS_DRV_OTHER 0x00 467 #define MLX_PHYS_DRV_DISK 0x01 468 #define MLX_PHYS_DRV_SEQUENTIAL 0x02 469 #define MLX_PHYS_DRV_CDROM 0x03 470 #define MLX_PHYS_DRV_FAST20 0x08 471 #define MLX_PHYS_DRV_SYNC 0x10 472 #define MLX_PHYS_DRV_FAST 0x20 473 #define MLX_PHYS_DRV_WIDE 0x40 474 #define MLX_PHYS_DRV_TAG 0x80 475 u_int8_t pd_status; 476 #define MLX_PHYS_DRV_DEAD 0x00 477 #define MLX_PHYS_DRV_WRONLY 0x02 478 #define MLX_PHYS_DRV_ONLINE 0x03 479 #define MLX_PHYS_DRV_STANDBY 0x10 480 u_int8_t pd_res1; 481 u_int8_t pd_period; 482 u_int8_t pd_offset; 483 u_int32_t pd_config_size; 484 } __attribute__ ((packed)); 485 486 struct mlx_core_cfg { 487 u_int8_t cc_num_sys_drives; 488 u_int8_t cc_res1[3]; 489 struct mlx_sys_drv cc_sys_drives[32]; 490 struct mlx_phys_drv cc_phys_drives[5 * 16]; 491 } __attribute__ ((packed)); 492 493 /* 494 * Bitfields: 495 * 496 * 0-3 dcdb_target SCSI target 497 * 4-7 dcdb_target SCSI channel 498 * 0-3 dcdb_length CDB length 499 * 4-7 dcdb_length high 4 bits of `datasize' 500 */ 501 struct mlx_dcdb { 502 u_int8_t dcdb_target; 503 u_int8_t dcdb_flags; 504 #define MLX_DCDB_NO_DATA 0x00 505 #define MLX_DCDB_DATA_IN 0x01 506 #define MLX_DCDB_DATA_OUT 0x02 507 #define MLX_DCDB_EARLY_STATUS 0x04 508 #define MLX_DCDB_TIMEOUT_10S 0x10 /* This lot is wrong? [ad] */ 509 #define MLX_DCDB_TIMEOUT_60S 0x20 510 #define MLX_DCDB_TIMEOUT_20M 0x30 511 #define MLX_DCDB_TIMEOUT_24H 0x40 512 #define MLX_DCDB_NO_AUTO_SENSE 0x40 /* XXX ?? */ 513 #define MLX_DCDB_DISCONNECT 0x80 514 u_int16_t dcdb_datasize; 515 u_int32_t dcdb_physaddr; 516 u_int8_t dcdb_length; 517 u_int8_t dcdb_sense_length; 518 u_int8_t dcdb_cdb[12]; 519 u_int8_t dcdb_sense[64]; 520 u_int8_t dcdb_status; 521 u_int8_t res1; 522 } __attribute__ ((packed)); 523 524 struct mlx_bbtable_entry { 525 u_int32_t bbt_block_number; 526 u_int8_t bbt_extent; 527 u_int8_t bbt_res1; 528 u_int8_t bbt_entry_type; 529 u_int8_t bbt_system_drive; /* high 3 bits reserved */ 530 } __attribute__ ((packed)); 531 532 #endif /* !_IC_MLXREG_H_ */ 533
Indexes created Fri Sep 26 20:09:58 GMT 2025