mlxreg.h revision 1.3
1 /* $NetBSD: mlxreg.h,v 1.3 2001/07/26 12:38:03 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Michael Smith 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * from FreeBSD: mlxreg.h,v 1.5.2.2 2000/04/24 19:40:50 msmith Exp 65 */ 66 67 #ifndef _IC_MLXREG_H_ 68 #define _IC_MLXREG_H_ 69 70 #define MLX_SECTOR_SIZE 512 71 72 /* 73 * Selected command codes. 74 */ 75 #define MLX_CMD_ENQUIRY_OLD 0x05 76 #define MLX_CMD_ENQUIRY 0x53 77 #define MLX_CMD_ENQUIRY2 0x1c 78 #define MLX_CMD_ENQSYSDRIVE 0x19 79 #define MLX_CMD_READSG 0xb6 80 #define MLX_CMD_WRITESG 0xb7 81 #define MLX_CMD_READSG_OLD 0x82 82 #define MLX_CMD_WRITESG_OLD 0x83 83 #define MLX_CMD_FLUSH 0x0a 84 #define MLX_CMD_LOGOP 0x72 85 #define MLX_CMD_REBUILDASYNC 0x16 86 #define MLX_CMD_CHECKASYNC 0x1e 87 #define MLX_CMD_REBUILDSTAT 0x0c 88 #define MLX_CMD_STOPCHANNEL 0x13 89 #define MLX_CMD_STARTCHANNEL 0x12 90 #define MLX_CMD_READ_CONFIG 0x4e 91 #define MLX_CMD_WRITE_CONFIG 0x4f 92 #define MLX_CMD_READ_DK_CONFIG 0x4a 93 #define MLX_CMD_WRITE_DK_CONFIG 0x4b 94 #define MLX_CMD_DIRECT_CDB 0x04 95 #define MLX_CMD_DEVICE_STATE 0x50 96 #define MLX_CMD_READ_CONFIG2 0x3d 97 #define MLX_CMD_WRITE_CONFIG2 0x3c 98 99 #ifdef _KERNEL 100 101 /* 102 * Status values. 103 */ 104 #define MLX_STATUS_OK 0x0000 105 #define MLX_STATUS_RDWROFFLINE 0x0002 /* read/write claims drive is offline */ 106 #define MLX_STATUS_WEDGED 0xdeaf /* controller not listening */ 107 #define MLX_STATUS_LOST 0xdead /* never came back */ 108 #define MLX_STATUS_BUSY 0xbabe /* command is in controller */ 109 110 /* 111 * V1 (EISA) interface. 112 */ 113 #define MLX_V1REG_IE 0x09 114 #define MLX_V1REG_IDB 0x0d 115 #define MLX_V1REG_ODB_EN 0x0e 116 #define MLX_V1REG_ODB 0x0f 117 #define MLX_V1REG_MAILBOX 0x10 118 119 #define MLX_V1_IDB_FULL 0x01 /* mailbox is full */ 120 #define MLX_V1_IDB_INIT_BUSY 0x02 /* init in progress */ 121 122 #define MLX_V1_IDB_SACK 0x02 /* acknowledge status read */ 123 #define MLX_V1_IDB_RESET 0x10 /* reset controller */ 124 125 #define MLX_V1_ODB_SAVAIL 0x01 /* status is available */ 126 #define MLX_V1_ODB_RESET 0x02 /* reset controller */ 127 128 #define MLX_V1_FWERROR_PEND 0x04 /* firmware error pending */ 129 130 #define MLX_V1_MAILBOX_LEN 13 131 132 /* 133 * V2/V3 interface. 134 */ 135 #define MLX_V3REG_MAILBOX 0x00 136 #define MLX_V3REG_STATUS_IDENT 0x0d 137 #define MLX_V3REG_STATUS 0x0e 138 #define MLX_V3REG_IDB 0x40 139 #define MLX_V3REG_ODB 0x41 140 #define MLX_V3REG_IE 0x43 141 #define MLX_V3REG_FWERROR 0x3f 142 #define MLX_V3REG_FWERROR_PARAM1 0x00 143 #define MLX_V3REG_FWERROR_PARAM2 0x01 144 145 #define MLX_V3_IDB_FULL 0x01 /* mailbox is full */ 146 #define MLX_V3_IDB_INIT_BUSY 0x02 /* init in progress */ 147 148 #define MLX_V3_IDB_SACK 0x02 /* acknowledge status read */ 149 #define MLX_V3_IDB_RESET 0x08 /* reset controller */ 150 151 #define MLX_V3_ODB_SAVAIL 0x01 /* status is available */ 152 153 #define MLX_V3_FWERROR_PEND 0x04 /* firmware error pending */ 154 155 #define MLX_V3_MAILBOX_LEN 13 156 157 /* 158 * V4 interface. 159 */ 160 #define MLX_V4REG_MAILBOX 0x1000 161 #define MLX_V4REG_STATUS_IDENT 0x1018 162 #define MLX_V4REG_STATUS 0x101a 163 #define MLX_V4REG_IDB 0x0020 164 #define MLX_V4REG_ODB 0x002c 165 #define MLX_V4REG_IE 0x0034 166 #define MLX_V4REG_FWERROR 0x103f 167 #define MLX_V4REG_FWERROR_PARAM1 0x1000 168 #define MLX_V4REG_FWERROR_PARAM2 0x1001 169 170 #define MLX_V4_IDB_FULL 0x01 /* mailbox is full */ 171 #define MLX_V4_IDB_INIT_BUSY 0x02 /* initialisation in progress */ 172 173 #define MLX_V4_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */ 174 #define MLX_V4_IDB_SACK 0x02 /* acknowledge status read */ 175 #define MLX_V4_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */ 176 177 #define MLX_V4_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */ 178 #define MLX_V4_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */ 179 180 #define MLX_V4_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */ 181 #define MLX_V4_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */ 182 183 #define MLX_V4_IE_MASK 0xfb /* message unit interrupt mask */ 184 #define MLX_V4_IE_DISINT 0x04 /* interrupt disable bit */ 185 186 #define MLX_V4_FWERROR_PEND 0x04 /* firmware error pending */ 187 188 #define MLX_V4_MAILBOX_LEN 16 189 190 /* 191 * V5 interface. 192 */ 193 #define MLX_V5REG_MAILBOX 0x50 194 #define MLX_V5REG_STATUS_IDENT 0x5d 195 #define MLX_V5REG_STATUS 0x5e 196 #define MLX_V5REG_IDB 0x60 197 #define MLX_V5REG_ODB 0x61 198 #define MLX_V5REG_IE 0x34 199 #define MLX_V5REG_FWERROR 0x63 200 #define MLX_V5REG_FWERROR_PARAM1 0x50 201 #define MLX_V5REG_FWERROR_PARAM2 0x51 202 203 #define MLX_V5_IDB_EMPTY 0x01 /* mailbox is empty */ 204 #define MLX_V5_IDB_INIT_DONE 0x02 /* initialisation has completed */ 205 206 #define MLX_V5_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */ 207 #define MLX_V5_IDB_SACK 0x02 /* acknowledge status read */ 208 #define MLX_V5_IDB_RESET 0x08 /* reset request */ 209 #define MLX_V5_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */ 210 211 #define MLX_V5_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */ 212 #define MLX_V5_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */ 213 214 #define MLX_V5_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */ 215 #define MLX_V5_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */ 216 217 #define MLX_V5_IE_DISINT 0x04 /* interrupt disable bit */ 218 219 #define MLX_V5_FWERROR_PEND 0x04 /* firmware error pending */ 220 221 #define MLX_V5_MAILBOX_LEN 16 222 223 #endif /* _KERNEL */ 224 225 /* 226 * Scatter-gather list format, type 1, kind 00. 227 */ 228 struct mlx_sgentry { 229 u_int32_t sge_addr; 230 u_int32_t sge_count; 231 } __attribute__ ((packed)); 232 233 /* 234 * Command result buffers, as placed in system memory by the controller. 235 */ 236 struct mlx_enquiry_old { 237 u_int8_t me_num_sys_drvs; 238 u_int8_t me_res1[3]; 239 u_int32_t me_drvsize[8]; 240 u_int16_t me_flash_age; 241 u_int8_t me_status_flags; 242 u_int8_t me_free_state_change_count; 243 u_int8_t me_fwminor; 244 u_int8_t me_fwmajor; 245 u_int8_t me_rebuild_flag; 246 u_int8_t me_max_commands; 247 u_int8_t me_offline_sd_count; 248 u_int8_t me_res3; 249 u_int8_t me_critical_sd_count; 250 u_int8_t me_res4[3]; 251 u_int8_t me_dead_count; 252 u_int8_t me_res5; 253 u_int8_t me_rebuild_count; 254 u_int8_t me_misc_flags; 255 struct { 256 u_int8_t dd_targ; 257 u_int8_t dd_chan; 258 } __attribute__ ((packed)) me_dead[20]; 259 } __attribute__ ((packed)); 260 261 struct mlx_enquiry { 262 u_int8_t me_num_sys_drvs; 263 u_int8_t me_res1[3]; 264 u_int32_t me_drvsize[32]; 265 u_int16_t me_flash_age; 266 u_int8_t me_status_flags; 267 #define MLX_ENQ_SFLAG_DEFWRERR 0x01 /* deferred write error indicator */ 268 #define MLX_ENQ_SFLAG_BATTLOW 0x02 /* battery low */ 269 u_int8_t me_res2; 270 u_int8_t me_fwminor; 271 u_int8_t me_fwmajor; 272 u_int8_t me_rebuild_flag; 273 u_int8_t me_max_commands; 274 u_int8_t me_offline_sd_count; 275 u_int8_t me_res3; 276 u_int16_t me_event_log_seq_num; 277 u_int8_t me_critical_sd_count; 278 u_int8_t me_res4[3]; 279 u_int8_t me_dead_count; 280 u_int8_t me_res5; 281 u_int8_t me_rebuild_count; 282 u_int8_t me_misc_flags; 283 #define MLX_ENQ_MISC_BBU 0x08 /* battery backup present */ 284 struct { 285 u_int8_t dd_targ; 286 u_int8_t dd_chan; 287 } __attribute__ ((packed)) me_dead[20]; 288 } __attribute__ ((packed)); 289 290 struct mlx_enquiry2 { 291 u_int8_t me_hardware_id[4]; 292 u_int8_t me_firmware_id[4]; 293 u_int32_t me_res1; 294 u_int8_t me_configured_channels; 295 u_int8_t me_actual_channels; 296 u_int8_t me_max_targets; 297 u_int8_t me_max_tags; 298 u_int8_t me_max_sys_drives; 299 u_int8_t me_max_arms; 300 u_int8_t me_max_spans; 301 u_int8_t me_res2; 302 u_int32_t me_res3; 303 u_int32_t me_mem_size; 304 u_int32_t me_cache_size; 305 u_int32_t me_flash_size; 306 u_int32_t me_nvram_size; 307 u_int16_t me_mem_type; 308 u_int16_t me_clock_speed; 309 u_int16_t me_mem_speed; 310 u_int16_t me_hardware_speed; 311 u_int8_t me_res4[12]; 312 u_int16_t me_max_commands; 313 u_int16_t me_max_sg; 314 u_int16_t me_max_dp; 315 u_int16_t me_max_iod; 316 u_int16_t me_max_comb; 317 u_int8_t me_latency; 318 u_int8_t me_res5; 319 u_int8_t me_scsi_timeout; 320 u_int8_t me_res6; 321 u_int16_t me_min_freelines; 322 u_int8_t me_res7[8]; 323 u_int8_t me_rate_const; 324 u_int8_t me_res8[11]; 325 u_int16_t me_physblk; 326 u_int16_t me_logblk; 327 u_int16_t me_maxblk; 328 u_int16_t me_blocking_factor; 329 u_int16_t me_cacheline; 330 u_int8_t me_scsi_cap; 331 u_int8_t me_res9[5]; 332 u_int16_t me_firmware_build; 333 u_int8_t me_fault_mgmt_type; 334 u_int8_t me_res10; 335 u_int32_t me_firmware_features; 336 u_int8_t me_res11[8]; 337 } __attribute__ ((packed)); 338 339 /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these. */ 340 struct mlx_enq_sys_drive { 341 u_int32_t sd_size; 342 u_int8_t sd_state; 343 u_int8_t sd_raidlevel; 344 u_int16_t sd_res1; 345 } __attribute__ ((packed)); 346 347 /* 348 * MLX_CMD_LOGOP/MLX_LOGOP_GET 349 * 350 * Bitfields: 351 * 352 * 0-4 el_target SCSI target 353 * 5-7 el_target SCSI channel 354 * 0-6 el_errorcode error code 355 * 7-7 el_errorcode validity (?) 356 * 0-3 el_sense sense key 357 * 4-4 el_sense reserved 358 * 5-5 el_sense ILI 359 * 6-6 el_sense EOM 360 * 7-7 el_sense filemark 361 */ 362 struct mlx_eventlog_entry { 363 u_int8_t el_type; 364 u_int8_t el_length; 365 u_int8_t el_target; 366 u_int8_t el_lun; 367 u_int16_t el_seqno; 368 u_int8_t el_errorcode; 369 u_int8_t el_segment; 370 u_int8_t el_sense; 371 u_int8_t el_information[4]; 372 u_int8_t el_addsense; 373 u_int8_t el_csi[4]; 374 u_int8_t el_asc; 375 u_int8_t el_asq; 376 u_int8_t el_res3[12]; 377 } __attribute__ ((packed)); 378 379 #define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */ 380 #define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */ 381 382 struct mlx_rebuild_stat { 383 u_int32_t rb_drive; 384 u_int32_t rb_size; 385 u_int32_t rb_remaining; 386 } __attribute__ ((packed)); 387 388 struct mlx_config { 389 u_int16_t cf_flags1; 390 #define MLX_CF2_ACTV_NEG 0x0002 391 #define MLX_CF2_NORSTRTRY 0x0080 392 #define MLX_CF2_STRGWRK 0x0100 393 #define MLX_CF2_HPSUPP 0x0200 394 #define MLX_CF2_NODISCN 0x0400 395 #define MLX_CF2_ARM 0x2000 396 #define MLX_CF2_OFM 0x8000 397 #define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM) 398 u_int8_t cf_oemid; 399 u_int8_t cf_oem_model; 400 u_int8_t cf_physical_sector; 401 u_int8_t cf_logical_sector; 402 u_int8_t cf_blockfactor; 403 u_int8_t cf_flags2; 404 #define MLX_CF2_READAH 0x01 405 #define MLX_CF2_BIOSDLY 0x02 406 #define MLX_CF2_REASS1S 0x10 407 #define MLX_CF2_FUAENABL 0x40 408 #define MLX_CF2_R5ALLS 0x80 409 u_int8_t cf_rcrate; 410 u_int8_t cf_res1; 411 u_int8_t cf_blocks_per_cache_line; 412 u_int8_t cf_blocks_per_stripe; 413 u_int8_t cf_scsi_param_0; 414 u_int8_t cf_scsi_param_1; 415 u_int8_t cf_scsi_param_2; 416 u_int8_t cf_scsi_param_3; 417 u_int8_t cf_scsi_param_4; 418 u_int8_t cf_scsi_param_5; 419 u_int8_t cf_scsi_initiator_id; 420 u_int8_t cf_res2; 421 u_int8_t cf_startup_mode; 422 u_int8_t cf_simultaneous_spinup_devices; 423 u_int8_t cf_delay_between_spinups; 424 u_int8_t cf_res3; 425 u_int16_t cf_checksum; 426 } __attribute__ ((packed)); 427 428 struct mlx_config2 { 429 struct mlx_config cf2_cf; 430 u_int8_t cf2_reserved0[26]; 431 u_int8_t cf2_flags; 432 #define MLX_CF2_BIOS_DIS 0x01 433 #define MLX_CF2_CDROM_DIS 0x02 434 #define MLX_CF2_GEOM_255 0x20 435 u_int8_t cf2_reserved1[9]; 436 u_int16_t cf2_checksum; 437 } __attribute__ ((__packed__)); 438 439 struct mlx_sys_drv_span { 440 u_int32_t sp_start_lba; 441 u_int32_t sp_nblks; 442 u_int8_t sp_arm[8]; 443 } __attribute__ ((packed)); 444 445 struct mlx_sys_drv { 446 u_int8_t sd_status; 447 u_int8_t sd_ext_status; 448 u_int8_t sd_mod1; 449 u_int8_t sd_mod2; 450 u_int8_t sd_raidlevel; 451 #define MLX_SYS_DRV_WRITEBACK (1<<7) 452 #define MLX_SYS_DRV_RAID0 0 453 #define MLX_SYS_DRV_RAID1 1 454 #define MLX_SYS_DRV_RAID3 3 455 #define MLX_SYS_DRV_RAID5 5 456 #define MLX_SYS_DRV_RAID6 6 457 #define MLX_SYS_DRV_JBOD 7 458 u_int8_t sd_valid_arms; 459 u_int8_t sd_valid_spans; 460 u_int8_t sd_init_state; 461 #define MLX_SYS_DRV_INITTED 0x81; 462 struct mlx_sys_drv_span sd_span[4]; 463 } __attribute__ ((packed)); 464 465 struct mlx_phys_drv { 466 u_int8_t pd_flags1; 467 #define MLX_PHYS_DRV_PRESENT 0x01 468 u_int8_t pd_flags2; 469 #define MLX_PHYS_DRV_OTHER 0x00 470 #define MLX_PHYS_DRV_DISK 0x01 471 #define MLX_PHYS_DRV_SEQUENTIAL 0x02 472 #define MLX_PHYS_DRV_CDROM 0x03 473 #define MLX_PHYS_DRV_FAST20 0x08 474 #define MLX_PHYS_DRV_SYNC 0x10 475 #define MLX_PHYS_DRV_FAST 0x20 476 #define MLX_PHYS_DRV_WIDE 0x40 477 #define MLX_PHYS_DRV_TAG 0x80 478 u_int8_t pd_status; 479 #define MLX_PHYS_DRV_DEAD 0x00 480 #define MLX_PHYS_DRV_WRONLY 0x02 481 #define MLX_PHYS_DRV_ONLINE 0x03 482 #define MLX_PHYS_DRV_STANDBY 0x10 483 u_int8_t pd_res1; 484 u_int8_t pd_period; 485 u_int8_t pd_offset; 486 u_int32_t pd_config_size; 487 } __attribute__ ((packed)); 488 489 struct mlx_core_cfg { 490 u_int8_t cc_num_sys_drives; 491 u_int8_t cc_res1[3]; 492 struct mlx_sys_drv cc_sys_drives[32]; 493 struct mlx_phys_drv cc_phys_drives[5 * 16]; 494 } __attribute__ ((packed)); 495 496 /* 497 * Bitfields: 498 * 499 * 0-3 dcdb_target SCSI target 500 * 4-7 dcdb_target SCSI channel 501 * 0-3 dcdb_length CDB length 502 * 4-7 dcdb_length high 4 bits of `datasize' 503 */ 504 struct mlx_dcdb { 505 u_int8_t dcdb_target; 506 u_int8_t dcdb_flags; 507 #define MLX_DCDB_NO_DATA 0x00 508 #define MLX_DCDB_DATA_IN 0x01 509 #define MLX_DCDB_DATA_OUT 0x02 510 #define MLX_DCDB_EARLY_STATUS 0x04 511 #define MLX_DCDB_TIMEOUT_10S 0x10 /* This lot is wrong? [ad] */ 512 #define MLX_DCDB_TIMEOUT_60S 0x20 513 #define MLX_DCDB_TIMEOUT_20M 0x30 514 #define MLX_DCDB_TIMEOUT_24H 0x40 515 #define MLX_DCDB_NO_AUTO_SENSE 0x40 /* XXX ?? */ 516 #define MLX_DCDB_DISCONNECT 0x80 517 u_int16_t dcdb_datasize; 518 u_int32_t dcdb_physaddr; 519 u_int8_t dcdb_length; 520 u_int8_t dcdb_sense_length; 521 u_int8_t dcdb_cdb[12]; 522 u_int8_t dcdb_sense[64]; 523 u_int8_t dcdb_status; 524 u_int8_t res1; 525 } __attribute__ ((packed)); 526 527 struct mlx_bbtable_entry { 528 u_int32_t bbt_block_number; 529 u_int8_t bbt_extent; 530 u_int8_t bbt_res1; 531 u_int8_t bbt_entry_type; 532 u_int8_t bbt_system_drive; /* high 3 bits reserved */ 533 } __attribute__ ((packed)); 534 535 #endif /* !_IC_MLXREG_H_ */ 536
Indexes created Fri Sep 26 08:10:20 GMT 2025