mpt_mpilib.h revision 1.1
1 /* $NetBSD: mpt_mpilib.h,v 1.1 2003/04/16 22:03:00 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 by LSI Logic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice immediately at the beginning of the file, without modification, 11 * this list of conditions, and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * 28 * Name: MPI_TYPE.H 29 * Title: MPI Basic type definitions 30 * Creation Date: June 6, 2000 31 * 32 * MPI Version: 01.02.01 33 * 34 * Version History 35 * --------------- 36 * 37 * Date Version Description 38 * -------- -------- ------------------------------------------------------ 39 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 40 * 06-06-00 01.00.01 Update version number for 1.0 release. 41 * 11-02-00 01.01.01 Original release for post 1.0 work 42 * 02-20-01 01.01.02 Added define and ifdef for MPI_POINTER. 43 * 08-08-01 01.02.01 Original release for v1.2 work. 44 * -------------------------------------------------------------------------- 45 */ 46 47 #ifndef MPI_TYPE_H 48 #define MPI_TYPE_H 49 50 51 /******************************************************************************* 52 * Define MPI_POINTER if it hasn't already been defined. By default MPI_POINTER 53 * is defined to be a near pointer. MPI_POINTER can be defined as a far pointer 54 * by defining MPI_POINTER as "far *" before this header file is included. 55 */ 56 #ifndef MPI_POINTER 57 #define MPI_POINTER * 58 #endif 59 60 61 /***************************************************************************** 62 * 63 * B a s i c T y p e s 64 * 65 *****************************************************************************/ 66 67 typedef signed char S8; 68 typedef unsigned char U8; 69 typedef signed short S16; 70 typedef unsigned short U16; 71 72 #if defined(unix) || defined(__arm) || defined(ALPHA) || defined(__GNUC__) 73 74 typedef signed int S32; 75 typedef unsigned int U32; 76 77 #else 78 79 typedef signed long S32; 80 typedef unsigned long U32; 81 82 #endif 83 84 85 typedef struct _S64 86 { 87 U32 Low; 88 S32 High; 89 } S64; 90 91 typedef struct _U64 92 { 93 U32 Low; 94 U32 High; 95 } U64; 96 97 98 /****************************************************************************/ 99 /* Pointers */ 100 /****************************************************************************/ 101 102 typedef S8 *PS8; 103 typedef U8 *PU8; 104 typedef S16 *PS16; 105 typedef U16 *PU16; 106 typedef S32 *PS32; 107 typedef U32 *PU32; 108 typedef S64 *PS64; 109 typedef U64 *PU64; 110 111 112 #endif 113 114 115 /* 116 * Copyright (c) 2000, 2001 by LSI Logic Corporation 117 * 118 * Redistribution and use in source and binary forms, with or without 119 * modification, are permitted provided that the following conditions 120 * are met: 121 * 1. Redistributions of source code must retain the above copyright 122 * notice immediately at the beginning of the file, without modification, 123 * this list of conditions, and the following disclaimer. 124 * 2. The name of the author may not be used to endorse or promote products 125 * derived from this software without specific prior written permission. 126 * 127 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 128 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 129 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 130 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 131 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 132 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 133 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 134 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 135 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 136 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 137 * SUCH DAMAGE. 138 * 139 * 140 * Name: MPI.H 141 * Title: MPI Message independent structures and definitions 142 * Creation Date: July 27, 2000 143 * 144 * MPI Version: 01.02.03 145 * 146 * Version History 147 * --------------- 148 * 149 * Date Version Description 150 * -------- -------- ------------------------------------------------------ 151 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 152 * 05-24-00 00.10.02 Added MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH definition. 153 * 06-06-00 01.00.01 Update MPI_VERSION_MAJOR and MPI_VERSION_MINOR. 154 * 06-22-00 01.00.02 Added MPI_IOCSTATUS_LAN_ definitions. 155 * Removed LAN_SUSPEND function definition. 156 * Added MPI_MSGFLAGS_CONTINUATION_REPLY definition. 157 * 06-30-00 01.00.03 Added MPI_CONTEXT_REPLY_TYPE_LAN definition. 158 * Added MPI_GET/SET_CONTEXT_REPLY_TYPE macros. 159 * 07-27-00 01.00.04 Added MPI_FAULT_ definitions. 160 * Removed MPI_IOCSTATUS_MSG/DATA_XFER_ERROR definitions. 161 * Added MPI_IOCSTATUS_INTERNAL_ERROR definition. 162 * Added MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH. 163 * 11-02-00 01.01.01 Original release for post 1.0 work. 164 * 12-04-00 01.01.02 Added new function codes. 165 * 01-09-01 01.01.03 Added more definitions to the system interface section 166 * Added MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT. 167 * 01-25-01 01.01.04 Changed MPI_VERSION_MINOR from 0x00 to 0x01. 168 * 02-20-01 01.01.05 Started using MPI_POINTER. 169 * Fixed value for MPI_DIAG_RW_ENABLE. 170 * Added defines for MPI_DIAG_PREVENT_IOC_BOOT and 171 * MPI_DIAG_CLEAR_FLASH_BAD_SIG. 172 * Obsoleted MPI_IOCSTATUS_TARGET_FC_ defines. 173 * 02-27-01 01.01.06 Removed MPI_HOST_INDEX_REGISTER define. 174 * Added function codes for RAID. 175 * 04-09-01 01.01.07 Added alternate define for MPI_DOORBELL_ACTIVE, 176 * MPI_DOORBELL_USED, to better match the spec. 177 * 08-08-01 01.02.01 Original release for v1.2 work. 178 * Changed MPI_VERSION_MINOR from 0x01 to 0x02. 179 * Added define MPI_FUNCTION_TOOLBOX. 180 * 09-28-01 01.02.02 New function code MPI_SCSI_ENCLOSURE_PROCESSOR. 181 * 11-01-01 01.02.03 Changed name to MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR. 182 * -------------------------------------------------------------------------- 183 */ 184 185 #ifndef MPI_H 186 #define MPI_H 187 188 189 /***************************************************************************** 190 * 191 * M P I V e r s i o n D e f i n i t i o n s 192 * 193 *****************************************************************************/ 194 195 #define MPI_VERSION_MAJOR (0x01) 196 #define MPI_VERSION_MINOR (0x02) 197 #define MPI_VERSION ((MPI_VERSION_MAJOR << 8) | MPI_VERSION_MINOR) 198 199 /* Note: The major versions of 0xe0 through 0xff are reserved */ 200 201 /***************************************************************************** 202 * 203 * I O C S t a t e D e f i n i t i o n s 204 * 205 *****************************************************************************/ 206 207 #define MPI_IOC_STATE_RESET (0x00000000) 208 #define MPI_IOC_STATE_READY (0x10000000) 209 #define MPI_IOC_STATE_OPERATIONAL (0x20000000) 210 #define MPI_IOC_STATE_FAULT (0x40000000) 211 212 #define MPI_IOC_STATE_MASK (0xF0000000) 213 #define MPI_IOC_STATE_SHIFT (28) 214 215 /* Fault state codes (product independent range 0x8000-0xFFFF) */ 216 217 #define MPI_FAULT_REQUEST_MESSAGE_PCI_PARITY_ERROR (0x8111) 218 #define MPI_FAULT_REQUEST_MESSAGE_PCI_BUS_FAULT (0x8112) 219 #define MPI_FAULT_REPLY_MESSAGE_PCI_PARITY_ERROR (0x8113) 220 #define MPI_FAULT_REPLY_MESSAGE_PCI_BUS_FAULT (0x8114) 221 #define MPI_FAULT_DATA_SEND_PCI_PARITY_ERROR (0x8115) 222 #define MPI_FAULT_DATA_SEND_PCI_BUS_FAULT (0x8116) 223 #define MPI_FAULT_DATA_RECEIVE_PCI_PARITY_ERROR (0x8117) 224 #define MPI_FAULT_DATA_RECEIVE_PCI_BUS_FAULT (0x8118) 225 226 227 /***************************************************************************** 228 * 229 * P C I S y s t e m I n t e r f a c e R e g i s t e r s 230 * 231 *****************************************************************************/ 232 233 /* S y s t e m D o o r b e l l */ 234 #define MPI_DOORBELL_OFFSET (0x00000000) 235 #define MPI_DOORBELL_ACTIVE (0x08000000) /* DoorbellUsed */ 236 #define MPI_DOORBELL_USED (MPI_DOORBELL_ACTIVE) 237 #define MPI_DOORBELL_ACTIVE_SHIFT (27) 238 #define MPI_DOORBELL_WHO_INIT_MASK (0x07000000) 239 #define MPI_DOORBELL_WHO_INIT_SHIFT (24) 240 #define MPI_DOORBELL_FUNCTION_MASK (0xFF000000) 241 #define MPI_DOORBELL_FUNCTION_SHIFT (24) 242 #define MPI_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 243 #define MPI_DOORBELL_ADD_DWORDS_SHIFT (16) 244 #define MPI_DOORBELL_DATA_MASK (0x0000FFFF) 245 246 247 #define MPI_WRITE_SEQUENCE_OFFSET (0x00000004) 248 #define MPI_WRSEQ_KEY_VALUE_MASK (0x0000000F) 249 #define MPI_WRSEQ_1ST_KEY_VALUE (0x04) 250 #define MPI_WRSEQ_2ND_KEY_VALUE (0x0B) 251 #define MPI_WRSEQ_3RD_KEY_VALUE (0x02) 252 #define MPI_WRSEQ_4TH_KEY_VALUE (0x07) 253 #define MPI_WRSEQ_5TH_KEY_VALUE (0x0D) 254 255 #define MPI_DIAGNOSTIC_OFFSET (0x00000008) 256 #define MPI_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 257 #define MPI_DIAG_PREVENT_IOC_BOOT (0x00000200) 258 #define MPI_DIAG_DRWE (0x00000080) 259 #define MPI_DIAG_FLASH_BAD_SIG (0x00000040) 260 #define MPI_DIAG_RESET_HISTORY (0x00000020) 261 #define MPI_DIAG_RW_ENABLE (0x00000010) 262 #define MPI_DIAG_RESET_ADAPTER (0x00000004) 263 #define MPI_DIAG_DISABLE_ARM (0x00000002) 264 #define MPI_DIAG_MEM_ENABLE (0x00000001) 265 266 #define MPI_TEST_BASE_ADDRESS_OFFSET (0x0000000C) 267 268 #define MPI_DIAG_RW_DATA_OFFSET (0x00000010) 269 270 #define MPI_DIAG_RW_ADDRESS_OFFSET (0x00000014) 271 272 #define MPI_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 273 #define MPI_HIS_IOP_DOORBELL_STATUS (0x80000000) 274 #define MPI_HIS_REPLY_MESSAGE_INTERRUPT (0x00000008) 275 #define MPI_HIS_DOORBELL_INTERRUPT (0x00000001) 276 277 #define MPI_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 278 #define MPI_HIM_RIM (0x00000008) 279 #define MPI_HIM_DIM (0x00000001) 280 281 #define MPI_REQUEST_QUEUE_OFFSET (0x00000040) 282 #define MPI_REQUEST_POST_FIFO_OFFSET (0x00000040) 283 284 #define MPI_REPLY_QUEUE_OFFSET (0x00000044) 285 #define MPI_REPLY_POST_FIFO_OFFSET (0x00000044) 286 #define MPI_REPLY_FREE_FIFO_OFFSET (0x00000044) 287 288 289 290 /***************************************************************************** 291 * 292 * M e s s a g e F r a m e D e s c r i p t o r s 293 * 294 *****************************************************************************/ 295 296 #define MPI_REQ_MF_DESCRIPTOR_NB_MASK (0x00000003) 297 #define MPI_REQ_MF_DESCRIPTOR_F_BIT (0x00000004) 298 #define MPI_REQ_MF_DESCRIPTOR_ADDRESS_MASK (0xFFFFFFF8) 299 300 #define MPI_ADDRESS_REPLY_A_BIT (0x80000000) 301 #define MPI_ADDRESS_REPLY_ADDRESS_MASK (0x7FFFFFFF) 302 303 #define MPI_CONTEXT_REPLY_A_BIT (0x80000000) 304 #define MPI_CONTEXT_REPLY_TYPE_MASK (0x60000000) 305 #define MPI_CONTEXT_REPLY_TYPE_SCSI_INIT (0x00) 306 #define MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET (0x01) 307 #define MPI_CONTEXT_REPLY_TYPE_LAN (0x02) 308 #define MPI_CONTEXT_REPLY_TYPE_SHIFT (29) 309 #define MPI_CONTEXT_REPLY_CONTEXT_MASK (0x1FFFFFFF) 310 311 312 /****************************************************************************/ 313 /* Context Reply macros */ 314 /****************************************************************************/ 315 316 #define MPI_GET_CONTEXT_REPLY_TYPE(x) (((x) & MPI_CONTEXT_REPLY_TYPE_MASK) \ 317 >> MPI_CONTEXT_REPLY_TYPE_SHIFT) 318 319 #define MPI_SET_CONTEXT_REPLY_TYPE(x, typ) \ 320 ((x) = ((x) & ~MPI_CONTEXT_REPLY_TYPE_MASK) | \ 321 (((typ) << MPI_CONTEXT_REPLY_TYPE_SHIFT) & \ 322 MPI_CONTEXT_REPLY_TYPE_MASK)) 323 324 325 /***************************************************************************** 326 * 327 * M e s s a g e F u n c t i o n s 328 * 0x80 -> 0x8F reserved for private message use per product 329 * 330 * 331 *****************************************************************************/ 332 333 #define MPI_FUNCTION_SCSI_IO_REQUEST (0x00) 334 #define MPI_FUNCTION_SCSI_TASK_MGMT (0x01) 335 #define MPI_FUNCTION_IOC_INIT (0x02) 336 #define MPI_FUNCTION_IOC_FACTS (0x03) 337 #define MPI_FUNCTION_CONFIG (0x04) 338 #define MPI_FUNCTION_PORT_FACTS (0x05) 339 #define MPI_FUNCTION_PORT_ENABLE (0x06) 340 #define MPI_FUNCTION_EVENT_NOTIFICATION (0x07) 341 #define MPI_FUNCTION_EVENT_ACK (0x08) 342 #define MPI_FUNCTION_FW_DOWNLOAD (0x09) 343 #define MPI_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A) 344 #define MPI_FUNCTION_TARGET_ASSIST (0x0B) 345 #define MPI_FUNCTION_TARGET_STATUS_SEND (0x0C) 346 #define MPI_FUNCTION_TARGET_MODE_ABORT (0x0D) 347 #define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC (0x0E) /* obsolete name */ 348 #define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC (0x0F) /* obsolete name */ 349 #define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC (0x10) /* obsolete name */ 350 #define MPI_FUNCTION_TARGET_FC_ABORT (0x11) /* obsolete name */ 351 #define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST (0x0E) 352 #define MPI_FUNCTION_FC_LINK_SRVC_RSP (0x0F) 353 #define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND (0x10) 354 #define MPI_FUNCTION_FC_ABORT (0x11) 355 #define MPI_FUNCTION_FW_UPLOAD (0x12) 356 #define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND (0x13) 357 #define MPI_FUNCTION_FC_PRIMITIVE_SEND (0x14) 358 359 #define MPI_FUNCTION_RAID_ACTION (0x15) 360 #define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 361 362 #define MPI_FUNCTION_TOOLBOX (0x17) 363 364 #define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 365 366 #define MPI_FUNCTION_LAN_SEND (0x20) 367 #define MPI_FUNCTION_LAN_RECEIVE (0x21) 368 #define MPI_FUNCTION_LAN_RESET (0x22) 369 370 #define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 371 #define MPI_FUNCTION_IO_UNIT_RESET (0x41) 372 #define MPI_FUNCTION_HANDSHAKE (0x42) 373 #define MPI_FUNCTION_REPLY_FRAME_REMOVAL (0x43) 374 375 376 377 /***************************************************************************** 378 * 379 * S c a t t e r G a t h e r E l e m e n t s 380 * 381 *****************************************************************************/ 382 383 /****************************************************************************/ 384 /* Simple element structures */ 385 /****************************************************************************/ 386 387 typedef struct _SGE_SIMPLE32 388 { 389 U32 FlagsLength; 390 U32 Address; 391 } SGE_SIMPLE32, MPI_POINTER PTR_SGE_SIMPLE32, 392 SGESimple32_t, MPI_POINTER pSGESimple32_t; 393 394 typedef struct _SGE_SIMPLE64 395 { 396 U32 FlagsLength; 397 U64 Address; 398 } SGE_SIMPLE64, MPI_POINTER PTR_SGE_SIMPLE64, 399 SGESimple64_t, MPI_POINTER pSGESimple64_t; 400 401 typedef struct _SGE_SIMPLE_UNION 402 { 403 U32 FlagsLength; 404 union 405 { 406 U32 Address32; 407 U64 Address64; 408 } _u; 409 } SGESimpleUnion_t, MPI_POINTER pSGESimpleUnion_t, 410 SGE_SIMPLE_UNION, MPI_POINTER PTR_SGE_SIMPLE_UNION; 411 412 /****************************************************************************/ 413 /* Chain element structures */ 414 /****************************************************************************/ 415 416 typedef struct _SGE_CHAIN32 417 { 418 U16 Length; 419 U8 NextChainOffset; 420 U8 Flags; 421 U32 Address; 422 } SGE_CHAIN32, MPI_POINTER PTR_SGE_CHAIN32, 423 SGEChain32_t, MPI_POINTER pSGEChain32_t; 424 425 typedef struct _SGE_CHAIN64 426 { 427 U16 Length; 428 U8 NextChainOffset; 429 U8 Flags; 430 U64 Address; 431 } SGE_CHAIN64, MPI_POINTER PTR_SGE_CHAIN64, 432 SGEChain64_t, MPI_POINTER pSGEChain64_t; 433 434 typedef struct _SGE_CHAIN_UNION 435 { 436 U16 Length; 437 U8 NextChainOffset; 438 U8 Flags; 439 union 440 { 441 U32 Address32; 442 U64 Address64; 443 } _u; 444 } SGE_CHAIN_UNION, MPI_POINTER PTR_SGE_CHAIN_UNION, 445 SGEChainUnion_t, MPI_POINTER pSGEChainUnion_t; 446 447 /****************************************************************************/ 448 /* Transaction Context element */ 449 /****************************************************************************/ 450 451 typedef struct _SGE_TRANSACTION32 452 { 453 U8 Reserved; 454 U8 ContextSize; 455 U8 DetailsLength; 456 U8 Flags; 457 U32 TransactionContext[1]; 458 U32 TransactionDetails[1]; 459 } SGE_TRANSACTION32, MPI_POINTER PTR_SGE_TRANSACTION32, 460 SGETransaction32_t, MPI_POINTER pSGETransaction32_t; 461 462 typedef struct _SGE_TRANSACTION64 463 { 464 U8 Reserved; 465 U8 ContextSize; 466 U8 DetailsLength; 467 U8 Flags; 468 U32 TransactionContext[2]; 469 U32 TransactionDetails[1]; 470 } SGE_TRANSACTION64, MPI_POINTER PTR_SGE_TRANSACTION64, 471 SGETransaction64_t, MPI_POINTER pSGETransaction64_t; 472 473 typedef struct _SGE_TRANSACTION96 474 { 475 U8 Reserved; 476 U8 ContextSize; 477 U8 DetailsLength; 478 U8 Flags; 479 U32 TransactionContext[3]; 480 U32 TransactionDetails[1]; 481 } SGE_TRANSACTION96, MPI_POINTER PTR_SGE_TRANSACTION96, 482 SGETransaction96_t, MPI_POINTER pSGETransaction96_t; 483 484 typedef struct _SGE_TRANSACTION128 485 { 486 U8 Reserved; 487 U8 ContextSize; 488 U8 DetailsLength; 489 U8 Flags; 490 U32 TransactionContext[4]; 491 U32 TransactionDetails[1]; 492 } SGE_TRANSACTION128, MPI_POINTER PTR_SGE_TRANSACTION128, 493 SGETransaction_t128, MPI_POINTER pSGETransaction_t128; 494 495 typedef struct _SGE_TRANSACTION_UNION 496 { 497 U8 Reserved; 498 U8 ContextSize; 499 U8 DetailsLength; 500 U8 Flags; 501 union 502 { 503 U32 TransactionContext32[1]; 504 U32 TransactionContext64[2]; 505 U32 TransactionContext96[3]; 506 U32 TransactionContext128[4]; 507 } _u; 508 U32 TransactionDetails[1]; 509 } SGE_TRANSACTION_UNION, MPI_POINTER PTR_SGE_TRANSACTION_UNION, 510 SGETransactionUnion_t, MPI_POINTER pSGETransactionUnion_t; 511 512 513 /****************************************************************************/ 514 /* SGE IO types union for IO SGL's */ 515 /****************************************************************************/ 516 517 typedef struct _SGE_IO_UNION 518 { 519 union 520 { 521 SGE_SIMPLE_UNION Simple; 522 SGE_CHAIN_UNION Chain; 523 } _u; 524 } SGE_IO_UNION, MPI_POINTER PTR_SGE_IO_UNION, 525 SGEIOUnion_t, MPI_POINTER pSGEIOUnion_t; 526 527 /****************************************************************************/ 528 /* SGE union for SGL's with Simple and Transaction elements */ 529 /****************************************************************************/ 530 531 typedef struct _SGE_TRANS_SIMPLE_UNION 532 { 533 union 534 { 535 SGE_SIMPLE_UNION Simple; 536 SGE_TRANSACTION_UNION Transaction; 537 } _u; 538 } SGE_TRANS_SIMPLE_UNION, MPI_POINTER PTR_SGE_TRANS_SIMPLE_UNION, 539 SGETransSimpleUnion_t, MPI_POINTER pSGETransSimpleUnion_t; 540 541 /****************************************************************************/ 542 /* All SGE types union */ 543 /****************************************************************************/ 544 545 typedef struct _SGE_MPI_UNION 546 { 547 union 548 { 549 SGE_SIMPLE_UNION Simple; 550 SGE_CHAIN_UNION Chain; 551 SGE_TRANSACTION_UNION Transaction; 552 } _u; 553 } SGE_MPI_UNION, MPI_POINTER PTR_SGE_MPI_UNION, 554 MPI_SGE_UNION_t, MPI_POINTER pMPI_SGE_UNION_t, 555 SGEAllUnion_t, MPI_POINTER pSGEAllUnion_t; 556 557 558 /****************************************************************************/ 559 /* SGE field definition and masks */ 560 /****************************************************************************/ 561 562 /* Flags field bit definitions */ 563 564 #define MPI_SGE_FLAGS_LAST_ELEMENT (0x80) 565 #define MPI_SGE_FLAGS_END_OF_BUFFER (0x40) 566 #define MPI_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 567 #define MPI_SGE_FLAGS_LOCAL_ADDRESS (0x08) 568 #define MPI_SGE_FLAGS_DIRECTION (0x04) 569 #define MPI_SGE_FLAGS_ADDRESS_SIZE (0x02) 570 #define MPI_SGE_FLAGS_END_OF_LIST (0x01) 571 572 #define MPI_SGE_FLAGS_SHIFT (24) 573 574 #define MPI_SGE_LENGTH_MASK (0x00FFFFFF) 575 #define MPI_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 576 577 /* Element Type */ 578 579 #define MPI_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 580 #define MPI_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 581 #define MPI_SGE_FLAGS_CHAIN_ELEMENT (0x30) 582 #define MPI_SGE_FLAGS_ELEMENT_MASK (0x30) 583 584 /* Address location */ 585 586 #define MPI_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 587 588 /* Direction */ 589 590 #define MPI_SGE_FLAGS_IOC_TO_HOST (0x00) 591 #define MPI_SGE_FLAGS_HOST_TO_IOC (0x04) 592 593 /* Address Size */ 594 595 #define MPI_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 596 #define MPI_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 597 598 /* Context Size */ 599 600 #define MPI_SGE_FLAGS_32_BIT_CONTEXT (0x00) 601 #define MPI_SGE_FLAGS_64_BIT_CONTEXT (0x02) 602 #define MPI_SGE_FLAGS_96_BIT_CONTEXT (0x04) 603 #define MPI_SGE_FLAGS_128_BIT_CONTEXT (0x06) 604 605 #define MPI_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 606 #define MPI_SGE_CHAIN_OFFSET_SHIFT (16) 607 608 609 /****************************************************************************/ 610 /* SGE operation Macros */ 611 /****************************************************************************/ 612 613 /* SIMPLE FlagsLength manipulations... */ 614 #define MPI_SGE_SET_FLAGS(f) ((U32)(f) << MPI_SGE_FLAGS_SHIFT) 615 #define MPI_SGE_GET_FLAGS(fl) (((fl) & ~MPI_SGE_LENGTH_MASK) >> MPI_SGE_FLAGS_SHIFT) 616 #define MPI_SGE_LENGTH(fl) ((fl) & MPI_SGE_LENGTH_MASK) 617 #define MPI_SGE_CHAIN_LENGTH(fl) ((fl) & MPI_SGE_CHAIN_LENGTH_MASK) 618 619 #define MPI_SGE_SET_FLAGS_LENGTH(f,l) (MPI_SGE_SET_FLAGS(f) | MPI_SGE_LENGTH(l)) 620 621 #define MPI_pSGE_GET_FLAGS(psg) MPI_SGE_GET_FLAGS((psg)->FlagsLength) 622 #define MPI_pSGE_GET_LENGTH(psg) MPI_SGE_LENGTH((psg)->FlagsLength) 623 #define MPI_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI_SGE_SET_FLAGS_LENGTH(f,l) 624 /* CAUTION - The following are READ-MODIFY-WRITE! */ 625 #define MPI_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI_SGE_SET_FLAGS(f) 626 #define MPI_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI_SGE_LENGTH(l) 627 628 #define MPI_GET_CHAIN_OFFSET(x) ((x&MPI_SGE_CHAIN_OFFSET_MASK)>>MPI_SGE_CHAIN_OFFSET_SHIFT) 629 630 631 632 /***************************************************************************** 633 * 634 * S t a n d a r d M e s s a g e S t r u c t u r e s 635 * 636 *****************************************************************************/ 637 638 /****************************************************************************/ 639 /* Standard message request header for all request messages */ 640 /****************************************************************************/ 641 642 typedef struct _MSG_REQUEST_HEADER 643 { 644 U8 Reserved[2]; /* function specific */ 645 U8 ChainOffset; 646 U8 Function; 647 U8 Reserved1[3]; /* function specific */ 648 U8 MsgFlags; 649 U32 MsgContext; 650 } MSG_REQUEST_HEADER, MPI_POINTER PTR_MSG_REQUEST_HEADER, 651 MPIHeader_t, MPI_POINTER pMPIHeader_t; 652 653 654 /****************************************************************************/ 655 /* Default Reply */ 656 /****************************************************************************/ 657 658 typedef struct _MSG_DEFAULT_REPLY 659 { 660 U8 Reserved[2]; /* function specific */ 661 U8 MsgLength; 662 U8 Function; 663 U8 Reserved1[3]; /* function specific */ 664 U8 MsgFlags; 665 U32 MsgContext; 666 U8 Reserved2[2]; /* function specific */ 667 U16 IOCStatus; 668 U32 IOCLogInfo; 669 } MSG_DEFAULT_REPLY, MPI_POINTER PTR_MSG_DEFAULT_REPLY, 670 MPIDefaultReply_t, MPI_POINTER pMPIDefaultReply_t; 671 672 673 /* MsgFlags definition for all replies */ 674 675 #define MPI_MSGFLAGS_CONTINUATION_REPLY (0x80) 676 677 678 /***************************************************************************** 679 * 680 * I O C S t a t u s V a l u e s 681 * 682 *****************************************************************************/ 683 684 /****************************************************************************/ 685 /* Common IOCStatus values for all replies */ 686 /****************************************************************************/ 687 688 #define MPI_IOCSTATUS_SUCCESS (0x0000) 689 #define MPI_IOCSTATUS_INVALID_FUNCTION (0x0001) 690 #define MPI_IOCSTATUS_BUSY (0x0002) 691 #define MPI_IOCSTATUS_INVALID_SGL (0x0003) 692 #define MPI_IOCSTATUS_INTERNAL_ERROR (0x0004) 693 #define MPI_IOCSTATUS_RESERVED (0x0005) 694 #define MPI_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 695 #define MPI_IOCSTATUS_INVALID_FIELD (0x0007) 696 #define MPI_IOCSTATUS_INVALID_STATE (0x0008) 697 698 /****************************************************************************/ 699 /* Config IOCStatus values */ 700 /****************************************************************************/ 701 702 #define MPI_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 703 #define MPI_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 704 #define MPI_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 705 #define MPI_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 706 #define MPI_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 707 #define MPI_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 708 709 /****************************************************************************/ 710 /* SCSIIO Reply (SPI & FCP) initiator values */ 711 /****************************************************************************/ 712 713 #define MPI_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 714 #define MPI_IOCSTATUS_SCSI_INVALID_BUS (0x0041) 715 #define MPI_IOCSTATUS_SCSI_INVALID_TARGETID (0x0042) 716 #define MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 717 #define MPI_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 718 #define MPI_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 719 #define MPI_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 720 #define MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 721 #define MPI_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 722 #define MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 723 #define MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 724 #define MPI_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 725 #define MPI_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 726 727 /****************************************************************************/ 728 /* SCSI (SPI & FCP) target values */ 729 /****************************************************************************/ 730 731 #define MPI_IOCSTATUS_TARGET_PRIORITY_IO (0x0060) 732 #define MPI_IOCSTATUS_TARGET_INVALID_PORT (0x0061) 733 #define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX (0x0062) 734 #define MPI_IOCSTATUS_TARGET_ABORTED (0x0063) 735 #define MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 736 #define MPI_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 737 #define MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 738 #define MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT (0x006B) 739 740 /****************************************************************************/ 741 /* Additional FCP target values */ 742 /****************************************************************************/ 743 744 #define MPI_IOCSTATUS_TARGET_FC_ABORTED (0x0066) /* obsolete */ 745 #define MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID (0x0067) /* obsolete */ 746 #define MPI_IOCSTATUS_TARGET_FC_DID_INVALID (0x0068) /* obsolete */ 747 #define MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT (0x0069) /* obsolete */ 748 749 /****************************************************************************/ 750 /* Fibre Channel Direct Access values */ 751 /****************************************************************************/ 752 753 #define MPI_IOCSTATUS_FC_ABORTED (0x0066) 754 #define MPI_IOCSTATUS_FC_RX_ID_INVALID (0x0067) 755 #define MPI_IOCSTATUS_FC_DID_INVALID (0x0068) 756 #define MPI_IOCSTATUS_FC_NODE_LOGGED_OUT (0x0069) 757 758 /****************************************************************************/ 759 /* LAN values */ 760 /****************************************************************************/ 761 762 #define MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND (0x0080) 763 #define MPI_IOCSTATUS_LAN_DEVICE_FAILURE (0x0081) 764 #define MPI_IOCSTATUS_LAN_TRANSMIT_ERROR (0x0082) 765 #define MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED (0x0083) 766 #define MPI_IOCSTATUS_LAN_RECEIVE_ERROR (0x0084) 767 #define MPI_IOCSTATUS_LAN_RECEIVE_ABORTED (0x0085) 768 #define MPI_IOCSTATUS_LAN_PARTIAL_PACKET (0x0086) 769 #define MPI_IOCSTATUS_LAN_CANCELED (0x0087) 770 771 772 /****************************************************************************/ 773 /* IOCStatus flag to indicate that log info is available */ 774 /****************************************************************************/ 775 776 #define MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 777 #define MPI_IOCSTATUS_MASK (0x7FFF) 778 779 /****************************************************************************/ 780 /* LogInfo Types */ 781 /****************************************************************************/ 782 783 #define MPI_IOCLOGINFO_TYPE_MASK (0xF0000000) 784 #define MPI_IOCLOGINFO_TYPE_NONE (0x0) 785 #define MPI_IOCLOGINFO_TYPE_SCSI (0x1) 786 #define MPI_IOCLOGINFO_TYPE_FC (0x2) 787 #define MPI_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 788 789 790 #endif 791 792 /* 793 * Copyright (c) 2000, 2001 by LSI Logic Corporation 794 * 795 * Redistribution and use in source and binary forms, with or without 796 * modification, are permitted provided that the following conditions 797 * are met: 798 * 1. Redistributions of source code must retain the above copyright 799 * notice immediately at the beginning of the file, without modification, 800 * this list of conditions, and the following disclaimer. 801 * 2. The name of the author may not be used to endorse or promote products 802 * derived from this software without specific prior written permission. 803 * 804 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 805 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 806 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 807 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 808 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 809 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 810 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 811 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 812 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 813 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 814 * SUCH DAMAGE. 815 * 816 * 817 * Name: MPI_CNFG.H 818 * Title: MPI Config message, structures, and Pages 819 * Creation Date: July 27, 2000 820 * 821 * MPI Version: 01.02.05 822 * 823 * Version History 824 * --------------- 825 * 826 * Date Version Description 827 * -------- -------- ------------------------------------------------------ 828 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 829 * 06-06-00 01.00.01 Update version number for 1.0 release. 830 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 831 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 832 * fields to FC_DEVICE_0 page, updated the page version. 833 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 834 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 835 * and updated the page versions. 836 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 837 * page and updated the page version. 838 * Added Information field and _INFO_PARAMS_NEGOTIATED 839 * definitionto SCSI_DEVICE_0 page. 840 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 841 * page version. 842 * Added BucketsRemaining to LAN_1 page, redefined the 843 * state values, and updated the page version. 844 * Revised bus width definitions in SCSI_PORT_0, 845 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 846 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 847 * version. 848 * Moved FC_DEVICE_0 PageAddress description to spec. 849 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 850 * widths in IOC_0 page and updated the page version. 851 * 11-02-00 01.01.01 Original release for post 1.0 work 852 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 853 * Port Page 2, FC Port Page 4, FC Port Page 5 854 * 11-15-00 01.01.02 Interim changes to match proposals 855 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 856 * 12-05-00 01.01.04 Modified config page actions. 857 * 01-09-01 01.01.05 Added defines for page address formats. 858 * Data size for Manufacturing pages 2 and 3 no longer 859 * defined here. 860 * Io Unit Page 2 size is fixed at 4 adapters and some 861 * flags were changed. 862 * SCSI Port Page 2 Device Settings modified. 863 * New fields added to FC Port Page 0 and some flags 864 * cleaned up. 865 * Removed impedance flash from FC Port Page 1. 866 * Added FC Port pages 6 and 7. 867 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 868 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 869 * Added some LinkType defines for FcPortPage0. 870 * 02-20-01 01.01.08 Started using MPI_POINTER. 871 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 872 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 873 * Added definitions and structures for IOC Page 2 and 874 * RAID Volume Page 2. 875 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 876 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 877 * Added VendorId and ProductRevLevel fields to 878 * RAIDVOL2_IM_PHYS_ID struct. 879 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 880 * defines to make them compatible to MPI version 1.0. 881 * Added structure offset comments. 882 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 883 * removed some obsolete ones. 884 * Added IO Unit Page 3. 885 * Modified defines for Scsi Port Page 2. 886 * Modified RAID Volume Pages. 887 * 08-08-01 01.02.01 Original release for v1.2 work. 888 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 889 * Added defines for the SEP bits in RVP2 VolumeSettings. 890 * Modified the DeviceSettings field in RVP2 to use the 891 * proper structure. 892 * Added defines for SES, SAF-TE, and cross channel for 893 * IOCPage2 CapabilitiesFlags. 894 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 895 * Removed define for 896 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 897 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 898 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 899 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 900 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 901 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 902 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 903 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 904 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 905 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 906 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 907 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 908 * Added rejected bits to SCSI Device Page 0 Information. 909 * Increased size of ALPA array in FC Port Page 2 by one 910 * and removed a one byte reserved field. 911 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 912 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 913 * Added structures for Manufacturing Page 4, IO Unit 914 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 915 * RAID PhysDisk Page 0. 916 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 917 * Modified some of the new defines to make them 32 918 * character unique. 919 * Modified how variable length pages (arrays) are defined. 920 * Added generic defines for hot spare pools and RAID 921 * volume types. 922 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 923 * -------------------------------------------------------------------------- 924 */ 925 926 #ifndef MPI_CNFG_H 927 #define MPI_CNFG_H 928 929 930 /***************************************************************************** 931 * 932 * C o n f i g M e s s a g e a n d S t r u c t u r e s 933 * 934 *****************************************************************************/ 935 936 typedef struct _CONFIG_PAGE_HEADER 937 { 938 U8 PageVersion; /* 00h */ 939 U8 PageLength; /* 01h */ 940 U8 PageNumber; /* 02h */ 941 U8 PageType; /* 03h */ 942 } fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 943 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 944 945 typedef union _CONFIG_PAGE_HEADER_UNION 946 { 947 ConfigPageHeader_t Struct; 948 U8 Bytes[4]; 949 U16 Word16[2]; 950 U32 Word32; 951 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 952 fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 953 954 955 /**************************************************************************** 956 * PageType field values 957 ****************************************************************************/ 958 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 959 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 960 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 961 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 962 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 963 964 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 965 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 966 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 967 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 968 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 969 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 970 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 971 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 972 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 973 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 974 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 975 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 976 977 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 978 979 980 /**************************************************************************** 981 * PageAddress field values 982 ****************************************************************************/ 983 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 984 985 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 986 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 987 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 988 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 989 990 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 991 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 992 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 993 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 994 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 995 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 996 997 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 998 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 999 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 1000 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 1001 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 1002 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 1003 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 1004 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 1005 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 1006 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 1007 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 1008 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 1009 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 1010 1011 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 1012 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 1013 1014 1015 1016 /**************************************************************************** 1017 * Config Request Message 1018 ****************************************************************************/ 1019 typedef struct _MSG_CONFIG 1020 { 1021 U8 Action; /* 00h */ 1022 U8 Reserved; /* 01h */ 1023 U8 ChainOffset; /* 02h */ 1024 U8 Function; /* 03h */ 1025 U8 Reserved1[3]; /* 04h */ 1026 U8 MsgFlags; /* 07h */ 1027 U32 MsgContext; /* 08h */ 1028 U8 Reserved2[8]; /* 0Ch */ 1029 fCONFIG_PAGE_HEADER Header; /* 14h */ 1030 U32 PageAddress; /* 18h */ 1031 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 1032 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 1033 Config_t, MPI_POINTER pConfig_t; 1034 1035 1036 /**************************************************************************** 1037 * Action field values 1038 ****************************************************************************/ 1039 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 1040 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 1041 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 1042 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 1043 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 1044 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 1045 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 1046 1047 1048 /* Config Reply Message */ 1049 typedef struct _MSG_CONFIG_REPLY 1050 { 1051 U8 Action; /* 00h */ 1052 U8 Reserved; /* 01h */ 1053 U8 MsgLength; /* 02h */ 1054 U8 Function; /* 03h */ 1055 U8 Reserved1[3]; /* 04h */ 1056 U8 MsgFlags; /* 07h */ 1057 U32 MsgContext; /* 08h */ 1058 U8 Reserved2[2]; /* 0Ch */ 1059 U16 IOCStatus; /* 0Eh */ 1060 U32 IOCLogInfo; /* 10h */ 1061 fCONFIG_PAGE_HEADER Header; /* 14h */ 1062 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 1063 ConfigReply_t, MPI_POINTER pConfigReply_t; 1064 1065 1066 1067 /***************************************************************************** 1068 * 1069 * C o n f i g u r a t i o n P a g e s 1070 * 1071 *****************************************************************************/ 1072 1073 /**************************************************************************** 1074 * Manufacturing Config pages 1075 ****************************************************************************/ 1076 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 1077 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 1078 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 1079 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 1080 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 1081 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 1082 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 1083 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 1084 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 1085 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 1086 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 1087 1088 typedef struct _CONFIG_PAGE_MANUFACTURING_0 1089 { 1090 fCONFIG_PAGE_HEADER Header; /* 00h */ 1091 U8 ChipName[16]; /* 04h */ 1092 U8 ChipRevision[8]; /* 14h */ 1093 U8 BoardName[16]; /* 1Ch */ 1094 U8 BoardAssembly[16]; /* 2Ch */ 1095 U8 BoardTracerNumber[16]; /* 3Ch */ 1096 1097 } fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 1098 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 1099 1100 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 1101 1102 1103 typedef struct _CONFIG_PAGE_MANUFACTURING_1 1104 { 1105 fCONFIG_PAGE_HEADER Header; /* 00h */ 1106 U8 VPD[256]; /* 04h */ 1107 } fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 1108 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 1109 1110 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 1111 1112 1113 typedef struct _MPI_CHIP_REVISION_ID 1114 { 1115 U16 DeviceID; /* 00h */ 1116 U8 PCIRevisionID; /* 02h */ 1117 U8 Reserved; /* 03h */ 1118 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 1119 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 1120 1121 1122 /* 1123 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1124 * one and check Header.PageLength at runtime. 1125 */ 1126 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 1127 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 1128 #endif 1129 1130 typedef struct _CONFIG_PAGE_MANUFACTURING_2 1131 { 1132 fCONFIG_PAGE_HEADER Header; /* 00h */ 1133 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 1134 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 1135 } fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 1136 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 1137 1138 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 1139 1140 1141 /* 1142 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1143 * one and check Header.PageLength at runtime. 1144 */ 1145 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 1146 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 1147 #endif 1148 1149 typedef struct _CONFIG_PAGE_MANUFACTURING_3 1150 { 1151 fCONFIG_PAGE_HEADER Header; /* 00h */ 1152 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 1153 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 1154 } fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 1155 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 1156 1157 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 1158 1159 1160 typedef struct _CONFIG_PAGE_MANUFACTURING_4 1161 { 1162 fCONFIG_PAGE_HEADER Header; /* 00h */ 1163 U32 Reserved1; /* 04h */ 1164 U8 InfoOffset0; /* 08h */ 1165 U8 InfoSize0; /* 09h */ 1166 U8 InfoOffset1; /* 0Ah */ 1167 U8 InfoSize1; /* 0Bh */ 1168 U8 InquirySize; /* 0Ch */ 1169 U8 Reserved2; /* 0Dh */ 1170 U16 Reserved3; /* 0Eh */ 1171 U8 InquiryData[56]; /* 10h */ 1172 U32 ISVolumeSettings; /* 48h */ 1173 U32 IMEVolumeSettings; /* 4Ch */ 1174 U32 IMVolumeSettings; /* 50h */ 1175 } fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 1176 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 1177 1178 #define MPI_MANUFACTURING4_PAGEVERSION (0x00) 1179 1180 1181 /**************************************************************************** 1182 * IO Unit Config Pages 1183 ****************************************************************************/ 1184 1185 typedef struct _CONFIG_PAGE_IO_UNIT_0 1186 { 1187 fCONFIG_PAGE_HEADER Header; /* 00h */ 1188 U64 UniqueValue; /* 04h */ 1189 } fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 1190 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 1191 1192 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 1193 1194 1195 typedef struct _CONFIG_PAGE_IO_UNIT_1 1196 { 1197 fCONFIG_PAGE_HEADER Header; /* 00h */ 1198 U32 Flags; /* 04h */ 1199 } fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 1200 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 1201 1202 #define MPI_IOUNITPAGE1_PAGEVERSION (0x00) 1203 1204 /* IO Unit Page 1 Flags defines */ 1205 1206 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 1207 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 1208 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 1209 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 1210 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 1211 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 1212 1213 1214 typedef struct _MPI_ADAPTER_INFO 1215 { 1216 U8 PciBusNumber; /* 00h */ 1217 U8 PciDeviceAndFunctionNumber; /* 01h */ 1218 U16 AdapterFlags; /* 02h */ 1219 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 1220 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 1221 1222 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1223 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1224 1225 typedef struct _CONFIG_PAGE_IO_UNIT_2 1226 { 1227 fCONFIG_PAGE_HEADER Header; /* 00h */ 1228 U32 Flags; /* 04h */ 1229 U32 BiosVersion; /* 08h */ 1230 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 1231 } fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 1232 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 1233 1234 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00) 1235 1236 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 1237 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 1238 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 1239 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 1240 1241 1242 /* 1243 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1244 * one and check Header.PageLength at runtime. 1245 */ 1246 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 1247 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 1248 #endif 1249 1250 typedef struct _CONFIG_PAGE_IO_UNIT_3 1251 { 1252 fCONFIG_PAGE_HEADER Header; /* 00h */ 1253 U8 GPIOCount; /* 04h */ 1254 U8 Reserved1; /* 05h */ 1255 U16 Reserved2; /* 06h */ 1256 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 1257 } fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 1258 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 1259 1260 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 1261 1262 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 1263 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1264 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 1265 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 1266 1267 1268 /**************************************************************************** 1269 * IOC Config Pages 1270 ****************************************************************************/ 1271 1272 typedef struct _CONFIG_PAGE_IOC_0 1273 { 1274 fCONFIG_PAGE_HEADER Header; /* 00h */ 1275 U32 TotalNVStore; /* 04h */ 1276 U32 FreeNVStore; /* 08h */ 1277 U16 VendorID; /* 0Ch */ 1278 U16 DeviceID; /* 0Eh */ 1279 U8 RevisionID; /* 10h */ 1280 U8 Reserved[3]; /* 11h */ 1281 U32 ClassCode; /* 14h */ 1282 U16 SubsystemVendorID; /* 18h */ 1283 U16 SubsystemID; /* 1Ah */ 1284 } fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 1285 IOCPage0_t, MPI_POINTER pIOCPage0_t; 1286 1287 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 1288 1289 1290 typedef struct _CONFIG_PAGE_IOC_1 1291 { 1292 fCONFIG_PAGE_HEADER Header; /* 00h */ 1293 U32 Flags; /* 04h */ 1294 U32 CoalescingTimeout; /* 08h */ 1295 U8 CoalescingDepth; /* 0Ch */ 1296 U8 Reserved[3]; /* 0Dh */ 1297 } fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 1298 IOCPage1_t, MPI_POINTER pIOCPage1_t; 1299 1300 #define MPI_IOCPAGE1_PAGEVERSION (0x00) 1301 1302 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 1303 1304 1305 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 1306 { 1307 U8 VolumeID; /* 00h */ 1308 U8 VolumeBus; /* 01h */ 1309 U8 VolumeIOC; /* 02h */ 1310 U8 VolumePageNumber; /* 03h */ 1311 U8 VolumeType; /* 04h */ 1312 U8 Reserved2; /* 05h */ 1313 U16 Reserved3; /* 06h */ 1314 } fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 1315 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 1316 1317 /* 1318 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1319 * one and check Header.PageLength at runtime. 1320 */ 1321 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1322 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 1323 #endif 1324 1325 typedef struct _CONFIG_PAGE_IOC_2 1326 { 1327 fCONFIG_PAGE_HEADER Header; /* 00h */ 1328 U32 CapabilitiesFlags; /* 04h */ 1329 U8 NumActiveVolumes; /* 08h */ 1330 U8 MaxVolumes; /* 09h */ 1331 U8 NumActivePhysDisks; /* 0Ah */ 1332 U8 MaxPhysDisks; /* 0Bh */ 1333 fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 1334 } fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 1335 IOCPage2_t, MPI_POINTER pIOCPage2_t; 1336 1337 #define MPI_IOCPAGE2_PAGEVERSION (0x01) 1338 1339 /* IOC Page 2 Capabilities flags */ 1340 1341 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1342 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1343 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1344 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1345 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1346 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1347 1348 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 1349 1350 #define MPI_RAID_VOL_TYPE_IS (0x00) 1351 #define MPI_RAID_VOL_TYPE_IME (0x01) 1352 #define MPI_RAID_VOL_TYPE_IM (0x02) 1353 1354 1355 typedef struct _IOC_3_PHYS_DISK 1356 { 1357 U8 PhysDiskID; /* 00h */ 1358 U8 PhysDiskBus; /* 01h */ 1359 U8 PhysDiskIOC; /* 02h */ 1360 U8 PhysDiskNum; /* 03h */ 1361 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1362 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1363 1364 /* 1365 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1366 * one and check Header.PageLength at runtime. 1367 */ 1368 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1369 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1370 #endif 1371 1372 typedef struct _CONFIG_PAGE_IOC_3 1373 { 1374 fCONFIG_PAGE_HEADER Header; /* 00h */ 1375 U8 NumPhysDisks; /* 04h */ 1376 U8 Reserved1; /* 05h */ 1377 U16 Reserved2; /* 06h */ 1378 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1379 } fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1380 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1381 1382 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1383 1384 1385 typedef struct _IOC_4_SEP 1386 { 1387 U8 SEPTargetID; /* 00h */ 1388 U8 SEPBus; /* 01h */ 1389 U16 Reserved; /* 02h */ 1390 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1391 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1392 1393 /* 1394 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1395 * one and check Header.PageLength at runtime. 1396 */ 1397 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1398 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1399 #endif 1400 1401 typedef struct _CONFIG_PAGE_IOC_4 1402 { 1403 fCONFIG_PAGE_HEADER Header; /* 00h */ 1404 U8 ActiveSEP; /* 04h */ 1405 U8 MaxSEP; /* 05h */ 1406 U16 Reserved1; /* 06h */ 1407 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1408 } fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1409 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1410 1411 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1412 1413 1414 /**************************************************************************** 1415 * SCSI Port Config Pages 1416 ****************************************************************************/ 1417 1418 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1419 { 1420 fCONFIG_PAGE_HEADER Header; /* 00h */ 1421 U32 Capabilities; /* 04h */ 1422 U32 PhysicalInterface; /* 08h */ 1423 } fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1424 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1425 1426 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) 1427 1428 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1429 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1430 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1431 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1432 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1433 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1434 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1435 1436 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1437 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1438 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1439 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1440 1441 1442 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1443 { 1444 fCONFIG_PAGE_HEADER Header; /* 00h */ 1445 U32 Configuration; /* 04h */ 1446 U32 OnBusTimerValue; /* 08h */ 1447 } fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1448 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1449 1450 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) 1451 1452 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1453 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1454 1455 1456 typedef struct _MPI_DEVICE_INFO 1457 { 1458 U8 Timeout; /* 00h */ 1459 U8 SyncFactor; /* 01h */ 1460 U16 DeviceFlags; /* 02h */ 1461 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1462 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1463 1464 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1465 { 1466 fCONFIG_PAGE_HEADER Header; /* 00h */ 1467 U32 PortFlags; /* 04h */ 1468 U32 PortSettings; /* 08h */ 1469 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1470 } fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1471 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1472 1473 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) 1474 1475 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1476 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1477 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1478 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1479 1480 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1481 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1482 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1483 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1484 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1485 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1486 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1487 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1488 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1489 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1490 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1491 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1492 1493 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1494 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1495 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1496 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1497 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1498 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1499 1500 1501 /**************************************************************************** 1502 * SCSI Target Device Config Pages 1503 ****************************************************************************/ 1504 1505 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1506 { 1507 fCONFIG_PAGE_HEADER Header; /* 00h */ 1508 U32 NegotiatedParameters; /* 04h */ 1509 U32 Information; /* 08h */ 1510 } fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1511 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1512 1513 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x02) 1514 1515 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1516 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1517 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1518 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1519 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1520 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1521 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1522 1523 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1524 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1525 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1526 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1527 1528 1529 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1530 { 1531 fCONFIG_PAGE_HEADER Header; /* 00h */ 1532 U32 RequestedParameters; /* 04h */ 1533 U32 Reserved; /* 08h */ 1534 U32 Configuration; /* 0Ch */ 1535 } fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1536 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1537 1538 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x03) 1539 1540 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1541 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1542 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1543 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1544 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1545 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1546 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1547 1548 #define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK (0x00000003) 1549 #define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK (0x00000300) 1550 1551 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1552 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1553 1554 1555 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1556 { 1557 fCONFIG_PAGE_HEADER Header; /* 00h */ 1558 U32 DomainValidation; /* 04h */ 1559 U32 ParityPipeSelect; /* 08h */ 1560 U32 DataPipeSelect; /* 0Ch */ 1561 } fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1562 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1563 1564 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x00) 1565 1566 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1567 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1568 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1569 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1570 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1571 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1572 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1573 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1574 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1575 1576 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1577 1578 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1579 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1580 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1581 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1582 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1583 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1584 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1585 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1586 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1587 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1588 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1589 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1590 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1591 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1592 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1593 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1594 1595 1596 /**************************************************************************** 1597 * FC Port Config Pages 1598 ****************************************************************************/ 1599 1600 typedef struct _CONFIG_PAGE_FC_PORT_0 1601 { 1602 fCONFIG_PAGE_HEADER Header; /* 00h */ 1603 U32 Flags; /* 04h */ 1604 U8 MPIPortNumber; /* 08h */ 1605 U8 LinkType; /* 09h */ 1606 U8 PortState; /* 0Ah */ 1607 U8 Reserved; /* 0Bh */ 1608 U32 PortIdentifier; /* 0Ch */ 1609 U64 WWNN; /* 10h */ 1610 U64 WWPN; /* 18h */ 1611 U32 SupportedServiceClass; /* 20h */ 1612 U32 SupportedSpeeds; /* 24h */ 1613 U32 CurrentSpeed; /* 28h */ 1614 U32 MaxFrameSize; /* 2Ch */ 1615 U64 FabricWWNN; /* 30h */ 1616 U64 FabricWWPN; /* 38h */ 1617 U32 DiscoveredPortsCount; /* 40h */ 1618 U32 MaxInitiators; /* 44h */ 1619 } fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1620 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1621 1622 #define MPI_FCPORTPAGE0_PAGEVERSION (0x01) 1623 1624 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1625 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1626 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1627 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1628 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1629 1630 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1631 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1632 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000030) 1633 1634 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1635 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1636 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1637 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1638 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1639 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1640 1641 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1642 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1643 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1644 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1645 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1646 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1647 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1648 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1649 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1650 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1651 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1652 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1653 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1654 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1655 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1656 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1657 1658 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1659 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1660 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1661 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1662 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1663 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1664 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1665 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1666 1667 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1668 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1669 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1670 1671 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1672 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1673 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1674 1675 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1676 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1677 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1678 1679 1680 typedef struct _CONFIG_PAGE_FC_PORT_1 1681 { 1682 fCONFIG_PAGE_HEADER Header; /* 00h */ 1683 U32 Flags; /* 04h */ 1684 U64 NoSEEPROMWWNN; /* 08h */ 1685 U64 NoSEEPROMWWPN; /* 10h */ 1686 U8 HardALPA; /* 18h */ 1687 U8 LinkConfig; /* 19h */ 1688 U8 TopologyConfig; /* 1Ah */ 1689 U8 Reserved; /* 1Bh */ 1690 } fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1691 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1692 1693 #define MPI_FCPORTPAGE1_PAGEVERSION (0x02) 1694 1695 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1696 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1697 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1698 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1699 1700 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1701 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1702 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1703 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1704 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1705 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1706 1707 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1708 1709 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1710 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1711 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1712 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1713 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1714 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1715 1716 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1717 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1718 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1719 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1720 1721 1722 typedef struct _CONFIG_PAGE_FC_PORT_2 1723 { 1724 fCONFIG_PAGE_HEADER Header; /* 00h */ 1725 U8 NumberActive; /* 04h */ 1726 U8 ALPA[127]; /* 05h */ 1727 } fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1728 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1729 1730 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1731 1732 1733 typedef struct _WWN_FORMAT 1734 { 1735 U64 WWNN; /* 00h */ 1736 U64 WWPN; /* 08h */ 1737 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1738 WWNFormat, MPI_POINTER pWWNFormat; 1739 1740 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1741 { 1742 WWN_FORMAT WWN; 1743 U32 Did; 1744 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1745 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1746 1747 typedef struct _FC_PORT_PERSISTENT 1748 { 1749 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1750 U8 TargetID; /* 10h */ 1751 U8 Bus; /* 11h */ 1752 U16 Flags; /* 12h */ 1753 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1754 PersistentData_t, MPI_POINTER pPersistentData_t; 1755 1756 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1757 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1758 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1759 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1760 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1761 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1762 1763 /* 1764 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1765 * one and check Header.PageLength at runtime. 1766 */ 1767 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1768 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1769 #endif 1770 1771 typedef struct _CONFIG_PAGE_FC_PORT_3 1772 { 1773 fCONFIG_PAGE_HEADER Header; /* 00h */ 1774 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1775 } fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1776 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1777 1778 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1779 1780 1781 typedef struct _CONFIG_PAGE_FC_PORT_4 1782 { 1783 fCONFIG_PAGE_HEADER Header; /* 00h */ 1784 U32 PortFlags; /* 04h */ 1785 U32 PortSettings; /* 08h */ 1786 } fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1787 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1788 1789 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1790 1791 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1792 1793 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1794 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1795 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1796 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1797 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1798 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1799 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1800 1801 1802 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1803 { 1804 U8 Flags; /* 00h */ 1805 U8 AliasAlpa; /* 01h */ 1806 U16 Reserved; /* 02h */ 1807 U64 AliasWWNN; /* 04h */ 1808 U64 AliasWWPN; /* 0Ch */ 1809 } fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1810 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1811 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1812 1813 /* 1814 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1815 * one and check Header.PageLength at runtime. 1816 */ 1817 #ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX 1818 #define MPI_FC_PORT_PAGE_5_ALIAS_MAX (1) 1819 #endif 1820 1821 typedef struct _CONFIG_PAGE_FC_PORT_5 1822 { 1823 fCONFIG_PAGE_HEADER Header; /* 00h */ 1824 fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];/* 04h */ 1825 } fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1826 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1827 1828 #define MPI_FCPORTPAGE5_PAGEVERSION (0x00) 1829 1830 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01) 1831 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02) 1832 1833 1834 typedef struct _CONFIG_PAGE_FC_PORT_6 1835 { 1836 fCONFIG_PAGE_HEADER Header; /* 00h */ 1837 U32 Reserved; /* 04h */ 1838 U64 TimeSinceReset; /* 08h */ 1839 U64 TxFrames; /* 10h */ 1840 U64 RxFrames; /* 18h */ 1841 U64 TxWords; /* 20h */ 1842 U64 RxWords; /* 28h */ 1843 U64 LipCount; /* 30h */ 1844 U64 NosCount; /* 38h */ 1845 U64 ErrorFrames; /* 40h */ 1846 U64 DumpedFrames; /* 48h */ 1847 U64 LinkFailureCount; /* 50h */ 1848 U64 LossOfSyncCount; /* 58h */ 1849 U64 LossOfSignalCount; /* 60h */ 1850 U64 PrimativeSeqErrCount; /* 68h */ 1851 U64 InvalidTxWordCount; /* 70h */ 1852 U64 InvalidCrcCount; /* 78h */ 1853 U64 FcpInitiatorIoCount; /* 80h */ 1854 } fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1855 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1856 1857 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1858 1859 1860 typedef struct _CONFIG_PAGE_FC_PORT_7 1861 { 1862 fCONFIG_PAGE_HEADER Header; /* 00h */ 1863 U32 Reserved; /* 04h */ 1864 U8 PortSymbolicName[256]; /* 08h */ 1865 } fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1866 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1867 1868 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1869 1870 1871 typedef struct _CONFIG_PAGE_FC_PORT_8 1872 { 1873 fCONFIG_PAGE_HEADER Header; /* 00h */ 1874 U32 BitVector[8]; /* 04h */ 1875 } fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1876 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1877 1878 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1879 1880 1881 typedef struct _CONFIG_PAGE_FC_PORT_9 1882 { 1883 fCONFIG_PAGE_HEADER Header; /* 00h */ 1884 U32 Reserved; /* 04h */ 1885 U64 GlobalWWPN; /* 08h */ 1886 U64 GlobalWWNN; /* 10h */ 1887 U32 UnitType; /* 18h */ 1888 U32 PhysicalPortNumber; /* 1Ch */ 1889 U32 NumAttachedNodes; /* 20h */ 1890 U16 IPVersion; /* 24h */ 1891 U16 UDPPortNumber; /* 26h */ 1892 U8 IPAddress[16]; /* 28h */ 1893 U16 Reserved1; /* 38h */ 1894 U16 TopologyDiscoveryFlags; /* 3Ah */ 1895 } fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1896 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1897 1898 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1899 1900 1901 /**************************************************************************** 1902 * FC Device Config Pages 1903 ****************************************************************************/ 1904 1905 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1906 { 1907 fCONFIG_PAGE_HEADER Header; /* 00h */ 1908 U64 WWNN; /* 04h */ 1909 U64 WWPN; /* 0Ch */ 1910 U32 PortIdentifier; /* 14h */ 1911 U8 Protocol; /* 18h */ 1912 U8 Flags; /* 19h */ 1913 U16 BBCredit; /* 1Ah */ 1914 U16 MaxRxFrameSize; /* 1Ch */ 1915 U8 Reserved1; /* 1Eh */ 1916 U8 PortNumber; /* 1Fh */ 1917 U8 FcPhLowestVersion; /* 20h */ 1918 U8 FcPhHighestVersion; /* 21h */ 1919 U8 CurrentTargetID; /* 22h */ 1920 U8 CurrentBus; /* 23h */ 1921 } fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 1922 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 1923 1924 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) 1925 1926 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 1927 1928 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 1929 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 1930 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 1931 1932 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 1933 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 1934 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 1935 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1936 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1937 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1938 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1939 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1940 1941 1942 /**************************************************************************** 1943 * RAID Volume Config Pages 1944 ****************************************************************************/ 1945 1946 typedef struct _RAID_VOL0_PHYS_DISK 1947 { 1948 U16 Reserved; /* 00h */ 1949 U8 PhysDiskMap; /* 02h */ 1950 U8 PhysDiskNum; /* 03h */ 1951 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 1952 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 1953 1954 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1955 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1956 1957 typedef struct _RAID_VOL0_STATUS 1958 { 1959 U8 Flags; /* 00h */ 1960 U8 State; /* 01h */ 1961 U16 Reserved; /* 02h */ 1962 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 1963 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 1964 1965 /* RAID Volume Page 0 VolumeStatus defines */ 1966 1967 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 1968 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 1969 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 1970 1971 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 1972 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 1973 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 1974 1975 typedef struct _RAID_VOL0_SETTINGS 1976 { 1977 U16 Settings; /* 00h */ 1978 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1979 U8 Reserved; /* 02h */ 1980 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 1981 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 1982 1983 /* RAID Volume Page 0 VolumeSettings defines */ 1984 1985 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 1986 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 1987 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 1988 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 1989 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 1990 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 1991 1992 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1993 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 1994 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 1995 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 1996 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 1997 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 1998 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 1999 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2000 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2001 2002 /* 2003 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2004 * one and check Header.PageLength at runtime. 2005 */ 2006 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2007 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2008 #endif 2009 2010 typedef struct _CONFIG_PAGE_RAID_VOL_0 2011 { 2012 fCONFIG_PAGE_HEADER Header; /* 00h */ 2013 U8 VolumeID; /* 04h */ 2014 U8 VolumeBus; /* 05h */ 2015 U8 VolumeIOC; /* 06h */ 2016 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2017 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2018 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2019 U32 MaxLBA; /* 10h */ 2020 U32 Reserved1; /* 14h */ 2021 U32 StripeSize; /* 18h */ 2022 U32 Reserved2; /* 1Ch */ 2023 U32 Reserved3; /* 20h */ 2024 U8 NumPhysDisks; /* 24h */ 2025 U8 Reserved4; /* 25h */ 2026 U16 Reserved5; /* 26h */ 2027 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2028 } fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2029 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2030 2031 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x00) 2032 2033 2034 /**************************************************************************** 2035 * RAID Physical Disk Config Pages 2036 ****************************************************************************/ 2037 2038 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2039 { 2040 U8 ErrorCdbByte; /* 00h */ 2041 U8 ErrorSenseKey; /* 01h */ 2042 U16 Reserved; /* 02h */ 2043 U16 ErrorCount; /* 04h */ 2044 U8 ErrorASC; /* 06h */ 2045 U8 ErrorASCQ; /* 07h */ 2046 U16 SmartCount; /* 08h */ 2047 U8 SmartASC; /* 0Ah */ 2048 U8 SmartASCQ; /* 0Bh */ 2049 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2050 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2051 2052 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2053 { 2054 U8 VendorID[8]; /* 00h */ 2055 U8 ProductID[16]; /* 08h */ 2056 U8 ProductRevLevel[4]; /* 18h */ 2057 U8 Info[32]; /* 1Ch */ 2058 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2059 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2060 2061 typedef struct _RAID_PHYS_DISK0_SETTINGS 2062 { 2063 U8 SepID; /* 00h */ 2064 U8 SepBus; /* 01h */ 2065 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2066 U8 PhysDiskSettings; /* 03h */ 2067 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2068 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2069 2070 typedef struct _RAID_PHYS_DISK0_STATUS 2071 { 2072 U8 Flags; /* 00h */ 2073 U8 State; /* 01h */ 2074 U16 Reserved; /* 02h */ 2075 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2076 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2077 2078 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 2079 2080 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2081 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2082 2083 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2084 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2085 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2086 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2087 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2088 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2089 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2090 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2091 2092 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2093 { 2094 fCONFIG_PAGE_HEADER Header; /* 00h */ 2095 U8 PhysDiskID; /* 04h */ 2096 U8 PhysDiskBus; /* 05h */ 2097 U8 PhysDiskIOC; /* 06h */ 2098 U8 PhysDiskNum; /* 07h */ 2099 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2100 U32 Reserved1; /* 0Ch */ 2101 U32 Reserved2; /* 10h */ 2102 U32 Reserved3; /* 14h */ 2103 U8 DiskIdentifier[16]; /* 18h */ 2104 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2105 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2106 U32 MaxLBA; /* 68h */ 2107 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2108 } fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2109 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2110 2111 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) 2112 2113 2114 /**************************************************************************** 2115 * LAN Config Pages 2116 ****************************************************************************/ 2117 2118 typedef struct _CONFIG_PAGE_LAN_0 2119 { 2120 ConfigPageHeader_t Header; /* 00h */ 2121 U16 TxRxModes; /* 04h */ 2122 U16 Reserved; /* 06h */ 2123 U32 PacketPrePad; /* 08h */ 2124 } fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2125 LANPage0_t, MPI_POINTER pLANPage0_t; 2126 2127 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2128 2129 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2130 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2131 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2132 2133 typedef struct _CONFIG_PAGE_LAN_1 2134 { 2135 ConfigPageHeader_t Header; /* 00h */ 2136 U16 Reserved; /* 04h */ 2137 U8 CurrentDeviceState; /* 06h */ 2138 U8 Reserved1; /* 07h */ 2139 U32 MinPacketSize; /* 08h */ 2140 U32 MaxPacketSize; /* 0Ch */ 2141 U32 HardwareAddressLow; /* 10h */ 2142 U32 HardwareAddressHigh; /* 14h */ 2143 U32 MaxWireSpeedLow; /* 18h */ 2144 U32 MaxWireSpeedHigh; /* 1Ch */ 2145 U32 BucketsRemaining; /* 20h */ 2146 U32 MaxReplySize; /* 24h */ 2147 U32 NegWireSpeedLow; /* 28h */ 2148 U32 NegWireSpeedHigh; /* 2Ch */ 2149 } fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2150 LANPage1_t, MPI_POINTER pLANPage1_t; 2151 2152 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2153 2154 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2155 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2156 2157 #endif 2158 2159 2160 /* 2161 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2162 * 2163 * Redistribution and use in source and binary forms, with or without 2164 * modification, are permitted provided that the following conditions 2165 * are met: 2166 * 1. Redistributions of source code must retain the above copyright 2167 * notice immediately at the beginning of the file, without modification, 2168 * this list of conditions, and the following disclaimer. 2169 * 2. The name of the author may not be used to endorse or promote products 2170 * derived from this software without specific prior written permission. 2171 * 2172 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2173 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2174 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2175 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2176 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2177 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2178 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2179 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2180 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2181 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2182 * SUCH DAMAGE. 2183 * 2184 * 2185 * Name: MPI_FC.H 2186 * Title: MPI Fibre Channel messages and structures 2187 * Creation Date: June 12, 2000 2188 * 2189 * MPI Version: 01.02.02 2190 * 2191 * Version History 2192 * --------------- 2193 * 2194 * Date Version Description 2195 * -------- -------- ------------------------------------------------------ 2196 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2197 * 06-06-00 01.00.01 Update version number for 1.0 release. 2198 * 06-12-00 01.00.02 Added _MSG_FC_ABORT_REPLY structure. 2199 * 11-02-00 01.01.01 Original release for post 1.0 work 2200 * 12-04-00 01.01.02 Added messages for Common Transport Send and 2201 * Primitive Send. 2202 * 01-09-01 01.01.03 Modifed some of the new flags to have an MPI prefix 2203 * and modified the FcPrimitiveSend flags. 2204 * 01-25-01 01.01.04 Move InitiatorIndex in LinkServiceRsp reply to a larger 2205 * field. 2206 * Added FC_ABORT_TYPE_CT_SEND_REQUEST and 2207 * FC_ABORT_TYPE_EXLINKSEND_REQUEST for FcAbort request. 2208 * Added MPI_FC_PRIM_SEND_FLAGS_STOP_SEND. 2209 * 02-20-01 01.01.05 Started using MPI_POINTER. 2210 * 03-27-01 01.01.06 Added Flags field to MSG_LINK_SERVICE_BUFFER_POST_REPLY 2211 * and defined MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED. 2212 * Added MPI_FC_PRIM_SEND_FLAGS_RESET_LINK define. 2213 * Added structure offset comments. 2214 * 04-09-01 01.01.07 Added RspLength field to MSG_LINK_SERVICE_RSP_REQUEST. 2215 * 08-08-01 01.02.01 Original release for v1.2 work. 2216 * 09-28-01 01.02.02 Change name of reserved field in 2217 * MSG_LINK_SERVICE_RSP_REPLY. 2218 * -------------------------------------------------------------------------- 2219 */ 2220 2221 #ifndef MPI_FC_H 2222 #define MPI_FC_H 2223 2224 2225 /***************************************************************************** 2226 * 2227 * F C T a r g e t M o d e M e s s a g e s 2228 * 2229 *****************************************************************************/ 2230 2231 /****************************************************************************/ 2232 /* Link Service Buffer Post messages */ 2233 /****************************************************************************/ 2234 2235 typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REQUEST 2236 { 2237 U8 BufferPostFlags; /* 00h */ 2238 U8 BufferCount; /* 01h */ 2239 U8 ChainOffset; /* 02h */ 2240 U8 Function; /* 03h */ 2241 U16 Reserved; /* 04h */ 2242 U8 Reserved1; /* 06h */ 2243 U8 MsgFlags; /* 07h */ 2244 U32 MsgContext; /* 08h */ 2245 SGE_TRANS_SIMPLE_UNION SGL; 2246 } MSG_LINK_SERVICE_BUFFER_POST_REQUEST, 2247 MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REQUEST, 2248 LinkServiceBufferPostRequest_t, MPI_POINTER pLinkServiceBufferPostRequest_t; 2249 2250 #define LINK_SERVICE_BUFFER_POST_FLAGS_PORT_MASK (0x01) 2251 2252 typedef struct _WWNFORMAT 2253 { 2254 U32 PortNameHigh; /* 00h */ 2255 U32 PortNameLow; /* 04h */ 2256 U32 NodeNameHigh; /* 08h */ 2257 U32 NodeNameLow; /* 0Ch */ 2258 } WWNFORMAT, 2259 WwnFormat_t; 2260 2261 /* Link Service Buffer Post Reply */ 2262 typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REPLY 2263 { 2264 U8 Flags; /* 00h */ 2265 U8 Reserved; /* 01h */ 2266 U8 MsgLength; /* 02h */ 2267 U8 Function; /* 03h */ 2268 U16 Reserved1; /* 04h */ 2269 U8 PortNumber; /* 06h */ 2270 U8 MsgFlags; /* 07h */ 2271 U32 MsgContext; /* 08h */ 2272 U16 Reserved2; /* 0Ch */ 2273 U16 IOCStatus; /* 0Eh */ 2274 U32 IOCLogInfo; /* 10h */ 2275 U32 TransferLength; /* 14h */ 2276 U32 TransactionContext; /* 18h */ 2277 U32 Rctl_Did; /* 1Ch */ 2278 U32 Csctl_Sid; /* 20h */ 2279 U32 Type_Fctl; /* 24h */ 2280 U16 SeqCnt; /* 28h */ 2281 U8 Dfctl; /* 2Ah */ 2282 U8 SeqId; /* 2Bh */ 2283 U16 Rxid; /* 2Ch */ 2284 U16 Oxid; /* 2Eh */ 2285 U32 Parameter; /* 30h */ 2286 WWNFORMAT Wwn; /* 34h */ 2287 } MSG_LINK_SERVICE_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REPLY, 2288 LinkServiceBufferPostReply_t, MPI_POINTER pLinkServiceBufferPostReply_t; 2289 2290 #define MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED (0x80) 2291 2292 #define MPI_FC_DID_MASK (0x00FFFFFF) 2293 #define MPI_FC_DID_SHIFT (0) 2294 #define MPI_FC_RCTL_MASK (0xFF000000) 2295 #define MPI_FC_RCTL_SHIFT (24) 2296 #define MPI_FC_SID_MASK (0x00FFFFFF) 2297 #define MPI_FC_SID_SHIFT (0) 2298 #define MPI_FC_CSCTL_MASK (0xFF000000) 2299 #define MPI_FC_CSCTL_SHIFT (24) 2300 #define MPI_FC_FCTL_MASK (0x00FFFFFF) 2301 #define MPI_FC_FCTL_SHIFT (0) 2302 #define MPI_FC_TYPE_MASK (0xFF000000) 2303 #define MPI_FC_TYPE_SHIFT (24) 2304 2305 /* obsolete name for the above */ 2306 #define FCP_TARGET_DID_MASK (0x00FFFFFF) 2307 #define FCP_TARGET_DID_SHIFT (0) 2308 #define FCP_TARGET_RCTL_MASK (0xFF000000) 2309 #define FCP_TARGET_RCTL_SHIFT (24) 2310 #define FCP_TARGET_SID_MASK (0x00FFFFFF) 2311 #define FCP_TARGET_SID_SHIFT (0) 2312 #define FCP_TARGET_CSCTL_MASK (0xFF000000) 2313 #define FCP_TARGET_CSCTL_SHIFT (24) 2314 #define FCP_TARGET_FCTL_MASK (0x00FFFFFF) 2315 #define FCP_TARGET_FCTL_SHIFT (0) 2316 #define FCP_TARGET_TYPE_MASK (0xFF000000) 2317 #define FCP_TARGET_TYPE_SHIFT (24) 2318 2319 2320 /****************************************************************************/ 2321 /* Link Service Response messages */ 2322 /****************************************************************************/ 2323 2324 typedef struct _MSG_LINK_SERVICE_RSP_REQUEST 2325 { 2326 U8 RspFlags; /* 00h */ 2327 U8 RspLength; /* 01h */ 2328 U8 ChainOffset; /* 02h */ 2329 U8 Function; /* 03h */ 2330 U16 Reserved1; /* 04h */ 2331 U8 Reserved2; /* 06h */ 2332 U8 MsgFlags; /* 07h */ 2333 U32 MsgContext; /* 08h */ 2334 U32 Rctl_Did; /* 0Ch */ 2335 U32 Csctl_Sid; /* 10h */ 2336 U32 Type_Fctl; /* 14h */ 2337 U16 SeqCnt; /* 18h */ 2338 U8 Dfctl; /* 1Ah */ 2339 U8 SeqId; /* 1Bh */ 2340 U16 Rxid; /* 1Ch */ 2341 U16 Oxid; /* 1Eh */ 2342 U32 Parameter; /* 20h */ 2343 SGE_SIMPLE_UNION SGL; /* 24h */ 2344 } MSG_LINK_SERVICE_RSP_REQUEST, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REQUEST, 2345 LinkServiceRspRequest_t, MPI_POINTER pLinkServiceRspRequest_t; 2346 2347 #define LINK_SERVICE_RSP_FLAGS_IMMEDIATE (0x80) 2348 #define LINK_SERVICE_RSP_FLAGS_PORT_MASK (0x01) 2349 2350 2351 /* Link Service Response Reply */ 2352 typedef struct _MSG_LINK_SERVICE_RSP_REPLY 2353 { 2354 U16 Reserved; /* 00h */ 2355 U8 MsgLength; /* 02h */ 2356 U8 Function; /* 03h */ 2357 U16 Reserved1; /* 04h */ 2358 U8 Reserved_0100_InitiatorIndex; /* 06h */ /* obsolete InitiatorIndex */ 2359 U8 MsgFlags; /* 07h */ 2360 U32 MsgContext; /* 08h */ 2361 U16 Reserved3; /* 0Ch */ 2362 U16 IOCStatus; /* 0Eh */ 2363 U32 IOCLogInfo; /* 10h */ 2364 U32 InitiatorIndex; /* 14h */ 2365 } MSG_LINK_SERVICE_RSP_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REPLY, 2366 LinkServiceRspReply_t, MPI_POINTER pLinkServiceRspReply_t; 2367 2368 2369 /****************************************************************************/ 2370 /* Extended Link Service Send messages */ 2371 /****************************************************************************/ 2372 2373 typedef struct _MSG_EXLINK_SERVICE_SEND_REQUEST 2374 { 2375 U8 SendFlags; /* 00h */ 2376 U8 Reserved; /* 01h */ 2377 U8 ChainOffset; /* 02h */ 2378 U8 Function; /* 03h */ 2379 U32 MsgFlags_Did; /* 04h */ 2380 U32 MsgContext; /* 08h */ 2381 U32 ElsCommandCode; /* 0Ch */ 2382 SGE_SIMPLE_UNION SGL; /* 10h */ 2383 } MSG_EXLINK_SERVICE_SEND_REQUEST, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REQUEST, 2384 ExLinkServiceSendRequest_t, MPI_POINTER pExLinkServiceSendRequest_t; 2385 2386 #define EX_LINK_SERVICE_SEND_DID_MASK (0x00FFFFFF) 2387 #define EX_LINK_SERVICE_SEND_DID_SHIFT (0) 2388 #define EX_LINK_SERVICE_SEND_MSGFLAGS_MASK (0xFF000000) 2389 #define EX_LINK_SERVICE_SEND_MSGFLAGS_SHIFT (24) 2390 2391 2392 /* Extended Link Service Send Reply */ 2393 typedef struct _MSG_EXLINK_SERVICE_SEND_REPLY 2394 { 2395 U16 Reserved; /* 00h */ 2396 U8 MsgLength; /* 02h */ 2397 U8 Function; /* 03h */ 2398 U16 Reserved1; /* 04h */ 2399 U8 Reserved2; /* 06h */ 2400 U8 MsgFlags; /* 07h */ 2401 U32 MsgContext; /* 08h */ 2402 U16 Reserved3; /* 0Ch */ 2403 U16 IOCStatus; /* 0Eh */ 2404 U32 IOCLogInfo; /* 10h */ 2405 U32 ResponseLength; /* 14h */ 2406 } MSG_EXLINK_SERVICE_SEND_REPLY, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REPLY, 2407 ExLinkServiceSendReply_t, MPI_POINTER pExLinkServiceSendReply_t; 2408 2409 /****************************************************************************/ 2410 /* FC Abort messages */ 2411 /****************************************************************************/ 2412 2413 typedef struct _MSG_FC_ABORT_REQUEST 2414 { 2415 U8 AbortFlags; /* 00h */ 2416 U8 AbortType; /* 01h */ 2417 U8 ChainOffset; /* 02h */ 2418 U8 Function; /* 03h */ 2419 U16 Reserved1; /* 04h */ 2420 U8 Reserved2; /* 06h */ 2421 U8 MsgFlags; /* 07h */ 2422 U32 MsgContext; /* 08h */ 2423 U32 TransactionContextToAbort; /* 0Ch */ 2424 } MSG_FC_ABORT_REQUEST, MPI_POINTER PTR_MSG_FC_ABORT_REQUEST, 2425 FcAbortRequest_t, MPI_POINTER pFcAbortRequest_t; 2426 2427 #define FC_ABORT_FLAG_PORT_MASK (0x01) 2428 2429 #define FC_ABORT_TYPE_ALL_FC_BUFFERS (0x00) 2430 #define FC_ABORT_TYPE_EXACT_FC_BUFFER (0x01) 2431 #define FC_ABORT_TYPE_CT_SEND_REQUEST (0x02) 2432 #define FC_ABORT_TYPE_EXLINKSEND_REQUEST (0x03) 2433 2434 /* FC Abort Reply */ 2435 typedef struct _MSG_FC_ABORT_REPLY 2436 { 2437 U16 Reserved; /* 00h */ 2438 U8 MsgLength; /* 02h */ 2439 U8 Function; /* 03h */ 2440 U16 Reserved1; /* 04h */ 2441 U8 Reserved2; /* 06h */ 2442 U8 MsgFlags; /* 07h */ 2443 U32 MsgContext; /* 08h */ 2444 U16 Reserved3; /* 0Ch */ 2445 U16 IOCStatus; /* 0Eh */ 2446 U32 IOCLogInfo; /* 10h */ 2447 } MSG_FC_ABORT_REPLY, MPI_POINTER PTR_MSG_FC_ABORT_REPLY, 2448 FcAbortReply_t, MPI_POINTER pFcAbortReply_t; 2449 2450 2451 /****************************************************************************/ 2452 /* FC Common Transport Send messages */ 2453 /****************************************************************************/ 2454 2455 typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REQUEST 2456 { 2457 U8 SendFlags; /* 00h */ 2458 U8 Reserved; /* 01h */ 2459 U8 ChainOffset; /* 02h */ 2460 U8 Function; /* 03h */ 2461 U32 MsgFlags_Did; /* 04h */ 2462 U32 MsgContext; /* 08h */ 2463 U16 CTCommandCode; /* 0Ch */ 2464 U8 FsType; /* 0Eh */ 2465 U8 Reserved1; /* 0Fh */ 2466 SGE_SIMPLE_UNION SGL; /* 10h */ 2467 } MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, 2468 MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, 2469 FcCommonTransportSendRequest_t, MPI_POINTER pFcCommonTransportSendRequest_t; 2470 2471 #define MPI_FC_CT_SEND_DID_MASK (0x00FFFFFF) 2472 #define MPI_FC_CT_SEND_DID_SHIFT (0) 2473 #define MPI_FC_CT_SEND_MSGFLAGS_MASK (0xFF000000) 2474 #define MPI_FC_CT_SEND_MSGFLAGS_SHIFT (24) 2475 2476 2477 /* FC Common Transport Send Reply */ 2478 typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REPLY 2479 { 2480 U16 Reserved; /* 00h */ 2481 U8 MsgLength; /* 02h */ 2482 U8 Function; /* 03h */ 2483 U16 Reserved1; /* 04h */ 2484 U8 Reserved2; /* 06h */ 2485 U8 MsgFlags; /* 07h */ 2486 U32 MsgContext; /* 08h */ 2487 U16 Reserved3; /* 0Ch */ 2488 U16 IOCStatus; /* 0Eh */ 2489 U32 IOCLogInfo; /* 10h */ 2490 U32 ResponseLength; /* 14h */ 2491 } MSG_FC_COMMON_TRANSPORT_SEND_REPLY, MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REPLY, 2492 FcCommonTransportSendReply_t, MPI_POINTER pFcCommonTransportSendReply_t; 2493 2494 2495 /****************************************************************************/ 2496 /* FC Primitive Send messages */ 2497 /****************************************************************************/ 2498 2499 typedef struct _MSG_FC_PRIMITIVE_SEND_REQUEST 2500 { 2501 U8 SendFlags; /* 00h */ 2502 U8 Reserved; /* 01h */ 2503 U8 ChainOffset; /* 02h */ 2504 U8 Function; /* 03h */ 2505 U16 Reserved1; /* 04h */ 2506 U8 Reserved2; /* 06h */ 2507 U8 MsgFlags; /* 07h */ 2508 U32 MsgContext; /* 08h */ 2509 U8 FcPrimitive[4]; /* 0Ch */ 2510 } MSG_FC_PRIMITIVE_SEND_REQUEST, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REQUEST, 2511 FcPrimitiveSendRequest_t, MPI_POINTER pFcPrimitiveSendRequest_t; 2512 2513 #define MPI_FC_PRIM_SEND_FLAGS_PORT_MASK (0x01) 2514 #define MPI_FC_PRIM_SEND_FLAGS_RESET_LINK (0x04) 2515 #define MPI_FC_PRIM_SEND_FLAGS_STOP_SEND (0x08) 2516 #define MPI_FC_PRIM_SEND_FLAGS_SEND_ONCE (0x10) 2517 #define MPI_FC_PRIM_SEND_FLAGS_SEND_AROUND (0x20) 2518 #define MPI_FC_PRIM_SEND_FLAGS_UNTIL_FULL (0x40) 2519 #define MPI_FC_PRIM_SEND_FLAGS_FOREVER (0x80) 2520 2521 /* FC Primitive Send Reply */ 2522 typedef struct _MSG_FC_PRIMITIVE_SEND_REPLY 2523 { 2524 U8 SendFlags; /* 00h */ 2525 U8 Reserved; /* 01h */ 2526 U8 MsgLength; /* 02h */ 2527 U8 Function; /* 03h */ 2528 U16 Reserved1; /* 04h */ 2529 U8 Reserved2; /* 06h */ 2530 U8 MsgFlags; /* 07h */ 2531 U32 MsgContext; /* 08h */ 2532 U16 Reserved3; /* 0Ch */ 2533 U16 IOCStatus; /* 0Eh */ 2534 U32 IOCLogInfo; /* 10h */ 2535 } MSG_FC_PRIMITIVE_SEND_REPLY, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REPLY, 2536 FcPrimitiveSendReply_t, MPI_POINTER pFcPrimitiveSendReply_t; 2537 2538 #endif 2539 2540 2541 /* 2542 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2543 * 2544 * Redistribution and use in source and binary forms, with or without 2545 * modification, are permitted provided that the following conditions 2546 * are met: 2547 * 1. Redistributions of source code must retain the above copyright 2548 * notice immediately at the beginning of the file, without modification, 2549 * this list of conditions, and the following disclaimer. 2550 * 2. The name of the author may not be used to endorse or promote products 2551 * derived from this software without specific prior written permission. 2552 * 2553 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2554 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2555 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2556 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2557 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2558 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2559 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2560 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2561 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2562 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2563 * SUCH DAMAGE. 2564 * 2565 * 2566 * Name: MPI_INIT.H 2567 * Title: MPI initiator mode messages and structures 2568 * Creation Date: June 8, 2000 2569 * 2570 * MPI Version: 01.02.04 2571 * 2572 * Version History 2573 * --------------- 2574 * 2575 * Date Version Description 2576 * -------- -------- ------------------------------------------------------ 2577 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2578 * 05-24-00 00.10.02 Added SenseBufferLength to _MSG_SCSI_IO_REPLY. 2579 * 06-06-00 01.00.01 Update version number for 1.0 release. 2580 * 06-08-00 01.00.02 Added MPI_SCSI_RSP_INFO_ definitions. 2581 * 11-02-00 01.01.01 Original release for post 1.0 work. 2582 * 12-04-00 01.01.02 Added MPI_SCSIIO_CONTROL_NO_DISCONNECT. 2583 * 02-20-01 01.01.03 Started using MPI_POINTER. 2584 * 03-27-01 01.01.04 Added structure offset comments. 2585 * 04-10-01 01.01.05 Added new MsgFlag for MSG_SCSI_TASK_MGMT. 2586 * 08-08-01 01.02.01 Original release for v1.2 work. 2587 * 08-29-01 01.02.02 Added MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET. 2588 * Added MPI_SCSI_STATE_QUEUE_TAG_REJECTED for 2589 * MSG_SCSI_IO_REPLY. 2590 * 09-28-01 01.02.03 Added structures and defines for SCSI Enclosure 2591 * Processor messages. 2592 * 10-04-01 01.02.04 Added defines for SEP request Action field. 2593 * -------------------------------------------------------------------------- 2594 */ 2595 2596 #ifndef MPI_INIT_H 2597 #define MPI_INIT_H 2598 2599 2600 /***************************************************************************** 2601 * 2602 * S C S I I n i t i a t o r M e s s a g e s 2603 * 2604 *****************************************************************************/ 2605 2606 /****************************************************************************/ 2607 /* SCSI IO messages and assocaited structures */ 2608 /****************************************************************************/ 2609 2610 typedef struct _MSG_SCSI_IO_REQUEST 2611 { 2612 U8 TargetID; /* 00h */ 2613 U8 Bus; /* 01h */ 2614 U8 ChainOffset; /* 02h */ 2615 U8 Function; /* 03h */ 2616 U8 CDBLength; /* 04h */ 2617 U8 SenseBufferLength; /* 05h */ 2618 U8 Reserved; /* 06h */ 2619 U8 MsgFlags; /* 07h */ 2620 U32 MsgContext; /* 08h */ 2621 U8 LUN[8]; /* 0Ch */ 2622 U32 Control; /* 14h */ 2623 U8 CDB[16]; /* 18h */ 2624 U32 DataLength; /* 28h */ 2625 U32 SenseBufferLowAddr; /* 2Ch */ 2626 SGE_IO_UNION SGL; /* 30h */ 2627 } MSG_SCSI_IO_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_REQUEST, 2628 SCSIIORequest_t, MPI_POINTER pSCSIIORequest_t; 2629 2630 2631 /* SCSIO MsgFlags bits */ 2632 2633 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) 2634 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) 2635 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) 2636 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) 2637 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) 2638 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) 2639 2640 /* SCSIIO LUN fields */ 2641 2642 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 2643 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 2644 #define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 2645 #define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 2646 #define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00) 2647 #define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00) 2648 2649 /* SCSIO Control bits */ 2650 2651 #define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 2652 #define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 2653 #define MPI_SCSIIO_CONTROL_WRITE (0x01000000) 2654 #define MPI_SCSIIO_CONTROL_READ (0x02000000) 2655 2656 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000) 2657 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 2658 2659 #define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 2660 #define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 2661 #define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100) 2662 #define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 2663 #define MPI_SCSIIO_CONTROL_ACAQ (0x00000400) 2664 #define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500) 2665 #define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700) 2666 2667 #define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000) 2668 #define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000) 2669 #define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000) 2670 #define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000) 2671 #define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000) 2672 #define MPI_SCSIIO_CONTROL_RESERVED (0x00080000) 2673 #define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000) 2674 #define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000) 2675 #define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000) 2676 2677 2678 /* SCSIIO reply structure */ 2679 typedef struct _MSG_SCSI_IO_REPLY 2680 { 2681 U8 TargetID; /* 00h */ 2682 U8 Bus; /* 01h */ 2683 U8 MsgLength; /* 02h */ 2684 U8 Function; /* 03h */ 2685 U8 CDBLength; /* 04h */ 2686 U8 SenseBufferLength; /* 05h */ 2687 U8 Reserved; /* 06h */ 2688 U8 MsgFlags; /* 07h */ 2689 U32 MsgContext; /* 08h */ 2690 U8 SCSIStatus; /* 0Ch */ 2691 U8 SCSIState; /* 0Dh */ 2692 U16 IOCStatus; /* 0Eh */ 2693 U32 IOCLogInfo; /* 10h */ 2694 U32 TransferCount; /* 14h */ 2695 U32 SenseCount; /* 18h */ 2696 U32 ResponseInfo; /* 1Ch */ 2697 } MSG_SCSI_IO_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_REPLY, 2698 SCSIIOReply_t, MPI_POINTER pSCSIIOReply_t; 2699 2700 2701 /* SCSIIO Reply SCSIStatus values (SAM-2 status codes) */ 2702 2703 #define MPI_SCSI_STATUS_SUCCESS (0x00) 2704 #define MPI_SCSI_STATUS_CHECK_CONDITION (0x02) 2705 #define MPI_SCSI_STATUS_CONDITION_MET (0x04) 2706 #define MPI_SCSI_STATUS_BUSY (0x08) 2707 #define MPI_SCSI_STATUS_INTERMEDIATE (0x10) 2708 #define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) 2709 #define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18) 2710 #define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22) 2711 #define MPI_SCSI_STATUS_TASK_SET_FULL (0x28) 2712 #define MPI_SCSI_STATUS_ACA_ACTIVE (0x30) 2713 2714 2715 /* SCSIIO Reply SCSIState values */ 2716 2717 #define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01) 2718 #define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02) 2719 #define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04) 2720 #define MPI_SCSI_STATE_TERMINATED (0x08) 2721 #define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10) 2722 #define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20) 2723 2724 /* SCSIIO Reply ResponseInfo values */ 2725 /* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */ 2726 2727 #define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000) 2728 #define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000) 2729 #define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000) 2730 #define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000) 2731 #define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000) 2732 #define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000) 2733 #define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000) 2734 2735 2736 /****************************************************************************/ 2737 /* SCSI Task Management messages */ 2738 /****************************************************************************/ 2739 2740 typedef struct _MSG_SCSI_TASK_MGMT 2741 { 2742 U8 TargetID; /* 00h */ 2743 U8 Bus; /* 01h */ 2744 U8 ChainOffset; /* 02h */ 2745 U8 Function; /* 03h */ 2746 U8 Reserved; /* 04h */ 2747 U8 TaskType; /* 05h */ 2748 U8 Reserved1; /* 06h */ 2749 U8 MsgFlags; /* 07h */ 2750 U32 MsgContext; /* 08h */ 2751 U8 LUN[8]; /* 0Ch */ 2752 U32 Reserved2[7]; /* 14h */ 2753 U32 TaskMsgContext; /* 30h */ 2754 } MSG_SCSI_TASK_MGMT, MPI_POINTER PTR_SCSI_TASK_MGMT, 2755 SCSITaskMgmt_t, MPI_POINTER pSCSITaskMgmt_t; 2756 2757 /* TaskType values */ 2758 2759 #define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 2760 #define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 2761 #define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 2762 #define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04) 2763 #define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 2764 2765 /* MsgFlags bits */ 2766 #define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00) 2767 #define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02) 2768 #define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04) 2769 2770 /* SCSI Task Management Reply */ 2771 typedef struct _MSG_SCSI_TASK_MGMT_REPLY 2772 { 2773 U8 TargetID; /* 00h */ 2774 U8 Bus; /* 01h */ 2775 U8 MsgLength; /* 02h */ 2776 U8 Function; /* 03h */ 2777 U8 Reserved; /* 04h */ 2778 U8 TaskType; /* 05h */ 2779 U8 Reserved1; /* 06h */ 2780 U8 MsgFlags; /* 07h */ 2781 U32 MsgContext; /* 08h */ 2782 U8 Reserved2[2]; /* 0Ch */ 2783 U16 IOCStatus; /* 0Eh */ 2784 U32 IOCLogInfo; /* 10h */ 2785 U32 TerminationCount; /* 14h */ 2786 } MSG_SCSI_TASK_MGMT_REPLY, MPI_POINTER PTR_MSG_SCSI_TASK_MGMT_REPLY, 2787 SCSITaskMgmtReply_t, MPI_POINTER pSCSITaskMgmtReply_t; 2788 2789 2790 /****************************************************************************/ 2791 /* SCSI Enclosure Processor messages */ 2792 /****************************************************************************/ 2793 2794 typedef struct _MSG_SEP_REQUEST 2795 { 2796 U8 TargetID; /* 00h */ 2797 U8 Bus; /* 01h */ 2798 U8 ChainOffset; /* 02h */ 2799 U8 Function; /* 03h */ 2800 U8 Action; /* 04h */ 2801 U8 Reserved1; /* 05h */ 2802 U8 Reserved2; /* 06h */ 2803 U8 MsgFlags; /* 07h */ 2804 U32 MsgContext; /* 08h */ 2805 U32 SlotStatus; /* 0Ch */ 2806 } MSG_SEP_REQUEST, MPI_POINTER PTR_MSG_SEP_REQUEST, 2807 SEPRequest_t, MPI_POINTER pSEPRequest_t; 2808 2809 /* Action defines */ 2810 #define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00) 2811 #define MPI_SEP_REQ_ACTION_READ_STATUS (0x01) 2812 2813 /* SlotStatus bits for MSG_SEP_REQUEST */ 2814 #define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) 2815 #define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) 2816 #define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) 2817 #define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 2818 #define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 2819 #define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020) 2820 #define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 2821 #define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) 2822 #define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) 2823 #define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 2824 #define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 2825 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) 2826 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000) 2827 #define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000) 2828 #define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 2829 #define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 2830 #define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000) 2831 #define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000) 2832 2833 2834 typedef struct _MSG_SEP_REPLY 2835 { 2836 U8 TargetID; /* 00h */ 2837 U8 Bus; /* 01h */ 2838 U8 MsgLength; /* 02h */ 2839 U8 Function; /* 03h */ 2840 U8 Action; /* 04h */ 2841 U8 Reserved1; /* 05h */ 2842 U8 Reserved2; /* 06h */ 2843 U8 MsgFlags; /* 07h */ 2844 U32 MsgContext; /* 08h */ 2845 U16 Reserved3; /* 0Ch */ 2846 U16 IOCStatus; /* 0Eh */ 2847 U32 IOCLogInfo; /* 10h */ 2848 U32 SlotStatus; /* 14h */ 2849 } MSG_SEP_REPLY, MPI_POINTER PTR_MSG_SEP_REPLY, 2850 SEPReply_t, MPI_POINTER pSEPReply_t; 2851 2852 /* SlotStatus bits for MSG_SEP_REPLY */ 2853 #define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) 2854 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) 2855 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) 2856 #define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 2857 #define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 2858 #define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020) 2859 #define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 2860 #define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) 2861 #define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) 2862 #define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 2863 #define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000) 2864 #define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 2865 #define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) 2866 #define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000) 2867 #define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 2868 #define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000) 2869 #define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000) 2870 #define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 2871 #define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 2872 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000) 2873 #define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000) 2874 #define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000) 2875 2876 #endif 2877 2878 /* 2879 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2880 * 2881 * Redistribution and use in source and binary forms, with or without 2882 * modification, are permitted provided that the following conditions 2883 * are met: 2884 * 1. Redistributions of source code must retain the above copyright 2885 * notice immediately at the beginning of the file, without modification, 2886 * this list of conditions, and the following disclaimer. 2887 * 2. The name of the author may not be used to endorse or promote products 2888 * derived from this software without specific prior written permission. 2889 * 2890 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2891 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2892 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2893 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2894 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2895 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2896 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2897 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2898 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2899 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2900 * SUCH DAMAGE. 2901 * 2902 * 2903 * Name: MPI_IOC.H 2904 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 2905 * Creation Date: August 11, 2000 2906 * 2907 * MPI Version: 01.02.04 2908 * 2909 * Version History 2910 * --------------- 2911 * 2912 * Date Version Description 2913 * -------- -------- ------------------------------------------------------ 2914 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2915 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. 2916 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. 2917 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. 2918 * Added _MSG_EVENT_ACK_REPLY structure. 2919 * Added _MSG_FW_DOWNLOAD_REPLY structure. 2920 * Added _MSG_TOOLBOX_REPLY structure. 2921 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. 2922 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, 2923 * _LINK_STATUS, _LOOP_STATE and _LOGOUT. 2924 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in 2925 * _MSG_EVENT_ACK_REPLY structure to match specification. 2926 * 11-02-00 01.01.01 Original release for post 1.0 work. 2927 * Added a value for Manufacturer to WhoInit. 2928 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and 2929 * removed toolbox message. 2930 * 01-09-01 01.01.03 Added event enabled and disabled defines. 2931 * Added structures for FwHeader and DataHeader. 2932 * Added ImageType to FwUpload reply. 2933 * 02-20-01 01.01.04 Started using MPI_POINTER. 2934 * 02-27-01 01.01.05 Added event for RAID status change and its event data. 2935 * Added IocNumber field to MSG_IOC_FACTS_REPLY. 2936 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. 2937 * Added structure offset comments. 2938 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. 2939 * 08-08-01 01.02.01 Original release for v1.2 work. 2940 * New format for FWVersion and ProductId in 2941 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. 2942 * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and 2943 * related structure and defines. 2944 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. 2945 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. 2946 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with 2947 * IOCExceptions and changed DataImageSize to reserved. 2948 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and 2949 * MPI_FW_UPLOAD_ITYPE_NVDATA. 2950 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. 2951 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. 2952 * -------------------------------------------------------------------------- 2953 */ 2954 2955 #ifndef MPI_IOC_H 2956 #define MPI_IOC_H 2957 2958 2959 /***************************************************************************** 2960 * 2961 * I O C M e s s a g e s 2962 * 2963 *****************************************************************************/ 2964 2965 /****************************************************************************/ 2966 /* IOCInit message */ 2967 /****************************************************************************/ 2968 2969 typedef struct _MSG_IOC_INIT 2970 { 2971 U8 WhoInit; /* 00h */ 2972 U8 Reserved; /* 01h */ 2973 U8 ChainOffset; /* 02h */ 2974 U8 Function; /* 03h */ 2975 U8 Flags; /* 04h */ 2976 U8 MaxDevices; /* 05h */ 2977 U8 MaxBuses; /* 06h */ 2978 U8 MsgFlags; /* 07h */ 2979 U32 MsgContext; /* 08h */ 2980 U16 ReplyFrameSize; /* 0Ch */ 2981 U8 Reserved1[2]; /* 0Eh */ 2982 U32 HostMfaHighAddr; /* 10h */ 2983 U32 SenseBufferHighAddr; /* 14h */ 2984 } MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, 2985 IOCInit_t, MPI_POINTER pIOCInit_t; 2986 2987 /* WhoInit values */ 2988 #define MPI_WHOINIT_NO_ONE (0x00) 2989 #define MPI_WHOINIT_SYSTEM_BIOS (0x01) 2990 #define MPI_WHOINIT_ROM_BIOS (0x02) 2991 #define MPI_WHOINIT_PCI_PEER (0x03) 2992 #define MPI_WHOINIT_HOST_DRIVER (0x04) 2993 #define MPI_WHOINIT_MANUFACTURER (0x05) 2994 2995 /* Flags values */ 2996 #define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) 2997 2998 typedef struct _MSG_IOC_INIT_REPLY 2999 { 3000 U8 WhoInit; /* 00h */ 3001 U8 Reserved; /* 01h */ 3002 U8 MsgLength; /* 02h */ 3003 U8 Function; /* 03h */ 3004 U8 Flags; /* 04h */ 3005 U8 MaxDevices; /* 05h */ 3006 U8 MaxBuses; /* 06h */ 3007 U8 MsgFlags; /* 07h */ 3008 U32 MsgContext; /* 08h */ 3009 U16 Reserved2; /* 0Ch */ 3010 U16 IOCStatus; /* 0Eh */ 3011 U32 IOCLogInfo; /* 10h */ 3012 } MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, 3013 IOCInitReply_t, MPI_POINTER pIOCInitReply_t; 3014 3015 3016 3017 /****************************************************************************/ 3018 /* IOC Facts message */ 3019 /****************************************************************************/ 3020 3021 typedef struct _MSG_IOC_FACTS 3022 { 3023 U8 Reserved[2]; /* 00h */ 3024 U8 ChainOffset; /* 01h */ 3025 U8 Function; /* 02h */ 3026 U8 Reserved1[3]; /* 03h */ 3027 U8 MsgFlags; /* 04h */ 3028 U32 MsgContext; /* 08h */ 3029 } MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, 3030 IOCFacts_t, MPI_POINTER pIOCFacts_t; 3031 3032 typedef struct _MPI_FW_VERSION_STRUCT 3033 { 3034 U8 Dev; /* 00h */ 3035 U8 Unit; /* 01h */ 3036 U8 Minor; /* 02h */ 3037 U8 Major; /* 03h */ 3038 } MPI_FW_VERSION_STRUCT; 3039 3040 typedef union _MPI_FW_VERSION 3041 { 3042 MPI_FW_VERSION_STRUCT Struct; 3043 U32 Word; 3044 } MPI_FW_VERSION; 3045 3046 /* IOC Facts Reply */ 3047 typedef struct _MSG_IOC_FACTS_REPLY 3048 { 3049 U16 MsgVersion; /* 00h */ 3050 U8 MsgLength; /* 02h */ 3051 U8 Function; /* 03h */ 3052 U16 Reserved; /* 04h */ 3053 U8 IOCNumber; /* 06h */ 3054 U8 MsgFlags; /* 07h */ 3055 U32 MsgContext; /* 08h */ 3056 U16 IOCExceptions; /* 0Ch */ 3057 U16 IOCStatus; /* 0Eh */ 3058 U32 IOCLogInfo; /* 10h */ 3059 U8 MaxChainDepth; /* 14h */ 3060 U8 WhoInit; /* 15h */ 3061 U8 BlockSize; /* 16h */ 3062 U8 Flags; /* 17h */ 3063 U16 ReplyQueueDepth; /* 18h */ 3064 U16 RequestFrameSize; /* 1Ah */ 3065 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ 3066 U16 ProductID; /* 1Eh */ 3067 U32 CurrentHostMfaHighAddr; /* 20h */ 3068 U16 GlobalCredits; /* 24h */ 3069 U8 NumberOfPorts; /* 26h */ 3070 U8 EventState; /* 27h */ 3071 U32 CurrentSenseBufferHighAddr; /* 28h */ 3072 U16 CurReplyFrameSize; /* 2Ch */ 3073 U8 MaxDevices; /* 2Eh */ 3074 U8 MaxBuses; /* 2Fh */ 3075 U32 FWImageSize; /* 30h */ 3076 U32 Reserved4; /* 34h */ 3077 MPI_FW_VERSION FWVersion; /* 38h */ 3078 } MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, 3079 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; 3080 3081 #define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 3082 #define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 3083 3084 #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 3085 3086 #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) 3087 3088 #define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) 3089 #define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) 3090 3091 3092 3093 /***************************************************************************** 3094 * 3095 * P o r t M e s s a g e s 3096 * 3097 *****************************************************************************/ 3098 3099 /****************************************************************************/ 3100 /* Port Facts message and Reply */ 3101 /****************************************************************************/ 3102 3103 typedef struct _MSG_PORT_FACTS 3104 { 3105 U8 Reserved[2]; /* 00h */ 3106 U8 ChainOffset; /* 02h */ 3107 U8 Function; /* 03h */ 3108 U8 Reserved1[2]; /* 04h */ 3109 U8 PortNumber; /* 06h */ 3110 U8 MsgFlags; /* 07h */ 3111 U32 MsgContext; /* 08h */ 3112 } MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, 3113 PortFacts_t, MPI_POINTER pPortFacts_t; 3114 3115 typedef struct _MSG_PORT_FACTS_REPLY 3116 { 3117 U16 Reserved; /* 00h */ 3118 U8 MsgLength; /* 02h */ 3119 U8 Function; /* 03h */ 3120 U16 Reserved1; /* 04h */ 3121 U8 PortNumber; /* 06h */ 3122 U8 MsgFlags; /* 07h */ 3123 U32 MsgContext; /* 08h */ 3124 U16 Reserved2; /* 0Ch */ 3125 U16 IOCStatus; /* 0Eh */ 3126 U32 IOCLogInfo; /* 10h */ 3127 U8 Reserved3; /* 14h */ 3128 U8 PortType; /* 15h */ 3129 U16 MaxDevices; /* 16h */ 3130 U16 PortSCSIID; /* 18h */ 3131 U16 ProtocolFlags; /* 1Ah */ 3132 U16 MaxPostedCmdBuffers; /* 1Ch */ 3133 U16 MaxPersistentIDs; /* 1Eh */ 3134 U16 MaxLanBuckets; /* 20h */ 3135 U16 Reserved4; /* 22h */ 3136 U32 Reserved5; /* 24h */ 3137 } MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, 3138 PortFactsReply_t, MPI_POINTER pPortFactsReply_t; 3139 3140 3141 /* PortTypes values */ 3142 3143 #define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) 3144 #define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) 3145 #define MPI_PORTFACTS_PORTTYPE_FC (0x10) 3146 3147 /* ProtocolFlags values */ 3148 3149 #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) 3150 #define MPI_PORTFACTS_PROTOCOL_LAN (0x02) 3151 #define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) 3152 #define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) 3153 3154 3155 /****************************************************************************/ 3156 /* Port Enable Message */ 3157 /****************************************************************************/ 3158 3159 typedef struct _MSG_PORT_ENABLE 3160 { 3161 U8 Reserved[2]; /* 00h */ 3162 U8 ChainOffset; /* 02h */ 3163 U8 Function; /* 03h */ 3164 U8 Reserved1[2]; /* 04h */ 3165 U8 PortNumber; /* 06h */ 3166 U8 MsgFlags; /* 07h */ 3167 U32 MsgContext; /* 08h */ 3168 } MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, 3169 PortEnable_t, MPI_POINTER pPortEnable_t; 3170 3171 typedef struct _MSG_PORT_ENABLE_REPLY 3172 { 3173 U8 Reserved[2]; /* 00h */ 3174 U8 MsgLength; /* 02h */ 3175 U8 Function; /* 03h */ 3176 U8 Reserved1[2]; /* 04h */ 3177 U8 PortNumber; /* 05h */ 3178 U8 MsgFlags; /* 07h */ 3179 U32 MsgContext; /* 08h */ 3180 U16 Reserved2; /* 0Ch */ 3181 U16 IOCStatus; /* 0Eh */ 3182 U32 IOCLogInfo; /* 10h */ 3183 } MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, 3184 PortEnableReply_t, MPI_POINTER pPortEnableReply_t; 3185 3186 3187 /***************************************************************************** 3188 * 3189 * E v e n t M e s s a g e s 3190 * 3191 *****************************************************************************/ 3192 3193 /****************************************************************************/ 3194 /* Event Notification messages */ 3195 /****************************************************************************/ 3196 3197 typedef struct _MSG_EVENT_NOTIFY 3198 { 3199 U8 Switch; /* 00h */ 3200 U8 Reserved; /* 01h */ 3201 U8 ChainOffset; /* 02h */ 3202 U8 Function; /* 03h */ 3203 U8 Reserved1[3]; /* 04h */ 3204 U8 MsgFlags; /* 07h */ 3205 U32 MsgContext; /* 08h */ 3206 } MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, 3207 EventNotification_t, MPI_POINTER pEventNotification_t; 3208 3209 /* Event Notification Reply */ 3210 3211 typedef struct _MSG_EVENT_NOTIFY_REPLY 3212 { 3213 U16 EventDataLength; /* 00h */ 3214 U8 MsgLength; /* 02h */ 3215 U8 Function; /* 03h */ 3216 U8 Reserved1[2]; /* 04h */ 3217 U8 AckRequired; /* 06h */ 3218 U8 MsgFlags; /* 07h */ 3219 U32 MsgContext; /* 08h */ 3220 U8 Reserved2[2]; /* 0Ch */ 3221 U16 IOCStatus; /* 0Eh */ 3222 U32 IOCLogInfo; /* 10h */ 3223 U32 Event; /* 14h */ 3224 U32 EventContext; /* 18h */ 3225 U32 Data[1]; /* 1Ch */ 3226 } MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, 3227 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; 3228 3229 /* Event Acknowledge */ 3230 3231 typedef struct _MSG_EVENT_ACK 3232 { 3233 U8 Reserved[2]; /* 00h */ 3234 U8 ChainOffset; /* 02h */ 3235 U8 Function; /* 03h */ 3236 U8 Reserved1[3]; /* 04h */ 3237 U8 MsgFlags; /* 07h */ 3238 U32 MsgContext; /* 08h */ 3239 U32 Event; /* 0Ch */ 3240 U32 EventContext; /* 10h */ 3241 } MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, 3242 EventAck_t, MPI_POINTER pEventAck_t; 3243 3244 typedef struct _MSG_EVENT_ACK_REPLY 3245 { 3246 U8 Reserved[2]; /* 00h */ 3247 U8 MsgLength; /* 02h */ 3248 U8 Function; /* 03h */ 3249 U8 Reserved1[3]; /* 04h */ 3250 U8 MsgFlags; /* 07h */ 3251 U32 MsgContext; /* 08h */ 3252 U16 Reserved2; /* 0Ch */ 3253 U16 IOCStatus; /* 0Eh */ 3254 U32 IOCLogInfo; /* 10h */ 3255 } MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, 3256 EventAckReply_t, MPI_POINTER pEventAckReply_t; 3257 3258 /* Switch */ 3259 3260 #define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) 3261 #define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) 3262 3263 /* Event */ 3264 3265 #define MPI_EVENT_NONE (0x00000000) 3266 #define MPI_EVENT_LOG_DATA (0x00000001) 3267 #define MPI_EVENT_STATE_CHANGE (0x00000002) 3268 #define MPI_EVENT_UNIT_ATTENTION (0x00000003) 3269 #define MPI_EVENT_IOC_BUS_RESET (0x00000004) 3270 #define MPI_EVENT_EXT_BUS_RESET (0x00000005) 3271 #define MPI_EVENT_RESCAN (0x00000006) 3272 #define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) 3273 #define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) 3274 #define MPI_EVENT_LOGOUT (0x00000009) 3275 #define MPI_EVENT_EVENT_CHANGE (0x0000000A) 3276 #define MPI_EVENT_INTEGRATED_RAID (0x0000000B) 3277 #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) 3278 #define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) 3279 3280 /* AckRequired field values */ 3281 3282 #define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 3283 #define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 3284 3285 /* EventChange Event data */ 3286 3287 typedef struct _EVENT_DATA_EVENT_CHANGE 3288 { 3289 U8 EventState; /* 00h */ 3290 U8 Reserved; /* 01h */ 3291 U16 Reserved1; /* 02h */ 3292 } EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, 3293 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; 3294 3295 /* SCSI Event data for Port, Bus and Device forms */ 3296 3297 typedef struct _EVENT_DATA_SCSI 3298 { 3299 U8 TargetID; /* 00h */ 3300 U8 BusPort; /* 01h */ 3301 U16 Reserved; /* 02h */ 3302 } EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, 3303 EventDataScsi_t, MPI_POINTER pEventDataScsi_t; 3304 3305 /* SCSI Device Status Change Event data */ 3306 3307 typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE 3308 { 3309 U8 TargetID; /* 00h */ 3310 U8 Bus; /* 01h */ 3311 U8 ReasonCode; /* 02h */ 3312 U8 LUN; /* 03h */ 3313 U8 ASC; /* 04h */ 3314 U8 ASCQ; /* 05h */ 3315 U16 Reserved; /* 06h */ 3316 } EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 3317 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 3318 MpiEventDataScsiDeviceStatusChange_t, 3319 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; 3320 3321 /* MPI SCSI Device Status Change Event data ReasonCode values */ 3322 #define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) 3323 #define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) 3324 #define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) 3325 3326 /* MPI Link Status Change Event data */ 3327 3328 typedef struct _EVENT_DATA_LINK_STATUS 3329 { 3330 U8 State; /* 00h */ 3331 U8 Reserved; /* 01h */ 3332 U16 Reserved1; /* 02h */ 3333 U8 Reserved2; /* 04h */ 3334 U8 Port; /* 05h */ 3335 U16 Reserved3; /* 06h */ 3336 } EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, 3337 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; 3338 3339 #define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) 3340 #define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) 3341 3342 /* MPI Loop State Change Event data */ 3343 3344 typedef struct _EVENT_DATA_LOOP_STATE 3345 { 3346 U8 Character4; /* 00h */ 3347 U8 Character3; /* 01h */ 3348 U8 Type; /* 02h */ 3349 U8 Reserved; /* 03h */ 3350 U8 Reserved1; /* 04h */ 3351 U8 Port; /* 05h */ 3352 U16 Reserved2; /* 06h */ 3353 } EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, 3354 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; 3355 3356 #define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) 3357 #define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) 3358 #define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) 3359 3360 /* MPI LOGOUT Event data */ 3361 3362 typedef struct _EVENT_DATA_LOGOUT 3363 { 3364 U32 NPortID; /* 00h */ 3365 U8 Reserved; /* 04h */ 3366 U8 Port; /* 05h */ 3367 U16 Reserved1; /* 06h */ 3368 } EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, 3369 EventDataLogout_t, MPI_POINTER pEventDataLogout_t; 3370 3371 /* MPI Integrated RAID Event data */ 3372 3373 typedef struct _EVENT_DATA_RAID 3374 { 3375 U8 VolumeID; /* 00h */ 3376 U8 VolumeBus; /* 01h */ 3377 U8 ReasonCode; /* 02h */ 3378 U8 PhysDiskNum; /* 03h */ 3379 U8 ASC; /* 04h */ 3380 U8 ASCQ; /* 05h */ 3381 U16 Reserved; /* 06h */ 3382 U32 SettingsStatus; /* 08h */ 3383 } EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, 3384 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; 3385 3386 /* MPI Integrated RAID Event data ReasonCode values */ 3387 #define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) 3388 #define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) 3389 #define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) 3390 #define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) 3391 #define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) 3392 #define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) 3393 #define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) 3394 #define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) 3395 #define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) 3396 #define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) 3397 #define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) 3398 #define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) 3399 3400 3401 /***************************************************************************** 3402 * 3403 * F i r m w a r e L o a d M e s s a g e s 3404 * 3405 *****************************************************************************/ 3406 3407 /****************************************************************************/ 3408 /* Firmware Download message and associated structures */ 3409 /****************************************************************************/ 3410 3411 typedef struct _MSG_FW_DOWNLOAD 3412 { 3413 U8 ImageType; /* 00h */ 3414 U8 Reserved; /* 01h */ 3415 U8 ChainOffset; /* 02h */ 3416 U8 Function; /* 03h */ 3417 U8 Reserved1[3]; /* 04h */ 3418 U8 MsgFlags; /* 07h */ 3419 U32 MsgContext; /* 08h */ 3420 SGE_MPI_UNION SGL; /* 0Ch */ 3421 } MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, 3422 FWDownload_t, MPI_POINTER pFWDownload_t; 3423 3424 #define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) 3425 #define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) 3426 #define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) 3427 #define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) 3428 3429 3430 typedef struct _FWDownloadTCSGE 3431 { 3432 U8 Reserved; /* 00h */ 3433 U8 ContextSize; /* 01h */ 3434 U8 DetailsLength; /* 02h */ 3435 U8 Flags; /* 03h */ 3436 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ 3437 U32 ImageOffset; /* 08h */ 3438 U32 ImageSize; /* 0Ch */ 3439 } FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, 3440 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; 3441 3442 /* Firmware Download reply */ 3443 typedef struct _MSG_FW_DOWNLOAD_REPLY 3444 { 3445 U8 ImageType; /* 00h */ 3446 U8 Reserved; /* 01h */ 3447 U8 MsgLength; /* 02h */ 3448 U8 Function; /* 03h */ 3449 U8 Reserved1[3]; /* 04h */ 3450 U8 MsgFlags; /* 07h */ 3451 U32 MsgContext; /* 08h */ 3452 U16 Reserved2; /* 0Ch */ 3453 U16 IOCStatus; /* 0Eh */ 3454 U32 IOCLogInfo; /* 10h */ 3455 } MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, 3456 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; 3457 3458 3459 /****************************************************************************/ 3460 /* Firmware Upload message and associated structures */ 3461 /****************************************************************************/ 3462 3463 typedef struct _MSG_FW_UPLOAD 3464 { 3465 U8 ImageType; /* 00h */ 3466 U8 Reserved; /* 01h */ 3467 U8 ChainOffset; /* 02h */ 3468 U8 Function; /* 03h */ 3469 U8 Reserved1[3]; /* 04h */ 3470 U8 MsgFlags; /* 07h */ 3471 U32 MsgContext; /* 08h */ 3472 SGE_MPI_UNION SGL; /* 0Ch */ 3473 } MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, 3474 FWUpload_t, MPI_POINTER pFWUpload_t; 3475 3476 #define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) 3477 #define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 3478 #define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 3479 #define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) 3480 3481 typedef struct _FWUploadTCSGE 3482 { 3483 U8 Reserved; /* 00h */ 3484 U8 ContextSize; /* 01h */ 3485 U8 DetailsLength; /* 02h */ 3486 U8 Flags; /* 03h */ 3487 U32 Reserved1; /* 04h */ 3488 U32 ImageOffset; /* 08h */ 3489 U32 ImageSize; /* 0Ch */ 3490 } FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, 3491 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; 3492 3493 /* Firmware Upload reply */ 3494 typedef struct _MSG_FW_UPLOAD_REPLY 3495 { 3496 U8 ImageType; /* 00h */ 3497 U8 Reserved; /* 01h */ 3498 U8 MsgLength; /* 02h */ 3499 U8 Function; /* 03h */ 3500 U8 Reserved1[3]; /* 04h */ 3501 U8 MsgFlags; /* 07h */ 3502 U32 MsgContext; /* 08h */ 3503 U16 Reserved2; /* 0Ch */ 3504 U16 IOCStatus; /* 0Eh */ 3505 U32 IOCLogInfo; /* 10h */ 3506 U32 ActualImageSize; /* 14h */ 3507 } MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, 3508 FWUploadReply_t, MPI_POINTER pFWUploadReply_t; 3509 3510 3511 typedef struct _MPI_FW_HEADER 3512 { 3513 U32 ArmBranchInstruction0; /* 00h */ 3514 U32 Signature0; /* 04h */ 3515 U32 Signature1; /* 08h */ 3516 U32 Signature2; /* 0Ch */ 3517 U32 ArmBranchInstruction1; /* 10h */ 3518 U32 ArmBranchInstruction2; /* 14h */ 3519 U32 Reserved; /* 18h */ 3520 U32 Checksum; /* 1Ch */ 3521 U16 VendorId; /* 20h */ 3522 U16 ProductId; /* 22h */ 3523 MPI_FW_VERSION FWVersion; /* 24h */ 3524 U32 SeqCodeVersion; /* 28h */ 3525 U32 ImageSize; /* 2Ch */ 3526 U32 NextImageHeaderOffset; /* 30h */ 3527 U32 LoadStartAddress; /* 34h */ 3528 U32 IopResetVectorValue; /* 38h */ 3529 U32 IopResetRegAddr; /* 3Ch */ 3530 U32 VersionNameWhat; /* 40h */ 3531 U8 VersionName[32]; /* 44h */ 3532 U32 VendorNameWhat; /* 64h */ 3533 U8 VendorName[32]; /* 68h */ 3534 } MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, 3535 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; 3536 3537 #define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) 3538 3539 /* defines for using the ProductId field */ 3540 #define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) 3541 #define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) 3542 #define MPI_FW_HEADER_PID_TYPE_FC (0x1000) 3543 3544 #define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) 3545 #define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) 3546 #define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 3547 #define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) 3548 #define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) 3549 #define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) 3550 #define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) 3551 3552 #define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) 3553 #define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) 3554 #define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) 3555 #define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) 3556 #define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) 3557 #define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) 3558 #define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) 3559 #define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) 3560 #define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) 3561 #define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) 3562 #define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) 3563 #define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) 3564 #define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) 3565 #define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) 3566 3567 typedef struct _MPI_EXT_IMAGE_HEADER 3568 { 3569 U8 ImageType; /* 00h */ 3570 U8 Reserved; /* 01h */ 3571 U16 Reserved1; /* 02h */ 3572 U32 Checksum; /* 04h */ 3573 U32 ImageSize; /* 08h */ 3574 U32 NextImageHeaderOffset; /* 0Ch */ 3575 U32 LoadStartAddress; /* 10h */ 3576 U32 Reserved2; /* 14h */ 3577 } MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, 3578 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; 3579 3580 /* defines for the ImageType field */ 3581 #define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 3582 #define MPI_EXT_IMAGE_TYPE_FW (0x01) 3583 #define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) 3584 3585 #endif 3586 3587 /* 3588 * Copyright (c) 2000, 2001 by LSI Logic Corporation 3589 * 3590 * Redistribution and use in source and binary forms, with or without 3591 * modification, are permitted provided that the following conditions 3592 * are met: 3593 * 1. Redistributions of source code must retain the above copyright 3594 * notice immediately at the beginning of the file, without modification, 3595 * this list of conditions, and the following disclaimer. 3596 * 2. The name of the author may not be used to endorse or promote products 3597 * derived from this software without specific prior written permission. 3598 * 3599 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 3600 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 3601 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 3602 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 3603 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3604 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3605 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3606 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3607 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3608 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3609 * SUCH DAMAGE. 3610 * 3611 * 3612 * Name: MPI_LAN.H 3613 * Title: MPI LAN messages and structures 3614 * Creation Date: June 30, 2000 3615 * 3616 * MPI Version: 01.02.01 3617 * 3618 * Version History 3619 * --------------- 3620 * 3621 * Date Version Description 3622 * -------- -------- ------------------------------------------------------ 3623 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 3624 * 05-24-00 00.10.02 Added LANStatus field to _MSG_LAN_SEND_REPLY. 3625 * Added LANStatus field to _MSG_LAN_RECEIVE_POST_REPLY. 3626 * Moved ListCount field in _MSG_LAN_RECEIVE_POST_REPLY. 3627 * 06-06-00 01.00.01 Update version number for 1.0 release. 3628 * 06-12-00 01.00.02 Added MPI_ to BUCKETSTATUS_ definitions. 3629 * 06-22-00 01.00.03 Major changes to match new LAN definition in 1.0 spec. 3630 * 06-30-00 01.00.04 Added Context Reply definitions per revised proposal. 3631 * Changed transaction context usage to bucket/buffer. 3632 * 07-05-00 01.00.05 Removed LAN_RECEIVE_POST_BUCKET_CONTEXT_MASK definition 3633 * to lan private header file 3634 * 11-02-00 01.01.01 Original release for post 1.0 work 3635 * 02-20-01 01.01.02 Started using MPI_POINTER. 3636 * 03-27-01 01.01.03 Added structure offset comments. 3637 * 08-08-01 01.02.01 Original release for v1.2 work. 3638 * -------------------------------------------------------------------------- 3639 */ 3640 3641 #ifndef MPI_LAN_H 3642 #define MPI_LAN_H 3643 3644 3645 /****************************************************************************** 3646 * 3647 * L A N M e s s a g e s 3648 * 3649 *******************************************************************************/ 3650 3651 /* LANSend messages */ 3652 3653 typedef struct _MSG_LAN_SEND_REQUEST 3654 { 3655 U16 Reserved; /* 00h */ 3656 U8 ChainOffset; /* 02h */ 3657 U8 Function; /* 03h */ 3658 U16 Reserved2; /* 04h */ 3659 U8 PortNumber; /* 06h */ 3660 U8 MsgFlags; /* 07h */ 3661 U32 MsgContext; /* 08h */ 3662 SGE_MPI_UNION SG_List[1]; /* 0Ch */ 3663 } MSG_LAN_SEND_REQUEST, MPI_POINTER PTR_MSG_LAN_SEND_REQUEST, 3664 LANSendRequest_t, MPI_POINTER pLANSendRequest_t; 3665 3666 3667 typedef struct _MSG_LAN_SEND_REPLY 3668 { 3669 U16 Reserved; /* 00h */ 3670 U8 MsgLength; /* 02h */ 3671 U8 Function; /* 03h */ 3672 U8 Reserved2; /* 04h */ 3673 U8 NumberOfContexts; /* 05h */ 3674 U8 PortNumber; /* 06h */ 3675 U8 MsgFlags; /* 07h */ 3676 U32 MsgContext; /* 08h */ 3677 U16 Reserved3; /* 0Ch */ 3678 U16 IOCStatus; /* 0Eh */ 3679 U32 IOCLogInfo; /* 10h */ 3680 U32 BufferContext; /* 14h */ 3681 } MSG_LAN_SEND_REPLY, MPI_POINTER PTR_MSG_LAN_SEND_REPLY, 3682 LANSendReply_t, MPI_POINTER pLANSendReply_t; 3683 3684 3685 /* LANReceivePost */ 3686 3687 typedef struct _MSG_LAN_RECEIVE_POST_REQUEST 3688 { 3689 U16 Reserved; /* 00h */ 3690 U8 ChainOffset; /* 02h */ 3691 U8 Function; /* 03h */ 3692 U16 Reserved2; /* 04h */ 3693 U8 PortNumber; /* 06h */ 3694 U8 MsgFlags; /* 07h */ 3695 U32 MsgContext; /* 08h */ 3696 U32 BucketCount; /* 0Ch */ 3697 SGE_MPI_UNION SG_List[1]; /* 10h */ 3698 } MSG_LAN_RECEIVE_POST_REQUEST, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REQUEST, 3699 LANReceivePostRequest_t, MPI_POINTER pLANReceivePostRequest_t; 3700 3701 3702 typedef struct _MSG_LAN_RECEIVE_POST_REPLY 3703 { 3704 U16 Reserved; /* 00h */ 3705 U8 MsgLength; /* 02h */ 3706 U8 Function; /* 03h */ 3707 U8 Reserved2; /* 04h */ 3708 U8 NumberOfContexts; /* 05h */ 3709 U8 PortNumber; /* 06h */ 3710 U8 MsgFlags; /* 07h */ 3711 U32 MsgContext; /* 08h */ 3712 U16 Reserved3; /* 0Ch */ 3713 U16 IOCStatus; /* 0Eh */ 3714 U32 IOCLogInfo; /* 10h */ 3715 U32 BucketsRemaining; /* 14h */ 3716 U32 PacketOffset; /* 18h */ 3717 U32 PacketLength; /* 1Ch */ 3718 U32 BucketContext[1]; /* 20h */ 3719 } MSG_LAN_RECEIVE_POST_REPLY, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REPLY, 3720 LANReceivePostReply_t, MPI_POINTER pLANReceivePostReply_t; 3721 3722 3723 /* LANReset */ 3724 3725 typedef struct _MSG_LAN_RESET_REQUEST 3726 { 3727 U16 Reserved; /* 00h */ 3728 U8 ChainOffset; /* 02h */ 3729 U8 Function; /* 03h */ 3730 U16 Reserved2; /* 04h */ 3731 U8 PortNumber; /* 05h */ 3732 U8 MsgFlags; /* 07h */ 3733 U32 MsgContext; /* 08h */ 3734 } MSG_LAN_RESET_REQUEST, MPI_POINTER PTR_MSG_LAN_RESET_REQUEST, 3735 LANResetRequest_t, MPI_POINTER pLANResetRequest_t; 3736 3737 3738 typedef struct _MSG_LAN_RESET_REPLY 3739 { 3740 U16 Reserved; /* 00h */ 3741 U8 MsgLength; /* 02h */ 3742 U8 Function; /* 03h */ 3743 U16 Reserved2; /* 04h */ 3744 U8 PortNumber; /* 06h */ 3745 U8 MsgFlags; /* 07h */ 3746 U32 MsgContext; /* 08h */ 3747 U16 Reserved3; /* 0Ch */ 3748 U16 IOCStatus; /* 0Eh */ 3749 U32 IOCLogInfo; /* 10h */ 3750 } MSG_LAN_RESET_REPLY, MPI_POINTER PTR_MSG_LAN_RESET_REPLY, 3751 LANResetReply_t, MPI_POINTER pLANResetReply_t; 3752 3753 3754 /****************************************************************************/ 3755 /* LAN Context Reply defines and macros */ 3756 /****************************************************************************/ 3757 3758 #define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF) 3759 #define LAN_REPLY_PACKET_LENGTH_SHIFT (0) 3760 #define LAN_REPLY_BUCKET_CONTEXT_MASK (0x07FF0000) 3761 #define LAN_REPLY_BUCKET_CONTEXT_SHIFT (16) 3762 #define LAN_REPLY_BUFFER_CONTEXT_MASK (0x07FFFFFF) 3763 #define LAN_REPLY_BUFFER_CONTEXT_SHIFT (0) 3764 #define LAN_REPLY_FORM_MASK (0x18000000) 3765 #define LAN_REPLY_FORM_RECEIVE_SINGLE (0x00) 3766 #define LAN_REPLY_FORM_RECEIVE_MULTIPLE (0x01) 3767 #define LAN_REPLY_FORM_SEND_SINGLE (0x02) 3768 #define LAN_REPLY_FORM_MESSAGE_CONTEXT (0x03) 3769 #define LAN_REPLY_FORM_SHIFT (27) 3770 3771 #define GET_LAN_PACKET_LENGTH(x) (((x) & LAN_REPLY_PACKET_LENGTH_MASK) \ 3772 >> LAN_REPLY_PACKET_LENGTH_SHIFT) 3773 3774 #define SET_LAN_PACKET_LENGTH(x, lth) \ 3775 ((x) = ((x) & ~LAN_REPLY_PACKET_LENGTH_MASK) | \ 3776 (((lth) << LAN_REPLY_PACKET_LENGTH_SHIFT) & \ 3777 LAN_REPLY_PACKET_LENGTH_MASK)) 3778 3779 #define GET_LAN_BUCKET_CONTEXT(x) (((x) & LAN_REPLY_BUCKET_CONTEXT_MASK) \ 3780 >> LAN_REPLY_BUCKET_CONTEXT_SHIFT) 3781 3782 #define SET_LAN_BUCKET_CONTEXT(x, ctx) \ 3783 ((x) = ((x) & ~LAN_REPLY_BUCKET_CONTEXT_MASK) | \ 3784 (((ctx) << LAN_REPLY_BUCKET_CONTEXT_SHIFT) & \ 3785 LAN_REPLY_BUCKET_CONTEXT_MASK)) 3786 3787 #define GET_LAN_BUFFER_CONTEXT(x) (((x) & LAN_REPLY_BUFFER_CONTEXT_MASK) \ 3788 >> LAN_REPLY_BUFFER_CONTEXT_SHIFT) 3789 3790 #define SET_LAN_BUFFER_CONTEXT(x, ctx) \ 3791 ((x) = ((x) & ~LAN_REPLY_BUFFER_CONTEXT_MASK) | \ 3792 (((ctx) << LAN_REPLY_BUFFER_CONTEXT_SHIFT) & \ 3793 LAN_REPLY_BUFFER_CONTEXT_MASK)) 3794 3795 #define GET_LAN_FORM(x) (((x) & LAN_REPLY_FORM_MASK) \ 3796 >> LAN_REPLY_FORM_SHIFT) 3797 3798 #define SET_LAN_FORM(x, frm) \ 3799 ((x) = ((x) & ~LAN_REPLY_FORM_MASK) | \ 3800 (((frm) << LAN_REPLY_FORM_SHIFT) & \ 3801 LAN_REPLY_FORM_MASK)) 3802 3803 3804 /****************************************************************************/ 3805 /* LAN Current Device State defines */ 3806 /****************************************************************************/ 3807 3808 #define MPI_LAN_DEVICE_STATE_RESET (0x00) 3809 #define MPI_LAN_DEVICE_STATE_OPERATIONAL (0x01) 3810 3811 3812 /****************************************************************************/ 3813 /* LAN Loopback defines */ 3814 /****************************************************************************/ 3815 3816 #define MPI_LAN_TX_MODES_ENABLE_LOOPBACK_SUPPRESSION (0x01) 3817 3818 #endif 3819 3820 3821 /* 3822 * Copyright (c) 2000, 2001 by LSI Logic Corporation 3823 * 3824 * Redistribution and use in source and binary forms, with or without 3825 * modification, are permitted provided that the following conditions 3826 * are met: 3827 * 1. Redistributions of source code must retain the above copyright 3828 * notice immediately at the beginning of the file, without modification, 3829 * this list of conditions, and the following disclaimer. 3830 * 2. The name of the author may not be used to endorse or promote products 3831 * derived from this software without specific prior written permission. 3832 * 3833 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 3834 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 3835 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 3836 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 3837 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3838 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3839 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3840 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3841 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3842 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3843 * SUCH DAMAGE. 3844 * 3845 * 3846 * Name: MPI_TARG.H 3847 * Title: MPI Target mode messages and structures 3848 * Creation Date: June 22, 2000 3849 * 3850 * MPI Version: 01.02.04 3851 * 3852 * Version History 3853 * --------------- 3854 * 3855 * Date Version Description 3856 * -------- -------- ------------------------------------------------------ 3857 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 3858 * 06-06-00 01.00.01 Update version number for 1.0 release. 3859 * 06-22-00 01.00.02 Added _MSG_TARGET_CMD_BUFFER_POST_REPLY structure. 3860 * Corrected DECSRIPTOR typo to DESCRIPTOR. 3861 * 11-02-00 01.01.01 Original release for post 1.0 work 3862 * Modified target mode to use IoIndex instead of 3863 * HostIndex and IocIndex. Added Alias. 3864 * 01-09-01 01.01.02 Added defines for TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER 3865 * and TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER. 3866 * 02-20-01 01.01.03 Started using MPI_POINTER. 3867 * Added structures for MPI_TARGET_SCSI_SPI_CMD_BUFFER and 3868 * MPI_TARGET_FCP_CMD_BUFFER. 3869 * 03-27-01 01.01.04 Added structure offset comments. 3870 * 08-08-01 01.02.01 Original release for v1.2 work. 3871 * 09-28-01 01.02.02 Added structure for MPI_TARGET_SCSI_SPI_STATUS_IU. 3872 * Added PriorityReason field to some replies and 3873 * defined more PriorityReason codes. 3874 * Added some defines for to support previous version 3875 * of MPI. 3876 * 10-04-01 01.02.03 Added PriorityReason to MSG_TARGET_ERROR_REPLY. 3877 * 11-01-01 01.02.04 Added define for TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY. 3878 * -------------------------------------------------------------------------- 3879 */ 3880 3881 #ifndef MPI_TARG_H 3882 #define MPI_TARG_H 3883 3884 3885 /****************************************************************************** 3886 * 3887 * S C S I T a r g e t M e s s a g e s 3888 * 3889 *******************************************************************************/ 3890 3891 typedef struct _CMD_BUFFER_DESCRIPTOR 3892 { 3893 U16 IoIndex; /* 00h */ 3894 U16 Reserved; /* 02h */ 3895 union /* 04h */ 3896 { 3897 U32 PhysicalAddress32; 3898 U64 PhysicalAddress64; 3899 } _u; 3900 } CMD_BUFFER_DESCRIPTOR, MPI_POINTER PTR_CMD_BUFFER_DESCRIPTOR, 3901 CmdBufferDescriptor_t, MPI_POINTER pCmdBufferDescriptor_t; 3902 3903 3904 /****************************************************************************/ 3905 /* Target Command Buffer Post Request */ 3906 /****************************************************************************/ 3907 3908 typedef struct _MSG_TARGET_CMD_BUFFER_POST_REQUEST 3909 { 3910 U8 BufferPostFlags; /* 00h */ 3911 U8 BufferCount; /* 01h */ 3912 U8 ChainOffset; /* 02h */ 3913 U8 Function; /* 03h */ 3914 U8 BufferLength; /* 04h */ 3915 U8 Reserved; /* 05h */ 3916 U8 Reserved1; /* 06h */ 3917 U8 MsgFlags; /* 07h */ 3918 U32 MsgContext; /* 08h */ 3919 CMD_BUFFER_DESCRIPTOR Buffer[1]; /* 0Ch */ 3920 } MSG_TARGET_CMD_BUFFER_POST_REQUEST, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REQUEST, 3921 TargetCmdBufferPostRequest_t, MPI_POINTER pTargetCmdBufferPostRequest_t; 3922 3923 #define CMD_BUFFER_POST_FLAGS_PORT_MASK (0x01) 3924 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_MASK (0x80) 3925 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_32 (0) 3926 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_64 (1) 3927 #define CMD_BUFFER_POST_FLAGS_64_BIT_ADDR (0x80) 3928 3929 #define CMD_BUFFER_POST_IO_INDEX_MASK (0x00003FFF) 3930 #define CMD_BUFFER_POST_IO_INDEX_MASK_0100 (0x000003FF) /* obsolete */ 3931 3932 3933 typedef struct _MSG_TARGET_CMD_BUFFER_POST_REPLY 3934 { 3935 U8 BufferPostFlags; /* 00h */ 3936 U8 BufferCount; /* 01h */ 3937 U8 MsgLength; /* 02h */ 3938 U8 Function; /* 03h */ 3939 U8 BufferLength; /* 04h */ 3940 U8 Reserved; /* 05h */ 3941 U8 Reserved1; /* 06h */ 3942 U8 MsgFlags; /* 07h */ 3943 U32 MsgContext; /* 08h */ 3944 U16 Reserved2; /* 0Ch */ 3945 U16 IOCStatus; /* 0Eh */ 3946 U32 IOCLogInfo; /* 10h */ 3947 } MSG_TARGET_CMD_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REPLY, 3948 TargetCmdBufferPostReply_t, MPI_POINTER pTargetCmdBufferPostReply_t; 3949 3950 /* the following structure is obsolete as of MPI v1.2 */ 3951 typedef struct _MSG_PRIORITY_CMD_RECEIVED_REPLY 3952 { 3953 U16 Reserved; /* 00h */ 3954 U8 MsgLength; /* 02h */ 3955 U8 Function; /* 03h */ 3956 U16 Reserved1; /* 04h */ 3957 U8 Reserved2; /* 06h */ 3958 U8 MsgFlags; /* 07h */ 3959 U32 MsgContext; /* 08h */ 3960 U8 PriorityReason; /* 0Ch */ 3961 U8 Reserved3; /* 0Dh */ 3962 U16 IOCStatus; /* 0Eh */ 3963 U32 IOCLogInfo; /* 10h */ 3964 U32 ReplyWord; /* 14h */ 3965 } MSG_PRIORITY_CMD_RECEIVED_REPLY, MPI_POINTER PTR_MSG_PRIORITY_CMD_RECEIVED_REPLY, 3966 PriorityCommandReceivedReply_t, MPI_POINTER pPriorityCommandReceivedReply_t; 3967 3968 #define PRIORITY_REASON_NO_DISCONNECT (0x00) 3969 #define PRIORITY_REASON_SCSI_TASK_MANAGEMENT (0x01) 3970 #define PRIORITY_REASON_CMD_PARITY_ERR (0x02) 3971 #define PRIORITY_REASON_MSG_OUT_PARITY_ERR (0x03) 3972 #define PRIORITY_REASON_LQ_CRC_ERR (0x04) 3973 #define PRIORITY_REASON_CMD_CRC_ERR (0x05) 3974 #define PRIORITY_REASON_PROTOCOL_ERR (0x06) 3975 #define PRIORITY_REASON_DATA_OUT_PARITY_ERR (0x07) 3976 #define PRIORITY_REASON_DATA_OUT_CRC_ERR (0x08) 3977 #define PRIORITY_REASON_UNKNOWN (0xFF) 3978 3979 3980 typedef struct _MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY 3981 { 3982 U16 Reserved; /* 00h */ 3983 U8 MsgLength; /* 02h */ 3984 U8 Function; /* 03h */ 3985 U16 Reserved1; /* 04h */ 3986 U8 Reserved2; /* 06h */ 3987 U8 MsgFlags; /* 07h */ 3988 U32 MsgContext; /* 08h */ 3989 U8 PriorityReason; /* 0Ch */ 3990 U8 Reserved3; /* 0Dh */ 3991 U16 IOCStatus; /* 0Eh */ 3992 U32 IOCLogInfo; /* 10h */ 3993 U32 ReplyWord; /* 14h */ 3994 } MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, 3995 MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, 3996 TargetCmdBufferPostErrorReply_t, MPI_POINTER pTargetCmdBufferPostErrorReply_t; 3997 3998 3999 typedef struct _MPI_TARGET_FCP_CMD_BUFFER 4000 { 4001 U8 FcpLun[8]; /* 00h */ 4002 U8 FcpCntl[4]; /* 08h */ 4003 U8 FcpCdb[16]; /* 0Ch */ 4004 U32 FcpDl; /* 1Ch */ 4005 } MPI_TARGET_FCP_CMD_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_CMD_BUFFER, 4006 MpiTargetFcpCmdBuffer, MPI_POINTER pMpiTargetFcpCmdBuffer; 4007 4008 4009 typedef struct _MPI_TARGET_SCSI_SPI_CMD_BUFFER 4010 { 4011 /* SPI L_Q information unit */ 4012 U8 L_QType; /* 00h */ 4013 U8 Reserved; /* 01h */ 4014 U16 Tag; /* 02h */ 4015 U8 LogicalUnitNumber[8]; /* 04h */ 4016 U32 DataLength; /* 0Ch */ 4017 /* SPI command information unit */ 4018 U8 ReservedFirstByteOfCommandIU; /* 10h */ 4019 U8 TaskAttribute; /* 11h */ 4020 U8 TaskManagementFlags; /* 12h */ 4021 U8 AdditionalCDBLength; /* 13h */ 4022 U8 CDB[16]; /* 14h */ 4023 } MPI_TARGET_SCSI_SPI_CMD_BUFFER, 4024 MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_CMD_BUFFER, 4025 MpiTargetScsiSpiCmdBuffer, MPI_POINTER pMpiTargetScsiSpiCmdBuffer; 4026 4027 4028 /****************************************************************************/ 4029 /* Target Assist Request */ 4030 /****************************************************************************/ 4031 4032 typedef struct _MSG_TARGET_ASSIST_REQUEST 4033 { 4034 U8 StatusCode; /* 00h */ 4035 U8 TargetAssistFlags; /* 01h */ 4036 U8 ChainOffset; /* 02h */ 4037 U8 Function; /* 03h */ 4038 U16 QueueTag; /* 04h */ 4039 U8 Reserved; /* 06h */ 4040 U8 MsgFlags; /* 07h */ 4041 U32 MsgContext; /* 08h */ 4042 U32 ReplyWord; /* 0Ch */ 4043 U8 LUN[8]; /* 10h */ 4044 U32 RelativeOffset; /* 18h */ 4045 U32 DataLength; /* 1Ch */ 4046 SGE_IO_UNION SGL[1]; /* 20h */ 4047 } MSG_TARGET_ASSIST_REQUEST, MPI_POINTER PTR_MSG_TARGET_ASSIST_REQUEST, 4048 TargetAssistRequest_t, MPI_POINTER pTargetAssistRequest_t; 4049 4050 #define TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01) 4051 #define TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02) 4052 #define TARGET_ASSIST_FLAGS_HIGH_PRIORITY (0x04) 4053 #define TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80) 4054 4055 4056 typedef struct _MSG_TARGET_ERROR_REPLY 4057 { 4058 U16 Reserved; /* 00h */ 4059 U8 MsgLength; /* 02h */ 4060 U8 Function; /* 03h */ 4061 U16 Reserved1; /* 04h */ 4062 U8 Reserved2; /* 06h */ 4063 U8 MsgFlags; /* 07h */ 4064 U32 MsgContext; /* 08h */ 4065 U8 PriorityReason; /* 0Ch */ 4066 U8 Reserved3; /* 0Dh */ 4067 U16 IOCStatus; /* 0Eh */ 4068 U32 IOCLogInfo; /* 10h */ 4069 U32 ReplyWord; /* 14h */ 4070 U32 TransferCount; /* 18h */ 4071 } MSG_TARGET_ERROR_REPLY, MPI_POINTER PTR_MSG_TARGET_ERROR_REPLY, 4072 TargetErrorReply_t, MPI_POINTER pTargetErrorReply_t; 4073 4074 4075 /****************************************************************************/ 4076 /* Target Status Send Request */ 4077 /****************************************************************************/ 4078 4079 typedef struct _MSG_TARGET_STATUS_SEND_REQUEST 4080 { 4081 U8 StatusCode; /* 00h */ 4082 U8 StatusFlags; /* 01h */ 4083 U8 ChainOffset; /* 02h */ 4084 U8 Function; /* 03h */ 4085 U16 QueueTag; /* 04h */ 4086 U8 Reserved; /* 06h */ 4087 U8 MsgFlags; /* 07h */ 4088 U32 MsgContext; /* 08h */ 4089 U32 ReplyWord; /* 0Ch */ 4090 U8 LUN[8]; /* 10h */ 4091 SGE_SIMPLE_UNION StatusDataSGE; /* 18h */ 4092 } MSG_TARGET_STATUS_SEND_REQUEST, MPI_POINTER PTR_MSG_TARGET_STATUS_SEND_REQUEST, 4093 TargetStatusSendRequest_t, MPI_POINTER pTargetStatusSendRequest_t; 4094 4095 #define TARGET_STATUS_SEND_FLAGS_AUTO_GOOD_STATUS (0x01) 4096 #define TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY (0x04) 4097 #define TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER (0x80) 4098 4099 typedef struct _MPI_TARGET_FCP_RSP_BUFFER 4100 { 4101 U8 Reserved0[8]; /* 00h */ 4102 U8 FcpStatus; /* 08h */ 4103 U8 FcpFlags; /* 09h */ 4104 U8 Reserved1[2]; /* 0Ah */ 4105 U32 FcpResid; /* 0Ch */ 4106 U32 FcpSenseLength; /* 10h */ 4107 U32 FcpResponseLength; /* 14h */ 4108 U8 FcpResponseData[8]; /* 18h */ 4109 U8 FcpSenseData[32]; /* Pad to 64 bytes */ /* 20h */ 4110 } MPI_TARGET_FCP_RSP_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_RSP_BUFFER, 4111 MpiTargetFcpRspBuffer, MPI_POINTER pMpiTargetFcpRspBuffer; 4112 4113 typedef struct _MPI_TARGET_SCSI_SPI_STATUS_IU 4114 { 4115 U8 Reserved0; /* 00h */ 4116 U8 Reserved1; /* 01h */ 4117 U8 Valid; /* 02h */ 4118 U8 Status; /* 03h */ 4119 U32 SenseDataListLength; /* 04h */ 4120 U32 PktFailuresListLength; /* 08h */ 4121 U8 SenseData[52]; /* Pad the IU to 64 bytes */ /* 0Ch */ 4122 } MPI_TARGET_SCSI_SPI_STATUS_IU, MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_STATUS_IU, 4123 TargetScsiSpiStatusIU_t, MPI_POINTER pTargetScsiSpiStatusIU_t; 4124 4125 /****************************************************************************/ 4126 /* Target Mode Abort Request */ 4127 /****************************************************************************/ 4128 4129 typedef struct _MSG_TARGET_MODE_ABORT_REQUEST 4130 { 4131 U8 AbortType; /* 00h */ 4132 U8 Reserved; /* 01h */ 4133 U8 ChainOffset; /* 02h */ 4134 U8 Function; /* 03h */ 4135 U16 Reserved1; /* 04h */ 4136 U8 Reserved2; /* 06h */ 4137 U8 MsgFlags; /* 07h */ 4138 U32 MsgContext; /* 08h */ 4139 U32 ReplyWord; /* 0Ch */ 4140 U32 MsgContextToAbort; /* 10h */ 4141 } MSG_TARGET_MODE_ABORT, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT, 4142 TargetModeAbort_t, MPI_POINTER pTargetModeAbort_t; 4143 4144 #define TARGET_MODE_ABORT_TYPE_ALL_CMD_BUFFERS (0x00) 4145 #define TARGET_MODE_ABORT_TYPE_ALL_IO (0x01) 4146 #define TARGET_MODE_ABORT_TYPE_EXACT_IO (0x02) 4147 #define TARGET_MODE_ABORT_TYPE_EXACT_IO_REQUEST (0x03) 4148 4149 /* Target Mode Abort Reply */ 4150 4151 typedef struct _MSG_TARGET_MODE_ABORT_REPLY 4152 { 4153 U16 Reserved; /* 00h */ 4154 U8 MsgLength; /* 02h */ 4155 U8 Function; /* 03h */ 4156 U16 Reserved1; /* 04h */ 4157 U8 Reserved2; /* 06h */ 4158 U8 MsgFlags; /* 07h */ 4159 U32 MsgContext; /* 08h */ 4160 U16 Reserved3; /* 0Ch */ 4161 U16 IOCStatus; /* 0Eh */ 4162 U32 IOCLogInfo; /* 10h */ 4163 U32 AbortCount; /* 14h */ 4164 } MSG_TARGET_MODE_ABORT_REPLY, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT_REPLY, 4165 TargetModeAbortReply_t, MPI_POINTER pTargetModeAbortReply_t; 4166 4167 4168 /****************************************************************************/ 4169 /* Target Mode Context Reply */ 4170 /****************************************************************************/ 4171 4172 #define TARGET_MODE_REPLY_IO_INDEX_MASK (0x00003FFF) 4173 #define TARGET_MODE_REPLY_IO_INDEX_SHIFT (0) 4174 #define TARGET_MODE_REPLY_INITIATOR_INDEX_MASK (0x03FFC000) 4175 #define TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT (14) 4176 #define TARGET_MODE_REPLY_ALIAS_MASK (0x0C000000) 4177 #define TARGET_MODE_REPLY_ALIAS_SHIFT (26) 4178 #define TARGET_MODE_REPLY_PORT_MASK (0x10000000) 4179 #define TARGET_MODE_REPLY_PORT_SHIFT (28) 4180 4181 4182 #define GET_IO_INDEX(x) (((x) & TARGET_MODE_REPLY_IO_INDEX_MASK) \ 4183 >> TARGET_MODE_REPLY_IO_INDEX_SHIFT) 4184 4185 #define SET_IO_INDEX(t, i) \ 4186 ((t) = ((t) & ~TARGET_MODE_REPLY_IO_INDEX_MASK) | \ 4187 (((i) << TARGET_MODE_REPLY_IO_INDEX_SHIFT) & \ 4188 TARGET_MODE_REPLY_IO_INDEX_MASK)) 4189 4190 #define GET_INITIATOR_INDEX(x) (((x) & TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) \ 4191 >> TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) 4192 4193 #define SET_INITIATOR_INDEX(t, ii) \ 4194 ((t) = ((t) & ~TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) | \ 4195 (((ii) << TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) & \ 4196 TARGET_MODE_REPLY_INITIATOR_INDEX_MASK)) 4197 4198 #define GET_ALIAS(x) (((x) & TARGET_MODE_REPLY_ALIAS_MASK) \ 4199 >> TARGET_MODE_REPLY_ALIAS_SHIFT) 4200 4201 #define SET_ALIAS(t, a) ((t) = ((t) & ~TARGET_MODE_REPLY_ALIAS_MASK) | \ 4202 (((a) << TARGET_MODE_REPLY_ALIAS_SHIFT) & \ 4203 TARGET_MODE_REPLY_ALIAS_MASK)) 4204 4205 #define GET_PORT(x) (((x) & TARGET_MODE_REPLY_PORT_MASK) \ 4206 >> TARGET_MODE_REPLY_PORT_SHIFT) 4207 4208 #define SET_PORT(t, p) ((t) = ((t) & ~TARGET_MODE_REPLY_PORT_MASK) | \ 4209 (((p) << TARGET_MODE_REPLY_PORT_SHIFT) & \ 4210 TARGET_MODE_REPLY_PORT_MASK)) 4211 4212 /* the following obsolete values are for MPI v1.0 support */ 4213 #define TARGET_MODE_REPLY_0100_MASK_HOST_INDEX (0x000003FF) 4214 #define TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX (0) 4215 #define TARGET_MODE_REPLY_0100_MASK_IOC_INDEX (0x001FF800) 4216 #define TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX (11) 4217 #define TARGET_MODE_REPLY_0100_PORT_MASK (0x00400000) 4218 #define TARGET_MODE_REPLY_0100_PORT_SHIFT (22) 4219 #define TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX (0x1F800000) 4220 #define TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX (23) 4221 4222 #define GET_HOST_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) \ 4223 >> TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) 4224 4225 #define SET_HOST_INDEX_0100(t, hi) \ 4226 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) | \ 4227 (((hi) << TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) & \ 4228 TARGET_MODE_REPLY_0100_MASK_HOST_INDEX)) 4229 4230 #define GET_IOC_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) \ 4231 >> TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) 4232 4233 #define SET_IOC_INDEX_0100(t, ii) \ 4234 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) | \ 4235 (((ii) << TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) & \ 4236 TARGET_MODE_REPLY_0100_MASK_IOC_INDEX)) 4237 4238 #define GET_INITIATOR_INDEX_0100(x) \ 4239 (((x) & TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) \ 4240 >> TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) 4241 4242 #define SET_INITIATOR_INDEX_0100(t, ii) \ 4243 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) | \ 4244 (((ii) << TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) & \ 4245 TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX)) 4246 4247 4248 #endif 4249 4250
Indexes created Sat Sep 27 14:09:57 GMT 2025