mvsata.c revision 1.35 1 1.35 christos /* $NetBSD: mvsata.c,v 1.35 2016/05/02 19:18:29 christos Exp $ */
2 1.1 kiyohara /*
3 1.1 kiyohara * Copyright (c) 2008 KIYOHARA Takashi
4 1.1 kiyohara * All rights reserved.
5 1.1 kiyohara *
6 1.1 kiyohara * Redistribution and use in source and binary forms, with or without
7 1.1 kiyohara * modification, are permitted provided that the following conditions
8 1.1 kiyohara * are met:
9 1.1 kiyohara * 1. Redistributions of source code must retain the above copyright
10 1.1 kiyohara * notice, this list of conditions and the following disclaimer.
11 1.1 kiyohara * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 kiyohara * notice, this list of conditions and the following disclaimer in the
13 1.1 kiyohara * documentation and/or other materials provided with the distribution.
14 1.1 kiyohara *
15 1.1 kiyohara * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 1.1 kiyohara * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 1.1 kiyohara * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 1.1 kiyohara * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 1.1 kiyohara * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 1.1 kiyohara * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 1.1 kiyohara * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 1.1 kiyohara * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 1.1 kiyohara * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 1.1 kiyohara * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 1.1 kiyohara * POSSIBILITY OF SUCH DAMAGE.
26 1.1 kiyohara */
27 1.1 kiyohara
28 1.1 kiyohara #include <sys/cdefs.h>
29 1.35 christos __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.35 2016/05/02 19:18:29 christos Exp $");
30 1.1 kiyohara
31 1.1 kiyohara #include "opt_mvsata.h"
32 1.1 kiyohara
33 1.24 bouyer /* ATAPI implementation not finished. */
34 1.1 kiyohara //#include "atapibus.h"
35 1.1 kiyohara
36 1.1 kiyohara #include <sys/param.h>
37 1.1 kiyohara #if NATAPIBUS > 0
38 1.1 kiyohara #include <sys/buf.h>
39 1.1 kiyohara #endif
40 1.1 kiyohara #include <sys/bus.h>
41 1.1 kiyohara #include <sys/cpu.h>
42 1.1 kiyohara #include <sys/device.h>
43 1.1 kiyohara #include <sys/disklabel.h>
44 1.1 kiyohara #include <sys/errno.h>
45 1.1 kiyohara #include <sys/kernel.h>
46 1.1 kiyohara #include <sys/malloc.h>
47 1.1 kiyohara #include <sys/proc.h>
48 1.1 kiyohara
49 1.1 kiyohara #include <machine/vmparam.h>
50 1.1 kiyohara
51 1.1 kiyohara #include <dev/ata/atareg.h>
52 1.1 kiyohara #include <dev/ata/atavar.h>
53 1.1 kiyohara #include <dev/ic/wdcvar.h>
54 1.29 jakllsch #include <dev/ata/satapmpreg.h>
55 1.1 kiyohara #include <dev/ata/satareg.h>
56 1.1 kiyohara #include <dev/ata/satavar.h>
57 1.1 kiyohara
58 1.1 kiyohara #if NATAPIBUS > 0
59 1.1 kiyohara #include <dev/scsipi/scsi_all.h> /* for SCSI status */
60 1.1 kiyohara #endif
61 1.1 kiyohara
62 1.1 kiyohara #include <dev/pci/pcidevs.h>
63 1.1 kiyohara
64 1.1 kiyohara #include <dev/ic/mvsatareg.h>
65 1.1 kiyohara #include <dev/ic/mvsatavar.h>
66 1.1 kiyohara
67 1.1 kiyohara
68 1.1 kiyohara #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev)
69 1.1 kiyohara #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev)
70 1.1 kiyohara
71 1.1 kiyohara #define MVSATA_HC_READ_4(hc, reg) \
72 1.1 kiyohara bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg))
73 1.1 kiyohara #define MVSATA_HC_WRITE_4(hc, reg, val) \
74 1.1 kiyohara bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val))
75 1.1 kiyohara #define MVSATA_EDMA_READ_4(mvport, reg) \
76 1.1 kiyohara bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg))
77 1.1 kiyohara #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \
78 1.1 kiyohara bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val))
79 1.1 kiyohara #define MVSATA_WDC_READ_2(mvport, reg) \
80 1.24 bouyer bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \
81 1.24 bouyer SHADOW_REG_BLOCK_OFFSET + (reg))
82 1.1 kiyohara #define MVSATA_WDC_READ_1(mvport, reg) \
83 1.24 bouyer bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \
84 1.24 bouyer SHADOW_REG_BLOCK_OFFSET + (reg))
85 1.1 kiyohara #define MVSATA_WDC_WRITE_2(mvport, reg, val) \
86 1.24 bouyer bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \
87 1.24 bouyer SHADOW_REG_BLOCK_OFFSET + (reg), (val))
88 1.1 kiyohara #define MVSATA_WDC_WRITE_1(mvport, reg, val) \
89 1.24 bouyer bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \
90 1.24 bouyer SHADOW_REG_BLOCK_OFFSET + (reg), (val))
91 1.1 kiyohara
92 1.1 kiyohara #ifdef MVSATA_DEBUG
93 1.1 kiyohara #define DPRINTF(x) if (mvsata_debug) printf x
94 1.1 kiyohara #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x
95 1.10 jakllsch int mvsata_debug = 2;
96 1.1 kiyohara #else
97 1.1 kiyohara #define DPRINTF(x)
98 1.1 kiyohara #define DPRINTFN(n,x)
99 1.1 kiyohara #endif
100 1.1 kiyohara
101 1.1 kiyohara #define ATA_DELAY 10000 /* 10s for a drive I/O */
102 1.1 kiyohara #define ATAPI_DELAY 10 /* 10 ms, this is used only before
103 1.1 kiyohara sending a cmd */
104 1.2 snj #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */
105 1.1 kiyohara
106 1.1 kiyohara #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE))
107 1.1 kiyohara
108 1.1 kiyohara
109 1.32 kiyohara static void mvsata_probe_drive(struct ata_channel *);
110 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
111 1.1 kiyohara static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *);
112 1.24 bouyer static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *);
113 1.1 kiyohara static void mvsata_reset_channel(struct ata_channel *, int);
114 1.1 kiyohara static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *);
115 1.1 kiyohara static int mvsata_addref(struct ata_drive_datas *);
116 1.1 kiyohara static void mvsata_delref(struct ata_drive_datas *);
117 1.1 kiyohara static void mvsata_killpending(struct ata_drive_datas *);
118 1.1 kiyohara
119 1.1 kiyohara #if NATAPIBUS > 0
120 1.1 kiyohara static void mvsata_atapibus_attach(struct atabus_softc *);
121 1.1 kiyohara static void mvsata_atapi_scsipi_request(struct scsipi_channel *,
122 1.1 kiyohara scsipi_adapter_req_t, void *);
123 1.1 kiyohara static void mvsata_atapi_minphys(struct buf *);
124 1.1 kiyohara static void mvsata_atapi_probe_device(struct atapibus_softc *, int);
125 1.1 kiyohara static void mvsata_atapi_kill_pending(struct scsipi_periph *);
126 1.1 kiyohara #endif
127 1.1 kiyohara #endif
128 1.1 kiyohara
129 1.1 kiyohara static void mvsata_setup_channel(struct ata_channel *);
130 1.1 kiyohara
131 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
132 1.1 kiyohara static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *);
133 1.1 kiyohara static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int);
134 1.1 kiyohara static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
135 1.1 kiyohara static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *);
136 1.1 kiyohara static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int,
137 1.1 kiyohara int);
138 1.1 kiyohara static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *);
139 1.1 kiyohara static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int);
140 1.1 kiyohara static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *,
141 1.1 kiyohara int);
142 1.1 kiyohara static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *);
143 1.1 kiyohara static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *);
144 1.1 kiyohara #if NATAPIBUS > 0
145 1.1 kiyohara static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *);
146 1.1 kiyohara static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int);
147 1.1 kiyohara static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *,
148 1.1 kiyohara int);
149 1.1 kiyohara static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *);
150 1.1 kiyohara static void mvsata_atapi_phase_complete(struct ata_xfer *);
151 1.1 kiyohara static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *);
152 1.1 kiyohara static void mvsata_atapi_polldsc(void *);
153 1.1 kiyohara #endif
154 1.1 kiyohara
155 1.9 jakllsch static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_bio *, void *);
156 1.1 kiyohara static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *);
157 1.1 kiyohara static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int);
158 1.1 kiyohara static void mvsata_edma_timeout(void *);
159 1.1 kiyohara static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *);
160 1.1 kiyohara #if NATAPIBUS > 0
161 1.1 kiyohara static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *);
162 1.1 kiyohara static void mvsata_bdma_start(struct mvsata_port *);
163 1.1 kiyohara #endif
164 1.1 kiyohara #endif
165 1.1 kiyohara
166 1.1 kiyohara static int mvsata_port_init(struct mvsata_hc *, int);
167 1.1 kiyohara static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *);
168 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
169 1.1 kiyohara static inline void mvsata_quetag_init(struct mvsata_port *);
170 1.1 kiyohara static inline int mvsata_quetag_get(struct mvsata_port *);
171 1.1 kiyohara static inline void mvsata_quetag_put(struct mvsata_port *, int);
172 1.1 kiyohara static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t,
173 1.1 kiyohara bus_dmamap_t *, size_t, int);
174 1.1 kiyohara static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t,
175 1.1 kiyohara bus_dmamap_t, void *);
176 1.1 kiyohara static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int);
177 1.1 kiyohara static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int);
178 1.1 kiyohara #endif
179 1.1 kiyohara
180 1.1 kiyohara static void mvsata_hreset_port(struct mvsata_port *);
181 1.1 kiyohara static void mvsata_reset_port(struct mvsata_port *);
182 1.1 kiyohara static void mvsata_reset_hc(struct mvsata_hc *);
183 1.29 jakllsch static uint32_t mvsata_softreset(struct mvsata_port *, int);
184 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
185 1.1 kiyohara static void mvsata_edma_reset_qptr(struct mvsata_port *);
186 1.1 kiyohara static inline void mvsata_edma_enable(struct mvsata_port *);
187 1.1 kiyohara static int mvsata_edma_disable(struct mvsata_port *, int, int);
188 1.1 kiyohara static void mvsata_edma_config(struct mvsata_port *, int);
189 1.1 kiyohara
190 1.1 kiyohara static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int,
191 1.1 kiyohara struct ata_bio *);
192 1.1 kiyohara #endif
193 1.1 kiyohara static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *);
194 1.1 kiyohara static void mvsata_fix_phy_gen1(struct mvsata_port *);
195 1.1 kiyohara static void mvsata_devconn_gen1(struct mvsata_port *);
196 1.1 kiyohara
197 1.1 kiyohara static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *);
198 1.1 kiyohara static void mvsata_fix_phy_gen2(struct mvsata_port *);
199 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
200 1.1 kiyohara static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int,
201 1.1 kiyohara struct ata_bio *);
202 1.1 kiyohara
203 1.1 kiyohara #ifdef MVSATA_DEBUG
204 1.1 kiyohara static void mvsata_print_crqb(struct mvsata_port *, int);
205 1.1 kiyohara static void mvsata_print_crpb(struct mvsata_port *, int);
206 1.1 kiyohara static void mvsata_print_eprd(struct mvsata_port *, int);
207 1.1 kiyohara #endif
208 1.1 kiyohara
209 1.1 kiyohara struct ata_bustype mvsata_ata_bustype = {
210 1.1 kiyohara SCSIPI_BUSTYPE_ATA,
211 1.1 kiyohara mvsata_bio,
212 1.1 kiyohara mvsata_reset_drive,
213 1.1 kiyohara mvsata_reset_channel,
214 1.1 kiyohara mvsata_exec_command,
215 1.1 kiyohara ata_get_params,
216 1.1 kiyohara mvsata_addref,
217 1.1 kiyohara mvsata_delref,
218 1.1 kiyohara mvsata_killpending
219 1.1 kiyohara };
220 1.1 kiyohara
221 1.1 kiyohara #if NATAPIBUS > 0
222 1.1 kiyohara static const struct scsipi_bustype mvsata_atapi_bustype = {
223 1.1 kiyohara SCSIPI_BUSTYPE_ATAPI,
224 1.1 kiyohara atapi_scsipi_cmd,
225 1.1 kiyohara atapi_interpret_sense,
226 1.1 kiyohara atapi_print_addr,
227 1.1 kiyohara mvsata_atapi_kill_pending,
228 1.16 bouyer NULL,
229 1.1 kiyohara };
230 1.1 kiyohara #endif /* NATAPIBUS */
231 1.1 kiyohara #endif
232 1.1 kiyohara
233 1.29 jakllsch static void
234 1.29 jakllsch mvsata_pmp_select(struct mvsata_port *mvport, int pmpport)
235 1.29 jakllsch {
236 1.29 jakllsch uint32_t ifctl;
237 1.29 jakllsch
238 1.29 jakllsch KASSERT(pmpport < PMP_MAX_DRIVES);
239 1.29 jakllsch #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG)
240 1.29 jakllsch if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) {
241 1.29 jakllsch panic("EDMA enabled");
242 1.29 jakllsch }
243 1.29 jakllsch #endif
244 1.29 jakllsch
245 1.29 jakllsch ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL);
246 1.29 jakllsch ifctl &= ~0xf;
247 1.29 jakllsch ifctl |= pmpport;
248 1.29 jakllsch MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl);
249 1.29 jakllsch }
250 1.1 kiyohara
251 1.1 kiyohara int
252 1.5 kiyohara mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product,
253 1.1 kiyohara int (*mvsata_sreset)(struct mvsata_softc *),
254 1.1 kiyohara int (*mvsata_misc_reset)(struct mvsata_softc *),
255 1.1 kiyohara int read_pre_amps)
256 1.1 kiyohara {
257 1.1 kiyohara struct mvsata_hc *mvhc;
258 1.1 kiyohara struct mvsata_port *mvport;
259 1.1 kiyohara uint32_t (*read_preamps)(struct mvsata_port *) = NULL;
260 1.1 kiyohara void (*_fix_phy)(struct mvsata_port *) = NULL;
261 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
262 1.1 kiyohara void (*edma_setup_crqb)
263 1.1 kiyohara (struct mvsata_port *, int, int, struct ata_bio *) = NULL;
264 1.1 kiyohara #endif
265 1.5 kiyohara int hc, port, channel;
266 1.1 kiyohara
267 1.1 kiyohara aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n",
268 1.1 kiyohara (product->generation == gen1) ? "I" :
269 1.1 kiyohara ((product->generation == gen2) ? "II" : "IIe"),
270 1.1 kiyohara product->hc, product->port);
271 1.1 kiyohara
272 1.1 kiyohara
273 1.1 kiyohara switch (product->generation) {
274 1.1 kiyohara case gen1:
275 1.1 kiyohara mvsata_sreset = NULL;
276 1.1 kiyohara read_pre_amps = 1; /* MUST */
277 1.1 kiyohara read_preamps = mvsata_read_preamps_gen1;
278 1.1 kiyohara _fix_phy = mvsata_fix_phy_gen1;
279 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
280 1.1 kiyohara edma_setup_crqb = mvsata_edma_setup_crqb;
281 1.1 kiyohara #endif
282 1.1 kiyohara break;
283 1.1 kiyohara
284 1.1 kiyohara case gen2:
285 1.1 kiyohara read_preamps = mvsata_read_preamps_gen2;
286 1.1 kiyohara _fix_phy = mvsata_fix_phy_gen2;
287 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
288 1.1 kiyohara edma_setup_crqb = mvsata_edma_setup_crqb;
289 1.1 kiyohara #endif
290 1.1 kiyohara break;
291 1.1 kiyohara
292 1.1 kiyohara case gen2e:
293 1.1 kiyohara read_preamps = mvsata_read_preamps_gen2;
294 1.1 kiyohara _fix_phy = mvsata_fix_phy_gen2;
295 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
296 1.1 kiyohara edma_setup_crqb = mvsata_edma_setup_crqb_gen2e;
297 1.1 kiyohara #endif
298 1.1 kiyohara break;
299 1.1 kiyohara }
300 1.1 kiyohara
301 1.5 kiyohara sc->sc_gen = product->generation;
302 1.5 kiyohara sc->sc_hc = product->hc;
303 1.5 kiyohara sc->sc_port = product->port;
304 1.5 kiyohara sc->sc_flags = product->flags;
305 1.1 kiyohara
306 1.1 kiyohara #ifdef MVSATA_WITHOUTDMA
307 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
308 1.1 kiyohara #else
309 1.3 mbalmer sc->sc_edma_setup_crqb = edma_setup_crqb;
310 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_cap |=
311 1.1 kiyohara (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA);
312 1.1 kiyohara #endif
313 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
314 1.6 kiyohara #ifdef MVSATA_WITHOUTDMA
315 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_dma_cap = 0;
316 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
317 1.1 kiyohara #else
318 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
319 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
320 1.1 kiyohara #endif
321 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels;
322 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port;
323 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
324 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype;
325 1.1 kiyohara #if NATAPIBUS > 0
326 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach;
327 1.1 kiyohara #endif
328 1.1 kiyohara #endif
329 1.24 bouyer sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */
330 1.29 jakllsch sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive;
331 1.1 kiyohara sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel;
332 1.1 kiyohara
333 1.1 kiyohara sc->sc_wdc_regs =
334 1.1 kiyohara malloc(sizeof(struct wdc_regs) * product->hc * product->port,
335 1.1 kiyohara M_DEVBUF, M_NOWAIT);
336 1.1 kiyohara if (sc->sc_wdc_regs == NULL) {
337 1.1 kiyohara aprint_error_dev(MVSATA_DEV(sc),
338 1.1 kiyohara "can't allocate wdc regs memory\n");
339 1.1 kiyohara return ENOMEM;
340 1.1 kiyohara }
341 1.1 kiyohara sc->sc_wdcdev.regs = sc->sc_wdc_regs;
342 1.1 kiyohara
343 1.1 kiyohara for (hc = 0; hc < sc->sc_hc; hc++) {
344 1.1 kiyohara mvhc = &sc->sc_hcs[hc];
345 1.1 kiyohara mvhc->hc = hc;
346 1.1 kiyohara mvhc->hc_sc = sc;
347 1.1 kiyohara mvhc->hc_iot = sc->sc_iot;
348 1.1 kiyohara if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
349 1.1 kiyohara hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE,
350 1.1 kiyohara &mvhc->hc_ioh)) {
351 1.1 kiyohara aprint_error_dev(MVSATA_DEV(sc),
352 1.1 kiyohara "can't subregion SATAHC %d registers\n", hc);
353 1.1 kiyohara continue;
354 1.1 kiyohara }
355 1.1 kiyohara
356 1.1 kiyohara for (port = 0; port < sc->sc_port; port++)
357 1.1 kiyohara if (mvsata_port_init(mvhc, port) == 0) {
358 1.1 kiyohara int pre_amps;
359 1.1 kiyohara
360 1.1 kiyohara mvport = mvhc->hc_ports[port];
361 1.1 kiyohara pre_amps = read_pre_amps ?
362 1.1 kiyohara read_preamps(mvport) : 0x00000720;
363 1.1 kiyohara mvport->_fix_phy_param.pre_amps = pre_amps;
364 1.1 kiyohara mvport->_fix_phy_param._fix_phy = _fix_phy;
365 1.1 kiyohara
366 1.1 kiyohara if (!mvsata_sreset)
367 1.1 kiyohara mvsata_reset_port(mvport);
368 1.1 kiyohara }
369 1.1 kiyohara
370 1.1 kiyohara if (!mvsata_sreset)
371 1.1 kiyohara mvsata_reset_hc(mvhc);
372 1.1 kiyohara }
373 1.1 kiyohara if (mvsata_sreset)
374 1.1 kiyohara mvsata_sreset(sc);
375 1.1 kiyohara
376 1.1 kiyohara if (mvsata_misc_reset)
377 1.1 kiyohara mvsata_misc_reset(sc);
378 1.1 kiyohara
379 1.1 kiyohara for (hc = 0; hc < sc->sc_hc; hc++)
380 1.1 kiyohara for (port = 0; port < sc->sc_port; port++) {
381 1.1 kiyohara mvport = sc->sc_hcs[hc].hc_ports[port];
382 1.1 kiyohara if (mvport == NULL)
383 1.1 kiyohara continue;
384 1.1 kiyohara if (mvsata_sreset)
385 1.1 kiyohara mvport->_fix_phy_param._fix_phy(mvport);
386 1.1 kiyohara }
387 1.1 kiyohara for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++)
388 1.1 kiyohara wdcattach(sc->sc_ata_channels[channel]);
389 1.1 kiyohara
390 1.1 kiyohara return 0;
391 1.1 kiyohara }
392 1.1 kiyohara
393 1.1 kiyohara int
394 1.1 kiyohara mvsata_intr(struct mvsata_hc *mvhc)
395 1.1 kiyohara {
396 1.1 kiyohara struct mvsata_softc *sc = mvhc->hc_sc;
397 1.1 kiyohara struct mvsata_port *mvport;
398 1.1 kiyohara uint32_t cause;
399 1.1 kiyohara int port, handled = 0;
400 1.1 kiyohara
401 1.1 kiyohara cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC);
402 1.1 kiyohara
403 1.1 kiyohara DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n",
404 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, cause));
405 1.1 kiyohara
406 1.1 kiyohara if (cause & SATAHC_IC_SAINTCOAL)
407 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL);
408 1.1 kiyohara cause &= ~SATAHC_IC_SAINTCOAL;
409 1.1 kiyohara for (port = 0; port < sc->sc_port; port++) {
410 1.1 kiyohara mvport = mvhc->hc_ports[port];
411 1.1 kiyohara
412 1.1 kiyohara if (cause & SATAHC_IC_DONE(port)) {
413 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
414 1.1 kiyohara handled = mvsata_edma_handle(mvport, NULL);
415 1.1 kiyohara #endif
416 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_IC,
417 1.1 kiyohara ~SATAHC_IC_DONE(port));
418 1.1 kiyohara }
419 1.1 kiyohara
420 1.1 kiyohara if (cause & SATAHC_IC_SADEVINTERRUPT(port)) {
421 1.1 kiyohara wdcintr(&mvport->port_ata_channel);
422 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_IC,
423 1.1 kiyohara ~SATAHC_IC_SADEVINTERRUPT(port));
424 1.1 kiyohara handled = 1;
425 1.1 kiyohara }
426 1.1 kiyohara }
427 1.1 kiyohara
428 1.1 kiyohara return handled;
429 1.1 kiyohara }
430 1.1 kiyohara
431 1.1 kiyohara int
432 1.1 kiyohara mvsata_error(struct mvsata_port *mvport)
433 1.1 kiyohara {
434 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
435 1.1 kiyohara uint32_t cause;
436 1.1 kiyohara
437 1.1 kiyohara cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC);
438 1.29 jakllsch /*
439 1.29 jakllsch * We must ack SATA_SE and SATA_FISIC before acking coresponding bits
440 1.29 jakllsch * in EDMA_IEC.
441 1.29 jakllsch */
442 1.29 jakllsch if (cause & EDMA_IE_SERRINT) {
443 1.29 jakllsch MVSATA_EDMA_WRITE_4(mvport, SATA_SE,
444 1.29 jakllsch MVSATA_EDMA_READ_4(mvport, SATA_SEIM));
445 1.29 jakllsch }
446 1.29 jakllsch if (cause & EDMA_IE_ETRANSINT) {
447 1.29 jakllsch MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC,
448 1.29 jakllsch ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM));
449 1.29 jakllsch }
450 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause);
451 1.1 kiyohara
452 1.1 kiyohara DPRINTFN(3, ("%s:%d:%d:"
453 1.1 kiyohara " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n",
454 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
455 1.1 kiyohara mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM),
456 1.1 kiyohara MVSATA_EDMA_READ_4(mvport, EDMA_S)));
457 1.1 kiyohara
458 1.1 kiyohara cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM);
459 1.1 kiyohara if (!cause)
460 1.1 kiyohara return 0;
461 1.1 kiyohara
462 1.29 jakllsch if (cause & EDMA_IE_EDEVDIS) {
463 1.1 kiyohara aprint_normal("%s:%d:%d: device disconnect\n",
464 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
465 1.1 kiyohara mvport->port_hc->hc, mvport->port);
466 1.29 jakllsch }
467 1.1 kiyohara if (cause & EDMA_IE_EDEVCON) {
468 1.1 kiyohara if (sc->sc_gen == gen1)
469 1.1 kiyohara mvsata_devconn_gen1(mvport);
470 1.1 kiyohara
471 1.1 kiyohara DPRINTFN(3, (" device connected\n"));
472 1.1 kiyohara }
473 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
474 1.1 kiyohara if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) ||
475 1.1 kiyohara (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) {
476 1.1 kiyohara switch (mvport->port_edmamode) {
477 1.1 kiyohara case dma:
478 1.1 kiyohara case queued:
479 1.1 kiyohara case ncq:
480 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
481 1.1 kiyohara mvsata_edma_enable(mvport);
482 1.1 kiyohara if (cause & EDMA_IE_EDEVERR)
483 1.1 kiyohara break;
484 1.1 kiyohara
485 1.1 kiyohara /* FALLTHROUGH */
486 1.1 kiyohara
487 1.1 kiyohara case nodma:
488 1.1 kiyohara default:
489 1.1 kiyohara aprint_error(
490 1.1 kiyohara "%s:%d:%d: EDMA self disable happen 0x%x\n",
491 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
492 1.1 kiyohara mvport->port_hc->hc, mvport->port, cause);
493 1.1 kiyohara break;
494 1.1 kiyohara }
495 1.1 kiyohara }
496 1.1 kiyohara #endif
497 1.1 kiyohara if (cause & EDMA_IE_ETRANSINT) {
498 1.1 kiyohara /* hot plug the Port Multiplier */
499 1.1 kiyohara aprint_normal("%s:%d:%d: detect Port Multiplier?\n",
500 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
501 1.1 kiyohara mvport->port_hc->hc, mvport->port);
502 1.1 kiyohara }
503 1.1 kiyohara
504 1.29 jakllsch return 1;
505 1.1 kiyohara }
506 1.1 kiyohara
507 1.1 kiyohara
508 1.1 kiyohara /*
509 1.1 kiyohara * ATA callback entry points
510 1.1 kiyohara */
511 1.1 kiyohara
512 1.29 jakllsch static void
513 1.29 jakllsch mvsata_probe_drive(struct ata_channel *chp)
514 1.29 jakllsch {
515 1.29 jakllsch struct mvsata_port * const mvport = (struct mvsata_port *)chp;
516 1.29 jakllsch uint32_t sstat, sig;
517 1.29 jakllsch
518 1.29 jakllsch sstat = sata_reset_interface(chp, mvport->port_iot,
519 1.30 bouyer mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT);
520 1.29 jakllsch switch (sstat) {
521 1.29 jakllsch case SStatus_DET_DEV:
522 1.29 jakllsch mvsata_pmp_select(mvport, PMP_PORT_CTL);
523 1.29 jakllsch sig = mvsata_softreset(mvport, AT_WAIT);
524 1.29 jakllsch sata_interpret_sig(chp, 0, sig);
525 1.29 jakllsch break;
526 1.29 jakllsch default:
527 1.29 jakllsch break;
528 1.29 jakllsch }
529 1.29 jakllsch }
530 1.29 jakllsch
531 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
532 1.1 kiyohara static int
533 1.1 kiyohara mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
534 1.1 kiyohara {
535 1.1 kiyohara struct ata_channel *chp = drvp->chnl_softc;
536 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
537 1.1 kiyohara struct ata_xfer *xfer;
538 1.1 kiyohara
539 1.7 riz DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64
540 1.7 riz ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel,
541 1.7 riz drvp->drive, ata_bio->blkno, ata_bio->bcount));
542 1.1 kiyohara
543 1.1 kiyohara xfer = ata_get_xfer(ATAXF_NOSLEEP);
544 1.1 kiyohara if (xfer == NULL)
545 1.1 kiyohara return ATACMD_TRY_AGAIN;
546 1.1 kiyohara if (atac->atac_cap & ATAC_CAP_NOIRQ)
547 1.1 kiyohara ata_bio->flags |= ATA_POLL;
548 1.1 kiyohara if (ata_bio->flags & ATA_POLL)
549 1.1 kiyohara xfer->c_flags |= C_POLL;
550 1.24 bouyer if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) &&
551 1.1 kiyohara (ata_bio->flags & ATA_SINGLE) == 0)
552 1.1 kiyohara xfer->c_flags |= C_DMA;
553 1.1 kiyohara xfer->c_drive = drvp->drive;
554 1.1 kiyohara xfer->c_cmd = ata_bio;
555 1.1 kiyohara xfer->c_databuf = ata_bio->databuf;
556 1.1 kiyohara xfer->c_bcount = ata_bio->bcount;
557 1.1 kiyohara xfer->c_start = mvsata_bio_start;
558 1.1 kiyohara xfer->c_intr = mvsata_bio_intr;
559 1.1 kiyohara xfer->c_kill_xfer = mvsata_bio_kill_xfer;
560 1.1 kiyohara ata_exec_xfer(chp, xfer);
561 1.1 kiyohara return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
562 1.1 kiyohara }
563 1.1 kiyohara
564 1.1 kiyohara static void
565 1.24 bouyer mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp)
566 1.1 kiyohara {
567 1.1 kiyohara struct ata_channel *chp = drvp->chnl_softc;
568 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
569 1.1 kiyohara uint32_t edma_c;
570 1.29 jakllsch uint32_t sig;
571 1.24 bouyer
572 1.1 kiyohara edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD);
573 1.1 kiyohara
574 1.1 kiyohara DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n",
575 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive,
576 1.1 kiyohara (edma_c & EDMA_CMD_EENEDMA) ? "" : "not "));
577 1.1 kiyohara
578 1.1 kiyohara if (edma_c & EDMA_CMD_EENEDMA)
579 1.1 kiyohara mvsata_edma_disable(mvport, 10000, flags & AT_WAIT);
580 1.1 kiyohara
581 1.29 jakllsch mvsata_pmp_select(mvport, drvp->drive);
582 1.29 jakllsch
583 1.29 jakllsch sig = mvsata_softreset(mvport, flags & AT_WAIT);
584 1.29 jakllsch
585 1.29 jakllsch if (sigp)
586 1.29 jakllsch *sigp = sig;
587 1.1 kiyohara
588 1.1 kiyohara if (edma_c & EDMA_CMD_EENEDMA) {
589 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
590 1.1 kiyohara mvsata_edma_enable(mvport);
591 1.1 kiyohara }
592 1.1 kiyohara return;
593 1.1 kiyohara }
594 1.1 kiyohara
595 1.1 kiyohara static void
596 1.1 kiyohara mvsata_reset_channel(struct ata_channel *chp, int flags)
597 1.1 kiyohara {
598 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
599 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
600 1.1 kiyohara struct ata_xfer *xfer;
601 1.1 kiyohara uint32_t sstat, ctrl;
602 1.1 kiyohara int i;
603 1.1 kiyohara
604 1.1 kiyohara DPRINTF(("%s: mvsata_reset_channel: channel=%d\n",
605 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel));
606 1.1 kiyohara
607 1.1 kiyohara mvsata_hreset_port(mvport);
608 1.1 kiyohara sstat = sata_reset_interface(chp, mvport->port_iot,
609 1.30 bouyer mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags);
610 1.1 kiyohara
611 1.1 kiyohara if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE &&
612 1.1 kiyohara sc->sc_gen != gen1) {
613 1.1 kiyohara /* Downgrade to GenI */
614 1.1 kiyohara const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY |
615 1.1 kiyohara SControl_DET_DISABLE;
616 1.1 kiyohara
617 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val);
618 1.1 kiyohara
619 1.1 kiyohara ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG);
620 1.1 kiyohara ctrl &= ~(1 << 17); /* Disable GenII */
621 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl);
622 1.1 kiyohara
623 1.1 kiyohara mvsata_hreset_port(mvport);
624 1.1 kiyohara sata_reset_interface(chp, mvport->port_iot,
625 1.30 bouyer mvport->port_sata_scontrol, mvport->port_sata_sstatus,
626 1.30 bouyer flags);
627 1.1 kiyohara }
628 1.1 kiyohara
629 1.8 jakllsch for (i = 0; i < MVSATA_EDMAQ_LEN; i++) {
630 1.1 kiyohara xfer = mvport->port_reqtbl[i].xfer;
631 1.1 kiyohara if (xfer == NULL)
632 1.1 kiyohara continue;
633 1.1 kiyohara chp->ch_queue->active_xfer = xfer;
634 1.1 kiyohara xfer->c_kill_xfer(chp, xfer, KILL_RESET);
635 1.1 kiyohara }
636 1.1 kiyohara
637 1.1 kiyohara mvsata_edma_config(mvport, mvport->port_edmamode);
638 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
639 1.1 kiyohara mvsata_edma_enable(mvport);
640 1.1 kiyohara return;
641 1.1 kiyohara }
642 1.1 kiyohara
643 1.1 kiyohara
644 1.1 kiyohara static int
645 1.1 kiyohara mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
646 1.1 kiyohara {
647 1.1 kiyohara struct ata_channel *chp = drvp->chnl_softc;
648 1.1 kiyohara #ifdef MVSATA_DEBUG
649 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
650 1.1 kiyohara #endif
651 1.1 kiyohara struct ata_xfer *xfer;
652 1.1 kiyohara int rv, s;
653 1.1 kiyohara
654 1.1 kiyohara DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d,"
655 1.29 jakllsch " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x,"
656 1.29 jakllsch " r_device=0x%02x, r_command=0x%02x\n",
657 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel,
658 1.29 jakllsch drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count,
659 1.29 jakllsch ata_c->r_features, ata_c->r_device, ata_c->r_command));
660 1.1 kiyohara
661 1.1 kiyohara xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
662 1.1 kiyohara ATAXF_NOSLEEP);
663 1.1 kiyohara if (xfer == NULL)
664 1.1 kiyohara return ATACMD_TRY_AGAIN;
665 1.1 kiyohara if (ata_c->flags & AT_POLL)
666 1.1 kiyohara xfer->c_flags |= C_POLL;
667 1.1 kiyohara if (ata_c->flags & AT_WAIT)
668 1.1 kiyohara xfer->c_flags |= C_WAIT;
669 1.1 kiyohara xfer->c_drive = drvp->drive;
670 1.1 kiyohara xfer->c_databuf = ata_c->data;
671 1.1 kiyohara xfer->c_bcount = ata_c->bcount;
672 1.1 kiyohara xfer->c_cmd = ata_c;
673 1.1 kiyohara xfer->c_start = mvsata_wdc_cmd_start;
674 1.1 kiyohara xfer->c_intr = mvsata_wdc_cmd_intr;
675 1.1 kiyohara xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer;
676 1.1 kiyohara s = splbio();
677 1.1 kiyohara ata_exec_xfer(chp, xfer);
678 1.1 kiyohara #ifdef DIAGNOSTIC
679 1.1 kiyohara if ((ata_c->flags & AT_POLL) != 0 &&
680 1.1 kiyohara (ata_c->flags & AT_DONE) == 0)
681 1.1 kiyohara panic("mvsata_exec_command: polled command not done");
682 1.1 kiyohara #endif
683 1.1 kiyohara if (ata_c->flags & AT_DONE)
684 1.1 kiyohara rv = ATACMD_COMPLETE;
685 1.1 kiyohara else {
686 1.1 kiyohara if (ata_c->flags & AT_WAIT) {
687 1.1 kiyohara while ((ata_c->flags & AT_DONE) == 0)
688 1.1 kiyohara tsleep(ata_c, PRIBIO, "mvsatacmd", 0);
689 1.1 kiyohara rv = ATACMD_COMPLETE;
690 1.1 kiyohara } else
691 1.1 kiyohara rv = ATACMD_QUEUED;
692 1.1 kiyohara }
693 1.1 kiyohara splx(s);
694 1.1 kiyohara return rv;
695 1.1 kiyohara }
696 1.1 kiyohara
697 1.1 kiyohara static int
698 1.1 kiyohara mvsata_addref(struct ata_drive_datas *drvp)
699 1.1 kiyohara {
700 1.1 kiyohara
701 1.1 kiyohara return 0;
702 1.1 kiyohara }
703 1.1 kiyohara
704 1.1 kiyohara static void
705 1.1 kiyohara mvsata_delref(struct ata_drive_datas *drvp)
706 1.1 kiyohara {
707 1.1 kiyohara
708 1.1 kiyohara return;
709 1.1 kiyohara }
710 1.1 kiyohara
711 1.1 kiyohara static void
712 1.1 kiyohara mvsata_killpending(struct ata_drive_datas *drvp)
713 1.1 kiyohara {
714 1.1 kiyohara
715 1.1 kiyohara return;
716 1.1 kiyohara }
717 1.1 kiyohara
718 1.1 kiyohara #if NATAPIBUS > 0
719 1.1 kiyohara static void
720 1.1 kiyohara mvsata_atapibus_attach(struct atabus_softc *ata_sc)
721 1.1 kiyohara {
722 1.1 kiyohara struct ata_channel *chp = ata_sc->sc_chan;
723 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
724 1.1 kiyohara struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
725 1.1 kiyohara struct scsipi_channel *chan = &chp->ch_atapi_channel;
726 1.1 kiyohara
727 1.1 kiyohara /*
728 1.1 kiyohara * Fill in the scsipi_adapter.
729 1.1 kiyohara */
730 1.1 kiyohara adapt->adapt_dev = atac->atac_dev;
731 1.1 kiyohara adapt->adapt_nchannels = atac->atac_nchannels;
732 1.1 kiyohara adapt->adapt_request = mvsata_atapi_scsipi_request;
733 1.1 kiyohara adapt->adapt_minphys = mvsata_atapi_minphys;
734 1.1 kiyohara atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device;
735 1.1 kiyohara
736 1.1 kiyohara /*
737 1.1 kiyohara * Fill in the scsipi_channel.
738 1.1 kiyohara */
739 1.1 kiyohara memset(chan, 0, sizeof(*chan));
740 1.1 kiyohara chan->chan_adapter = adapt;
741 1.1 kiyohara chan->chan_bustype = &mvsata_atapi_bustype;
742 1.1 kiyohara chan->chan_channel = chp->ch_channel;
743 1.1 kiyohara chan->chan_flags = SCSIPI_CHAN_OPENINGS;
744 1.1 kiyohara chan->chan_openings = 1;
745 1.1 kiyohara chan->chan_max_periph = 1;
746 1.1 kiyohara chan->chan_ntargets = 1;
747 1.1 kiyohara chan->chan_nluns = 1;
748 1.1 kiyohara
749 1.1 kiyohara chp->atapibus =
750 1.1 kiyohara config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint);
751 1.1 kiyohara }
752 1.1 kiyohara
753 1.1 kiyohara static void
754 1.1 kiyohara mvsata_atapi_scsipi_request(struct scsipi_channel *chan,
755 1.1 kiyohara scsipi_adapter_req_t req, void *arg)
756 1.1 kiyohara {
757 1.1 kiyohara struct scsipi_adapter *adapt = chan->chan_adapter;
758 1.1 kiyohara struct scsipi_periph *periph;
759 1.1 kiyohara struct scsipi_xfer *sc_xfer;
760 1.1 kiyohara struct mvsata_softc *sc = device_private(adapt->adapt_dev);
761 1.1 kiyohara struct atac_softc *atac = &sc->sc_wdcdev.sc_atac;
762 1.1 kiyohara struct ata_xfer *xfer;
763 1.1 kiyohara int channel = chan->chan_channel;
764 1.1 kiyohara int drive, s;
765 1.1 kiyohara
766 1.1 kiyohara switch (req) {
767 1.1 kiyohara case ADAPTER_REQ_RUN_XFER:
768 1.1 kiyohara sc_xfer = arg;
769 1.1 kiyohara periph = sc_xfer->xs_periph;
770 1.1 kiyohara drive = periph->periph_target;
771 1.1 kiyohara
772 1.1 kiyohara if (!device_is_active(atac->atac_dev)) {
773 1.1 kiyohara sc_xfer->error = XS_DRIVER_STUFFUP;
774 1.1 kiyohara scsipi_done(sc_xfer);
775 1.1 kiyohara return;
776 1.1 kiyohara }
777 1.1 kiyohara xfer = ata_get_xfer(ATAXF_NOSLEEP);
778 1.1 kiyohara if (xfer == NULL) {
779 1.1 kiyohara sc_xfer->error = XS_RESOURCE_SHORTAGE;
780 1.1 kiyohara scsipi_done(sc_xfer);
781 1.1 kiyohara return;
782 1.1 kiyohara }
783 1.1 kiyohara
784 1.1 kiyohara if (sc_xfer->xs_control & XS_CTL_POLL)
785 1.1 kiyohara xfer->c_flags |= C_POLL;
786 1.1 kiyohara xfer->c_drive = drive;
787 1.1 kiyohara xfer->c_flags |= C_ATAPI;
788 1.1 kiyohara xfer->c_cmd = sc_xfer;
789 1.1 kiyohara xfer->c_databuf = sc_xfer->data;
790 1.1 kiyohara xfer->c_bcount = sc_xfer->datalen;
791 1.1 kiyohara xfer->c_start = mvsata_atapi_start;
792 1.1 kiyohara xfer->c_intr = mvsata_atapi_intr;
793 1.1 kiyohara xfer->c_kill_xfer = mvsata_atapi_kill_xfer;
794 1.1 kiyohara xfer->c_dscpoll = 0;
795 1.1 kiyohara s = splbio();
796 1.1 kiyohara ata_exec_xfer(atac->atac_channels[channel], xfer);
797 1.1 kiyohara #ifdef DIAGNOSTIC
798 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
799 1.1 kiyohara (sc_xfer->xs_status & XS_STS_DONE) == 0)
800 1.1 kiyohara panic("mvsata_atapi_scsipi_request:"
801 1.1 kiyohara " polled command not done");
802 1.1 kiyohara #endif
803 1.1 kiyohara splx(s);
804 1.1 kiyohara return;
805 1.1 kiyohara
806 1.1 kiyohara default:
807 1.1 kiyohara /* Not supported, nothing to do. */
808 1.1 kiyohara ;
809 1.1 kiyohara }
810 1.1 kiyohara }
811 1.1 kiyohara
812 1.1 kiyohara static void
813 1.1 kiyohara mvsata_atapi_minphys(struct buf *bp)
814 1.1 kiyohara {
815 1.1 kiyohara
816 1.1 kiyohara if (bp->b_bcount > MAXPHYS)
817 1.1 kiyohara bp->b_bcount = MAXPHYS;
818 1.1 kiyohara minphys(bp);
819 1.1 kiyohara }
820 1.1 kiyohara
821 1.1 kiyohara static void
822 1.1 kiyohara mvsata_atapi_probe_device(struct atapibus_softc *sc, int target)
823 1.1 kiyohara {
824 1.1 kiyohara struct scsipi_channel *chan = sc->sc_channel;
825 1.1 kiyohara struct scsipi_periph *periph;
826 1.1 kiyohara struct ataparams ids;
827 1.1 kiyohara struct ataparams *id = &ids;
828 1.1 kiyohara struct mvsata_softc *mvc =
829 1.1 kiyohara device_private(chan->chan_adapter->adapt_dev);
830 1.1 kiyohara struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac;
831 1.1 kiyohara struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
832 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[target];
833 1.1 kiyohara struct scsipibus_attach_args sa;
834 1.1 kiyohara char serial_number[21], model[41], firmware_revision[9];
835 1.1 kiyohara int s;
836 1.1 kiyohara
837 1.1 kiyohara /* skip if already attached */
838 1.1 kiyohara if (scsipi_lookup_periph(chan, target, 0) != NULL)
839 1.1 kiyohara return;
840 1.1 kiyohara
841 1.1 kiyohara /* if no ATAPI device detected at attach time, skip */
842 1.24 bouyer if (drvp->drive_type != ATA_DRIVET_ATAPI) {
843 1.1 kiyohara DPRINTF(("%s:%d: mvsata_atapi_probe_device:"
844 1.1 kiyohara " drive %d not present\n",
845 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, target));
846 1.1 kiyohara return;
847 1.1 kiyohara }
848 1.1 kiyohara
849 1.1 kiyohara /* Some ATAPI devices need a bit more time after software reset. */
850 1.1 kiyohara delay(5000);
851 1.1 kiyohara if (ata_get_params(drvp, AT_WAIT, id) == 0) {
852 1.1 kiyohara #ifdef ATAPI_DEBUG_PROBE
853 1.1 kiyohara log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n",
854 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, target,
855 1.1 kiyohara id->atap_config & ATAPI_CFG_CMD_MASK,
856 1.1 kiyohara id->atap_config & ATAPI_CFG_DRQ_MASK);
857 1.1 kiyohara #endif
858 1.1 kiyohara periph = scsipi_alloc_periph(M_NOWAIT);
859 1.1 kiyohara if (periph == NULL) {
860 1.1 kiyohara aprint_error_dev(atac->atac_dev,
861 1.1 kiyohara "unable to allocate periph"
862 1.1 kiyohara " for channel %d drive %d\n",
863 1.1 kiyohara chp->ch_channel, target);
864 1.1 kiyohara return;
865 1.1 kiyohara }
866 1.1 kiyohara periph->periph_dev = NULL;
867 1.1 kiyohara periph->periph_channel = chan;
868 1.1 kiyohara periph->periph_switch = &atapi_probe_periphsw;
869 1.1 kiyohara periph->periph_target = target;
870 1.1 kiyohara periph->periph_lun = 0;
871 1.1 kiyohara periph->periph_quirks = PQUIRK_ONLYBIG;
872 1.1 kiyohara
873 1.1 kiyohara #ifdef SCSIPI_DEBUG
874 1.1 kiyohara if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
875 1.1 kiyohara SCSIPI_DEBUG_TARGET == target)
876 1.1 kiyohara periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
877 1.1 kiyohara #endif
878 1.1 kiyohara periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
879 1.1 kiyohara if (id->atap_config & ATAPI_CFG_REMOV)
880 1.1 kiyohara periph->periph_flags |= PERIPH_REMOVABLE;
881 1.1 kiyohara if (periph->periph_type == T_SEQUENTIAL) {
882 1.1 kiyohara s = splbio();
883 1.24 bouyer drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW;
884 1.1 kiyohara splx(s);
885 1.1 kiyohara }
886 1.1 kiyohara
887 1.1 kiyohara sa.sa_periph = periph;
888 1.1 kiyohara sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config);
889 1.1 kiyohara sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
890 1.1 kiyohara T_REMOV : T_FIXED;
891 1.35 christos strnvisx(model, sizeof(model), id->atap_model, 40,
892 1.35 christos VIS_TRIM|VIS_SAFE|VIS_OCTAL);
893 1.35 christos strnvisx(serial_number, sizeof(serial_number), id->atap_serial,
894 1.35 christos 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL);
895 1.35 christos strnvisx(firmware_revision, sizeof(firmware_revision),
896 1.35 christos id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL);
897 1.1 kiyohara sa.sa_inqbuf.vendor = model;
898 1.1 kiyohara sa.sa_inqbuf.product = serial_number;
899 1.1 kiyohara sa.sa_inqbuf.revision = firmware_revision;
900 1.1 kiyohara
901 1.1 kiyohara /*
902 1.1 kiyohara * Determine the operating mode capabilities of the device.
903 1.1 kiyohara */
904 1.1 kiyohara if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
905 1.1 kiyohara periph->periph_cap |= PERIPH_CAP_CMD16;
906 1.1 kiyohara /* XXX This is gross. */
907 1.1 kiyohara periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
908 1.1 kiyohara
909 1.1 kiyohara drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
910 1.1 kiyohara
911 1.1 kiyohara if (drvp->drv_softc)
912 1.1 kiyohara ata_probe_caps(drvp);
913 1.1 kiyohara else {
914 1.1 kiyohara s = splbio();
915 1.24 bouyer drvp->drive_type = ATA_DRIVET_NONE;
916 1.1 kiyohara splx(s);
917 1.1 kiyohara }
918 1.1 kiyohara } else {
919 1.1 kiyohara DPRINTF(("%s:%d: mvsata_atapi_probe_device:"
920 1.1 kiyohara " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n",
921 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, target,
922 1.1 kiyohara chp->ch_error));
923 1.1 kiyohara s = splbio();
924 1.24 bouyer drvp->drive_type = ATA_DRIVET_NONE;
925 1.1 kiyohara splx(s);
926 1.1 kiyohara }
927 1.1 kiyohara }
928 1.1 kiyohara
929 1.1 kiyohara /*
930 1.1 kiyohara * Kill off all pending xfers for a periph.
931 1.1 kiyohara *
932 1.1 kiyohara * Must be called at splbio().
933 1.1 kiyohara */
934 1.1 kiyohara static void
935 1.1 kiyohara mvsata_atapi_kill_pending(struct scsipi_periph *periph)
936 1.1 kiyohara {
937 1.1 kiyohara struct atac_softc *atac =
938 1.1 kiyohara device_private(periph->periph_channel->chan_adapter->adapt_dev);
939 1.1 kiyohara struct ata_channel *chp =
940 1.1 kiyohara atac->atac_channels[periph->periph_channel->chan_channel];
941 1.1 kiyohara
942 1.1 kiyohara ata_kill_pending(&chp->ch_drive[periph->periph_target]);
943 1.1 kiyohara }
944 1.1 kiyohara #endif /* NATAPIBUS > 0 */
945 1.1 kiyohara #endif /* MVSATA_WITHOUTDMA */
946 1.1 kiyohara
947 1.1 kiyohara
948 1.1 kiyohara /*
949 1.1 kiyohara * mvsata_setup_channel()
950 1.1 kiyohara * Setup EDMA registers and prepare/purge DMA resources.
951 1.1 kiyohara * We assuming already stopped the EDMA.
952 1.1 kiyohara */
953 1.1 kiyohara static void
954 1.1 kiyohara mvsata_setup_channel(struct ata_channel *chp)
955 1.1 kiyohara {
956 1.1 kiyohara #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG)
957 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
958 1.1 kiyohara #endif
959 1.1 kiyohara struct ata_drive_datas *drvp;
960 1.1 kiyohara uint32_t edma_mode;
961 1.1 kiyohara int drive, s;
962 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
963 1.1 kiyohara int i;
964 1.1 kiyohara const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN;
965 1.1 kiyohara const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN;
966 1.1 kiyohara const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN;
967 1.1 kiyohara #endif
968 1.1 kiyohara
969 1.1 kiyohara DPRINTF(("%s:%d: mvsata_setup_channel: ",
970 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel));
971 1.1 kiyohara
972 1.1 kiyohara edma_mode = nodma;
973 1.24 bouyer for (drive = 0; drive < chp->ch_ndrives; drive++) {
974 1.1 kiyohara drvp = &chp->ch_drive[drive];
975 1.1 kiyohara
976 1.1 kiyohara /* If no drive, skip */
977 1.24 bouyer if (drvp->drive_type == ATA_DRIVET_NONE)
978 1.1 kiyohara continue;
979 1.1 kiyohara
980 1.24 bouyer if (drvp->drive_flags & ATA_DRIVE_UDMA) {
981 1.1 kiyohara /* use Ultra/DMA */
982 1.1 kiyohara s = splbio();
983 1.24 bouyer drvp->drive_flags &= ~ATA_DRIVE_DMA;
984 1.1 kiyohara splx(s);
985 1.1 kiyohara }
986 1.1 kiyohara
987 1.24 bouyer if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA))
988 1.24 bouyer if (drvp->drive_type == ATA_DRIVET_ATA)
989 1.1 kiyohara edma_mode = dma;
990 1.1 kiyohara }
991 1.1 kiyohara
992 1.1 kiyohara DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : ""));
993 1.1 kiyohara
994 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
995 1.1 kiyohara if (edma_mode == nodma) {
996 1.1 kiyohara no_edma:
997 1.1 kiyohara if (mvport->port_crqb != NULL)
998 1.1 kiyohara mvsata_edma_resource_purge(mvport, mvport->port_dmat,
999 1.1 kiyohara mvport->port_crqb_dmamap, mvport->port_crqb);
1000 1.1 kiyohara if (mvport->port_crpb != NULL)
1001 1.1 kiyohara mvsata_edma_resource_purge(mvport, mvport->port_dmat,
1002 1.1 kiyohara mvport->port_crpb_dmamap, mvport->port_crpb);
1003 1.1 kiyohara if (mvport->port_eprd != NULL)
1004 1.1 kiyohara mvsata_edma_resource_purge(mvport, mvport->port_dmat,
1005 1.1 kiyohara mvport->port_eprd_dmamap, mvport->port_eprd);
1006 1.1 kiyohara
1007 1.1 kiyohara return;
1008 1.1 kiyohara }
1009 1.1 kiyohara
1010 1.1 kiyohara if (mvport->port_crqb == NULL)
1011 1.1 kiyohara mvport->port_crqb = mvsata_edma_resource_prepare(mvport,
1012 1.1 kiyohara mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1);
1013 1.1 kiyohara if (mvport->port_crpb == NULL)
1014 1.1 kiyohara mvport->port_crpb = mvsata_edma_resource_prepare(mvport,
1015 1.1 kiyohara mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0);
1016 1.1 kiyohara if (mvport->port_eprd == NULL) {
1017 1.1 kiyohara mvport->port_eprd = mvsata_edma_resource_prepare(mvport,
1018 1.1 kiyohara mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size,
1019 1.1 kiyohara 1);
1020 1.1 kiyohara for (i = 0; i < MVSATA_EDMAQ_LEN; i++) {
1021 1.1 kiyohara mvport->port_reqtbl[i].eprd_offset =
1022 1.1 kiyohara i * MVSATA_EPRD_MAX_SIZE;
1023 1.1 kiyohara mvport->port_reqtbl[i].eprd = mvport->port_eprd +
1024 1.1 kiyohara i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd);
1025 1.1 kiyohara }
1026 1.1 kiyohara }
1027 1.1 kiyohara
1028 1.1 kiyohara if (mvport->port_crqb == NULL || mvport->port_crpb == NULL ||
1029 1.1 kiyohara mvport->port_eprd == NULL) {
1030 1.1 kiyohara aprint_error_dev(MVSATA_DEV2(mvport),
1031 1.1 kiyohara "channel %d: can't use EDMA\n", chp->ch_channel);
1032 1.1 kiyohara s = splbio();
1033 1.24 bouyer for (drive = 0; drive < chp->ch_ndrives; drive++) {
1034 1.1 kiyohara drvp = &chp->ch_drive[drive];
1035 1.1 kiyohara
1036 1.1 kiyohara /* If no drive, skip */
1037 1.24 bouyer if (drvp->drive_type == ATA_DRIVET_NONE)
1038 1.1 kiyohara continue;
1039 1.1 kiyohara
1040 1.24 bouyer drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA);
1041 1.1 kiyohara }
1042 1.1 kiyohara splx(s);
1043 1.1 kiyohara goto no_edma;
1044 1.1 kiyohara }
1045 1.1 kiyohara
1046 1.1 kiyohara mvsata_edma_config(mvport, edma_mode);
1047 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
1048 1.1 kiyohara mvsata_edma_enable(mvport);
1049 1.1 kiyohara #endif
1050 1.1 kiyohara }
1051 1.1 kiyohara
1052 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
1053 1.1 kiyohara static void
1054 1.1 kiyohara mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
1055 1.1 kiyohara {
1056 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1057 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
1058 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
1059 1.1 kiyohara struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1060 1.1 kiyohara struct ata_bio *ata_bio = xfer->c_cmd;
1061 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
1062 1.1 kiyohara int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
1063 1.1 kiyohara u_int16_t cyl;
1064 1.1 kiyohara u_int8_t head, sect, cmd = 0;
1065 1.1 kiyohara int nblks, error;
1066 1.1 kiyohara
1067 1.1 kiyohara DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n",
1068 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
1069 1.1 kiyohara
1070 1.1 kiyohara if (xfer->c_flags & C_DMA)
1071 1.1 kiyohara if (drvp->n_xfers <= NXFER)
1072 1.1 kiyohara drvp->n_xfers++;
1073 1.1 kiyohara
1074 1.1 kiyohara again:
1075 1.1 kiyohara /*
1076 1.1 kiyohara *
1077 1.1 kiyohara * When starting a multi-sector transfer, or doing single-sector
1078 1.1 kiyohara * transfers...
1079 1.1 kiyohara */
1080 1.1 kiyohara if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) {
1081 1.1 kiyohara if (ata_bio->flags & ATA_SINGLE)
1082 1.1 kiyohara nblks = 1;
1083 1.1 kiyohara else
1084 1.1 kiyohara nblks = xfer->c_bcount / ata_bio->lp->d_secsize;
1085 1.1 kiyohara /* Check for bad sectors and adjust transfer, if necessary. */
1086 1.1 kiyohara if ((ata_bio->lp->d_flags & D_BADSECT) != 0) {
1087 1.1 kiyohara long blkdiff;
1088 1.1 kiyohara int i;
1089 1.1 kiyohara
1090 1.1 kiyohara for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1;
1091 1.1 kiyohara i++) {
1092 1.1 kiyohara blkdiff -= ata_bio->blkno;
1093 1.1 kiyohara if (blkdiff < 0)
1094 1.1 kiyohara continue;
1095 1.1 kiyohara if (blkdiff == 0)
1096 1.1 kiyohara /* Replace current block of transfer. */
1097 1.1 kiyohara ata_bio->blkno =
1098 1.1 kiyohara ata_bio->lp->d_secperunit -
1099 1.1 kiyohara ata_bio->lp->d_nsectors - i - 1;
1100 1.1 kiyohara if (blkdiff < nblks) {
1101 1.1 kiyohara /* Bad block inside transfer. */
1102 1.1 kiyohara ata_bio->flags |= ATA_SINGLE;
1103 1.1 kiyohara nblks = 1;
1104 1.1 kiyohara }
1105 1.1 kiyohara break;
1106 1.1 kiyohara }
1107 1.1 kiyohara /* Transfer is okay now. */
1108 1.1 kiyohara }
1109 1.1 kiyohara if (xfer->c_flags & C_DMA) {
1110 1.1 kiyohara ata_bio->nblks = nblks;
1111 1.1 kiyohara ata_bio->nbytes = xfer->c_bcount;
1112 1.1 kiyohara
1113 1.1 kiyohara if (xfer->c_flags & C_POLL)
1114 1.1 kiyohara sc->sc_enable_intr(mvport, 0 /*off*/);
1115 1.9 jakllsch error = mvsata_edma_enqueue(mvport, ata_bio,
1116 1.1 kiyohara (char *)xfer->c_databuf + xfer->c_skip);
1117 1.1 kiyohara if (error) {
1118 1.1 kiyohara if (error == EINVAL) {
1119 1.1 kiyohara /*
1120 1.1 kiyohara * We can't do DMA on this transfer
1121 1.1 kiyohara * for some reason. Fall back to
1122 1.1 kiyohara * PIO.
1123 1.1 kiyohara */
1124 1.1 kiyohara xfer->c_flags &= ~C_DMA;
1125 1.1 kiyohara error = 0;
1126 1.1 kiyohara goto do_pio;
1127 1.1 kiyohara }
1128 1.1 kiyohara if (error == EBUSY) {
1129 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1130 1.1 kiyohara "channel %d: EDMA Queue full\n",
1131 1.1 kiyohara chp->ch_channel);
1132 1.1 kiyohara /*
1133 1.1 kiyohara * XXXX: Perhaps, after it waits for
1134 1.1 kiyohara * a while, it is necessary to call
1135 1.1 kiyohara * bio_start again.
1136 1.1 kiyohara */
1137 1.1 kiyohara }
1138 1.1 kiyohara ata_bio->error = ERR_DMA;
1139 1.1 kiyohara ata_bio->r_error = 0;
1140 1.1 kiyohara mvsata_bio_done(chp, xfer);
1141 1.1 kiyohara return;
1142 1.1 kiyohara }
1143 1.1 kiyohara chp->ch_flags |= ATACH_DMA_WAIT;
1144 1.1 kiyohara /* start timeout machinery */
1145 1.1 kiyohara if ((xfer->c_flags & C_POLL) == 0)
1146 1.1 kiyohara callout_reset(&chp->ch_callout,
1147 1.1 kiyohara ATA_DELAY / 1000 * hz,
1148 1.1 kiyohara mvsata_edma_timeout, xfer);
1149 1.1 kiyohara /* wait for irq */
1150 1.1 kiyohara goto intr;
1151 1.1 kiyohara } /* else not DMA */
1152 1.1 kiyohara do_pio:
1153 1.1 kiyohara if (ata_bio->flags & ATA_LBA48) {
1154 1.1 kiyohara sect = 0;
1155 1.1 kiyohara cyl = 0;
1156 1.1 kiyohara head = 0;
1157 1.1 kiyohara } else if (ata_bio->flags & ATA_LBA) {
1158 1.1 kiyohara sect = (ata_bio->blkno >> 0) & 0xff;
1159 1.1 kiyohara cyl = (ata_bio->blkno >> 8) & 0xffff;
1160 1.1 kiyohara head = (ata_bio->blkno >> 24) & 0x0f;
1161 1.1 kiyohara head |= WDSD_LBA;
1162 1.1 kiyohara } else {
1163 1.1 kiyohara int blkno = ata_bio->blkno;
1164 1.1 kiyohara sect = blkno % ata_bio->lp->d_nsectors;
1165 1.1 kiyohara sect++; /* Sectors begin with 1, not 0. */
1166 1.1 kiyohara blkno /= ata_bio->lp->d_nsectors;
1167 1.1 kiyohara head = blkno % ata_bio->lp->d_ntracks;
1168 1.1 kiyohara blkno /= ata_bio->lp->d_ntracks;
1169 1.1 kiyohara cyl = blkno;
1170 1.1 kiyohara head |= WDSD_CHS;
1171 1.1 kiyohara }
1172 1.1 kiyohara ata_bio->nblks = min(nblks, ata_bio->multi);
1173 1.1 kiyohara ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize;
1174 1.1 kiyohara KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0);
1175 1.1 kiyohara if (ata_bio->nblks > 1)
1176 1.1 kiyohara cmd = (ata_bio->flags & ATA_READ) ?
1177 1.1 kiyohara WDCC_READMULTI : WDCC_WRITEMULTI;
1178 1.1 kiyohara else
1179 1.1 kiyohara cmd = (ata_bio->flags & ATA_READ) ?
1180 1.1 kiyohara WDCC_READ : WDCC_WRITE;
1181 1.1 kiyohara
1182 1.1 kiyohara /* EDMA disable, if enabled this channel. */
1183 1.1 kiyohara if (mvport->port_edmamode != nodma)
1184 1.1 kiyohara mvsata_edma_disable(mvport, 10 /* ms */, wait_flags);
1185 1.1 kiyohara
1186 1.29 jakllsch mvsata_pmp_select(mvport, xfer->c_drive);
1187 1.29 jakllsch
1188 1.1 kiyohara /* Do control operations specially. */
1189 1.1 kiyohara if (__predict_false(drvp->state < READY)) {
1190 1.1 kiyohara /*
1191 1.1 kiyohara * Actually, we want to be careful not to mess with
1192 1.1 kiyohara * the control state if the device is currently busy,
1193 1.1 kiyohara * but we can assume that we never get to this point
1194 1.1 kiyohara * if that's the case.
1195 1.1 kiyohara */
1196 1.1 kiyohara /*
1197 1.1 kiyohara * If it's not a polled command, we need the kernel
1198 1.1 kiyohara * thread
1199 1.1 kiyohara */
1200 1.1 kiyohara if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) {
1201 1.1 kiyohara chp->ch_queue->queue_freeze++;
1202 1.1 kiyohara wakeup(&chp->ch_thread);
1203 1.1 kiyohara return;
1204 1.1 kiyohara }
1205 1.1 kiyohara if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive,
1206 1.1 kiyohara (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) {
1207 1.1 kiyohara mvsata_bio_done(chp, xfer);
1208 1.1 kiyohara return;
1209 1.1 kiyohara }
1210 1.1 kiyohara }
1211 1.1 kiyohara
1212 1.1 kiyohara /* Initiate command! */
1213 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1214 1.1 kiyohara switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) {
1215 1.1 kiyohara case WDCWAIT_OK:
1216 1.1 kiyohara break;
1217 1.1 kiyohara case WDCWAIT_TOUT:
1218 1.1 kiyohara goto timeout;
1219 1.1 kiyohara case WDCWAIT_THR:
1220 1.1 kiyohara return;
1221 1.1 kiyohara }
1222 1.1 kiyohara if (ata_bio->flags & ATA_LBA48)
1223 1.29 jakllsch wdccommandext(chp, 0, atacmd_to48(cmd),
1224 1.25 jakllsch ata_bio->blkno, nblks, 0, WDSD_LBA);
1225 1.1 kiyohara else
1226 1.29 jakllsch wdccommand(chp, 0, cmd, cyl,
1227 1.1 kiyohara head, sect, nblks,
1228 1.34 christos (ata_bio->lp->d_type == DKTYPE_ST506) ?
1229 1.1 kiyohara ata_bio->lp->d_precompcyl / 4 : 0);
1230 1.1 kiyohara
1231 1.1 kiyohara /* start timeout machinery */
1232 1.1 kiyohara if ((xfer->c_flags & C_POLL) == 0)
1233 1.1 kiyohara callout_reset(&chp->ch_callout,
1234 1.1 kiyohara ATA_DELAY / 1000 * hz, wdctimeout, chp);
1235 1.1 kiyohara } else if (ata_bio->nblks > 1) {
1236 1.1 kiyohara /* The number of blocks in the last stretch may be smaller. */
1237 1.1 kiyohara nblks = xfer->c_bcount / ata_bio->lp->d_secsize;
1238 1.1 kiyohara if (ata_bio->nblks > nblks) {
1239 1.1 kiyohara ata_bio->nblks = nblks;
1240 1.1 kiyohara ata_bio->nbytes = xfer->c_bcount;
1241 1.1 kiyohara }
1242 1.1 kiyohara }
1243 1.1 kiyohara /* If this was a write and not using DMA, push the data. */
1244 1.1 kiyohara if ((ata_bio->flags & ATA_READ) == 0) {
1245 1.1 kiyohara /*
1246 1.1 kiyohara * we have to busy-wait here, we can't rely on running in
1247 1.1 kiyohara * thread context.
1248 1.1 kiyohara */
1249 1.1 kiyohara if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) {
1250 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1251 1.1 kiyohara "channel %d: drive %d timeout waiting for DRQ,"
1252 1.1 kiyohara " st=0x%02x, err=0x%02x\n",
1253 1.1 kiyohara chp->ch_channel, xfer->c_drive, chp->ch_status,
1254 1.1 kiyohara chp->ch_error);
1255 1.1 kiyohara ata_bio->error = TIMEOUT;
1256 1.1 kiyohara mvsata_bio_done(chp, xfer);
1257 1.1 kiyohara return;
1258 1.1 kiyohara }
1259 1.1 kiyohara if (chp->ch_status & WDCS_ERR) {
1260 1.1 kiyohara ata_bio->error = ERROR;
1261 1.1 kiyohara ata_bio->r_error = chp->ch_error;
1262 1.1 kiyohara mvsata_bio_done(chp, xfer);
1263 1.1 kiyohara return;
1264 1.1 kiyohara }
1265 1.1 kiyohara
1266 1.1 kiyohara wdc->dataout_pio(chp, drvp->drive_flags,
1267 1.1 kiyohara (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes);
1268 1.1 kiyohara }
1269 1.1 kiyohara
1270 1.1 kiyohara intr:
1271 1.1 kiyohara /* Wait for IRQ (either real or polled) */
1272 1.1 kiyohara if ((ata_bio->flags & ATA_POLL) == 0) {
1273 1.1 kiyohara chp->ch_flags |= ATACH_IRQ_WAIT;
1274 1.1 kiyohara } else {
1275 1.1 kiyohara /* Wait for at last 400ns for status bit to be valid */
1276 1.1 kiyohara delay(1);
1277 1.1 kiyohara if (chp->ch_flags & ATACH_DMA_WAIT) {
1278 1.1 kiyohara mvsata_edma_wait(mvport, xfer, ATA_DELAY);
1279 1.1 kiyohara sc->sc_enable_intr(mvport, 1 /*on*/);
1280 1.1 kiyohara chp->ch_flags &= ~ATACH_DMA_WAIT;
1281 1.1 kiyohara }
1282 1.1 kiyohara mvsata_bio_intr(chp, xfer, 0);
1283 1.1 kiyohara if ((ata_bio->flags & ATA_ITSDONE) == 0)
1284 1.1 kiyohara goto again;
1285 1.1 kiyohara }
1286 1.1 kiyohara return;
1287 1.1 kiyohara
1288 1.1 kiyohara timeout:
1289 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1290 1.1 kiyohara "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n",
1291 1.1 kiyohara chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error);
1292 1.1 kiyohara ata_bio->error = TIMEOUT;
1293 1.1 kiyohara mvsata_bio_done(chp, xfer);
1294 1.1 kiyohara return;
1295 1.1 kiyohara }
1296 1.1 kiyohara
1297 1.1 kiyohara static int
1298 1.1 kiyohara mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1299 1.1 kiyohara {
1300 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
1301 1.1 kiyohara struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1302 1.1 kiyohara struct ata_bio *ata_bio = xfer->c_cmd;
1303 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
1304 1.1 kiyohara
1305 1.1 kiyohara DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n",
1306 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
1307 1.1 kiyohara
1308 1.10 jakllsch chp->ch_flags &= ~(ATACH_IRQ_WAIT|ATACH_DMA_WAIT);
1309 1.10 jakllsch
1310 1.1 kiyohara /*
1311 1.10 jakllsch * If we missed an interrupt transfer, reset and restart.
1312 1.1 kiyohara * Don't try to continue transfer, we may have missed cycles.
1313 1.1 kiyohara */
1314 1.1 kiyohara if (xfer->c_flags & C_TIMEOU) {
1315 1.1 kiyohara ata_bio->error = TIMEOUT;
1316 1.1 kiyohara mvsata_bio_done(chp, xfer);
1317 1.1 kiyohara return 1;
1318 1.1 kiyohara }
1319 1.1 kiyohara
1320 1.28 jakllsch /* Is it not a transfer, but a control operation? */
1321 1.28 jakllsch if (!(xfer->c_flags & C_DMA) && drvp->state < READY) {
1322 1.28 jakllsch aprint_error_dev(atac->atac_dev,
1323 1.28 jakllsch "channel %d: drive %d bad state %d in mvsata_bio_intr\n",
1324 1.28 jakllsch chp->ch_channel, xfer->c_drive, drvp->state);
1325 1.28 jakllsch panic("mvsata_bio_intr: bad state");
1326 1.28 jakllsch }
1327 1.28 jakllsch
1328 1.1 kiyohara /* Ack interrupt done by wdc_wait_for_unbusy */
1329 1.1 kiyohara if (!(xfer->c_flags & C_DMA) &&
1330 1.1 kiyohara (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL)
1331 1.1 kiyohara == WDCWAIT_TOUT)) {
1332 1.1 kiyohara if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1333 1.1 kiyohara return 0; /* IRQ was not for us */
1334 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1335 1.1 kiyohara "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n",
1336 1.1 kiyohara chp->ch_channel, xfer->c_drive, xfer->c_bcount,
1337 1.1 kiyohara xfer->c_skip);
1338 1.1 kiyohara ata_bio->error = TIMEOUT;
1339 1.1 kiyohara mvsata_bio_done(chp, xfer);
1340 1.1 kiyohara return 1;
1341 1.1 kiyohara }
1342 1.1 kiyohara
1343 1.1 kiyohara if (xfer->c_flags & C_DMA) {
1344 1.1 kiyohara if (ata_bio->error == NOERROR)
1345 1.1 kiyohara goto end;
1346 1.1 kiyohara if (ata_bio->error == ERR_DMA)
1347 1.1 kiyohara ata_dmaerr(drvp,
1348 1.1 kiyohara (xfer->c_flags & C_POLL) ? AT_POLL : 0);
1349 1.1 kiyohara }
1350 1.1 kiyohara
1351 1.1 kiyohara /* if we had an error, end */
1352 1.1 kiyohara if (ata_bio->error != NOERROR) {
1353 1.1 kiyohara mvsata_bio_done(chp, xfer);
1354 1.1 kiyohara return 1;
1355 1.1 kiyohara }
1356 1.1 kiyohara
1357 1.1 kiyohara /* If this was a read and not using DMA, fetch the data. */
1358 1.1 kiyohara if ((ata_bio->flags & ATA_READ) != 0) {
1359 1.1 kiyohara if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) {
1360 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1361 1.1 kiyohara "channel %d: drive %d read intr before drq\n",
1362 1.1 kiyohara chp->ch_channel, xfer->c_drive);
1363 1.1 kiyohara ata_bio->error = TIMEOUT;
1364 1.1 kiyohara mvsata_bio_done(chp, xfer);
1365 1.1 kiyohara return 1;
1366 1.1 kiyohara }
1367 1.1 kiyohara wdc->datain_pio(chp, drvp->drive_flags,
1368 1.1 kiyohara (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes);
1369 1.1 kiyohara }
1370 1.1 kiyohara
1371 1.1 kiyohara end:
1372 1.1 kiyohara ata_bio->blkno += ata_bio->nblks;
1373 1.1 kiyohara ata_bio->blkdone += ata_bio->nblks;
1374 1.1 kiyohara xfer->c_skip += ata_bio->nbytes;
1375 1.1 kiyohara xfer->c_bcount -= ata_bio->nbytes;
1376 1.1 kiyohara /* See if this transfer is complete. */
1377 1.1 kiyohara if (xfer->c_bcount > 0) {
1378 1.1 kiyohara if ((ata_bio->flags & ATA_POLL) == 0)
1379 1.1 kiyohara /* Start the next operation */
1380 1.1 kiyohara mvsata_bio_start(chp, xfer);
1381 1.1 kiyohara else
1382 1.1 kiyohara /* Let mvsata_bio_start do the loop */
1383 1.1 kiyohara return 1;
1384 1.1 kiyohara } else { /* Done with this transfer */
1385 1.1 kiyohara ata_bio->error = NOERROR;
1386 1.1 kiyohara mvsata_bio_done(chp, xfer);
1387 1.1 kiyohara }
1388 1.1 kiyohara return 1;
1389 1.1 kiyohara }
1390 1.1 kiyohara
1391 1.1 kiyohara static void
1392 1.1 kiyohara mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1393 1.1 kiyohara {
1394 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1395 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
1396 1.1 kiyohara struct ata_bio *ata_bio = xfer->c_cmd;
1397 1.1 kiyohara int drive = xfer->c_drive;
1398 1.1 kiyohara
1399 1.1 kiyohara DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n",
1400 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
1401 1.1 kiyohara
1402 1.1 kiyohara /* EDMA restart, if enabled */
1403 1.1 kiyohara if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) {
1404 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
1405 1.1 kiyohara mvsata_edma_enable(mvport);
1406 1.1 kiyohara }
1407 1.1 kiyohara
1408 1.1 kiyohara ata_free_xfer(chp, xfer);
1409 1.1 kiyohara
1410 1.1 kiyohara ata_bio->flags |= ATA_ITSDONE;
1411 1.1 kiyohara switch (reason) {
1412 1.1 kiyohara case KILL_GONE:
1413 1.1 kiyohara ata_bio->error = ERR_NODEV;
1414 1.1 kiyohara break;
1415 1.1 kiyohara case KILL_RESET:
1416 1.1 kiyohara ata_bio->error = ERR_RESET;
1417 1.1 kiyohara break;
1418 1.1 kiyohara default:
1419 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1420 1.1 kiyohara "mvsata_bio_kill_xfer: unknown reason %d\n", reason);
1421 1.1 kiyohara panic("mvsata_bio_kill_xfer");
1422 1.1 kiyohara }
1423 1.1 kiyohara ata_bio->r_error = WDCE_ABRT;
1424 1.1 kiyohara (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1425 1.1 kiyohara }
1426 1.1 kiyohara
1427 1.1 kiyohara static void
1428 1.1 kiyohara mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer)
1429 1.1 kiyohara {
1430 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1431 1.1 kiyohara struct ata_bio *ata_bio = xfer->c_cmd;
1432 1.1 kiyohara int drive = xfer->c_drive;
1433 1.1 kiyohara
1434 1.1 kiyohara DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n",
1435 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive,
1436 1.1 kiyohara (u_int)xfer->c_flags));
1437 1.1 kiyohara
1438 1.1 kiyohara callout_stop(&chp->ch_callout);
1439 1.1 kiyohara
1440 1.1 kiyohara /* EDMA restart, if enabled */
1441 1.1 kiyohara if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) {
1442 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
1443 1.1 kiyohara mvsata_edma_enable(mvport);
1444 1.1 kiyohara }
1445 1.1 kiyohara
1446 1.1 kiyohara /* feed back residual bcount to our caller */
1447 1.1 kiyohara ata_bio->bcount = xfer->c_bcount;
1448 1.1 kiyohara
1449 1.1 kiyohara /* mark controller inactive and free xfer */
1450 1.10 jakllsch KASSERT(chp->ch_queue->active_xfer != NULL);
1451 1.1 kiyohara chp->ch_queue->active_xfer = NULL;
1452 1.1 kiyohara ata_free_xfer(chp, xfer);
1453 1.1 kiyohara
1454 1.24 bouyer if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1455 1.1 kiyohara ata_bio->error = ERR_NODEV;
1456 1.24 bouyer chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1457 1.1 kiyohara wakeup(&chp->ch_queue->active_xfer);
1458 1.1 kiyohara }
1459 1.1 kiyohara ata_bio->flags |= ATA_ITSDONE;
1460 1.1 kiyohara (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1461 1.1 kiyohara atastart(chp);
1462 1.1 kiyohara }
1463 1.1 kiyohara
1464 1.1 kiyohara static int
1465 1.1 kiyohara mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive,
1466 1.1 kiyohara int flags)
1467 1.1 kiyohara {
1468 1.1 kiyohara struct ata_channel *chp = &mvport->port_ata_channel;
1469 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
1470 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[drive];
1471 1.1 kiyohara const char *errstring;
1472 1.1 kiyohara
1473 1.31 jakllsch flags |= AT_POLL; /* XXX */
1474 1.31 jakllsch
1475 1.1 kiyohara /*
1476 1.1 kiyohara * disable interrupts, all commands here should be quick
1477 1.4 snj * enough to be able to poll, and we don't go here that often
1478 1.1 kiyohara */
1479 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS);
1480 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1481 1.1 kiyohara DELAY(10);
1482 1.1 kiyohara errstring = "wait";
1483 1.1 kiyohara if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1484 1.1 kiyohara goto ctrltimeout;
1485 1.29 jakllsch wdccommandshort(chp, 0, WDCC_RECAL);
1486 1.29 jakllsch /* Wait for at least 400ns for status bit to be valid */
1487 1.1 kiyohara DELAY(1);
1488 1.1 kiyohara errstring = "recal";
1489 1.1 kiyohara if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1490 1.1 kiyohara goto ctrltimeout;
1491 1.1 kiyohara if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1492 1.1 kiyohara goto ctrlerror;
1493 1.1 kiyohara /* Don't try to set modes if controller can't be adjusted */
1494 1.1 kiyohara if (atac->atac_set_modes == NULL)
1495 1.1 kiyohara goto geometry;
1496 1.1 kiyohara /* Also don't try if the drive didn't report its mode */
1497 1.24 bouyer if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0)
1498 1.1 kiyohara goto geometry;
1499 1.29 jakllsch wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1500 1.1 kiyohara 0x08 | drvp->PIO_mode, WDSF_SET_MODE);
1501 1.1 kiyohara errstring = "piomode";
1502 1.1 kiyohara if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1503 1.1 kiyohara goto ctrltimeout;
1504 1.1 kiyohara if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1505 1.1 kiyohara goto ctrlerror;
1506 1.24 bouyer if (drvp->drive_flags & ATA_DRIVE_UDMA)
1507 1.29 jakllsch wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1508 1.1 kiyohara 0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
1509 1.24 bouyer else if (drvp->drive_flags & ATA_DRIVE_DMA)
1510 1.29 jakllsch wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1511 1.1 kiyohara 0x20 | drvp->DMA_mode, WDSF_SET_MODE);
1512 1.1 kiyohara else
1513 1.1 kiyohara goto geometry;
1514 1.1 kiyohara errstring = "dmamode";
1515 1.1 kiyohara if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1516 1.1 kiyohara goto ctrltimeout;
1517 1.1 kiyohara if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1518 1.1 kiyohara goto ctrlerror;
1519 1.1 kiyohara geometry:
1520 1.1 kiyohara if (ata_bio->flags & ATA_LBA)
1521 1.1 kiyohara goto multimode;
1522 1.29 jakllsch wdccommand(chp, 0, WDCC_IDP, ata_bio->lp->d_ncylinders,
1523 1.1 kiyohara ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors,
1524 1.34 christos (ata_bio->lp->d_type == DKTYPE_ST506) ?
1525 1.1 kiyohara ata_bio->lp->d_precompcyl / 4 : 0);
1526 1.1 kiyohara errstring = "geometry";
1527 1.1 kiyohara if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1528 1.1 kiyohara goto ctrltimeout;
1529 1.1 kiyohara if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1530 1.1 kiyohara goto ctrlerror;
1531 1.1 kiyohara multimode:
1532 1.1 kiyohara if (ata_bio->multi == 1)
1533 1.1 kiyohara goto ready;
1534 1.29 jakllsch wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0);
1535 1.1 kiyohara errstring = "setmulti";
1536 1.1 kiyohara if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags))
1537 1.1 kiyohara goto ctrltimeout;
1538 1.1 kiyohara if (chp->ch_status & (WDCS_ERR | WDCS_DWF))
1539 1.1 kiyohara goto ctrlerror;
1540 1.1 kiyohara ready:
1541 1.1 kiyohara drvp->state = READY;
1542 1.1 kiyohara /*
1543 1.1 kiyohara * The drive is usable now
1544 1.1 kiyohara */
1545 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1546 1.1 kiyohara delay(10); /* some drives need a little delay here */
1547 1.1 kiyohara return 0;
1548 1.1 kiyohara
1549 1.1 kiyohara ctrltimeout:
1550 1.1 kiyohara aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n",
1551 1.1 kiyohara chp->ch_channel, drive, errstring);
1552 1.1 kiyohara ata_bio->error = TIMEOUT;
1553 1.1 kiyohara goto ctrldone;
1554 1.1 kiyohara ctrlerror:
1555 1.1 kiyohara aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ",
1556 1.1 kiyohara chp->ch_channel, drive, errstring);
1557 1.1 kiyohara if (chp->ch_status & WDCS_DWF) {
1558 1.1 kiyohara aprint_error("drive fault\n");
1559 1.1 kiyohara ata_bio->error = ERR_DF;
1560 1.1 kiyohara } else {
1561 1.1 kiyohara aprint_error("error (%x)\n", chp->ch_error);
1562 1.1 kiyohara ata_bio->r_error = chp->ch_error;
1563 1.1 kiyohara ata_bio->error = ERROR;
1564 1.1 kiyohara }
1565 1.1 kiyohara ctrldone:
1566 1.1 kiyohara drvp->state = 0;
1567 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1568 1.1 kiyohara return -1;
1569 1.1 kiyohara }
1570 1.1 kiyohara
1571 1.1 kiyohara static void
1572 1.1 kiyohara mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
1573 1.1 kiyohara {
1574 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1575 1.1 kiyohara int drive = xfer->c_drive;
1576 1.1 kiyohara int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
1577 1.1 kiyohara struct ata_command *ata_c = xfer->c_cmd;
1578 1.1 kiyohara
1579 1.1 kiyohara DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n",
1580 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive));
1581 1.1 kiyohara
1582 1.1 kiyohara /* First, EDMA disable, if enabled this channel. */
1583 1.1 kiyohara if (mvport->port_edmamode != nodma)
1584 1.1 kiyohara mvsata_edma_disable(mvport, 10 /* ms */, wait_flags);
1585 1.1 kiyohara
1586 1.29 jakllsch mvsata_pmp_select(mvport, drive);
1587 1.29 jakllsch
1588 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1589 1.1 kiyohara switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
1590 1.1 kiyohara ata_c->r_st_bmask, ata_c->timeout, wait_flags)) {
1591 1.1 kiyohara case WDCWAIT_OK:
1592 1.1 kiyohara break;
1593 1.1 kiyohara case WDCWAIT_TOUT:
1594 1.1 kiyohara ata_c->flags |= AT_TIMEOU;
1595 1.1 kiyohara mvsata_wdc_cmd_done(chp, xfer);
1596 1.1 kiyohara return;
1597 1.1 kiyohara case WDCWAIT_THR:
1598 1.1 kiyohara return;
1599 1.1 kiyohara }
1600 1.1 kiyohara if (ata_c->flags & AT_POLL)
1601 1.1 kiyohara /* polled command, disable interrupts */
1602 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS);
1603 1.15 jakllsch if ((ata_c->flags & AT_LBA48) != 0) {
1604 1.29 jakllsch wdccommandext(chp, 0, ata_c->r_command,
1605 1.25 jakllsch ata_c->r_lba, ata_c->r_count, ata_c->r_features,
1606 1.25 jakllsch ata_c->r_device & ~0x10);
1607 1.15 jakllsch } else {
1608 1.29 jakllsch wdccommand(chp, 0, ata_c->r_command,
1609 1.15 jakllsch (ata_c->r_lba >> 8) & 0xffff,
1610 1.15 jakllsch (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) |
1611 1.15 jakllsch ((ata_c->r_lba >> 24) & 0x0f),
1612 1.15 jakllsch ata_c->r_lba & 0xff,
1613 1.15 jakllsch ata_c->r_count & 0xff,
1614 1.15 jakllsch ata_c->r_features & 0xff);
1615 1.15 jakllsch }
1616 1.1 kiyohara
1617 1.1 kiyohara if ((ata_c->flags & AT_POLL) == 0) {
1618 1.1 kiyohara chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1619 1.1 kiyohara callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz,
1620 1.1 kiyohara wdctimeout, chp);
1621 1.1 kiyohara return;
1622 1.1 kiyohara }
1623 1.1 kiyohara /*
1624 1.1 kiyohara * Polled command. Wait for drive ready or drq. Done in intr().
1625 1.1 kiyohara * Wait for at last 400ns for status bit to be valid.
1626 1.1 kiyohara */
1627 1.1 kiyohara delay(10); /* 400ns delay */
1628 1.1 kiyohara mvsata_wdc_cmd_intr(chp, xfer, 0);
1629 1.1 kiyohara }
1630 1.1 kiyohara
1631 1.1 kiyohara static int
1632 1.1 kiyohara mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1633 1.1 kiyohara {
1634 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1635 1.1 kiyohara struct wdc_softc *wdc = CHAN_TO_WDC(chp);
1636 1.1 kiyohara struct ata_command *ata_c = xfer->c_cmd;
1637 1.1 kiyohara int bcount = ata_c->bcount;
1638 1.1 kiyohara char *data = ata_c->data;
1639 1.1 kiyohara int wflags;
1640 1.1 kiyohara int drive_flags;
1641 1.1 kiyohara
1642 1.1 kiyohara if (ata_c->r_command == WDCC_IDENTIFY ||
1643 1.1 kiyohara ata_c->r_command == ATAPI_IDENTIFY_DEVICE)
1644 1.1 kiyohara /*
1645 1.1 kiyohara * The IDENTIFY data has been designed as an array of
1646 1.1 kiyohara * u_int16_t, so we can byteswap it on the fly.
1647 1.1 kiyohara * Historically it's what we have always done so keeping it
1648 1.1 kiyohara * here ensure binary backward compatibility.
1649 1.1 kiyohara */
1650 1.24 bouyer drive_flags = ATA_DRIVE_NOSTREAM |
1651 1.1 kiyohara chp->ch_drive[xfer->c_drive].drive_flags;
1652 1.1 kiyohara else
1653 1.1 kiyohara /*
1654 1.1 kiyohara * Other data structure are opaque and should be transfered
1655 1.1 kiyohara * as is.
1656 1.1 kiyohara */
1657 1.1 kiyohara drive_flags = chp->ch_drive[xfer->c_drive].drive_flags;
1658 1.1 kiyohara
1659 1.1 kiyohara if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL))
1660 1.1 kiyohara /* both wait and poll, we can tsleep here */
1661 1.1 kiyohara wflags = AT_WAIT | AT_POLL;
1662 1.1 kiyohara else
1663 1.1 kiyohara wflags = AT_POLL;
1664 1.1 kiyohara
1665 1.1 kiyohara again:
1666 1.1 kiyohara DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n",
1667 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive));
1668 1.1 kiyohara
1669 1.1 kiyohara /*
1670 1.1 kiyohara * after a ATAPI_SOFT_RESET, the device will have released the bus.
1671 1.1 kiyohara * Reselect again, it doesn't hurt for others commands, and the time
1672 1.13 jakllsch * penalty for the extra register write is acceptable,
1673 1.13 jakllsch * wdc_exec_command() isn't called often (mostly for autoconfig)
1674 1.1 kiyohara */
1675 1.15 jakllsch if ((xfer->c_flags & C_ATAPI) != 0) {
1676 1.15 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1677 1.15 jakllsch }
1678 1.1 kiyohara if ((ata_c->flags & AT_XFDONE) != 0) {
1679 1.1 kiyohara /*
1680 1.1 kiyohara * We have completed a data xfer. The drive should now be
1681 1.1 kiyohara * in its initial state
1682 1.1 kiyohara */
1683 1.1 kiyohara if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
1684 1.1 kiyohara ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0,
1685 1.1 kiyohara wflags) == WDCWAIT_TOUT) {
1686 1.1 kiyohara if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1687 1.1 kiyohara return 0; /* IRQ was not for us */
1688 1.1 kiyohara ata_c->flags |= AT_TIMEOU;
1689 1.1 kiyohara }
1690 1.1 kiyohara goto out;
1691 1.1 kiyohara }
1692 1.1 kiyohara if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask,
1693 1.1 kiyohara (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) {
1694 1.1 kiyohara if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1695 1.1 kiyohara return 0; /* IRQ was not for us */
1696 1.1 kiyohara ata_c->flags |= AT_TIMEOU;
1697 1.1 kiyohara goto out;
1698 1.1 kiyohara }
1699 1.33 kiyohara delay(20); /* XXXXX: Delay more times. */
1700 1.1 kiyohara if (ata_c->flags & AT_READ) {
1701 1.1 kiyohara if ((chp->ch_status & WDCS_DRQ) == 0) {
1702 1.1 kiyohara ata_c->flags |= AT_TIMEOU;
1703 1.1 kiyohara goto out;
1704 1.1 kiyohara }
1705 1.1 kiyohara wdc->datain_pio(chp, drive_flags, data, bcount);
1706 1.1 kiyohara /* at this point the drive should be in its initial state */
1707 1.1 kiyohara ata_c->flags |= AT_XFDONE;
1708 1.1 kiyohara /*
1709 1.1 kiyohara * XXX checking the status register again here cause some
1710 1.1 kiyohara * hardware to timeout.
1711 1.1 kiyohara */
1712 1.1 kiyohara } else if (ata_c->flags & AT_WRITE) {
1713 1.1 kiyohara if ((chp->ch_status & WDCS_DRQ) == 0) {
1714 1.1 kiyohara ata_c->flags |= AT_TIMEOU;
1715 1.1 kiyohara goto out;
1716 1.1 kiyohara }
1717 1.1 kiyohara wdc->dataout_pio(chp, drive_flags, data, bcount);
1718 1.1 kiyohara ata_c->flags |= AT_XFDONE;
1719 1.1 kiyohara if ((ata_c->flags & AT_POLL) == 0) {
1720 1.1 kiyohara chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */
1721 1.1 kiyohara callout_reset(&chp->ch_callout,
1722 1.1 kiyohara mstohz(ata_c->timeout), wdctimeout, chp);
1723 1.1 kiyohara return 1;
1724 1.1 kiyohara } else
1725 1.1 kiyohara goto again;
1726 1.1 kiyohara }
1727 1.1 kiyohara out:
1728 1.1 kiyohara mvsata_wdc_cmd_done(chp, xfer);
1729 1.1 kiyohara return 1;
1730 1.1 kiyohara }
1731 1.1 kiyohara
1732 1.1 kiyohara static void
1733 1.1 kiyohara mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer,
1734 1.1 kiyohara int reason)
1735 1.1 kiyohara {
1736 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1737 1.1 kiyohara struct ata_command *ata_c = xfer->c_cmd;
1738 1.1 kiyohara
1739 1.1 kiyohara DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n",
1740 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive));
1741 1.1 kiyohara
1742 1.1 kiyohara switch (reason) {
1743 1.1 kiyohara case KILL_GONE:
1744 1.1 kiyohara ata_c->flags |= AT_GONE;
1745 1.1 kiyohara break;
1746 1.1 kiyohara case KILL_RESET:
1747 1.1 kiyohara ata_c->flags |= AT_RESET;
1748 1.1 kiyohara break;
1749 1.1 kiyohara default:
1750 1.1 kiyohara aprint_error_dev(MVSATA_DEV2(mvport),
1751 1.1 kiyohara "mvsata_cmd_kill_xfer: unknown reason %d\n", reason);
1752 1.1 kiyohara panic("mvsata_cmd_kill_xfer");
1753 1.1 kiyohara }
1754 1.1 kiyohara mvsata_wdc_cmd_done_end(chp, xfer);
1755 1.1 kiyohara }
1756 1.1 kiyohara
1757 1.1 kiyohara static void
1758 1.1 kiyohara mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer)
1759 1.1 kiyohara {
1760 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1761 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
1762 1.1 kiyohara struct ata_command *ata_c = xfer->c_cmd;
1763 1.1 kiyohara
1764 1.1 kiyohara DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n",
1765 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
1766 1.1 kiyohara ata_c->flags));
1767 1.1 kiyohara
1768 1.1 kiyohara if (chp->ch_status & WDCS_DWF)
1769 1.1 kiyohara ata_c->flags |= AT_DF;
1770 1.1 kiyohara if (chp->ch_status & WDCS_ERR) {
1771 1.1 kiyohara ata_c->flags |= AT_ERROR;
1772 1.1 kiyohara ata_c->r_error = chp->ch_error;
1773 1.1 kiyohara }
1774 1.1 kiyohara if ((ata_c->flags & AT_READREG) != 0 &&
1775 1.1 kiyohara device_is_active(atac->atac_dev) &&
1776 1.1 kiyohara (ata_c->flags & (AT_ERROR | AT_DF)) == 0) {
1777 1.15 jakllsch ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS);
1778 1.15 jakllsch ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE);
1779 1.1 kiyohara ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC);
1780 1.15 jakllsch ata_c->r_lba =
1781 1.15 jakllsch (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0;
1782 1.15 jakllsch ata_c->r_lba |=
1783 1.15 jakllsch (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8;
1784 1.15 jakllsch ata_c->r_lba |=
1785 1.15 jakllsch (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16;
1786 1.15 jakllsch ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H);
1787 1.15 jakllsch if ((ata_c->flags & AT_LBA48) != 0) {
1788 1.15 jakllsch if ((ata_c->flags & AT_POLL) != 0) {
1789 1.15 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1790 1.15 jakllsch WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS);
1791 1.15 jakllsch } else {
1792 1.15 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1793 1.15 jakllsch WDCTL_HOB|WDCTL_4BIT);
1794 1.15 jakllsch }
1795 1.15 jakllsch ata_c->r_count |=
1796 1.15 jakllsch MVSATA_WDC_READ_1(mvport, SRB_SC) << 8;
1797 1.24 bouyer ata_c->r_lba |=
1798 1.15 jakllsch (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24;
1799 1.15 jakllsch ata_c->r_lba |=
1800 1.15 jakllsch (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32;
1801 1.15 jakllsch ata_c->r_lba |=
1802 1.15 jakllsch (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40;
1803 1.15 jakllsch if ((ata_c->flags & AT_POLL) != 0) {
1804 1.15 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1805 1.15 jakllsch WDCTL_4BIT|WDCTL_IDS);
1806 1.15 jakllsch } else {
1807 1.15 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_CAS,
1808 1.15 jakllsch WDCTL_4BIT);
1809 1.15 jakllsch }
1810 1.15 jakllsch } else {
1811 1.15 jakllsch ata_c->r_lba |=
1812 1.15 jakllsch (uint64_t)(ata_c->r_device & 0x0f) << 24;
1813 1.15 jakllsch }
1814 1.1 kiyohara }
1815 1.1 kiyohara callout_stop(&chp->ch_callout);
1816 1.1 kiyohara chp->ch_queue->active_xfer = NULL;
1817 1.1 kiyohara if (ata_c->flags & AT_POLL) {
1818 1.1 kiyohara /* enable interrupts */
1819 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1820 1.1 kiyohara delay(10); /* some drives need a little delay here */
1821 1.1 kiyohara }
1822 1.24 bouyer if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1823 1.1 kiyohara mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE);
1824 1.24 bouyer chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1825 1.1 kiyohara wakeup(&chp->ch_queue->active_xfer);
1826 1.1 kiyohara } else
1827 1.1 kiyohara mvsata_wdc_cmd_done_end(chp, xfer);
1828 1.1 kiyohara }
1829 1.1 kiyohara
1830 1.1 kiyohara static void
1831 1.1 kiyohara mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer)
1832 1.1 kiyohara {
1833 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1834 1.1 kiyohara struct ata_command *ata_c = xfer->c_cmd;
1835 1.1 kiyohara
1836 1.1 kiyohara /* EDMA restart, if enabled */
1837 1.1 kiyohara if (mvport->port_edmamode != nodma) {
1838 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
1839 1.1 kiyohara mvsata_edma_enable(mvport);
1840 1.1 kiyohara }
1841 1.1 kiyohara
1842 1.1 kiyohara ata_c->flags |= AT_DONE;
1843 1.1 kiyohara ata_free_xfer(chp, xfer);
1844 1.1 kiyohara if (ata_c->flags & AT_WAIT)
1845 1.1 kiyohara wakeup(ata_c);
1846 1.1 kiyohara else if (ata_c->callback)
1847 1.1 kiyohara ata_c->callback(ata_c->callback_arg);
1848 1.1 kiyohara atastart(chp);
1849 1.1 kiyohara
1850 1.1 kiyohara return;
1851 1.1 kiyohara }
1852 1.1 kiyohara
1853 1.1 kiyohara #if NATAPIBUS > 0
1854 1.1 kiyohara static void
1855 1.1 kiyohara mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
1856 1.1 kiyohara {
1857 1.1 kiyohara struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac;
1858 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
1859 1.1 kiyohara struct atac_softc *atac = &sc->sc_wdcdev.sc_atac;
1860 1.1 kiyohara struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1861 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
1862 1.1 kiyohara const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0;
1863 1.1 kiyohara const char *errstring;
1864 1.1 kiyohara
1865 1.1 kiyohara DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n",
1866 1.1 kiyohara device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
1867 1.1 kiyohara xfer->c_drive, sc_xfer->xs_control));
1868 1.1 kiyohara
1869 1.1 kiyohara if (mvport->port_edmamode != nodma)
1870 1.1 kiyohara mvsata_edma_disable(mvport, 10 /* ms */, wait_flags);
1871 1.1 kiyohara
1872 1.29 jakllsch mvsata_pmp_select(mvport, xfer->c_drive);
1873 1.29 jakllsch
1874 1.1 kiyohara if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER))
1875 1.1 kiyohara drvp->n_xfers++;
1876 1.1 kiyohara
1877 1.1 kiyohara /* Do control operations specially. */
1878 1.1 kiyohara if (__predict_false(drvp->state < READY)) {
1879 1.1 kiyohara /* If it's not a polled command, we need the kernel thread */
1880 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) {
1881 1.1 kiyohara chp->ch_queue->queue_freeze++;
1882 1.1 kiyohara wakeup(&chp->ch_thread);
1883 1.1 kiyohara return;
1884 1.1 kiyohara }
1885 1.1 kiyohara /*
1886 1.1 kiyohara * disable interrupts, all commands here should be quick
1887 1.4 snj * enough to be able to poll, and we don't go here that often
1888 1.1 kiyohara */
1889 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS);
1890 1.1 kiyohara
1891 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1892 1.1 kiyohara /* Don't try to set mode if controller can't be adjusted */
1893 1.1 kiyohara if (atac->atac_set_modes == NULL)
1894 1.1 kiyohara goto ready;
1895 1.1 kiyohara /* Also don't try if the drive didn't report its mode */
1896 1.24 bouyer if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0)
1897 1.1 kiyohara goto ready;
1898 1.1 kiyohara errstring = "unbusy";
1899 1.1 kiyohara if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags))
1900 1.1 kiyohara goto timeout;
1901 1.29 jakllsch wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1902 1.1 kiyohara 0x08 | drvp->PIO_mode, WDSF_SET_MODE);
1903 1.1 kiyohara errstring = "piomode";
1904 1.1 kiyohara if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags))
1905 1.1 kiyohara goto timeout;
1906 1.1 kiyohara if (chp->ch_status & WDCS_ERR) {
1907 1.1 kiyohara if (chp->ch_error == WDCE_ABRT) {
1908 1.1 kiyohara /*
1909 1.1 kiyohara * Some ATAPI drives reject PIO settings.
1910 1.1 kiyohara * Fall back to PIO mode 3 since that's the
1911 1.1 kiyohara * minimum for ATAPI.
1912 1.1 kiyohara */
1913 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1914 1.1 kiyohara "channel %d drive %d: PIO mode %d rejected,"
1915 1.1 kiyohara " falling back to PIO mode 3\n",
1916 1.1 kiyohara chp->ch_channel, xfer->c_drive,
1917 1.1 kiyohara drvp->PIO_mode);
1918 1.1 kiyohara if (drvp->PIO_mode > 3)
1919 1.1 kiyohara drvp->PIO_mode = 3;
1920 1.1 kiyohara } else
1921 1.1 kiyohara goto error;
1922 1.1 kiyohara }
1923 1.24 bouyer if (drvp->drive_flags & ATA_DRIVE_UDMA)
1924 1.29 jakllsch wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1925 1.1 kiyohara 0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
1926 1.1 kiyohara else
1927 1.24 bouyer if (drvp->drive_flags & ATA_DRIVE_DMA)
1928 1.29 jakllsch wdccommand(chp, 0, SET_FEATURES, 0, 0, 0,
1929 1.1 kiyohara 0x20 | drvp->DMA_mode, WDSF_SET_MODE);
1930 1.1 kiyohara else
1931 1.1 kiyohara goto ready;
1932 1.1 kiyohara errstring = "dmamode";
1933 1.1 kiyohara if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags))
1934 1.1 kiyohara goto timeout;
1935 1.1 kiyohara if (chp->ch_status & WDCS_ERR) {
1936 1.1 kiyohara if (chp->ch_error == WDCE_ABRT) {
1937 1.24 bouyer if (drvp->drive_flags & ATA_DRIVE_UDMA)
1938 1.1 kiyohara goto error;
1939 1.1 kiyohara else {
1940 1.1 kiyohara /*
1941 1.1 kiyohara * The drive rejected our DMA setting.
1942 1.1 kiyohara * Fall back to mode 1.
1943 1.1 kiyohara */
1944 1.1 kiyohara aprint_error_dev(atac->atac_dev,
1945 1.1 kiyohara "channel %d drive %d:"
1946 1.1 kiyohara " DMA mode %d rejected,"
1947 1.1 kiyohara " falling back to DMA mode 0\n",
1948 1.1 kiyohara chp->ch_channel, xfer->c_drive,
1949 1.1 kiyohara drvp->DMA_mode);
1950 1.1 kiyohara if (drvp->DMA_mode > 0)
1951 1.1 kiyohara drvp->DMA_mode = 0;
1952 1.1 kiyohara }
1953 1.1 kiyohara } else
1954 1.1 kiyohara goto error;
1955 1.1 kiyohara }
1956 1.1 kiyohara ready:
1957 1.1 kiyohara drvp->state = READY;
1958 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
1959 1.1 kiyohara delay(10); /* some drives need a little delay here */
1960 1.1 kiyohara }
1961 1.1 kiyohara /* start timeout machinery */
1962 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
1963 1.1 kiyohara callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
1964 1.1 kiyohara wdctimeout, chp);
1965 1.1 kiyohara
1966 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
1967 1.1 kiyohara switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) {
1968 1.1 kiyohara case WDCWAIT_OK:
1969 1.1 kiyohara break;
1970 1.1 kiyohara case WDCWAIT_TOUT:
1971 1.1 kiyohara aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n",
1972 1.1 kiyohara chp->ch_status);
1973 1.1 kiyohara sc_xfer->error = XS_TIMEOUT;
1974 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
1975 1.1 kiyohara return;
1976 1.1 kiyohara case WDCWAIT_THR:
1977 1.1 kiyohara return;
1978 1.1 kiyohara }
1979 1.1 kiyohara
1980 1.1 kiyohara /*
1981 1.1 kiyohara * Even with WDCS_ERR, the device should accept a command packet
1982 1.1 kiyohara * Limit length to what can be stuffed into the cylinder register
1983 1.1 kiyohara * (16 bits). Some CD-ROMs seem to interpret '0' as 65536,
1984 1.1 kiyohara * but not all devices do that and it's not obvious from the
1985 1.1 kiyohara * ATAPI spec that that behaviour should be expected. If more
1986 1.1 kiyohara * data is necessary, multiple data transfer phases will be done.
1987 1.1 kiyohara */
1988 1.1 kiyohara
1989 1.29 jakllsch wdccommand(chp, 0, ATAPI_PKT_CMD,
1990 1.1 kiyohara xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0,
1991 1.1 kiyohara (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0);
1992 1.1 kiyohara
1993 1.1 kiyohara /*
1994 1.1 kiyohara * If there is no interrupt for CMD input, busy-wait for it (done in
1995 1.1 kiyohara * the interrupt routine. If it is a polled command, call the interrupt
1996 1.1 kiyohara * routine until command is done.
1997 1.1 kiyohara */
1998 1.1 kiyohara if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) !=
1999 1.1 kiyohara ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) {
2000 1.1 kiyohara /* Wait for at last 400ns for status bit to be valid */
2001 1.1 kiyohara DELAY(1);
2002 1.1 kiyohara mvsata_atapi_intr(chp, xfer, 0);
2003 1.1 kiyohara } else
2004 1.1 kiyohara chp->ch_flags |= ATACH_IRQ_WAIT;
2005 1.1 kiyohara if (sc_xfer->xs_control & XS_CTL_POLL) {
2006 1.1 kiyohara if (chp->ch_flags & ATACH_DMA_WAIT) {
2007 1.1 kiyohara wdc_dmawait(chp, xfer, sc_xfer->timeout);
2008 1.1 kiyohara chp->ch_flags &= ~ATACH_DMA_WAIT;
2009 1.1 kiyohara }
2010 1.1 kiyohara while ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
2011 1.1 kiyohara /* Wait for at last 400ns for status bit to be valid */
2012 1.1 kiyohara DELAY(1);
2013 1.1 kiyohara mvsata_atapi_intr(chp, xfer, 0);
2014 1.1 kiyohara }
2015 1.1 kiyohara }
2016 1.1 kiyohara return;
2017 1.1 kiyohara
2018 1.1 kiyohara timeout:
2019 1.1 kiyohara aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n",
2020 1.1 kiyohara chp->ch_channel, xfer->c_drive, errstring);
2021 1.1 kiyohara sc_xfer->error = XS_TIMEOUT;
2022 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
2023 1.1 kiyohara delay(10); /* some drives need a little delay here */
2024 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2025 1.1 kiyohara return;
2026 1.1 kiyohara
2027 1.1 kiyohara error:
2028 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2029 1.1 kiyohara "channel %d drive %d: %s error (0x%x)\n",
2030 1.1 kiyohara chp->ch_channel, xfer->c_drive, errstring, chp->ch_error);
2031 1.1 kiyohara sc_xfer->error = XS_SHORTSENSE;
2032 1.1 kiyohara sc_xfer->sense.atapi_sense = chp->ch_error;
2033 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
2034 1.1 kiyohara delay(10); /* some drives need a little delay here */
2035 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2036 1.1 kiyohara return;
2037 1.1 kiyohara }
2038 1.1 kiyohara
2039 1.1 kiyohara static int
2040 1.1 kiyohara mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
2041 1.1 kiyohara {
2042 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
2043 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
2044 1.1 kiyohara struct wdc_softc *wdc = CHAN_TO_WDC(chp);
2045 1.1 kiyohara struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2046 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
2047 1.1 kiyohara int len, phase, ire, error, retries=0, i;
2048 1.1 kiyohara void *cmd;
2049 1.1 kiyohara
2050 1.1 kiyohara DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n",
2051 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive));
2052 1.1 kiyohara
2053 1.1 kiyohara /* Is it not a transfer, but a control operation? */
2054 1.1 kiyohara if (drvp->state < READY) {
2055 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2056 1.1 kiyohara "channel %d drive %d: bad state %d\n",
2057 1.1 kiyohara chp->ch_channel, xfer->c_drive, drvp->state);
2058 1.1 kiyohara panic("mvsata_atapi_intr: bad state");
2059 1.1 kiyohara }
2060 1.1 kiyohara /*
2061 1.1 kiyohara * If we missed an interrupt in a PIO transfer, reset and restart.
2062 1.1 kiyohara * Don't try to continue transfer, we may have missed cycles.
2063 1.1 kiyohara */
2064 1.1 kiyohara if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) {
2065 1.1 kiyohara sc_xfer->error = XS_TIMEOUT;
2066 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2067 1.1 kiyohara return 1;
2068 1.1 kiyohara }
2069 1.1 kiyohara
2070 1.1 kiyohara /* Ack interrupt done in wdc_wait_for_unbusy */
2071 1.1 kiyohara MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM);
2072 1.1 kiyohara if (wdc_wait_for_unbusy(chp,
2073 1.1 kiyohara (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) {
2074 1.1 kiyohara if (irq && (xfer->c_flags & C_TIMEOU) == 0)
2075 1.1 kiyohara return 0; /* IRQ was not for us */
2076 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2077 1.1 kiyohara "channel %d: device timeout, c_bcount=%d, c_skip=%d\n",
2078 1.1 kiyohara chp->ch_channel, xfer->c_bcount, xfer->c_skip);
2079 1.1 kiyohara if (xfer->c_flags & C_DMA)
2080 1.1 kiyohara ata_dmaerr(drvp,
2081 1.1 kiyohara (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2082 1.1 kiyohara sc_xfer->error = XS_TIMEOUT;
2083 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2084 1.1 kiyohara return 1;
2085 1.1 kiyohara }
2086 1.1 kiyohara
2087 1.1 kiyohara /*
2088 1.1 kiyohara * If we missed an IRQ and were using DMA, flag it as a DMA error
2089 1.1 kiyohara * and reset device.
2090 1.1 kiyohara */
2091 1.1 kiyohara if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) {
2092 1.1 kiyohara ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2093 1.1 kiyohara sc_xfer->error = XS_RESET;
2094 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2095 1.1 kiyohara return (1);
2096 1.1 kiyohara }
2097 1.1 kiyohara /*
2098 1.1 kiyohara * if the request sense command was aborted, report the short sense
2099 1.1 kiyohara * previously recorded, else continue normal processing
2100 1.1 kiyohara */
2101 1.1 kiyohara
2102 1.1 kiyohara again:
2103 1.1 kiyohara len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) +
2104 1.1 kiyohara 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH);
2105 1.1 kiyohara ire = MVSATA_WDC_READ_1(mvport, SRB_SC);
2106 1.1 kiyohara phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ);
2107 1.1 kiyohara DPRINTF((
2108 1.1 kiyohara "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :",
2109 1.1 kiyohara xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire));
2110 1.1 kiyohara
2111 1.1 kiyohara switch (phase) {
2112 1.1 kiyohara case PHASE_CMDOUT:
2113 1.1 kiyohara cmd = sc_xfer->cmd;
2114 1.1 kiyohara DPRINTF(("PHASE_CMDOUT\n"));
2115 1.1 kiyohara /* Init the DMA channel if necessary */
2116 1.1 kiyohara if (xfer->c_flags & C_DMA) {
2117 1.1 kiyohara error = mvsata_bdma_init(mvport, sc_xfer,
2118 1.1 kiyohara (char *)xfer->c_databuf + xfer->c_skip);
2119 1.1 kiyohara if (error) {
2120 1.1 kiyohara if (error == EINVAL) {
2121 1.1 kiyohara /*
2122 1.1 kiyohara * We can't do DMA on this transfer
2123 1.1 kiyohara * for some reason. Fall back to PIO.
2124 1.1 kiyohara */
2125 1.1 kiyohara xfer->c_flags &= ~C_DMA;
2126 1.1 kiyohara error = 0;
2127 1.1 kiyohara } else {
2128 1.1 kiyohara sc_xfer->error = XS_DRIVER_STUFFUP;
2129 1.1 kiyohara break;
2130 1.1 kiyohara }
2131 1.1 kiyohara }
2132 1.1 kiyohara }
2133 1.1 kiyohara
2134 1.1 kiyohara /* send packet command */
2135 1.1 kiyohara /* Commands are 12 or 16 bytes long. It's 32-bit aligned */
2136 1.1 kiyohara wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen);
2137 1.1 kiyohara
2138 1.1 kiyohara /* Start the DMA channel if necessary */
2139 1.1 kiyohara if (xfer->c_flags & C_DMA) {
2140 1.1 kiyohara mvsata_bdma_start(mvport);
2141 1.1 kiyohara chp->ch_flags |= ATACH_DMA_WAIT;
2142 1.1 kiyohara }
2143 1.1 kiyohara
2144 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
2145 1.1 kiyohara chp->ch_flags |= ATACH_IRQ_WAIT;
2146 1.1 kiyohara return 1;
2147 1.1 kiyohara
2148 1.1 kiyohara case PHASE_DATAOUT:
2149 1.1 kiyohara /* write data */
2150 1.1 kiyohara DPRINTF(("PHASE_DATAOUT\n"));
2151 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 ||
2152 1.1 kiyohara (xfer->c_flags & C_DMA) != 0) {
2153 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2154 1.1 kiyohara "channel %d drive %d: bad data phase DATAOUT\n",
2155 1.1 kiyohara chp->ch_channel, xfer->c_drive);
2156 1.1 kiyohara if (xfer->c_flags & C_DMA)
2157 1.1 kiyohara ata_dmaerr(drvp,
2158 1.1 kiyohara (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2159 1.1 kiyohara sc_xfer->error = XS_TIMEOUT;
2160 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2161 1.1 kiyohara return 1;
2162 1.1 kiyohara }
2163 1.1 kiyohara xfer->c_lenoff = len - xfer->c_bcount;
2164 1.1 kiyohara if (xfer->c_bcount < len) {
2165 1.1 kiyohara aprint_error_dev(atac->atac_dev, "channel %d drive %d:"
2166 1.1 kiyohara " warning: write only %d of %d requested bytes\n",
2167 1.1 kiyohara chp->ch_channel, xfer->c_drive, xfer->c_bcount,
2168 1.1 kiyohara len);
2169 1.1 kiyohara len = xfer->c_bcount;
2170 1.1 kiyohara }
2171 1.1 kiyohara
2172 1.1 kiyohara wdc->dataout_pio(chp, drvp->drive_flags,
2173 1.1 kiyohara (char *)xfer->c_databuf + xfer->c_skip, len);
2174 1.1 kiyohara
2175 1.1 kiyohara for (i = xfer->c_lenoff; i > 0; i -= 2)
2176 1.1 kiyohara MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0);
2177 1.1 kiyohara
2178 1.1 kiyohara xfer->c_skip += len;
2179 1.1 kiyohara xfer->c_bcount -= len;
2180 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
2181 1.1 kiyohara chp->ch_flags |= ATACH_IRQ_WAIT;
2182 1.1 kiyohara return 1;
2183 1.1 kiyohara
2184 1.1 kiyohara case PHASE_DATAIN:
2185 1.1 kiyohara /* Read data */
2186 1.1 kiyohara DPRINTF(("PHASE_DATAIN\n"));
2187 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 ||
2188 1.1 kiyohara (xfer->c_flags & C_DMA) != 0) {
2189 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2190 1.1 kiyohara "channel %d drive %d: bad data phase DATAIN\n",
2191 1.1 kiyohara chp->ch_channel, xfer->c_drive);
2192 1.1 kiyohara if (xfer->c_flags & C_DMA)
2193 1.1 kiyohara ata_dmaerr(drvp,
2194 1.1 kiyohara (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2195 1.1 kiyohara sc_xfer->error = XS_TIMEOUT;
2196 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2197 1.1 kiyohara return 1;
2198 1.1 kiyohara }
2199 1.1 kiyohara xfer->c_lenoff = len - xfer->c_bcount;
2200 1.1 kiyohara if (xfer->c_bcount < len) {
2201 1.1 kiyohara aprint_error_dev(atac->atac_dev, "channel %d drive %d:"
2202 1.1 kiyohara " warning: reading only %d of %d bytes\n",
2203 1.1 kiyohara chp->ch_channel, xfer->c_drive, xfer->c_bcount,
2204 1.1 kiyohara len);
2205 1.1 kiyohara len = xfer->c_bcount;
2206 1.1 kiyohara }
2207 1.1 kiyohara
2208 1.1 kiyohara wdc->datain_pio(chp, drvp->drive_flags,
2209 1.1 kiyohara (char *)xfer->c_databuf + xfer->c_skip, len);
2210 1.1 kiyohara
2211 1.1 kiyohara if (xfer->c_lenoff > 0)
2212 1.1 kiyohara wdcbit_bucket(chp, len - xfer->c_bcount);
2213 1.1 kiyohara
2214 1.1 kiyohara xfer->c_skip += len;
2215 1.1 kiyohara xfer->c_bcount -= len;
2216 1.1 kiyohara if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
2217 1.1 kiyohara chp->ch_flags |= ATACH_IRQ_WAIT;
2218 1.1 kiyohara return 1;
2219 1.1 kiyohara
2220 1.1 kiyohara case PHASE_ABORTED:
2221 1.1 kiyohara case PHASE_COMPLETED:
2222 1.1 kiyohara DPRINTF(("PHASE_COMPLETED\n"));
2223 1.1 kiyohara if (xfer->c_flags & C_DMA)
2224 1.1 kiyohara xfer->c_bcount -= sc_xfer->datalen;
2225 1.1 kiyohara sc_xfer->resid = xfer->c_bcount;
2226 1.1 kiyohara mvsata_atapi_phase_complete(xfer);
2227 1.1 kiyohara return 1;
2228 1.1 kiyohara
2229 1.1 kiyohara default:
2230 1.1 kiyohara if (++retries<500) {
2231 1.1 kiyohara DELAY(100);
2232 1.1 kiyohara chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS);
2233 1.1 kiyohara chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE);
2234 1.1 kiyohara goto again;
2235 1.1 kiyohara }
2236 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2237 1.1 kiyohara "channel %d drive %d: unknown phase 0x%x\n",
2238 1.1 kiyohara chp->ch_channel, xfer->c_drive, phase);
2239 1.1 kiyohara if (chp->ch_status & WDCS_ERR) {
2240 1.1 kiyohara sc_xfer->error = XS_SHORTSENSE;
2241 1.1 kiyohara sc_xfer->sense.atapi_sense = chp->ch_error;
2242 1.1 kiyohara } else {
2243 1.1 kiyohara if (xfer->c_flags & C_DMA)
2244 1.1 kiyohara ata_dmaerr(drvp,
2245 1.1 kiyohara (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2246 1.1 kiyohara sc_xfer->error = XS_RESET;
2247 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2248 1.1 kiyohara return (1);
2249 1.1 kiyohara }
2250 1.1 kiyohara }
2251 1.1 kiyohara DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x "
2252 1.1 kiyohara "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense));
2253 1.1 kiyohara mvsata_atapi_done(chp, xfer);
2254 1.1 kiyohara return 1;
2255 1.1 kiyohara }
2256 1.1 kiyohara
2257 1.1 kiyohara static void
2258 1.1 kiyohara mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer,
2259 1.1 kiyohara int reason)
2260 1.1 kiyohara {
2261 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
2262 1.1 kiyohara struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2263 1.1 kiyohara
2264 1.1 kiyohara /* remove this command from xfer queue */
2265 1.1 kiyohara switch (reason) {
2266 1.1 kiyohara case KILL_GONE:
2267 1.1 kiyohara sc_xfer->error = XS_DRIVER_STUFFUP;
2268 1.1 kiyohara break;
2269 1.1 kiyohara
2270 1.1 kiyohara case KILL_RESET:
2271 1.1 kiyohara sc_xfer->error = XS_RESET;
2272 1.1 kiyohara break;
2273 1.1 kiyohara
2274 1.1 kiyohara default:
2275 1.1 kiyohara aprint_error_dev(MVSATA_DEV2(mvport),
2276 1.1 kiyohara "mvsata_atapi_kill_xfer: unknown reason %d\n", reason);
2277 1.1 kiyohara panic("mvsata_atapi_kill_xfer");
2278 1.1 kiyohara }
2279 1.1 kiyohara ata_free_xfer(chp, xfer);
2280 1.1 kiyohara scsipi_done(sc_xfer);
2281 1.1 kiyohara }
2282 1.1 kiyohara
2283 1.1 kiyohara static void
2284 1.1 kiyohara mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer)
2285 1.1 kiyohara {
2286 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
2287 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
2288 1.1 kiyohara struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2289 1.1 kiyohara
2290 1.29 jakllsch mvsata_pmp_select(mvport, xfer->c_drive);
2291 1.29 jakllsch
2292 1.29 jakllsch wdccommandshort(chp, 0, ATAPI_SOFT_RESET);
2293 1.1 kiyohara drvp->state = 0;
2294 1.1 kiyohara if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) {
2295 1.1 kiyohara printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev),
2296 1.1 kiyohara chp->ch_channel, xfer->c_drive);
2297 1.1 kiyohara sc_xfer->error = XS_SELTIMEOUT;
2298 1.1 kiyohara }
2299 1.1 kiyohara mvsata_atapi_done(chp, xfer);
2300 1.1 kiyohara return;
2301 1.1 kiyohara }
2302 1.1 kiyohara
2303 1.1 kiyohara static void
2304 1.1 kiyohara mvsata_atapi_phase_complete(struct ata_xfer *xfer)
2305 1.1 kiyohara {
2306 1.1 kiyohara struct ata_channel *chp = xfer->c_chp;
2307 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
2308 1.1 kiyohara struct wdc_softc *wdc = CHAN_TO_WDC(chp);
2309 1.1 kiyohara struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2310 1.1 kiyohara struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
2311 1.1 kiyohara
2312 1.1 kiyohara /* wait for DSC if needed */
2313 1.24 bouyer if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) {
2314 1.1 kiyohara DPRINTFN(1,
2315 1.1 kiyohara ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n",
2316 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel,
2317 1.1 kiyohara xfer->c_drive, xfer->c_dscpoll));
2318 1.1 kiyohara if (cold)
2319 1.1 kiyohara panic("mvsata_atapi_phase_complete: cold");
2320 1.1 kiyohara
2321 1.1 kiyohara if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) ==
2322 1.1 kiyohara WDCWAIT_TOUT) {
2323 1.1 kiyohara /* 10ms not enough, try again in 1 tick */
2324 1.1 kiyohara if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) {
2325 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2326 1.1 kiyohara "channel %d: wait_for_dsc failed\n",
2327 1.1 kiyohara chp->ch_channel);
2328 1.1 kiyohara sc_xfer->error = XS_TIMEOUT;
2329 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2330 1.1 kiyohara return;
2331 1.1 kiyohara } else
2332 1.1 kiyohara callout_reset(&chp->ch_callout, 1,
2333 1.1 kiyohara mvsata_atapi_polldsc, xfer);
2334 1.1 kiyohara return;
2335 1.1 kiyohara }
2336 1.1 kiyohara }
2337 1.1 kiyohara
2338 1.1 kiyohara /*
2339 1.1 kiyohara * Some drive occasionally set WDCS_ERR with
2340 1.1 kiyohara * "ATA illegal length indication" in the error
2341 1.1 kiyohara * register. If we read some data the sense is valid
2342 1.1 kiyohara * anyway, so don't report the error.
2343 1.1 kiyohara */
2344 1.1 kiyohara if (chp->ch_status & WDCS_ERR &&
2345 1.1 kiyohara ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
2346 1.1 kiyohara sc_xfer->resid == sc_xfer->datalen)) {
2347 1.1 kiyohara /* save the short sense */
2348 1.1 kiyohara sc_xfer->error = XS_SHORTSENSE;
2349 1.1 kiyohara sc_xfer->sense.atapi_sense = chp->ch_error;
2350 1.1 kiyohara if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) {
2351 1.1 kiyohara /* ask scsipi to send a REQUEST_SENSE */
2352 1.1 kiyohara sc_xfer->error = XS_BUSY;
2353 1.1 kiyohara sc_xfer->status = SCSI_CHECK;
2354 1.1 kiyohara } else
2355 1.1 kiyohara if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) {
2356 1.1 kiyohara ata_dmaerr(drvp,
2357 1.1 kiyohara (xfer->c_flags & C_POLL) ? AT_POLL : 0);
2358 1.1 kiyohara sc_xfer->error = XS_RESET;
2359 1.1 kiyohara mvsata_atapi_reset(chp, xfer);
2360 1.1 kiyohara return;
2361 1.1 kiyohara }
2362 1.1 kiyohara }
2363 1.1 kiyohara if (xfer->c_bcount != 0)
2364 1.1 kiyohara DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:"
2365 1.1 kiyohara " bcount value is %d after io\n",
2366 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel,
2367 1.1 kiyohara xfer->c_drive, xfer->c_bcount));
2368 1.1 kiyohara #ifdef DIAGNOSTIC
2369 1.1 kiyohara if (xfer->c_bcount < 0)
2370 1.1 kiyohara aprint_error_dev(atac->atac_dev,
2371 1.1 kiyohara "channel %d drive %d: mvsata_atapi_intr:"
2372 1.1 kiyohara " warning: bcount value is %d after io\n",
2373 1.1 kiyohara chp->ch_channel, xfer->c_drive, xfer->c_bcount);
2374 1.1 kiyohara #endif
2375 1.1 kiyohara
2376 1.1 kiyohara DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:"
2377 1.1 kiyohara " mvsata_atapi_done(), error 0x%x sense 0x%x\n",
2378 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
2379 1.1 kiyohara sc_xfer->error, sc_xfer->sense.atapi_sense));
2380 1.1 kiyohara mvsata_atapi_done(chp, xfer);
2381 1.1 kiyohara }
2382 1.1 kiyohara
2383 1.1 kiyohara static void
2384 1.1 kiyohara mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer)
2385 1.14 jakllsch {
2386 1.1 kiyohara struct atac_softc *atac = chp->ch_atac;
2387 1.1 kiyohara struct scsipi_xfer *sc_xfer = xfer->c_cmd;
2388 1.1 kiyohara int drive = xfer->c_drive;
2389 1.1 kiyohara
2390 1.1 kiyohara DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n",
2391 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
2392 1.1 kiyohara (u_int)xfer->c_flags));
2393 1.1 kiyohara callout_stop(&chp->ch_callout);
2394 1.1 kiyohara /* mark controller inactive and free the command */
2395 1.1 kiyohara chp->ch_queue->active_xfer = NULL;
2396 1.1 kiyohara ata_free_xfer(chp, xfer);
2397 1.1 kiyohara
2398 1.24 bouyer if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
2399 1.1 kiyohara sc_xfer->error = XS_DRIVER_STUFFUP;
2400 1.24 bouyer chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
2401 1.1 kiyohara wakeup(&chp->ch_queue->active_xfer);
2402 1.1 kiyohara }
2403 1.1 kiyohara
2404 1.1 kiyohara DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n",
2405 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel));
2406 1.1 kiyohara scsipi_done(sc_xfer);
2407 1.1 kiyohara DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n",
2408 1.1 kiyohara device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags));
2409 1.1 kiyohara atastart(chp);
2410 1.1 kiyohara }
2411 1.1 kiyohara
2412 1.1 kiyohara static void
2413 1.1 kiyohara mvsata_atapi_polldsc(void *arg)
2414 1.1 kiyohara {
2415 1.1 kiyohara
2416 1.1 kiyohara mvsata_atapi_phase_complete(arg);
2417 1.1 kiyohara }
2418 1.1 kiyohara #endif /* NATAPIBUS > 0 */
2419 1.1 kiyohara
2420 1.1 kiyohara
2421 1.1 kiyohara /*
2422 1.9 jakllsch * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(),
2423 1.1 kiyohara * if supported queuing command by atabus? The race condition will not happen
2424 1.1 kiyohara * if this is called only to the thread of atabus.
2425 1.1 kiyohara */
2426 1.1 kiyohara static int
2427 1.9 jakllsch mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio,
2428 1.1 kiyohara void *databuf)
2429 1.1 kiyohara {
2430 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
2431 1.1 kiyohara struct ata_channel *chp = &mvport->port_ata_channel;
2432 1.1 kiyohara struct eprd *eprd;
2433 1.1 kiyohara bus_addr_t crqb_base_addr;
2434 1.1 kiyohara bus_dmamap_t data_dmamap;
2435 1.1 kiyohara uint32_t reg;
2436 1.1 kiyohara int quetag, erqqip, erqqop, next, rv, i;
2437 1.1 kiyohara
2438 1.9 jakllsch DPRINTFN(2, ("%s:%d:%d: mvsata_edma_enqueue:"
2439 1.7 riz " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n",
2440 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
2441 1.1 kiyohara mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags));
2442 1.1 kiyohara
2443 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP);
2444 1.1 kiyohara erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2445 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP);
2446 1.1 kiyohara erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2447 1.1 kiyohara next = erqqip;
2448 1.1 kiyohara MVSATA_EDMAQ_INC(next);
2449 1.1 kiyohara if (next == erqqop)
2450 1.1 kiyohara /* queue full */
2451 1.1 kiyohara return EBUSY;
2452 1.1 kiyohara if ((quetag = mvsata_quetag_get(mvport)) == -1)
2453 1.1 kiyohara /* tag nothing */
2454 1.1 kiyohara return EBUSY;
2455 1.1 kiyohara DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag));
2456 1.1 kiyohara
2457 1.1 kiyohara rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes,
2458 1.1 kiyohara ata_bio->flags);
2459 1.1 kiyohara if (rv != 0)
2460 1.1 kiyohara return rv;
2461 1.1 kiyohara
2462 1.10 jakllsch KASSERT(mvport->port_reqtbl[quetag].xfer == NULL);
2463 1.10 jakllsch KASSERT(chp->ch_queue->active_xfer != NULL);
2464 1.1 kiyohara mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer;
2465 1.1 kiyohara
2466 1.1 kiyohara /* setup EDMA Physical Region Descriptors (ePRD) Table Data */
2467 1.1 kiyohara data_dmamap = mvport->port_reqtbl[quetag].data_dmamap;
2468 1.1 kiyohara eprd = mvport->port_reqtbl[quetag].eprd;
2469 1.1 kiyohara for (i = 0; i < data_dmamap->dm_nsegs; i++) {
2470 1.1 kiyohara bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr;
2471 1.1 kiyohara bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len;
2472 1.1 kiyohara
2473 1.1 kiyohara eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK);
2474 1.1 kiyohara eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len));
2475 1.1 kiyohara eprd->eot = htole16(0);
2476 1.1 kiyohara eprd->prdbah = htole32((ds_addr >> 16) >> 16);
2477 1.1 kiyohara eprd++;
2478 1.1 kiyohara }
2479 1.1 kiyohara (eprd - 1)->eot |= htole16(EPRD_EOT);
2480 1.1 kiyohara #ifdef MVSATA_DEBUG
2481 1.1 kiyohara if (mvsata_debug >= 3)
2482 1.1 kiyohara mvsata_print_eprd(mvport, quetag);
2483 1.1 kiyohara #endif
2484 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap,
2485 1.1 kiyohara mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE,
2486 1.1 kiyohara BUS_DMASYNC_PREWRITE);
2487 1.1 kiyohara
2488 1.1 kiyohara /* setup EDMA Command Request Block (CRQB) Data */
2489 1.1 kiyohara sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio);
2490 1.1 kiyohara #ifdef MVSATA_DEBUG
2491 1.1 kiyohara if (mvsata_debug >= 3)
2492 1.1 kiyohara mvsata_print_crqb(mvport, erqqip);
2493 1.1 kiyohara #endif
2494 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap,
2495 1.1 kiyohara erqqip * sizeof(union mvsata_crqb),
2496 1.1 kiyohara sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE);
2497 1.1 kiyohara
2498 1.1 kiyohara MVSATA_EDMAQ_INC(erqqip);
2499 1.1 kiyohara
2500 1.1 kiyohara crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr &
2501 1.1 kiyohara (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK);
2502 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16);
2503 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP,
2504 1.1 kiyohara crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT));
2505 1.1 kiyohara
2506 1.1 kiyohara return 0;
2507 1.1 kiyohara }
2508 1.1 kiyohara
2509 1.1 kiyohara static int
2510 1.1 kiyohara mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1)
2511 1.1 kiyohara {
2512 1.1 kiyohara struct ata_channel *chp = &mvport->port_ata_channel;
2513 1.1 kiyohara struct crpb *crpb;
2514 1.1 kiyohara struct ata_bio *ata_bio;
2515 1.1 kiyohara struct ata_xfer *xfer;
2516 1.1 kiyohara uint32_t reg;
2517 1.1 kiyohara int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n;
2518 1.1 kiyohara
2519 1.1 kiyohara /* First, Sync for Request Queue buffer */
2520 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP);
2521 1.1 kiyohara erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2522 1.1 kiyohara if (mvport->port_prev_erqqop != erqqop) {
2523 1.1 kiyohara const int s = sizeof(union mvsata_crqb);
2524 1.1 kiyohara
2525 1.1 kiyohara if (mvport->port_prev_erqqop < erqqop)
2526 1.1 kiyohara n = erqqop - mvport->port_prev_erqqop;
2527 1.1 kiyohara else {
2528 1.1 kiyohara if (erqqop > 0)
2529 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat,
2530 1.1 kiyohara mvport->port_crqb_dmamap, 0, erqqop * s,
2531 1.1 kiyohara BUS_DMASYNC_POSTWRITE);
2532 1.1 kiyohara n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop;
2533 1.1 kiyohara }
2534 1.1 kiyohara if (n > 0)
2535 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat,
2536 1.1 kiyohara mvport->port_crqb_dmamap,
2537 1.1 kiyohara mvport->port_prev_erqqop * s, n * s,
2538 1.1 kiyohara BUS_DMASYNC_POSTWRITE);
2539 1.1 kiyohara mvport->port_prev_erqqop = erqqop;
2540 1.1 kiyohara }
2541 1.1 kiyohara
2542 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP);
2543 1.1 kiyohara erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT;
2544 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP);
2545 1.1 kiyohara erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT;
2546 1.1 kiyohara
2547 1.1 kiyohara DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n",
2548 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
2549 1.1 kiyohara mvport->port, erpqip, erpqop));
2550 1.1 kiyohara
2551 1.1 kiyohara if (erpqop == erpqip)
2552 1.1 kiyohara return 0;
2553 1.1 kiyohara
2554 1.1 kiyohara if (erpqop < erpqip)
2555 1.1 kiyohara n = erpqip - erpqop;
2556 1.1 kiyohara else {
2557 1.1 kiyohara if (erpqip > 0)
2558 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat,
2559 1.1 kiyohara mvport->port_crpb_dmamap,
2560 1.1 kiyohara 0, erpqip * sizeof(struct crpb),
2561 1.1 kiyohara BUS_DMASYNC_POSTREAD);
2562 1.1 kiyohara n = MVSATA_EDMAQ_LEN - erpqop;
2563 1.1 kiyohara }
2564 1.1 kiyohara if (n > 0)
2565 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap,
2566 1.1 kiyohara erpqop * sizeof(struct crpb),
2567 1.1 kiyohara n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD);
2568 1.1 kiyohara
2569 1.1 kiyohara prev_erpqop = erpqop;
2570 1.1 kiyohara while (erpqop != erpqip) {
2571 1.1 kiyohara #ifdef MVSATA_DEBUG
2572 1.1 kiyohara if (mvsata_debug >= 3)
2573 1.1 kiyohara mvsata_print_crpb(mvport, erpqop);
2574 1.1 kiyohara #endif
2575 1.1 kiyohara crpb = mvport->port_crpb + erpqop;
2576 1.1 kiyohara quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id));
2577 1.10 jakllsch KASSERT(chp->ch_queue->active_xfer != NULL);
2578 1.10 jakllsch xfer = chp->ch_queue->active_xfer;
2579 1.10 jakllsch KASSERT(xfer == mvport->port_reqtbl[quetag].xfer);
2580 1.1 kiyohara #ifdef DIAGNOSTIC
2581 1.1 kiyohara if (xfer == NULL)
2582 1.10 jakllsch panic("unknown response received: %s:%d:%d: tag 0x%x\n",
2583 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
2584 1.1 kiyohara mvport->port_hc->hc, mvport->port, quetag);
2585 1.1 kiyohara #endif
2586 1.1 kiyohara
2587 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap,
2588 1.1 kiyohara mvport->port_reqtbl[quetag].eprd_offset,
2589 1.1 kiyohara MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE);
2590 1.1 kiyohara
2591 1.1 kiyohara chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg));
2592 1.1 kiyohara chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg));
2593 1.1 kiyohara ata_bio = xfer->c_cmd;
2594 1.1 kiyohara ata_bio->error = NOERROR;
2595 1.1 kiyohara ata_bio->r_error = 0;
2596 1.1 kiyohara if (chp->ch_status & WDCS_ERR)
2597 1.1 kiyohara ata_bio->error = ERROR;
2598 1.1 kiyohara if (chp->ch_status & WDCS_BSY)
2599 1.1 kiyohara ata_bio->error = TIMEOUT;
2600 1.1 kiyohara if (chp->ch_error)
2601 1.1 kiyohara ata_bio->error = ERR_DMA;
2602 1.1 kiyohara
2603 1.1 kiyohara mvsata_dma_bufunload(mvport, quetag, ata_bio->flags);
2604 1.1 kiyohara mvport->port_reqtbl[quetag].xfer = NULL;
2605 1.1 kiyohara mvsata_quetag_put(mvport, quetag);
2606 1.1 kiyohara MVSATA_EDMAQ_INC(erpqop);
2607 1.1 kiyohara
2608 1.1 kiyohara #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */
2609 1.1 kiyohara erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) &
2610 1.1 kiyohara EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2611 1.1 kiyohara if (erpqop == erqqip)
2612 1.1 kiyohara chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT);
2613 1.1 kiyohara #endif
2614 1.1 kiyohara mvsata_bio_intr(chp, xfer, 1);
2615 1.1 kiyohara if (xfer1 == NULL)
2616 1.1 kiyohara handled++;
2617 1.1 kiyohara else if (xfer == xfer1) {
2618 1.1 kiyohara handled = 1;
2619 1.1 kiyohara break;
2620 1.1 kiyohara }
2621 1.1 kiyohara }
2622 1.1 kiyohara if (prev_erpqop < erpqop)
2623 1.1 kiyohara n = erpqop - prev_erpqop;
2624 1.1 kiyohara else {
2625 1.1 kiyohara if (erpqop > 0)
2626 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat,
2627 1.1 kiyohara mvport->port_crpb_dmamap, 0,
2628 1.1 kiyohara erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD);
2629 1.1 kiyohara n = MVSATA_EDMAQ_LEN - prev_erpqop;
2630 1.1 kiyohara }
2631 1.1 kiyohara if (n > 0)
2632 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap,
2633 1.1 kiyohara prev_erpqop * sizeof(struct crpb),
2634 1.1 kiyohara n * sizeof(struct crpb), BUS_DMASYNC_PREREAD);
2635 1.1 kiyohara
2636 1.1 kiyohara reg &= ~EDMA_RESQP_ERPQP_MASK;
2637 1.1 kiyohara reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT);
2638 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg);
2639 1.1 kiyohara
2640 1.1 kiyohara #if 0 /* already cleared ago? */
2641 1.1 kiyohara erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) &
2642 1.1 kiyohara EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;
2643 1.1 kiyohara if (erpqop == erqqip)
2644 1.1 kiyohara chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT);
2645 1.1 kiyohara #endif
2646 1.1 kiyohara
2647 1.1 kiyohara return handled;
2648 1.1 kiyohara }
2649 1.1 kiyohara
2650 1.1 kiyohara static int
2651 1.1 kiyohara mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout)
2652 1.1 kiyohara {
2653 1.1 kiyohara struct ata_bio *ata_bio = xfer->c_cmd;
2654 1.1 kiyohara int xtime;
2655 1.1 kiyohara
2656 1.1 kiyohara for (xtime = 0; xtime < timeout / 10; xtime++) {
2657 1.1 kiyohara if (mvsata_edma_handle(mvport, xfer))
2658 1.1 kiyohara return 0;
2659 1.30 bouyer if (ata_bio->flags & ATA_POLL)
2660 1.1 kiyohara delay(10000);
2661 1.1 kiyohara else
2662 1.1 kiyohara tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10));
2663 1.1 kiyohara }
2664 1.1 kiyohara
2665 1.1 kiyohara DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer));
2666 1.1 kiyohara mvsata_edma_rqq_remove(mvport, xfer);
2667 1.1 kiyohara xfer->c_flags |= C_TIMEOU;
2668 1.1 kiyohara return 1;
2669 1.1 kiyohara }
2670 1.1 kiyohara
2671 1.1 kiyohara static void
2672 1.1 kiyohara mvsata_edma_timeout(void *arg)
2673 1.1 kiyohara {
2674 1.1 kiyohara struct ata_xfer *xfer = (struct ata_xfer *)arg;
2675 1.1 kiyohara struct ata_channel *chp = xfer->c_chp;
2676 1.1 kiyohara struct mvsata_port *mvport = (struct mvsata_port *)chp;
2677 1.1 kiyohara int s;
2678 1.1 kiyohara
2679 1.1 kiyohara s = splbio();
2680 1.1 kiyohara DPRINTF(("mvsata_edma_timeout: %p\n", xfer));
2681 1.1 kiyohara if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
2682 1.1 kiyohara mvsata_edma_rqq_remove(mvport, xfer);
2683 1.1 kiyohara xfer->c_flags |= C_TIMEOU;
2684 1.1 kiyohara mvsata_bio_intr(chp, xfer, 1);
2685 1.1 kiyohara }
2686 1.1 kiyohara splx(s);
2687 1.1 kiyohara }
2688 1.1 kiyohara
2689 1.1 kiyohara static void
2690 1.1 kiyohara mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer)
2691 1.1 kiyohara {
2692 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
2693 1.1 kiyohara struct ata_bio *ata_bio;
2694 1.1 kiyohara bus_addr_t crqb_base_addr;
2695 1.1 kiyohara int erqqip, i;
2696 1.1 kiyohara
2697 1.1 kiyohara /* First, hardware reset, stop EDMA */
2698 1.1 kiyohara mvsata_hreset_port(mvport);
2699 1.1 kiyohara
2700 1.1 kiyohara /* cleanup completed EDMA safely */
2701 1.1 kiyohara mvsata_edma_handle(mvport, NULL);
2702 1.1 kiyohara
2703 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0,
2704 1.1 kiyohara sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE);
2705 1.1 kiyohara for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) {
2706 1.1 kiyohara if (mvport->port_reqtbl[i].xfer == NULL)
2707 1.1 kiyohara continue;
2708 1.1 kiyohara
2709 1.1 kiyohara ata_bio = mvport->port_reqtbl[i].xfer->c_cmd;
2710 1.1 kiyohara if (mvport->port_reqtbl[i].xfer == xfer) {
2711 1.1 kiyohara /* remove xfer from EDMA request queue */
2712 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat,
2713 1.1 kiyohara mvport->port_eprd_dmamap,
2714 1.1 kiyohara mvport->port_reqtbl[i].eprd_offset,
2715 1.1 kiyohara MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE);
2716 1.1 kiyohara mvsata_dma_bufunload(mvport, i, ata_bio->flags);
2717 1.1 kiyohara mvport->port_reqtbl[i].xfer = NULL;
2718 1.1 kiyohara mvsata_quetag_put(mvport, i);
2719 1.1 kiyohara continue;
2720 1.1 kiyohara }
2721 1.1 kiyohara
2722 1.1 kiyohara sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio);
2723 1.1 kiyohara erqqip++;
2724 1.1 kiyohara }
2725 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0,
2726 1.1 kiyohara sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN,
2727 1.1 kiyohara BUS_DMASYNC_POSTWRITE);
2728 1.1 kiyohara
2729 1.1 kiyohara mvsata_edma_config(mvport, mvport->port_edmamode);
2730 1.1 kiyohara mvsata_edma_reset_qptr(mvport);
2731 1.1 kiyohara mvsata_edma_enable(mvport);
2732 1.1 kiyohara
2733 1.1 kiyohara crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr &
2734 1.1 kiyohara (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK);
2735 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16);
2736 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP,
2737 1.1 kiyohara crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT));
2738 1.1 kiyohara }
2739 1.1 kiyohara
2740 1.1 kiyohara #if NATAPIBUS > 0
2741 1.1 kiyohara static int
2742 1.1 kiyohara mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer,
2743 1.1 kiyohara void *databuf)
2744 1.1 kiyohara {
2745 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
2746 1.1 kiyohara struct eprd *eprd;
2747 1.1 kiyohara bus_dmamap_t data_dmamap;
2748 1.1 kiyohara bus_addr_t eprd_addr;
2749 1.1 kiyohara int quetag, rv;
2750 1.1 kiyohara
2751 1.1 kiyohara DPRINTFN(2,
2752 1.1 kiyohara ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n",
2753 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
2754 1.1 kiyohara mvport->port, sc_xfer->datalen, sc_xfer->xs_control));
2755 1.1 kiyohara
2756 1.1 kiyohara if ((quetag = mvsata_quetag_get(mvport)) == -1)
2757 1.1 kiyohara /* tag nothing */
2758 1.1 kiyohara return EBUSY;
2759 1.1 kiyohara DPRINTFN(2, (" quetag=%d\n", quetag));
2760 1.1 kiyohara
2761 1.1 kiyohara rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen,
2762 1.1 kiyohara sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0);
2763 1.1 kiyohara if (rv != 0)
2764 1.1 kiyohara return rv;
2765 1.1 kiyohara
2766 1.10 jakllsch KASSERT(chp->ch_queue->active_xfer != NULL);
2767 1.10 jakllsch KASSERT(mvport->port_reqtbl[quetag].xfer == NULL);
2768 1.1 kiyohara mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer;
2769 1.1 kiyohara
2770 1.1 kiyohara /* setup EDMA Physical Region Descriptors (ePRD) Table Data */
2771 1.1 kiyohara data_dmamap = mvport->port_reqtbl[quetag].data_dmamap;
2772 1.1 kiyohara eprd = mvport->port_reqtbl[quetag].eprd;
2773 1.1 kiyohara for (i = 0; i < data_dmamap->dm_nsegs; i++) {
2774 1.1 kiyohara bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr;
2775 1.1 kiyohara bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len;
2776 1.1 kiyohara
2777 1.1 kiyohara eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK);
2778 1.1 kiyohara eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len));
2779 1.1 kiyohara eprd->eot = htole16(0);
2780 1.1 kiyohara eprd->prdbah = htole32((ds_addr >> 16) >> 16);
2781 1.1 kiyohara eprd++;
2782 1.1 kiyohara }
2783 1.1 kiyohara (eprd - 1)->eot |= htole16(EPRD_EOT);
2784 1.1 kiyohara #ifdef MVSATA_DEBUG
2785 1.1 kiyohara if (mvsata_debug >= 3)
2786 1.1 kiyohara mvsata_print_eprd(mvport, quetag);
2787 1.1 kiyohara #endif
2788 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap,
2789 1.1 kiyohara mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE,
2790 1.1 kiyohara BUS_DMASYNC_PREWRITE);
2791 1.1 kiyohara eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr +
2792 1.1 kiyohara mvport->port_reqtbl[quetag].eprd_offset;
2793 1.1 kiyohara
2794 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK);
2795 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16);
2796 1.1 kiyohara
2797 1.1 kiyohara if (sc_xfer->xs_control & XS_CTL_DATA_IN)
2798 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ);
2799 1.1 kiyohara else
2800 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0);
2801 1.1 kiyohara
2802 1.1 kiyohara return 0;
2803 1.1 kiyohara }
2804 1.1 kiyohara
2805 1.1 kiyohara static void
2806 1.1 kiyohara mvsata_bdma_start(struct mvsata_port *mvport)
2807 1.1 kiyohara {
2808 1.1 kiyohara
2809 1.1 kiyohara #ifdef MVSATA_DEBUG
2810 1.1 kiyohara if (mvsata_debug >= 3)
2811 1.1 kiyohara mvsata_print_eprd(mvport, 0);
2812 1.1 kiyohara #endif
2813 1.1 kiyohara
2814 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, DMA_C,
2815 1.1 kiyohara MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START);
2816 1.1 kiyohara }
2817 1.1 kiyohara #endif
2818 1.1 kiyohara #endif
2819 1.1 kiyohara
2820 1.1 kiyohara
2821 1.1 kiyohara static int
2822 1.1 kiyohara mvsata_port_init(struct mvsata_hc *mvhc, int port)
2823 1.1 kiyohara {
2824 1.1 kiyohara struct mvsata_softc *sc = mvhc->hc_sc;
2825 1.1 kiyohara struct mvsata_port *mvport;
2826 1.1 kiyohara struct ata_channel *chp;
2827 1.1 kiyohara int channel, rv, i;
2828 1.1 kiyohara const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN;
2829 1.1 kiyohara const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN;
2830 1.1 kiyohara const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN;
2831 1.1 kiyohara
2832 1.1 kiyohara mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF,
2833 1.1 kiyohara M_ZERO | M_NOWAIT);
2834 1.1 kiyohara if (mvport == NULL) {
2835 1.1 kiyohara aprint_error("%s:%d: can't allocate memory for port %d\n",
2836 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2837 1.1 kiyohara return ENOMEM;
2838 1.1 kiyohara }
2839 1.1 kiyohara
2840 1.1 kiyohara mvport->port = port;
2841 1.1 kiyohara mvport->port_hc = mvhc;
2842 1.1 kiyohara mvport->port_edmamode = nodma;
2843 1.1 kiyohara
2844 1.1 kiyohara rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh,
2845 1.1 kiyohara EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE,
2846 1.1 kiyohara EDMA_REGISTERS_SIZE, &mvport->port_ioh);
2847 1.1 kiyohara if (rv != 0) {
2848 1.1 kiyohara aprint_error("%s:%d: can't subregion EDMA %d registers\n",
2849 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2850 1.1 kiyohara goto fail0;
2851 1.1 kiyohara }
2852 1.1 kiyohara mvport->port_iot = mvhc->hc_iot;
2853 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4,
2854 1.1 kiyohara &mvport->port_sata_sstatus);
2855 1.1 kiyohara if (rv != 0) {
2856 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n",
2857 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2858 1.1 kiyohara goto fail0;
2859 1.1 kiyohara }
2860 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4,
2861 1.1 kiyohara &mvport->port_sata_serror);
2862 1.1 kiyohara if (rv != 0) {
2863 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion serror regs\n",
2864 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2865 1.1 kiyohara goto fail0;
2866 1.1 kiyohara }
2867 1.1 kiyohara if (sc->sc_rev == gen1)
2868 1.1 kiyohara rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh,
2869 1.1 kiyohara SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol);
2870 1.1 kiyohara else
2871 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2872 1.1 kiyohara SATA_SC, 4, &mvport->port_sata_scontrol);
2873 1.1 kiyohara if (rv != 0) {
2874 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n",
2875 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port);
2876 1.1 kiyohara goto fail0;
2877 1.1 kiyohara }
2878 1.1 kiyohara mvport->port_dmat = sc->sc_dmat;
2879 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
2880 1.1 kiyohara mvsata_quetag_init(mvport);
2881 1.1 kiyohara #endif
2882 1.1 kiyohara mvhc->hc_ports[port] = mvport;
2883 1.1 kiyohara
2884 1.1 kiyohara channel = mvhc->hc * sc->sc_port + port;
2885 1.1 kiyohara chp = &mvport->port_ata_channel;
2886 1.1 kiyohara chp->ch_channel = channel;
2887 1.1 kiyohara chp->ch_atac = &sc->sc_wdcdev.sc_atac;
2888 1.1 kiyohara chp->ch_queue = &mvport->port_ata_queue;
2889 1.1 kiyohara sc->sc_ata_channels[channel] = chp;
2890 1.1 kiyohara
2891 1.1 kiyohara rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel);
2892 1.1 kiyohara if (rv != 0)
2893 1.1 kiyohara goto fail0;
2894 1.1 kiyohara
2895 1.1 kiyohara rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0,
2896 1.1 kiyohara BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap);
2897 1.1 kiyohara if (rv != 0) {
2898 1.1 kiyohara aprint_error(
2899 1.1 kiyohara "%s:%d:%d: EDMA CRQB map create failed: error=%d\n",
2900 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv);
2901 1.1 kiyohara goto fail0;
2902 1.1 kiyohara }
2903 1.1 kiyohara rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0,
2904 1.1 kiyohara BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap);
2905 1.1 kiyohara if (rv != 0) {
2906 1.1 kiyohara aprint_error(
2907 1.1 kiyohara "%s:%d:%d: EDMA CRPB map create failed: error=%d\n",
2908 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv);
2909 1.1 kiyohara goto fail1;
2910 1.1 kiyohara }
2911 1.1 kiyohara rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1,
2912 1.1 kiyohara eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap);
2913 1.1 kiyohara if (rv != 0) {
2914 1.1 kiyohara aprint_error(
2915 1.1 kiyohara "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n",
2916 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv);
2917 1.1 kiyohara goto fail2;
2918 1.1 kiyohara }
2919 1.1 kiyohara for (i = 0; i < MVSATA_EDMAQ_LEN; i++) {
2920 1.1 kiyohara rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS,
2921 1.1 kiyohara MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT,
2922 1.1 kiyohara &mvport->port_reqtbl[i].data_dmamap);
2923 1.1 kiyohara if (rv != 0) {
2924 1.1 kiyohara aprint_error("%s:%d:%d:"
2925 1.1 kiyohara " EDMA data map(%d) create failed: error=%d\n",
2926 1.1 kiyohara device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i,
2927 1.1 kiyohara rv);
2928 1.1 kiyohara goto fail3;
2929 1.1 kiyohara }
2930 1.1 kiyohara }
2931 1.1 kiyohara
2932 1.1 kiyohara return 0;
2933 1.1 kiyohara
2934 1.1 kiyohara fail3:
2935 1.1 kiyohara for (i--; i >= 0; i--)
2936 1.1 kiyohara bus_dmamap_destroy(mvport->port_dmat,
2937 1.1 kiyohara mvport->port_reqtbl[i].data_dmamap);
2938 1.1 kiyohara bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap);
2939 1.1 kiyohara fail2:
2940 1.1 kiyohara bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap);
2941 1.1 kiyohara fail1:
2942 1.1 kiyohara bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap);
2943 1.1 kiyohara fail0:
2944 1.1 kiyohara return rv;
2945 1.1 kiyohara }
2946 1.1 kiyohara
2947 1.1 kiyohara static int
2948 1.1 kiyohara mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr)
2949 1.1 kiyohara {
2950 1.1 kiyohara int hc, port, rv, i;
2951 1.1 kiyohara
2952 1.1 kiyohara hc = mvport->port_hc->hc;
2953 1.1 kiyohara port = mvport->port;
2954 1.1 kiyohara
2955 1.1 kiyohara /* Create subregion for Shadow Registers Map */
2956 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2957 1.1 kiyohara SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh);
2958 1.1 kiyohara if (rv != 0) {
2959 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n",
2960 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), hc, port);
2961 1.1 kiyohara return rv;
2962 1.1 kiyohara }
2963 1.1 kiyohara wdr->cmd_iot = mvport->port_iot;
2964 1.1 kiyohara
2965 1.1 kiyohara /* Once create subregion for each command registers */
2966 1.1 kiyohara for (i = 0; i < WDC_NREG; i++) {
2967 1.1 kiyohara rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
2968 1.1 kiyohara i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]);
2969 1.1 kiyohara if (rv != 0) {
2970 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion cmd regs\n",
2971 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), hc, port);
2972 1.1 kiyohara return rv;
2973 1.1 kiyohara }
2974 1.1 kiyohara }
2975 1.1 kiyohara /* Create subregion for Alternate Status register */
2976 1.1 kiyohara rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
2977 1.1 kiyohara i * 4, sizeof(uint32_t), &wdr->ctl_ioh);
2978 1.1 kiyohara if (rv != 0) {
2979 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion cmd regs\n",
2980 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), hc, port);
2981 1.1 kiyohara return rv;
2982 1.1 kiyohara }
2983 1.1 kiyohara wdr->ctl_iot = mvport->port_iot;
2984 1.1 kiyohara
2985 1.1 kiyohara wdc_init_shadow_regs(&mvport->port_ata_channel);
2986 1.1 kiyohara
2987 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2988 1.1 kiyohara SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh);
2989 1.1 kiyohara if (rv != 0) {
2990 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion SATA regs\n",
2991 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), hc, port);
2992 1.1 kiyohara return rv;
2993 1.1 kiyohara }
2994 1.1 kiyohara wdr->sata_iot = mvport->port_iot;
2995 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
2996 1.1 kiyohara SATA_SC, sizeof(uint32_t), &wdr->sata_control);
2997 1.1 kiyohara if (rv != 0) {
2998 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion SControl\n",
2999 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), hc, port);
3000 1.1 kiyohara return rv;
3001 1.1 kiyohara }
3002 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
3003 1.1 kiyohara SATA_SS, sizeof(uint32_t), &wdr->sata_status);
3004 1.1 kiyohara if (rv != 0) {
3005 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion SStatus\n",
3006 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), hc, port);
3007 1.1 kiyohara return rv;
3008 1.1 kiyohara }
3009 1.1 kiyohara rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh,
3010 1.1 kiyohara SATA_SE, sizeof(uint32_t), &wdr->sata_error);
3011 1.1 kiyohara if (rv != 0) {
3012 1.1 kiyohara aprint_error("%s:%d:%d: couldn't subregion SError\n",
3013 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), hc, port);
3014 1.1 kiyohara return rv;
3015 1.1 kiyohara }
3016 1.1 kiyohara
3017 1.1 kiyohara return 0;
3018 1.1 kiyohara }
3019 1.1 kiyohara
3020 1.1 kiyohara
3021 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
3022 1.1 kiyohara /*
3023 1.1 kiyohara * There are functions to determine Host Queue Tag.
3024 1.1 kiyohara * XXXX: We hope to rotate Tag to facilitate debugging.
3025 1.1 kiyohara */
3026 1.1 kiyohara
3027 1.1 kiyohara static inline void
3028 1.1 kiyohara mvsata_quetag_init(struct mvsata_port *mvport)
3029 1.1 kiyohara {
3030 1.1 kiyohara
3031 1.1 kiyohara mvport->port_quetagidx = 0;
3032 1.1 kiyohara }
3033 1.1 kiyohara
3034 1.1 kiyohara static inline int
3035 1.1 kiyohara mvsata_quetag_get(struct mvsata_port *mvport)
3036 1.1 kiyohara {
3037 1.1 kiyohara int begin = mvport->port_quetagidx;
3038 1.1 kiyohara
3039 1.1 kiyohara do {
3040 1.1 kiyohara if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) {
3041 1.1 kiyohara MVSATA_EDMAQ_INC(mvport->port_quetagidx);
3042 1.1 kiyohara return mvport->port_quetagidx;
3043 1.1 kiyohara }
3044 1.1 kiyohara MVSATA_EDMAQ_INC(mvport->port_quetagidx);
3045 1.1 kiyohara } while (mvport->port_quetagidx != begin);
3046 1.1 kiyohara
3047 1.1 kiyohara return -1;
3048 1.1 kiyohara }
3049 1.1 kiyohara
3050 1.1 kiyohara static inline void
3051 1.1 kiyohara mvsata_quetag_put(struct mvsata_port *mvport, int quetag)
3052 1.1 kiyohara {
3053 1.1 kiyohara
3054 1.1 kiyohara /* nothing */
3055 1.1 kiyohara }
3056 1.1 kiyohara
3057 1.1 kiyohara static void *
3058 1.1 kiyohara mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat,
3059 1.1 kiyohara bus_dmamap_t *dmamap, size_t size, int write)
3060 1.1 kiyohara {
3061 1.1 kiyohara bus_dma_segment_t seg;
3062 1.1 kiyohara int nseg, rv;
3063 1.1 kiyohara void *kva;
3064 1.1 kiyohara
3065 1.1 kiyohara rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg,
3066 1.1 kiyohara BUS_DMA_NOWAIT);
3067 1.1 kiyohara if (rv != 0) {
3068 1.1 kiyohara aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n",
3069 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
3070 1.1 kiyohara mvport->port_hc->hc, mvport->port, rv);
3071 1.1 kiyohara goto fail;
3072 1.1 kiyohara }
3073 1.1 kiyohara
3074 1.1 kiyohara rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT);
3075 1.1 kiyohara if (rv != 0) {
3076 1.1 kiyohara aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n",
3077 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
3078 1.1 kiyohara mvport->port_hc->hc, mvport->port, rv);
3079 1.1 kiyohara goto free;
3080 1.1 kiyohara }
3081 1.1 kiyohara
3082 1.1 kiyohara rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL,
3083 1.1 kiyohara BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ));
3084 1.1 kiyohara if (rv != 0) {
3085 1.1 kiyohara aprint_error("%s:%d:%d: DMA map load failed: error=%d\n",
3086 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
3087 1.1 kiyohara mvport->port_hc->hc, mvport->port, rv);
3088 1.1 kiyohara goto unmap;
3089 1.1 kiyohara }
3090 1.1 kiyohara
3091 1.1 kiyohara if (!write)
3092 1.1 kiyohara bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD);
3093 1.1 kiyohara
3094 1.1 kiyohara return kva;
3095 1.1 kiyohara
3096 1.1 kiyohara unmap:
3097 1.1 kiyohara bus_dmamem_unmap(dmat, kva, size);
3098 1.1 kiyohara free:
3099 1.1 kiyohara bus_dmamem_free(dmat, &seg, nseg);
3100 1.1 kiyohara fail:
3101 1.1 kiyohara return NULL;
3102 1.1 kiyohara }
3103 1.1 kiyohara
3104 1.1 kiyohara /* ARGSUSED */
3105 1.1 kiyohara static void
3106 1.1 kiyohara mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat,
3107 1.1 kiyohara bus_dmamap_t dmamap, void *kva)
3108 1.1 kiyohara {
3109 1.1 kiyohara
3110 1.1 kiyohara bus_dmamap_unload(dmat, dmamap);
3111 1.1 kiyohara bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize);
3112 1.1 kiyohara bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs);
3113 1.1 kiyohara }
3114 1.1 kiyohara
3115 1.1 kiyohara static int
3116 1.1 kiyohara mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf,
3117 1.1 kiyohara size_t datalen, int flags)
3118 1.1 kiyohara {
3119 1.1 kiyohara int rv, lop, sop;
3120 1.1 kiyohara bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap;
3121 1.1 kiyohara
3122 1.1 kiyohara lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE;
3123 1.1 kiyohara sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE;
3124 1.1 kiyohara
3125 1.1 kiyohara rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen,
3126 1.1 kiyohara NULL, BUS_DMA_NOWAIT | lop);
3127 1.1 kiyohara if (rv) {
3128 1.1 kiyohara aprint_error("%s:%d:%d: buffer load failed: error=%d",
3129 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc,
3130 1.1 kiyohara mvport->port, rv);
3131 1.1 kiyohara return rv;
3132 1.1 kiyohara }
3133 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0,
3134 1.1 kiyohara data_dmamap->dm_mapsize, sop);
3135 1.1 kiyohara
3136 1.1 kiyohara return 0;
3137 1.1 kiyohara }
3138 1.1 kiyohara
3139 1.1 kiyohara static inline void
3140 1.1 kiyohara mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags)
3141 1.1 kiyohara {
3142 1.1 kiyohara bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap;
3143 1.1 kiyohara
3144 1.1 kiyohara bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0,
3145 1.1 kiyohara data_dmamap->dm_mapsize,
3146 1.1 kiyohara (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3147 1.1 kiyohara bus_dmamap_unload(mvport->port_dmat, data_dmamap);
3148 1.1 kiyohara }
3149 1.1 kiyohara #endif
3150 1.1 kiyohara
3151 1.1 kiyohara static void
3152 1.1 kiyohara mvsata_hreset_port(struct mvsata_port *mvport)
3153 1.1 kiyohara {
3154 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3155 1.1 kiyohara
3156 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST);
3157 1.1 kiyohara
3158 1.1 kiyohara delay(25); /* allow reset propagation */
3159 1.1 kiyohara
3160 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0);
3161 1.1 kiyohara
3162 1.1 kiyohara mvport->_fix_phy_param._fix_phy(mvport);
3163 1.1 kiyohara
3164 1.1 kiyohara if (sc->sc_gen == gen1)
3165 1.1 kiyohara delay(1000);
3166 1.1 kiyohara }
3167 1.1 kiyohara
3168 1.1 kiyohara static void
3169 1.1 kiyohara mvsata_reset_port(struct mvsata_port *mvport)
3170 1.1 kiyohara {
3171 1.1 kiyohara device_t parent = device_parent(MVSATA_DEV2(mvport));
3172 1.1 kiyohara
3173 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA);
3174 1.1 kiyohara
3175 1.1 kiyohara mvsata_hreset_port(mvport);
3176 1.1 kiyohara
3177 1.1 kiyohara if (device_is_a(parent, "pci"))
3178 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG,
3179 1.1 kiyohara EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ);
3180 1.1 kiyohara else /* SoC */
3181 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG,
3182 1.1 kiyohara EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2);
3183 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0);
3184 1.29 jakllsch MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000);
3185 1.29 jakllsch MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0);
3186 1.29 jakllsch MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0);
3187 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0);
3188 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0);
3189 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0);
3190 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0);
3191 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0);
3192 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0);
3193 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0);
3194 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0);
3195 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0);
3196 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0);
3197 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc);
3198 1.1 kiyohara }
3199 1.1 kiyohara
3200 1.1 kiyohara static void
3201 1.1 kiyohara mvsata_reset_hc(struct mvsata_hc *mvhc)
3202 1.1 kiyohara {
3203 1.1 kiyohara #if 0
3204 1.1 kiyohara uint32_t val;
3205 1.1 kiyohara #endif
3206 1.1 kiyohara
3207 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0);
3208 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0);
3209 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0);
3210 1.1 kiyohara
3211 1.1 kiyohara #if 0 /* XXXX needs? */
3212 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, 0x01c, 0);
3213 1.1 kiyohara
3214 1.1 kiyohara /*
3215 1.1 kiyohara * Keep the SS during power on and the reference clock bits (reset
3216 1.1 kiyohara * sample)
3217 1.1 kiyohara */
3218 1.1 kiyohara val = MVSATA_HC_READ_4(mvhc, 0x020);
3219 1.1 kiyohara val &= 0x1c1c1c1c;
3220 1.1 kiyohara val |= 0x03030303;
3221 1.1 kiyohara MVSATA_HC_READ_4(mvhc, 0x020, 0);
3222 1.1 kiyohara #endif
3223 1.1 kiyohara }
3224 1.1 kiyohara
3225 1.29 jakllsch #define WDCDELAY 100 /* 100 microseconds */
3226 1.29 jakllsch #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
3227 1.29 jakllsch
3228 1.29 jakllsch static uint32_t
3229 1.1 kiyohara mvsata_softreset(struct mvsata_port *mvport, int waitok)
3230 1.1 kiyohara {
3231 1.29 jakllsch uint32_t sig0 = ~0;
3232 1.29 jakllsch int timeout, nloop;
3233 1.29 jakllsch uint8_t st0;
3234 1.1 kiyohara
3235 1.29 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
3236 1.29 jakllsch delay(10);
3237 1.29 jakllsch (void) MVSATA_WDC_READ_1(mvport, SRB_FE);
3238 1.29 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT);
3239 1.1 kiyohara delay(10);
3240 1.1 kiyohara
3241 1.29 jakllsch if (!waitok)
3242 1.29 jakllsch nloop = WDCNDELAY_RST;
3243 1.29 jakllsch else
3244 1.29 jakllsch nloop = WDC_RESET_WAIT * hz / 1000;
3245 1.29 jakllsch
3246 1.29 jakllsch /* wait for BSY to deassert */
3247 1.29 jakllsch for (timeout = 0; timeout < nloop; timeout++) {
3248 1.29 jakllsch st0 = MVSATA_WDC_READ_1(mvport, SRB_CS);
3249 1.29 jakllsch
3250 1.29 jakllsch if ((st0 & WDCS_BSY) == 0) {
3251 1.29 jakllsch sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0;
3252 1.29 jakllsch sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8;
3253 1.29 jakllsch sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16;
3254 1.29 jakllsch sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24;
3255 1.29 jakllsch goto out;
3256 1.1 kiyohara }
3257 1.29 jakllsch if (!waitok)
3258 1.29 jakllsch delay(WDCDELAY);
3259 1.29 jakllsch else
3260 1.29 jakllsch tsleep(&nloop, PRIBIO, "atarst", 1);
3261 1.1 kiyohara }
3262 1.29 jakllsch
3263 1.29 jakllsch out:
3264 1.29 jakllsch MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT);
3265 1.29 jakllsch return sig0;
3266 1.1 kiyohara }
3267 1.1 kiyohara
3268 1.29 jakllsch #ifndef MVSATA_WITHOUTDMA
3269 1.1 kiyohara static void
3270 1.1 kiyohara mvsata_edma_reset_qptr(struct mvsata_port *mvport)
3271 1.1 kiyohara {
3272 1.1 kiyohara const bus_addr_t crpb_addr =
3273 1.1 kiyohara mvport->port_crpb_dmamap->dm_segs[0].ds_addr;
3274 1.1 kiyohara const uint32_t crpb_addr_mask =
3275 1.1 kiyohara EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK;
3276 1.1 kiyohara
3277 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0);
3278 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0);
3279 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0);
3280 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16);
3281 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0);
3282 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask));
3283 1.1 kiyohara }
3284 1.1 kiyohara
3285 1.1 kiyohara static inline void
3286 1.1 kiyohara mvsata_edma_enable(struct mvsata_port *mvport)
3287 1.1 kiyohara {
3288 1.1 kiyohara
3289 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA);
3290 1.1 kiyohara }
3291 1.1 kiyohara
3292 1.1 kiyohara static int
3293 1.1 kiyohara mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok)
3294 1.1 kiyohara {
3295 1.1 kiyohara uint32_t status, command;
3296 1.1 kiyohara int ms;
3297 1.1 kiyohara
3298 1.1 kiyohara if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) {
3299 1.1 kiyohara for (ms = 0; ms < timeout; ms++) {
3300 1.1 kiyohara status = MVSATA_EDMA_READ_4(mvport, EDMA_S);
3301 1.1 kiyohara if (status & EDMA_S_EDMAIDLE)
3302 1.1 kiyohara break;
3303 1.1 kiyohara if (waitok)
3304 1.1 kiyohara tsleep(&waitok, PRIBIO, "mvsata_edma1",
3305 1.1 kiyohara mstohz(1));
3306 1.1 kiyohara else
3307 1.1 kiyohara delay(1000);
3308 1.1 kiyohara }
3309 1.29 jakllsch if (ms == timeout) {
3310 1.29 jakllsch aprint_error("%s:%d:%d: unable to stop EDMA\n",
3311 1.29 jakllsch device_xname(MVSATA_DEV2(mvport)),
3312 1.29 jakllsch mvport->port_hc->hc, mvport->port);
3313 1.1 kiyohara return EBUSY;
3314 1.29 jakllsch }
3315 1.1 kiyohara
3316 1.1 kiyohara /* The diable bit (eDsEDMA) is self negated. */
3317 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA);
3318 1.1 kiyohara
3319 1.1 kiyohara for ( ; ms < timeout; ms++) {
3320 1.1 kiyohara command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD);
3321 1.1 kiyohara if (!(command & EDMA_CMD_EENEDMA))
3322 1.1 kiyohara break;
3323 1.1 kiyohara if (waitok)
3324 1.1 kiyohara tsleep(&waitok, PRIBIO, "mvsata_edma2",
3325 1.1 kiyohara mstohz(1));
3326 1.1 kiyohara else
3327 1.1 kiyohara delay(1000);
3328 1.1 kiyohara }
3329 1.1 kiyohara if (ms == timeout) {
3330 1.1 kiyohara aprint_error("%s:%d:%d: unable to stop EDMA\n",
3331 1.1 kiyohara device_xname(MVSATA_DEV2(mvport)),
3332 1.1 kiyohara mvport->port_hc->hc, mvport->port);
3333 1.1 kiyohara return EBUSY;
3334 1.1 kiyohara }
3335 1.1 kiyohara }
3336 1.1 kiyohara return 0;
3337 1.1 kiyohara }
3338 1.1 kiyohara
3339 1.1 kiyohara /*
3340 1.1 kiyohara * Set EDMA registers according to mode.
3341 1.1 kiyohara * ex. NCQ/TCQ(queued)/non queued.
3342 1.1 kiyohara */
3343 1.1 kiyohara static void
3344 1.1 kiyohara mvsata_edma_config(struct mvsata_port *mvport, int mode)
3345 1.1 kiyohara {
3346 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3347 1.1 kiyohara uint32_t reg;
3348 1.1 kiyohara
3349 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG);
3350 1.1 kiyohara reg |= EDMA_CFG_RESERVED;
3351 1.1 kiyohara
3352 1.1 kiyohara if (mode == ncq) {
3353 1.1 kiyohara if (sc->sc_gen == gen1) {
3354 1.1 kiyohara aprint_error_dev(MVSATA_DEV2(mvport),
3355 1.1 kiyohara "GenI not support NCQ\n");
3356 1.1 kiyohara return;
3357 1.1 kiyohara } else if (sc->sc_gen == gen2)
3358 1.1 kiyohara reg |= EDMA_CFG_EDEVERR;
3359 1.1 kiyohara reg |= EDMA_CFG_ESATANATVCMDQUE;
3360 1.1 kiyohara } else if (mode == queued) {
3361 1.1 kiyohara reg &= ~EDMA_CFG_ESATANATVCMDQUE;
3362 1.1 kiyohara reg |= EDMA_CFG_EQUE;
3363 1.1 kiyohara } else
3364 1.1 kiyohara reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE);
3365 1.1 kiyohara
3366 1.1 kiyohara if (sc->sc_gen == gen1)
3367 1.1 kiyohara reg |= EDMA_CFG_ERDBSZ;
3368 1.1 kiyohara else if (sc->sc_gen == gen2)
3369 1.1 kiyohara reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN);
3370 1.1 kiyohara else if (sc->sc_gen == gen2e) {
3371 1.1 kiyohara device_t parent = device_parent(MVSATA_DEV(sc));
3372 1.1 kiyohara
3373 1.1 kiyohara reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN);
3374 1.1 kiyohara reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN);
3375 1.1 kiyohara
3376 1.1 kiyohara if (device_is_a(parent, "pci"))
3377 1.1 kiyohara reg |= (
3378 1.1 kiyohara #if NATAPIBUS > 0
3379 1.1 kiyohara EDMA_CFG_EEARLYCOMPLETIONEN |
3380 1.1 kiyohara #endif
3381 1.1 kiyohara EDMA_CFG_ECUTTHROUGHEN |
3382 1.1 kiyohara EDMA_CFG_EWRBUFFERLEN |
3383 1.1 kiyohara EDMA_CFG_ERDBSZEXT);
3384 1.1 kiyohara }
3385 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg);
3386 1.1 kiyohara
3387 1.1 kiyohara reg = (
3388 1.1 kiyohara EDMA_IE_EIORDYERR |
3389 1.1 kiyohara EDMA_IE_ETRANSINT |
3390 1.1 kiyohara EDMA_IE_EDEVCON |
3391 1.1 kiyohara EDMA_IE_EDEVDIS);
3392 1.1 kiyohara if (sc->sc_gen != gen1)
3393 1.1 kiyohara reg |= (
3394 1.1 kiyohara EDMA_IE_TRANSPROTERR |
3395 1.1 kiyohara EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) |
3396 1.1 kiyohara EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3397 1.1 kiyohara EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3398 1.1 kiyohara EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3399 1.1 kiyohara EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) |
3400 1.1 kiyohara EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3401 1.1 kiyohara EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3402 1.1 kiyohara EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3403 1.1 kiyohara EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3404 1.1 kiyohara EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3405 1.1 kiyohara EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3406 1.1 kiyohara EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) |
3407 1.1 kiyohara EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) |
3408 1.1 kiyohara EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) |
3409 1.1 kiyohara EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) |
3410 1.1 kiyohara EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) |
3411 1.1 kiyohara EDMA_IE_ESELFDIS);
3412 1.1 kiyohara
3413 1.1 kiyohara if (mode == ncq)
3414 1.1 kiyohara reg |= EDMA_IE_EDEVERR;
3415 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg);
3416 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC);
3417 1.1 kiyohara reg &= ~EDMA_IE_EDEVERR;
3418 1.1 kiyohara if (mode != ncq)
3419 1.1 kiyohara reg |= EDMA_IE_EDEVERR;
3420 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg);
3421 1.1 kiyohara if (sc->sc_gen == gen2e) {
3422 1.1 kiyohara /*
3423 1.1 kiyohara * Clear FISWait4HostRdyEn[0] and [2].
3424 1.1 kiyohara * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1.
3425 1.1 kiyohara * [2]: SDB FIS is received with <ERR> bit set to 1.
3426 1.1 kiyohara */
3427 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC);
3428 1.1 kiyohara reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 |
3429 1.1 kiyohara SATA_FISC_FISWAIT4HOSTRDYEN_B2);
3430 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg);
3431 1.1 kiyohara }
3432 1.1 kiyohara
3433 1.1 kiyohara mvport->port_edmamode = mode;
3434 1.1 kiyohara }
3435 1.1 kiyohara
3436 1.1 kiyohara
3437 1.1 kiyohara /*
3438 1.1 kiyohara * Generation dependent functions
3439 1.1 kiyohara */
3440 1.1 kiyohara
3441 1.1 kiyohara static void
3442 1.1 kiyohara mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag,
3443 1.1 kiyohara struct ata_bio *ata_bio)
3444 1.1 kiyohara {
3445 1.1 kiyohara struct crqb *crqb;
3446 1.1 kiyohara bus_addr_t eprd_addr;
3447 1.1 kiyohara daddr_t blkno;
3448 1.1 kiyohara uint32_t rw;
3449 1.1 kiyohara uint8_t cmd, head;
3450 1.1 kiyohara int i;
3451 1.1 kiyohara const int drive =
3452 1.1 kiyohara mvport->port_ata_channel.ch_queue->active_xfer->c_drive;
3453 1.1 kiyohara
3454 1.1 kiyohara eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr +
3455 1.1 kiyohara mvport->port_reqtbl[quetag].eprd_offset;
3456 1.1 kiyohara rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE;
3457 1.1 kiyohara cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA;
3458 1.26 jakllsch if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) {
3459 1.26 jakllsch head = WDSD_LBA;
3460 1.26 jakllsch } else {
3461 1.26 jakllsch head = 0;
3462 1.26 jakllsch }
3463 1.1 kiyohara blkno = ata_bio->blkno;
3464 1.1 kiyohara if (ata_bio->flags & ATA_LBA48)
3465 1.1 kiyohara cmd = atacmd_to48(cmd);
3466 1.1 kiyohara else {
3467 1.1 kiyohara head |= ((ata_bio->blkno >> 24) & 0xf);
3468 1.1 kiyohara blkno &= 0xffffff;
3469 1.1 kiyohara }
3470 1.1 kiyohara crqb = &mvport->port_crqb->crqb + erqqip;
3471 1.1 kiyohara crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK);
3472 1.1 kiyohara crqb->cprdbh = htole32((eprd_addr >> 16) >> 16);
3473 1.1 kiyohara crqb->ctrlflg =
3474 1.1 kiyohara htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive));
3475 1.1 kiyohara i = 0;
3476 1.1 kiyohara if (mvport->port_edmamode == dma) {
3477 1.1 kiyohara if (ata_bio->flags & ATA_LBA48)
3478 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3479 1.1 kiyohara CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8));
3480 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3481 1.1 kiyohara CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks));
3482 1.1 kiyohara } else { /* ncq/queued */
3483 1.1 kiyohara
3484 1.1 kiyohara /*
3485 1.1 kiyohara * XXXX: Oops, ata command is not correct. And, atabus layer
3486 1.1 kiyohara * has not been supported yet now.
3487 1.1 kiyohara * Queued DMA read/write.
3488 1.1 kiyohara * read/write FPDMAQueued.
3489 1.1 kiyohara */
3490 1.1 kiyohara
3491 1.1 kiyohara if (ata_bio->flags & ATA_LBA48)
3492 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3493 1.1 kiyohara CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8));
3494 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3495 1.1 kiyohara CRQB_ATACOMMAND_FEATURES, ata_bio->nblks));
3496 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3497 1.1 kiyohara CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3));
3498 1.1 kiyohara }
3499 1.1 kiyohara if (ata_bio->flags & ATA_LBA48) {
3500 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3501 1.1 kiyohara CRQB_ATACOMMAND_LBALOW, blkno >> 24));
3502 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3503 1.1 kiyohara CRQB_ATACOMMAND_LBAMID, blkno >> 32));
3504 1.1 kiyohara crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND(
3505 1.1 kiyohara CRQB_ATACOMMAND_LBAHIGH, blkno >> 40));
3506 1.1 kiyohara }
3507 1.1 kiyohara crqb->atacommand[i++] =
3508 1.1 kiyohara htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno));
3509 1.1 kiyohara crqb->atacommand[i++] =
3510 1.1 kiyohara htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8));
3511 1.1 kiyohara crqb->atacommand[i++] =
3512 1.1 kiyohara htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16));
3513 1.1 kiyohara crqb->atacommand[i++] =
3514 1.1 kiyohara htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head));
3515 1.1 kiyohara crqb->atacommand[i++] = htole16(
3516 1.1 kiyohara CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) |
3517 1.1 kiyohara CRQB_ATACOMMAND_LAST);
3518 1.1 kiyohara }
3519 1.1 kiyohara #endif
3520 1.1 kiyohara
3521 1.1 kiyohara static uint32_t
3522 1.1 kiyohara mvsata_read_preamps_gen1(struct mvsata_port *mvport)
3523 1.1 kiyohara {
3524 1.1 kiyohara struct mvsata_hc *hc = mvport->port_hc;
3525 1.1 kiyohara uint32_t reg;
3526 1.1 kiyohara
3527 1.1 kiyohara reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port));
3528 1.1 kiyohara /*
3529 1.1 kiyohara * [12:11] : pre
3530 1.1 kiyohara * [7:5] : amps
3531 1.1 kiyohara */
3532 1.1 kiyohara return reg & 0x000018e0;
3533 1.1 kiyohara }
3534 1.1 kiyohara
3535 1.1 kiyohara static void
3536 1.1 kiyohara mvsata_fix_phy_gen1(struct mvsata_port *mvport)
3537 1.1 kiyohara {
3538 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3539 1.1 kiyohara struct mvsata_hc *mvhc = mvport->port_hc;
3540 1.1 kiyohara uint32_t reg;
3541 1.1 kiyohara int port = mvport->port, fix_apm_sq = 0;
3542 1.1 kiyohara
3543 1.1 kiyohara if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) {
3544 1.1 kiyohara if (sc->sc_rev == 0x01)
3545 1.1 kiyohara fix_apm_sq = 1;
3546 1.1 kiyohara } else {
3547 1.1 kiyohara if (sc->sc_rev == 0x00)
3548 1.1 kiyohara fix_apm_sq = 1;
3549 1.1 kiyohara }
3550 1.1 kiyohara
3551 1.1 kiyohara if (fix_apm_sq) {
3552 1.1 kiyohara /*
3553 1.1 kiyohara * Disable auto-power management
3554 1.1 kiyohara * 88SX50xx FEr SATA#12
3555 1.1 kiyohara */
3556 1.1 kiyohara reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port));
3557 1.1 kiyohara reg |= (1 << 19);
3558 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg);
3559 1.1 kiyohara
3560 1.1 kiyohara /*
3561 1.1 kiyohara * Fix squelch threshold
3562 1.1 kiyohara * 88SX50xx FEr SATA#9
3563 1.1 kiyohara */
3564 1.1 kiyohara reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port));
3565 1.1 kiyohara reg &= ~0x3;
3566 1.1 kiyohara reg |= 0x1;
3567 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg);
3568 1.1 kiyohara }
3569 1.1 kiyohara
3570 1.1 kiyohara /* Revert values of pre-emphasis and signal amps to the saved ones */
3571 1.1 kiyohara reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port));
3572 1.1 kiyohara reg &= ~0x000018e0; /* pre and amps mask */
3573 1.1 kiyohara reg |= mvport->_fix_phy_param.pre_amps;
3574 1.1 kiyohara MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg);
3575 1.1 kiyohara }
3576 1.1 kiyohara
3577 1.1 kiyohara static void
3578 1.1 kiyohara mvsata_devconn_gen1(struct mvsata_port *mvport)
3579 1.1 kiyohara {
3580 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3581 1.1 kiyohara
3582 1.1 kiyohara /* Fix for 88SX50xx FEr SATA#2 */
3583 1.1 kiyohara mvport->_fix_phy_param._fix_phy(mvport);
3584 1.1 kiyohara
3585 1.1 kiyohara /* If disk is connected, then enable the activity LED */
3586 1.1 kiyohara if (sc->sc_rev == 0x03) {
3587 1.1 kiyohara /* XXXXX */
3588 1.1 kiyohara }
3589 1.1 kiyohara }
3590 1.1 kiyohara
3591 1.1 kiyohara static uint32_t
3592 1.1 kiyohara mvsata_read_preamps_gen2(struct mvsata_port *mvport)
3593 1.1 kiyohara {
3594 1.1 kiyohara uint32_t reg;
3595 1.1 kiyohara
3596 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3597 1.1 kiyohara /*
3598 1.1 kiyohara * [10:8] : amps
3599 1.1 kiyohara * [7:5] : pre
3600 1.1 kiyohara */
3601 1.1 kiyohara return reg & 0x000007e0;
3602 1.1 kiyohara }
3603 1.1 kiyohara
3604 1.1 kiyohara static void
3605 1.1 kiyohara mvsata_fix_phy_gen2(struct mvsata_port *mvport)
3606 1.1 kiyohara {
3607 1.1 kiyohara struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport));
3608 1.1 kiyohara uint32_t reg;
3609 1.1 kiyohara
3610 1.1 kiyohara if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) ||
3611 1.1 kiyohara sc->sc_gen == gen2e) {
3612 1.1 kiyohara /*
3613 1.1 kiyohara * Fix for
3614 1.1 kiyohara * 88SX60X1 FEr SATA #23
3615 1.1 kiyohara * 88SX6042/88SX7042 FEr SATA #23
3616 1.1 kiyohara * 88F5182 FEr #SATA-S13
3617 1.1 kiyohara * 88F5082 FEr #SATA-S13
3618 1.1 kiyohara */
3619 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3620 1.1 kiyohara reg &= ~(1 << 16);
3621 1.1 kiyohara reg |= (1 << 31);
3622 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);
3623 1.1 kiyohara
3624 1.1 kiyohara delay(200);
3625 1.1 kiyohara
3626 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3627 1.1 kiyohara reg &= ~((1 << 16) | (1 << 31));
3628 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);
3629 1.1 kiyohara
3630 1.1 kiyohara delay(200);
3631 1.1 kiyohara }
3632 1.1 kiyohara
3633 1.1 kiyohara /* Fix values in PHY Mode 3 Register.*/
3634 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3);
3635 1.1 kiyohara reg &= ~0x7F900000;
3636 1.1 kiyohara reg |= 0x2A800000;
3637 1.1 kiyohara /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */
3638 1.1 kiyohara if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 ||
3639 1.1 kiyohara sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 ||
3640 1.1 kiyohara sc->sc_model == PCI_PRODUCT_MARVELL_88F6082)
3641 1.1 kiyohara reg &= ~0x0000001c;
3642 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg);
3643 1.1 kiyohara
3644 1.1 kiyohara /*
3645 1.1 kiyohara * Fix values in PHY Mode 4 Register.
3646 1.1 kiyohara * 88SX60x1 FEr SATA#10
3647 1.1 kiyohara * 88F5182 GL #SATA-S10
3648 1.1 kiyohara * 88F5082 GL #SATA-S10
3649 1.1 kiyohara */
3650 1.1 kiyohara if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) ||
3651 1.1 kiyohara sc->sc_gen == gen2e) {
3652 1.1 kiyohara uint32_t tmp = 0;
3653 1.1 kiyohara
3654 1.1 kiyohara /* 88SX60x1 FEr SATA #13 */
3655 1.1 kiyohara if (sc->sc_gen == 2 && sc->sc_rev == 0x07)
3656 1.1 kiyohara tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3);
3657 1.1 kiyohara
3658 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4);
3659 1.1 kiyohara reg |= (1 << 0);
3660 1.1 kiyohara reg &= ~(1 << 1);
3661 1.1 kiyohara /* PHY Mode 4 Register of Gen IIE has some restriction */
3662 1.1 kiyohara if (sc->sc_gen == gen2e) {
3663 1.1 kiyohara reg &= ~0x5de3fffc;
3664 1.1 kiyohara reg |= (1 << 2);
3665 1.1 kiyohara }
3666 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg);
3667 1.1 kiyohara
3668 1.1 kiyohara /* 88SX60x1 FEr SATA #13 */
3669 1.1 kiyohara if (sc->sc_gen == 2 && sc->sc_rev == 0x07)
3670 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp);
3671 1.1 kiyohara }
3672 1.1 kiyohara
3673 1.1 kiyohara /* Revert values of pre-emphasis and signal amps to the saved ones */
3674 1.1 kiyohara reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);
3675 1.1 kiyohara reg &= ~0x000007e0; /* pre and amps mask */
3676 1.1 kiyohara reg |= mvport->_fix_phy_param.pre_amps;
3677 1.1 kiyohara reg &= ~(1 << 16);
3678 1.1 kiyohara if (sc->sc_gen == gen2e) {
3679 1.1 kiyohara /*
3680 1.1 kiyohara * according to mvSata 3.6.1, some IIE values are fixed.
3681 1.1 kiyohara * some reserved fields must be written with fixed values.
3682 1.1 kiyohara */
3683 1.1 kiyohara reg &= ~0xC30FF01F;
3684 1.1 kiyohara reg |= 0x0000900F;
3685 1.1 kiyohara }
3686 1.1 kiyohara MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);
3687 1.1 kiyohara }
3688 1.1 kiyohara
3689 1.1 kiyohara #ifndef MVSATA_WITHOUTDMA
3690 1.1 kiyohara static void
3691 1.1 kiyohara mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag,
3692 1.1 kiyohara struct ata_bio *ata_bio)
3693 1.1 kiyohara {
3694 1.1 kiyohara struct crqb_gen2e *crqb;
3695 1.1 kiyohara bus_addr_t eprd_addr;
3696 1.1 kiyohara daddr_t blkno;
3697 1.1 kiyohara uint32_t ctrlflg, rw;
3698 1.1 kiyohara uint8_t cmd, head;
3699 1.1 kiyohara const int drive =
3700 1.1 kiyohara mvport->port_ata_channel.ch_queue->active_xfer->c_drive;
3701 1.1 kiyohara
3702 1.1 kiyohara eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr +
3703 1.1 kiyohara mvport->port_reqtbl[quetag].eprd_offset;
3704 1.1 kiyohara rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE;
3705 1.27 jakllsch ctrlflg = (rw | CRQB_CDEVICEQUETAG(0) | CRQB_CPMPORT(drive) |
3706 1.1 kiyohara CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag));
3707 1.1 kiyohara cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA;
3708 1.26 jakllsch if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) {
3709 1.26 jakllsch head = WDSD_LBA;
3710 1.26 jakllsch } else {
3711 1.26 jakllsch head = 0;
3712 1.26 jakllsch }
3713 1.1 kiyohara blkno = ata_bio->blkno;
3714 1.1 kiyohara if (ata_bio->flags & ATA_LBA48)
3715 1.1 kiyohara cmd = atacmd_to48(cmd);
3716 1.1 kiyohara else {
3717 1.1 kiyohara head |= ((ata_bio->blkno >> 24) & 0xf);
3718 1.1 kiyohara blkno &= 0xffffff;
3719 1.1 kiyohara }
3720 1.1 kiyohara crqb = &mvport->port_crqb->crqb_gen2e + erqqip;
3721 1.1 kiyohara crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK);
3722 1.1 kiyohara crqb->cprdbh = htole32((eprd_addr >> 16) >> 16);
3723 1.1 kiyohara crqb->ctrlflg = htole32(ctrlflg);
3724 1.1 kiyohara if (mvport->port_edmamode == dma) {
3725 1.1 kiyohara crqb->atacommand[0] = htole32(cmd << 16);
3726 1.1 kiyohara crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24);
3727 1.1 kiyohara crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff));
3728 1.1 kiyohara crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff);
3729 1.1 kiyohara } else { /* ncq/queued */
3730 1.1 kiyohara
3731 1.1 kiyohara /*
3732 1.1 kiyohara * XXXX: Oops, ata command is not correct. And, atabus layer
3733 1.1 kiyohara * has not been supported yet now.
3734 1.1 kiyohara * Queued DMA read/write.
3735 1.1 kiyohara * read/write FPDMAQueued.
3736 1.1 kiyohara */
3737 1.1 kiyohara
3738 1.1 kiyohara crqb->atacommand[0] = htole32(
3739 1.1 kiyohara (cmd << 16) | ((ata_bio->nblks & 0xff) << 24));
3740 1.1 kiyohara crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24);
3741 1.1 kiyohara crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) |
3742 1.1 kiyohara ((ata_bio->nblks >> 8) & 0xff));
3743 1.1 kiyohara crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff);
3744 1.1 kiyohara crqb->atacommand[3] = htole32(quetag << 3);
3745 1.1 kiyohara }
3746 1.1 kiyohara }
3747 1.1 kiyohara
3748 1.1 kiyohara
3749 1.1 kiyohara #ifdef MVSATA_DEBUG
3750 1.1 kiyohara #define MVSATA_DEBUG_PRINT(type, size, n, p) \
3751 1.1 kiyohara do { \
3752 1.1 kiyohara int _i; \
3753 1.1 kiyohara u_char *_p = (p); \
3754 1.1 kiyohara \
3755 1.1 kiyohara printf(#type "(%d)", (n)); \
3756 1.1 kiyohara for (_i = 0; _i < (size); _i++, _p++) { \
3757 1.1 kiyohara if (_i % 16 == 0) \
3758 1.1 kiyohara printf("\n "); \
3759 1.1 kiyohara printf(" %02x", *_p); \
3760 1.1 kiyohara } \
3761 1.1 kiyohara printf("\n"); \
3762 1.1 kiyohara } while (0 /* CONSTCOND */)
3763 1.1 kiyohara
3764 1.1 kiyohara static void
3765 1.1 kiyohara mvsata_print_crqb(struct mvsata_port *mvport, int n)
3766 1.1 kiyohara {
3767 1.1 kiyohara
3768 1.1 kiyohara MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb),
3769 1.1 kiyohara n, (u_char *)(mvport->port_crqb + n));
3770 1.1 kiyohara }
3771 1.1 kiyohara
3772 1.1 kiyohara static void
3773 1.1 kiyohara mvsata_print_crpb(struct mvsata_port *mvport, int n)
3774 1.1 kiyohara {
3775 1.1 kiyohara
3776 1.1 kiyohara MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb),
3777 1.1 kiyohara n, (u_char *)(mvport->port_crpb + n));
3778 1.1 kiyohara }
3779 1.1 kiyohara
3780 1.1 kiyohara static void
3781 1.1 kiyohara mvsata_print_eprd(struct mvsata_port *mvport, int n)
3782 1.1 kiyohara {
3783 1.1 kiyohara struct eprd *eprd;
3784 1.1 kiyohara int i = 0;
3785 1.1 kiyohara
3786 1.1 kiyohara eprd = mvport->port_reqtbl[n].eprd;
3787 1.1 kiyohara while (1 /*CONSTCOND*/) {
3788 1.1 kiyohara MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd),
3789 1.1 kiyohara i, (u_char *)eprd);
3790 1.1 kiyohara if (eprd->eot & EPRD_EOT)
3791 1.1 kiyohara break;
3792 1.1 kiyohara eprd++;
3793 1.1 kiyohara i++;
3794 1.1 kiyohara }
3795 1.1 kiyohara }
3796 1.1 kiyohara #endif
3797 1.1 kiyohara #endif
3798