mvsata.c revision 1.12
1 /* $NetBSD: mvsata.c,v 1.12 2012/01/09 01:01:49 jakllsch Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.12 2012/01/09 01:01:49 jakllsch Exp $"); 30 31 #include "opt_mvsata.h" 32 33 /* ATAPI implementation not finished. Also don't work shadow registers? */ 34 //#include "atapibus.h" 35 36 #include <sys/param.h> 37 #if NATAPIBUS > 0 38 #include <sys/buf.h> 39 #endif 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/disklabel.h> 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 49 #include <machine/vmparam.h> 50 51 #include <dev/ata/atareg.h> 52 #include <dev/ata/atavar.h> 53 #include <dev/ic/wdcvar.h> 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 57 #if NATAPIBUS > 0 58 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 59 #endif 60 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ic/mvsatareg.h> 64 #include <dev/ic/mvsatavar.h> 65 66 67 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 68 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 69 70 #define MVSATA_HC_READ_4(hc, reg) \ 71 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 72 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 73 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 74 #define MVSATA_EDMA_READ_4(mvport, reg) \ 75 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 76 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 77 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 78 #define MVSATA_WDC_READ_2(mvport, reg) \ 79 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, (reg)) 80 #define MVSATA_WDC_READ_1(mvport, reg) \ 81 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, (reg)) 82 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 83 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 84 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 85 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 86 87 #ifdef MVSATA_DEBUG 88 #define DPRINTF(x) if (mvsata_debug) printf x 89 #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x 90 int mvsata_debug = 2; 91 #else 92 #define DPRINTF(x) 93 #define DPRINTFN(n,x) 94 #endif 95 96 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 97 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 98 sending a cmd */ 99 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 100 101 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 102 103 104 #ifndef MVSATA_WITHOUTDMA 105 static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *); 106 static void mvsata_reset_drive(struct ata_drive_datas *, int); 107 static void mvsata_reset_channel(struct ata_channel *, int); 108 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *); 109 static int mvsata_addref(struct ata_drive_datas *); 110 static void mvsata_delref(struct ata_drive_datas *); 111 static void mvsata_killpending(struct ata_drive_datas *); 112 113 #if NATAPIBUS > 0 114 static void mvsata_atapibus_attach(struct atabus_softc *); 115 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 116 scsipi_adapter_req_t, void *); 117 static void mvsata_atapi_minphys(struct buf *); 118 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 119 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 120 #endif 121 #endif 122 123 static void mvsata_setup_channel(struct ata_channel *); 124 125 #ifndef MVSATA_WITHOUTDMA 126 static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 127 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 128 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 129 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 130 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 131 int); 132 static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 133 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 134 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 135 int); 136 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 137 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 138 #if NATAPIBUS > 0 139 static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 140 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 141 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 142 int); 143 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 144 static void mvsata_atapi_phase_complete(struct ata_xfer *); 145 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_atapi_polldsc(void *); 147 #endif 148 149 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_bio *, void *); 150 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 151 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 152 static void mvsata_edma_timeout(void *); 153 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 154 #if NATAPIBUS > 0 155 static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *); 156 static void mvsata_bdma_start(struct mvsata_port *); 157 #endif 158 #endif 159 160 static int mvsata_port_init(struct mvsata_hc *, int); 161 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 162 #ifndef MVSATA_WITHOUTDMA 163 static inline void mvsata_quetag_init(struct mvsata_port *); 164 static inline int mvsata_quetag_get(struct mvsata_port *); 165 static inline void mvsata_quetag_put(struct mvsata_port *, int); 166 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 167 bus_dmamap_t *, size_t, int); 168 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 169 bus_dmamap_t, void *); 170 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 171 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 172 #endif 173 174 static void mvsata_hreset_port(struct mvsata_port *); 175 static void mvsata_reset_port(struct mvsata_port *); 176 static void mvsata_reset_hc(struct mvsata_hc *); 177 #ifndef MVSATA_WITHOUTDMA 178 static void mvsata_softreset(struct mvsata_port *, int); 179 static void mvsata_edma_reset_qptr(struct mvsata_port *); 180 static inline void mvsata_edma_enable(struct mvsata_port *); 181 static int mvsata_edma_disable(struct mvsata_port *, int, int); 182 static void mvsata_edma_config(struct mvsata_port *, int); 183 184 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int, 185 struct ata_bio *); 186 #endif 187 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 188 static void mvsata_fix_phy_gen1(struct mvsata_port *); 189 static void mvsata_devconn_gen1(struct mvsata_port *); 190 191 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 192 static void mvsata_fix_phy_gen2(struct mvsata_port *); 193 #ifndef MVSATA_WITHOUTDMA 194 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int, 195 struct ata_bio *); 196 197 #ifdef MVSATA_DEBUG 198 static void mvsata_print_crqb(struct mvsata_port *, int); 199 static void mvsata_print_crpb(struct mvsata_port *, int); 200 static void mvsata_print_eprd(struct mvsata_port *, int); 201 #endif 202 203 204 struct ata_bustype mvsata_ata_bustype = { 205 SCSIPI_BUSTYPE_ATA, 206 mvsata_bio, 207 mvsata_reset_drive, 208 mvsata_reset_channel, 209 mvsata_exec_command, 210 ata_get_params, 211 mvsata_addref, 212 mvsata_delref, 213 mvsata_killpending 214 }; 215 216 #if NATAPIBUS > 0 217 static const struct scsipi_bustype mvsata_atapi_bustype = { 218 SCSIPI_BUSTYPE_ATAPI, 219 atapi_scsipi_cmd, 220 atapi_interpret_sense, 221 atapi_print_addr, 222 mvsata_atapi_kill_pending, 223 }; 224 #endif /* NATAPIBUS */ 225 #endif 226 227 228 int 229 mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product, 230 int (*mvsata_sreset)(struct mvsata_softc *), 231 int (*mvsata_misc_reset)(struct mvsata_softc *), 232 int read_pre_amps) 233 { 234 struct mvsata_hc *mvhc; 235 struct mvsata_port *mvport; 236 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 237 void (*_fix_phy)(struct mvsata_port *) = NULL; 238 #ifndef MVSATA_WITHOUTDMA 239 void (*edma_setup_crqb) 240 (struct mvsata_port *, int, int, struct ata_bio *) = NULL; 241 #endif 242 int hc, port, channel; 243 244 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 245 (product->generation == gen1) ? "I" : 246 ((product->generation == gen2) ? "II" : "IIe"), 247 product->hc, product->port); 248 249 250 switch (product->generation) { 251 case gen1: 252 mvsata_sreset = NULL; 253 read_pre_amps = 1; /* MUST */ 254 read_preamps = mvsata_read_preamps_gen1; 255 _fix_phy = mvsata_fix_phy_gen1; 256 #ifndef MVSATA_WITHOUTDMA 257 edma_setup_crqb = mvsata_edma_setup_crqb; 258 #endif 259 break; 260 261 case gen2: 262 read_preamps = mvsata_read_preamps_gen2; 263 _fix_phy = mvsata_fix_phy_gen2; 264 #ifndef MVSATA_WITHOUTDMA 265 edma_setup_crqb = mvsata_edma_setup_crqb; 266 #endif 267 break; 268 269 case gen2e: 270 read_preamps = mvsata_read_preamps_gen2; 271 _fix_phy = mvsata_fix_phy_gen2; 272 #ifndef MVSATA_WITHOUTDMA 273 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 274 #endif 275 break; 276 } 277 278 sc->sc_gen = product->generation; 279 sc->sc_hc = product->hc; 280 sc->sc_port = product->port; 281 sc->sc_flags = product->flags; 282 283 #ifdef MVSATA_WITHOUTDMA 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 285 #else 286 sc->sc_edma_setup_crqb = edma_setup_crqb; 287 sc->sc_wdcdev.sc_atac.atac_cap |= 288 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 289 #endif 290 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 291 #ifdef MVSATA_WITHOUTDMA 292 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 293 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 294 #else 295 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 297 #endif 298 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 299 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 300 #ifndef MVSATA_WITHOUTDMA 301 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 302 #if NATAPIBUS > 0 303 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 304 #endif 305 #endif 306 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 307 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 308 309 sc->sc_wdc_regs = 310 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 311 M_DEVBUF, M_NOWAIT); 312 if (sc->sc_wdc_regs == NULL) { 313 aprint_error_dev(MVSATA_DEV(sc), 314 "can't allocate wdc regs memory\n"); 315 return ENOMEM; 316 } 317 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 318 319 for (hc = 0; hc < sc->sc_hc; hc++) { 320 mvhc = &sc->sc_hcs[hc]; 321 mvhc->hc = hc; 322 mvhc->hc_sc = sc; 323 mvhc->hc_iot = sc->sc_iot; 324 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 325 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 326 &mvhc->hc_ioh)) { 327 aprint_error_dev(MVSATA_DEV(sc), 328 "can't subregion SATAHC %d registers\n", hc); 329 continue; 330 } 331 332 for (port = 0; port < sc->sc_port; port++) 333 if (mvsata_port_init(mvhc, port) == 0) { 334 int pre_amps; 335 336 mvport = mvhc->hc_ports[port]; 337 pre_amps = read_pre_amps ? 338 read_preamps(mvport) : 0x00000720; 339 mvport->_fix_phy_param.pre_amps = pre_amps; 340 mvport->_fix_phy_param._fix_phy = _fix_phy; 341 342 if (!mvsata_sreset) 343 mvsata_reset_port(mvport); 344 } 345 346 if (!mvsata_sreset) 347 mvsata_reset_hc(mvhc); 348 } 349 if (mvsata_sreset) 350 mvsata_sreset(sc); 351 352 if (mvsata_misc_reset) 353 mvsata_misc_reset(sc); 354 355 for (hc = 0; hc < sc->sc_hc; hc++) 356 for (port = 0; port < sc->sc_port; port++) { 357 mvport = sc->sc_hcs[hc].hc_ports[port]; 358 if (mvport == NULL) 359 continue; 360 if (mvsata_sreset) 361 mvport->_fix_phy_param._fix_phy(mvport); 362 } 363 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 364 wdcattach(sc->sc_ata_channels[channel]); 365 366 return 0; 367 } 368 369 int 370 mvsata_intr(struct mvsata_hc *mvhc) 371 { 372 struct mvsata_softc *sc = mvhc->hc_sc; 373 struct mvsata_port *mvport; 374 uint32_t cause; 375 int port, handled = 0; 376 377 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 378 379 DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n", 380 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 381 382 if (cause & SATAHC_IC_SAINTCOAL) 383 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 384 cause &= ~SATAHC_IC_SAINTCOAL; 385 for (port = 0; port < sc->sc_port; port++) { 386 mvport = mvhc->hc_ports[port]; 387 388 if (cause & SATAHC_IC_DONE(port)) { 389 #ifndef MVSATA_WITHOUTDMA 390 handled = mvsata_edma_handle(mvport, NULL); 391 #endif 392 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 393 ~SATAHC_IC_DONE(port)); 394 } 395 396 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 397 wdcintr(&mvport->port_ata_channel); 398 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 399 ~SATAHC_IC_SADEVINTERRUPT(port)); 400 handled = 1; 401 } 402 } 403 404 return handled; 405 } 406 407 int 408 mvsata_error(struct mvsata_port *mvport) 409 { 410 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 411 uint32_t cause; 412 int handled = 0; 413 414 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 415 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 416 417 DPRINTFN(3, ("%s:%d:%d:" 418 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 419 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 420 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 421 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 422 423 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 424 if (!cause) 425 return 0; 426 427 /* If PM connected, connect/disconnect interrupts storm could happen */ 428 if (MVSATA_EDMA_READ_4(mvport, EDMA_IEC) & 429 (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) 430 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 431 delay(20 * 1000); 432 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 433 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 434 } 435 436 if (cause & EDMA_IE_EDEVDIS) 437 aprint_normal("%s:%d:%d: device disconnect\n", 438 device_xname(MVSATA_DEV2(mvport)), 439 mvport->port_hc->hc, mvport->port); 440 if (cause & EDMA_IE_EDEVCON) { 441 if (sc->sc_gen == gen1) 442 mvsata_devconn_gen1(mvport); 443 444 DPRINTFN(3, (" device connected\n")); 445 handled = 1; 446 } 447 #ifndef MVSATA_WITHOUTDMA 448 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 449 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 450 switch (mvport->port_edmamode) { 451 case dma: 452 case queued: 453 case ncq: 454 mvsata_edma_reset_qptr(mvport); 455 mvsata_edma_enable(mvport); 456 if (cause & EDMA_IE_EDEVERR) 457 break; 458 459 /* FALLTHROUGH */ 460 461 case nodma: 462 default: 463 aprint_error( 464 "%s:%d:%d: EDMA self disable happen 0x%x\n", 465 device_xname(MVSATA_DEV2(mvport)), 466 mvport->port_hc->hc, mvport->port, cause); 467 break; 468 } 469 handled = 1; 470 } 471 #endif 472 if (cause & EDMA_IE_ETRANSINT) { 473 /* hot plug the Port Multiplier */ 474 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 475 device_xname(MVSATA_DEV2(mvport)), 476 mvport->port_hc->hc, mvport->port); 477 } 478 479 return handled; 480 } 481 482 483 /* 484 * ATA callback entry points 485 */ 486 487 #ifndef MVSATA_WITHOUTDMA 488 static int 489 mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 490 { 491 struct ata_channel *chp = drvp->chnl_softc; 492 struct atac_softc *atac = chp->ch_atac; 493 struct ata_xfer *xfer; 494 495 DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 496 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 497 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 498 499 xfer = ata_get_xfer(ATAXF_NOSLEEP); 500 if (xfer == NULL) 501 return ATACMD_TRY_AGAIN; 502 if (atac->atac_cap & ATAC_CAP_NOIRQ) 503 ata_bio->flags |= ATA_POLL; 504 if (ata_bio->flags & ATA_POLL) 505 xfer->c_flags |= C_POLL; 506 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 507 (ata_bio->flags & ATA_SINGLE) == 0) 508 xfer->c_flags |= C_DMA; 509 xfer->c_drive = drvp->drive; 510 xfer->c_cmd = ata_bio; 511 xfer->c_databuf = ata_bio->databuf; 512 xfer->c_bcount = ata_bio->bcount; 513 xfer->c_start = mvsata_bio_start; 514 xfer->c_intr = mvsata_bio_intr; 515 xfer->c_kill_xfer = mvsata_bio_kill_xfer; 516 ata_exec_xfer(chp, xfer); 517 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 518 } 519 520 static void 521 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags) 522 { 523 struct ata_channel *chp = drvp->chnl_softc; 524 struct mvsata_port *mvport = (struct mvsata_port *)chp; 525 uint32_t edma_c; 526 527 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 528 529 DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 530 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 531 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 532 533 if (edma_c & EDMA_CMD_EENEDMA) 534 mvsata_edma_disable(mvport, 10000, flags & AT_WAIT); 535 536 mvsata_softreset(mvport, flags & AT_WAIT); 537 538 if (edma_c & EDMA_CMD_EENEDMA) { 539 mvsata_edma_reset_qptr(mvport); 540 mvsata_edma_enable(mvport); 541 } 542 return; 543 } 544 545 static void 546 mvsata_reset_channel(struct ata_channel *chp, int flags) 547 { 548 struct mvsata_port *mvport = (struct mvsata_port *)chp; 549 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 550 struct ata_xfer *xfer; 551 uint32_t sstat, ctrl; 552 int i; 553 554 DPRINTF(("%s: mvsata_reset_channel: channel=%d\n", 555 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 556 557 mvsata_hreset_port(mvport); 558 sstat = sata_reset_interface(chp, mvport->port_iot, 559 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 560 561 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 562 sc->sc_gen != gen1) { 563 /* Downgrade to GenI */ 564 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 565 SControl_DET_DISABLE; 566 567 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 568 569 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 570 ctrl &= ~(1 << 17); /* Disable GenII */ 571 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 572 573 mvsata_hreset_port(mvport); 574 sata_reset_interface(chp, mvport->port_iot, 575 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 576 } 577 578 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 579 xfer = mvport->port_reqtbl[i].xfer; 580 if (xfer == NULL) 581 continue; 582 chp->ch_queue->active_xfer = xfer; 583 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 584 } 585 586 mvsata_edma_config(mvport, mvport->port_edmamode); 587 mvsata_edma_reset_qptr(mvport); 588 mvsata_edma_enable(mvport); 589 return; 590 } 591 592 593 static int 594 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 595 { 596 struct ata_channel *chp = drvp->chnl_softc; 597 #ifdef MVSATA_DEBUG 598 struct mvsata_port *mvport = (struct mvsata_port *)chp; 599 #endif 600 struct ata_xfer *xfer; 601 int rv, s; 602 603 DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 604 " r_command=0x%x, r_head=0x%x, r_cyl=0x%x, r_sector=0x%x," 605 " r_count=0x%x, r_features=0x%x\n", 606 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 607 drvp->drive, ata_c->bcount, ata_c->r_command, ata_c->r_head, 608 ata_c->r_cyl, ata_c->r_sector, ata_c->r_count, ata_c->r_features)); 609 610 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 611 ATAXF_NOSLEEP); 612 if (xfer == NULL) 613 return ATACMD_TRY_AGAIN; 614 if (ata_c->flags & AT_POLL) 615 xfer->c_flags |= C_POLL; 616 if (ata_c->flags & AT_WAIT) 617 xfer->c_flags |= C_WAIT; 618 xfer->c_drive = drvp->drive; 619 xfer->c_databuf = ata_c->data; 620 xfer->c_bcount = ata_c->bcount; 621 xfer->c_cmd = ata_c; 622 xfer->c_start = mvsata_wdc_cmd_start; 623 xfer->c_intr = mvsata_wdc_cmd_intr; 624 xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer; 625 s = splbio(); 626 ata_exec_xfer(chp, xfer); 627 #ifdef DIAGNOSTIC 628 if ((ata_c->flags & AT_POLL) != 0 && 629 (ata_c->flags & AT_DONE) == 0) 630 panic("mvsata_exec_command: polled command not done"); 631 #endif 632 if (ata_c->flags & AT_DONE) 633 rv = ATACMD_COMPLETE; 634 else { 635 if (ata_c->flags & AT_WAIT) { 636 while ((ata_c->flags & AT_DONE) == 0) 637 tsleep(ata_c, PRIBIO, "mvsatacmd", 0); 638 rv = ATACMD_COMPLETE; 639 } else 640 rv = ATACMD_QUEUED; 641 } 642 splx(s); 643 return rv; 644 } 645 646 static int 647 mvsata_addref(struct ata_drive_datas *drvp) 648 { 649 650 return 0; 651 } 652 653 static void 654 mvsata_delref(struct ata_drive_datas *drvp) 655 { 656 657 return; 658 } 659 660 static void 661 mvsata_killpending(struct ata_drive_datas *drvp) 662 { 663 664 return; 665 } 666 667 #if NATAPIBUS > 0 668 static void 669 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 670 { 671 struct ata_channel *chp = ata_sc->sc_chan; 672 struct atac_softc *atac = chp->ch_atac; 673 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 674 struct scsipi_channel *chan = &chp->ch_atapi_channel; 675 676 /* 677 * Fill in the scsipi_adapter. 678 */ 679 adapt->adapt_dev = atac->atac_dev; 680 adapt->adapt_nchannels = atac->atac_nchannels; 681 adapt->adapt_request = mvsata_atapi_scsipi_request; 682 adapt->adapt_minphys = mvsata_atapi_minphys; 683 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 684 685 /* 686 * Fill in the scsipi_channel. 687 */ 688 memset(chan, 0, sizeof(*chan)); 689 chan->chan_adapter = adapt; 690 chan->chan_bustype = &mvsata_atapi_bustype; 691 chan->chan_channel = chp->ch_channel; 692 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 693 chan->chan_openings = 1; 694 chan->chan_max_periph = 1; 695 chan->chan_ntargets = 1; 696 chan->chan_nluns = 1; 697 698 chp->atapibus = 699 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 700 } 701 702 static void 703 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 704 scsipi_adapter_req_t req, void *arg) 705 { 706 struct scsipi_adapter *adapt = chan->chan_adapter; 707 struct scsipi_periph *periph; 708 struct scsipi_xfer *sc_xfer; 709 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 710 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 711 struct ata_xfer *xfer; 712 int channel = chan->chan_channel; 713 int drive, s; 714 715 switch (req) { 716 case ADAPTER_REQ_RUN_XFER: 717 sc_xfer = arg; 718 periph = sc_xfer->xs_periph; 719 drive = periph->periph_target; 720 721 if (!device_is_active(atac->atac_dev)) { 722 sc_xfer->error = XS_DRIVER_STUFFUP; 723 scsipi_done(sc_xfer); 724 return; 725 } 726 xfer = ata_get_xfer(ATAXF_NOSLEEP); 727 if (xfer == NULL) { 728 sc_xfer->error = XS_RESOURCE_SHORTAGE; 729 scsipi_done(sc_xfer); 730 return; 731 } 732 733 if (sc_xfer->xs_control & XS_CTL_POLL) 734 xfer->c_flags |= C_POLL; 735 xfer->c_drive = drive; 736 xfer->c_flags |= C_ATAPI; 737 xfer->c_cmd = sc_xfer; 738 xfer->c_databuf = sc_xfer->data; 739 xfer->c_bcount = sc_xfer->datalen; 740 xfer->c_start = mvsata_atapi_start; 741 xfer->c_intr = mvsata_atapi_intr; 742 xfer->c_kill_xfer = mvsata_atapi_kill_xfer; 743 xfer->c_dscpoll = 0; 744 s = splbio(); 745 ata_exec_xfer(atac->atac_channels[channel], xfer); 746 #ifdef DIAGNOSTIC 747 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 748 (sc_xfer->xs_status & XS_STS_DONE) == 0) 749 panic("mvsata_atapi_scsipi_request:" 750 " polled command not done"); 751 #endif 752 splx(s); 753 return; 754 755 default: 756 /* Not supported, nothing to do. */ 757 ; 758 } 759 } 760 761 static void 762 mvsata_atapi_minphys(struct buf *bp) 763 { 764 765 if (bp->b_bcount > MAXPHYS) 766 bp->b_bcount = MAXPHYS; 767 minphys(bp); 768 } 769 770 static void 771 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 772 { 773 struct scsipi_channel *chan = sc->sc_channel; 774 struct scsipi_periph *periph; 775 struct ataparams ids; 776 struct ataparams *id = &ids; 777 struct mvsata_softc *mvc = 778 device_private(chan->chan_adapter->adapt_dev); 779 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 780 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 781 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 782 struct scsipibus_attach_args sa; 783 char serial_number[21], model[41], firmware_revision[9]; 784 int s; 785 786 /* skip if already attached */ 787 if (scsipi_lookup_periph(chan, target, 0) != NULL) 788 return; 789 790 /* if no ATAPI device detected at attach time, skip */ 791 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 792 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 793 " drive %d not present\n", 794 device_xname(atac->atac_dev), chp->ch_channel, target)); 795 return; 796 } 797 798 /* Some ATAPI devices need a bit more time after software reset. */ 799 delay(5000); 800 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 801 #ifdef ATAPI_DEBUG_PROBE 802 log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n", 803 device_xname(atac->atac_dev), chp->ch_channel, target, 804 id->atap_config & ATAPI_CFG_CMD_MASK, 805 id->atap_config & ATAPI_CFG_DRQ_MASK); 806 #endif 807 periph = scsipi_alloc_periph(M_NOWAIT); 808 if (periph == NULL) { 809 aprint_error_dev(atac->atac_dev, 810 "unable to allocate periph" 811 " for channel %d drive %d\n", 812 chp->ch_channel, target); 813 return; 814 } 815 periph->periph_dev = NULL; 816 periph->periph_channel = chan; 817 periph->periph_switch = &atapi_probe_periphsw; 818 periph->periph_target = target; 819 periph->periph_lun = 0; 820 periph->periph_quirks = PQUIRK_ONLYBIG; 821 822 #ifdef SCSIPI_DEBUG 823 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 824 SCSIPI_DEBUG_TARGET == target) 825 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 826 #endif 827 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 828 if (id->atap_config & ATAPI_CFG_REMOV) 829 periph->periph_flags |= PERIPH_REMOVABLE; 830 if (periph->periph_type == T_SEQUENTIAL) { 831 s = splbio(); 832 drvp->drive_flags |= DRIVE_ATAPIST; 833 splx(s); 834 } 835 836 sa.sa_periph = periph; 837 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 838 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 839 T_REMOV : T_FIXED; 840 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 841 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 20); 842 scsipi_strvis((u_char *)firmware_revision, 8, id->atap_revision, 843 8); 844 sa.sa_inqbuf.vendor = model; 845 sa.sa_inqbuf.product = serial_number; 846 sa.sa_inqbuf.revision = firmware_revision; 847 848 /* 849 * Determine the operating mode capabilities of the device. 850 */ 851 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 852 periph->periph_cap |= PERIPH_CAP_CMD16; 853 /* XXX This is gross. */ 854 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 855 856 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 857 858 if (drvp->drv_softc) 859 ata_probe_caps(drvp); 860 else { 861 s = splbio(); 862 drvp->drive_flags &= ~DRIVE_ATAPI; 863 splx(s); 864 } 865 } else { 866 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 867 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n", 868 device_xname(atac->atac_dev), chp->ch_channel, target, 869 chp->ch_error)); 870 s = splbio(); 871 drvp->drive_flags &= ~DRIVE_ATAPI; 872 splx(s); 873 } 874 } 875 876 /* 877 * Kill off all pending xfers for a periph. 878 * 879 * Must be called at splbio(). 880 */ 881 static void 882 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 883 { 884 struct atac_softc *atac = 885 device_private(periph->periph_channel->chan_adapter->adapt_dev); 886 struct ata_channel *chp = 887 atac->atac_channels[periph->periph_channel->chan_channel]; 888 889 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 890 } 891 #endif /* NATAPIBUS > 0 */ 892 #endif /* MVSATA_WITHOUTDMA */ 893 894 895 /* 896 * mvsata_setup_channel() 897 * Setup EDMA registers and prepare/purge DMA resources. 898 * We assuming already stopped the EDMA. 899 */ 900 static void 901 mvsata_setup_channel(struct ata_channel *chp) 902 { 903 #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG) 904 struct mvsata_port *mvport = (struct mvsata_port *)chp; 905 #endif 906 struct ata_drive_datas *drvp; 907 uint32_t edma_mode; 908 int drive, s; 909 #ifndef MVSATA_WITHOUTDMA 910 int i; 911 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 912 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 913 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 914 #endif 915 916 DPRINTF(("%s:%d: mvsata_setup_channel: ", 917 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 918 919 edma_mode = nodma; 920 for (drive = 0; drive < chp->ch_ndrive; drive++) { 921 drvp = &chp->ch_drive[drive]; 922 923 /* If no drive, skip */ 924 if (!(drvp->drive_flags & DRIVE)) 925 continue; 926 927 if (drvp->drive_flags & DRIVE_UDMA) { 928 /* use Ultra/DMA */ 929 s = splbio(); 930 drvp->drive_flags &= ~DRIVE_DMA; 931 splx(s); 932 } 933 934 if (drvp->drive_flags & (DRIVE_UDMA | DRIVE_DMA)) 935 if (drvp->drive_flags & DRIVE_ATA) 936 edma_mode = dma; 937 } 938 939 DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 940 941 #ifndef MVSATA_WITHOUTDMA 942 if (edma_mode == nodma) { 943 no_edma: 944 if (mvport->port_crqb != NULL) 945 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 946 mvport->port_crqb_dmamap, mvport->port_crqb); 947 if (mvport->port_crpb != NULL) 948 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 949 mvport->port_crpb_dmamap, mvport->port_crpb); 950 if (mvport->port_eprd != NULL) 951 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 952 mvport->port_eprd_dmamap, mvport->port_eprd); 953 954 return; 955 } 956 957 if (mvport->port_crqb == NULL) 958 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 959 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 960 if (mvport->port_crpb == NULL) 961 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 962 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 963 if (mvport->port_eprd == NULL) { 964 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 965 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 966 1); 967 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 968 mvport->port_reqtbl[i].eprd_offset = 969 i * MVSATA_EPRD_MAX_SIZE; 970 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 971 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 972 } 973 } 974 975 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 976 mvport->port_eprd == NULL) { 977 aprint_error_dev(MVSATA_DEV2(mvport), 978 "channel %d: can't use EDMA\n", chp->ch_channel); 979 s = splbio(); 980 for (drive = 0; drive < chp->ch_ndrive; drive++) { 981 drvp = &chp->ch_drive[drive]; 982 983 /* If no drive, skip */ 984 if (!(drvp->drive_flags & DRIVE)) 985 continue; 986 987 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 988 } 989 splx(s); 990 goto no_edma; 991 } 992 993 mvsata_edma_config(mvport, edma_mode); 994 mvsata_edma_reset_qptr(mvport); 995 mvsata_edma_enable(mvport); 996 #endif 997 } 998 999 #ifndef MVSATA_WITHOUTDMA 1000 static void 1001 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1002 { 1003 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1004 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1005 struct atac_softc *atac = chp->ch_atac; 1006 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1007 struct ata_bio *ata_bio = xfer->c_cmd; 1008 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1009 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1010 u_int16_t cyl; 1011 u_int8_t head, sect, cmd = 0; 1012 int nblks, error; 1013 1014 DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n", 1015 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1016 1017 if (xfer->c_flags & C_DMA) 1018 if (drvp->n_xfers <= NXFER) 1019 drvp->n_xfers++; 1020 1021 again: 1022 /* 1023 * 1024 * When starting a multi-sector transfer, or doing single-sector 1025 * transfers... 1026 */ 1027 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1028 if (ata_bio->flags & ATA_SINGLE) 1029 nblks = 1; 1030 else 1031 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1032 /* Check for bad sectors and adjust transfer, if necessary. */ 1033 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 1034 long blkdiff; 1035 int i; 1036 1037 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 1038 i++) { 1039 blkdiff -= ata_bio->blkno; 1040 if (blkdiff < 0) 1041 continue; 1042 if (blkdiff == 0) 1043 /* Replace current block of transfer. */ 1044 ata_bio->blkno = 1045 ata_bio->lp->d_secperunit - 1046 ata_bio->lp->d_nsectors - i - 1; 1047 if (blkdiff < nblks) { 1048 /* Bad block inside transfer. */ 1049 ata_bio->flags |= ATA_SINGLE; 1050 nblks = 1; 1051 } 1052 break; 1053 } 1054 /* Transfer is okay now. */ 1055 } 1056 if (xfer->c_flags & C_DMA) { 1057 ata_bio->nblks = nblks; 1058 ata_bio->nbytes = xfer->c_bcount; 1059 1060 if (xfer->c_flags & C_POLL) 1061 sc->sc_enable_intr(mvport, 0 /*off*/); 1062 error = mvsata_edma_enqueue(mvport, ata_bio, 1063 (char *)xfer->c_databuf + xfer->c_skip); 1064 if (error) { 1065 if (error == EINVAL) { 1066 /* 1067 * We can't do DMA on this transfer 1068 * for some reason. Fall back to 1069 * PIO. 1070 */ 1071 xfer->c_flags &= ~C_DMA; 1072 error = 0; 1073 goto do_pio; 1074 } 1075 if (error == EBUSY) { 1076 aprint_error_dev(atac->atac_dev, 1077 "channel %d: EDMA Queue full\n", 1078 chp->ch_channel); 1079 /* 1080 * XXXX: Perhaps, after it waits for 1081 * a while, it is necessary to call 1082 * bio_start again. 1083 */ 1084 } 1085 ata_bio->error = ERR_DMA; 1086 ata_bio->r_error = 0; 1087 mvsata_bio_done(chp, xfer); 1088 return; 1089 } 1090 chp->ch_flags |= ATACH_DMA_WAIT; 1091 /* start timeout machinery */ 1092 if ((xfer->c_flags & C_POLL) == 0) 1093 callout_reset(&chp->ch_callout, 1094 ATA_DELAY / 1000 * hz, 1095 mvsata_edma_timeout, xfer); 1096 /* wait for irq */ 1097 goto intr; 1098 } /* else not DMA */ 1099 do_pio: 1100 if (ata_bio->flags & ATA_LBA48) { 1101 sect = 0; 1102 cyl = 0; 1103 head = 0; 1104 } else if (ata_bio->flags & ATA_LBA) { 1105 sect = (ata_bio->blkno >> 0) & 0xff; 1106 cyl = (ata_bio->blkno >> 8) & 0xffff; 1107 head = (ata_bio->blkno >> 24) & 0x0f; 1108 head |= WDSD_LBA; 1109 } else { 1110 int blkno = ata_bio->blkno; 1111 sect = blkno % ata_bio->lp->d_nsectors; 1112 sect++; /* Sectors begin with 1, not 0. */ 1113 blkno /= ata_bio->lp->d_nsectors; 1114 head = blkno % ata_bio->lp->d_ntracks; 1115 blkno /= ata_bio->lp->d_ntracks; 1116 cyl = blkno; 1117 head |= WDSD_CHS; 1118 } 1119 ata_bio->nblks = min(nblks, ata_bio->multi); 1120 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 1121 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1122 if (ata_bio->nblks > 1) 1123 cmd = (ata_bio->flags & ATA_READ) ? 1124 WDCC_READMULTI : WDCC_WRITEMULTI; 1125 else 1126 cmd = (ata_bio->flags & ATA_READ) ? 1127 WDCC_READ : WDCC_WRITE; 1128 1129 /* EDMA disable, if enabled this channel. */ 1130 if (mvport->port_edmamode != nodma) 1131 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1132 1133 /* Do control operations specially. */ 1134 if (__predict_false(drvp->state < READY)) { 1135 /* 1136 * Actually, we want to be careful not to mess with 1137 * the control state if the device is currently busy, 1138 * but we can assume that we never get to this point 1139 * if that's the case. 1140 */ 1141 /* 1142 * If it's not a polled command, we need the kernel 1143 * thread 1144 */ 1145 if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) { 1146 chp->ch_queue->queue_freeze++; 1147 wakeup(&chp->ch_thread); 1148 return; 1149 } 1150 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1151 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1152 mvsata_bio_done(chp, xfer); 1153 return; 1154 } 1155 } 1156 1157 /* Initiate command! */ 1158 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1159 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 1160 case WDCWAIT_OK: 1161 break; 1162 case WDCWAIT_TOUT: 1163 goto timeout; 1164 case WDCWAIT_THR: 1165 return; 1166 } 1167 if (ata_bio->flags & ATA_LBA48) 1168 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 1169 (uint64_t)ata_bio->blkno, nblks, 0); 1170 else 1171 wdccommand(chp, xfer->c_drive, cmd, cyl, 1172 head, sect, nblks, 1173 (ata_bio->lp->d_type == DTYPE_ST506) ? 1174 ata_bio->lp->d_precompcyl / 4 : 0); 1175 1176 /* start timeout machinery */ 1177 if ((xfer->c_flags & C_POLL) == 0) 1178 callout_reset(&chp->ch_callout, 1179 ATA_DELAY / 1000 * hz, wdctimeout, chp); 1180 } else if (ata_bio->nblks > 1) { 1181 /* The number of blocks in the last stretch may be smaller. */ 1182 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1183 if (ata_bio->nblks > nblks) { 1184 ata_bio->nblks = nblks; 1185 ata_bio->nbytes = xfer->c_bcount; 1186 } 1187 } 1188 /* If this was a write and not using DMA, push the data. */ 1189 if ((ata_bio->flags & ATA_READ) == 0) { 1190 /* 1191 * we have to busy-wait here, we can't rely on running in 1192 * thread context. 1193 */ 1194 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 1195 aprint_error_dev(atac->atac_dev, 1196 "channel %d: drive %d timeout waiting for DRQ," 1197 " st=0x%02x, err=0x%02x\n", 1198 chp->ch_channel, xfer->c_drive, chp->ch_status, 1199 chp->ch_error); 1200 ata_bio->error = TIMEOUT; 1201 mvsata_bio_done(chp, xfer); 1202 return; 1203 } 1204 if (chp->ch_status & WDCS_ERR) { 1205 ata_bio->error = ERROR; 1206 ata_bio->r_error = chp->ch_error; 1207 mvsata_bio_done(chp, xfer); 1208 return; 1209 } 1210 1211 wdc->dataout_pio(chp, drvp->drive_flags, 1212 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1213 } 1214 1215 intr: 1216 /* Wait for IRQ (either real or polled) */ 1217 if ((ata_bio->flags & ATA_POLL) == 0) { 1218 chp->ch_flags |= ATACH_IRQ_WAIT; 1219 } else { 1220 /* Wait for at last 400ns for status bit to be valid */ 1221 delay(1); 1222 if (chp->ch_flags & ATACH_DMA_WAIT) { 1223 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1224 sc->sc_enable_intr(mvport, 1 /*on*/); 1225 chp->ch_flags &= ~ATACH_DMA_WAIT; 1226 } 1227 mvsata_bio_intr(chp, xfer, 0); 1228 if ((ata_bio->flags & ATA_ITSDONE) == 0) 1229 goto again; 1230 } 1231 return; 1232 1233 timeout: 1234 aprint_error_dev(atac->atac_dev, 1235 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1236 chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error); 1237 ata_bio->error = TIMEOUT; 1238 mvsata_bio_done(chp, xfer); 1239 return; 1240 } 1241 1242 static int 1243 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1244 { 1245 struct atac_softc *atac = chp->ch_atac; 1246 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1247 struct ata_bio *ata_bio = xfer->c_cmd; 1248 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1249 1250 DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n", 1251 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1252 1253 chp->ch_flags &= ~(ATACH_IRQ_WAIT|ATACH_DMA_WAIT); 1254 1255 /* Is it not a transfer, but a control operation? */ 1256 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1257 aprint_error_dev(atac->atac_dev, 1258 "channel %d: drive %d bad state %d in mvsata_bio_intr\n", 1259 chp->ch_channel, xfer->c_drive, drvp->state); 1260 panic("mvsata_bio_intr: bad state"); 1261 } 1262 1263 /* 1264 * If we missed an interrupt transfer, reset and restart. 1265 * Don't try to continue transfer, we may have missed cycles. 1266 */ 1267 if (xfer->c_flags & C_TIMEOU) { 1268 ata_bio->error = TIMEOUT; 1269 mvsata_bio_done(chp, xfer); 1270 return 1; 1271 } 1272 1273 /* Ack interrupt done by wdc_wait_for_unbusy */ 1274 if (!(xfer->c_flags & C_DMA) && 1275 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) 1276 == WDCWAIT_TOUT)) { 1277 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1278 return 0; /* IRQ was not for us */ 1279 aprint_error_dev(atac->atac_dev, 1280 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1281 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1282 xfer->c_skip); 1283 ata_bio->error = TIMEOUT; 1284 mvsata_bio_done(chp, xfer); 1285 return 1; 1286 } 1287 1288 if (xfer->c_flags & C_DMA) { 1289 if (ata_bio->error == NOERROR) 1290 goto end; 1291 if (ata_bio->error == ERR_DMA) 1292 ata_dmaerr(drvp, 1293 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1294 } 1295 1296 /* if we had an error, end */ 1297 if (ata_bio->error != NOERROR) { 1298 mvsata_bio_done(chp, xfer); 1299 return 1; 1300 } 1301 1302 /* If this was a read and not using DMA, fetch the data. */ 1303 if ((ata_bio->flags & ATA_READ) != 0) { 1304 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 1305 aprint_error_dev(atac->atac_dev, 1306 "channel %d: drive %d read intr before drq\n", 1307 chp->ch_channel, xfer->c_drive); 1308 ata_bio->error = TIMEOUT; 1309 mvsata_bio_done(chp, xfer); 1310 return 1; 1311 } 1312 wdc->datain_pio(chp, drvp->drive_flags, 1313 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1314 } 1315 1316 end: 1317 ata_bio->blkno += ata_bio->nblks; 1318 ata_bio->blkdone += ata_bio->nblks; 1319 xfer->c_skip += ata_bio->nbytes; 1320 xfer->c_bcount -= ata_bio->nbytes; 1321 /* See if this transfer is complete. */ 1322 if (xfer->c_bcount > 0) { 1323 if ((ata_bio->flags & ATA_POLL) == 0) 1324 /* Start the next operation */ 1325 mvsata_bio_start(chp, xfer); 1326 else 1327 /* Let mvsata_bio_start do the loop */ 1328 return 1; 1329 } else { /* Done with this transfer */ 1330 ata_bio->error = NOERROR; 1331 mvsata_bio_done(chp, xfer); 1332 } 1333 return 1; 1334 } 1335 1336 static void 1337 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1338 { 1339 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1340 struct atac_softc *atac = chp->ch_atac; 1341 struct ata_bio *ata_bio = xfer->c_cmd; 1342 int drive = xfer->c_drive; 1343 1344 DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1345 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1346 1347 /* EDMA restart, if enabled */ 1348 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1349 mvsata_edma_reset_qptr(mvport); 1350 mvsata_edma_enable(mvport); 1351 } 1352 1353 ata_free_xfer(chp, xfer); 1354 1355 ata_bio->flags |= ATA_ITSDONE; 1356 switch (reason) { 1357 case KILL_GONE: 1358 ata_bio->error = ERR_NODEV; 1359 break; 1360 case KILL_RESET: 1361 ata_bio->error = ERR_RESET; 1362 break; 1363 default: 1364 aprint_error_dev(atac->atac_dev, 1365 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1366 panic("mvsata_bio_kill_xfer"); 1367 } 1368 ata_bio->r_error = WDCE_ABRT; 1369 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1370 } 1371 1372 static void 1373 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1374 { 1375 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1376 struct ata_bio *ata_bio = xfer->c_cmd; 1377 int drive = xfer->c_drive; 1378 1379 DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1380 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1381 (u_int)xfer->c_flags)); 1382 1383 callout_stop(&chp->ch_callout); 1384 1385 /* EDMA restart, if enabled */ 1386 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1387 mvsata_edma_reset_qptr(mvport); 1388 mvsata_edma_enable(mvport); 1389 } 1390 1391 /* feed back residual bcount to our caller */ 1392 ata_bio->bcount = xfer->c_bcount; 1393 1394 /* mark controller inactive and free xfer */ 1395 KASSERT(chp->ch_queue->active_xfer != NULL); 1396 chp->ch_queue->active_xfer = NULL; 1397 ata_free_xfer(chp, xfer); 1398 1399 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1400 ata_bio->error = ERR_NODEV; 1401 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1402 wakeup(&chp->ch_queue->active_xfer); 1403 } 1404 ata_bio->flags |= ATA_ITSDONE; 1405 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1406 atastart(chp); 1407 } 1408 1409 static int 1410 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1411 int flags) 1412 { 1413 struct ata_channel *chp = &mvport->port_ata_channel; 1414 struct atac_softc *atac = chp->ch_atac; 1415 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1416 const char *errstring; 1417 1418 flags |= AT_POLL; /* XXX */ 1419 1420 /* 1421 * disable interrupts, all commands here should be quick 1422 * enough to be able to poll, and we don't go here that often 1423 */ 1424 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1425 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1426 DELAY(10); 1427 errstring = "wait"; 1428 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1429 goto ctrltimeout; 1430 wdccommandshort(chp, drive, WDCC_RECAL); 1431 /* Wait for at last 400ns for status bit to be valid */ 1432 DELAY(1); 1433 errstring = "recal"; 1434 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1435 goto ctrltimeout; 1436 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1437 goto ctrlerror; 1438 /* Don't try to set modes if controller can't be adjusted */ 1439 if (atac->atac_set_modes == NULL) 1440 goto geometry; 1441 /* Also don't try if the drive didn't report its mode */ 1442 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1443 goto geometry; 1444 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1445 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1446 errstring = "piomode"; 1447 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1448 goto ctrltimeout; 1449 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1450 goto ctrlerror; 1451 if (drvp->drive_flags & DRIVE_UDMA) 1452 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1453 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1454 else if (drvp->drive_flags & DRIVE_DMA) 1455 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1456 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1457 else 1458 goto geometry; 1459 errstring = "dmamode"; 1460 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1461 goto ctrltimeout; 1462 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1463 goto ctrlerror; 1464 geometry: 1465 if (ata_bio->flags & ATA_LBA) 1466 goto multimode; 1467 wdccommand(chp, drive, WDCC_IDP, ata_bio->lp->d_ncylinders, 1468 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 1469 (ata_bio->lp->d_type == DTYPE_ST506) ? 1470 ata_bio->lp->d_precompcyl / 4 : 0); 1471 errstring = "geometry"; 1472 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1473 goto ctrltimeout; 1474 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1475 goto ctrlerror; 1476 multimode: 1477 if (ata_bio->multi == 1) 1478 goto ready; 1479 wdccommand(chp, drive, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0); 1480 errstring = "setmulti"; 1481 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1482 goto ctrltimeout; 1483 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1484 goto ctrlerror; 1485 ready: 1486 drvp->state = READY; 1487 /* 1488 * The drive is usable now 1489 */ 1490 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1491 delay(10); /* some drives need a little delay here */ 1492 return 0; 1493 1494 ctrltimeout: 1495 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1496 chp->ch_channel, drive, errstring); 1497 ata_bio->error = TIMEOUT; 1498 goto ctrldone; 1499 ctrlerror: 1500 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1501 chp->ch_channel, drive, errstring); 1502 if (chp->ch_status & WDCS_DWF) { 1503 aprint_error("drive fault\n"); 1504 ata_bio->error = ERR_DF; 1505 } else { 1506 aprint_error("error (%x)\n", chp->ch_error); 1507 ata_bio->r_error = chp->ch_error; 1508 ata_bio->error = ERROR; 1509 } 1510 ctrldone: 1511 drvp->state = 0; 1512 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1513 return -1; 1514 } 1515 1516 static void 1517 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1518 { 1519 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1520 int drive = xfer->c_drive; 1521 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1522 struct ata_command *ata_c = xfer->c_cmd; 1523 1524 DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n", 1525 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1526 1527 /* First, EDMA disable, if enabled this channel. */ 1528 if (mvport->port_edmamode != nodma) 1529 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1530 1531 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1532 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1533 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1534 case WDCWAIT_OK: 1535 break; 1536 case WDCWAIT_TOUT: 1537 ata_c->flags |= AT_TIMEOU; 1538 mvsata_wdc_cmd_done(chp, xfer); 1539 return; 1540 case WDCWAIT_THR: 1541 return; 1542 } 1543 if (ata_c->flags & AT_POLL) 1544 /* polled command, disable interrupts */ 1545 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1546 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1547 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1548 1549 if ((ata_c->flags & AT_POLL) == 0) { 1550 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1551 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1552 wdctimeout, chp); 1553 return; 1554 } 1555 /* 1556 * Polled command. Wait for drive ready or drq. Done in intr(). 1557 * Wait for at last 400ns for status bit to be valid. 1558 */ 1559 delay(10); /* 400ns delay */ 1560 mvsata_wdc_cmd_intr(chp, xfer, 0); 1561 } 1562 1563 static int 1564 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1565 { 1566 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1567 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1568 struct ata_command *ata_c = xfer->c_cmd; 1569 int bcount = ata_c->bcount; 1570 char *data = ata_c->data; 1571 int wflags; 1572 int drive_flags; 1573 1574 if (ata_c->r_command == WDCC_IDENTIFY || 1575 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1576 /* 1577 * The IDENTIFY data has been designed as an array of 1578 * u_int16_t, so we can byteswap it on the fly. 1579 * Historically it's what we have always done so keeping it 1580 * here ensure binary backward compatibility. 1581 */ 1582 drive_flags = DRIVE_NOSTREAM | 1583 chp->ch_drive[xfer->c_drive].drive_flags; 1584 else 1585 /* 1586 * Other data structure are opaque and should be transfered 1587 * as is. 1588 */ 1589 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1590 1591 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1592 /* both wait and poll, we can tsleep here */ 1593 wflags = AT_WAIT | AT_POLL; 1594 else 1595 wflags = AT_POLL; 1596 1597 again: 1598 DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n", 1599 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1600 1601 /* 1602 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1603 * Reselect again, it doesn't hurt for others commands, and the time 1604 * penalty for the extra regiter write is acceptable, 1605 * wdc_exec_command() isn't called often (mosly for autoconfig) 1606 */ 1607 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1608 if ((ata_c->flags & AT_XFDONE) != 0) { 1609 /* 1610 * We have completed a data xfer. The drive should now be 1611 * in its initial state 1612 */ 1613 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1614 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1615 wflags) == WDCWAIT_TOUT) { 1616 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1617 return 0; /* IRQ was not for us */ 1618 ata_c->flags |= AT_TIMEOU; 1619 } 1620 goto out; 1621 } 1622 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1623 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1624 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1625 return 0; /* IRQ was not for us */ 1626 ata_c->flags |= AT_TIMEOU; 1627 goto out; 1628 } 1629 if (ata_c->flags & AT_READ) { 1630 if ((chp->ch_status & WDCS_DRQ) == 0) { 1631 ata_c->flags |= AT_TIMEOU; 1632 goto out; 1633 } 1634 wdc->datain_pio(chp, drive_flags, data, bcount); 1635 /* at this point the drive should be in its initial state */ 1636 ata_c->flags |= AT_XFDONE; 1637 /* 1638 * XXX checking the status register again here cause some 1639 * hardware to timeout. 1640 */ 1641 } else if (ata_c->flags & AT_WRITE) { 1642 if ((chp->ch_status & WDCS_DRQ) == 0) { 1643 ata_c->flags |= AT_TIMEOU; 1644 goto out; 1645 } 1646 wdc->dataout_pio(chp, drive_flags, data, bcount); 1647 ata_c->flags |= AT_XFDONE; 1648 if ((ata_c->flags & AT_POLL) == 0) { 1649 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */ 1650 callout_reset(&chp->ch_callout, 1651 mstohz(ata_c->timeout), wdctimeout, chp); 1652 return 1; 1653 } else 1654 goto again; 1655 } 1656 out: 1657 mvsata_wdc_cmd_done(chp, xfer); 1658 return 1; 1659 } 1660 1661 static void 1662 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1663 int reason) 1664 { 1665 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1666 struct ata_command *ata_c = xfer->c_cmd; 1667 1668 DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1669 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1670 1671 switch (reason) { 1672 case KILL_GONE: 1673 ata_c->flags |= AT_GONE; 1674 break; 1675 case KILL_RESET: 1676 ata_c->flags |= AT_RESET; 1677 break; 1678 default: 1679 aprint_error_dev(MVSATA_DEV2(mvport), 1680 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1681 panic("mvsata_cmd_kill_xfer"); 1682 } 1683 mvsata_wdc_cmd_done_end(chp, xfer); 1684 } 1685 1686 static void 1687 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1688 { 1689 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1690 struct atac_softc *atac = chp->ch_atac; 1691 struct ata_command *ata_c = xfer->c_cmd; 1692 1693 DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1694 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1695 ata_c->flags)); 1696 1697 if (chp->ch_status & WDCS_DWF) 1698 ata_c->flags |= AT_DF; 1699 if (chp->ch_status & WDCS_ERR) { 1700 ata_c->flags |= AT_ERROR; 1701 ata_c->r_error = chp->ch_error; 1702 } 1703 if ((ata_c->flags & AT_READREG) != 0 && 1704 device_is_active(atac->atac_dev) && 1705 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1706 ata_c->r_head = MVSATA_WDC_READ_1(mvport, SRB_H); 1707 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1708 ata_c->r_sector = MVSATA_WDC_READ_1(mvport, SRB_LBAL); 1709 ata_c->r_cyl = MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1710 ata_c->r_cyl |= MVSATA_WDC_READ_1(mvport, SRB_LBAH); 1711 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1712 ata_c->r_features = ata_c->r_error; 1713 } 1714 callout_stop(&chp->ch_callout); 1715 chp->ch_queue->active_xfer = NULL; 1716 if (ata_c->flags & AT_POLL) { 1717 /* enable interrupts */ 1718 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1719 delay(10); /* some drives need a little delay here */ 1720 } 1721 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1722 mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE); 1723 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1724 wakeup(&chp->ch_queue->active_xfer); 1725 } else 1726 mvsata_wdc_cmd_done_end(chp, xfer); 1727 } 1728 1729 static void 1730 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1731 { 1732 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1733 struct ata_command *ata_c = xfer->c_cmd; 1734 1735 /* EDMA restart, if enabled */ 1736 if (mvport->port_edmamode != nodma) { 1737 mvsata_edma_reset_qptr(mvport); 1738 mvsata_edma_enable(mvport); 1739 } 1740 1741 ata_c->flags |= AT_DONE; 1742 ata_free_xfer(chp, xfer); 1743 if (ata_c->flags & AT_WAIT) 1744 wakeup(ata_c); 1745 else if (ata_c->callback) 1746 ata_c->callback(ata_c->callback_arg); 1747 atastart(chp); 1748 1749 return; 1750 } 1751 1752 #if NATAPIBUS > 0 1753 static void 1754 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1755 { 1756 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 1757 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1758 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1759 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1760 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1761 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1762 const char *errstring; 1763 1764 DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 1765 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1766 xfer->c_drive, sc_xfer->xs_control)); 1767 1768 if (mvport->port_edmamode != nodma) 1769 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1770 1771 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 1772 drvp->n_xfers++; 1773 1774 /* Do control operations specially. */ 1775 if (__predict_false(drvp->state < READY)) { 1776 /* If it's not a polled command, we need the kernel thread */ 1777 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) { 1778 chp->ch_queue->queue_freeze++; 1779 wakeup(&chp->ch_thread); 1780 return; 1781 } 1782 /* 1783 * disable interrupts, all commands here should be quick 1784 * enough to be able to poll, and we don't go here that often 1785 */ 1786 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1787 1788 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1789 /* Don't try to set mode if controller can't be adjusted */ 1790 if (atac->atac_set_modes == NULL) 1791 goto ready; 1792 /* Also don't try if the drive didn't report its mode */ 1793 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1794 goto ready; 1795 errstring = "unbusy"; 1796 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) 1797 goto timeout; 1798 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1799 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1800 errstring = "piomode"; 1801 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1802 goto timeout; 1803 if (chp->ch_status & WDCS_ERR) { 1804 if (chp->ch_error == WDCE_ABRT) { 1805 /* 1806 * Some ATAPI drives reject PIO settings. 1807 * Fall back to PIO mode 3 since that's the 1808 * minimum for ATAPI. 1809 */ 1810 aprint_error_dev(atac->atac_dev, 1811 "channel %d drive %d: PIO mode %d rejected," 1812 " falling back to PIO mode 3\n", 1813 chp->ch_channel, xfer->c_drive, 1814 drvp->PIO_mode); 1815 if (drvp->PIO_mode > 3) 1816 drvp->PIO_mode = 3; 1817 } else 1818 goto error; 1819 } 1820 if (drvp->drive_flags & DRIVE_UDMA) 1821 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1822 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1823 else 1824 if (drvp->drive_flags & DRIVE_DMA) 1825 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1826 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1827 else 1828 goto ready; 1829 errstring = "dmamode"; 1830 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1831 goto timeout; 1832 if (chp->ch_status & WDCS_ERR) { 1833 if (chp->ch_error == WDCE_ABRT) { 1834 if (drvp->drive_flags & DRIVE_UDMA) 1835 goto error; 1836 else { 1837 /* 1838 * The drive rejected our DMA setting. 1839 * Fall back to mode 1. 1840 */ 1841 aprint_error_dev(atac->atac_dev, 1842 "channel %d drive %d:" 1843 " DMA mode %d rejected," 1844 " falling back to DMA mode 0\n", 1845 chp->ch_channel, xfer->c_drive, 1846 drvp->DMA_mode); 1847 if (drvp->DMA_mode > 0) 1848 drvp->DMA_mode = 0; 1849 } 1850 } else 1851 goto error; 1852 } 1853 ready: 1854 drvp->state = READY; 1855 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1856 delay(10); /* some drives need a little delay here */ 1857 } 1858 /* start timeout machinery */ 1859 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 1860 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1861 wdctimeout, chp); 1862 1863 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1864 switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) { 1865 case WDCWAIT_OK: 1866 break; 1867 case WDCWAIT_TOUT: 1868 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 1869 chp->ch_status); 1870 sc_xfer->error = XS_TIMEOUT; 1871 mvsata_atapi_reset(chp, xfer); 1872 return; 1873 case WDCWAIT_THR: 1874 return; 1875 } 1876 1877 /* 1878 * Even with WDCS_ERR, the device should accept a command packet 1879 * Limit length to what can be stuffed into the cylinder register 1880 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 1881 * but not all devices do that and it's not obvious from the 1882 * ATAPI spec that that behaviour should be expected. If more 1883 * data is necessary, multiple data transfer phases will be done. 1884 */ 1885 1886 wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD, 1887 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 1888 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1889 1890 /* 1891 * If there is no interrupt for CMD input, busy-wait for it (done in 1892 * the interrupt routine. If it is a polled command, call the interrupt 1893 * routine until command is done. 1894 */ 1895 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 1896 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) { 1897 /* Wait for at last 400ns for status bit to be valid */ 1898 DELAY(1); 1899 mvsata_atapi_intr(chp, xfer, 0); 1900 } else 1901 chp->ch_flags |= ATACH_IRQ_WAIT; 1902 if (sc_xfer->xs_control & XS_CTL_POLL) { 1903 if (chp->ch_flags & ATACH_DMA_WAIT) { 1904 wdc_dmawait(chp, xfer, sc_xfer->timeout); 1905 chp->ch_flags &= ~ATACH_DMA_WAIT; 1906 } 1907 while ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1908 /* Wait for at last 400ns for status bit to be valid */ 1909 DELAY(1); 1910 mvsata_atapi_intr(chp, xfer, 0); 1911 } 1912 } 1913 return; 1914 1915 timeout: 1916 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 1917 chp->ch_channel, xfer->c_drive, errstring); 1918 sc_xfer->error = XS_TIMEOUT; 1919 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1920 delay(10); /* some drives need a little delay here */ 1921 mvsata_atapi_reset(chp, xfer); 1922 return; 1923 1924 error: 1925 aprint_error_dev(atac->atac_dev, 1926 "channel %d drive %d: %s error (0x%x)\n", 1927 chp->ch_channel, xfer->c_drive, errstring, chp->ch_error); 1928 sc_xfer->error = XS_SHORTSENSE; 1929 sc_xfer->sense.atapi_sense = chp->ch_error; 1930 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1931 delay(10); /* some drives need a little delay here */ 1932 mvsata_atapi_reset(chp, xfer); 1933 return; 1934 } 1935 1936 static int 1937 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1938 { 1939 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1940 struct atac_softc *atac = chp->ch_atac; 1941 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1942 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1943 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1944 int len, phase, ire, error, retries=0, i; 1945 void *cmd; 1946 1947 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n", 1948 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1949 1950 /* Is it not a transfer, but a control operation? */ 1951 if (drvp->state < READY) { 1952 aprint_error_dev(atac->atac_dev, 1953 "channel %d drive %d: bad state %d\n", 1954 chp->ch_channel, xfer->c_drive, drvp->state); 1955 panic("mvsata_atapi_intr: bad state"); 1956 } 1957 /* 1958 * If we missed an interrupt in a PIO transfer, reset and restart. 1959 * Don't try to continue transfer, we may have missed cycles. 1960 */ 1961 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 1962 sc_xfer->error = XS_TIMEOUT; 1963 mvsata_atapi_reset(chp, xfer); 1964 return 1; 1965 } 1966 1967 /* Ack interrupt done in wdc_wait_for_unbusy */ 1968 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1969 if (wdc_wait_for_unbusy(chp, 1970 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) { 1971 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1972 return 0; /* IRQ was not for us */ 1973 aprint_error_dev(atac->atac_dev, 1974 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 1975 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 1976 if (xfer->c_flags & C_DMA) 1977 ata_dmaerr(drvp, 1978 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1979 sc_xfer->error = XS_TIMEOUT; 1980 mvsata_atapi_reset(chp, xfer); 1981 return 1; 1982 } 1983 1984 /* 1985 * If we missed an IRQ and were using DMA, flag it as a DMA error 1986 * and reset device. 1987 */ 1988 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 1989 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1990 sc_xfer->error = XS_RESET; 1991 mvsata_atapi_reset(chp, xfer); 1992 return (1); 1993 } 1994 /* 1995 * if the request sense command was aborted, report the short sense 1996 * previously recorded, else continue normal processing 1997 */ 1998 1999 again: 2000 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2001 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2002 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2003 phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ); 2004 DPRINTF(( 2005 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2006 xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire)); 2007 2008 switch (phase) { 2009 case PHASE_CMDOUT: 2010 cmd = sc_xfer->cmd; 2011 DPRINTF(("PHASE_CMDOUT\n")); 2012 /* Init the DMA channel if necessary */ 2013 if (xfer->c_flags & C_DMA) { 2014 error = mvsata_bdma_init(mvport, sc_xfer, 2015 (char *)xfer->c_databuf + xfer->c_skip); 2016 if (error) { 2017 if (error == EINVAL) { 2018 /* 2019 * We can't do DMA on this transfer 2020 * for some reason. Fall back to PIO. 2021 */ 2022 xfer->c_flags &= ~C_DMA; 2023 error = 0; 2024 } else { 2025 sc_xfer->error = XS_DRIVER_STUFFUP; 2026 break; 2027 } 2028 } 2029 } 2030 2031 /* send packet command */ 2032 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2033 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2034 2035 /* Start the DMA channel if necessary */ 2036 if (xfer->c_flags & C_DMA) { 2037 mvsata_bdma_start(mvport); 2038 chp->ch_flags |= ATACH_DMA_WAIT; 2039 } 2040 2041 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2042 chp->ch_flags |= ATACH_IRQ_WAIT; 2043 return 1; 2044 2045 case PHASE_DATAOUT: 2046 /* write data */ 2047 DPRINTF(("PHASE_DATAOUT\n")); 2048 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2049 (xfer->c_flags & C_DMA) != 0) { 2050 aprint_error_dev(atac->atac_dev, 2051 "channel %d drive %d: bad data phase DATAOUT\n", 2052 chp->ch_channel, xfer->c_drive); 2053 if (xfer->c_flags & C_DMA) 2054 ata_dmaerr(drvp, 2055 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2056 sc_xfer->error = XS_TIMEOUT; 2057 mvsata_atapi_reset(chp, xfer); 2058 return 1; 2059 } 2060 xfer->c_lenoff = len - xfer->c_bcount; 2061 if (xfer->c_bcount < len) { 2062 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2063 " warning: write only %d of %d requested bytes\n", 2064 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2065 len); 2066 len = xfer->c_bcount; 2067 } 2068 2069 wdc->dataout_pio(chp, drvp->drive_flags, 2070 (char *)xfer->c_databuf + xfer->c_skip, len); 2071 2072 for (i = xfer->c_lenoff; i > 0; i -= 2) 2073 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2074 2075 xfer->c_skip += len; 2076 xfer->c_bcount -= len; 2077 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2078 chp->ch_flags |= ATACH_IRQ_WAIT; 2079 return 1; 2080 2081 case PHASE_DATAIN: 2082 /* Read data */ 2083 DPRINTF(("PHASE_DATAIN\n")); 2084 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2085 (xfer->c_flags & C_DMA) != 0) { 2086 aprint_error_dev(atac->atac_dev, 2087 "channel %d drive %d: bad data phase DATAIN\n", 2088 chp->ch_channel, xfer->c_drive); 2089 if (xfer->c_flags & C_DMA) 2090 ata_dmaerr(drvp, 2091 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2092 sc_xfer->error = XS_TIMEOUT; 2093 mvsata_atapi_reset(chp, xfer); 2094 return 1; 2095 } 2096 xfer->c_lenoff = len - xfer->c_bcount; 2097 if (xfer->c_bcount < len) { 2098 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2099 " warning: reading only %d of %d bytes\n", 2100 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2101 len); 2102 len = xfer->c_bcount; 2103 } 2104 2105 wdc->datain_pio(chp, drvp->drive_flags, 2106 (char *)xfer->c_databuf + xfer->c_skip, len); 2107 2108 if (xfer->c_lenoff > 0) 2109 wdcbit_bucket(chp, len - xfer->c_bcount); 2110 2111 xfer->c_skip += len; 2112 xfer->c_bcount -= len; 2113 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2114 chp->ch_flags |= ATACH_IRQ_WAIT; 2115 return 1; 2116 2117 case PHASE_ABORTED: 2118 case PHASE_COMPLETED: 2119 DPRINTF(("PHASE_COMPLETED\n")); 2120 if (xfer->c_flags & C_DMA) 2121 xfer->c_bcount -= sc_xfer->datalen; 2122 sc_xfer->resid = xfer->c_bcount; 2123 mvsata_atapi_phase_complete(xfer); 2124 return 1; 2125 2126 default: 2127 if (++retries<500) { 2128 DELAY(100); 2129 chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 2130 chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 2131 goto again; 2132 } 2133 aprint_error_dev(atac->atac_dev, 2134 "channel %d drive %d: unknown phase 0x%x\n", 2135 chp->ch_channel, xfer->c_drive, phase); 2136 if (chp->ch_status & WDCS_ERR) { 2137 sc_xfer->error = XS_SHORTSENSE; 2138 sc_xfer->sense.atapi_sense = chp->ch_error; 2139 } else { 2140 if (xfer->c_flags & C_DMA) 2141 ata_dmaerr(drvp, 2142 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2143 sc_xfer->error = XS_RESET; 2144 mvsata_atapi_reset(chp, xfer); 2145 return (1); 2146 } 2147 } 2148 DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x " 2149 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense)); 2150 mvsata_atapi_done(chp, xfer); 2151 return 1; 2152 } 2153 2154 static void 2155 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2156 int reason) 2157 { 2158 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2159 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2160 2161 /* remove this command from xfer queue */ 2162 switch (reason) { 2163 case KILL_GONE: 2164 sc_xfer->error = XS_DRIVER_STUFFUP; 2165 break; 2166 2167 case KILL_RESET: 2168 sc_xfer->error = XS_RESET; 2169 break; 2170 2171 default: 2172 aprint_error_dev(MVSATA_DEV2(mvport), 2173 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2174 panic("mvsata_atapi_kill_xfer"); 2175 } 2176 ata_free_xfer(chp, xfer); 2177 scsipi_done(sc_xfer); 2178 } 2179 2180 static void 2181 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2182 { 2183 struct atac_softc *atac = chp->ch_atac; 2184 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2185 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2186 2187 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 2188 drvp->state = 0; 2189 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) { 2190 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2191 chp->ch_channel, xfer->c_drive); 2192 sc_xfer->error = XS_SELTIMEOUT; 2193 } 2194 mvsata_atapi_done(chp, xfer); 2195 return; 2196 } 2197 2198 static void 2199 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2200 { 2201 struct ata_channel *chp = xfer->c_chp; 2202 struct atac_softc *atac = chp->ch_atac; 2203 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2204 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2205 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2206 2207 /* wait for DSC if needed */ 2208 if (drvp->drive_flags & DRIVE_ATAPIST) { 2209 DPRINTFN(1, 2210 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2211 device_xname(atac->atac_dev), chp->ch_channel, 2212 xfer->c_drive, xfer->c_dscpoll)); 2213 if (cold) 2214 panic("mvsata_atapi_phase_complete: cold"); 2215 2216 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) == 2217 WDCWAIT_TOUT) { 2218 /* 10ms not enough, try again in 1 tick */ 2219 if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) { 2220 aprint_error_dev(atac->atac_dev, 2221 "channel %d: wait_for_dsc failed\n", 2222 chp->ch_channel); 2223 sc_xfer->error = XS_TIMEOUT; 2224 mvsata_atapi_reset(chp, xfer); 2225 return; 2226 } else 2227 callout_reset(&chp->ch_callout, 1, 2228 mvsata_atapi_polldsc, xfer); 2229 return; 2230 } 2231 } 2232 2233 /* 2234 * Some drive occasionally set WDCS_ERR with 2235 * "ATA illegal length indication" in the error 2236 * register. If we read some data the sense is valid 2237 * anyway, so don't report the error. 2238 */ 2239 if (chp->ch_status & WDCS_ERR && 2240 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2241 sc_xfer->resid == sc_xfer->datalen)) { 2242 /* save the short sense */ 2243 sc_xfer->error = XS_SHORTSENSE; 2244 sc_xfer->sense.atapi_sense = chp->ch_error; 2245 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2246 /* ask scsipi to send a REQUEST_SENSE */ 2247 sc_xfer->error = XS_BUSY; 2248 sc_xfer->status = SCSI_CHECK; 2249 } else 2250 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2251 ata_dmaerr(drvp, 2252 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2253 sc_xfer->error = XS_RESET; 2254 mvsata_atapi_reset(chp, xfer); 2255 return; 2256 } 2257 } 2258 if (xfer->c_bcount != 0) 2259 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:" 2260 " bcount value is %d after io\n", 2261 device_xname(atac->atac_dev), chp->ch_channel, 2262 xfer->c_drive, xfer->c_bcount)); 2263 #ifdef DIAGNOSTIC 2264 if (xfer->c_bcount < 0) 2265 aprint_error_dev(atac->atac_dev, 2266 "channel %d drive %d: mvsata_atapi_intr:" 2267 " warning: bcount value is %d after io\n", 2268 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2269 #endif 2270 2271 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:" 2272 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2273 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2274 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2275 mvsata_atapi_done(chp, xfer); 2276 } 2277 2278 static void 2279 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2280 { 2281 struct atac_softc *atac = chp->ch_atac; 2282 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2283 int drive = xfer->c_drive; 2284 2285 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2286 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2287 (u_int)xfer->c_flags)); 2288 callout_stop(&chp->ch_callout); 2289 /* mark controller inactive and free the command */ 2290 chp->ch_queue->active_xfer = NULL; 2291 ata_free_xfer(chp, xfer); 2292 2293 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 2294 sc_xfer->error = XS_DRIVER_STUFFUP; 2295 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 2296 wakeup(&chp->ch_queue->active_xfer); 2297 } 2298 2299 DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2300 device_xname(atac->atac_dev), chp->ch_channel)); 2301 scsipi_done(sc_xfer); 2302 DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2303 device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags)); 2304 atastart(chp); 2305 } 2306 2307 static void 2308 mvsata_atapi_polldsc(void *arg) 2309 { 2310 2311 mvsata_atapi_phase_complete(arg); 2312 } 2313 #endif /* NATAPIBUS > 0 */ 2314 2315 2316 /* 2317 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2318 * if supported queuing command by atabus? The race condition will not happen 2319 * if this is called only to the thread of atabus. 2320 */ 2321 static int 2322 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio, 2323 void *databuf) 2324 { 2325 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2326 struct ata_channel *chp = &mvport->port_ata_channel; 2327 struct eprd *eprd; 2328 bus_addr_t crqb_base_addr; 2329 bus_dmamap_t data_dmamap; 2330 uint32_t reg; 2331 int quetag, erqqip, erqqop, next, rv, i; 2332 2333 DPRINTFN(2, ("%s:%d:%d: mvsata_edma_enqueue:" 2334 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2335 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2336 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2337 2338 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2339 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2340 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2341 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2342 next = erqqip; 2343 MVSATA_EDMAQ_INC(next); 2344 if (next == erqqop) 2345 /* queue full */ 2346 return EBUSY; 2347 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2348 /* tag nothing */ 2349 return EBUSY; 2350 DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag)); 2351 2352 rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes, 2353 ata_bio->flags); 2354 if (rv != 0) 2355 return rv; 2356 2357 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2358 KASSERT(chp->ch_queue->active_xfer != NULL); 2359 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2360 2361 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2362 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2363 eprd = mvport->port_reqtbl[quetag].eprd; 2364 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2365 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2366 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2367 2368 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2369 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2370 eprd->eot = htole16(0); 2371 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2372 eprd++; 2373 } 2374 (eprd - 1)->eot |= htole16(EPRD_EOT); 2375 #ifdef MVSATA_DEBUG 2376 if (mvsata_debug >= 3) 2377 mvsata_print_eprd(mvport, quetag); 2378 #endif 2379 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2380 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2381 BUS_DMASYNC_PREWRITE); 2382 2383 /* setup EDMA Command Request Block (CRQB) Data */ 2384 sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio); 2385 #ifdef MVSATA_DEBUG 2386 if (mvsata_debug >= 3) 2387 mvsata_print_crqb(mvport, erqqip); 2388 #endif 2389 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2390 erqqip * sizeof(union mvsata_crqb), 2391 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2392 2393 MVSATA_EDMAQ_INC(erqqip); 2394 2395 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2396 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2397 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2398 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2399 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2400 2401 return 0; 2402 } 2403 2404 static int 2405 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2406 { 2407 struct ata_channel *chp = &mvport->port_ata_channel; 2408 struct crpb *crpb; 2409 struct ata_bio *ata_bio; 2410 struct ata_xfer *xfer; 2411 uint32_t reg; 2412 int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2413 2414 /* First, Sync for Request Queue buffer */ 2415 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2416 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2417 if (mvport->port_prev_erqqop != erqqop) { 2418 const int s = sizeof(union mvsata_crqb); 2419 2420 if (mvport->port_prev_erqqop < erqqop) 2421 n = erqqop - mvport->port_prev_erqqop; 2422 else { 2423 if (erqqop > 0) 2424 bus_dmamap_sync(mvport->port_dmat, 2425 mvport->port_crqb_dmamap, 0, erqqop * s, 2426 BUS_DMASYNC_POSTWRITE); 2427 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2428 } 2429 if (n > 0) 2430 bus_dmamap_sync(mvport->port_dmat, 2431 mvport->port_crqb_dmamap, 2432 mvport->port_prev_erqqop * s, n * s, 2433 BUS_DMASYNC_POSTWRITE); 2434 mvport->port_prev_erqqop = erqqop; 2435 } 2436 2437 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2438 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2439 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2440 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2441 2442 DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2443 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2444 mvport->port, erpqip, erpqop)); 2445 2446 if (erpqop == erpqip) 2447 return 0; 2448 2449 if (erpqop < erpqip) 2450 n = erpqip - erpqop; 2451 else { 2452 if (erpqip > 0) 2453 bus_dmamap_sync(mvport->port_dmat, 2454 mvport->port_crpb_dmamap, 2455 0, erpqip * sizeof(struct crpb), 2456 BUS_DMASYNC_POSTREAD); 2457 n = MVSATA_EDMAQ_LEN - erpqop; 2458 } 2459 if (n > 0) 2460 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2461 erpqop * sizeof(struct crpb), 2462 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2463 2464 prev_erpqop = erpqop; 2465 while (erpqop != erpqip) { 2466 #ifdef MVSATA_DEBUG 2467 if (mvsata_debug >= 3) 2468 mvsata_print_crpb(mvport, erpqop); 2469 #endif 2470 crpb = mvport->port_crpb + erpqop; 2471 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2472 KASSERT(chp->ch_queue->active_xfer != NULL); 2473 xfer = chp->ch_queue->active_xfer; 2474 KASSERT(xfer == mvport->port_reqtbl[quetag].xfer); 2475 #ifdef DIAGNOSTIC 2476 if (xfer == NULL) 2477 panic("unknown response received: %s:%d:%d: tag 0x%x\n", 2478 device_xname(MVSATA_DEV2(mvport)), 2479 mvport->port_hc->hc, mvport->port, quetag); 2480 #endif 2481 2482 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2483 mvport->port_reqtbl[quetag].eprd_offset, 2484 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2485 2486 chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2487 chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2488 ata_bio = xfer->c_cmd; 2489 ata_bio->error = NOERROR; 2490 ata_bio->r_error = 0; 2491 if (chp->ch_status & WDCS_ERR) 2492 ata_bio->error = ERROR; 2493 if (chp->ch_status & WDCS_BSY) 2494 ata_bio->error = TIMEOUT; 2495 if (chp->ch_error) 2496 ata_bio->error = ERR_DMA; 2497 2498 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2499 mvport->port_reqtbl[quetag].xfer = NULL; 2500 mvsata_quetag_put(mvport, quetag); 2501 MVSATA_EDMAQ_INC(erpqop); 2502 2503 #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */ 2504 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2505 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2506 if (erpqop == erqqip) 2507 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2508 #endif 2509 mvsata_bio_intr(chp, xfer, 1); 2510 if (xfer1 == NULL) 2511 handled++; 2512 else if (xfer == xfer1) { 2513 handled = 1; 2514 break; 2515 } 2516 } 2517 if (prev_erpqop < erpqop) 2518 n = erpqop - prev_erpqop; 2519 else { 2520 if (erpqop > 0) 2521 bus_dmamap_sync(mvport->port_dmat, 2522 mvport->port_crpb_dmamap, 0, 2523 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2524 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2525 } 2526 if (n > 0) 2527 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2528 prev_erpqop * sizeof(struct crpb), 2529 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2530 2531 reg &= ~EDMA_RESQP_ERPQP_MASK; 2532 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2533 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2534 2535 #if 0 /* already cleared ago? */ 2536 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2537 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2538 if (erpqop == erqqip) 2539 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2540 #endif 2541 2542 return handled; 2543 } 2544 2545 static int 2546 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2547 { 2548 struct ata_bio *ata_bio = xfer->c_cmd; 2549 int xtime; 2550 2551 for (xtime = 0; xtime < timeout / 10; xtime++) { 2552 if (mvsata_edma_handle(mvport, xfer)) 2553 return 0; 2554 if (ata_bio->flags & ATA_NOSLEEP) 2555 delay(10000); 2556 else 2557 tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10)); 2558 } 2559 2560 DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer)); 2561 mvsata_edma_rqq_remove(mvport, xfer); 2562 xfer->c_flags |= C_TIMEOU; 2563 return 1; 2564 } 2565 2566 static void 2567 mvsata_edma_timeout(void *arg) 2568 { 2569 struct ata_xfer *xfer = (struct ata_xfer *)arg; 2570 struct ata_channel *chp = xfer->c_chp; 2571 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2572 int s; 2573 2574 s = splbio(); 2575 DPRINTF(("mvsata_edma_timeout: %p\n", xfer)); 2576 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 2577 mvsata_edma_rqq_remove(mvport, xfer); 2578 xfer->c_flags |= C_TIMEOU; 2579 mvsata_bio_intr(chp, xfer, 1); 2580 } 2581 splx(s); 2582 } 2583 2584 static void 2585 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2586 { 2587 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2588 struct ata_bio *ata_bio; 2589 bus_addr_t crqb_base_addr; 2590 int erqqip, i; 2591 2592 /* First, hardware reset, stop EDMA */ 2593 mvsata_hreset_port(mvport); 2594 2595 /* cleanup completed EDMA safely */ 2596 mvsata_edma_handle(mvport, NULL); 2597 2598 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2599 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2600 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2601 if (mvport->port_reqtbl[i].xfer == NULL) 2602 continue; 2603 2604 ata_bio = mvport->port_reqtbl[i].xfer->c_cmd; 2605 if (mvport->port_reqtbl[i].xfer == xfer) { 2606 /* remove xfer from EDMA request queue */ 2607 bus_dmamap_sync(mvport->port_dmat, 2608 mvport->port_eprd_dmamap, 2609 mvport->port_reqtbl[i].eprd_offset, 2610 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2611 mvsata_dma_bufunload(mvport, i, ata_bio->flags); 2612 mvport->port_reqtbl[i].xfer = NULL; 2613 mvsata_quetag_put(mvport, i); 2614 continue; 2615 } 2616 2617 sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio); 2618 erqqip++; 2619 } 2620 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2621 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2622 BUS_DMASYNC_POSTWRITE); 2623 2624 mvsata_edma_config(mvport, mvport->port_edmamode); 2625 mvsata_edma_reset_qptr(mvport); 2626 mvsata_edma_enable(mvport); 2627 2628 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2629 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2630 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2631 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2632 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2633 } 2634 2635 #if NATAPIBUS > 0 2636 static int 2637 mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer, 2638 void *databuf) 2639 { 2640 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2641 struct eprd *eprd; 2642 bus_dmamap_t data_dmamap; 2643 bus_addr_t eprd_addr; 2644 int quetag, rv; 2645 2646 DPRINTFN(2, 2647 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2648 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2649 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2650 2651 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2652 /* tag nothing */ 2653 return EBUSY; 2654 DPRINTFN(2, (" quetag=%d\n", quetag)); 2655 2656 rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen, 2657 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2658 if (rv != 0) 2659 return rv; 2660 2661 KASSERT(chp->ch_queue->active_xfer != NULL); 2662 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2663 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2664 2665 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2666 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2667 eprd = mvport->port_reqtbl[quetag].eprd; 2668 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2669 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2670 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2671 2672 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2673 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2674 eprd->eot = htole16(0); 2675 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2676 eprd++; 2677 } 2678 (eprd - 1)->eot |= htole16(EPRD_EOT); 2679 #ifdef MVSATA_DEBUG 2680 if (mvsata_debug >= 3) 2681 mvsata_print_eprd(mvport, quetag); 2682 #endif 2683 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2684 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2685 BUS_DMASYNC_PREWRITE); 2686 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2687 mvport->port_reqtbl[quetag].eprd_offset; 2688 2689 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2690 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2691 2692 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2693 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2694 else 2695 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2696 2697 return 0; 2698 } 2699 2700 static void 2701 mvsata_bdma_start(struct mvsata_port *mvport) 2702 { 2703 2704 #ifdef MVSATA_DEBUG 2705 if (mvsata_debug >= 3) 2706 mvsata_print_eprd(mvport, 0); 2707 #endif 2708 2709 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2710 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2711 } 2712 #endif 2713 #endif 2714 2715 2716 static int 2717 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2718 { 2719 struct mvsata_softc *sc = mvhc->hc_sc; 2720 struct mvsata_port *mvport; 2721 struct ata_channel *chp; 2722 int channel, rv, i; 2723 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2724 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2725 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2726 2727 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2728 M_ZERO | M_NOWAIT); 2729 if (mvport == NULL) { 2730 aprint_error("%s:%d: can't allocate memory for port %d\n", 2731 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2732 return ENOMEM; 2733 } 2734 2735 mvport->port = port; 2736 mvport->port_hc = mvhc; 2737 mvport->port_edmamode = nodma; 2738 2739 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2740 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 2741 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 2742 if (rv != 0) { 2743 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 2744 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2745 goto fail0; 2746 } 2747 mvport->port_iot = mvhc->hc_iot; 2748 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 2749 &mvport->port_sata_sstatus); 2750 if (rv != 0) { 2751 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 2752 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2753 goto fail0; 2754 } 2755 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 2756 &mvport->port_sata_serror); 2757 if (rv != 0) { 2758 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 2759 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2760 goto fail0; 2761 } 2762 if (sc->sc_rev == gen1) 2763 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2764 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 2765 else 2766 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2767 SATA_SC, 4, &mvport->port_sata_scontrol); 2768 if (rv != 0) { 2769 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 2770 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2771 goto fail0; 2772 } 2773 mvport->port_dmat = sc->sc_dmat; 2774 #ifndef MVSATA_WITHOUTDMA 2775 mvsata_quetag_init(mvport); 2776 #endif 2777 mvhc->hc_ports[port] = mvport; 2778 2779 channel = mvhc->hc * sc->sc_port + port; 2780 chp = &mvport->port_ata_channel; 2781 chp->ch_channel = channel; 2782 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 2783 chp->ch_ndrive = 1; /* SATA is always 1 drive */ 2784 chp->ch_queue = &mvport->port_ata_queue; 2785 sc->sc_ata_channels[channel] = chp; 2786 2787 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 2788 if (rv != 0) 2789 goto fail0; 2790 2791 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 2792 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 2793 if (rv != 0) { 2794 aprint_error( 2795 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 2796 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2797 goto fail0; 2798 } 2799 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 2800 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 2801 if (rv != 0) { 2802 aprint_error( 2803 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 2804 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2805 goto fail1; 2806 } 2807 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 2808 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 2809 if (rv != 0) { 2810 aprint_error( 2811 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 2812 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2813 goto fail2; 2814 } 2815 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 2816 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 2817 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 2818 &mvport->port_reqtbl[i].data_dmamap); 2819 if (rv != 0) { 2820 aprint_error("%s:%d:%d:" 2821 " EDMA data map(%d) create failed: error=%d\n", 2822 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 2823 rv); 2824 goto fail3; 2825 } 2826 } 2827 2828 return 0; 2829 2830 fail3: 2831 for (i--; i >= 0; i--) 2832 bus_dmamap_destroy(mvport->port_dmat, 2833 mvport->port_reqtbl[i].data_dmamap); 2834 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 2835 fail2: 2836 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 2837 fail1: 2838 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 2839 fail0: 2840 return rv; 2841 } 2842 2843 static int 2844 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 2845 { 2846 int hc, port, rv, i; 2847 2848 hc = mvport->port_hc->hc; 2849 port = mvport->port; 2850 2851 /* Create subregion for Shadow Registers Map */ 2852 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2853 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 2854 if (rv != 0) { 2855 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 2856 device_xname(MVSATA_DEV2(mvport)), hc, port); 2857 return rv; 2858 } 2859 wdr->cmd_iot = mvport->port_iot; 2860 2861 /* Once create subregion for each command registers */ 2862 for (i = 0; i < WDC_NREG; i++) { 2863 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2864 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 2865 if (rv != 0) { 2866 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2867 device_xname(MVSATA_DEV2(mvport)), hc, port); 2868 return rv; 2869 } 2870 } 2871 /* Create subregion for Alternate Status register */ 2872 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2873 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 2874 if (rv != 0) { 2875 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2876 device_xname(MVSATA_DEV2(mvport)), hc, port); 2877 return rv; 2878 } 2879 wdr->ctl_iot = mvport->port_iot; 2880 2881 wdc_init_shadow_regs(&mvport->port_ata_channel); 2882 2883 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2884 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 2885 if (rv != 0) { 2886 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 2887 device_xname(MVSATA_DEV2(mvport)), hc, port); 2888 return rv; 2889 } 2890 wdr->sata_iot = mvport->port_iot; 2891 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2892 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 2893 if (rv != 0) { 2894 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 2895 device_xname(MVSATA_DEV2(mvport)), hc, port); 2896 return rv; 2897 } 2898 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2899 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 2900 if (rv != 0) { 2901 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 2902 device_xname(MVSATA_DEV2(mvport)), hc, port); 2903 return rv; 2904 } 2905 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2906 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 2907 if (rv != 0) { 2908 aprint_error("%s:%d:%d: couldn't subregion SError\n", 2909 device_xname(MVSATA_DEV2(mvport)), hc, port); 2910 return rv; 2911 } 2912 2913 return 0; 2914 } 2915 2916 2917 #ifndef MVSATA_WITHOUTDMA 2918 /* 2919 * There are functions to determine Host Queue Tag. 2920 * XXXX: We hope to rotate Tag to facilitate debugging. 2921 */ 2922 2923 static inline void 2924 mvsata_quetag_init(struct mvsata_port *mvport) 2925 { 2926 2927 mvport->port_quetagidx = 0; 2928 } 2929 2930 static inline int 2931 mvsata_quetag_get(struct mvsata_port *mvport) 2932 { 2933 int begin = mvport->port_quetagidx; 2934 2935 do { 2936 if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) { 2937 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2938 return mvport->port_quetagidx; 2939 } 2940 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2941 } while (mvport->port_quetagidx != begin); 2942 2943 return -1; 2944 } 2945 2946 static inline void 2947 mvsata_quetag_put(struct mvsata_port *mvport, int quetag) 2948 { 2949 2950 /* nothing */ 2951 } 2952 2953 static void * 2954 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 2955 bus_dmamap_t *dmamap, size_t size, int write) 2956 { 2957 bus_dma_segment_t seg; 2958 int nseg, rv; 2959 void *kva; 2960 2961 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 2962 BUS_DMA_NOWAIT); 2963 if (rv != 0) { 2964 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 2965 device_xname(MVSATA_DEV2(mvport)), 2966 mvport->port_hc->hc, mvport->port, rv); 2967 goto fail; 2968 } 2969 2970 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 2971 if (rv != 0) { 2972 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 2973 device_xname(MVSATA_DEV2(mvport)), 2974 mvport->port_hc->hc, mvport->port, rv); 2975 goto free; 2976 } 2977 2978 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 2979 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 2980 if (rv != 0) { 2981 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 2982 device_xname(MVSATA_DEV2(mvport)), 2983 mvport->port_hc->hc, mvport->port, rv); 2984 goto unmap; 2985 } 2986 2987 if (!write) 2988 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 2989 2990 return kva; 2991 2992 unmap: 2993 bus_dmamem_unmap(dmat, kva, size); 2994 free: 2995 bus_dmamem_free(dmat, &seg, nseg); 2996 fail: 2997 return NULL; 2998 } 2999 3000 /* ARGSUSED */ 3001 static void 3002 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3003 bus_dmamap_t dmamap, void *kva) 3004 { 3005 3006 bus_dmamap_unload(dmat, dmamap); 3007 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3008 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3009 } 3010 3011 static int 3012 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3013 size_t datalen, int flags) 3014 { 3015 int rv, lop, sop; 3016 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3017 3018 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3019 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3020 3021 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3022 NULL, BUS_DMA_NOWAIT | lop); 3023 if (rv) { 3024 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3025 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3026 mvport->port, rv); 3027 return rv; 3028 } 3029 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3030 data_dmamap->dm_mapsize, sop); 3031 3032 return 0; 3033 } 3034 3035 static inline void 3036 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3037 { 3038 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3039 3040 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3041 data_dmamap->dm_mapsize, 3042 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3043 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3044 } 3045 #endif 3046 3047 static void 3048 mvsata_hreset_port(struct mvsata_port *mvport) 3049 { 3050 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3051 3052 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3053 3054 delay(25); /* allow reset propagation */ 3055 3056 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3057 3058 mvport->_fix_phy_param._fix_phy(mvport); 3059 3060 if (sc->sc_gen == gen1) 3061 delay(1000); 3062 } 3063 3064 static void 3065 mvsata_reset_port(struct mvsata_port *mvport) 3066 { 3067 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3068 3069 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3070 3071 mvsata_hreset_port(mvport); 3072 3073 if (device_is_a(parent, "pci")) 3074 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3075 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3076 else /* SoC */ 3077 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3078 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3079 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3080 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3081 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3082 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3083 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3084 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3085 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3086 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3087 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3088 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3089 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3090 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3091 3092 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3093 } 3094 3095 static void 3096 mvsata_reset_hc(struct mvsata_hc *mvhc) 3097 { 3098 #if 0 3099 uint32_t val; 3100 #endif 3101 3102 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3103 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3104 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3105 3106 #if 0 /* XXXX needs? */ 3107 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3108 3109 /* 3110 * Keep the SS during power on and the reference clock bits (reset 3111 * sample) 3112 */ 3113 val = MVSATA_HC_READ_4(mvhc, 0x020); 3114 val &= 0x1c1c1c1c; 3115 val |= 0x03030303; 3116 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3117 #endif 3118 } 3119 3120 #ifndef MVSATA_WITHOUTDMA 3121 static void 3122 mvsata_softreset(struct mvsata_port *mvport, int waitok) 3123 { 3124 uint32_t stat; 3125 int i; 3126 3127 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS); 3128 delay(10); 3129 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS); 3130 delay(2000); 3131 3132 if (waitok) { 3133 /* wait maximum 31sec */ 3134 for (i = 31000; i > 0; i--) { 3135 stat = MVSATA_WDC_READ_1(mvport, SRB_CS); 3136 if (!(stat & WDCS_BSY)) 3137 break; 3138 delay(1000); 3139 } 3140 if (i == 0) 3141 aprint_error("%s:%d:%d: soft reset failed\n", 3142 device_xname(MVSATA_DEV2(mvport)), 3143 mvport->port_hc->hc, mvport->port); 3144 } 3145 } 3146 3147 static void 3148 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3149 { 3150 const bus_addr_t crpb_addr = 3151 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3152 const uint32_t crpb_addr_mask = 3153 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3154 3155 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3156 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3157 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3158 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3159 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3160 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3161 } 3162 3163 static inline void 3164 mvsata_edma_enable(struct mvsata_port *mvport) 3165 { 3166 3167 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3168 } 3169 3170 static int 3171 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok) 3172 { 3173 uint32_t status, command; 3174 int ms; 3175 3176 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3177 for (ms = 0; ms < timeout; ms++) { 3178 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3179 if (status & EDMA_S_EDMAIDLE) 3180 break; 3181 if (waitok) 3182 tsleep(&waitok, PRIBIO, "mvsata_edma1", 3183 mstohz(1)); 3184 else 3185 delay(1000); 3186 } 3187 if (ms == timeout) 3188 return EBUSY; 3189 3190 /* The diable bit (eDsEDMA) is self negated. */ 3191 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3192 3193 for ( ; ms < timeout; ms++) { 3194 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3195 if (!(command & EDMA_CMD_EENEDMA)) 3196 break; 3197 if (waitok) 3198 tsleep(&waitok, PRIBIO, "mvsata_edma2", 3199 mstohz(1)); 3200 else 3201 delay(1000); 3202 } 3203 if (ms == timeout) { 3204 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3205 device_xname(MVSATA_DEV2(mvport)), 3206 mvport->port_hc->hc, mvport->port); 3207 return EBUSY; 3208 } 3209 } 3210 return 0; 3211 } 3212 3213 /* 3214 * Set EDMA registers according to mode. 3215 * ex. NCQ/TCQ(queued)/non queued. 3216 */ 3217 static void 3218 mvsata_edma_config(struct mvsata_port *mvport, int mode) 3219 { 3220 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3221 uint32_t reg; 3222 3223 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3224 reg |= EDMA_CFG_RESERVED; 3225 3226 if (mode == ncq) { 3227 if (sc->sc_gen == gen1) { 3228 aprint_error_dev(MVSATA_DEV2(mvport), 3229 "GenI not support NCQ\n"); 3230 return; 3231 } else if (sc->sc_gen == gen2) 3232 reg |= EDMA_CFG_EDEVERR; 3233 reg |= EDMA_CFG_ESATANATVCMDQUE; 3234 } else if (mode == queued) { 3235 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3236 reg |= EDMA_CFG_EQUE; 3237 } else 3238 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3239 3240 if (sc->sc_gen == gen1) 3241 reg |= EDMA_CFG_ERDBSZ; 3242 else if (sc->sc_gen == gen2) 3243 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3244 else if (sc->sc_gen == gen2e) { 3245 device_t parent = device_parent(MVSATA_DEV(sc)); 3246 3247 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3248 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3249 3250 if (device_is_a(parent, "pci")) 3251 reg |= ( 3252 #if NATAPIBUS > 0 3253 EDMA_CFG_EEARLYCOMPLETIONEN | 3254 #endif 3255 EDMA_CFG_ECUTTHROUGHEN | 3256 EDMA_CFG_EWRBUFFERLEN | 3257 EDMA_CFG_ERDBSZEXT); 3258 } 3259 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3260 3261 reg = ( 3262 EDMA_IE_EIORDYERR | 3263 EDMA_IE_ETRANSINT | 3264 EDMA_IE_EDEVCON | 3265 EDMA_IE_EDEVDIS); 3266 if (sc->sc_gen != gen1) 3267 reg |= ( 3268 EDMA_IE_TRANSPROTERR | 3269 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3270 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3271 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3272 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3273 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3274 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3275 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3276 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3277 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3278 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3279 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3280 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3281 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3282 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3283 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3284 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3285 EDMA_IE_ESELFDIS); 3286 3287 if (mode == ncq) 3288 reg |= EDMA_IE_EDEVERR; 3289 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3290 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3291 reg &= ~EDMA_IE_EDEVERR; 3292 if (mode != ncq) 3293 reg |= EDMA_IE_EDEVERR; 3294 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3295 if (sc->sc_gen == gen2e) { 3296 /* 3297 * Clear FISWait4HostRdyEn[0] and [2]. 3298 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3299 * [2]: SDB FIS is received with <ERR> bit set to 1. 3300 */ 3301 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3302 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3303 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3304 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3305 } 3306 3307 mvport->port_edmamode = mode; 3308 } 3309 3310 3311 /* 3312 * Generation dependent functions 3313 */ 3314 3315 static void 3316 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag, 3317 struct ata_bio *ata_bio) 3318 { 3319 struct crqb *crqb; 3320 bus_addr_t eprd_addr; 3321 daddr_t blkno; 3322 uint32_t rw; 3323 uint8_t cmd, head; 3324 int i; 3325 const int drive = 3326 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3327 3328 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3329 mvport->port_reqtbl[quetag].eprd_offset; 3330 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3331 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3332 head = WDSD_LBA; 3333 blkno = ata_bio->blkno; 3334 if (ata_bio->flags & ATA_LBA48) 3335 cmd = atacmd_to48(cmd); 3336 else { 3337 head |= ((ata_bio->blkno >> 24) & 0xf); 3338 blkno &= 0xffffff; 3339 } 3340 crqb = &mvport->port_crqb->crqb + erqqip; 3341 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3342 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3343 crqb->ctrlflg = 3344 htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive)); 3345 i = 0; 3346 if (mvport->port_edmamode == dma) { 3347 if (ata_bio->flags & ATA_LBA48) 3348 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3349 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3350 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3351 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3352 } else { /* ncq/queued */ 3353 3354 /* 3355 * XXXX: Oops, ata command is not correct. And, atabus layer 3356 * has not been supported yet now. 3357 * Queued DMA read/write. 3358 * read/write FPDMAQueued. 3359 */ 3360 3361 if (ata_bio->flags & ATA_LBA48) 3362 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3363 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3364 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3365 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3366 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3367 CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3)); 3368 } 3369 if (ata_bio->flags & ATA_LBA48) { 3370 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3371 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3372 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3373 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3374 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3375 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3376 } 3377 crqb->atacommand[i++] = 3378 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3379 crqb->atacommand[i++] = 3380 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3381 crqb->atacommand[i++] = 3382 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3383 crqb->atacommand[i++] = 3384 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3385 crqb->atacommand[i++] = htole16( 3386 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3387 CRQB_ATACOMMAND_LAST); 3388 } 3389 #endif 3390 3391 static uint32_t 3392 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3393 { 3394 struct mvsata_hc *hc = mvport->port_hc; 3395 uint32_t reg; 3396 3397 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3398 /* 3399 * [12:11] : pre 3400 * [7:5] : amps 3401 */ 3402 return reg & 0x000018e0; 3403 } 3404 3405 static void 3406 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3407 { 3408 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3409 struct mvsata_hc *mvhc = mvport->port_hc; 3410 uint32_t reg; 3411 int port = mvport->port, fix_apm_sq = 0; 3412 3413 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3414 if (sc->sc_rev == 0x01) 3415 fix_apm_sq = 1; 3416 } else { 3417 if (sc->sc_rev == 0x00) 3418 fix_apm_sq = 1; 3419 } 3420 3421 if (fix_apm_sq) { 3422 /* 3423 * Disable auto-power management 3424 * 88SX50xx FEr SATA#12 3425 */ 3426 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3427 reg |= (1 << 19); 3428 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3429 3430 /* 3431 * Fix squelch threshold 3432 * 88SX50xx FEr SATA#9 3433 */ 3434 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3435 reg &= ~0x3; 3436 reg |= 0x1; 3437 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3438 } 3439 3440 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3441 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3442 reg &= ~0x000018e0; /* pre and amps mask */ 3443 reg |= mvport->_fix_phy_param.pre_amps; 3444 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3445 } 3446 3447 static void 3448 mvsata_devconn_gen1(struct mvsata_port *mvport) 3449 { 3450 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3451 3452 /* Fix for 88SX50xx FEr SATA#2 */ 3453 mvport->_fix_phy_param._fix_phy(mvport); 3454 3455 /* If disk is connected, then enable the activity LED */ 3456 if (sc->sc_rev == 0x03) { 3457 /* XXXXX */ 3458 } 3459 } 3460 3461 static uint32_t 3462 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3463 { 3464 uint32_t reg; 3465 3466 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3467 /* 3468 * [10:8] : amps 3469 * [7:5] : pre 3470 */ 3471 return reg & 0x000007e0; 3472 } 3473 3474 static void 3475 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3476 { 3477 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3478 uint32_t reg; 3479 3480 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3481 sc->sc_gen == gen2e) { 3482 /* 3483 * Fix for 3484 * 88SX60X1 FEr SATA #23 3485 * 88SX6042/88SX7042 FEr SATA #23 3486 * 88F5182 FEr #SATA-S13 3487 * 88F5082 FEr #SATA-S13 3488 */ 3489 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3490 reg &= ~(1 << 16); 3491 reg |= (1 << 31); 3492 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3493 3494 delay(200); 3495 3496 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3497 reg &= ~((1 << 16) | (1 << 31)); 3498 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3499 3500 delay(200); 3501 } 3502 3503 /* Fix values in PHY Mode 3 Register.*/ 3504 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3505 reg &= ~0x7F900000; 3506 reg |= 0x2A800000; 3507 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3508 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3509 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3510 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3511 reg &= ~0x0000001c; 3512 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3513 3514 /* 3515 * Fix values in PHY Mode 4 Register. 3516 * 88SX60x1 FEr SATA#10 3517 * 88F5182 GL #SATA-S10 3518 * 88F5082 GL #SATA-S10 3519 */ 3520 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3521 sc->sc_gen == gen2e) { 3522 uint32_t tmp = 0; 3523 3524 /* 88SX60x1 FEr SATA #13 */ 3525 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3526 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3527 3528 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3529 reg |= (1 << 0); 3530 reg &= ~(1 << 1); 3531 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3532 if (sc->sc_gen == gen2e) { 3533 reg &= ~0x5de3fffc; 3534 reg |= (1 << 2); 3535 } 3536 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3537 3538 /* 88SX60x1 FEr SATA #13 */ 3539 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3540 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3541 } 3542 3543 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3544 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3545 reg &= ~0x000007e0; /* pre and amps mask */ 3546 reg |= mvport->_fix_phy_param.pre_amps; 3547 reg &= ~(1 << 16); 3548 if (sc->sc_gen == gen2e) { 3549 /* 3550 * according to mvSata 3.6.1, some IIE values are fixed. 3551 * some reserved fields must be written with fixed values. 3552 */ 3553 reg &= ~0xC30FF01F; 3554 reg |= 0x0000900F; 3555 } 3556 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3557 } 3558 3559 #ifndef MVSATA_WITHOUTDMA 3560 static void 3561 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag, 3562 struct ata_bio *ata_bio) 3563 { 3564 struct crqb_gen2e *crqb; 3565 bus_addr_t eprd_addr; 3566 daddr_t blkno; 3567 uint32_t ctrlflg, rw; 3568 uint8_t cmd, head; 3569 const int drive = 3570 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3571 3572 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3573 mvport->port_reqtbl[quetag].eprd_offset; 3574 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3575 ctrlflg = (rw | CRQB_CDEVICEQUETAG(quetag) | CRQB_CPMPORT(drive) | 3576 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag)); 3577 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3578 head = WDSD_LBA; 3579 blkno = ata_bio->blkno; 3580 if (ata_bio->flags & ATA_LBA48) 3581 cmd = atacmd_to48(cmd); 3582 else { 3583 head |= ((ata_bio->blkno >> 24) & 0xf); 3584 blkno &= 0xffffff; 3585 } 3586 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3587 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3588 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3589 crqb->ctrlflg = htole32(ctrlflg); 3590 if (mvport->port_edmamode == dma) { 3591 crqb->atacommand[0] = htole32(cmd << 16); 3592 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3593 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff)); 3594 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3595 } else { /* ncq/queued */ 3596 3597 /* 3598 * XXXX: Oops, ata command is not correct. And, atabus layer 3599 * has not been supported yet now. 3600 * Queued DMA read/write. 3601 * read/write FPDMAQueued. 3602 */ 3603 3604 crqb->atacommand[0] = htole32( 3605 (cmd << 16) | ((ata_bio->nblks & 0xff) << 24)); 3606 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3607 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) | 3608 ((ata_bio->nblks >> 8) & 0xff)); 3609 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3610 crqb->atacommand[3] = htole32(quetag << 3); 3611 } 3612 } 3613 3614 3615 #ifdef MVSATA_DEBUG 3616 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3617 do { \ 3618 int _i; \ 3619 u_char *_p = (p); \ 3620 \ 3621 printf(#type "(%d)", (n)); \ 3622 for (_i = 0; _i < (size); _i++, _p++) { \ 3623 if (_i % 16 == 0) \ 3624 printf("\n "); \ 3625 printf(" %02x", *_p); \ 3626 } \ 3627 printf("\n"); \ 3628 } while (0 /* CONSTCOND */) 3629 3630 static void 3631 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3632 { 3633 3634 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3635 n, (u_char *)(mvport->port_crqb + n)); 3636 } 3637 3638 static void 3639 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3640 { 3641 3642 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3643 n, (u_char *)(mvport->port_crpb + n)); 3644 } 3645 3646 static void 3647 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3648 { 3649 struct eprd *eprd; 3650 int i = 0; 3651 3652 eprd = mvport->port_reqtbl[n].eprd; 3653 while (1 /*CONSTCOND*/) { 3654 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3655 i, (u_char *)eprd); 3656 if (eprd->eot & EPRD_EOT) 3657 break; 3658 eprd++; 3659 i++; 3660 } 3661 } 3662 #endif 3663 #endif 3664
Indexes created Mon Sep 22 13:09:51 GMT 2025