mvsata.c revision 1.15
1 /* $NetBSD: mvsata.c,v 1.15 2012/01/24 20:04:08 jakllsch Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.15 2012/01/24 20:04:08 jakllsch Exp $"); 30 31 #include "opt_mvsata.h" 32 33 /* ATAPI implementation not finished. Also don't work shadow registers? */ 34 //#include "atapibus.h" 35 36 #include <sys/param.h> 37 #if NATAPIBUS > 0 38 #include <sys/buf.h> 39 #endif 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/disklabel.h> 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 49 #include <machine/vmparam.h> 50 51 #include <dev/ata/atareg.h> 52 #include <dev/ata/atavar.h> 53 #include <dev/ic/wdcvar.h> 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 57 #if NATAPIBUS > 0 58 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 59 #endif 60 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ic/mvsatareg.h> 64 #include <dev/ic/mvsatavar.h> 65 66 67 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 68 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 69 70 #define MVSATA_HC_READ_4(hc, reg) \ 71 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 72 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 73 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 74 #define MVSATA_EDMA_READ_4(mvport, reg) \ 75 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 76 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 77 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 78 #define MVSATA_WDC_READ_2(mvport, reg) \ 79 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, (reg)) 80 #define MVSATA_WDC_READ_1(mvport, reg) \ 81 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, (reg)) 82 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 83 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 84 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 85 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 86 87 #ifdef MVSATA_DEBUG 88 #define DPRINTF(x) if (mvsata_debug) printf x 89 #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x 90 int mvsata_debug = 2; 91 #else 92 #define DPRINTF(x) 93 #define DPRINTFN(n,x) 94 #endif 95 96 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 97 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 98 sending a cmd */ 99 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 100 101 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 102 103 104 #ifndef MVSATA_WITHOUTDMA 105 static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *); 106 static void mvsata_reset_drive(struct ata_drive_datas *, int); 107 static void mvsata_reset_channel(struct ata_channel *, int); 108 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *); 109 static int mvsata_addref(struct ata_drive_datas *); 110 static void mvsata_delref(struct ata_drive_datas *); 111 static void mvsata_killpending(struct ata_drive_datas *); 112 113 #if NATAPIBUS > 0 114 static void mvsata_atapibus_attach(struct atabus_softc *); 115 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 116 scsipi_adapter_req_t, void *); 117 static void mvsata_atapi_minphys(struct buf *); 118 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 119 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 120 #endif 121 #endif 122 123 static void mvsata_setup_channel(struct ata_channel *); 124 125 #ifndef MVSATA_WITHOUTDMA 126 static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 127 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 128 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 129 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 130 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 131 int); 132 static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 133 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 134 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 135 int); 136 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 137 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 138 #if NATAPIBUS > 0 139 static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 140 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 141 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 142 int); 143 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 144 static void mvsata_atapi_phase_complete(struct ata_xfer *); 145 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_atapi_polldsc(void *); 147 #endif 148 149 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_bio *, void *); 150 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 151 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 152 static void mvsata_edma_timeout(void *); 153 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 154 #if NATAPIBUS > 0 155 static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *); 156 static void mvsata_bdma_start(struct mvsata_port *); 157 #endif 158 #endif 159 160 static int mvsata_port_init(struct mvsata_hc *, int); 161 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 162 #ifndef MVSATA_WITHOUTDMA 163 static inline void mvsata_quetag_init(struct mvsata_port *); 164 static inline int mvsata_quetag_get(struct mvsata_port *); 165 static inline void mvsata_quetag_put(struct mvsata_port *, int); 166 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 167 bus_dmamap_t *, size_t, int); 168 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 169 bus_dmamap_t, void *); 170 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 171 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 172 #endif 173 174 static void mvsata_hreset_port(struct mvsata_port *); 175 static void mvsata_reset_port(struct mvsata_port *); 176 static void mvsata_reset_hc(struct mvsata_hc *); 177 #ifndef MVSATA_WITHOUTDMA 178 static void mvsata_softreset(struct mvsata_port *, int); 179 static void mvsata_edma_reset_qptr(struct mvsata_port *); 180 static inline void mvsata_edma_enable(struct mvsata_port *); 181 static int mvsata_edma_disable(struct mvsata_port *, int, int); 182 static void mvsata_edma_config(struct mvsata_port *, int); 183 184 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int, 185 struct ata_bio *); 186 #endif 187 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 188 static void mvsata_fix_phy_gen1(struct mvsata_port *); 189 static void mvsata_devconn_gen1(struct mvsata_port *); 190 191 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 192 static void mvsata_fix_phy_gen2(struct mvsata_port *); 193 #ifndef MVSATA_WITHOUTDMA 194 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int, 195 struct ata_bio *); 196 197 #ifdef MVSATA_DEBUG 198 static void mvsata_print_crqb(struct mvsata_port *, int); 199 static void mvsata_print_crpb(struct mvsata_port *, int); 200 static void mvsata_print_eprd(struct mvsata_port *, int); 201 #endif 202 203 204 struct ata_bustype mvsata_ata_bustype = { 205 SCSIPI_BUSTYPE_ATA, 206 mvsata_bio, 207 mvsata_reset_drive, 208 mvsata_reset_channel, 209 mvsata_exec_command, 210 ata_get_params, 211 mvsata_addref, 212 mvsata_delref, 213 mvsata_killpending 214 }; 215 216 #if NATAPIBUS > 0 217 static const struct scsipi_bustype mvsata_atapi_bustype = { 218 SCSIPI_BUSTYPE_ATAPI, 219 atapi_scsipi_cmd, 220 atapi_interpret_sense, 221 atapi_print_addr, 222 mvsata_atapi_kill_pending, 223 }; 224 #endif /* NATAPIBUS */ 225 #endif 226 227 228 int 229 mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product, 230 int (*mvsata_sreset)(struct mvsata_softc *), 231 int (*mvsata_misc_reset)(struct mvsata_softc *), 232 int read_pre_amps) 233 { 234 struct mvsata_hc *mvhc; 235 struct mvsata_port *mvport; 236 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 237 void (*_fix_phy)(struct mvsata_port *) = NULL; 238 #ifndef MVSATA_WITHOUTDMA 239 void (*edma_setup_crqb) 240 (struct mvsata_port *, int, int, struct ata_bio *) = NULL; 241 #endif 242 int hc, port, channel; 243 244 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 245 (product->generation == gen1) ? "I" : 246 ((product->generation == gen2) ? "II" : "IIe"), 247 product->hc, product->port); 248 249 250 switch (product->generation) { 251 case gen1: 252 mvsata_sreset = NULL; 253 read_pre_amps = 1; /* MUST */ 254 read_preamps = mvsata_read_preamps_gen1; 255 _fix_phy = mvsata_fix_phy_gen1; 256 #ifndef MVSATA_WITHOUTDMA 257 edma_setup_crqb = mvsata_edma_setup_crqb; 258 #endif 259 break; 260 261 case gen2: 262 read_preamps = mvsata_read_preamps_gen2; 263 _fix_phy = mvsata_fix_phy_gen2; 264 #ifndef MVSATA_WITHOUTDMA 265 edma_setup_crqb = mvsata_edma_setup_crqb; 266 #endif 267 break; 268 269 case gen2e: 270 read_preamps = mvsata_read_preamps_gen2; 271 _fix_phy = mvsata_fix_phy_gen2; 272 #ifndef MVSATA_WITHOUTDMA 273 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 274 #endif 275 break; 276 } 277 278 sc->sc_gen = product->generation; 279 sc->sc_hc = product->hc; 280 sc->sc_port = product->port; 281 sc->sc_flags = product->flags; 282 283 #ifdef MVSATA_WITHOUTDMA 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 285 #else 286 sc->sc_edma_setup_crqb = edma_setup_crqb; 287 sc->sc_wdcdev.sc_atac.atac_cap |= 288 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 289 #endif 290 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 291 #ifdef MVSATA_WITHOUTDMA 292 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 293 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 294 #else 295 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 297 #endif 298 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 299 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 300 #ifndef MVSATA_WITHOUTDMA 301 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 302 #if NATAPIBUS > 0 303 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 304 #endif 305 #endif 306 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 307 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 308 309 sc->sc_wdc_regs = 310 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 311 M_DEVBUF, M_NOWAIT); 312 if (sc->sc_wdc_regs == NULL) { 313 aprint_error_dev(MVSATA_DEV(sc), 314 "can't allocate wdc regs memory\n"); 315 return ENOMEM; 316 } 317 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 318 319 for (hc = 0; hc < sc->sc_hc; hc++) { 320 mvhc = &sc->sc_hcs[hc]; 321 mvhc->hc = hc; 322 mvhc->hc_sc = sc; 323 mvhc->hc_iot = sc->sc_iot; 324 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 325 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 326 &mvhc->hc_ioh)) { 327 aprint_error_dev(MVSATA_DEV(sc), 328 "can't subregion SATAHC %d registers\n", hc); 329 continue; 330 } 331 332 for (port = 0; port < sc->sc_port; port++) 333 if (mvsata_port_init(mvhc, port) == 0) { 334 int pre_amps; 335 336 mvport = mvhc->hc_ports[port]; 337 pre_amps = read_pre_amps ? 338 read_preamps(mvport) : 0x00000720; 339 mvport->_fix_phy_param.pre_amps = pre_amps; 340 mvport->_fix_phy_param._fix_phy = _fix_phy; 341 342 if (!mvsata_sreset) 343 mvsata_reset_port(mvport); 344 } 345 346 if (!mvsata_sreset) 347 mvsata_reset_hc(mvhc); 348 } 349 if (mvsata_sreset) 350 mvsata_sreset(sc); 351 352 if (mvsata_misc_reset) 353 mvsata_misc_reset(sc); 354 355 for (hc = 0; hc < sc->sc_hc; hc++) 356 for (port = 0; port < sc->sc_port; port++) { 357 mvport = sc->sc_hcs[hc].hc_ports[port]; 358 if (mvport == NULL) 359 continue; 360 if (mvsata_sreset) 361 mvport->_fix_phy_param._fix_phy(mvport); 362 } 363 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 364 wdcattach(sc->sc_ata_channels[channel]); 365 366 return 0; 367 } 368 369 int 370 mvsata_intr(struct mvsata_hc *mvhc) 371 { 372 struct mvsata_softc *sc = mvhc->hc_sc; 373 struct mvsata_port *mvport; 374 uint32_t cause; 375 int port, handled = 0; 376 377 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 378 379 DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n", 380 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 381 382 if (cause & SATAHC_IC_SAINTCOAL) 383 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 384 cause &= ~SATAHC_IC_SAINTCOAL; 385 for (port = 0; port < sc->sc_port; port++) { 386 mvport = mvhc->hc_ports[port]; 387 388 if (cause & SATAHC_IC_DONE(port)) { 389 #ifndef MVSATA_WITHOUTDMA 390 handled = mvsata_edma_handle(mvport, NULL); 391 #endif 392 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 393 ~SATAHC_IC_DONE(port)); 394 } 395 396 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 397 wdcintr(&mvport->port_ata_channel); 398 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 399 ~SATAHC_IC_SADEVINTERRUPT(port)); 400 handled = 1; 401 } 402 } 403 404 return handled; 405 } 406 407 int 408 mvsata_error(struct mvsata_port *mvport) 409 { 410 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 411 uint32_t cause; 412 int handled = 0; 413 414 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 415 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 416 417 DPRINTFN(3, ("%s:%d:%d:" 418 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 419 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 420 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 421 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 422 423 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 424 if (!cause) 425 return 0; 426 427 /* If PM connected, connect/disconnect interrupts storm could happen */ 428 if (MVSATA_EDMA_READ_4(mvport, EDMA_IEC) & 429 (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) 430 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 431 delay(20 * 1000); 432 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 433 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 434 } 435 436 if (cause & EDMA_IE_EDEVDIS) 437 aprint_normal("%s:%d:%d: device disconnect\n", 438 device_xname(MVSATA_DEV2(mvport)), 439 mvport->port_hc->hc, mvport->port); 440 if (cause & EDMA_IE_EDEVCON) { 441 if (sc->sc_gen == gen1) 442 mvsata_devconn_gen1(mvport); 443 444 DPRINTFN(3, (" device connected\n")); 445 handled = 1; 446 } 447 #ifndef MVSATA_WITHOUTDMA 448 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 449 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 450 switch (mvport->port_edmamode) { 451 case dma: 452 case queued: 453 case ncq: 454 mvsata_edma_reset_qptr(mvport); 455 mvsata_edma_enable(mvport); 456 if (cause & EDMA_IE_EDEVERR) 457 break; 458 459 /* FALLTHROUGH */ 460 461 case nodma: 462 default: 463 aprint_error( 464 "%s:%d:%d: EDMA self disable happen 0x%x\n", 465 device_xname(MVSATA_DEV2(mvport)), 466 mvport->port_hc->hc, mvport->port, cause); 467 break; 468 } 469 handled = 1; 470 } 471 #endif 472 if (cause & EDMA_IE_ETRANSINT) { 473 /* hot plug the Port Multiplier */ 474 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 475 device_xname(MVSATA_DEV2(mvport)), 476 mvport->port_hc->hc, mvport->port); 477 } 478 479 return handled; 480 } 481 482 483 /* 484 * ATA callback entry points 485 */ 486 487 #ifndef MVSATA_WITHOUTDMA 488 static int 489 mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 490 { 491 struct ata_channel *chp = drvp->chnl_softc; 492 struct atac_softc *atac = chp->ch_atac; 493 struct ata_xfer *xfer; 494 495 DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 496 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 497 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 498 499 xfer = ata_get_xfer(ATAXF_NOSLEEP); 500 if (xfer == NULL) 501 return ATACMD_TRY_AGAIN; 502 if (atac->atac_cap & ATAC_CAP_NOIRQ) 503 ata_bio->flags |= ATA_POLL; 504 if (ata_bio->flags & ATA_POLL) 505 xfer->c_flags |= C_POLL; 506 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 507 (ata_bio->flags & ATA_SINGLE) == 0) 508 xfer->c_flags |= C_DMA; 509 xfer->c_drive = drvp->drive; 510 xfer->c_cmd = ata_bio; 511 xfer->c_databuf = ata_bio->databuf; 512 xfer->c_bcount = ata_bio->bcount; 513 xfer->c_start = mvsata_bio_start; 514 xfer->c_intr = mvsata_bio_intr; 515 xfer->c_kill_xfer = mvsata_bio_kill_xfer; 516 ata_exec_xfer(chp, xfer); 517 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 518 } 519 520 static void 521 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags) 522 { 523 struct ata_channel *chp = drvp->chnl_softc; 524 struct mvsata_port *mvport = (struct mvsata_port *)chp; 525 uint32_t edma_c; 526 527 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 528 529 DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 530 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 531 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 532 533 if (edma_c & EDMA_CMD_EENEDMA) 534 mvsata_edma_disable(mvport, 10000, flags & AT_WAIT); 535 536 mvsata_softreset(mvport, flags & AT_WAIT); 537 538 if (edma_c & EDMA_CMD_EENEDMA) { 539 mvsata_edma_reset_qptr(mvport); 540 mvsata_edma_enable(mvport); 541 } 542 return; 543 } 544 545 static void 546 mvsata_reset_channel(struct ata_channel *chp, int flags) 547 { 548 struct mvsata_port *mvport = (struct mvsata_port *)chp; 549 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 550 struct ata_xfer *xfer; 551 uint32_t sstat, ctrl; 552 int i; 553 554 DPRINTF(("%s: mvsata_reset_channel: channel=%d\n", 555 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 556 557 mvsata_hreset_port(mvport); 558 sstat = sata_reset_interface(chp, mvport->port_iot, 559 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 560 561 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 562 sc->sc_gen != gen1) { 563 /* Downgrade to GenI */ 564 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 565 SControl_DET_DISABLE; 566 567 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 568 569 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 570 ctrl &= ~(1 << 17); /* Disable GenII */ 571 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 572 573 mvsata_hreset_port(mvport); 574 sata_reset_interface(chp, mvport->port_iot, 575 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 576 } 577 578 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 579 xfer = mvport->port_reqtbl[i].xfer; 580 if (xfer == NULL) 581 continue; 582 chp->ch_queue->active_xfer = xfer; 583 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 584 } 585 586 mvsata_edma_config(mvport, mvport->port_edmamode); 587 mvsata_edma_reset_qptr(mvport); 588 mvsata_edma_enable(mvport); 589 return; 590 } 591 592 593 static int 594 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 595 { 596 struct ata_channel *chp = drvp->chnl_softc; 597 #ifdef MVSATA_DEBUG 598 struct mvsata_port *mvport = (struct mvsata_port *)chp; 599 #endif 600 struct ata_xfer *xfer; 601 int rv, s; 602 603 DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 604 " r_command=0x%x, r_head=0x%x, r_cyl=0x%x, r_sector=0x%x," 605 " r_count=0x%x, r_features=0x%x\n", 606 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 607 drvp->drive, ata_c->bcount, ata_c->r_command, ata_c->r_head, 608 ata_c->r_cyl, ata_c->r_sector, ata_c->r_count, ata_c->r_features)); 609 610 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 611 ATAXF_NOSLEEP); 612 if (xfer == NULL) 613 return ATACMD_TRY_AGAIN; 614 if (ata_c->flags & AT_POLL) 615 xfer->c_flags |= C_POLL; 616 if (ata_c->flags & AT_WAIT) 617 xfer->c_flags |= C_WAIT; 618 xfer->c_drive = drvp->drive; 619 xfer->c_databuf = ata_c->data; 620 xfer->c_bcount = ata_c->bcount; 621 xfer->c_cmd = ata_c; 622 xfer->c_start = mvsata_wdc_cmd_start; 623 xfer->c_intr = mvsata_wdc_cmd_intr; 624 xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer; 625 s = splbio(); 626 ata_exec_xfer(chp, xfer); 627 #ifdef DIAGNOSTIC 628 if ((ata_c->flags & AT_POLL) != 0 && 629 (ata_c->flags & AT_DONE) == 0) 630 panic("mvsata_exec_command: polled command not done"); 631 #endif 632 if (ata_c->flags & AT_DONE) 633 rv = ATACMD_COMPLETE; 634 else { 635 if (ata_c->flags & AT_WAIT) { 636 while ((ata_c->flags & AT_DONE) == 0) 637 tsleep(ata_c, PRIBIO, "mvsatacmd", 0); 638 rv = ATACMD_COMPLETE; 639 } else 640 rv = ATACMD_QUEUED; 641 } 642 splx(s); 643 return rv; 644 } 645 646 static int 647 mvsata_addref(struct ata_drive_datas *drvp) 648 { 649 650 return 0; 651 } 652 653 static void 654 mvsata_delref(struct ata_drive_datas *drvp) 655 { 656 657 return; 658 } 659 660 static void 661 mvsata_killpending(struct ata_drive_datas *drvp) 662 { 663 664 return; 665 } 666 667 #if NATAPIBUS > 0 668 static void 669 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 670 { 671 struct ata_channel *chp = ata_sc->sc_chan; 672 struct atac_softc *atac = chp->ch_atac; 673 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 674 struct scsipi_channel *chan = &chp->ch_atapi_channel; 675 676 /* 677 * Fill in the scsipi_adapter. 678 */ 679 adapt->adapt_dev = atac->atac_dev; 680 adapt->adapt_nchannels = atac->atac_nchannels; 681 adapt->adapt_request = mvsata_atapi_scsipi_request; 682 adapt->adapt_minphys = mvsata_atapi_minphys; 683 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 684 685 /* 686 * Fill in the scsipi_channel. 687 */ 688 memset(chan, 0, sizeof(*chan)); 689 chan->chan_adapter = adapt; 690 chan->chan_bustype = &mvsata_atapi_bustype; 691 chan->chan_channel = chp->ch_channel; 692 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 693 chan->chan_openings = 1; 694 chan->chan_max_periph = 1; 695 chan->chan_ntargets = 1; 696 chan->chan_nluns = 1; 697 698 chp->atapibus = 699 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 700 } 701 702 static void 703 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 704 scsipi_adapter_req_t req, void *arg) 705 { 706 struct scsipi_adapter *adapt = chan->chan_adapter; 707 struct scsipi_periph *periph; 708 struct scsipi_xfer *sc_xfer; 709 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 710 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 711 struct ata_xfer *xfer; 712 int channel = chan->chan_channel; 713 int drive, s; 714 715 switch (req) { 716 case ADAPTER_REQ_RUN_XFER: 717 sc_xfer = arg; 718 periph = sc_xfer->xs_periph; 719 drive = periph->periph_target; 720 721 if (!device_is_active(atac->atac_dev)) { 722 sc_xfer->error = XS_DRIVER_STUFFUP; 723 scsipi_done(sc_xfer); 724 return; 725 } 726 xfer = ata_get_xfer(ATAXF_NOSLEEP); 727 if (xfer == NULL) { 728 sc_xfer->error = XS_RESOURCE_SHORTAGE; 729 scsipi_done(sc_xfer); 730 return; 731 } 732 733 if (sc_xfer->xs_control & XS_CTL_POLL) 734 xfer->c_flags |= C_POLL; 735 xfer->c_drive = drive; 736 xfer->c_flags |= C_ATAPI; 737 xfer->c_cmd = sc_xfer; 738 xfer->c_databuf = sc_xfer->data; 739 xfer->c_bcount = sc_xfer->datalen; 740 xfer->c_start = mvsata_atapi_start; 741 xfer->c_intr = mvsata_atapi_intr; 742 xfer->c_kill_xfer = mvsata_atapi_kill_xfer; 743 xfer->c_dscpoll = 0; 744 s = splbio(); 745 ata_exec_xfer(atac->atac_channels[channel], xfer); 746 #ifdef DIAGNOSTIC 747 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 748 (sc_xfer->xs_status & XS_STS_DONE) == 0) 749 panic("mvsata_atapi_scsipi_request:" 750 " polled command not done"); 751 #endif 752 splx(s); 753 return; 754 755 default: 756 /* Not supported, nothing to do. */ 757 ; 758 } 759 } 760 761 static void 762 mvsata_atapi_minphys(struct buf *bp) 763 { 764 765 if (bp->b_bcount > MAXPHYS) 766 bp->b_bcount = MAXPHYS; 767 minphys(bp); 768 } 769 770 static void 771 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 772 { 773 struct scsipi_channel *chan = sc->sc_channel; 774 struct scsipi_periph *periph; 775 struct ataparams ids; 776 struct ataparams *id = &ids; 777 struct mvsata_softc *mvc = 778 device_private(chan->chan_adapter->adapt_dev); 779 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 780 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 781 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 782 struct scsipibus_attach_args sa; 783 char serial_number[21], model[41], firmware_revision[9]; 784 int s; 785 786 /* skip if already attached */ 787 if (scsipi_lookup_periph(chan, target, 0) != NULL) 788 return; 789 790 /* if no ATAPI device detected at attach time, skip */ 791 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 792 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 793 " drive %d not present\n", 794 device_xname(atac->atac_dev), chp->ch_channel, target)); 795 return; 796 } 797 798 /* Some ATAPI devices need a bit more time after software reset. */ 799 delay(5000); 800 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 801 #ifdef ATAPI_DEBUG_PROBE 802 log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n", 803 device_xname(atac->atac_dev), chp->ch_channel, target, 804 id->atap_config & ATAPI_CFG_CMD_MASK, 805 id->atap_config & ATAPI_CFG_DRQ_MASK); 806 #endif 807 periph = scsipi_alloc_periph(M_NOWAIT); 808 if (periph == NULL) { 809 aprint_error_dev(atac->atac_dev, 810 "unable to allocate periph" 811 " for channel %d drive %d\n", 812 chp->ch_channel, target); 813 return; 814 } 815 periph->periph_dev = NULL; 816 periph->periph_channel = chan; 817 periph->periph_switch = &atapi_probe_periphsw; 818 periph->periph_target = target; 819 periph->periph_lun = 0; 820 periph->periph_quirks = PQUIRK_ONLYBIG; 821 822 #ifdef SCSIPI_DEBUG 823 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 824 SCSIPI_DEBUG_TARGET == target) 825 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 826 #endif 827 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 828 if (id->atap_config & ATAPI_CFG_REMOV) 829 periph->periph_flags |= PERIPH_REMOVABLE; 830 if (periph->periph_type == T_SEQUENTIAL) { 831 s = splbio(); 832 drvp->drive_flags |= DRIVE_ATAPIST; 833 splx(s); 834 } 835 836 sa.sa_periph = periph; 837 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 838 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 839 T_REMOV : T_FIXED; 840 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 841 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 20); 842 scsipi_strvis((u_char *)firmware_revision, 8, id->atap_revision, 843 8); 844 sa.sa_inqbuf.vendor = model; 845 sa.sa_inqbuf.product = serial_number; 846 sa.sa_inqbuf.revision = firmware_revision; 847 848 /* 849 * Determine the operating mode capabilities of the device. 850 */ 851 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 852 periph->periph_cap |= PERIPH_CAP_CMD16; 853 /* XXX This is gross. */ 854 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 855 856 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 857 858 if (drvp->drv_softc) 859 ata_probe_caps(drvp); 860 else { 861 s = splbio(); 862 drvp->drive_flags &= ~DRIVE_ATAPI; 863 splx(s); 864 } 865 } else { 866 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 867 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n", 868 device_xname(atac->atac_dev), chp->ch_channel, target, 869 chp->ch_error)); 870 s = splbio(); 871 drvp->drive_flags &= ~DRIVE_ATAPI; 872 splx(s); 873 } 874 } 875 876 /* 877 * Kill off all pending xfers for a periph. 878 * 879 * Must be called at splbio(). 880 */ 881 static void 882 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 883 { 884 struct atac_softc *atac = 885 device_private(periph->periph_channel->chan_adapter->adapt_dev); 886 struct ata_channel *chp = 887 atac->atac_channels[periph->periph_channel->chan_channel]; 888 889 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 890 } 891 #endif /* NATAPIBUS > 0 */ 892 #endif /* MVSATA_WITHOUTDMA */ 893 894 895 /* 896 * mvsata_setup_channel() 897 * Setup EDMA registers and prepare/purge DMA resources. 898 * We assuming already stopped the EDMA. 899 */ 900 static void 901 mvsata_setup_channel(struct ata_channel *chp) 902 { 903 #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG) 904 struct mvsata_port *mvport = (struct mvsata_port *)chp; 905 #endif 906 struct ata_drive_datas *drvp; 907 uint32_t edma_mode; 908 int drive, s; 909 #ifndef MVSATA_WITHOUTDMA 910 int i; 911 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 912 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 913 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 914 #endif 915 916 DPRINTF(("%s:%d: mvsata_setup_channel: ", 917 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 918 919 edma_mode = nodma; 920 for (drive = 0; drive < chp->ch_ndrive; drive++) { 921 drvp = &chp->ch_drive[drive]; 922 923 /* If no drive, skip */ 924 if (!(drvp->drive_flags & DRIVE)) 925 continue; 926 927 if (drvp->drive_flags & DRIVE_UDMA) { 928 /* use Ultra/DMA */ 929 s = splbio(); 930 drvp->drive_flags &= ~DRIVE_DMA; 931 splx(s); 932 } 933 934 if (drvp->drive_flags & (DRIVE_UDMA | DRIVE_DMA)) 935 if (drvp->drive_flags & DRIVE_ATA) 936 edma_mode = dma; 937 } 938 939 DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 940 941 #ifndef MVSATA_WITHOUTDMA 942 if (edma_mode == nodma) { 943 no_edma: 944 if (mvport->port_crqb != NULL) 945 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 946 mvport->port_crqb_dmamap, mvport->port_crqb); 947 if (mvport->port_crpb != NULL) 948 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 949 mvport->port_crpb_dmamap, mvport->port_crpb); 950 if (mvport->port_eprd != NULL) 951 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 952 mvport->port_eprd_dmamap, mvport->port_eprd); 953 954 return; 955 } 956 957 if (mvport->port_crqb == NULL) 958 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 959 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 960 if (mvport->port_crpb == NULL) 961 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 962 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 963 if (mvport->port_eprd == NULL) { 964 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 965 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 966 1); 967 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 968 mvport->port_reqtbl[i].eprd_offset = 969 i * MVSATA_EPRD_MAX_SIZE; 970 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 971 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 972 } 973 } 974 975 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 976 mvport->port_eprd == NULL) { 977 aprint_error_dev(MVSATA_DEV2(mvport), 978 "channel %d: can't use EDMA\n", chp->ch_channel); 979 s = splbio(); 980 for (drive = 0; drive < chp->ch_ndrive; drive++) { 981 drvp = &chp->ch_drive[drive]; 982 983 /* If no drive, skip */ 984 if (!(drvp->drive_flags & DRIVE)) 985 continue; 986 987 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 988 } 989 splx(s); 990 goto no_edma; 991 } 992 993 mvsata_edma_config(mvport, edma_mode); 994 mvsata_edma_reset_qptr(mvport); 995 mvsata_edma_enable(mvport); 996 #endif 997 } 998 999 #ifndef MVSATA_WITHOUTDMA 1000 static void 1001 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1002 { 1003 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1004 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1005 struct atac_softc *atac = chp->ch_atac; 1006 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1007 struct ata_bio *ata_bio = xfer->c_cmd; 1008 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1009 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1010 u_int16_t cyl; 1011 u_int8_t head, sect, cmd = 0; 1012 int nblks, error; 1013 1014 DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n", 1015 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1016 1017 if (xfer->c_flags & C_DMA) 1018 if (drvp->n_xfers <= NXFER) 1019 drvp->n_xfers++; 1020 1021 again: 1022 /* 1023 * 1024 * When starting a multi-sector transfer, or doing single-sector 1025 * transfers... 1026 */ 1027 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1028 if (ata_bio->flags & ATA_SINGLE) 1029 nblks = 1; 1030 else 1031 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1032 /* Check for bad sectors and adjust transfer, if necessary. */ 1033 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 1034 long blkdiff; 1035 int i; 1036 1037 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 1038 i++) { 1039 blkdiff -= ata_bio->blkno; 1040 if (blkdiff < 0) 1041 continue; 1042 if (blkdiff == 0) 1043 /* Replace current block of transfer. */ 1044 ata_bio->blkno = 1045 ata_bio->lp->d_secperunit - 1046 ata_bio->lp->d_nsectors - i - 1; 1047 if (blkdiff < nblks) { 1048 /* Bad block inside transfer. */ 1049 ata_bio->flags |= ATA_SINGLE; 1050 nblks = 1; 1051 } 1052 break; 1053 } 1054 /* Transfer is okay now. */ 1055 } 1056 if (xfer->c_flags & C_DMA) { 1057 ata_bio->nblks = nblks; 1058 ata_bio->nbytes = xfer->c_bcount; 1059 1060 if (xfer->c_flags & C_POLL) 1061 sc->sc_enable_intr(mvport, 0 /*off*/); 1062 error = mvsata_edma_enqueue(mvport, ata_bio, 1063 (char *)xfer->c_databuf + xfer->c_skip); 1064 if (error) { 1065 if (error == EINVAL) { 1066 /* 1067 * We can't do DMA on this transfer 1068 * for some reason. Fall back to 1069 * PIO. 1070 */ 1071 xfer->c_flags &= ~C_DMA; 1072 error = 0; 1073 goto do_pio; 1074 } 1075 if (error == EBUSY) { 1076 aprint_error_dev(atac->atac_dev, 1077 "channel %d: EDMA Queue full\n", 1078 chp->ch_channel); 1079 /* 1080 * XXXX: Perhaps, after it waits for 1081 * a while, it is necessary to call 1082 * bio_start again. 1083 */ 1084 } 1085 ata_bio->error = ERR_DMA; 1086 ata_bio->r_error = 0; 1087 mvsata_bio_done(chp, xfer); 1088 return; 1089 } 1090 chp->ch_flags |= ATACH_DMA_WAIT; 1091 /* start timeout machinery */ 1092 if ((xfer->c_flags & C_POLL) == 0) 1093 callout_reset(&chp->ch_callout, 1094 ATA_DELAY / 1000 * hz, 1095 mvsata_edma_timeout, xfer); 1096 /* wait for irq */ 1097 goto intr; 1098 } /* else not DMA */ 1099 do_pio: 1100 if (ata_bio->flags & ATA_LBA48) { 1101 sect = 0; 1102 cyl = 0; 1103 head = 0; 1104 } else if (ata_bio->flags & ATA_LBA) { 1105 sect = (ata_bio->blkno >> 0) & 0xff; 1106 cyl = (ata_bio->blkno >> 8) & 0xffff; 1107 head = (ata_bio->blkno >> 24) & 0x0f; 1108 head |= WDSD_LBA; 1109 } else { 1110 int blkno = ata_bio->blkno; 1111 sect = blkno % ata_bio->lp->d_nsectors; 1112 sect++; /* Sectors begin with 1, not 0. */ 1113 blkno /= ata_bio->lp->d_nsectors; 1114 head = blkno % ata_bio->lp->d_ntracks; 1115 blkno /= ata_bio->lp->d_ntracks; 1116 cyl = blkno; 1117 head |= WDSD_CHS; 1118 } 1119 ata_bio->nblks = min(nblks, ata_bio->multi); 1120 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 1121 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1122 if (ata_bio->nblks > 1) 1123 cmd = (ata_bio->flags & ATA_READ) ? 1124 WDCC_READMULTI : WDCC_WRITEMULTI; 1125 else 1126 cmd = (ata_bio->flags & ATA_READ) ? 1127 WDCC_READ : WDCC_WRITE; 1128 1129 /* EDMA disable, if enabled this channel. */ 1130 if (mvport->port_edmamode != nodma) 1131 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1132 1133 /* Do control operations specially. */ 1134 if (__predict_false(drvp->state < READY)) { 1135 /* 1136 * Actually, we want to be careful not to mess with 1137 * the control state if the device is currently busy, 1138 * but we can assume that we never get to this point 1139 * if that's the case. 1140 */ 1141 /* 1142 * If it's not a polled command, we need the kernel 1143 * thread 1144 */ 1145 if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) { 1146 chp->ch_queue->queue_freeze++; 1147 wakeup(&chp->ch_thread); 1148 return; 1149 } 1150 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1151 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1152 mvsata_bio_done(chp, xfer); 1153 return; 1154 } 1155 } 1156 1157 /* Initiate command! */ 1158 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1159 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 1160 case WDCWAIT_OK: 1161 break; 1162 case WDCWAIT_TOUT: 1163 goto timeout; 1164 case WDCWAIT_THR: 1165 return; 1166 } 1167 if (ata_bio->flags & ATA_LBA48) 1168 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 1169 (uint64_t)ata_bio->blkno, nblks, 0); 1170 else 1171 wdccommand(chp, xfer->c_drive, cmd, cyl, 1172 head, sect, nblks, 1173 (ata_bio->lp->d_type == DTYPE_ST506) ? 1174 ata_bio->lp->d_precompcyl / 4 : 0); 1175 1176 /* start timeout machinery */ 1177 if ((xfer->c_flags & C_POLL) == 0) 1178 callout_reset(&chp->ch_callout, 1179 ATA_DELAY / 1000 * hz, wdctimeout, chp); 1180 } else if (ata_bio->nblks > 1) { 1181 /* The number of blocks in the last stretch may be smaller. */ 1182 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1183 if (ata_bio->nblks > nblks) { 1184 ata_bio->nblks = nblks; 1185 ata_bio->nbytes = xfer->c_bcount; 1186 } 1187 } 1188 /* If this was a write and not using DMA, push the data. */ 1189 if ((ata_bio->flags & ATA_READ) == 0) { 1190 /* 1191 * we have to busy-wait here, we can't rely on running in 1192 * thread context. 1193 */ 1194 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 1195 aprint_error_dev(atac->atac_dev, 1196 "channel %d: drive %d timeout waiting for DRQ," 1197 " st=0x%02x, err=0x%02x\n", 1198 chp->ch_channel, xfer->c_drive, chp->ch_status, 1199 chp->ch_error); 1200 ata_bio->error = TIMEOUT; 1201 mvsata_bio_done(chp, xfer); 1202 return; 1203 } 1204 if (chp->ch_status & WDCS_ERR) { 1205 ata_bio->error = ERROR; 1206 ata_bio->r_error = chp->ch_error; 1207 mvsata_bio_done(chp, xfer); 1208 return; 1209 } 1210 1211 wdc->dataout_pio(chp, drvp->drive_flags, 1212 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1213 } 1214 1215 intr: 1216 /* Wait for IRQ (either real or polled) */ 1217 if ((ata_bio->flags & ATA_POLL) == 0) { 1218 chp->ch_flags |= ATACH_IRQ_WAIT; 1219 } else { 1220 /* Wait for at last 400ns for status bit to be valid */ 1221 delay(1); 1222 if (chp->ch_flags & ATACH_DMA_WAIT) { 1223 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1224 sc->sc_enable_intr(mvport, 1 /*on*/); 1225 chp->ch_flags &= ~ATACH_DMA_WAIT; 1226 } 1227 mvsata_bio_intr(chp, xfer, 0); 1228 if ((ata_bio->flags & ATA_ITSDONE) == 0) 1229 goto again; 1230 } 1231 return; 1232 1233 timeout: 1234 aprint_error_dev(atac->atac_dev, 1235 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1236 chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error); 1237 ata_bio->error = TIMEOUT; 1238 mvsata_bio_done(chp, xfer); 1239 return; 1240 } 1241 1242 static int 1243 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1244 { 1245 struct atac_softc *atac = chp->ch_atac; 1246 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1247 struct ata_bio *ata_bio = xfer->c_cmd; 1248 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1249 1250 DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n", 1251 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1252 1253 chp->ch_flags &= ~(ATACH_IRQ_WAIT|ATACH_DMA_WAIT); 1254 1255 /* Is it not a transfer, but a control operation? */ 1256 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1257 aprint_error_dev(atac->atac_dev, 1258 "channel %d: drive %d bad state %d in mvsata_bio_intr\n", 1259 chp->ch_channel, xfer->c_drive, drvp->state); 1260 panic("mvsata_bio_intr: bad state"); 1261 } 1262 1263 /* 1264 * If we missed an interrupt transfer, reset and restart. 1265 * Don't try to continue transfer, we may have missed cycles. 1266 */ 1267 if (xfer->c_flags & C_TIMEOU) { 1268 ata_bio->error = TIMEOUT; 1269 mvsata_bio_done(chp, xfer); 1270 return 1; 1271 } 1272 1273 /* Ack interrupt done by wdc_wait_for_unbusy */ 1274 if (!(xfer->c_flags & C_DMA) && 1275 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) 1276 == WDCWAIT_TOUT)) { 1277 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1278 return 0; /* IRQ was not for us */ 1279 aprint_error_dev(atac->atac_dev, 1280 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1281 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1282 xfer->c_skip); 1283 ata_bio->error = TIMEOUT; 1284 mvsata_bio_done(chp, xfer); 1285 return 1; 1286 } 1287 1288 if (xfer->c_flags & C_DMA) { 1289 if (ata_bio->error == NOERROR) 1290 goto end; 1291 if (ata_bio->error == ERR_DMA) 1292 ata_dmaerr(drvp, 1293 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1294 } 1295 1296 /* if we had an error, end */ 1297 if (ata_bio->error != NOERROR) { 1298 mvsata_bio_done(chp, xfer); 1299 return 1; 1300 } 1301 1302 /* If this was a read and not using DMA, fetch the data. */ 1303 if ((ata_bio->flags & ATA_READ) != 0) { 1304 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 1305 aprint_error_dev(atac->atac_dev, 1306 "channel %d: drive %d read intr before drq\n", 1307 chp->ch_channel, xfer->c_drive); 1308 ata_bio->error = TIMEOUT; 1309 mvsata_bio_done(chp, xfer); 1310 return 1; 1311 } 1312 wdc->datain_pio(chp, drvp->drive_flags, 1313 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1314 } 1315 1316 end: 1317 ata_bio->blkno += ata_bio->nblks; 1318 ata_bio->blkdone += ata_bio->nblks; 1319 xfer->c_skip += ata_bio->nbytes; 1320 xfer->c_bcount -= ata_bio->nbytes; 1321 /* See if this transfer is complete. */ 1322 if (xfer->c_bcount > 0) { 1323 if ((ata_bio->flags & ATA_POLL) == 0) 1324 /* Start the next operation */ 1325 mvsata_bio_start(chp, xfer); 1326 else 1327 /* Let mvsata_bio_start do the loop */ 1328 return 1; 1329 } else { /* Done with this transfer */ 1330 ata_bio->error = NOERROR; 1331 mvsata_bio_done(chp, xfer); 1332 } 1333 return 1; 1334 } 1335 1336 static void 1337 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1338 { 1339 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1340 struct atac_softc *atac = chp->ch_atac; 1341 struct ata_bio *ata_bio = xfer->c_cmd; 1342 int drive = xfer->c_drive; 1343 1344 DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1345 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1346 1347 /* EDMA restart, if enabled */ 1348 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1349 mvsata_edma_reset_qptr(mvport); 1350 mvsata_edma_enable(mvport); 1351 } 1352 1353 ata_free_xfer(chp, xfer); 1354 1355 ata_bio->flags |= ATA_ITSDONE; 1356 switch (reason) { 1357 case KILL_GONE: 1358 ata_bio->error = ERR_NODEV; 1359 break; 1360 case KILL_RESET: 1361 ata_bio->error = ERR_RESET; 1362 break; 1363 default: 1364 aprint_error_dev(atac->atac_dev, 1365 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1366 panic("mvsata_bio_kill_xfer"); 1367 } 1368 ata_bio->r_error = WDCE_ABRT; 1369 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1370 } 1371 1372 static void 1373 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1374 { 1375 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1376 struct ata_bio *ata_bio = xfer->c_cmd; 1377 int drive = xfer->c_drive; 1378 1379 DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1380 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1381 (u_int)xfer->c_flags)); 1382 1383 callout_stop(&chp->ch_callout); 1384 1385 /* EDMA restart, if enabled */ 1386 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1387 mvsata_edma_reset_qptr(mvport); 1388 mvsata_edma_enable(mvport); 1389 } 1390 1391 /* feed back residual bcount to our caller */ 1392 ata_bio->bcount = xfer->c_bcount; 1393 1394 /* mark controller inactive and free xfer */ 1395 KASSERT(chp->ch_queue->active_xfer != NULL); 1396 chp->ch_queue->active_xfer = NULL; 1397 ata_free_xfer(chp, xfer); 1398 1399 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1400 ata_bio->error = ERR_NODEV; 1401 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1402 wakeup(&chp->ch_queue->active_xfer); 1403 } 1404 ata_bio->flags |= ATA_ITSDONE; 1405 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1406 atastart(chp); 1407 } 1408 1409 static int 1410 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1411 int flags) 1412 { 1413 struct ata_channel *chp = &mvport->port_ata_channel; 1414 struct atac_softc *atac = chp->ch_atac; 1415 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1416 const char *errstring; 1417 1418 flags |= AT_POLL; /* XXX */ 1419 1420 /* 1421 * disable interrupts, all commands here should be quick 1422 * enough to be able to poll, and we don't go here that often 1423 */ 1424 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1425 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1426 DELAY(10); 1427 errstring = "wait"; 1428 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1429 goto ctrltimeout; 1430 wdccommandshort(chp, drive, WDCC_RECAL); 1431 /* Wait for at last 400ns for status bit to be valid */ 1432 DELAY(1); 1433 errstring = "recal"; 1434 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1435 goto ctrltimeout; 1436 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1437 goto ctrlerror; 1438 /* Don't try to set modes if controller can't be adjusted */ 1439 if (atac->atac_set_modes == NULL) 1440 goto geometry; 1441 /* Also don't try if the drive didn't report its mode */ 1442 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1443 goto geometry; 1444 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1445 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1446 errstring = "piomode"; 1447 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1448 goto ctrltimeout; 1449 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1450 goto ctrlerror; 1451 if (drvp->drive_flags & DRIVE_UDMA) 1452 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1453 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1454 else if (drvp->drive_flags & DRIVE_DMA) 1455 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1456 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1457 else 1458 goto geometry; 1459 errstring = "dmamode"; 1460 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1461 goto ctrltimeout; 1462 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1463 goto ctrlerror; 1464 geometry: 1465 if (ata_bio->flags & ATA_LBA) 1466 goto multimode; 1467 wdccommand(chp, drive, WDCC_IDP, ata_bio->lp->d_ncylinders, 1468 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 1469 (ata_bio->lp->d_type == DTYPE_ST506) ? 1470 ata_bio->lp->d_precompcyl / 4 : 0); 1471 errstring = "geometry"; 1472 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1473 goto ctrltimeout; 1474 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1475 goto ctrlerror; 1476 multimode: 1477 if (ata_bio->multi == 1) 1478 goto ready; 1479 wdccommand(chp, drive, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0); 1480 errstring = "setmulti"; 1481 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1482 goto ctrltimeout; 1483 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1484 goto ctrlerror; 1485 ready: 1486 drvp->state = READY; 1487 /* 1488 * The drive is usable now 1489 */ 1490 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1491 delay(10); /* some drives need a little delay here */ 1492 return 0; 1493 1494 ctrltimeout: 1495 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1496 chp->ch_channel, drive, errstring); 1497 ata_bio->error = TIMEOUT; 1498 goto ctrldone; 1499 ctrlerror: 1500 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1501 chp->ch_channel, drive, errstring); 1502 if (chp->ch_status & WDCS_DWF) { 1503 aprint_error("drive fault\n"); 1504 ata_bio->error = ERR_DF; 1505 } else { 1506 aprint_error("error (%x)\n", chp->ch_error); 1507 ata_bio->r_error = chp->ch_error; 1508 ata_bio->error = ERROR; 1509 } 1510 ctrldone: 1511 drvp->state = 0; 1512 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1513 return -1; 1514 } 1515 1516 static void 1517 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1518 { 1519 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1520 int drive = xfer->c_drive; 1521 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1522 struct ata_command *ata_c = xfer->c_cmd; 1523 1524 DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n", 1525 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1526 1527 /* First, EDMA disable, if enabled this channel. */ 1528 if (mvport->port_edmamode != nodma) 1529 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1530 1531 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1532 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1533 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1534 case WDCWAIT_OK: 1535 break; 1536 case WDCWAIT_TOUT: 1537 ata_c->flags |= AT_TIMEOU; 1538 mvsata_wdc_cmd_done(chp, xfer); 1539 return; 1540 case WDCWAIT_THR: 1541 return; 1542 } 1543 if (ata_c->flags & AT_POLL) 1544 /* polled command, disable interrupts */ 1545 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1546 if ((ata_c->flags & AT_LBA48) != 0) { 1547 wdccommandext(chp, drive, ata_c->r_command, 1548 ata_c->r_lba, ata_c->r_count, ata_c->r_features); 1549 } else { 1550 wdccommand(chp, drive, ata_c->r_command, 1551 (ata_c->r_lba >> 8) & 0xffff, 1552 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1553 ((ata_c->r_lba >> 24) & 0x0f), 1554 ata_c->r_lba & 0xff, 1555 ata_c->r_count & 0xff, 1556 ata_c->r_features & 0xff); 1557 } 1558 1559 if ((ata_c->flags & AT_POLL) == 0) { 1560 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1561 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1562 wdctimeout, chp); 1563 return; 1564 } 1565 /* 1566 * Polled command. Wait for drive ready or drq. Done in intr(). 1567 * Wait for at last 400ns for status bit to be valid. 1568 */ 1569 delay(10); /* 400ns delay */ 1570 mvsata_wdc_cmd_intr(chp, xfer, 0); 1571 } 1572 1573 static int 1574 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1575 { 1576 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1577 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1578 struct ata_command *ata_c = xfer->c_cmd; 1579 int bcount = ata_c->bcount; 1580 char *data = ata_c->data; 1581 int wflags; 1582 int drive_flags; 1583 1584 if (ata_c->r_command == WDCC_IDENTIFY || 1585 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1586 /* 1587 * The IDENTIFY data has been designed as an array of 1588 * u_int16_t, so we can byteswap it on the fly. 1589 * Historically it's what we have always done so keeping it 1590 * here ensure binary backward compatibility. 1591 */ 1592 drive_flags = DRIVE_NOSTREAM | 1593 chp->ch_drive[xfer->c_drive].drive_flags; 1594 else 1595 /* 1596 * Other data structure are opaque and should be transfered 1597 * as is. 1598 */ 1599 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1600 1601 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1602 /* both wait and poll, we can tsleep here */ 1603 wflags = AT_WAIT | AT_POLL; 1604 else 1605 wflags = AT_POLL; 1606 1607 again: 1608 DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n", 1609 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1610 1611 /* 1612 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1613 * Reselect again, it doesn't hurt for others commands, and the time 1614 * penalty for the extra register write is acceptable, 1615 * wdc_exec_command() isn't called often (mostly for autoconfig) 1616 */ 1617 if ((xfer->c_flags & C_ATAPI) != 0) { 1618 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1619 } 1620 if ((ata_c->flags & AT_XFDONE) != 0) { 1621 /* 1622 * We have completed a data xfer. The drive should now be 1623 * in its initial state 1624 */ 1625 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1626 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1627 wflags) == WDCWAIT_TOUT) { 1628 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1629 return 0; /* IRQ was not for us */ 1630 ata_c->flags |= AT_TIMEOU; 1631 } 1632 goto out; 1633 } 1634 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1635 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1636 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1637 return 0; /* IRQ was not for us */ 1638 ata_c->flags |= AT_TIMEOU; 1639 goto out; 1640 } 1641 if (ata_c->flags & AT_READ) { 1642 if ((chp->ch_status & WDCS_DRQ) == 0) { 1643 ata_c->flags |= AT_TIMEOU; 1644 goto out; 1645 } 1646 wdc->datain_pio(chp, drive_flags, data, bcount); 1647 /* at this point the drive should be in its initial state */ 1648 ata_c->flags |= AT_XFDONE; 1649 /* 1650 * XXX checking the status register again here cause some 1651 * hardware to timeout. 1652 */ 1653 } else if (ata_c->flags & AT_WRITE) { 1654 if ((chp->ch_status & WDCS_DRQ) == 0) { 1655 ata_c->flags |= AT_TIMEOU; 1656 goto out; 1657 } 1658 wdc->dataout_pio(chp, drive_flags, data, bcount); 1659 ata_c->flags |= AT_XFDONE; 1660 if ((ata_c->flags & AT_POLL) == 0) { 1661 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */ 1662 callout_reset(&chp->ch_callout, 1663 mstohz(ata_c->timeout), wdctimeout, chp); 1664 return 1; 1665 } else 1666 goto again; 1667 } 1668 out: 1669 mvsata_wdc_cmd_done(chp, xfer); 1670 return 1; 1671 } 1672 1673 static void 1674 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1675 int reason) 1676 { 1677 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1678 struct ata_command *ata_c = xfer->c_cmd; 1679 1680 DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1681 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1682 1683 switch (reason) { 1684 case KILL_GONE: 1685 ata_c->flags |= AT_GONE; 1686 break; 1687 case KILL_RESET: 1688 ata_c->flags |= AT_RESET; 1689 break; 1690 default: 1691 aprint_error_dev(MVSATA_DEV2(mvport), 1692 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1693 panic("mvsata_cmd_kill_xfer"); 1694 } 1695 mvsata_wdc_cmd_done_end(chp, xfer); 1696 } 1697 1698 static void 1699 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1700 { 1701 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1702 struct atac_softc *atac = chp->ch_atac; 1703 struct ata_command *ata_c = xfer->c_cmd; 1704 1705 DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1706 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1707 ata_c->flags)); 1708 1709 if (chp->ch_status & WDCS_DWF) 1710 ata_c->flags |= AT_DF; 1711 if (chp->ch_status & WDCS_ERR) { 1712 ata_c->flags |= AT_ERROR; 1713 ata_c->r_error = chp->ch_error; 1714 } 1715 if ((ata_c->flags & AT_READREG) != 0 && 1716 device_is_active(atac->atac_dev) && 1717 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1718 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1719 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1720 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1721 ata_c->r_lba = 1722 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1723 ata_c->r_lba |= 1724 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1725 ata_c->r_lba |= 1726 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1727 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1728 if ((ata_c->flags & AT_LBA48) != 0) { 1729 if ((ata_c->flags & AT_POLL) != 0) { 1730 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1731 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1732 } else { 1733 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1734 WDCTL_HOB|WDCTL_4BIT); 1735 } 1736 ata_c->r_count |= 1737 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1738 ata_c->r_lba = 1739 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1740 ata_c->r_lba |= 1741 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1742 ata_c->r_lba |= 1743 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1744 if ((ata_c->flags & AT_POLL) != 0) { 1745 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1746 WDCTL_4BIT|WDCTL_IDS); 1747 } else { 1748 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1749 WDCTL_4BIT); 1750 } 1751 } else { 1752 ata_c->r_lba |= 1753 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1754 } 1755 } 1756 callout_stop(&chp->ch_callout); 1757 chp->ch_queue->active_xfer = NULL; 1758 if (ata_c->flags & AT_POLL) { 1759 /* enable interrupts */ 1760 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1761 delay(10); /* some drives need a little delay here */ 1762 } 1763 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1764 mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE); 1765 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1766 wakeup(&chp->ch_queue->active_xfer); 1767 } else 1768 mvsata_wdc_cmd_done_end(chp, xfer); 1769 } 1770 1771 static void 1772 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1773 { 1774 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1775 struct ata_command *ata_c = xfer->c_cmd; 1776 1777 /* EDMA restart, if enabled */ 1778 if (mvport->port_edmamode != nodma) { 1779 mvsata_edma_reset_qptr(mvport); 1780 mvsata_edma_enable(mvport); 1781 } 1782 1783 ata_c->flags |= AT_DONE; 1784 ata_free_xfer(chp, xfer); 1785 if (ata_c->flags & AT_WAIT) 1786 wakeup(ata_c); 1787 else if (ata_c->callback) 1788 ata_c->callback(ata_c->callback_arg); 1789 atastart(chp); 1790 1791 return; 1792 } 1793 1794 #if NATAPIBUS > 0 1795 static void 1796 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1797 { 1798 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 1799 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1800 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1801 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1802 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1803 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1804 const char *errstring; 1805 1806 DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 1807 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1808 xfer->c_drive, sc_xfer->xs_control)); 1809 1810 if (mvport->port_edmamode != nodma) 1811 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1812 1813 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 1814 drvp->n_xfers++; 1815 1816 /* Do control operations specially. */ 1817 if (__predict_false(drvp->state < READY)) { 1818 /* If it's not a polled command, we need the kernel thread */ 1819 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) { 1820 chp->ch_queue->queue_freeze++; 1821 wakeup(&chp->ch_thread); 1822 return; 1823 } 1824 /* 1825 * disable interrupts, all commands here should be quick 1826 * enough to be able to poll, and we don't go here that often 1827 */ 1828 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1829 1830 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1831 /* Don't try to set mode if controller can't be adjusted */ 1832 if (atac->atac_set_modes == NULL) 1833 goto ready; 1834 /* Also don't try if the drive didn't report its mode */ 1835 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1836 goto ready; 1837 errstring = "unbusy"; 1838 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) 1839 goto timeout; 1840 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1841 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1842 errstring = "piomode"; 1843 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1844 goto timeout; 1845 if (chp->ch_status & WDCS_ERR) { 1846 if (chp->ch_error == WDCE_ABRT) { 1847 /* 1848 * Some ATAPI drives reject PIO settings. 1849 * Fall back to PIO mode 3 since that's the 1850 * minimum for ATAPI. 1851 */ 1852 aprint_error_dev(atac->atac_dev, 1853 "channel %d drive %d: PIO mode %d rejected," 1854 " falling back to PIO mode 3\n", 1855 chp->ch_channel, xfer->c_drive, 1856 drvp->PIO_mode); 1857 if (drvp->PIO_mode > 3) 1858 drvp->PIO_mode = 3; 1859 } else 1860 goto error; 1861 } 1862 if (drvp->drive_flags & DRIVE_UDMA) 1863 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1864 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1865 else 1866 if (drvp->drive_flags & DRIVE_DMA) 1867 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1868 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1869 else 1870 goto ready; 1871 errstring = "dmamode"; 1872 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1873 goto timeout; 1874 if (chp->ch_status & WDCS_ERR) { 1875 if (chp->ch_error == WDCE_ABRT) { 1876 if (drvp->drive_flags & DRIVE_UDMA) 1877 goto error; 1878 else { 1879 /* 1880 * The drive rejected our DMA setting. 1881 * Fall back to mode 1. 1882 */ 1883 aprint_error_dev(atac->atac_dev, 1884 "channel %d drive %d:" 1885 " DMA mode %d rejected," 1886 " falling back to DMA mode 0\n", 1887 chp->ch_channel, xfer->c_drive, 1888 drvp->DMA_mode); 1889 if (drvp->DMA_mode > 0) 1890 drvp->DMA_mode = 0; 1891 } 1892 } else 1893 goto error; 1894 } 1895 ready: 1896 drvp->state = READY; 1897 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1898 delay(10); /* some drives need a little delay here */ 1899 } 1900 /* start timeout machinery */ 1901 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 1902 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1903 wdctimeout, chp); 1904 1905 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1906 switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) { 1907 case WDCWAIT_OK: 1908 break; 1909 case WDCWAIT_TOUT: 1910 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 1911 chp->ch_status); 1912 sc_xfer->error = XS_TIMEOUT; 1913 mvsata_atapi_reset(chp, xfer); 1914 return; 1915 case WDCWAIT_THR: 1916 return; 1917 } 1918 1919 /* 1920 * Even with WDCS_ERR, the device should accept a command packet 1921 * Limit length to what can be stuffed into the cylinder register 1922 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 1923 * but not all devices do that and it's not obvious from the 1924 * ATAPI spec that that behaviour should be expected. If more 1925 * data is necessary, multiple data transfer phases will be done. 1926 */ 1927 1928 wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD, 1929 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 1930 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1931 1932 /* 1933 * If there is no interrupt for CMD input, busy-wait for it (done in 1934 * the interrupt routine. If it is a polled command, call the interrupt 1935 * routine until command is done. 1936 */ 1937 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 1938 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) { 1939 /* Wait for at last 400ns for status bit to be valid */ 1940 DELAY(1); 1941 mvsata_atapi_intr(chp, xfer, 0); 1942 } else 1943 chp->ch_flags |= ATACH_IRQ_WAIT; 1944 if (sc_xfer->xs_control & XS_CTL_POLL) { 1945 if (chp->ch_flags & ATACH_DMA_WAIT) { 1946 wdc_dmawait(chp, xfer, sc_xfer->timeout); 1947 chp->ch_flags &= ~ATACH_DMA_WAIT; 1948 } 1949 while ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1950 /* Wait for at last 400ns for status bit to be valid */ 1951 DELAY(1); 1952 mvsata_atapi_intr(chp, xfer, 0); 1953 } 1954 } 1955 return; 1956 1957 timeout: 1958 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 1959 chp->ch_channel, xfer->c_drive, errstring); 1960 sc_xfer->error = XS_TIMEOUT; 1961 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1962 delay(10); /* some drives need a little delay here */ 1963 mvsata_atapi_reset(chp, xfer); 1964 return; 1965 1966 error: 1967 aprint_error_dev(atac->atac_dev, 1968 "channel %d drive %d: %s error (0x%x)\n", 1969 chp->ch_channel, xfer->c_drive, errstring, chp->ch_error); 1970 sc_xfer->error = XS_SHORTSENSE; 1971 sc_xfer->sense.atapi_sense = chp->ch_error; 1972 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1973 delay(10); /* some drives need a little delay here */ 1974 mvsata_atapi_reset(chp, xfer); 1975 return; 1976 } 1977 1978 static int 1979 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1980 { 1981 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1982 struct atac_softc *atac = chp->ch_atac; 1983 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1984 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1985 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1986 int len, phase, ire, error, retries=0, i; 1987 void *cmd; 1988 1989 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n", 1990 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1991 1992 /* Is it not a transfer, but a control operation? */ 1993 if (drvp->state < READY) { 1994 aprint_error_dev(atac->atac_dev, 1995 "channel %d drive %d: bad state %d\n", 1996 chp->ch_channel, xfer->c_drive, drvp->state); 1997 panic("mvsata_atapi_intr: bad state"); 1998 } 1999 /* 2000 * If we missed an interrupt in a PIO transfer, reset and restart. 2001 * Don't try to continue transfer, we may have missed cycles. 2002 */ 2003 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2004 sc_xfer->error = XS_TIMEOUT; 2005 mvsata_atapi_reset(chp, xfer); 2006 return 1; 2007 } 2008 2009 /* Ack interrupt done in wdc_wait_for_unbusy */ 2010 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2011 if (wdc_wait_for_unbusy(chp, 2012 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) { 2013 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 2014 return 0; /* IRQ was not for us */ 2015 aprint_error_dev(atac->atac_dev, 2016 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2017 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2018 if (xfer->c_flags & C_DMA) 2019 ata_dmaerr(drvp, 2020 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2021 sc_xfer->error = XS_TIMEOUT; 2022 mvsata_atapi_reset(chp, xfer); 2023 return 1; 2024 } 2025 2026 /* 2027 * If we missed an IRQ and were using DMA, flag it as a DMA error 2028 * and reset device. 2029 */ 2030 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2031 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2032 sc_xfer->error = XS_RESET; 2033 mvsata_atapi_reset(chp, xfer); 2034 return (1); 2035 } 2036 /* 2037 * if the request sense command was aborted, report the short sense 2038 * previously recorded, else continue normal processing 2039 */ 2040 2041 again: 2042 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2043 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2044 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2045 phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ); 2046 DPRINTF(( 2047 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2048 xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire)); 2049 2050 switch (phase) { 2051 case PHASE_CMDOUT: 2052 cmd = sc_xfer->cmd; 2053 DPRINTF(("PHASE_CMDOUT\n")); 2054 /* Init the DMA channel if necessary */ 2055 if (xfer->c_flags & C_DMA) { 2056 error = mvsata_bdma_init(mvport, sc_xfer, 2057 (char *)xfer->c_databuf + xfer->c_skip); 2058 if (error) { 2059 if (error == EINVAL) { 2060 /* 2061 * We can't do DMA on this transfer 2062 * for some reason. Fall back to PIO. 2063 */ 2064 xfer->c_flags &= ~C_DMA; 2065 error = 0; 2066 } else { 2067 sc_xfer->error = XS_DRIVER_STUFFUP; 2068 break; 2069 } 2070 } 2071 } 2072 2073 /* send packet command */ 2074 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2075 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2076 2077 /* Start the DMA channel if necessary */ 2078 if (xfer->c_flags & C_DMA) { 2079 mvsata_bdma_start(mvport); 2080 chp->ch_flags |= ATACH_DMA_WAIT; 2081 } 2082 2083 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2084 chp->ch_flags |= ATACH_IRQ_WAIT; 2085 return 1; 2086 2087 case PHASE_DATAOUT: 2088 /* write data */ 2089 DPRINTF(("PHASE_DATAOUT\n")); 2090 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2091 (xfer->c_flags & C_DMA) != 0) { 2092 aprint_error_dev(atac->atac_dev, 2093 "channel %d drive %d: bad data phase DATAOUT\n", 2094 chp->ch_channel, xfer->c_drive); 2095 if (xfer->c_flags & C_DMA) 2096 ata_dmaerr(drvp, 2097 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2098 sc_xfer->error = XS_TIMEOUT; 2099 mvsata_atapi_reset(chp, xfer); 2100 return 1; 2101 } 2102 xfer->c_lenoff = len - xfer->c_bcount; 2103 if (xfer->c_bcount < len) { 2104 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2105 " warning: write only %d of %d requested bytes\n", 2106 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2107 len); 2108 len = xfer->c_bcount; 2109 } 2110 2111 wdc->dataout_pio(chp, drvp->drive_flags, 2112 (char *)xfer->c_databuf + xfer->c_skip, len); 2113 2114 for (i = xfer->c_lenoff; i > 0; i -= 2) 2115 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2116 2117 xfer->c_skip += len; 2118 xfer->c_bcount -= len; 2119 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2120 chp->ch_flags |= ATACH_IRQ_WAIT; 2121 return 1; 2122 2123 case PHASE_DATAIN: 2124 /* Read data */ 2125 DPRINTF(("PHASE_DATAIN\n")); 2126 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2127 (xfer->c_flags & C_DMA) != 0) { 2128 aprint_error_dev(atac->atac_dev, 2129 "channel %d drive %d: bad data phase DATAIN\n", 2130 chp->ch_channel, xfer->c_drive); 2131 if (xfer->c_flags & C_DMA) 2132 ata_dmaerr(drvp, 2133 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2134 sc_xfer->error = XS_TIMEOUT; 2135 mvsata_atapi_reset(chp, xfer); 2136 return 1; 2137 } 2138 xfer->c_lenoff = len - xfer->c_bcount; 2139 if (xfer->c_bcount < len) { 2140 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2141 " warning: reading only %d of %d bytes\n", 2142 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2143 len); 2144 len = xfer->c_bcount; 2145 } 2146 2147 wdc->datain_pio(chp, drvp->drive_flags, 2148 (char *)xfer->c_databuf + xfer->c_skip, len); 2149 2150 if (xfer->c_lenoff > 0) 2151 wdcbit_bucket(chp, len - xfer->c_bcount); 2152 2153 xfer->c_skip += len; 2154 xfer->c_bcount -= len; 2155 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2156 chp->ch_flags |= ATACH_IRQ_WAIT; 2157 return 1; 2158 2159 case PHASE_ABORTED: 2160 case PHASE_COMPLETED: 2161 DPRINTF(("PHASE_COMPLETED\n")); 2162 if (xfer->c_flags & C_DMA) 2163 xfer->c_bcount -= sc_xfer->datalen; 2164 sc_xfer->resid = xfer->c_bcount; 2165 mvsata_atapi_phase_complete(xfer); 2166 return 1; 2167 2168 default: 2169 if (++retries<500) { 2170 DELAY(100); 2171 chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 2172 chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 2173 goto again; 2174 } 2175 aprint_error_dev(atac->atac_dev, 2176 "channel %d drive %d: unknown phase 0x%x\n", 2177 chp->ch_channel, xfer->c_drive, phase); 2178 if (chp->ch_status & WDCS_ERR) { 2179 sc_xfer->error = XS_SHORTSENSE; 2180 sc_xfer->sense.atapi_sense = chp->ch_error; 2181 } else { 2182 if (xfer->c_flags & C_DMA) 2183 ata_dmaerr(drvp, 2184 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2185 sc_xfer->error = XS_RESET; 2186 mvsata_atapi_reset(chp, xfer); 2187 return (1); 2188 } 2189 } 2190 DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x " 2191 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense)); 2192 mvsata_atapi_done(chp, xfer); 2193 return 1; 2194 } 2195 2196 static void 2197 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2198 int reason) 2199 { 2200 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2201 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2202 2203 /* remove this command from xfer queue */ 2204 switch (reason) { 2205 case KILL_GONE: 2206 sc_xfer->error = XS_DRIVER_STUFFUP; 2207 break; 2208 2209 case KILL_RESET: 2210 sc_xfer->error = XS_RESET; 2211 break; 2212 2213 default: 2214 aprint_error_dev(MVSATA_DEV2(mvport), 2215 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2216 panic("mvsata_atapi_kill_xfer"); 2217 } 2218 ata_free_xfer(chp, xfer); 2219 scsipi_done(sc_xfer); 2220 } 2221 2222 static void 2223 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2224 { 2225 struct atac_softc *atac = chp->ch_atac; 2226 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2227 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2228 2229 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 2230 drvp->state = 0; 2231 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) { 2232 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2233 chp->ch_channel, xfer->c_drive); 2234 sc_xfer->error = XS_SELTIMEOUT; 2235 } 2236 mvsata_atapi_done(chp, xfer); 2237 return; 2238 } 2239 2240 static void 2241 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2242 { 2243 struct ata_channel *chp = xfer->c_chp; 2244 struct atac_softc *atac = chp->ch_atac; 2245 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2246 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2247 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2248 2249 /* wait for DSC if needed */ 2250 if (drvp->drive_flags & DRIVE_ATAPIST) { 2251 DPRINTFN(1, 2252 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2253 device_xname(atac->atac_dev), chp->ch_channel, 2254 xfer->c_drive, xfer->c_dscpoll)); 2255 if (cold) 2256 panic("mvsata_atapi_phase_complete: cold"); 2257 2258 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) == 2259 WDCWAIT_TOUT) { 2260 /* 10ms not enough, try again in 1 tick */ 2261 if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) { 2262 aprint_error_dev(atac->atac_dev, 2263 "channel %d: wait_for_dsc failed\n", 2264 chp->ch_channel); 2265 sc_xfer->error = XS_TIMEOUT; 2266 mvsata_atapi_reset(chp, xfer); 2267 return; 2268 } else 2269 callout_reset(&chp->ch_callout, 1, 2270 mvsata_atapi_polldsc, xfer); 2271 return; 2272 } 2273 } 2274 2275 /* 2276 * Some drive occasionally set WDCS_ERR with 2277 * "ATA illegal length indication" in the error 2278 * register. If we read some data the sense is valid 2279 * anyway, so don't report the error. 2280 */ 2281 if (chp->ch_status & WDCS_ERR && 2282 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2283 sc_xfer->resid == sc_xfer->datalen)) { 2284 /* save the short sense */ 2285 sc_xfer->error = XS_SHORTSENSE; 2286 sc_xfer->sense.atapi_sense = chp->ch_error; 2287 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2288 /* ask scsipi to send a REQUEST_SENSE */ 2289 sc_xfer->error = XS_BUSY; 2290 sc_xfer->status = SCSI_CHECK; 2291 } else 2292 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2293 ata_dmaerr(drvp, 2294 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2295 sc_xfer->error = XS_RESET; 2296 mvsata_atapi_reset(chp, xfer); 2297 return; 2298 } 2299 } 2300 if (xfer->c_bcount != 0) 2301 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:" 2302 " bcount value is %d after io\n", 2303 device_xname(atac->atac_dev), chp->ch_channel, 2304 xfer->c_drive, xfer->c_bcount)); 2305 #ifdef DIAGNOSTIC 2306 if (xfer->c_bcount < 0) 2307 aprint_error_dev(atac->atac_dev, 2308 "channel %d drive %d: mvsata_atapi_intr:" 2309 " warning: bcount value is %d after io\n", 2310 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2311 #endif 2312 2313 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:" 2314 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2315 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2316 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2317 mvsata_atapi_done(chp, xfer); 2318 } 2319 2320 static void 2321 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2322 { 2323 struct atac_softc *atac = chp->ch_atac; 2324 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2325 int drive = xfer->c_drive; 2326 2327 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2328 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2329 (u_int)xfer->c_flags)); 2330 callout_stop(&chp->ch_callout); 2331 /* mark controller inactive and free the command */ 2332 chp->ch_queue->active_xfer = NULL; 2333 ata_free_xfer(chp, xfer); 2334 2335 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 2336 sc_xfer->error = XS_DRIVER_STUFFUP; 2337 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 2338 wakeup(&chp->ch_queue->active_xfer); 2339 } 2340 2341 DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2342 device_xname(atac->atac_dev), chp->ch_channel)); 2343 scsipi_done(sc_xfer); 2344 DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2345 device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags)); 2346 atastart(chp); 2347 } 2348 2349 static void 2350 mvsata_atapi_polldsc(void *arg) 2351 { 2352 2353 mvsata_atapi_phase_complete(arg); 2354 } 2355 #endif /* NATAPIBUS > 0 */ 2356 2357 2358 /* 2359 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2360 * if supported queuing command by atabus? The race condition will not happen 2361 * if this is called only to the thread of atabus. 2362 */ 2363 static int 2364 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio, 2365 void *databuf) 2366 { 2367 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2368 struct ata_channel *chp = &mvport->port_ata_channel; 2369 struct eprd *eprd; 2370 bus_addr_t crqb_base_addr; 2371 bus_dmamap_t data_dmamap; 2372 uint32_t reg; 2373 int quetag, erqqip, erqqop, next, rv, i; 2374 2375 DPRINTFN(2, ("%s:%d:%d: mvsata_edma_enqueue:" 2376 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2377 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2378 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2379 2380 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2381 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2382 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2383 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2384 next = erqqip; 2385 MVSATA_EDMAQ_INC(next); 2386 if (next == erqqop) 2387 /* queue full */ 2388 return EBUSY; 2389 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2390 /* tag nothing */ 2391 return EBUSY; 2392 DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag)); 2393 2394 rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes, 2395 ata_bio->flags); 2396 if (rv != 0) 2397 return rv; 2398 2399 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2400 KASSERT(chp->ch_queue->active_xfer != NULL); 2401 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2402 2403 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2404 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2405 eprd = mvport->port_reqtbl[quetag].eprd; 2406 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2407 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2408 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2409 2410 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2411 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2412 eprd->eot = htole16(0); 2413 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2414 eprd++; 2415 } 2416 (eprd - 1)->eot |= htole16(EPRD_EOT); 2417 #ifdef MVSATA_DEBUG 2418 if (mvsata_debug >= 3) 2419 mvsata_print_eprd(mvport, quetag); 2420 #endif 2421 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2422 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2423 BUS_DMASYNC_PREWRITE); 2424 2425 /* setup EDMA Command Request Block (CRQB) Data */ 2426 sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio); 2427 #ifdef MVSATA_DEBUG 2428 if (mvsata_debug >= 3) 2429 mvsata_print_crqb(mvport, erqqip); 2430 #endif 2431 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2432 erqqip * sizeof(union mvsata_crqb), 2433 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2434 2435 MVSATA_EDMAQ_INC(erqqip); 2436 2437 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2438 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2439 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2440 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2441 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2442 2443 return 0; 2444 } 2445 2446 static int 2447 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2448 { 2449 struct ata_channel *chp = &mvport->port_ata_channel; 2450 struct crpb *crpb; 2451 struct ata_bio *ata_bio; 2452 struct ata_xfer *xfer; 2453 uint32_t reg; 2454 int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2455 2456 /* First, Sync for Request Queue buffer */ 2457 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2458 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2459 if (mvport->port_prev_erqqop != erqqop) { 2460 const int s = sizeof(union mvsata_crqb); 2461 2462 if (mvport->port_prev_erqqop < erqqop) 2463 n = erqqop - mvport->port_prev_erqqop; 2464 else { 2465 if (erqqop > 0) 2466 bus_dmamap_sync(mvport->port_dmat, 2467 mvport->port_crqb_dmamap, 0, erqqop * s, 2468 BUS_DMASYNC_POSTWRITE); 2469 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2470 } 2471 if (n > 0) 2472 bus_dmamap_sync(mvport->port_dmat, 2473 mvport->port_crqb_dmamap, 2474 mvport->port_prev_erqqop * s, n * s, 2475 BUS_DMASYNC_POSTWRITE); 2476 mvport->port_prev_erqqop = erqqop; 2477 } 2478 2479 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2480 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2481 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2482 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2483 2484 DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2485 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2486 mvport->port, erpqip, erpqop)); 2487 2488 if (erpqop == erpqip) 2489 return 0; 2490 2491 if (erpqop < erpqip) 2492 n = erpqip - erpqop; 2493 else { 2494 if (erpqip > 0) 2495 bus_dmamap_sync(mvport->port_dmat, 2496 mvport->port_crpb_dmamap, 2497 0, erpqip * sizeof(struct crpb), 2498 BUS_DMASYNC_POSTREAD); 2499 n = MVSATA_EDMAQ_LEN - erpqop; 2500 } 2501 if (n > 0) 2502 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2503 erpqop * sizeof(struct crpb), 2504 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2505 2506 prev_erpqop = erpqop; 2507 while (erpqop != erpqip) { 2508 #ifdef MVSATA_DEBUG 2509 if (mvsata_debug >= 3) 2510 mvsata_print_crpb(mvport, erpqop); 2511 #endif 2512 crpb = mvport->port_crpb + erpqop; 2513 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2514 KASSERT(chp->ch_queue->active_xfer != NULL); 2515 xfer = chp->ch_queue->active_xfer; 2516 KASSERT(xfer == mvport->port_reqtbl[quetag].xfer); 2517 #ifdef DIAGNOSTIC 2518 if (xfer == NULL) 2519 panic("unknown response received: %s:%d:%d: tag 0x%x\n", 2520 device_xname(MVSATA_DEV2(mvport)), 2521 mvport->port_hc->hc, mvport->port, quetag); 2522 #endif 2523 2524 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2525 mvport->port_reqtbl[quetag].eprd_offset, 2526 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2527 2528 chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2529 chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2530 ata_bio = xfer->c_cmd; 2531 ata_bio->error = NOERROR; 2532 ata_bio->r_error = 0; 2533 if (chp->ch_status & WDCS_ERR) 2534 ata_bio->error = ERROR; 2535 if (chp->ch_status & WDCS_BSY) 2536 ata_bio->error = TIMEOUT; 2537 if (chp->ch_error) 2538 ata_bio->error = ERR_DMA; 2539 2540 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2541 mvport->port_reqtbl[quetag].xfer = NULL; 2542 mvsata_quetag_put(mvport, quetag); 2543 MVSATA_EDMAQ_INC(erpqop); 2544 2545 #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */ 2546 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2547 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2548 if (erpqop == erqqip) 2549 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2550 #endif 2551 mvsata_bio_intr(chp, xfer, 1); 2552 if (xfer1 == NULL) 2553 handled++; 2554 else if (xfer == xfer1) { 2555 handled = 1; 2556 break; 2557 } 2558 } 2559 if (prev_erpqop < erpqop) 2560 n = erpqop - prev_erpqop; 2561 else { 2562 if (erpqop > 0) 2563 bus_dmamap_sync(mvport->port_dmat, 2564 mvport->port_crpb_dmamap, 0, 2565 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2566 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2567 } 2568 if (n > 0) 2569 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2570 prev_erpqop * sizeof(struct crpb), 2571 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2572 2573 reg &= ~EDMA_RESQP_ERPQP_MASK; 2574 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2575 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2576 2577 #if 0 /* already cleared ago? */ 2578 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2579 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2580 if (erpqop == erqqip) 2581 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2582 #endif 2583 2584 return handled; 2585 } 2586 2587 static int 2588 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2589 { 2590 struct ata_bio *ata_bio = xfer->c_cmd; 2591 int xtime; 2592 2593 for (xtime = 0; xtime < timeout / 10; xtime++) { 2594 if (mvsata_edma_handle(mvport, xfer)) 2595 return 0; 2596 if (ata_bio->flags & ATA_NOSLEEP) 2597 delay(10000); 2598 else 2599 tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10)); 2600 } 2601 2602 DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer)); 2603 mvsata_edma_rqq_remove(mvport, xfer); 2604 xfer->c_flags |= C_TIMEOU; 2605 return 1; 2606 } 2607 2608 static void 2609 mvsata_edma_timeout(void *arg) 2610 { 2611 struct ata_xfer *xfer = (struct ata_xfer *)arg; 2612 struct ata_channel *chp = xfer->c_chp; 2613 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2614 int s; 2615 2616 s = splbio(); 2617 DPRINTF(("mvsata_edma_timeout: %p\n", xfer)); 2618 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 2619 mvsata_edma_rqq_remove(mvport, xfer); 2620 xfer->c_flags |= C_TIMEOU; 2621 mvsata_bio_intr(chp, xfer, 1); 2622 } 2623 splx(s); 2624 } 2625 2626 static void 2627 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2628 { 2629 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2630 struct ata_bio *ata_bio; 2631 bus_addr_t crqb_base_addr; 2632 int erqqip, i; 2633 2634 /* First, hardware reset, stop EDMA */ 2635 mvsata_hreset_port(mvport); 2636 2637 /* cleanup completed EDMA safely */ 2638 mvsata_edma_handle(mvport, NULL); 2639 2640 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2641 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2642 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2643 if (mvport->port_reqtbl[i].xfer == NULL) 2644 continue; 2645 2646 ata_bio = mvport->port_reqtbl[i].xfer->c_cmd; 2647 if (mvport->port_reqtbl[i].xfer == xfer) { 2648 /* remove xfer from EDMA request queue */ 2649 bus_dmamap_sync(mvport->port_dmat, 2650 mvport->port_eprd_dmamap, 2651 mvport->port_reqtbl[i].eprd_offset, 2652 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2653 mvsata_dma_bufunload(mvport, i, ata_bio->flags); 2654 mvport->port_reqtbl[i].xfer = NULL; 2655 mvsata_quetag_put(mvport, i); 2656 continue; 2657 } 2658 2659 sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio); 2660 erqqip++; 2661 } 2662 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2663 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2664 BUS_DMASYNC_POSTWRITE); 2665 2666 mvsata_edma_config(mvport, mvport->port_edmamode); 2667 mvsata_edma_reset_qptr(mvport); 2668 mvsata_edma_enable(mvport); 2669 2670 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2671 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2672 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2673 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2674 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2675 } 2676 2677 #if NATAPIBUS > 0 2678 static int 2679 mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer, 2680 void *databuf) 2681 { 2682 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2683 struct eprd *eprd; 2684 bus_dmamap_t data_dmamap; 2685 bus_addr_t eprd_addr; 2686 int quetag, rv; 2687 2688 DPRINTFN(2, 2689 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2690 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2691 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2692 2693 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2694 /* tag nothing */ 2695 return EBUSY; 2696 DPRINTFN(2, (" quetag=%d\n", quetag)); 2697 2698 rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen, 2699 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2700 if (rv != 0) 2701 return rv; 2702 2703 KASSERT(chp->ch_queue->active_xfer != NULL); 2704 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2705 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2706 2707 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2708 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2709 eprd = mvport->port_reqtbl[quetag].eprd; 2710 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2711 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2712 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2713 2714 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2715 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2716 eprd->eot = htole16(0); 2717 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2718 eprd++; 2719 } 2720 (eprd - 1)->eot |= htole16(EPRD_EOT); 2721 #ifdef MVSATA_DEBUG 2722 if (mvsata_debug >= 3) 2723 mvsata_print_eprd(mvport, quetag); 2724 #endif 2725 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2726 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2727 BUS_DMASYNC_PREWRITE); 2728 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2729 mvport->port_reqtbl[quetag].eprd_offset; 2730 2731 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2732 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2733 2734 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2735 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2736 else 2737 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2738 2739 return 0; 2740 } 2741 2742 static void 2743 mvsata_bdma_start(struct mvsata_port *mvport) 2744 { 2745 2746 #ifdef MVSATA_DEBUG 2747 if (mvsata_debug >= 3) 2748 mvsata_print_eprd(mvport, 0); 2749 #endif 2750 2751 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2752 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2753 } 2754 #endif 2755 #endif 2756 2757 2758 static int 2759 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2760 { 2761 struct mvsata_softc *sc = mvhc->hc_sc; 2762 struct mvsata_port *mvport; 2763 struct ata_channel *chp; 2764 int channel, rv, i; 2765 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2766 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2767 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2768 2769 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2770 M_ZERO | M_NOWAIT); 2771 if (mvport == NULL) { 2772 aprint_error("%s:%d: can't allocate memory for port %d\n", 2773 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2774 return ENOMEM; 2775 } 2776 2777 mvport->port = port; 2778 mvport->port_hc = mvhc; 2779 mvport->port_edmamode = nodma; 2780 2781 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2782 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 2783 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 2784 if (rv != 0) { 2785 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 2786 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2787 goto fail0; 2788 } 2789 mvport->port_iot = mvhc->hc_iot; 2790 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 2791 &mvport->port_sata_sstatus); 2792 if (rv != 0) { 2793 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 2794 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2795 goto fail0; 2796 } 2797 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 2798 &mvport->port_sata_serror); 2799 if (rv != 0) { 2800 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 2801 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2802 goto fail0; 2803 } 2804 if (sc->sc_rev == gen1) 2805 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2806 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 2807 else 2808 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2809 SATA_SC, 4, &mvport->port_sata_scontrol); 2810 if (rv != 0) { 2811 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 2812 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2813 goto fail0; 2814 } 2815 mvport->port_dmat = sc->sc_dmat; 2816 #ifndef MVSATA_WITHOUTDMA 2817 mvsata_quetag_init(mvport); 2818 #endif 2819 mvhc->hc_ports[port] = mvport; 2820 2821 channel = mvhc->hc * sc->sc_port + port; 2822 chp = &mvport->port_ata_channel; 2823 chp->ch_channel = channel; 2824 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 2825 chp->ch_ndrive = 1; /* SATA is always 1 drive */ 2826 chp->ch_queue = &mvport->port_ata_queue; 2827 sc->sc_ata_channels[channel] = chp; 2828 2829 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 2830 if (rv != 0) 2831 goto fail0; 2832 2833 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 2834 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 2835 if (rv != 0) { 2836 aprint_error( 2837 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 2838 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2839 goto fail0; 2840 } 2841 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 2842 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 2843 if (rv != 0) { 2844 aprint_error( 2845 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 2846 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2847 goto fail1; 2848 } 2849 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 2850 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 2851 if (rv != 0) { 2852 aprint_error( 2853 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 2854 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2855 goto fail2; 2856 } 2857 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 2858 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 2859 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 2860 &mvport->port_reqtbl[i].data_dmamap); 2861 if (rv != 0) { 2862 aprint_error("%s:%d:%d:" 2863 " EDMA data map(%d) create failed: error=%d\n", 2864 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 2865 rv); 2866 goto fail3; 2867 } 2868 } 2869 2870 return 0; 2871 2872 fail3: 2873 for (i--; i >= 0; i--) 2874 bus_dmamap_destroy(mvport->port_dmat, 2875 mvport->port_reqtbl[i].data_dmamap); 2876 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 2877 fail2: 2878 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 2879 fail1: 2880 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 2881 fail0: 2882 return rv; 2883 } 2884 2885 static int 2886 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 2887 { 2888 int hc, port, rv, i; 2889 2890 hc = mvport->port_hc->hc; 2891 port = mvport->port; 2892 2893 /* Create subregion for Shadow Registers Map */ 2894 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2895 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 2896 if (rv != 0) { 2897 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 2898 device_xname(MVSATA_DEV2(mvport)), hc, port); 2899 return rv; 2900 } 2901 wdr->cmd_iot = mvport->port_iot; 2902 2903 /* Once create subregion for each command registers */ 2904 for (i = 0; i < WDC_NREG; i++) { 2905 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2906 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 2907 if (rv != 0) { 2908 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2909 device_xname(MVSATA_DEV2(mvport)), hc, port); 2910 return rv; 2911 } 2912 } 2913 /* Create subregion for Alternate Status register */ 2914 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2915 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 2916 if (rv != 0) { 2917 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2918 device_xname(MVSATA_DEV2(mvport)), hc, port); 2919 return rv; 2920 } 2921 wdr->ctl_iot = mvport->port_iot; 2922 2923 wdc_init_shadow_regs(&mvport->port_ata_channel); 2924 2925 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2926 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 2927 if (rv != 0) { 2928 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 2929 device_xname(MVSATA_DEV2(mvport)), hc, port); 2930 return rv; 2931 } 2932 wdr->sata_iot = mvport->port_iot; 2933 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2934 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 2935 if (rv != 0) { 2936 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 2937 device_xname(MVSATA_DEV2(mvport)), hc, port); 2938 return rv; 2939 } 2940 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2941 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 2942 if (rv != 0) { 2943 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 2944 device_xname(MVSATA_DEV2(mvport)), hc, port); 2945 return rv; 2946 } 2947 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2948 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 2949 if (rv != 0) { 2950 aprint_error("%s:%d:%d: couldn't subregion SError\n", 2951 device_xname(MVSATA_DEV2(mvport)), hc, port); 2952 return rv; 2953 } 2954 2955 return 0; 2956 } 2957 2958 2959 #ifndef MVSATA_WITHOUTDMA 2960 /* 2961 * There are functions to determine Host Queue Tag. 2962 * XXXX: We hope to rotate Tag to facilitate debugging. 2963 */ 2964 2965 static inline void 2966 mvsata_quetag_init(struct mvsata_port *mvport) 2967 { 2968 2969 mvport->port_quetagidx = 0; 2970 } 2971 2972 static inline int 2973 mvsata_quetag_get(struct mvsata_port *mvport) 2974 { 2975 int begin = mvport->port_quetagidx; 2976 2977 do { 2978 if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) { 2979 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2980 return mvport->port_quetagidx; 2981 } 2982 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2983 } while (mvport->port_quetagidx != begin); 2984 2985 return -1; 2986 } 2987 2988 static inline void 2989 mvsata_quetag_put(struct mvsata_port *mvport, int quetag) 2990 { 2991 2992 /* nothing */ 2993 } 2994 2995 static void * 2996 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 2997 bus_dmamap_t *dmamap, size_t size, int write) 2998 { 2999 bus_dma_segment_t seg; 3000 int nseg, rv; 3001 void *kva; 3002 3003 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3004 BUS_DMA_NOWAIT); 3005 if (rv != 0) { 3006 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3007 device_xname(MVSATA_DEV2(mvport)), 3008 mvport->port_hc->hc, mvport->port, rv); 3009 goto fail; 3010 } 3011 3012 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3013 if (rv != 0) { 3014 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3015 device_xname(MVSATA_DEV2(mvport)), 3016 mvport->port_hc->hc, mvport->port, rv); 3017 goto free; 3018 } 3019 3020 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3021 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3022 if (rv != 0) { 3023 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3024 device_xname(MVSATA_DEV2(mvport)), 3025 mvport->port_hc->hc, mvport->port, rv); 3026 goto unmap; 3027 } 3028 3029 if (!write) 3030 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3031 3032 return kva; 3033 3034 unmap: 3035 bus_dmamem_unmap(dmat, kva, size); 3036 free: 3037 bus_dmamem_free(dmat, &seg, nseg); 3038 fail: 3039 return NULL; 3040 } 3041 3042 /* ARGSUSED */ 3043 static void 3044 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3045 bus_dmamap_t dmamap, void *kva) 3046 { 3047 3048 bus_dmamap_unload(dmat, dmamap); 3049 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3050 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3051 } 3052 3053 static int 3054 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3055 size_t datalen, int flags) 3056 { 3057 int rv, lop, sop; 3058 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3059 3060 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3061 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3062 3063 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3064 NULL, BUS_DMA_NOWAIT | lop); 3065 if (rv) { 3066 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3067 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3068 mvport->port, rv); 3069 return rv; 3070 } 3071 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3072 data_dmamap->dm_mapsize, sop); 3073 3074 return 0; 3075 } 3076 3077 static inline void 3078 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3079 { 3080 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3081 3082 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3083 data_dmamap->dm_mapsize, 3084 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3085 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3086 } 3087 #endif 3088 3089 static void 3090 mvsata_hreset_port(struct mvsata_port *mvport) 3091 { 3092 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3093 3094 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3095 3096 delay(25); /* allow reset propagation */ 3097 3098 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3099 3100 mvport->_fix_phy_param._fix_phy(mvport); 3101 3102 if (sc->sc_gen == gen1) 3103 delay(1000); 3104 } 3105 3106 static void 3107 mvsata_reset_port(struct mvsata_port *mvport) 3108 { 3109 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3110 3111 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3112 3113 mvsata_hreset_port(mvport); 3114 3115 if (device_is_a(parent, "pci")) 3116 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3117 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3118 else /* SoC */ 3119 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3120 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3121 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3122 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3123 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3124 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3125 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3126 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3127 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3128 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3129 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3130 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3131 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3132 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3133 3134 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3135 } 3136 3137 static void 3138 mvsata_reset_hc(struct mvsata_hc *mvhc) 3139 { 3140 #if 0 3141 uint32_t val; 3142 #endif 3143 3144 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3145 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3146 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3147 3148 #if 0 /* XXXX needs? */ 3149 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3150 3151 /* 3152 * Keep the SS during power on and the reference clock bits (reset 3153 * sample) 3154 */ 3155 val = MVSATA_HC_READ_4(mvhc, 0x020); 3156 val &= 0x1c1c1c1c; 3157 val |= 0x03030303; 3158 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3159 #endif 3160 } 3161 3162 #ifndef MVSATA_WITHOUTDMA 3163 static void 3164 mvsata_softreset(struct mvsata_port *mvport, int waitok) 3165 { 3166 uint32_t stat; 3167 int i; 3168 3169 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS); 3170 delay(10); 3171 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS); 3172 delay(2000); 3173 3174 if (waitok) { 3175 /* wait maximum 31sec */ 3176 for (i = 31000; i > 0; i--) { 3177 stat = MVSATA_WDC_READ_1(mvport, SRB_CS); 3178 if (!(stat & WDCS_BSY)) 3179 break; 3180 delay(1000); 3181 } 3182 if (i == 0) 3183 aprint_error("%s:%d:%d: soft reset failed\n", 3184 device_xname(MVSATA_DEV2(mvport)), 3185 mvport->port_hc->hc, mvport->port); 3186 } 3187 } 3188 3189 static void 3190 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3191 { 3192 const bus_addr_t crpb_addr = 3193 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3194 const uint32_t crpb_addr_mask = 3195 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3196 3197 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3198 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3199 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3200 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3201 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3202 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3203 } 3204 3205 static inline void 3206 mvsata_edma_enable(struct mvsata_port *mvport) 3207 { 3208 3209 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3210 } 3211 3212 static int 3213 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok) 3214 { 3215 uint32_t status, command; 3216 int ms; 3217 3218 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3219 for (ms = 0; ms < timeout; ms++) { 3220 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3221 if (status & EDMA_S_EDMAIDLE) 3222 break; 3223 if (waitok) 3224 tsleep(&waitok, PRIBIO, "mvsata_edma1", 3225 mstohz(1)); 3226 else 3227 delay(1000); 3228 } 3229 if (ms == timeout) 3230 return EBUSY; 3231 3232 /* The diable bit (eDsEDMA) is self negated. */ 3233 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3234 3235 for ( ; ms < timeout; ms++) { 3236 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3237 if (!(command & EDMA_CMD_EENEDMA)) 3238 break; 3239 if (waitok) 3240 tsleep(&waitok, PRIBIO, "mvsata_edma2", 3241 mstohz(1)); 3242 else 3243 delay(1000); 3244 } 3245 if (ms == timeout) { 3246 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3247 device_xname(MVSATA_DEV2(mvport)), 3248 mvport->port_hc->hc, mvport->port); 3249 return EBUSY; 3250 } 3251 } 3252 return 0; 3253 } 3254 3255 /* 3256 * Set EDMA registers according to mode. 3257 * ex. NCQ/TCQ(queued)/non queued. 3258 */ 3259 static void 3260 mvsata_edma_config(struct mvsata_port *mvport, int mode) 3261 { 3262 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3263 uint32_t reg; 3264 3265 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3266 reg |= EDMA_CFG_RESERVED; 3267 3268 if (mode == ncq) { 3269 if (sc->sc_gen == gen1) { 3270 aprint_error_dev(MVSATA_DEV2(mvport), 3271 "GenI not support NCQ\n"); 3272 return; 3273 } else if (sc->sc_gen == gen2) 3274 reg |= EDMA_CFG_EDEVERR; 3275 reg |= EDMA_CFG_ESATANATVCMDQUE; 3276 } else if (mode == queued) { 3277 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3278 reg |= EDMA_CFG_EQUE; 3279 } else 3280 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3281 3282 if (sc->sc_gen == gen1) 3283 reg |= EDMA_CFG_ERDBSZ; 3284 else if (sc->sc_gen == gen2) 3285 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3286 else if (sc->sc_gen == gen2e) { 3287 device_t parent = device_parent(MVSATA_DEV(sc)); 3288 3289 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3290 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3291 3292 if (device_is_a(parent, "pci")) 3293 reg |= ( 3294 #if NATAPIBUS > 0 3295 EDMA_CFG_EEARLYCOMPLETIONEN | 3296 #endif 3297 EDMA_CFG_ECUTTHROUGHEN | 3298 EDMA_CFG_EWRBUFFERLEN | 3299 EDMA_CFG_ERDBSZEXT); 3300 } 3301 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3302 3303 reg = ( 3304 EDMA_IE_EIORDYERR | 3305 EDMA_IE_ETRANSINT | 3306 EDMA_IE_EDEVCON | 3307 EDMA_IE_EDEVDIS); 3308 if (sc->sc_gen != gen1) 3309 reg |= ( 3310 EDMA_IE_TRANSPROTERR | 3311 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3312 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3313 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3314 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3315 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3316 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3317 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3318 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3319 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3320 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3321 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3322 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3323 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3324 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3325 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3326 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3327 EDMA_IE_ESELFDIS); 3328 3329 if (mode == ncq) 3330 reg |= EDMA_IE_EDEVERR; 3331 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3332 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3333 reg &= ~EDMA_IE_EDEVERR; 3334 if (mode != ncq) 3335 reg |= EDMA_IE_EDEVERR; 3336 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3337 if (sc->sc_gen == gen2e) { 3338 /* 3339 * Clear FISWait4HostRdyEn[0] and [2]. 3340 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3341 * [2]: SDB FIS is received with <ERR> bit set to 1. 3342 */ 3343 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3344 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3345 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3346 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3347 } 3348 3349 mvport->port_edmamode = mode; 3350 } 3351 3352 3353 /* 3354 * Generation dependent functions 3355 */ 3356 3357 static void 3358 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag, 3359 struct ata_bio *ata_bio) 3360 { 3361 struct crqb *crqb; 3362 bus_addr_t eprd_addr; 3363 daddr_t blkno; 3364 uint32_t rw; 3365 uint8_t cmd, head; 3366 int i; 3367 const int drive = 3368 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3369 3370 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3371 mvport->port_reqtbl[quetag].eprd_offset; 3372 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3373 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3374 head = WDSD_LBA; 3375 blkno = ata_bio->blkno; 3376 if (ata_bio->flags & ATA_LBA48) 3377 cmd = atacmd_to48(cmd); 3378 else { 3379 head |= ((ata_bio->blkno >> 24) & 0xf); 3380 blkno &= 0xffffff; 3381 } 3382 crqb = &mvport->port_crqb->crqb + erqqip; 3383 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3384 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3385 crqb->ctrlflg = 3386 htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive)); 3387 i = 0; 3388 if (mvport->port_edmamode == dma) { 3389 if (ata_bio->flags & ATA_LBA48) 3390 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3391 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3392 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3393 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3394 } else { /* ncq/queued */ 3395 3396 /* 3397 * XXXX: Oops, ata command is not correct. And, atabus layer 3398 * has not been supported yet now. 3399 * Queued DMA read/write. 3400 * read/write FPDMAQueued. 3401 */ 3402 3403 if (ata_bio->flags & ATA_LBA48) 3404 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3405 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3406 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3407 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3408 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3409 CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3)); 3410 } 3411 if (ata_bio->flags & ATA_LBA48) { 3412 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3413 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3414 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3415 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3416 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3417 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3418 } 3419 crqb->atacommand[i++] = 3420 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3421 crqb->atacommand[i++] = 3422 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3423 crqb->atacommand[i++] = 3424 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3425 crqb->atacommand[i++] = 3426 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3427 crqb->atacommand[i++] = htole16( 3428 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3429 CRQB_ATACOMMAND_LAST); 3430 } 3431 #endif 3432 3433 static uint32_t 3434 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3435 { 3436 struct mvsata_hc *hc = mvport->port_hc; 3437 uint32_t reg; 3438 3439 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3440 /* 3441 * [12:11] : pre 3442 * [7:5] : amps 3443 */ 3444 return reg & 0x000018e0; 3445 } 3446 3447 static void 3448 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3449 { 3450 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3451 struct mvsata_hc *mvhc = mvport->port_hc; 3452 uint32_t reg; 3453 int port = mvport->port, fix_apm_sq = 0; 3454 3455 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3456 if (sc->sc_rev == 0x01) 3457 fix_apm_sq = 1; 3458 } else { 3459 if (sc->sc_rev == 0x00) 3460 fix_apm_sq = 1; 3461 } 3462 3463 if (fix_apm_sq) { 3464 /* 3465 * Disable auto-power management 3466 * 88SX50xx FEr SATA#12 3467 */ 3468 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3469 reg |= (1 << 19); 3470 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3471 3472 /* 3473 * Fix squelch threshold 3474 * 88SX50xx FEr SATA#9 3475 */ 3476 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3477 reg &= ~0x3; 3478 reg |= 0x1; 3479 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3480 } 3481 3482 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3483 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3484 reg &= ~0x000018e0; /* pre and amps mask */ 3485 reg |= mvport->_fix_phy_param.pre_amps; 3486 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3487 } 3488 3489 static void 3490 mvsata_devconn_gen1(struct mvsata_port *mvport) 3491 { 3492 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3493 3494 /* Fix for 88SX50xx FEr SATA#2 */ 3495 mvport->_fix_phy_param._fix_phy(mvport); 3496 3497 /* If disk is connected, then enable the activity LED */ 3498 if (sc->sc_rev == 0x03) { 3499 /* XXXXX */ 3500 } 3501 } 3502 3503 static uint32_t 3504 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3505 { 3506 uint32_t reg; 3507 3508 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3509 /* 3510 * [10:8] : amps 3511 * [7:5] : pre 3512 */ 3513 return reg & 0x000007e0; 3514 } 3515 3516 static void 3517 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3518 { 3519 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3520 uint32_t reg; 3521 3522 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3523 sc->sc_gen == gen2e) { 3524 /* 3525 * Fix for 3526 * 88SX60X1 FEr SATA #23 3527 * 88SX6042/88SX7042 FEr SATA #23 3528 * 88F5182 FEr #SATA-S13 3529 * 88F5082 FEr #SATA-S13 3530 */ 3531 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3532 reg &= ~(1 << 16); 3533 reg |= (1 << 31); 3534 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3535 3536 delay(200); 3537 3538 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3539 reg &= ~((1 << 16) | (1 << 31)); 3540 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3541 3542 delay(200); 3543 } 3544 3545 /* Fix values in PHY Mode 3 Register.*/ 3546 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3547 reg &= ~0x7F900000; 3548 reg |= 0x2A800000; 3549 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3550 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3551 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3552 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3553 reg &= ~0x0000001c; 3554 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3555 3556 /* 3557 * Fix values in PHY Mode 4 Register. 3558 * 88SX60x1 FEr SATA#10 3559 * 88F5182 GL #SATA-S10 3560 * 88F5082 GL #SATA-S10 3561 */ 3562 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3563 sc->sc_gen == gen2e) { 3564 uint32_t tmp = 0; 3565 3566 /* 88SX60x1 FEr SATA #13 */ 3567 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3568 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3569 3570 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3571 reg |= (1 << 0); 3572 reg &= ~(1 << 1); 3573 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3574 if (sc->sc_gen == gen2e) { 3575 reg &= ~0x5de3fffc; 3576 reg |= (1 << 2); 3577 } 3578 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3579 3580 /* 88SX60x1 FEr SATA #13 */ 3581 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3582 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3583 } 3584 3585 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3586 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3587 reg &= ~0x000007e0; /* pre and amps mask */ 3588 reg |= mvport->_fix_phy_param.pre_amps; 3589 reg &= ~(1 << 16); 3590 if (sc->sc_gen == gen2e) { 3591 /* 3592 * according to mvSata 3.6.1, some IIE values are fixed. 3593 * some reserved fields must be written with fixed values. 3594 */ 3595 reg &= ~0xC30FF01F; 3596 reg |= 0x0000900F; 3597 } 3598 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3599 } 3600 3601 #ifndef MVSATA_WITHOUTDMA 3602 static void 3603 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag, 3604 struct ata_bio *ata_bio) 3605 { 3606 struct crqb_gen2e *crqb; 3607 bus_addr_t eprd_addr; 3608 daddr_t blkno; 3609 uint32_t ctrlflg, rw; 3610 uint8_t cmd, head; 3611 const int drive = 3612 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3613 3614 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3615 mvport->port_reqtbl[quetag].eprd_offset; 3616 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3617 ctrlflg = (rw | CRQB_CDEVICEQUETAG(quetag) | CRQB_CPMPORT(drive) | 3618 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag)); 3619 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3620 head = WDSD_LBA; 3621 blkno = ata_bio->blkno; 3622 if (ata_bio->flags & ATA_LBA48) 3623 cmd = atacmd_to48(cmd); 3624 else { 3625 head |= ((ata_bio->blkno >> 24) & 0xf); 3626 blkno &= 0xffffff; 3627 } 3628 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3629 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3630 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3631 crqb->ctrlflg = htole32(ctrlflg); 3632 if (mvport->port_edmamode == dma) { 3633 crqb->atacommand[0] = htole32(cmd << 16); 3634 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3635 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff)); 3636 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3637 } else { /* ncq/queued */ 3638 3639 /* 3640 * XXXX: Oops, ata command is not correct. And, atabus layer 3641 * has not been supported yet now. 3642 * Queued DMA read/write. 3643 * read/write FPDMAQueued. 3644 */ 3645 3646 crqb->atacommand[0] = htole32( 3647 (cmd << 16) | ((ata_bio->nblks & 0xff) << 24)); 3648 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3649 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) | 3650 ((ata_bio->nblks >> 8) & 0xff)); 3651 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3652 crqb->atacommand[3] = htole32(quetag << 3); 3653 } 3654 } 3655 3656 3657 #ifdef MVSATA_DEBUG 3658 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3659 do { \ 3660 int _i; \ 3661 u_char *_p = (p); \ 3662 \ 3663 printf(#type "(%d)", (n)); \ 3664 for (_i = 0; _i < (size); _i++, _p++) { \ 3665 if (_i % 16 == 0) \ 3666 printf("\n "); \ 3667 printf(" %02x", *_p); \ 3668 } \ 3669 printf("\n"); \ 3670 } while (0 /* CONSTCOND */) 3671 3672 static void 3673 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3674 { 3675 3676 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3677 n, (u_char *)(mvport->port_crqb + n)); 3678 } 3679 3680 static void 3681 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3682 { 3683 3684 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3685 n, (u_char *)(mvport->port_crpb + n)); 3686 } 3687 3688 static void 3689 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3690 { 3691 struct eprd *eprd; 3692 int i = 0; 3693 3694 eprd = mvport->port_reqtbl[n].eprd; 3695 while (1 /*CONSTCOND*/) { 3696 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3697 i, (u_char *)eprd); 3698 if (eprd->eot & EPRD_EOT) 3699 break; 3700 eprd++; 3701 i++; 3702 } 3703 } 3704 #endif 3705 #endif 3706
Indexes created Wed Sep 24 02:09:48 GMT 2025