mvsata.c revision 1.16
1 /* $NetBSD: mvsata.c,v 1.16 2012/04/20 20:23:20 bouyer Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.16 2012/04/20 20:23:20 bouyer Exp $"); 30 31 #include "opt_mvsata.h" 32 33 /* ATAPI implementation not finished. Also don't work shadow registers? */ 34 //#include "atapibus.h" 35 36 #include <sys/param.h> 37 #if NATAPIBUS > 0 38 #include <sys/buf.h> 39 #endif 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/disklabel.h> 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 49 #include <machine/vmparam.h> 50 51 #include <dev/ata/atareg.h> 52 #include <dev/ata/atavar.h> 53 #include <dev/ic/wdcvar.h> 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 57 #if NATAPIBUS > 0 58 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 59 #endif 60 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ic/mvsatareg.h> 64 #include <dev/ic/mvsatavar.h> 65 66 67 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 68 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 69 70 #define MVSATA_HC_READ_4(hc, reg) \ 71 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 72 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 73 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 74 #define MVSATA_EDMA_READ_4(mvport, reg) \ 75 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 76 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 77 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 78 #define MVSATA_WDC_READ_2(mvport, reg) \ 79 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, (reg)) 80 #define MVSATA_WDC_READ_1(mvport, reg) \ 81 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, (reg)) 82 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 83 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 84 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 85 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 86 87 #ifdef MVSATA_DEBUG 88 #define DPRINTF(x) if (mvsata_debug) printf x 89 #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x 90 int mvsata_debug = 2; 91 #else 92 #define DPRINTF(x) 93 #define DPRINTFN(n,x) 94 #endif 95 96 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 97 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 98 sending a cmd */ 99 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 100 101 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 102 103 104 #ifndef MVSATA_WITHOUTDMA 105 static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *); 106 static void mvsata_reset_drive(struct ata_drive_datas *, int); 107 static void mvsata_reset_channel(struct ata_channel *, int); 108 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *); 109 static int mvsata_addref(struct ata_drive_datas *); 110 static void mvsata_delref(struct ata_drive_datas *); 111 static void mvsata_killpending(struct ata_drive_datas *); 112 113 #if NATAPIBUS > 0 114 static void mvsata_atapibus_attach(struct atabus_softc *); 115 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 116 scsipi_adapter_req_t, void *); 117 static void mvsata_atapi_minphys(struct buf *); 118 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 119 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 120 #endif 121 #endif 122 123 static void mvsata_setup_channel(struct ata_channel *); 124 125 #ifndef MVSATA_WITHOUTDMA 126 static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 127 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 128 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 129 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 130 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 131 int); 132 static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 133 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 134 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 135 int); 136 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 137 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 138 #if NATAPIBUS > 0 139 static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 140 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 141 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 142 int); 143 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 144 static void mvsata_atapi_phase_complete(struct ata_xfer *); 145 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_atapi_polldsc(void *); 147 #endif 148 149 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_bio *, void *); 150 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 151 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 152 static void mvsata_edma_timeout(void *); 153 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 154 #if NATAPIBUS > 0 155 static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *); 156 static void mvsata_bdma_start(struct mvsata_port *); 157 #endif 158 #endif 159 160 static int mvsata_port_init(struct mvsata_hc *, int); 161 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 162 #ifndef MVSATA_WITHOUTDMA 163 static inline void mvsata_quetag_init(struct mvsata_port *); 164 static inline int mvsata_quetag_get(struct mvsata_port *); 165 static inline void mvsata_quetag_put(struct mvsata_port *, int); 166 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 167 bus_dmamap_t *, size_t, int); 168 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 169 bus_dmamap_t, void *); 170 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 171 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 172 #endif 173 174 static void mvsata_hreset_port(struct mvsata_port *); 175 static void mvsata_reset_port(struct mvsata_port *); 176 static void mvsata_reset_hc(struct mvsata_hc *); 177 #ifndef MVSATA_WITHOUTDMA 178 static void mvsata_softreset(struct mvsata_port *, int); 179 static void mvsata_edma_reset_qptr(struct mvsata_port *); 180 static inline void mvsata_edma_enable(struct mvsata_port *); 181 static int mvsata_edma_disable(struct mvsata_port *, int, int); 182 static void mvsata_edma_config(struct mvsata_port *, int); 183 184 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int, 185 struct ata_bio *); 186 #endif 187 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 188 static void mvsata_fix_phy_gen1(struct mvsata_port *); 189 static void mvsata_devconn_gen1(struct mvsata_port *); 190 191 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 192 static void mvsata_fix_phy_gen2(struct mvsata_port *); 193 #ifndef MVSATA_WITHOUTDMA 194 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int, 195 struct ata_bio *); 196 197 #ifdef MVSATA_DEBUG 198 static void mvsata_print_crqb(struct mvsata_port *, int); 199 static void mvsata_print_crpb(struct mvsata_port *, int); 200 static void mvsata_print_eprd(struct mvsata_port *, int); 201 #endif 202 203 204 struct ata_bustype mvsata_ata_bustype = { 205 SCSIPI_BUSTYPE_ATA, 206 mvsata_bio, 207 mvsata_reset_drive, 208 mvsata_reset_channel, 209 mvsata_exec_command, 210 ata_get_params, 211 mvsata_addref, 212 mvsata_delref, 213 mvsata_killpending 214 }; 215 216 #if NATAPIBUS > 0 217 static const struct scsipi_bustype mvsata_atapi_bustype = { 218 SCSIPI_BUSTYPE_ATAPI, 219 atapi_scsipi_cmd, 220 atapi_interpret_sense, 221 atapi_print_addr, 222 mvsata_atapi_kill_pending, 223 NULL, 224 }; 225 #endif /* NATAPIBUS */ 226 #endif 227 228 229 int 230 mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product, 231 int (*mvsata_sreset)(struct mvsata_softc *), 232 int (*mvsata_misc_reset)(struct mvsata_softc *), 233 int read_pre_amps) 234 { 235 struct mvsata_hc *mvhc; 236 struct mvsata_port *mvport; 237 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 238 void (*_fix_phy)(struct mvsata_port *) = NULL; 239 #ifndef MVSATA_WITHOUTDMA 240 void (*edma_setup_crqb) 241 (struct mvsata_port *, int, int, struct ata_bio *) = NULL; 242 #endif 243 int hc, port, channel; 244 245 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 246 (product->generation == gen1) ? "I" : 247 ((product->generation == gen2) ? "II" : "IIe"), 248 product->hc, product->port); 249 250 251 switch (product->generation) { 252 case gen1: 253 mvsata_sreset = NULL; 254 read_pre_amps = 1; /* MUST */ 255 read_preamps = mvsata_read_preamps_gen1; 256 _fix_phy = mvsata_fix_phy_gen1; 257 #ifndef MVSATA_WITHOUTDMA 258 edma_setup_crqb = mvsata_edma_setup_crqb; 259 #endif 260 break; 261 262 case gen2: 263 read_preamps = mvsata_read_preamps_gen2; 264 _fix_phy = mvsata_fix_phy_gen2; 265 #ifndef MVSATA_WITHOUTDMA 266 edma_setup_crqb = mvsata_edma_setup_crqb; 267 #endif 268 break; 269 270 case gen2e: 271 read_preamps = mvsata_read_preamps_gen2; 272 _fix_phy = mvsata_fix_phy_gen2; 273 #ifndef MVSATA_WITHOUTDMA 274 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 275 #endif 276 break; 277 } 278 279 sc->sc_gen = product->generation; 280 sc->sc_hc = product->hc; 281 sc->sc_port = product->port; 282 sc->sc_flags = product->flags; 283 284 #ifdef MVSATA_WITHOUTDMA 285 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 286 #else 287 sc->sc_edma_setup_crqb = edma_setup_crqb; 288 sc->sc_wdcdev.sc_atac.atac_cap |= 289 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 290 #endif 291 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 292 #ifdef MVSATA_WITHOUTDMA 293 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 295 #else 296 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 297 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 298 #endif 299 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 300 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 301 #ifndef MVSATA_WITHOUTDMA 302 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 303 #if NATAPIBUS > 0 304 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 305 #endif 306 #endif 307 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 308 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 309 310 sc->sc_wdc_regs = 311 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 312 M_DEVBUF, M_NOWAIT); 313 if (sc->sc_wdc_regs == NULL) { 314 aprint_error_dev(MVSATA_DEV(sc), 315 "can't allocate wdc regs memory\n"); 316 return ENOMEM; 317 } 318 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 319 320 for (hc = 0; hc < sc->sc_hc; hc++) { 321 mvhc = &sc->sc_hcs[hc]; 322 mvhc->hc = hc; 323 mvhc->hc_sc = sc; 324 mvhc->hc_iot = sc->sc_iot; 325 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 326 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 327 &mvhc->hc_ioh)) { 328 aprint_error_dev(MVSATA_DEV(sc), 329 "can't subregion SATAHC %d registers\n", hc); 330 continue; 331 } 332 333 for (port = 0; port < sc->sc_port; port++) 334 if (mvsata_port_init(mvhc, port) == 0) { 335 int pre_amps; 336 337 mvport = mvhc->hc_ports[port]; 338 pre_amps = read_pre_amps ? 339 read_preamps(mvport) : 0x00000720; 340 mvport->_fix_phy_param.pre_amps = pre_amps; 341 mvport->_fix_phy_param._fix_phy = _fix_phy; 342 343 if (!mvsata_sreset) 344 mvsata_reset_port(mvport); 345 } 346 347 if (!mvsata_sreset) 348 mvsata_reset_hc(mvhc); 349 } 350 if (mvsata_sreset) 351 mvsata_sreset(sc); 352 353 if (mvsata_misc_reset) 354 mvsata_misc_reset(sc); 355 356 for (hc = 0; hc < sc->sc_hc; hc++) 357 for (port = 0; port < sc->sc_port; port++) { 358 mvport = sc->sc_hcs[hc].hc_ports[port]; 359 if (mvport == NULL) 360 continue; 361 if (mvsata_sreset) 362 mvport->_fix_phy_param._fix_phy(mvport); 363 } 364 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 365 wdcattach(sc->sc_ata_channels[channel]); 366 367 return 0; 368 } 369 370 int 371 mvsata_intr(struct mvsata_hc *mvhc) 372 { 373 struct mvsata_softc *sc = mvhc->hc_sc; 374 struct mvsata_port *mvport; 375 uint32_t cause; 376 int port, handled = 0; 377 378 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 379 380 DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n", 381 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 382 383 if (cause & SATAHC_IC_SAINTCOAL) 384 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 385 cause &= ~SATAHC_IC_SAINTCOAL; 386 for (port = 0; port < sc->sc_port; port++) { 387 mvport = mvhc->hc_ports[port]; 388 389 if (cause & SATAHC_IC_DONE(port)) { 390 #ifndef MVSATA_WITHOUTDMA 391 handled = mvsata_edma_handle(mvport, NULL); 392 #endif 393 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 394 ~SATAHC_IC_DONE(port)); 395 } 396 397 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 398 wdcintr(&mvport->port_ata_channel); 399 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 400 ~SATAHC_IC_SADEVINTERRUPT(port)); 401 handled = 1; 402 } 403 } 404 405 return handled; 406 } 407 408 int 409 mvsata_error(struct mvsata_port *mvport) 410 { 411 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 412 uint32_t cause; 413 int handled = 0; 414 415 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 416 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 417 418 DPRINTFN(3, ("%s:%d:%d:" 419 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 420 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 421 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 422 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 423 424 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 425 if (!cause) 426 return 0; 427 428 /* If PM connected, connect/disconnect interrupts storm could happen */ 429 if (MVSATA_EDMA_READ_4(mvport, EDMA_IEC) & 430 (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) 431 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 432 delay(20 * 1000); 433 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 434 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 435 } 436 437 if (cause & EDMA_IE_EDEVDIS) 438 aprint_normal("%s:%d:%d: device disconnect\n", 439 device_xname(MVSATA_DEV2(mvport)), 440 mvport->port_hc->hc, mvport->port); 441 if (cause & EDMA_IE_EDEVCON) { 442 if (sc->sc_gen == gen1) 443 mvsata_devconn_gen1(mvport); 444 445 DPRINTFN(3, (" device connected\n")); 446 handled = 1; 447 } 448 #ifndef MVSATA_WITHOUTDMA 449 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 450 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 451 switch (mvport->port_edmamode) { 452 case dma: 453 case queued: 454 case ncq: 455 mvsata_edma_reset_qptr(mvport); 456 mvsata_edma_enable(mvport); 457 if (cause & EDMA_IE_EDEVERR) 458 break; 459 460 /* FALLTHROUGH */ 461 462 case nodma: 463 default: 464 aprint_error( 465 "%s:%d:%d: EDMA self disable happen 0x%x\n", 466 device_xname(MVSATA_DEV2(mvport)), 467 mvport->port_hc->hc, mvport->port, cause); 468 break; 469 } 470 handled = 1; 471 } 472 #endif 473 if (cause & EDMA_IE_ETRANSINT) { 474 /* hot plug the Port Multiplier */ 475 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 476 device_xname(MVSATA_DEV2(mvport)), 477 mvport->port_hc->hc, mvport->port); 478 } 479 480 return handled; 481 } 482 483 484 /* 485 * ATA callback entry points 486 */ 487 488 #ifndef MVSATA_WITHOUTDMA 489 static int 490 mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 491 { 492 struct ata_channel *chp = drvp->chnl_softc; 493 struct atac_softc *atac = chp->ch_atac; 494 struct ata_xfer *xfer; 495 496 DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 497 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 498 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 499 500 xfer = ata_get_xfer(ATAXF_NOSLEEP); 501 if (xfer == NULL) 502 return ATACMD_TRY_AGAIN; 503 if (atac->atac_cap & ATAC_CAP_NOIRQ) 504 ata_bio->flags |= ATA_POLL; 505 if (ata_bio->flags & ATA_POLL) 506 xfer->c_flags |= C_POLL; 507 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 508 (ata_bio->flags & ATA_SINGLE) == 0) 509 xfer->c_flags |= C_DMA; 510 xfer->c_drive = drvp->drive; 511 xfer->c_cmd = ata_bio; 512 xfer->c_databuf = ata_bio->databuf; 513 xfer->c_bcount = ata_bio->bcount; 514 xfer->c_start = mvsata_bio_start; 515 xfer->c_intr = mvsata_bio_intr; 516 xfer->c_kill_xfer = mvsata_bio_kill_xfer; 517 ata_exec_xfer(chp, xfer); 518 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 519 } 520 521 static void 522 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags) 523 { 524 struct ata_channel *chp = drvp->chnl_softc; 525 struct mvsata_port *mvport = (struct mvsata_port *)chp; 526 uint32_t edma_c; 527 528 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 529 530 DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 531 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 532 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 533 534 if (edma_c & EDMA_CMD_EENEDMA) 535 mvsata_edma_disable(mvport, 10000, flags & AT_WAIT); 536 537 mvsata_softreset(mvport, flags & AT_WAIT); 538 539 if (edma_c & EDMA_CMD_EENEDMA) { 540 mvsata_edma_reset_qptr(mvport); 541 mvsata_edma_enable(mvport); 542 } 543 return; 544 } 545 546 static void 547 mvsata_reset_channel(struct ata_channel *chp, int flags) 548 { 549 struct mvsata_port *mvport = (struct mvsata_port *)chp; 550 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 551 struct ata_xfer *xfer; 552 uint32_t sstat, ctrl; 553 int i; 554 555 DPRINTF(("%s: mvsata_reset_channel: channel=%d\n", 556 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 557 558 mvsata_hreset_port(mvport); 559 sstat = sata_reset_interface(chp, mvport->port_iot, 560 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 561 562 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 563 sc->sc_gen != gen1) { 564 /* Downgrade to GenI */ 565 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 566 SControl_DET_DISABLE; 567 568 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 569 570 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 571 ctrl &= ~(1 << 17); /* Disable GenII */ 572 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 573 574 mvsata_hreset_port(mvport); 575 sata_reset_interface(chp, mvport->port_iot, 576 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 577 } 578 579 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 580 xfer = mvport->port_reqtbl[i].xfer; 581 if (xfer == NULL) 582 continue; 583 chp->ch_queue->active_xfer = xfer; 584 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 585 } 586 587 mvsata_edma_config(mvport, mvport->port_edmamode); 588 mvsata_edma_reset_qptr(mvport); 589 mvsata_edma_enable(mvport); 590 return; 591 } 592 593 594 static int 595 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 596 { 597 struct ata_channel *chp = drvp->chnl_softc; 598 #ifdef MVSATA_DEBUG 599 struct mvsata_port *mvport = (struct mvsata_port *)chp; 600 #endif 601 struct ata_xfer *xfer; 602 int rv, s; 603 604 DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 605 " r_command=0x%x, r_head=0x%x, r_cyl=0x%x, r_sector=0x%x," 606 " r_count=0x%x, r_features=0x%x\n", 607 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 608 drvp->drive, ata_c->bcount, ata_c->r_command, ata_c->r_head, 609 ata_c->r_cyl, ata_c->r_sector, ata_c->r_count, ata_c->r_features)); 610 611 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 612 ATAXF_NOSLEEP); 613 if (xfer == NULL) 614 return ATACMD_TRY_AGAIN; 615 if (ata_c->flags & AT_POLL) 616 xfer->c_flags |= C_POLL; 617 if (ata_c->flags & AT_WAIT) 618 xfer->c_flags |= C_WAIT; 619 xfer->c_drive = drvp->drive; 620 xfer->c_databuf = ata_c->data; 621 xfer->c_bcount = ata_c->bcount; 622 xfer->c_cmd = ata_c; 623 xfer->c_start = mvsata_wdc_cmd_start; 624 xfer->c_intr = mvsata_wdc_cmd_intr; 625 xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer; 626 s = splbio(); 627 ata_exec_xfer(chp, xfer); 628 #ifdef DIAGNOSTIC 629 if ((ata_c->flags & AT_POLL) != 0 && 630 (ata_c->flags & AT_DONE) == 0) 631 panic("mvsata_exec_command: polled command not done"); 632 #endif 633 if (ata_c->flags & AT_DONE) 634 rv = ATACMD_COMPLETE; 635 else { 636 if (ata_c->flags & AT_WAIT) { 637 while ((ata_c->flags & AT_DONE) == 0) 638 tsleep(ata_c, PRIBIO, "mvsatacmd", 0); 639 rv = ATACMD_COMPLETE; 640 } else 641 rv = ATACMD_QUEUED; 642 } 643 splx(s); 644 return rv; 645 } 646 647 static int 648 mvsata_addref(struct ata_drive_datas *drvp) 649 { 650 651 return 0; 652 } 653 654 static void 655 mvsata_delref(struct ata_drive_datas *drvp) 656 { 657 658 return; 659 } 660 661 static void 662 mvsata_killpending(struct ata_drive_datas *drvp) 663 { 664 665 return; 666 } 667 668 #if NATAPIBUS > 0 669 static void 670 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 671 { 672 struct ata_channel *chp = ata_sc->sc_chan; 673 struct atac_softc *atac = chp->ch_atac; 674 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 675 struct scsipi_channel *chan = &chp->ch_atapi_channel; 676 677 /* 678 * Fill in the scsipi_adapter. 679 */ 680 adapt->adapt_dev = atac->atac_dev; 681 adapt->adapt_nchannels = atac->atac_nchannels; 682 adapt->adapt_request = mvsata_atapi_scsipi_request; 683 adapt->adapt_minphys = mvsata_atapi_minphys; 684 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 685 686 /* 687 * Fill in the scsipi_channel. 688 */ 689 memset(chan, 0, sizeof(*chan)); 690 chan->chan_adapter = adapt; 691 chan->chan_bustype = &mvsata_atapi_bustype; 692 chan->chan_channel = chp->ch_channel; 693 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 694 chan->chan_openings = 1; 695 chan->chan_max_periph = 1; 696 chan->chan_ntargets = 1; 697 chan->chan_nluns = 1; 698 699 chp->atapibus = 700 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 701 } 702 703 static void 704 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 705 scsipi_adapter_req_t req, void *arg) 706 { 707 struct scsipi_adapter *adapt = chan->chan_adapter; 708 struct scsipi_periph *periph; 709 struct scsipi_xfer *sc_xfer; 710 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 711 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 712 struct ata_xfer *xfer; 713 int channel = chan->chan_channel; 714 int drive, s; 715 716 switch (req) { 717 case ADAPTER_REQ_RUN_XFER: 718 sc_xfer = arg; 719 periph = sc_xfer->xs_periph; 720 drive = periph->periph_target; 721 722 if (!device_is_active(atac->atac_dev)) { 723 sc_xfer->error = XS_DRIVER_STUFFUP; 724 scsipi_done(sc_xfer); 725 return; 726 } 727 xfer = ata_get_xfer(ATAXF_NOSLEEP); 728 if (xfer == NULL) { 729 sc_xfer->error = XS_RESOURCE_SHORTAGE; 730 scsipi_done(sc_xfer); 731 return; 732 } 733 734 if (sc_xfer->xs_control & XS_CTL_POLL) 735 xfer->c_flags |= C_POLL; 736 xfer->c_drive = drive; 737 xfer->c_flags |= C_ATAPI; 738 xfer->c_cmd = sc_xfer; 739 xfer->c_databuf = sc_xfer->data; 740 xfer->c_bcount = sc_xfer->datalen; 741 xfer->c_start = mvsata_atapi_start; 742 xfer->c_intr = mvsata_atapi_intr; 743 xfer->c_kill_xfer = mvsata_atapi_kill_xfer; 744 xfer->c_dscpoll = 0; 745 s = splbio(); 746 ata_exec_xfer(atac->atac_channels[channel], xfer); 747 #ifdef DIAGNOSTIC 748 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 749 (sc_xfer->xs_status & XS_STS_DONE) == 0) 750 panic("mvsata_atapi_scsipi_request:" 751 " polled command not done"); 752 #endif 753 splx(s); 754 return; 755 756 default: 757 /* Not supported, nothing to do. */ 758 ; 759 } 760 } 761 762 static void 763 mvsata_atapi_minphys(struct buf *bp) 764 { 765 766 if (bp->b_bcount > MAXPHYS) 767 bp->b_bcount = MAXPHYS; 768 minphys(bp); 769 } 770 771 static void 772 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 773 { 774 struct scsipi_channel *chan = sc->sc_channel; 775 struct scsipi_periph *periph; 776 struct ataparams ids; 777 struct ataparams *id = &ids; 778 struct mvsata_softc *mvc = 779 device_private(chan->chan_adapter->adapt_dev); 780 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 781 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 782 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 783 struct scsipibus_attach_args sa; 784 char serial_number[21], model[41], firmware_revision[9]; 785 int s; 786 787 /* skip if already attached */ 788 if (scsipi_lookup_periph(chan, target, 0) != NULL) 789 return; 790 791 /* if no ATAPI device detected at attach time, skip */ 792 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 793 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 794 " drive %d not present\n", 795 device_xname(atac->atac_dev), chp->ch_channel, target)); 796 return; 797 } 798 799 /* Some ATAPI devices need a bit more time after software reset. */ 800 delay(5000); 801 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 802 #ifdef ATAPI_DEBUG_PROBE 803 log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n", 804 device_xname(atac->atac_dev), chp->ch_channel, target, 805 id->atap_config & ATAPI_CFG_CMD_MASK, 806 id->atap_config & ATAPI_CFG_DRQ_MASK); 807 #endif 808 periph = scsipi_alloc_periph(M_NOWAIT); 809 if (periph == NULL) { 810 aprint_error_dev(atac->atac_dev, 811 "unable to allocate periph" 812 " for channel %d drive %d\n", 813 chp->ch_channel, target); 814 return; 815 } 816 periph->periph_dev = NULL; 817 periph->periph_channel = chan; 818 periph->periph_switch = &atapi_probe_periphsw; 819 periph->periph_target = target; 820 periph->periph_lun = 0; 821 periph->periph_quirks = PQUIRK_ONLYBIG; 822 823 #ifdef SCSIPI_DEBUG 824 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 825 SCSIPI_DEBUG_TARGET == target) 826 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 827 #endif 828 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 829 if (id->atap_config & ATAPI_CFG_REMOV) 830 periph->periph_flags |= PERIPH_REMOVABLE; 831 if (periph->periph_type == T_SEQUENTIAL) { 832 s = splbio(); 833 drvp->drive_flags |= DRIVE_ATAPIST; 834 splx(s); 835 } 836 837 sa.sa_periph = periph; 838 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 839 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 840 T_REMOV : T_FIXED; 841 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 842 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 20); 843 scsipi_strvis((u_char *)firmware_revision, 8, id->atap_revision, 844 8); 845 sa.sa_inqbuf.vendor = model; 846 sa.sa_inqbuf.product = serial_number; 847 sa.sa_inqbuf.revision = firmware_revision; 848 849 /* 850 * Determine the operating mode capabilities of the device. 851 */ 852 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 853 periph->periph_cap |= PERIPH_CAP_CMD16; 854 /* XXX This is gross. */ 855 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 856 857 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 858 859 if (drvp->drv_softc) 860 ata_probe_caps(drvp); 861 else { 862 s = splbio(); 863 drvp->drive_flags &= ~DRIVE_ATAPI; 864 splx(s); 865 } 866 } else { 867 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 868 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n", 869 device_xname(atac->atac_dev), chp->ch_channel, target, 870 chp->ch_error)); 871 s = splbio(); 872 drvp->drive_flags &= ~DRIVE_ATAPI; 873 splx(s); 874 } 875 } 876 877 /* 878 * Kill off all pending xfers for a periph. 879 * 880 * Must be called at splbio(). 881 */ 882 static void 883 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 884 { 885 struct atac_softc *atac = 886 device_private(periph->periph_channel->chan_adapter->adapt_dev); 887 struct ata_channel *chp = 888 atac->atac_channels[periph->periph_channel->chan_channel]; 889 890 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 891 } 892 #endif /* NATAPIBUS > 0 */ 893 #endif /* MVSATA_WITHOUTDMA */ 894 895 896 /* 897 * mvsata_setup_channel() 898 * Setup EDMA registers and prepare/purge DMA resources. 899 * We assuming already stopped the EDMA. 900 */ 901 static void 902 mvsata_setup_channel(struct ata_channel *chp) 903 { 904 #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG) 905 struct mvsata_port *mvport = (struct mvsata_port *)chp; 906 #endif 907 struct ata_drive_datas *drvp; 908 uint32_t edma_mode; 909 int drive, s; 910 #ifndef MVSATA_WITHOUTDMA 911 int i; 912 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 913 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 914 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 915 #endif 916 917 DPRINTF(("%s:%d: mvsata_setup_channel: ", 918 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 919 920 edma_mode = nodma; 921 for (drive = 0; drive < chp->ch_ndrive; drive++) { 922 drvp = &chp->ch_drive[drive]; 923 924 /* If no drive, skip */ 925 if (!(drvp->drive_flags & DRIVE)) 926 continue; 927 928 if (drvp->drive_flags & DRIVE_UDMA) { 929 /* use Ultra/DMA */ 930 s = splbio(); 931 drvp->drive_flags &= ~DRIVE_DMA; 932 splx(s); 933 } 934 935 if (drvp->drive_flags & (DRIVE_UDMA | DRIVE_DMA)) 936 if (drvp->drive_flags & DRIVE_ATA) 937 edma_mode = dma; 938 } 939 940 DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 941 942 #ifndef MVSATA_WITHOUTDMA 943 if (edma_mode == nodma) { 944 no_edma: 945 if (mvport->port_crqb != NULL) 946 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 947 mvport->port_crqb_dmamap, mvport->port_crqb); 948 if (mvport->port_crpb != NULL) 949 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 950 mvport->port_crpb_dmamap, mvport->port_crpb); 951 if (mvport->port_eprd != NULL) 952 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 953 mvport->port_eprd_dmamap, mvport->port_eprd); 954 955 return; 956 } 957 958 if (mvport->port_crqb == NULL) 959 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 960 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 961 if (mvport->port_crpb == NULL) 962 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 963 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 964 if (mvport->port_eprd == NULL) { 965 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 966 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 967 1); 968 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 969 mvport->port_reqtbl[i].eprd_offset = 970 i * MVSATA_EPRD_MAX_SIZE; 971 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 972 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 973 } 974 } 975 976 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 977 mvport->port_eprd == NULL) { 978 aprint_error_dev(MVSATA_DEV2(mvport), 979 "channel %d: can't use EDMA\n", chp->ch_channel); 980 s = splbio(); 981 for (drive = 0; drive < chp->ch_ndrive; drive++) { 982 drvp = &chp->ch_drive[drive]; 983 984 /* If no drive, skip */ 985 if (!(drvp->drive_flags & DRIVE)) 986 continue; 987 988 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 989 } 990 splx(s); 991 goto no_edma; 992 } 993 994 mvsata_edma_config(mvport, edma_mode); 995 mvsata_edma_reset_qptr(mvport); 996 mvsata_edma_enable(mvport); 997 #endif 998 } 999 1000 #ifndef MVSATA_WITHOUTDMA 1001 static void 1002 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1003 { 1004 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1005 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1006 struct atac_softc *atac = chp->ch_atac; 1007 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1008 struct ata_bio *ata_bio = xfer->c_cmd; 1009 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1010 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1011 u_int16_t cyl; 1012 u_int8_t head, sect, cmd = 0; 1013 int nblks, error; 1014 1015 DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n", 1016 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1017 1018 if (xfer->c_flags & C_DMA) 1019 if (drvp->n_xfers <= NXFER) 1020 drvp->n_xfers++; 1021 1022 again: 1023 /* 1024 * 1025 * When starting a multi-sector transfer, or doing single-sector 1026 * transfers... 1027 */ 1028 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1029 if (ata_bio->flags & ATA_SINGLE) 1030 nblks = 1; 1031 else 1032 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1033 /* Check for bad sectors and adjust transfer, if necessary. */ 1034 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 1035 long blkdiff; 1036 int i; 1037 1038 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 1039 i++) { 1040 blkdiff -= ata_bio->blkno; 1041 if (blkdiff < 0) 1042 continue; 1043 if (blkdiff == 0) 1044 /* Replace current block of transfer. */ 1045 ata_bio->blkno = 1046 ata_bio->lp->d_secperunit - 1047 ata_bio->lp->d_nsectors - i - 1; 1048 if (blkdiff < nblks) { 1049 /* Bad block inside transfer. */ 1050 ata_bio->flags |= ATA_SINGLE; 1051 nblks = 1; 1052 } 1053 break; 1054 } 1055 /* Transfer is okay now. */ 1056 } 1057 if (xfer->c_flags & C_DMA) { 1058 ata_bio->nblks = nblks; 1059 ata_bio->nbytes = xfer->c_bcount; 1060 1061 if (xfer->c_flags & C_POLL) 1062 sc->sc_enable_intr(mvport, 0 /*off*/); 1063 error = mvsata_edma_enqueue(mvport, ata_bio, 1064 (char *)xfer->c_databuf + xfer->c_skip); 1065 if (error) { 1066 if (error == EINVAL) { 1067 /* 1068 * We can't do DMA on this transfer 1069 * for some reason. Fall back to 1070 * PIO. 1071 */ 1072 xfer->c_flags &= ~C_DMA; 1073 error = 0; 1074 goto do_pio; 1075 } 1076 if (error == EBUSY) { 1077 aprint_error_dev(atac->atac_dev, 1078 "channel %d: EDMA Queue full\n", 1079 chp->ch_channel); 1080 /* 1081 * XXXX: Perhaps, after it waits for 1082 * a while, it is necessary to call 1083 * bio_start again. 1084 */ 1085 } 1086 ata_bio->error = ERR_DMA; 1087 ata_bio->r_error = 0; 1088 mvsata_bio_done(chp, xfer); 1089 return; 1090 } 1091 chp->ch_flags |= ATACH_DMA_WAIT; 1092 /* start timeout machinery */ 1093 if ((xfer->c_flags & C_POLL) == 0) 1094 callout_reset(&chp->ch_callout, 1095 ATA_DELAY / 1000 * hz, 1096 mvsata_edma_timeout, xfer); 1097 /* wait for irq */ 1098 goto intr; 1099 } /* else not DMA */ 1100 do_pio: 1101 if (ata_bio->flags & ATA_LBA48) { 1102 sect = 0; 1103 cyl = 0; 1104 head = 0; 1105 } else if (ata_bio->flags & ATA_LBA) { 1106 sect = (ata_bio->blkno >> 0) & 0xff; 1107 cyl = (ata_bio->blkno >> 8) & 0xffff; 1108 head = (ata_bio->blkno >> 24) & 0x0f; 1109 head |= WDSD_LBA; 1110 } else { 1111 int blkno = ata_bio->blkno; 1112 sect = blkno % ata_bio->lp->d_nsectors; 1113 sect++; /* Sectors begin with 1, not 0. */ 1114 blkno /= ata_bio->lp->d_nsectors; 1115 head = blkno % ata_bio->lp->d_ntracks; 1116 blkno /= ata_bio->lp->d_ntracks; 1117 cyl = blkno; 1118 head |= WDSD_CHS; 1119 } 1120 ata_bio->nblks = min(nblks, ata_bio->multi); 1121 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 1122 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1123 if (ata_bio->nblks > 1) 1124 cmd = (ata_bio->flags & ATA_READ) ? 1125 WDCC_READMULTI : WDCC_WRITEMULTI; 1126 else 1127 cmd = (ata_bio->flags & ATA_READ) ? 1128 WDCC_READ : WDCC_WRITE; 1129 1130 /* EDMA disable, if enabled this channel. */ 1131 if (mvport->port_edmamode != nodma) 1132 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1133 1134 /* Do control operations specially. */ 1135 if (__predict_false(drvp->state < READY)) { 1136 /* 1137 * Actually, we want to be careful not to mess with 1138 * the control state if the device is currently busy, 1139 * but we can assume that we never get to this point 1140 * if that's the case. 1141 */ 1142 /* 1143 * If it's not a polled command, we need the kernel 1144 * thread 1145 */ 1146 if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) { 1147 chp->ch_queue->queue_freeze++; 1148 wakeup(&chp->ch_thread); 1149 return; 1150 } 1151 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1152 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1153 mvsata_bio_done(chp, xfer); 1154 return; 1155 } 1156 } 1157 1158 /* Initiate command! */ 1159 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1160 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 1161 case WDCWAIT_OK: 1162 break; 1163 case WDCWAIT_TOUT: 1164 goto timeout; 1165 case WDCWAIT_THR: 1166 return; 1167 } 1168 if (ata_bio->flags & ATA_LBA48) 1169 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 1170 (uint64_t)ata_bio->blkno, nblks, 0); 1171 else 1172 wdccommand(chp, xfer->c_drive, cmd, cyl, 1173 head, sect, nblks, 1174 (ata_bio->lp->d_type == DTYPE_ST506) ? 1175 ata_bio->lp->d_precompcyl / 4 : 0); 1176 1177 /* start timeout machinery */ 1178 if ((xfer->c_flags & C_POLL) == 0) 1179 callout_reset(&chp->ch_callout, 1180 ATA_DELAY / 1000 * hz, wdctimeout, chp); 1181 } else if (ata_bio->nblks > 1) { 1182 /* The number of blocks in the last stretch may be smaller. */ 1183 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1184 if (ata_bio->nblks > nblks) { 1185 ata_bio->nblks = nblks; 1186 ata_bio->nbytes = xfer->c_bcount; 1187 } 1188 } 1189 /* If this was a write and not using DMA, push the data. */ 1190 if ((ata_bio->flags & ATA_READ) == 0) { 1191 /* 1192 * we have to busy-wait here, we can't rely on running in 1193 * thread context. 1194 */ 1195 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 1196 aprint_error_dev(atac->atac_dev, 1197 "channel %d: drive %d timeout waiting for DRQ," 1198 " st=0x%02x, err=0x%02x\n", 1199 chp->ch_channel, xfer->c_drive, chp->ch_status, 1200 chp->ch_error); 1201 ata_bio->error = TIMEOUT; 1202 mvsata_bio_done(chp, xfer); 1203 return; 1204 } 1205 if (chp->ch_status & WDCS_ERR) { 1206 ata_bio->error = ERROR; 1207 ata_bio->r_error = chp->ch_error; 1208 mvsata_bio_done(chp, xfer); 1209 return; 1210 } 1211 1212 wdc->dataout_pio(chp, drvp->drive_flags, 1213 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1214 } 1215 1216 intr: 1217 /* Wait for IRQ (either real or polled) */ 1218 if ((ata_bio->flags & ATA_POLL) == 0) { 1219 chp->ch_flags |= ATACH_IRQ_WAIT; 1220 } else { 1221 /* Wait for at last 400ns for status bit to be valid */ 1222 delay(1); 1223 if (chp->ch_flags & ATACH_DMA_WAIT) { 1224 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1225 sc->sc_enable_intr(mvport, 1 /*on*/); 1226 chp->ch_flags &= ~ATACH_DMA_WAIT; 1227 } 1228 mvsata_bio_intr(chp, xfer, 0); 1229 if ((ata_bio->flags & ATA_ITSDONE) == 0) 1230 goto again; 1231 } 1232 return; 1233 1234 timeout: 1235 aprint_error_dev(atac->atac_dev, 1236 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1237 chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error); 1238 ata_bio->error = TIMEOUT; 1239 mvsata_bio_done(chp, xfer); 1240 return; 1241 } 1242 1243 static int 1244 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1245 { 1246 struct atac_softc *atac = chp->ch_atac; 1247 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1248 struct ata_bio *ata_bio = xfer->c_cmd; 1249 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1250 1251 DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n", 1252 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1253 1254 chp->ch_flags &= ~(ATACH_IRQ_WAIT|ATACH_DMA_WAIT); 1255 1256 /* Is it not a transfer, but a control operation? */ 1257 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1258 aprint_error_dev(atac->atac_dev, 1259 "channel %d: drive %d bad state %d in mvsata_bio_intr\n", 1260 chp->ch_channel, xfer->c_drive, drvp->state); 1261 panic("mvsata_bio_intr: bad state"); 1262 } 1263 1264 /* 1265 * If we missed an interrupt transfer, reset and restart. 1266 * Don't try to continue transfer, we may have missed cycles. 1267 */ 1268 if (xfer->c_flags & C_TIMEOU) { 1269 ata_bio->error = TIMEOUT; 1270 mvsata_bio_done(chp, xfer); 1271 return 1; 1272 } 1273 1274 /* Ack interrupt done by wdc_wait_for_unbusy */ 1275 if (!(xfer->c_flags & C_DMA) && 1276 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) 1277 == WDCWAIT_TOUT)) { 1278 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1279 return 0; /* IRQ was not for us */ 1280 aprint_error_dev(atac->atac_dev, 1281 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1282 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1283 xfer->c_skip); 1284 ata_bio->error = TIMEOUT; 1285 mvsata_bio_done(chp, xfer); 1286 return 1; 1287 } 1288 1289 if (xfer->c_flags & C_DMA) { 1290 if (ata_bio->error == NOERROR) 1291 goto end; 1292 if (ata_bio->error == ERR_DMA) 1293 ata_dmaerr(drvp, 1294 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1295 } 1296 1297 /* if we had an error, end */ 1298 if (ata_bio->error != NOERROR) { 1299 mvsata_bio_done(chp, xfer); 1300 return 1; 1301 } 1302 1303 /* If this was a read and not using DMA, fetch the data. */ 1304 if ((ata_bio->flags & ATA_READ) != 0) { 1305 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 1306 aprint_error_dev(atac->atac_dev, 1307 "channel %d: drive %d read intr before drq\n", 1308 chp->ch_channel, xfer->c_drive); 1309 ata_bio->error = TIMEOUT; 1310 mvsata_bio_done(chp, xfer); 1311 return 1; 1312 } 1313 wdc->datain_pio(chp, drvp->drive_flags, 1314 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1315 } 1316 1317 end: 1318 ata_bio->blkno += ata_bio->nblks; 1319 ata_bio->blkdone += ata_bio->nblks; 1320 xfer->c_skip += ata_bio->nbytes; 1321 xfer->c_bcount -= ata_bio->nbytes; 1322 /* See if this transfer is complete. */ 1323 if (xfer->c_bcount > 0) { 1324 if ((ata_bio->flags & ATA_POLL) == 0) 1325 /* Start the next operation */ 1326 mvsata_bio_start(chp, xfer); 1327 else 1328 /* Let mvsata_bio_start do the loop */ 1329 return 1; 1330 } else { /* Done with this transfer */ 1331 ata_bio->error = NOERROR; 1332 mvsata_bio_done(chp, xfer); 1333 } 1334 return 1; 1335 } 1336 1337 static void 1338 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1339 { 1340 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1341 struct atac_softc *atac = chp->ch_atac; 1342 struct ata_bio *ata_bio = xfer->c_cmd; 1343 int drive = xfer->c_drive; 1344 1345 DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1346 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1347 1348 /* EDMA restart, if enabled */ 1349 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1350 mvsata_edma_reset_qptr(mvport); 1351 mvsata_edma_enable(mvport); 1352 } 1353 1354 ata_free_xfer(chp, xfer); 1355 1356 ata_bio->flags |= ATA_ITSDONE; 1357 switch (reason) { 1358 case KILL_GONE: 1359 ata_bio->error = ERR_NODEV; 1360 break; 1361 case KILL_RESET: 1362 ata_bio->error = ERR_RESET; 1363 break; 1364 default: 1365 aprint_error_dev(atac->atac_dev, 1366 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1367 panic("mvsata_bio_kill_xfer"); 1368 } 1369 ata_bio->r_error = WDCE_ABRT; 1370 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1371 } 1372 1373 static void 1374 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1375 { 1376 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1377 struct ata_bio *ata_bio = xfer->c_cmd; 1378 int drive = xfer->c_drive; 1379 1380 DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1381 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1382 (u_int)xfer->c_flags)); 1383 1384 callout_stop(&chp->ch_callout); 1385 1386 /* EDMA restart, if enabled */ 1387 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1388 mvsata_edma_reset_qptr(mvport); 1389 mvsata_edma_enable(mvport); 1390 } 1391 1392 /* feed back residual bcount to our caller */ 1393 ata_bio->bcount = xfer->c_bcount; 1394 1395 /* mark controller inactive and free xfer */ 1396 KASSERT(chp->ch_queue->active_xfer != NULL); 1397 chp->ch_queue->active_xfer = NULL; 1398 ata_free_xfer(chp, xfer); 1399 1400 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1401 ata_bio->error = ERR_NODEV; 1402 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1403 wakeup(&chp->ch_queue->active_xfer); 1404 } 1405 ata_bio->flags |= ATA_ITSDONE; 1406 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1407 atastart(chp); 1408 } 1409 1410 static int 1411 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1412 int flags) 1413 { 1414 struct ata_channel *chp = &mvport->port_ata_channel; 1415 struct atac_softc *atac = chp->ch_atac; 1416 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1417 const char *errstring; 1418 1419 flags |= AT_POLL; /* XXX */ 1420 1421 /* 1422 * disable interrupts, all commands here should be quick 1423 * enough to be able to poll, and we don't go here that often 1424 */ 1425 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1426 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1427 DELAY(10); 1428 errstring = "wait"; 1429 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1430 goto ctrltimeout; 1431 wdccommandshort(chp, drive, WDCC_RECAL); 1432 /* Wait for at last 400ns for status bit to be valid */ 1433 DELAY(1); 1434 errstring = "recal"; 1435 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1436 goto ctrltimeout; 1437 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1438 goto ctrlerror; 1439 /* Don't try to set modes if controller can't be adjusted */ 1440 if (atac->atac_set_modes == NULL) 1441 goto geometry; 1442 /* Also don't try if the drive didn't report its mode */ 1443 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1444 goto geometry; 1445 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1446 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1447 errstring = "piomode"; 1448 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1449 goto ctrltimeout; 1450 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1451 goto ctrlerror; 1452 if (drvp->drive_flags & DRIVE_UDMA) 1453 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1454 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1455 else if (drvp->drive_flags & DRIVE_DMA) 1456 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1457 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1458 else 1459 goto geometry; 1460 errstring = "dmamode"; 1461 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1462 goto ctrltimeout; 1463 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1464 goto ctrlerror; 1465 geometry: 1466 if (ata_bio->flags & ATA_LBA) 1467 goto multimode; 1468 wdccommand(chp, drive, WDCC_IDP, ata_bio->lp->d_ncylinders, 1469 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 1470 (ata_bio->lp->d_type == DTYPE_ST506) ? 1471 ata_bio->lp->d_precompcyl / 4 : 0); 1472 errstring = "geometry"; 1473 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1474 goto ctrltimeout; 1475 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1476 goto ctrlerror; 1477 multimode: 1478 if (ata_bio->multi == 1) 1479 goto ready; 1480 wdccommand(chp, drive, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0); 1481 errstring = "setmulti"; 1482 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1483 goto ctrltimeout; 1484 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1485 goto ctrlerror; 1486 ready: 1487 drvp->state = READY; 1488 /* 1489 * The drive is usable now 1490 */ 1491 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1492 delay(10); /* some drives need a little delay here */ 1493 return 0; 1494 1495 ctrltimeout: 1496 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1497 chp->ch_channel, drive, errstring); 1498 ata_bio->error = TIMEOUT; 1499 goto ctrldone; 1500 ctrlerror: 1501 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1502 chp->ch_channel, drive, errstring); 1503 if (chp->ch_status & WDCS_DWF) { 1504 aprint_error("drive fault\n"); 1505 ata_bio->error = ERR_DF; 1506 } else { 1507 aprint_error("error (%x)\n", chp->ch_error); 1508 ata_bio->r_error = chp->ch_error; 1509 ata_bio->error = ERROR; 1510 } 1511 ctrldone: 1512 drvp->state = 0; 1513 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1514 return -1; 1515 } 1516 1517 static void 1518 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1519 { 1520 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1521 int drive = xfer->c_drive; 1522 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1523 struct ata_command *ata_c = xfer->c_cmd; 1524 1525 DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n", 1526 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1527 1528 /* First, EDMA disable, if enabled this channel. */ 1529 if (mvport->port_edmamode != nodma) 1530 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1531 1532 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1533 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1534 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1535 case WDCWAIT_OK: 1536 break; 1537 case WDCWAIT_TOUT: 1538 ata_c->flags |= AT_TIMEOU; 1539 mvsata_wdc_cmd_done(chp, xfer); 1540 return; 1541 case WDCWAIT_THR: 1542 return; 1543 } 1544 if (ata_c->flags & AT_POLL) 1545 /* polled command, disable interrupts */ 1546 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1547 if ((ata_c->flags & AT_LBA48) != 0) { 1548 wdccommandext(chp, drive, ata_c->r_command, 1549 ata_c->r_lba, ata_c->r_count, ata_c->r_features); 1550 } else { 1551 wdccommand(chp, drive, ata_c->r_command, 1552 (ata_c->r_lba >> 8) & 0xffff, 1553 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1554 ((ata_c->r_lba >> 24) & 0x0f), 1555 ata_c->r_lba & 0xff, 1556 ata_c->r_count & 0xff, 1557 ata_c->r_features & 0xff); 1558 } 1559 1560 if ((ata_c->flags & AT_POLL) == 0) { 1561 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1562 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1563 wdctimeout, chp); 1564 return; 1565 } 1566 /* 1567 * Polled command. Wait for drive ready or drq. Done in intr(). 1568 * Wait for at last 400ns for status bit to be valid. 1569 */ 1570 delay(10); /* 400ns delay */ 1571 mvsata_wdc_cmd_intr(chp, xfer, 0); 1572 } 1573 1574 static int 1575 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1576 { 1577 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1578 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1579 struct ata_command *ata_c = xfer->c_cmd; 1580 int bcount = ata_c->bcount; 1581 char *data = ata_c->data; 1582 int wflags; 1583 int drive_flags; 1584 1585 if (ata_c->r_command == WDCC_IDENTIFY || 1586 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1587 /* 1588 * The IDENTIFY data has been designed as an array of 1589 * u_int16_t, so we can byteswap it on the fly. 1590 * Historically it's what we have always done so keeping it 1591 * here ensure binary backward compatibility. 1592 */ 1593 drive_flags = DRIVE_NOSTREAM | 1594 chp->ch_drive[xfer->c_drive].drive_flags; 1595 else 1596 /* 1597 * Other data structure are opaque and should be transfered 1598 * as is. 1599 */ 1600 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1601 1602 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1603 /* both wait and poll, we can tsleep here */ 1604 wflags = AT_WAIT | AT_POLL; 1605 else 1606 wflags = AT_POLL; 1607 1608 again: 1609 DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n", 1610 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1611 1612 /* 1613 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1614 * Reselect again, it doesn't hurt for others commands, and the time 1615 * penalty for the extra register write is acceptable, 1616 * wdc_exec_command() isn't called often (mostly for autoconfig) 1617 */ 1618 if ((xfer->c_flags & C_ATAPI) != 0) { 1619 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1620 } 1621 if ((ata_c->flags & AT_XFDONE) != 0) { 1622 /* 1623 * We have completed a data xfer. The drive should now be 1624 * in its initial state 1625 */ 1626 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1627 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1628 wflags) == WDCWAIT_TOUT) { 1629 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1630 return 0; /* IRQ was not for us */ 1631 ata_c->flags |= AT_TIMEOU; 1632 } 1633 goto out; 1634 } 1635 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1636 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1637 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1638 return 0; /* IRQ was not for us */ 1639 ata_c->flags |= AT_TIMEOU; 1640 goto out; 1641 } 1642 if (ata_c->flags & AT_READ) { 1643 if ((chp->ch_status & WDCS_DRQ) == 0) { 1644 ata_c->flags |= AT_TIMEOU; 1645 goto out; 1646 } 1647 wdc->datain_pio(chp, drive_flags, data, bcount); 1648 /* at this point the drive should be in its initial state */ 1649 ata_c->flags |= AT_XFDONE; 1650 /* 1651 * XXX checking the status register again here cause some 1652 * hardware to timeout. 1653 */ 1654 } else if (ata_c->flags & AT_WRITE) { 1655 if ((chp->ch_status & WDCS_DRQ) == 0) { 1656 ata_c->flags |= AT_TIMEOU; 1657 goto out; 1658 } 1659 wdc->dataout_pio(chp, drive_flags, data, bcount); 1660 ata_c->flags |= AT_XFDONE; 1661 if ((ata_c->flags & AT_POLL) == 0) { 1662 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */ 1663 callout_reset(&chp->ch_callout, 1664 mstohz(ata_c->timeout), wdctimeout, chp); 1665 return 1; 1666 } else 1667 goto again; 1668 } 1669 out: 1670 mvsata_wdc_cmd_done(chp, xfer); 1671 return 1; 1672 } 1673 1674 static void 1675 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1676 int reason) 1677 { 1678 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1679 struct ata_command *ata_c = xfer->c_cmd; 1680 1681 DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1682 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1683 1684 switch (reason) { 1685 case KILL_GONE: 1686 ata_c->flags |= AT_GONE; 1687 break; 1688 case KILL_RESET: 1689 ata_c->flags |= AT_RESET; 1690 break; 1691 default: 1692 aprint_error_dev(MVSATA_DEV2(mvport), 1693 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1694 panic("mvsata_cmd_kill_xfer"); 1695 } 1696 mvsata_wdc_cmd_done_end(chp, xfer); 1697 } 1698 1699 static void 1700 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1701 { 1702 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1703 struct atac_softc *atac = chp->ch_atac; 1704 struct ata_command *ata_c = xfer->c_cmd; 1705 1706 DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1707 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1708 ata_c->flags)); 1709 1710 if (chp->ch_status & WDCS_DWF) 1711 ata_c->flags |= AT_DF; 1712 if (chp->ch_status & WDCS_ERR) { 1713 ata_c->flags |= AT_ERROR; 1714 ata_c->r_error = chp->ch_error; 1715 } 1716 if ((ata_c->flags & AT_READREG) != 0 && 1717 device_is_active(atac->atac_dev) && 1718 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1719 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1720 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1721 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1722 ata_c->r_lba = 1723 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1724 ata_c->r_lba |= 1725 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1726 ata_c->r_lba |= 1727 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1728 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1729 if ((ata_c->flags & AT_LBA48) != 0) { 1730 if ((ata_c->flags & AT_POLL) != 0) { 1731 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1732 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1733 } else { 1734 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1735 WDCTL_HOB|WDCTL_4BIT); 1736 } 1737 ata_c->r_count |= 1738 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1739 ata_c->r_lba = 1740 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1741 ata_c->r_lba |= 1742 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1743 ata_c->r_lba |= 1744 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1745 if ((ata_c->flags & AT_POLL) != 0) { 1746 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1747 WDCTL_4BIT|WDCTL_IDS); 1748 } else { 1749 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1750 WDCTL_4BIT); 1751 } 1752 } else { 1753 ata_c->r_lba |= 1754 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1755 } 1756 } 1757 callout_stop(&chp->ch_callout); 1758 chp->ch_queue->active_xfer = NULL; 1759 if (ata_c->flags & AT_POLL) { 1760 /* enable interrupts */ 1761 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1762 delay(10); /* some drives need a little delay here */ 1763 } 1764 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1765 mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE); 1766 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1767 wakeup(&chp->ch_queue->active_xfer); 1768 } else 1769 mvsata_wdc_cmd_done_end(chp, xfer); 1770 } 1771 1772 static void 1773 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1774 { 1775 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1776 struct ata_command *ata_c = xfer->c_cmd; 1777 1778 /* EDMA restart, if enabled */ 1779 if (mvport->port_edmamode != nodma) { 1780 mvsata_edma_reset_qptr(mvport); 1781 mvsata_edma_enable(mvport); 1782 } 1783 1784 ata_c->flags |= AT_DONE; 1785 ata_free_xfer(chp, xfer); 1786 if (ata_c->flags & AT_WAIT) 1787 wakeup(ata_c); 1788 else if (ata_c->callback) 1789 ata_c->callback(ata_c->callback_arg); 1790 atastart(chp); 1791 1792 return; 1793 } 1794 1795 #if NATAPIBUS > 0 1796 static void 1797 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1798 { 1799 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 1800 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1801 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1802 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1803 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1804 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1805 const char *errstring; 1806 1807 DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 1808 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1809 xfer->c_drive, sc_xfer->xs_control)); 1810 1811 if (mvport->port_edmamode != nodma) 1812 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1813 1814 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 1815 drvp->n_xfers++; 1816 1817 /* Do control operations specially. */ 1818 if (__predict_false(drvp->state < READY)) { 1819 /* If it's not a polled command, we need the kernel thread */ 1820 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) { 1821 chp->ch_queue->queue_freeze++; 1822 wakeup(&chp->ch_thread); 1823 return; 1824 } 1825 /* 1826 * disable interrupts, all commands here should be quick 1827 * enough to be able to poll, and we don't go here that often 1828 */ 1829 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1830 1831 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1832 /* Don't try to set mode if controller can't be adjusted */ 1833 if (atac->atac_set_modes == NULL) 1834 goto ready; 1835 /* Also don't try if the drive didn't report its mode */ 1836 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1837 goto ready; 1838 errstring = "unbusy"; 1839 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) 1840 goto timeout; 1841 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1842 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1843 errstring = "piomode"; 1844 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1845 goto timeout; 1846 if (chp->ch_status & WDCS_ERR) { 1847 if (chp->ch_error == WDCE_ABRT) { 1848 /* 1849 * Some ATAPI drives reject PIO settings. 1850 * Fall back to PIO mode 3 since that's the 1851 * minimum for ATAPI. 1852 */ 1853 aprint_error_dev(atac->atac_dev, 1854 "channel %d drive %d: PIO mode %d rejected," 1855 " falling back to PIO mode 3\n", 1856 chp->ch_channel, xfer->c_drive, 1857 drvp->PIO_mode); 1858 if (drvp->PIO_mode > 3) 1859 drvp->PIO_mode = 3; 1860 } else 1861 goto error; 1862 } 1863 if (drvp->drive_flags & DRIVE_UDMA) 1864 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1865 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1866 else 1867 if (drvp->drive_flags & DRIVE_DMA) 1868 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1869 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1870 else 1871 goto ready; 1872 errstring = "dmamode"; 1873 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1874 goto timeout; 1875 if (chp->ch_status & WDCS_ERR) { 1876 if (chp->ch_error == WDCE_ABRT) { 1877 if (drvp->drive_flags & DRIVE_UDMA) 1878 goto error; 1879 else { 1880 /* 1881 * The drive rejected our DMA setting. 1882 * Fall back to mode 1. 1883 */ 1884 aprint_error_dev(atac->atac_dev, 1885 "channel %d drive %d:" 1886 " DMA mode %d rejected," 1887 " falling back to DMA mode 0\n", 1888 chp->ch_channel, xfer->c_drive, 1889 drvp->DMA_mode); 1890 if (drvp->DMA_mode > 0) 1891 drvp->DMA_mode = 0; 1892 } 1893 } else 1894 goto error; 1895 } 1896 ready: 1897 drvp->state = READY; 1898 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1899 delay(10); /* some drives need a little delay here */ 1900 } 1901 /* start timeout machinery */ 1902 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 1903 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1904 wdctimeout, chp); 1905 1906 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1907 switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) { 1908 case WDCWAIT_OK: 1909 break; 1910 case WDCWAIT_TOUT: 1911 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 1912 chp->ch_status); 1913 sc_xfer->error = XS_TIMEOUT; 1914 mvsata_atapi_reset(chp, xfer); 1915 return; 1916 case WDCWAIT_THR: 1917 return; 1918 } 1919 1920 /* 1921 * Even with WDCS_ERR, the device should accept a command packet 1922 * Limit length to what can be stuffed into the cylinder register 1923 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 1924 * but not all devices do that and it's not obvious from the 1925 * ATAPI spec that that behaviour should be expected. If more 1926 * data is necessary, multiple data transfer phases will be done. 1927 */ 1928 1929 wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD, 1930 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 1931 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1932 1933 /* 1934 * If there is no interrupt for CMD input, busy-wait for it (done in 1935 * the interrupt routine. If it is a polled command, call the interrupt 1936 * routine until command is done. 1937 */ 1938 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 1939 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) { 1940 /* Wait for at last 400ns for status bit to be valid */ 1941 DELAY(1); 1942 mvsata_atapi_intr(chp, xfer, 0); 1943 } else 1944 chp->ch_flags |= ATACH_IRQ_WAIT; 1945 if (sc_xfer->xs_control & XS_CTL_POLL) { 1946 if (chp->ch_flags & ATACH_DMA_WAIT) { 1947 wdc_dmawait(chp, xfer, sc_xfer->timeout); 1948 chp->ch_flags &= ~ATACH_DMA_WAIT; 1949 } 1950 while ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1951 /* Wait for at last 400ns for status bit to be valid */ 1952 DELAY(1); 1953 mvsata_atapi_intr(chp, xfer, 0); 1954 } 1955 } 1956 return; 1957 1958 timeout: 1959 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 1960 chp->ch_channel, xfer->c_drive, errstring); 1961 sc_xfer->error = XS_TIMEOUT; 1962 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1963 delay(10); /* some drives need a little delay here */ 1964 mvsata_atapi_reset(chp, xfer); 1965 return; 1966 1967 error: 1968 aprint_error_dev(atac->atac_dev, 1969 "channel %d drive %d: %s error (0x%x)\n", 1970 chp->ch_channel, xfer->c_drive, errstring, chp->ch_error); 1971 sc_xfer->error = XS_SHORTSENSE; 1972 sc_xfer->sense.atapi_sense = chp->ch_error; 1973 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1974 delay(10); /* some drives need a little delay here */ 1975 mvsata_atapi_reset(chp, xfer); 1976 return; 1977 } 1978 1979 static int 1980 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1981 { 1982 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1983 struct atac_softc *atac = chp->ch_atac; 1984 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1985 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1986 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1987 int len, phase, ire, error, retries=0, i; 1988 void *cmd; 1989 1990 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n", 1991 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1992 1993 /* Is it not a transfer, but a control operation? */ 1994 if (drvp->state < READY) { 1995 aprint_error_dev(atac->atac_dev, 1996 "channel %d drive %d: bad state %d\n", 1997 chp->ch_channel, xfer->c_drive, drvp->state); 1998 panic("mvsata_atapi_intr: bad state"); 1999 } 2000 /* 2001 * If we missed an interrupt in a PIO transfer, reset and restart. 2002 * Don't try to continue transfer, we may have missed cycles. 2003 */ 2004 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2005 sc_xfer->error = XS_TIMEOUT; 2006 mvsata_atapi_reset(chp, xfer); 2007 return 1; 2008 } 2009 2010 /* Ack interrupt done in wdc_wait_for_unbusy */ 2011 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2012 if (wdc_wait_for_unbusy(chp, 2013 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) { 2014 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 2015 return 0; /* IRQ was not for us */ 2016 aprint_error_dev(atac->atac_dev, 2017 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2018 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2019 if (xfer->c_flags & C_DMA) 2020 ata_dmaerr(drvp, 2021 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2022 sc_xfer->error = XS_TIMEOUT; 2023 mvsata_atapi_reset(chp, xfer); 2024 return 1; 2025 } 2026 2027 /* 2028 * If we missed an IRQ and were using DMA, flag it as a DMA error 2029 * and reset device. 2030 */ 2031 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2032 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2033 sc_xfer->error = XS_RESET; 2034 mvsata_atapi_reset(chp, xfer); 2035 return (1); 2036 } 2037 /* 2038 * if the request sense command was aborted, report the short sense 2039 * previously recorded, else continue normal processing 2040 */ 2041 2042 again: 2043 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2044 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2045 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2046 phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ); 2047 DPRINTF(( 2048 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2049 xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire)); 2050 2051 switch (phase) { 2052 case PHASE_CMDOUT: 2053 cmd = sc_xfer->cmd; 2054 DPRINTF(("PHASE_CMDOUT\n")); 2055 /* Init the DMA channel if necessary */ 2056 if (xfer->c_flags & C_DMA) { 2057 error = mvsata_bdma_init(mvport, sc_xfer, 2058 (char *)xfer->c_databuf + xfer->c_skip); 2059 if (error) { 2060 if (error == EINVAL) { 2061 /* 2062 * We can't do DMA on this transfer 2063 * for some reason. Fall back to PIO. 2064 */ 2065 xfer->c_flags &= ~C_DMA; 2066 error = 0; 2067 } else { 2068 sc_xfer->error = XS_DRIVER_STUFFUP; 2069 break; 2070 } 2071 } 2072 } 2073 2074 /* send packet command */ 2075 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2076 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2077 2078 /* Start the DMA channel if necessary */ 2079 if (xfer->c_flags & C_DMA) { 2080 mvsata_bdma_start(mvport); 2081 chp->ch_flags |= ATACH_DMA_WAIT; 2082 } 2083 2084 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2085 chp->ch_flags |= ATACH_IRQ_WAIT; 2086 return 1; 2087 2088 case PHASE_DATAOUT: 2089 /* write data */ 2090 DPRINTF(("PHASE_DATAOUT\n")); 2091 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2092 (xfer->c_flags & C_DMA) != 0) { 2093 aprint_error_dev(atac->atac_dev, 2094 "channel %d drive %d: bad data phase DATAOUT\n", 2095 chp->ch_channel, xfer->c_drive); 2096 if (xfer->c_flags & C_DMA) 2097 ata_dmaerr(drvp, 2098 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2099 sc_xfer->error = XS_TIMEOUT; 2100 mvsata_atapi_reset(chp, xfer); 2101 return 1; 2102 } 2103 xfer->c_lenoff = len - xfer->c_bcount; 2104 if (xfer->c_bcount < len) { 2105 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2106 " warning: write only %d of %d requested bytes\n", 2107 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2108 len); 2109 len = xfer->c_bcount; 2110 } 2111 2112 wdc->dataout_pio(chp, drvp->drive_flags, 2113 (char *)xfer->c_databuf + xfer->c_skip, len); 2114 2115 for (i = xfer->c_lenoff; i > 0; i -= 2) 2116 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2117 2118 xfer->c_skip += len; 2119 xfer->c_bcount -= len; 2120 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2121 chp->ch_flags |= ATACH_IRQ_WAIT; 2122 return 1; 2123 2124 case PHASE_DATAIN: 2125 /* Read data */ 2126 DPRINTF(("PHASE_DATAIN\n")); 2127 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2128 (xfer->c_flags & C_DMA) != 0) { 2129 aprint_error_dev(atac->atac_dev, 2130 "channel %d drive %d: bad data phase DATAIN\n", 2131 chp->ch_channel, xfer->c_drive); 2132 if (xfer->c_flags & C_DMA) 2133 ata_dmaerr(drvp, 2134 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2135 sc_xfer->error = XS_TIMEOUT; 2136 mvsata_atapi_reset(chp, xfer); 2137 return 1; 2138 } 2139 xfer->c_lenoff = len - xfer->c_bcount; 2140 if (xfer->c_bcount < len) { 2141 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2142 " warning: reading only %d of %d bytes\n", 2143 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2144 len); 2145 len = xfer->c_bcount; 2146 } 2147 2148 wdc->datain_pio(chp, drvp->drive_flags, 2149 (char *)xfer->c_databuf + xfer->c_skip, len); 2150 2151 if (xfer->c_lenoff > 0) 2152 wdcbit_bucket(chp, len - xfer->c_bcount); 2153 2154 xfer->c_skip += len; 2155 xfer->c_bcount -= len; 2156 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2157 chp->ch_flags |= ATACH_IRQ_WAIT; 2158 return 1; 2159 2160 case PHASE_ABORTED: 2161 case PHASE_COMPLETED: 2162 DPRINTF(("PHASE_COMPLETED\n")); 2163 if (xfer->c_flags & C_DMA) 2164 xfer->c_bcount -= sc_xfer->datalen; 2165 sc_xfer->resid = xfer->c_bcount; 2166 mvsata_atapi_phase_complete(xfer); 2167 return 1; 2168 2169 default: 2170 if (++retries<500) { 2171 DELAY(100); 2172 chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 2173 chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 2174 goto again; 2175 } 2176 aprint_error_dev(atac->atac_dev, 2177 "channel %d drive %d: unknown phase 0x%x\n", 2178 chp->ch_channel, xfer->c_drive, phase); 2179 if (chp->ch_status & WDCS_ERR) { 2180 sc_xfer->error = XS_SHORTSENSE; 2181 sc_xfer->sense.atapi_sense = chp->ch_error; 2182 } else { 2183 if (xfer->c_flags & C_DMA) 2184 ata_dmaerr(drvp, 2185 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2186 sc_xfer->error = XS_RESET; 2187 mvsata_atapi_reset(chp, xfer); 2188 return (1); 2189 } 2190 } 2191 DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x " 2192 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense)); 2193 mvsata_atapi_done(chp, xfer); 2194 return 1; 2195 } 2196 2197 static void 2198 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2199 int reason) 2200 { 2201 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2202 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2203 2204 /* remove this command from xfer queue */ 2205 switch (reason) { 2206 case KILL_GONE: 2207 sc_xfer->error = XS_DRIVER_STUFFUP; 2208 break; 2209 2210 case KILL_RESET: 2211 sc_xfer->error = XS_RESET; 2212 break; 2213 2214 default: 2215 aprint_error_dev(MVSATA_DEV2(mvport), 2216 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2217 panic("mvsata_atapi_kill_xfer"); 2218 } 2219 ata_free_xfer(chp, xfer); 2220 scsipi_done(sc_xfer); 2221 } 2222 2223 static void 2224 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2225 { 2226 struct atac_softc *atac = chp->ch_atac; 2227 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2228 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2229 2230 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 2231 drvp->state = 0; 2232 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) { 2233 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2234 chp->ch_channel, xfer->c_drive); 2235 sc_xfer->error = XS_SELTIMEOUT; 2236 } 2237 mvsata_atapi_done(chp, xfer); 2238 return; 2239 } 2240 2241 static void 2242 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2243 { 2244 struct ata_channel *chp = xfer->c_chp; 2245 struct atac_softc *atac = chp->ch_atac; 2246 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2247 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2248 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2249 2250 /* wait for DSC if needed */ 2251 if (drvp->drive_flags & DRIVE_ATAPIST) { 2252 DPRINTFN(1, 2253 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2254 device_xname(atac->atac_dev), chp->ch_channel, 2255 xfer->c_drive, xfer->c_dscpoll)); 2256 if (cold) 2257 panic("mvsata_atapi_phase_complete: cold"); 2258 2259 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) == 2260 WDCWAIT_TOUT) { 2261 /* 10ms not enough, try again in 1 tick */ 2262 if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) { 2263 aprint_error_dev(atac->atac_dev, 2264 "channel %d: wait_for_dsc failed\n", 2265 chp->ch_channel); 2266 sc_xfer->error = XS_TIMEOUT; 2267 mvsata_atapi_reset(chp, xfer); 2268 return; 2269 } else 2270 callout_reset(&chp->ch_callout, 1, 2271 mvsata_atapi_polldsc, xfer); 2272 return; 2273 } 2274 } 2275 2276 /* 2277 * Some drive occasionally set WDCS_ERR with 2278 * "ATA illegal length indication" in the error 2279 * register. If we read some data the sense is valid 2280 * anyway, so don't report the error. 2281 */ 2282 if (chp->ch_status & WDCS_ERR && 2283 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2284 sc_xfer->resid == sc_xfer->datalen)) { 2285 /* save the short sense */ 2286 sc_xfer->error = XS_SHORTSENSE; 2287 sc_xfer->sense.atapi_sense = chp->ch_error; 2288 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2289 /* ask scsipi to send a REQUEST_SENSE */ 2290 sc_xfer->error = XS_BUSY; 2291 sc_xfer->status = SCSI_CHECK; 2292 } else 2293 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2294 ata_dmaerr(drvp, 2295 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2296 sc_xfer->error = XS_RESET; 2297 mvsata_atapi_reset(chp, xfer); 2298 return; 2299 } 2300 } 2301 if (xfer->c_bcount != 0) 2302 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:" 2303 " bcount value is %d after io\n", 2304 device_xname(atac->atac_dev), chp->ch_channel, 2305 xfer->c_drive, xfer->c_bcount)); 2306 #ifdef DIAGNOSTIC 2307 if (xfer->c_bcount < 0) 2308 aprint_error_dev(atac->atac_dev, 2309 "channel %d drive %d: mvsata_atapi_intr:" 2310 " warning: bcount value is %d after io\n", 2311 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2312 #endif 2313 2314 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:" 2315 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2316 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2317 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2318 mvsata_atapi_done(chp, xfer); 2319 } 2320 2321 static void 2322 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2323 { 2324 struct atac_softc *atac = chp->ch_atac; 2325 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2326 int drive = xfer->c_drive; 2327 2328 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2329 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2330 (u_int)xfer->c_flags)); 2331 callout_stop(&chp->ch_callout); 2332 /* mark controller inactive and free the command */ 2333 chp->ch_queue->active_xfer = NULL; 2334 ata_free_xfer(chp, xfer); 2335 2336 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 2337 sc_xfer->error = XS_DRIVER_STUFFUP; 2338 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 2339 wakeup(&chp->ch_queue->active_xfer); 2340 } 2341 2342 DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2343 device_xname(atac->atac_dev), chp->ch_channel)); 2344 scsipi_done(sc_xfer); 2345 DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2346 device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags)); 2347 atastart(chp); 2348 } 2349 2350 static void 2351 mvsata_atapi_polldsc(void *arg) 2352 { 2353 2354 mvsata_atapi_phase_complete(arg); 2355 } 2356 #endif /* NATAPIBUS > 0 */ 2357 2358 2359 /* 2360 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2361 * if supported queuing command by atabus? The race condition will not happen 2362 * if this is called only to the thread of atabus. 2363 */ 2364 static int 2365 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio, 2366 void *databuf) 2367 { 2368 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2369 struct ata_channel *chp = &mvport->port_ata_channel; 2370 struct eprd *eprd; 2371 bus_addr_t crqb_base_addr; 2372 bus_dmamap_t data_dmamap; 2373 uint32_t reg; 2374 int quetag, erqqip, erqqop, next, rv, i; 2375 2376 DPRINTFN(2, ("%s:%d:%d: mvsata_edma_enqueue:" 2377 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2378 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2379 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2380 2381 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2382 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2383 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2384 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2385 next = erqqip; 2386 MVSATA_EDMAQ_INC(next); 2387 if (next == erqqop) 2388 /* queue full */ 2389 return EBUSY; 2390 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2391 /* tag nothing */ 2392 return EBUSY; 2393 DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag)); 2394 2395 rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes, 2396 ata_bio->flags); 2397 if (rv != 0) 2398 return rv; 2399 2400 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2401 KASSERT(chp->ch_queue->active_xfer != NULL); 2402 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2403 2404 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2405 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2406 eprd = mvport->port_reqtbl[quetag].eprd; 2407 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2408 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2409 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2410 2411 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2412 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2413 eprd->eot = htole16(0); 2414 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2415 eprd++; 2416 } 2417 (eprd - 1)->eot |= htole16(EPRD_EOT); 2418 #ifdef MVSATA_DEBUG 2419 if (mvsata_debug >= 3) 2420 mvsata_print_eprd(mvport, quetag); 2421 #endif 2422 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2423 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2424 BUS_DMASYNC_PREWRITE); 2425 2426 /* setup EDMA Command Request Block (CRQB) Data */ 2427 sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio); 2428 #ifdef MVSATA_DEBUG 2429 if (mvsata_debug >= 3) 2430 mvsata_print_crqb(mvport, erqqip); 2431 #endif 2432 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2433 erqqip * sizeof(union mvsata_crqb), 2434 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2435 2436 MVSATA_EDMAQ_INC(erqqip); 2437 2438 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2439 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2440 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2441 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2442 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2443 2444 return 0; 2445 } 2446 2447 static int 2448 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2449 { 2450 struct ata_channel *chp = &mvport->port_ata_channel; 2451 struct crpb *crpb; 2452 struct ata_bio *ata_bio; 2453 struct ata_xfer *xfer; 2454 uint32_t reg; 2455 int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2456 2457 /* First, Sync for Request Queue buffer */ 2458 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2459 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2460 if (mvport->port_prev_erqqop != erqqop) { 2461 const int s = sizeof(union mvsata_crqb); 2462 2463 if (mvport->port_prev_erqqop < erqqop) 2464 n = erqqop - mvport->port_prev_erqqop; 2465 else { 2466 if (erqqop > 0) 2467 bus_dmamap_sync(mvport->port_dmat, 2468 mvport->port_crqb_dmamap, 0, erqqop * s, 2469 BUS_DMASYNC_POSTWRITE); 2470 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2471 } 2472 if (n > 0) 2473 bus_dmamap_sync(mvport->port_dmat, 2474 mvport->port_crqb_dmamap, 2475 mvport->port_prev_erqqop * s, n * s, 2476 BUS_DMASYNC_POSTWRITE); 2477 mvport->port_prev_erqqop = erqqop; 2478 } 2479 2480 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2481 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2482 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2483 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2484 2485 DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2486 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2487 mvport->port, erpqip, erpqop)); 2488 2489 if (erpqop == erpqip) 2490 return 0; 2491 2492 if (erpqop < erpqip) 2493 n = erpqip - erpqop; 2494 else { 2495 if (erpqip > 0) 2496 bus_dmamap_sync(mvport->port_dmat, 2497 mvport->port_crpb_dmamap, 2498 0, erpqip * sizeof(struct crpb), 2499 BUS_DMASYNC_POSTREAD); 2500 n = MVSATA_EDMAQ_LEN - erpqop; 2501 } 2502 if (n > 0) 2503 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2504 erpqop * sizeof(struct crpb), 2505 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2506 2507 prev_erpqop = erpqop; 2508 while (erpqop != erpqip) { 2509 #ifdef MVSATA_DEBUG 2510 if (mvsata_debug >= 3) 2511 mvsata_print_crpb(mvport, erpqop); 2512 #endif 2513 crpb = mvport->port_crpb + erpqop; 2514 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2515 KASSERT(chp->ch_queue->active_xfer != NULL); 2516 xfer = chp->ch_queue->active_xfer; 2517 KASSERT(xfer == mvport->port_reqtbl[quetag].xfer); 2518 #ifdef DIAGNOSTIC 2519 if (xfer == NULL) 2520 panic("unknown response received: %s:%d:%d: tag 0x%x\n", 2521 device_xname(MVSATA_DEV2(mvport)), 2522 mvport->port_hc->hc, mvport->port, quetag); 2523 #endif 2524 2525 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2526 mvport->port_reqtbl[quetag].eprd_offset, 2527 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2528 2529 chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2530 chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2531 ata_bio = xfer->c_cmd; 2532 ata_bio->error = NOERROR; 2533 ata_bio->r_error = 0; 2534 if (chp->ch_status & WDCS_ERR) 2535 ata_bio->error = ERROR; 2536 if (chp->ch_status & WDCS_BSY) 2537 ata_bio->error = TIMEOUT; 2538 if (chp->ch_error) 2539 ata_bio->error = ERR_DMA; 2540 2541 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2542 mvport->port_reqtbl[quetag].xfer = NULL; 2543 mvsata_quetag_put(mvport, quetag); 2544 MVSATA_EDMAQ_INC(erpqop); 2545 2546 #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */ 2547 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2548 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2549 if (erpqop == erqqip) 2550 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2551 #endif 2552 mvsata_bio_intr(chp, xfer, 1); 2553 if (xfer1 == NULL) 2554 handled++; 2555 else if (xfer == xfer1) { 2556 handled = 1; 2557 break; 2558 } 2559 } 2560 if (prev_erpqop < erpqop) 2561 n = erpqop - prev_erpqop; 2562 else { 2563 if (erpqop > 0) 2564 bus_dmamap_sync(mvport->port_dmat, 2565 mvport->port_crpb_dmamap, 0, 2566 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2567 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2568 } 2569 if (n > 0) 2570 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2571 prev_erpqop * sizeof(struct crpb), 2572 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2573 2574 reg &= ~EDMA_RESQP_ERPQP_MASK; 2575 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2576 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2577 2578 #if 0 /* already cleared ago? */ 2579 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2580 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2581 if (erpqop == erqqip) 2582 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2583 #endif 2584 2585 return handled; 2586 } 2587 2588 static int 2589 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2590 { 2591 struct ata_bio *ata_bio = xfer->c_cmd; 2592 int xtime; 2593 2594 for (xtime = 0; xtime < timeout / 10; xtime++) { 2595 if (mvsata_edma_handle(mvport, xfer)) 2596 return 0; 2597 if (ata_bio->flags & ATA_NOSLEEP) 2598 delay(10000); 2599 else 2600 tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10)); 2601 } 2602 2603 DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer)); 2604 mvsata_edma_rqq_remove(mvport, xfer); 2605 xfer->c_flags |= C_TIMEOU; 2606 return 1; 2607 } 2608 2609 static void 2610 mvsata_edma_timeout(void *arg) 2611 { 2612 struct ata_xfer *xfer = (struct ata_xfer *)arg; 2613 struct ata_channel *chp = xfer->c_chp; 2614 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2615 int s; 2616 2617 s = splbio(); 2618 DPRINTF(("mvsata_edma_timeout: %p\n", xfer)); 2619 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 2620 mvsata_edma_rqq_remove(mvport, xfer); 2621 xfer->c_flags |= C_TIMEOU; 2622 mvsata_bio_intr(chp, xfer, 1); 2623 } 2624 splx(s); 2625 } 2626 2627 static void 2628 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2629 { 2630 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2631 struct ata_bio *ata_bio; 2632 bus_addr_t crqb_base_addr; 2633 int erqqip, i; 2634 2635 /* First, hardware reset, stop EDMA */ 2636 mvsata_hreset_port(mvport); 2637 2638 /* cleanup completed EDMA safely */ 2639 mvsata_edma_handle(mvport, NULL); 2640 2641 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2642 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2643 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2644 if (mvport->port_reqtbl[i].xfer == NULL) 2645 continue; 2646 2647 ata_bio = mvport->port_reqtbl[i].xfer->c_cmd; 2648 if (mvport->port_reqtbl[i].xfer == xfer) { 2649 /* remove xfer from EDMA request queue */ 2650 bus_dmamap_sync(mvport->port_dmat, 2651 mvport->port_eprd_dmamap, 2652 mvport->port_reqtbl[i].eprd_offset, 2653 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2654 mvsata_dma_bufunload(mvport, i, ata_bio->flags); 2655 mvport->port_reqtbl[i].xfer = NULL; 2656 mvsata_quetag_put(mvport, i); 2657 continue; 2658 } 2659 2660 sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio); 2661 erqqip++; 2662 } 2663 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2664 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2665 BUS_DMASYNC_POSTWRITE); 2666 2667 mvsata_edma_config(mvport, mvport->port_edmamode); 2668 mvsata_edma_reset_qptr(mvport); 2669 mvsata_edma_enable(mvport); 2670 2671 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2672 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2673 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2674 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2675 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2676 } 2677 2678 #if NATAPIBUS > 0 2679 static int 2680 mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer, 2681 void *databuf) 2682 { 2683 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2684 struct eprd *eprd; 2685 bus_dmamap_t data_dmamap; 2686 bus_addr_t eprd_addr; 2687 int quetag, rv; 2688 2689 DPRINTFN(2, 2690 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2691 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2692 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2693 2694 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2695 /* tag nothing */ 2696 return EBUSY; 2697 DPRINTFN(2, (" quetag=%d\n", quetag)); 2698 2699 rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen, 2700 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2701 if (rv != 0) 2702 return rv; 2703 2704 KASSERT(chp->ch_queue->active_xfer != NULL); 2705 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2706 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2707 2708 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2709 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2710 eprd = mvport->port_reqtbl[quetag].eprd; 2711 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2712 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2713 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2714 2715 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2716 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2717 eprd->eot = htole16(0); 2718 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2719 eprd++; 2720 } 2721 (eprd - 1)->eot |= htole16(EPRD_EOT); 2722 #ifdef MVSATA_DEBUG 2723 if (mvsata_debug >= 3) 2724 mvsata_print_eprd(mvport, quetag); 2725 #endif 2726 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2727 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2728 BUS_DMASYNC_PREWRITE); 2729 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2730 mvport->port_reqtbl[quetag].eprd_offset; 2731 2732 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2733 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2734 2735 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2736 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2737 else 2738 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2739 2740 return 0; 2741 } 2742 2743 static void 2744 mvsata_bdma_start(struct mvsata_port *mvport) 2745 { 2746 2747 #ifdef MVSATA_DEBUG 2748 if (mvsata_debug >= 3) 2749 mvsata_print_eprd(mvport, 0); 2750 #endif 2751 2752 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2753 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2754 } 2755 #endif 2756 #endif 2757 2758 2759 static int 2760 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2761 { 2762 struct mvsata_softc *sc = mvhc->hc_sc; 2763 struct mvsata_port *mvport; 2764 struct ata_channel *chp; 2765 int channel, rv, i; 2766 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2767 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2768 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2769 2770 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2771 M_ZERO | M_NOWAIT); 2772 if (mvport == NULL) { 2773 aprint_error("%s:%d: can't allocate memory for port %d\n", 2774 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2775 return ENOMEM; 2776 } 2777 2778 mvport->port = port; 2779 mvport->port_hc = mvhc; 2780 mvport->port_edmamode = nodma; 2781 2782 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2783 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 2784 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 2785 if (rv != 0) { 2786 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 2787 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2788 goto fail0; 2789 } 2790 mvport->port_iot = mvhc->hc_iot; 2791 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 2792 &mvport->port_sata_sstatus); 2793 if (rv != 0) { 2794 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 2795 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2796 goto fail0; 2797 } 2798 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 2799 &mvport->port_sata_serror); 2800 if (rv != 0) { 2801 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 2802 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2803 goto fail0; 2804 } 2805 if (sc->sc_rev == gen1) 2806 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2807 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 2808 else 2809 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2810 SATA_SC, 4, &mvport->port_sata_scontrol); 2811 if (rv != 0) { 2812 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 2813 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2814 goto fail0; 2815 } 2816 mvport->port_dmat = sc->sc_dmat; 2817 #ifndef MVSATA_WITHOUTDMA 2818 mvsata_quetag_init(mvport); 2819 #endif 2820 mvhc->hc_ports[port] = mvport; 2821 2822 channel = mvhc->hc * sc->sc_port + port; 2823 chp = &mvport->port_ata_channel; 2824 chp->ch_channel = channel; 2825 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 2826 chp->ch_ndrive = 1; /* SATA is always 1 drive */ 2827 chp->ch_queue = &mvport->port_ata_queue; 2828 sc->sc_ata_channels[channel] = chp; 2829 2830 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 2831 if (rv != 0) 2832 goto fail0; 2833 2834 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 2835 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 2836 if (rv != 0) { 2837 aprint_error( 2838 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 2839 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2840 goto fail0; 2841 } 2842 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 2843 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 2844 if (rv != 0) { 2845 aprint_error( 2846 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 2847 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2848 goto fail1; 2849 } 2850 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 2851 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 2852 if (rv != 0) { 2853 aprint_error( 2854 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 2855 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2856 goto fail2; 2857 } 2858 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 2859 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 2860 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 2861 &mvport->port_reqtbl[i].data_dmamap); 2862 if (rv != 0) { 2863 aprint_error("%s:%d:%d:" 2864 " EDMA data map(%d) create failed: error=%d\n", 2865 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 2866 rv); 2867 goto fail3; 2868 } 2869 } 2870 2871 return 0; 2872 2873 fail3: 2874 for (i--; i >= 0; i--) 2875 bus_dmamap_destroy(mvport->port_dmat, 2876 mvport->port_reqtbl[i].data_dmamap); 2877 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 2878 fail2: 2879 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 2880 fail1: 2881 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 2882 fail0: 2883 return rv; 2884 } 2885 2886 static int 2887 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 2888 { 2889 int hc, port, rv, i; 2890 2891 hc = mvport->port_hc->hc; 2892 port = mvport->port; 2893 2894 /* Create subregion for Shadow Registers Map */ 2895 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2896 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 2897 if (rv != 0) { 2898 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 2899 device_xname(MVSATA_DEV2(mvport)), hc, port); 2900 return rv; 2901 } 2902 wdr->cmd_iot = mvport->port_iot; 2903 2904 /* Once create subregion for each command registers */ 2905 for (i = 0; i < WDC_NREG; i++) { 2906 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2907 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 2908 if (rv != 0) { 2909 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2910 device_xname(MVSATA_DEV2(mvport)), hc, port); 2911 return rv; 2912 } 2913 } 2914 /* Create subregion for Alternate Status register */ 2915 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2916 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 2917 if (rv != 0) { 2918 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2919 device_xname(MVSATA_DEV2(mvport)), hc, port); 2920 return rv; 2921 } 2922 wdr->ctl_iot = mvport->port_iot; 2923 2924 wdc_init_shadow_regs(&mvport->port_ata_channel); 2925 2926 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2927 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 2928 if (rv != 0) { 2929 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 2930 device_xname(MVSATA_DEV2(mvport)), hc, port); 2931 return rv; 2932 } 2933 wdr->sata_iot = mvport->port_iot; 2934 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2935 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 2936 if (rv != 0) { 2937 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 2938 device_xname(MVSATA_DEV2(mvport)), hc, port); 2939 return rv; 2940 } 2941 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2942 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 2943 if (rv != 0) { 2944 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 2945 device_xname(MVSATA_DEV2(mvport)), hc, port); 2946 return rv; 2947 } 2948 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2949 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 2950 if (rv != 0) { 2951 aprint_error("%s:%d:%d: couldn't subregion SError\n", 2952 device_xname(MVSATA_DEV2(mvport)), hc, port); 2953 return rv; 2954 } 2955 2956 return 0; 2957 } 2958 2959 2960 #ifndef MVSATA_WITHOUTDMA 2961 /* 2962 * There are functions to determine Host Queue Tag. 2963 * XXXX: We hope to rotate Tag to facilitate debugging. 2964 */ 2965 2966 static inline void 2967 mvsata_quetag_init(struct mvsata_port *mvport) 2968 { 2969 2970 mvport->port_quetagidx = 0; 2971 } 2972 2973 static inline int 2974 mvsata_quetag_get(struct mvsata_port *mvport) 2975 { 2976 int begin = mvport->port_quetagidx; 2977 2978 do { 2979 if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) { 2980 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2981 return mvport->port_quetagidx; 2982 } 2983 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2984 } while (mvport->port_quetagidx != begin); 2985 2986 return -1; 2987 } 2988 2989 static inline void 2990 mvsata_quetag_put(struct mvsata_port *mvport, int quetag) 2991 { 2992 2993 /* nothing */ 2994 } 2995 2996 static void * 2997 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 2998 bus_dmamap_t *dmamap, size_t size, int write) 2999 { 3000 bus_dma_segment_t seg; 3001 int nseg, rv; 3002 void *kva; 3003 3004 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3005 BUS_DMA_NOWAIT); 3006 if (rv != 0) { 3007 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3008 device_xname(MVSATA_DEV2(mvport)), 3009 mvport->port_hc->hc, mvport->port, rv); 3010 goto fail; 3011 } 3012 3013 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3014 if (rv != 0) { 3015 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3016 device_xname(MVSATA_DEV2(mvport)), 3017 mvport->port_hc->hc, mvport->port, rv); 3018 goto free; 3019 } 3020 3021 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3022 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3023 if (rv != 0) { 3024 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3025 device_xname(MVSATA_DEV2(mvport)), 3026 mvport->port_hc->hc, mvport->port, rv); 3027 goto unmap; 3028 } 3029 3030 if (!write) 3031 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3032 3033 return kva; 3034 3035 unmap: 3036 bus_dmamem_unmap(dmat, kva, size); 3037 free: 3038 bus_dmamem_free(dmat, &seg, nseg); 3039 fail: 3040 return NULL; 3041 } 3042 3043 /* ARGSUSED */ 3044 static void 3045 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3046 bus_dmamap_t dmamap, void *kva) 3047 { 3048 3049 bus_dmamap_unload(dmat, dmamap); 3050 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3051 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3052 } 3053 3054 static int 3055 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3056 size_t datalen, int flags) 3057 { 3058 int rv, lop, sop; 3059 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3060 3061 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3062 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3063 3064 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3065 NULL, BUS_DMA_NOWAIT | lop); 3066 if (rv) { 3067 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3068 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3069 mvport->port, rv); 3070 return rv; 3071 } 3072 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3073 data_dmamap->dm_mapsize, sop); 3074 3075 return 0; 3076 } 3077 3078 static inline void 3079 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3080 { 3081 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3082 3083 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3084 data_dmamap->dm_mapsize, 3085 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3086 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3087 } 3088 #endif 3089 3090 static void 3091 mvsata_hreset_port(struct mvsata_port *mvport) 3092 { 3093 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3094 3095 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3096 3097 delay(25); /* allow reset propagation */ 3098 3099 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3100 3101 mvport->_fix_phy_param._fix_phy(mvport); 3102 3103 if (sc->sc_gen == gen1) 3104 delay(1000); 3105 } 3106 3107 static void 3108 mvsata_reset_port(struct mvsata_port *mvport) 3109 { 3110 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3111 3112 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3113 3114 mvsata_hreset_port(mvport); 3115 3116 if (device_is_a(parent, "pci")) 3117 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3118 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3119 else /* SoC */ 3120 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3121 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3122 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3123 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3124 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3125 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3126 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3127 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3128 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3129 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3130 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3131 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3132 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3133 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3134 3135 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3136 } 3137 3138 static void 3139 mvsata_reset_hc(struct mvsata_hc *mvhc) 3140 { 3141 #if 0 3142 uint32_t val; 3143 #endif 3144 3145 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3146 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3147 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3148 3149 #if 0 /* XXXX needs? */ 3150 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3151 3152 /* 3153 * Keep the SS during power on and the reference clock bits (reset 3154 * sample) 3155 */ 3156 val = MVSATA_HC_READ_4(mvhc, 0x020); 3157 val &= 0x1c1c1c1c; 3158 val |= 0x03030303; 3159 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3160 #endif 3161 } 3162 3163 #ifndef MVSATA_WITHOUTDMA 3164 static void 3165 mvsata_softreset(struct mvsata_port *mvport, int waitok) 3166 { 3167 uint32_t stat; 3168 int i; 3169 3170 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS); 3171 delay(10); 3172 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS); 3173 delay(2000); 3174 3175 if (waitok) { 3176 /* wait maximum 31sec */ 3177 for (i = 31000; i > 0; i--) { 3178 stat = MVSATA_WDC_READ_1(mvport, SRB_CS); 3179 if (!(stat & WDCS_BSY)) 3180 break; 3181 delay(1000); 3182 } 3183 if (i == 0) 3184 aprint_error("%s:%d:%d: soft reset failed\n", 3185 device_xname(MVSATA_DEV2(mvport)), 3186 mvport->port_hc->hc, mvport->port); 3187 } 3188 } 3189 3190 static void 3191 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3192 { 3193 const bus_addr_t crpb_addr = 3194 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3195 const uint32_t crpb_addr_mask = 3196 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3197 3198 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3199 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3200 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3201 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3202 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3203 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3204 } 3205 3206 static inline void 3207 mvsata_edma_enable(struct mvsata_port *mvport) 3208 { 3209 3210 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3211 } 3212 3213 static int 3214 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok) 3215 { 3216 uint32_t status, command; 3217 int ms; 3218 3219 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3220 for (ms = 0; ms < timeout; ms++) { 3221 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3222 if (status & EDMA_S_EDMAIDLE) 3223 break; 3224 if (waitok) 3225 tsleep(&waitok, PRIBIO, "mvsata_edma1", 3226 mstohz(1)); 3227 else 3228 delay(1000); 3229 } 3230 if (ms == timeout) 3231 return EBUSY; 3232 3233 /* The diable bit (eDsEDMA) is self negated. */ 3234 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3235 3236 for ( ; ms < timeout; ms++) { 3237 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3238 if (!(command & EDMA_CMD_EENEDMA)) 3239 break; 3240 if (waitok) 3241 tsleep(&waitok, PRIBIO, "mvsata_edma2", 3242 mstohz(1)); 3243 else 3244 delay(1000); 3245 } 3246 if (ms == timeout) { 3247 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3248 device_xname(MVSATA_DEV2(mvport)), 3249 mvport->port_hc->hc, mvport->port); 3250 return EBUSY; 3251 } 3252 } 3253 return 0; 3254 } 3255 3256 /* 3257 * Set EDMA registers according to mode. 3258 * ex. NCQ/TCQ(queued)/non queued. 3259 */ 3260 static void 3261 mvsata_edma_config(struct mvsata_port *mvport, int mode) 3262 { 3263 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3264 uint32_t reg; 3265 3266 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3267 reg |= EDMA_CFG_RESERVED; 3268 3269 if (mode == ncq) { 3270 if (sc->sc_gen == gen1) { 3271 aprint_error_dev(MVSATA_DEV2(mvport), 3272 "GenI not support NCQ\n"); 3273 return; 3274 } else if (sc->sc_gen == gen2) 3275 reg |= EDMA_CFG_EDEVERR; 3276 reg |= EDMA_CFG_ESATANATVCMDQUE; 3277 } else if (mode == queued) { 3278 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3279 reg |= EDMA_CFG_EQUE; 3280 } else 3281 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3282 3283 if (sc->sc_gen == gen1) 3284 reg |= EDMA_CFG_ERDBSZ; 3285 else if (sc->sc_gen == gen2) 3286 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3287 else if (sc->sc_gen == gen2e) { 3288 device_t parent = device_parent(MVSATA_DEV(sc)); 3289 3290 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3291 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3292 3293 if (device_is_a(parent, "pci")) 3294 reg |= ( 3295 #if NATAPIBUS > 0 3296 EDMA_CFG_EEARLYCOMPLETIONEN | 3297 #endif 3298 EDMA_CFG_ECUTTHROUGHEN | 3299 EDMA_CFG_EWRBUFFERLEN | 3300 EDMA_CFG_ERDBSZEXT); 3301 } 3302 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3303 3304 reg = ( 3305 EDMA_IE_EIORDYERR | 3306 EDMA_IE_ETRANSINT | 3307 EDMA_IE_EDEVCON | 3308 EDMA_IE_EDEVDIS); 3309 if (sc->sc_gen != gen1) 3310 reg |= ( 3311 EDMA_IE_TRANSPROTERR | 3312 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3313 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3314 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3315 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3316 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3317 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3318 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3319 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3320 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3321 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3322 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3323 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3324 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3325 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3326 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3327 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3328 EDMA_IE_ESELFDIS); 3329 3330 if (mode == ncq) 3331 reg |= EDMA_IE_EDEVERR; 3332 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3333 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3334 reg &= ~EDMA_IE_EDEVERR; 3335 if (mode != ncq) 3336 reg |= EDMA_IE_EDEVERR; 3337 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3338 if (sc->sc_gen == gen2e) { 3339 /* 3340 * Clear FISWait4HostRdyEn[0] and [2]. 3341 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3342 * [2]: SDB FIS is received with <ERR> bit set to 1. 3343 */ 3344 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3345 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3346 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3347 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3348 } 3349 3350 mvport->port_edmamode = mode; 3351 } 3352 3353 3354 /* 3355 * Generation dependent functions 3356 */ 3357 3358 static void 3359 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag, 3360 struct ata_bio *ata_bio) 3361 { 3362 struct crqb *crqb; 3363 bus_addr_t eprd_addr; 3364 daddr_t blkno; 3365 uint32_t rw; 3366 uint8_t cmd, head; 3367 int i; 3368 const int drive = 3369 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3370 3371 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3372 mvport->port_reqtbl[quetag].eprd_offset; 3373 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3374 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3375 head = WDSD_LBA; 3376 blkno = ata_bio->blkno; 3377 if (ata_bio->flags & ATA_LBA48) 3378 cmd = atacmd_to48(cmd); 3379 else { 3380 head |= ((ata_bio->blkno >> 24) & 0xf); 3381 blkno &= 0xffffff; 3382 } 3383 crqb = &mvport->port_crqb->crqb + erqqip; 3384 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3385 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3386 crqb->ctrlflg = 3387 htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive)); 3388 i = 0; 3389 if (mvport->port_edmamode == dma) { 3390 if (ata_bio->flags & ATA_LBA48) 3391 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3392 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3393 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3394 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3395 } else { /* ncq/queued */ 3396 3397 /* 3398 * XXXX: Oops, ata command is not correct. And, atabus layer 3399 * has not been supported yet now. 3400 * Queued DMA read/write. 3401 * read/write FPDMAQueued. 3402 */ 3403 3404 if (ata_bio->flags & ATA_LBA48) 3405 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3406 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3407 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3408 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3409 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3410 CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3)); 3411 } 3412 if (ata_bio->flags & ATA_LBA48) { 3413 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3414 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3415 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3416 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3417 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3418 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3419 } 3420 crqb->atacommand[i++] = 3421 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3422 crqb->atacommand[i++] = 3423 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3424 crqb->atacommand[i++] = 3425 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3426 crqb->atacommand[i++] = 3427 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3428 crqb->atacommand[i++] = htole16( 3429 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3430 CRQB_ATACOMMAND_LAST); 3431 } 3432 #endif 3433 3434 static uint32_t 3435 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3436 { 3437 struct mvsata_hc *hc = mvport->port_hc; 3438 uint32_t reg; 3439 3440 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3441 /* 3442 * [12:11] : pre 3443 * [7:5] : amps 3444 */ 3445 return reg & 0x000018e0; 3446 } 3447 3448 static void 3449 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3450 { 3451 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3452 struct mvsata_hc *mvhc = mvport->port_hc; 3453 uint32_t reg; 3454 int port = mvport->port, fix_apm_sq = 0; 3455 3456 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3457 if (sc->sc_rev == 0x01) 3458 fix_apm_sq = 1; 3459 } else { 3460 if (sc->sc_rev == 0x00) 3461 fix_apm_sq = 1; 3462 } 3463 3464 if (fix_apm_sq) { 3465 /* 3466 * Disable auto-power management 3467 * 88SX50xx FEr SATA#12 3468 */ 3469 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3470 reg |= (1 << 19); 3471 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3472 3473 /* 3474 * Fix squelch threshold 3475 * 88SX50xx FEr SATA#9 3476 */ 3477 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3478 reg &= ~0x3; 3479 reg |= 0x1; 3480 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3481 } 3482 3483 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3484 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3485 reg &= ~0x000018e0; /* pre and amps mask */ 3486 reg |= mvport->_fix_phy_param.pre_amps; 3487 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3488 } 3489 3490 static void 3491 mvsata_devconn_gen1(struct mvsata_port *mvport) 3492 { 3493 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3494 3495 /* Fix for 88SX50xx FEr SATA#2 */ 3496 mvport->_fix_phy_param._fix_phy(mvport); 3497 3498 /* If disk is connected, then enable the activity LED */ 3499 if (sc->sc_rev == 0x03) { 3500 /* XXXXX */ 3501 } 3502 } 3503 3504 static uint32_t 3505 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3506 { 3507 uint32_t reg; 3508 3509 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3510 /* 3511 * [10:8] : amps 3512 * [7:5] : pre 3513 */ 3514 return reg & 0x000007e0; 3515 } 3516 3517 static void 3518 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3519 { 3520 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3521 uint32_t reg; 3522 3523 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3524 sc->sc_gen == gen2e) { 3525 /* 3526 * Fix for 3527 * 88SX60X1 FEr SATA #23 3528 * 88SX6042/88SX7042 FEr SATA #23 3529 * 88F5182 FEr #SATA-S13 3530 * 88F5082 FEr #SATA-S13 3531 */ 3532 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3533 reg &= ~(1 << 16); 3534 reg |= (1 << 31); 3535 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3536 3537 delay(200); 3538 3539 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3540 reg &= ~((1 << 16) | (1 << 31)); 3541 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3542 3543 delay(200); 3544 } 3545 3546 /* Fix values in PHY Mode 3 Register.*/ 3547 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3548 reg &= ~0x7F900000; 3549 reg |= 0x2A800000; 3550 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3551 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3552 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3553 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3554 reg &= ~0x0000001c; 3555 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3556 3557 /* 3558 * Fix values in PHY Mode 4 Register. 3559 * 88SX60x1 FEr SATA#10 3560 * 88F5182 GL #SATA-S10 3561 * 88F5082 GL #SATA-S10 3562 */ 3563 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3564 sc->sc_gen == gen2e) { 3565 uint32_t tmp = 0; 3566 3567 /* 88SX60x1 FEr SATA #13 */ 3568 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3569 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3570 3571 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3572 reg |= (1 << 0); 3573 reg &= ~(1 << 1); 3574 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3575 if (sc->sc_gen == gen2e) { 3576 reg &= ~0x5de3fffc; 3577 reg |= (1 << 2); 3578 } 3579 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3580 3581 /* 88SX60x1 FEr SATA #13 */ 3582 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3583 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3584 } 3585 3586 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3587 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3588 reg &= ~0x000007e0; /* pre and amps mask */ 3589 reg |= mvport->_fix_phy_param.pre_amps; 3590 reg &= ~(1 << 16); 3591 if (sc->sc_gen == gen2e) { 3592 /* 3593 * according to mvSata 3.6.1, some IIE values are fixed. 3594 * some reserved fields must be written with fixed values. 3595 */ 3596 reg &= ~0xC30FF01F; 3597 reg |= 0x0000900F; 3598 } 3599 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3600 } 3601 3602 #ifndef MVSATA_WITHOUTDMA 3603 static void 3604 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag, 3605 struct ata_bio *ata_bio) 3606 { 3607 struct crqb_gen2e *crqb; 3608 bus_addr_t eprd_addr; 3609 daddr_t blkno; 3610 uint32_t ctrlflg, rw; 3611 uint8_t cmd, head; 3612 const int drive = 3613 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3614 3615 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3616 mvport->port_reqtbl[quetag].eprd_offset; 3617 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3618 ctrlflg = (rw | CRQB_CDEVICEQUETAG(quetag) | CRQB_CPMPORT(drive) | 3619 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag)); 3620 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3621 head = WDSD_LBA; 3622 blkno = ata_bio->blkno; 3623 if (ata_bio->flags & ATA_LBA48) 3624 cmd = atacmd_to48(cmd); 3625 else { 3626 head |= ((ata_bio->blkno >> 24) & 0xf); 3627 blkno &= 0xffffff; 3628 } 3629 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3630 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3631 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3632 crqb->ctrlflg = htole32(ctrlflg); 3633 if (mvport->port_edmamode == dma) { 3634 crqb->atacommand[0] = htole32(cmd << 16); 3635 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3636 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff)); 3637 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3638 } else { /* ncq/queued */ 3639 3640 /* 3641 * XXXX: Oops, ata command is not correct. And, atabus layer 3642 * has not been supported yet now. 3643 * Queued DMA read/write. 3644 * read/write FPDMAQueued. 3645 */ 3646 3647 crqb->atacommand[0] = htole32( 3648 (cmd << 16) | ((ata_bio->nblks & 0xff) << 24)); 3649 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3650 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) | 3651 ((ata_bio->nblks >> 8) & 0xff)); 3652 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3653 crqb->atacommand[3] = htole32(quetag << 3); 3654 } 3655 } 3656 3657 3658 #ifdef MVSATA_DEBUG 3659 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3660 do { \ 3661 int _i; \ 3662 u_char *_p = (p); \ 3663 \ 3664 printf(#type "(%d)", (n)); \ 3665 for (_i = 0; _i < (size); _i++, _p++) { \ 3666 if (_i % 16 == 0) \ 3667 printf("\n "); \ 3668 printf(" %02x", *_p); \ 3669 } \ 3670 printf("\n"); \ 3671 } while (0 /* CONSTCOND */) 3672 3673 static void 3674 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3675 { 3676 3677 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3678 n, (u_char *)(mvport->port_crqb + n)); 3679 } 3680 3681 static void 3682 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3683 { 3684 3685 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3686 n, (u_char *)(mvport->port_crpb + n)); 3687 } 3688 3689 static void 3690 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3691 { 3692 struct eprd *eprd; 3693 int i = 0; 3694 3695 eprd = mvport->port_reqtbl[n].eprd; 3696 while (1 /*CONSTCOND*/) { 3697 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3698 i, (u_char *)eprd); 3699 if (eprd->eot & EPRD_EOT) 3700 break; 3701 eprd++; 3702 i++; 3703 } 3704 } 3705 #endif 3706 #endif 3707
Indexes created Thu Sep 25 06:09:39 GMT 2025