mvsata.c revision 1.24
1 /* $NetBSD: mvsata.c,v 1.24 2012/07/31 15:50:34 bouyer Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.24 2012/07/31 15:50:34 bouyer Exp $"); 30 31 #include "opt_mvsata.h" 32 33 /* ATAPI implementation not finished. */ 34 //#include "atapibus.h" 35 36 #include <sys/param.h> 37 #if NATAPIBUS > 0 38 #include <sys/buf.h> 39 #endif 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/disklabel.h> 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 49 #include <machine/vmparam.h> 50 51 #include <dev/ata/atareg.h> 52 #include <dev/ata/atavar.h> 53 #include <dev/ic/wdcvar.h> 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 57 #if NATAPIBUS > 0 58 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 59 #endif 60 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ic/mvsatareg.h> 64 #include <dev/ic/mvsatavar.h> 65 66 67 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 68 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 69 70 #define MVSATA_HC_READ_4(hc, reg) \ 71 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 72 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 73 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 74 #define MVSATA_EDMA_READ_4(mvport, reg) \ 75 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 76 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 77 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 78 #define MVSATA_WDC_READ_2(mvport, reg) \ 79 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 80 SHADOW_REG_BLOCK_OFFSET + (reg)) 81 #define MVSATA_WDC_READ_1(mvport, reg) \ 82 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 83 SHADOW_REG_BLOCK_OFFSET + (reg)) 84 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 85 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 86 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 87 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 88 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 89 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 90 91 #ifdef MVSATA_DEBUG 92 #define DPRINTF(x) if (mvsata_debug) printf x 93 #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x 94 int mvsata_debug = 2; 95 #else 96 #define DPRINTF(x) 97 #define DPRINTFN(n,x) 98 #endif 99 100 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 101 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 102 sending a cmd */ 103 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 104 105 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 106 107 108 #ifndef MVSATA_WITHOUTDMA 109 static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *); 110 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 111 static void mvsata_reset_channel(struct ata_channel *, int); 112 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *); 113 static int mvsata_addref(struct ata_drive_datas *); 114 static void mvsata_delref(struct ata_drive_datas *); 115 static void mvsata_killpending(struct ata_drive_datas *); 116 117 #if NATAPIBUS > 0 118 static void mvsata_atapibus_attach(struct atabus_softc *); 119 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 120 scsipi_adapter_req_t, void *); 121 static void mvsata_atapi_minphys(struct buf *); 122 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 123 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 124 #endif 125 #endif 126 127 static void mvsata_setup_channel(struct ata_channel *); 128 129 #ifndef MVSATA_WITHOUTDMA 130 static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 131 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 132 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 133 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 134 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 135 int); 136 static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 137 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 138 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 139 int); 140 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 141 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 142 #if NATAPIBUS > 0 143 static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 144 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 145 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 146 int); 147 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 148 static void mvsata_atapi_phase_complete(struct ata_xfer *); 149 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 150 static void mvsata_atapi_polldsc(void *); 151 #endif 152 153 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_bio *, void *); 154 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 155 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 156 static void mvsata_edma_timeout(void *); 157 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 158 #if NATAPIBUS > 0 159 static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *); 160 static void mvsata_bdma_start(struct mvsata_port *); 161 #endif 162 #endif 163 164 static int mvsata_port_init(struct mvsata_hc *, int); 165 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 166 #ifndef MVSATA_WITHOUTDMA 167 static inline void mvsata_quetag_init(struct mvsata_port *); 168 static inline int mvsata_quetag_get(struct mvsata_port *); 169 static inline void mvsata_quetag_put(struct mvsata_port *, int); 170 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 171 bus_dmamap_t *, size_t, int); 172 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 173 bus_dmamap_t, void *); 174 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 175 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 176 #endif 177 178 static void mvsata_hreset_port(struct mvsata_port *); 179 static void mvsata_reset_port(struct mvsata_port *); 180 static void mvsata_reset_hc(struct mvsata_hc *); 181 #ifndef MVSATA_WITHOUTDMA 182 static void mvsata_softreset(struct mvsata_port *, int); 183 static void mvsata_edma_reset_qptr(struct mvsata_port *); 184 static inline void mvsata_edma_enable(struct mvsata_port *); 185 static int mvsata_edma_disable(struct mvsata_port *, int, int); 186 static void mvsata_edma_config(struct mvsata_port *, int); 187 188 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int, 189 struct ata_bio *); 190 #endif 191 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 192 static void mvsata_fix_phy_gen1(struct mvsata_port *); 193 static void mvsata_devconn_gen1(struct mvsata_port *); 194 195 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 196 static void mvsata_fix_phy_gen2(struct mvsata_port *); 197 #ifndef MVSATA_WITHOUTDMA 198 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int, 199 struct ata_bio *); 200 201 #ifdef MVSATA_DEBUG 202 static void mvsata_print_crqb(struct mvsata_port *, int); 203 static void mvsata_print_crpb(struct mvsata_port *, int); 204 static void mvsata_print_eprd(struct mvsata_port *, int); 205 #endif 206 207 208 struct ata_bustype mvsata_ata_bustype = { 209 SCSIPI_BUSTYPE_ATA, 210 mvsata_bio, 211 mvsata_reset_drive, 212 mvsata_reset_channel, 213 mvsata_exec_command, 214 ata_get_params, 215 mvsata_addref, 216 mvsata_delref, 217 mvsata_killpending 218 }; 219 220 #if NATAPIBUS > 0 221 static const struct scsipi_bustype mvsata_atapi_bustype = { 222 SCSIPI_BUSTYPE_ATAPI, 223 atapi_scsipi_cmd, 224 atapi_interpret_sense, 225 atapi_print_addr, 226 mvsata_atapi_kill_pending, 227 NULL, 228 }; 229 #endif /* NATAPIBUS */ 230 #endif 231 232 233 int 234 mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product, 235 int (*mvsata_sreset)(struct mvsata_softc *), 236 int (*mvsata_misc_reset)(struct mvsata_softc *), 237 int read_pre_amps) 238 { 239 struct mvsata_hc *mvhc; 240 struct mvsata_port *mvport; 241 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 242 void (*_fix_phy)(struct mvsata_port *) = NULL; 243 #ifndef MVSATA_WITHOUTDMA 244 void (*edma_setup_crqb) 245 (struct mvsata_port *, int, int, struct ata_bio *) = NULL; 246 #endif 247 int hc, port, channel; 248 249 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 250 (product->generation == gen1) ? "I" : 251 ((product->generation == gen2) ? "II" : "IIe"), 252 product->hc, product->port); 253 254 255 switch (product->generation) { 256 case gen1: 257 mvsata_sreset = NULL; 258 read_pre_amps = 1; /* MUST */ 259 read_preamps = mvsata_read_preamps_gen1; 260 _fix_phy = mvsata_fix_phy_gen1; 261 #ifndef MVSATA_WITHOUTDMA 262 edma_setup_crqb = mvsata_edma_setup_crqb; 263 #endif 264 break; 265 266 case gen2: 267 read_preamps = mvsata_read_preamps_gen2; 268 _fix_phy = mvsata_fix_phy_gen2; 269 #ifndef MVSATA_WITHOUTDMA 270 edma_setup_crqb = mvsata_edma_setup_crqb; 271 #endif 272 break; 273 274 case gen2e: 275 read_preamps = mvsata_read_preamps_gen2; 276 _fix_phy = mvsata_fix_phy_gen2; 277 #ifndef MVSATA_WITHOUTDMA 278 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 279 #endif 280 break; 281 } 282 283 sc->sc_gen = product->generation; 284 sc->sc_hc = product->hc; 285 sc->sc_port = product->port; 286 sc->sc_flags = product->flags; 287 288 #ifdef MVSATA_WITHOUTDMA 289 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 290 #else 291 sc->sc_edma_setup_crqb = edma_setup_crqb; 292 sc->sc_wdcdev.sc_atac.atac_cap |= 293 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 294 #endif 295 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 296 #ifdef MVSATA_WITHOUTDMA 297 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 298 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 299 #else 300 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 301 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 302 #endif 303 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 304 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 305 #ifndef MVSATA_WITHOUTDMA 306 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 307 #if NATAPIBUS > 0 308 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 309 #endif 310 #endif 311 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 312 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 313 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 314 315 sc->sc_wdc_regs = 316 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 317 M_DEVBUF, M_NOWAIT); 318 if (sc->sc_wdc_regs == NULL) { 319 aprint_error_dev(MVSATA_DEV(sc), 320 "can't allocate wdc regs memory\n"); 321 return ENOMEM; 322 } 323 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 324 325 for (hc = 0; hc < sc->sc_hc; hc++) { 326 mvhc = &sc->sc_hcs[hc]; 327 mvhc->hc = hc; 328 mvhc->hc_sc = sc; 329 mvhc->hc_iot = sc->sc_iot; 330 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 331 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 332 &mvhc->hc_ioh)) { 333 aprint_error_dev(MVSATA_DEV(sc), 334 "can't subregion SATAHC %d registers\n", hc); 335 continue; 336 } 337 338 for (port = 0; port < sc->sc_port; port++) 339 if (mvsata_port_init(mvhc, port) == 0) { 340 int pre_amps; 341 342 mvport = mvhc->hc_ports[port]; 343 pre_amps = read_pre_amps ? 344 read_preamps(mvport) : 0x00000720; 345 mvport->_fix_phy_param.pre_amps = pre_amps; 346 mvport->_fix_phy_param._fix_phy = _fix_phy; 347 348 if (!mvsata_sreset) 349 mvsata_reset_port(mvport); 350 } 351 352 if (!mvsata_sreset) 353 mvsata_reset_hc(mvhc); 354 } 355 if (mvsata_sreset) 356 mvsata_sreset(sc); 357 358 if (mvsata_misc_reset) 359 mvsata_misc_reset(sc); 360 361 for (hc = 0; hc < sc->sc_hc; hc++) 362 for (port = 0; port < sc->sc_port; port++) { 363 mvport = sc->sc_hcs[hc].hc_ports[port]; 364 if (mvport == NULL) 365 continue; 366 if (mvsata_sreset) 367 mvport->_fix_phy_param._fix_phy(mvport); 368 } 369 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 370 wdcattach(sc->sc_ata_channels[channel]); 371 372 return 0; 373 } 374 375 int 376 mvsata_intr(struct mvsata_hc *mvhc) 377 { 378 struct mvsata_softc *sc = mvhc->hc_sc; 379 struct mvsata_port *mvport; 380 uint32_t cause; 381 int port, handled = 0; 382 383 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 384 385 DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n", 386 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 387 388 if (cause & SATAHC_IC_SAINTCOAL) 389 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 390 cause &= ~SATAHC_IC_SAINTCOAL; 391 for (port = 0; port < sc->sc_port; port++) { 392 mvport = mvhc->hc_ports[port]; 393 394 if (cause & SATAHC_IC_DONE(port)) { 395 #ifndef MVSATA_WITHOUTDMA 396 handled = mvsata_edma_handle(mvport, NULL); 397 #endif 398 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 399 ~SATAHC_IC_DONE(port)); 400 } 401 402 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 403 wdcintr(&mvport->port_ata_channel); 404 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 405 ~SATAHC_IC_SADEVINTERRUPT(port)); 406 handled = 1; 407 } 408 } 409 410 return handled; 411 } 412 413 int 414 mvsata_error(struct mvsata_port *mvport) 415 { 416 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 417 uint32_t cause; 418 int handled = 0; 419 420 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 421 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 422 423 DPRINTFN(3, ("%s:%d:%d:" 424 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 425 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 426 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 427 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 428 429 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 430 if (!cause) 431 return 0; 432 433 /* If PM connected, connect/disconnect interrupts storm could happen */ 434 if (MVSATA_EDMA_READ_4(mvport, EDMA_IEC) & 435 (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) 436 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 437 delay(20 * 1000); 438 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 439 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 440 } 441 442 if (cause & EDMA_IE_EDEVDIS) 443 aprint_normal("%s:%d:%d: device disconnect\n", 444 device_xname(MVSATA_DEV2(mvport)), 445 mvport->port_hc->hc, mvport->port); 446 if (cause & EDMA_IE_EDEVCON) { 447 if (sc->sc_gen == gen1) 448 mvsata_devconn_gen1(mvport); 449 450 DPRINTFN(3, (" device connected\n")); 451 handled = 1; 452 } 453 #ifndef MVSATA_WITHOUTDMA 454 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 455 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 456 switch (mvport->port_edmamode) { 457 case dma: 458 case queued: 459 case ncq: 460 mvsata_edma_reset_qptr(mvport); 461 mvsata_edma_enable(mvport); 462 if (cause & EDMA_IE_EDEVERR) 463 break; 464 465 /* FALLTHROUGH */ 466 467 case nodma: 468 default: 469 aprint_error( 470 "%s:%d:%d: EDMA self disable happen 0x%x\n", 471 device_xname(MVSATA_DEV2(mvport)), 472 mvport->port_hc->hc, mvport->port, cause); 473 break; 474 } 475 handled = 1; 476 } 477 #endif 478 if (cause & EDMA_IE_ETRANSINT) { 479 /* hot plug the Port Multiplier */ 480 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 481 device_xname(MVSATA_DEV2(mvport)), 482 mvport->port_hc->hc, mvport->port); 483 } 484 485 return handled; 486 } 487 488 489 /* 490 * ATA callback entry points 491 */ 492 493 #ifndef MVSATA_WITHOUTDMA 494 static int 495 mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 496 { 497 struct ata_channel *chp = drvp->chnl_softc; 498 struct atac_softc *atac = chp->ch_atac; 499 struct ata_xfer *xfer; 500 501 DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 502 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 503 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 504 505 xfer = ata_get_xfer(ATAXF_NOSLEEP); 506 if (xfer == NULL) 507 return ATACMD_TRY_AGAIN; 508 if (atac->atac_cap & ATAC_CAP_NOIRQ) 509 ata_bio->flags |= ATA_POLL; 510 if (ata_bio->flags & ATA_POLL) 511 xfer->c_flags |= C_POLL; 512 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 513 (ata_bio->flags & ATA_SINGLE) == 0) 514 xfer->c_flags |= C_DMA; 515 xfer->c_drive = drvp->drive; 516 xfer->c_cmd = ata_bio; 517 xfer->c_databuf = ata_bio->databuf; 518 xfer->c_bcount = ata_bio->bcount; 519 xfer->c_start = mvsata_bio_start; 520 xfer->c_intr = mvsata_bio_intr; 521 xfer->c_kill_xfer = mvsata_bio_kill_xfer; 522 ata_exec_xfer(chp, xfer); 523 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 524 } 525 526 static void 527 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 528 { 529 struct ata_channel *chp = drvp->chnl_softc; 530 struct mvsata_port *mvport = (struct mvsata_port *)chp; 531 uint32_t edma_c; 532 533 KASSERT(sigp == NULL); 534 535 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 536 537 DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 538 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 539 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 540 541 if (edma_c & EDMA_CMD_EENEDMA) 542 mvsata_edma_disable(mvport, 10000, flags & AT_WAIT); 543 544 mvsata_softreset(mvport, flags & AT_WAIT); 545 546 if (edma_c & EDMA_CMD_EENEDMA) { 547 mvsata_edma_reset_qptr(mvport); 548 mvsata_edma_enable(mvport); 549 } 550 return; 551 } 552 553 static void 554 mvsata_reset_channel(struct ata_channel *chp, int flags) 555 { 556 struct mvsata_port *mvport = (struct mvsata_port *)chp; 557 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 558 struct ata_xfer *xfer; 559 uint32_t sstat, ctrl; 560 int i; 561 562 DPRINTF(("%s: mvsata_reset_channel: channel=%d\n", 563 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 564 565 mvsata_hreset_port(mvport); 566 sstat = sata_reset_interface(chp, mvport->port_iot, 567 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 568 569 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 570 sc->sc_gen != gen1) { 571 /* Downgrade to GenI */ 572 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 573 SControl_DET_DISABLE; 574 575 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 576 577 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 578 ctrl &= ~(1 << 17); /* Disable GenII */ 579 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 580 581 mvsata_hreset_port(mvport); 582 sata_reset_interface(chp, mvport->port_iot, 583 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 584 } 585 586 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 587 xfer = mvport->port_reqtbl[i].xfer; 588 if (xfer == NULL) 589 continue; 590 chp->ch_queue->active_xfer = xfer; 591 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 592 } 593 594 mvsata_edma_config(mvport, mvport->port_edmamode); 595 mvsata_edma_reset_qptr(mvport); 596 mvsata_edma_enable(mvport); 597 return; 598 } 599 600 601 static int 602 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 603 { 604 struct ata_channel *chp = drvp->chnl_softc; 605 #ifdef MVSATA_DEBUG 606 struct mvsata_port *mvport = (struct mvsata_port *)chp; 607 #endif 608 struct ata_xfer *xfer; 609 int rv, s; 610 611 DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 612 " r_command=0x%x, r_head=0x%x, r_cyl=0x%x, r_sector=0x%x," 613 " r_count=0x%x, r_features=0x%x\n", 614 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 615 drvp->drive, ata_c->bcount, ata_c->r_command, ata_c->r_head, 616 ata_c->r_cyl, ata_c->r_sector, ata_c->r_count, ata_c->r_features)); 617 618 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 619 ATAXF_NOSLEEP); 620 if (xfer == NULL) 621 return ATACMD_TRY_AGAIN; 622 if (ata_c->flags & AT_POLL) 623 xfer->c_flags |= C_POLL; 624 if (ata_c->flags & AT_WAIT) 625 xfer->c_flags |= C_WAIT; 626 xfer->c_drive = drvp->drive; 627 xfer->c_databuf = ata_c->data; 628 xfer->c_bcount = ata_c->bcount; 629 xfer->c_cmd = ata_c; 630 xfer->c_start = mvsata_wdc_cmd_start; 631 xfer->c_intr = mvsata_wdc_cmd_intr; 632 xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer; 633 s = splbio(); 634 ata_exec_xfer(chp, xfer); 635 #ifdef DIAGNOSTIC 636 if ((ata_c->flags & AT_POLL) != 0 && 637 (ata_c->flags & AT_DONE) == 0) 638 panic("mvsata_exec_command: polled command not done"); 639 #endif 640 if (ata_c->flags & AT_DONE) 641 rv = ATACMD_COMPLETE; 642 else { 643 if (ata_c->flags & AT_WAIT) { 644 while ((ata_c->flags & AT_DONE) == 0) 645 tsleep(ata_c, PRIBIO, "mvsatacmd", 0); 646 rv = ATACMD_COMPLETE; 647 } else 648 rv = ATACMD_QUEUED; 649 } 650 splx(s); 651 return rv; 652 } 653 654 static int 655 mvsata_addref(struct ata_drive_datas *drvp) 656 { 657 658 return 0; 659 } 660 661 static void 662 mvsata_delref(struct ata_drive_datas *drvp) 663 { 664 665 return; 666 } 667 668 static void 669 mvsata_killpending(struct ata_drive_datas *drvp) 670 { 671 672 return; 673 } 674 675 #if NATAPIBUS > 0 676 static void 677 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 678 { 679 struct ata_channel *chp = ata_sc->sc_chan; 680 struct atac_softc *atac = chp->ch_atac; 681 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 682 struct scsipi_channel *chan = &chp->ch_atapi_channel; 683 684 /* 685 * Fill in the scsipi_adapter. 686 */ 687 adapt->adapt_dev = atac->atac_dev; 688 adapt->adapt_nchannels = atac->atac_nchannels; 689 adapt->adapt_request = mvsata_atapi_scsipi_request; 690 adapt->adapt_minphys = mvsata_atapi_minphys; 691 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 692 693 /* 694 * Fill in the scsipi_channel. 695 */ 696 memset(chan, 0, sizeof(*chan)); 697 chan->chan_adapter = adapt; 698 chan->chan_bustype = &mvsata_atapi_bustype; 699 chan->chan_channel = chp->ch_channel; 700 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 701 chan->chan_openings = 1; 702 chan->chan_max_periph = 1; 703 chan->chan_ntargets = 1; 704 chan->chan_nluns = 1; 705 706 chp->atapibus = 707 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 708 } 709 710 static void 711 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 712 scsipi_adapter_req_t req, void *arg) 713 { 714 struct scsipi_adapter *adapt = chan->chan_adapter; 715 struct scsipi_periph *periph; 716 struct scsipi_xfer *sc_xfer; 717 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 718 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 719 struct ata_xfer *xfer; 720 int channel = chan->chan_channel; 721 int drive, s; 722 723 switch (req) { 724 case ADAPTER_REQ_RUN_XFER: 725 sc_xfer = arg; 726 periph = sc_xfer->xs_periph; 727 drive = periph->periph_target; 728 729 if (!device_is_active(atac->atac_dev)) { 730 sc_xfer->error = XS_DRIVER_STUFFUP; 731 scsipi_done(sc_xfer); 732 return; 733 } 734 xfer = ata_get_xfer(ATAXF_NOSLEEP); 735 if (xfer == NULL) { 736 sc_xfer->error = XS_RESOURCE_SHORTAGE; 737 scsipi_done(sc_xfer); 738 return; 739 } 740 741 if (sc_xfer->xs_control & XS_CTL_POLL) 742 xfer->c_flags |= C_POLL; 743 xfer->c_drive = drive; 744 xfer->c_flags |= C_ATAPI; 745 xfer->c_cmd = sc_xfer; 746 xfer->c_databuf = sc_xfer->data; 747 xfer->c_bcount = sc_xfer->datalen; 748 xfer->c_start = mvsata_atapi_start; 749 xfer->c_intr = mvsata_atapi_intr; 750 xfer->c_kill_xfer = mvsata_atapi_kill_xfer; 751 xfer->c_dscpoll = 0; 752 s = splbio(); 753 ata_exec_xfer(atac->atac_channels[channel], xfer); 754 #ifdef DIAGNOSTIC 755 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 756 (sc_xfer->xs_status & XS_STS_DONE) == 0) 757 panic("mvsata_atapi_scsipi_request:" 758 " polled command not done"); 759 #endif 760 splx(s); 761 return; 762 763 default: 764 /* Not supported, nothing to do. */ 765 ; 766 } 767 } 768 769 static void 770 mvsata_atapi_minphys(struct buf *bp) 771 { 772 773 if (bp->b_bcount > MAXPHYS) 774 bp->b_bcount = MAXPHYS; 775 minphys(bp); 776 } 777 778 static void 779 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 780 { 781 struct scsipi_channel *chan = sc->sc_channel; 782 struct scsipi_periph *periph; 783 struct ataparams ids; 784 struct ataparams *id = &ids; 785 struct mvsata_softc *mvc = 786 device_private(chan->chan_adapter->adapt_dev); 787 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 788 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 789 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 790 struct scsipibus_attach_args sa; 791 char serial_number[21], model[41], firmware_revision[9]; 792 int s; 793 794 /* skip if already attached */ 795 if (scsipi_lookup_periph(chan, target, 0) != NULL) 796 return; 797 798 /* if no ATAPI device detected at attach time, skip */ 799 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 800 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 801 " drive %d not present\n", 802 device_xname(atac->atac_dev), chp->ch_channel, target)); 803 return; 804 } 805 806 /* Some ATAPI devices need a bit more time after software reset. */ 807 delay(5000); 808 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 809 #ifdef ATAPI_DEBUG_PROBE 810 log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n", 811 device_xname(atac->atac_dev), chp->ch_channel, target, 812 id->atap_config & ATAPI_CFG_CMD_MASK, 813 id->atap_config & ATAPI_CFG_DRQ_MASK); 814 #endif 815 periph = scsipi_alloc_periph(M_NOWAIT); 816 if (periph == NULL) { 817 aprint_error_dev(atac->atac_dev, 818 "unable to allocate periph" 819 " for channel %d drive %d\n", 820 chp->ch_channel, target); 821 return; 822 } 823 periph->periph_dev = NULL; 824 periph->periph_channel = chan; 825 periph->periph_switch = &atapi_probe_periphsw; 826 periph->periph_target = target; 827 periph->periph_lun = 0; 828 periph->periph_quirks = PQUIRK_ONLYBIG; 829 830 #ifdef SCSIPI_DEBUG 831 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 832 SCSIPI_DEBUG_TARGET == target) 833 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 834 #endif 835 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 836 if (id->atap_config & ATAPI_CFG_REMOV) 837 periph->periph_flags |= PERIPH_REMOVABLE; 838 if (periph->periph_type == T_SEQUENTIAL) { 839 s = splbio(); 840 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 841 splx(s); 842 } 843 844 sa.sa_periph = periph; 845 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 846 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 847 T_REMOV : T_FIXED; 848 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 849 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 20); 850 scsipi_strvis((u_char *)firmware_revision, 8, id->atap_revision, 851 8); 852 sa.sa_inqbuf.vendor = model; 853 sa.sa_inqbuf.product = serial_number; 854 sa.sa_inqbuf.revision = firmware_revision; 855 856 /* 857 * Determine the operating mode capabilities of the device. 858 */ 859 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 860 periph->periph_cap |= PERIPH_CAP_CMD16; 861 /* XXX This is gross. */ 862 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 863 864 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 865 866 if (drvp->drv_softc) 867 ata_probe_caps(drvp); 868 else { 869 s = splbio(); 870 drvp->drive_type = ATA_DRIVET_NONE; 871 splx(s); 872 } 873 } else { 874 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 875 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n", 876 device_xname(atac->atac_dev), chp->ch_channel, target, 877 chp->ch_error)); 878 s = splbio(); 879 drvp->drive_type = ATA_DRIVET_NONE; 880 splx(s); 881 } 882 } 883 884 /* 885 * Kill off all pending xfers for a periph. 886 * 887 * Must be called at splbio(). 888 */ 889 static void 890 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 891 { 892 struct atac_softc *atac = 893 device_private(periph->periph_channel->chan_adapter->adapt_dev); 894 struct ata_channel *chp = 895 atac->atac_channels[periph->periph_channel->chan_channel]; 896 897 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 898 } 899 #endif /* NATAPIBUS > 0 */ 900 #endif /* MVSATA_WITHOUTDMA */ 901 902 903 /* 904 * mvsata_setup_channel() 905 * Setup EDMA registers and prepare/purge DMA resources. 906 * We assuming already stopped the EDMA. 907 */ 908 static void 909 mvsata_setup_channel(struct ata_channel *chp) 910 { 911 #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG) 912 struct mvsata_port *mvport = (struct mvsata_port *)chp; 913 #endif 914 struct ata_drive_datas *drvp; 915 uint32_t edma_mode; 916 int drive, s; 917 #ifndef MVSATA_WITHOUTDMA 918 int i; 919 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 920 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 921 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 922 #endif 923 924 DPRINTF(("%s:%d: mvsata_setup_channel: ", 925 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 926 927 edma_mode = nodma; 928 for (drive = 0; drive < chp->ch_ndrives; drive++) { 929 drvp = &chp->ch_drive[drive]; 930 931 /* If no drive, skip */ 932 if (drvp->drive_type == ATA_DRIVET_NONE) 933 continue; 934 935 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 936 /* use Ultra/DMA */ 937 s = splbio(); 938 drvp->drive_flags &= ~ATA_DRIVE_DMA; 939 splx(s); 940 } 941 942 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) 943 if (drvp->drive_type == ATA_DRIVET_ATA) 944 edma_mode = dma; 945 } 946 947 DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 948 949 #ifndef MVSATA_WITHOUTDMA 950 if (edma_mode == nodma) { 951 no_edma: 952 if (mvport->port_crqb != NULL) 953 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 954 mvport->port_crqb_dmamap, mvport->port_crqb); 955 if (mvport->port_crpb != NULL) 956 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 957 mvport->port_crpb_dmamap, mvport->port_crpb); 958 if (mvport->port_eprd != NULL) 959 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 960 mvport->port_eprd_dmamap, mvport->port_eprd); 961 962 return; 963 } 964 965 if (mvport->port_crqb == NULL) 966 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 967 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 968 if (mvport->port_crpb == NULL) 969 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 970 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 971 if (mvport->port_eprd == NULL) { 972 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 973 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 974 1); 975 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 976 mvport->port_reqtbl[i].eprd_offset = 977 i * MVSATA_EPRD_MAX_SIZE; 978 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 979 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 980 } 981 } 982 983 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 984 mvport->port_eprd == NULL) { 985 aprint_error_dev(MVSATA_DEV2(mvport), 986 "channel %d: can't use EDMA\n", chp->ch_channel); 987 s = splbio(); 988 for (drive = 0; drive < chp->ch_ndrives; drive++) { 989 drvp = &chp->ch_drive[drive]; 990 991 /* If no drive, skip */ 992 if (drvp->drive_type == ATA_DRIVET_NONE) 993 continue; 994 995 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 996 } 997 splx(s); 998 goto no_edma; 999 } 1000 1001 mvsata_edma_config(mvport, edma_mode); 1002 mvsata_edma_reset_qptr(mvport); 1003 mvsata_edma_enable(mvport); 1004 #endif 1005 } 1006 1007 #ifndef MVSATA_WITHOUTDMA 1008 static void 1009 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1010 { 1011 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1012 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1013 struct atac_softc *atac = chp->ch_atac; 1014 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1015 struct ata_bio *ata_bio = xfer->c_cmd; 1016 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1017 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1018 u_int16_t cyl; 1019 u_int8_t head, sect, cmd = 0; 1020 int nblks, error; 1021 1022 DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n", 1023 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1024 1025 if (xfer->c_flags & C_DMA) 1026 if (drvp->n_xfers <= NXFER) 1027 drvp->n_xfers++; 1028 1029 again: 1030 /* 1031 * 1032 * When starting a multi-sector transfer, or doing single-sector 1033 * transfers... 1034 */ 1035 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1036 if (ata_bio->flags & ATA_SINGLE) 1037 nblks = 1; 1038 else 1039 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1040 /* Check for bad sectors and adjust transfer, if necessary. */ 1041 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 1042 long blkdiff; 1043 int i; 1044 1045 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 1046 i++) { 1047 blkdiff -= ata_bio->blkno; 1048 if (blkdiff < 0) 1049 continue; 1050 if (blkdiff == 0) 1051 /* Replace current block of transfer. */ 1052 ata_bio->blkno = 1053 ata_bio->lp->d_secperunit - 1054 ata_bio->lp->d_nsectors - i - 1; 1055 if (blkdiff < nblks) { 1056 /* Bad block inside transfer. */ 1057 ata_bio->flags |= ATA_SINGLE; 1058 nblks = 1; 1059 } 1060 break; 1061 } 1062 /* Transfer is okay now. */ 1063 } 1064 if (xfer->c_flags & C_DMA) { 1065 ata_bio->nblks = nblks; 1066 ata_bio->nbytes = xfer->c_bcount; 1067 1068 if (xfer->c_flags & C_POLL) 1069 sc->sc_enable_intr(mvport, 0 /*off*/); 1070 error = mvsata_edma_enqueue(mvport, ata_bio, 1071 (char *)xfer->c_databuf + xfer->c_skip); 1072 if (error) { 1073 if (error == EINVAL) { 1074 /* 1075 * We can't do DMA on this transfer 1076 * for some reason. Fall back to 1077 * PIO. 1078 */ 1079 xfer->c_flags &= ~C_DMA; 1080 error = 0; 1081 goto do_pio; 1082 } 1083 if (error == EBUSY) { 1084 aprint_error_dev(atac->atac_dev, 1085 "channel %d: EDMA Queue full\n", 1086 chp->ch_channel); 1087 /* 1088 * XXXX: Perhaps, after it waits for 1089 * a while, it is necessary to call 1090 * bio_start again. 1091 */ 1092 } 1093 ata_bio->error = ERR_DMA; 1094 ata_bio->r_error = 0; 1095 mvsata_bio_done(chp, xfer); 1096 return; 1097 } 1098 chp->ch_flags |= ATACH_DMA_WAIT; 1099 /* start timeout machinery */ 1100 if ((xfer->c_flags & C_POLL) == 0) 1101 callout_reset(&chp->ch_callout, 1102 ATA_DELAY / 1000 * hz, 1103 mvsata_edma_timeout, xfer); 1104 /* wait for irq */ 1105 goto intr; 1106 } /* else not DMA */ 1107 do_pio: 1108 if (ata_bio->flags & ATA_LBA48) { 1109 sect = 0; 1110 cyl = 0; 1111 head = 0; 1112 } else if (ata_bio->flags & ATA_LBA) { 1113 sect = (ata_bio->blkno >> 0) & 0xff; 1114 cyl = (ata_bio->blkno >> 8) & 0xffff; 1115 head = (ata_bio->blkno >> 24) & 0x0f; 1116 head |= WDSD_LBA; 1117 } else { 1118 int blkno = ata_bio->blkno; 1119 sect = blkno % ata_bio->lp->d_nsectors; 1120 sect++; /* Sectors begin with 1, not 0. */ 1121 blkno /= ata_bio->lp->d_nsectors; 1122 head = blkno % ata_bio->lp->d_ntracks; 1123 blkno /= ata_bio->lp->d_ntracks; 1124 cyl = blkno; 1125 head |= WDSD_CHS; 1126 } 1127 ata_bio->nblks = min(nblks, ata_bio->multi); 1128 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 1129 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1130 if (ata_bio->nblks > 1) 1131 cmd = (ata_bio->flags & ATA_READ) ? 1132 WDCC_READMULTI : WDCC_WRITEMULTI; 1133 else 1134 cmd = (ata_bio->flags & ATA_READ) ? 1135 WDCC_READ : WDCC_WRITE; 1136 1137 /* EDMA disable, if enabled this channel. */ 1138 if (mvport->port_edmamode != nodma) 1139 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1140 1141 /* Do control operations specially. */ 1142 if (__predict_false(drvp->state < READY)) { 1143 /* 1144 * Actually, we want to be careful not to mess with 1145 * the control state if the device is currently busy, 1146 * but we can assume that we never get to this point 1147 * if that's the case. 1148 */ 1149 /* 1150 * If it's not a polled command, we need the kernel 1151 * thread 1152 */ 1153 if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) { 1154 chp->ch_queue->queue_freeze++; 1155 wakeup(&chp->ch_thread); 1156 return; 1157 } 1158 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1159 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1160 mvsata_bio_done(chp, xfer); 1161 return; 1162 } 1163 } 1164 1165 /* Initiate command! */ 1166 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1167 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 1168 case WDCWAIT_OK: 1169 break; 1170 case WDCWAIT_TOUT: 1171 goto timeout; 1172 case WDCWAIT_THR: 1173 return; 1174 } 1175 if (ata_bio->flags & ATA_LBA48) 1176 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 1177 (uint64_t)ata_bio->blkno, nblks, 0); 1178 else 1179 wdccommand(chp, xfer->c_drive, cmd, cyl, 1180 head, sect, nblks, 1181 (ata_bio->lp->d_type == DTYPE_ST506) ? 1182 ata_bio->lp->d_precompcyl / 4 : 0); 1183 1184 /* start timeout machinery */ 1185 if ((xfer->c_flags & C_POLL) == 0) 1186 callout_reset(&chp->ch_callout, 1187 ATA_DELAY / 1000 * hz, wdctimeout, chp); 1188 } else if (ata_bio->nblks > 1) { 1189 /* The number of blocks in the last stretch may be smaller. */ 1190 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1191 if (ata_bio->nblks > nblks) { 1192 ata_bio->nblks = nblks; 1193 ata_bio->nbytes = xfer->c_bcount; 1194 } 1195 } 1196 /* If this was a write and not using DMA, push the data. */ 1197 if ((ata_bio->flags & ATA_READ) == 0) { 1198 /* 1199 * we have to busy-wait here, we can't rely on running in 1200 * thread context. 1201 */ 1202 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 1203 aprint_error_dev(atac->atac_dev, 1204 "channel %d: drive %d timeout waiting for DRQ," 1205 " st=0x%02x, err=0x%02x\n", 1206 chp->ch_channel, xfer->c_drive, chp->ch_status, 1207 chp->ch_error); 1208 ata_bio->error = TIMEOUT; 1209 mvsata_bio_done(chp, xfer); 1210 return; 1211 } 1212 if (chp->ch_status & WDCS_ERR) { 1213 ata_bio->error = ERROR; 1214 ata_bio->r_error = chp->ch_error; 1215 mvsata_bio_done(chp, xfer); 1216 return; 1217 } 1218 1219 wdc->dataout_pio(chp, drvp->drive_flags, 1220 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1221 } 1222 1223 intr: 1224 /* Wait for IRQ (either real or polled) */ 1225 if ((ata_bio->flags & ATA_POLL) == 0) { 1226 chp->ch_flags |= ATACH_IRQ_WAIT; 1227 } else { 1228 /* Wait for at last 400ns for status bit to be valid */ 1229 delay(1); 1230 if (chp->ch_flags & ATACH_DMA_WAIT) { 1231 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1232 sc->sc_enable_intr(mvport, 1 /*on*/); 1233 chp->ch_flags &= ~ATACH_DMA_WAIT; 1234 } 1235 mvsata_bio_intr(chp, xfer, 0); 1236 if ((ata_bio->flags & ATA_ITSDONE) == 0) 1237 goto again; 1238 } 1239 return; 1240 1241 timeout: 1242 aprint_error_dev(atac->atac_dev, 1243 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1244 chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error); 1245 ata_bio->error = TIMEOUT; 1246 mvsata_bio_done(chp, xfer); 1247 return; 1248 } 1249 1250 static int 1251 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1252 { 1253 struct atac_softc *atac = chp->ch_atac; 1254 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1255 struct ata_bio *ata_bio = xfer->c_cmd; 1256 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1257 1258 DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n", 1259 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1260 1261 chp->ch_flags &= ~(ATACH_IRQ_WAIT|ATACH_DMA_WAIT); 1262 1263 /* Is it not a transfer, but a control operation? */ 1264 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1265 aprint_error_dev(atac->atac_dev, 1266 "channel %d: drive %d bad state %d in mvsata_bio_intr\n", 1267 chp->ch_channel, xfer->c_drive, drvp->state); 1268 panic("mvsata_bio_intr: bad state"); 1269 } 1270 1271 /* 1272 * If we missed an interrupt transfer, reset and restart. 1273 * Don't try to continue transfer, we may have missed cycles. 1274 */ 1275 if (xfer->c_flags & C_TIMEOU) { 1276 ata_bio->error = TIMEOUT; 1277 mvsata_bio_done(chp, xfer); 1278 return 1; 1279 } 1280 1281 /* Ack interrupt done by wdc_wait_for_unbusy */ 1282 if (!(xfer->c_flags & C_DMA) && 1283 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) 1284 == WDCWAIT_TOUT)) { 1285 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1286 return 0; /* IRQ was not for us */ 1287 aprint_error_dev(atac->atac_dev, 1288 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1289 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1290 xfer->c_skip); 1291 ata_bio->error = TIMEOUT; 1292 mvsata_bio_done(chp, xfer); 1293 return 1; 1294 } 1295 1296 if (xfer->c_flags & C_DMA) { 1297 if (ata_bio->error == NOERROR) 1298 goto end; 1299 if (ata_bio->error == ERR_DMA) 1300 ata_dmaerr(drvp, 1301 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1302 } 1303 1304 /* if we had an error, end */ 1305 if (ata_bio->error != NOERROR) { 1306 mvsata_bio_done(chp, xfer); 1307 return 1; 1308 } 1309 1310 /* If this was a read and not using DMA, fetch the data. */ 1311 if ((ata_bio->flags & ATA_READ) != 0) { 1312 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 1313 aprint_error_dev(atac->atac_dev, 1314 "channel %d: drive %d read intr before drq\n", 1315 chp->ch_channel, xfer->c_drive); 1316 ata_bio->error = TIMEOUT; 1317 mvsata_bio_done(chp, xfer); 1318 return 1; 1319 } 1320 wdc->datain_pio(chp, drvp->drive_flags, 1321 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1322 } 1323 1324 end: 1325 ata_bio->blkno += ata_bio->nblks; 1326 ata_bio->blkdone += ata_bio->nblks; 1327 xfer->c_skip += ata_bio->nbytes; 1328 xfer->c_bcount -= ata_bio->nbytes; 1329 /* See if this transfer is complete. */ 1330 if (xfer->c_bcount > 0) { 1331 if ((ata_bio->flags & ATA_POLL) == 0) 1332 /* Start the next operation */ 1333 mvsata_bio_start(chp, xfer); 1334 else 1335 /* Let mvsata_bio_start do the loop */ 1336 return 1; 1337 } else { /* Done with this transfer */ 1338 ata_bio->error = NOERROR; 1339 mvsata_bio_done(chp, xfer); 1340 } 1341 return 1; 1342 } 1343 1344 static void 1345 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1346 { 1347 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1348 struct atac_softc *atac = chp->ch_atac; 1349 struct ata_bio *ata_bio = xfer->c_cmd; 1350 int drive = xfer->c_drive; 1351 1352 DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1353 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1354 1355 /* EDMA restart, if enabled */ 1356 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1357 mvsata_edma_reset_qptr(mvport); 1358 mvsata_edma_enable(mvport); 1359 } 1360 1361 ata_free_xfer(chp, xfer); 1362 1363 ata_bio->flags |= ATA_ITSDONE; 1364 switch (reason) { 1365 case KILL_GONE: 1366 ata_bio->error = ERR_NODEV; 1367 break; 1368 case KILL_RESET: 1369 ata_bio->error = ERR_RESET; 1370 break; 1371 default: 1372 aprint_error_dev(atac->atac_dev, 1373 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1374 panic("mvsata_bio_kill_xfer"); 1375 } 1376 ata_bio->r_error = WDCE_ABRT; 1377 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1378 } 1379 1380 static void 1381 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1382 { 1383 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1384 struct ata_bio *ata_bio = xfer->c_cmd; 1385 int drive = xfer->c_drive; 1386 1387 DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1388 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1389 (u_int)xfer->c_flags)); 1390 1391 callout_stop(&chp->ch_callout); 1392 1393 /* EDMA restart, if enabled */ 1394 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1395 mvsata_edma_reset_qptr(mvport); 1396 mvsata_edma_enable(mvport); 1397 } 1398 1399 /* feed back residual bcount to our caller */ 1400 ata_bio->bcount = xfer->c_bcount; 1401 1402 /* mark controller inactive and free xfer */ 1403 KASSERT(chp->ch_queue->active_xfer != NULL); 1404 chp->ch_queue->active_xfer = NULL; 1405 ata_free_xfer(chp, xfer); 1406 1407 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1408 ata_bio->error = ERR_NODEV; 1409 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1410 wakeup(&chp->ch_queue->active_xfer); 1411 } 1412 ata_bio->flags |= ATA_ITSDONE; 1413 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1414 atastart(chp); 1415 } 1416 1417 static int 1418 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1419 int flags) 1420 { 1421 struct ata_channel *chp = &mvport->port_ata_channel; 1422 struct atac_softc *atac = chp->ch_atac; 1423 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1424 const char *errstring; 1425 1426 flags |= AT_POLL; /* XXX */ 1427 1428 /* 1429 * disable interrupts, all commands here should be quick 1430 * enough to be able to poll, and we don't go here that often 1431 */ 1432 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1433 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1434 DELAY(10); 1435 errstring = "wait"; 1436 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1437 goto ctrltimeout; 1438 wdccommandshort(chp, drive, WDCC_RECAL); 1439 /* Wait for at last 400ns for status bit to be valid */ 1440 DELAY(1); 1441 errstring = "recal"; 1442 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1443 goto ctrltimeout; 1444 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1445 goto ctrlerror; 1446 /* Don't try to set modes if controller can't be adjusted */ 1447 if (atac->atac_set_modes == NULL) 1448 goto geometry; 1449 /* Also don't try if the drive didn't report its mode */ 1450 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1451 goto geometry; 1452 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1453 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1454 errstring = "piomode"; 1455 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1456 goto ctrltimeout; 1457 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1458 goto ctrlerror; 1459 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1460 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1461 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1462 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1463 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1464 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1465 else 1466 goto geometry; 1467 errstring = "dmamode"; 1468 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1469 goto ctrltimeout; 1470 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1471 goto ctrlerror; 1472 geometry: 1473 if (ata_bio->flags & ATA_LBA) 1474 goto multimode; 1475 wdccommand(chp, drive, WDCC_IDP, ata_bio->lp->d_ncylinders, 1476 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 1477 (ata_bio->lp->d_type == DTYPE_ST506) ? 1478 ata_bio->lp->d_precompcyl / 4 : 0); 1479 errstring = "geometry"; 1480 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1481 goto ctrltimeout; 1482 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1483 goto ctrlerror; 1484 multimode: 1485 if (ata_bio->multi == 1) 1486 goto ready; 1487 wdccommand(chp, drive, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0); 1488 errstring = "setmulti"; 1489 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1490 goto ctrltimeout; 1491 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1492 goto ctrlerror; 1493 ready: 1494 drvp->state = READY; 1495 /* 1496 * The drive is usable now 1497 */ 1498 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1499 delay(10); /* some drives need a little delay here */ 1500 return 0; 1501 1502 ctrltimeout: 1503 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1504 chp->ch_channel, drive, errstring); 1505 ata_bio->error = TIMEOUT; 1506 goto ctrldone; 1507 ctrlerror: 1508 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1509 chp->ch_channel, drive, errstring); 1510 if (chp->ch_status & WDCS_DWF) { 1511 aprint_error("drive fault\n"); 1512 ata_bio->error = ERR_DF; 1513 } else { 1514 aprint_error("error (%x)\n", chp->ch_error); 1515 ata_bio->r_error = chp->ch_error; 1516 ata_bio->error = ERROR; 1517 } 1518 ctrldone: 1519 drvp->state = 0; 1520 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1521 return -1; 1522 } 1523 1524 static void 1525 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1526 { 1527 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1528 int drive = xfer->c_drive; 1529 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1530 struct ata_command *ata_c = xfer->c_cmd; 1531 1532 DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n", 1533 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1534 1535 /* First, EDMA disable, if enabled this channel. */ 1536 if (mvport->port_edmamode != nodma) 1537 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1538 1539 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1540 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1541 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1542 case WDCWAIT_OK: 1543 break; 1544 case WDCWAIT_TOUT: 1545 ata_c->flags |= AT_TIMEOU; 1546 mvsata_wdc_cmd_done(chp, xfer); 1547 return; 1548 case WDCWAIT_THR: 1549 return; 1550 } 1551 if (ata_c->flags & AT_POLL) 1552 /* polled command, disable interrupts */ 1553 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1554 if ((ata_c->flags & AT_LBA48) != 0) { 1555 wdccommandext(chp, drive, ata_c->r_command, 1556 ata_c->r_lba, ata_c->r_count, ata_c->r_features); 1557 } else { 1558 wdccommand(chp, drive, ata_c->r_command, 1559 (ata_c->r_lba >> 8) & 0xffff, 1560 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1561 ((ata_c->r_lba >> 24) & 0x0f), 1562 ata_c->r_lba & 0xff, 1563 ata_c->r_count & 0xff, 1564 ata_c->r_features & 0xff); 1565 } 1566 1567 if ((ata_c->flags & AT_POLL) == 0) { 1568 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1569 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1570 wdctimeout, chp); 1571 return; 1572 } 1573 /* 1574 * Polled command. Wait for drive ready or drq. Done in intr(). 1575 * Wait for at last 400ns for status bit to be valid. 1576 */ 1577 delay(10); /* 400ns delay */ 1578 mvsata_wdc_cmd_intr(chp, xfer, 0); 1579 } 1580 1581 static int 1582 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1583 { 1584 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1585 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1586 struct ata_command *ata_c = xfer->c_cmd; 1587 int bcount = ata_c->bcount; 1588 char *data = ata_c->data; 1589 int wflags; 1590 int drive_flags; 1591 1592 if (ata_c->r_command == WDCC_IDENTIFY || 1593 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1594 /* 1595 * The IDENTIFY data has been designed as an array of 1596 * u_int16_t, so we can byteswap it on the fly. 1597 * Historically it's what we have always done so keeping it 1598 * here ensure binary backward compatibility. 1599 */ 1600 drive_flags = ATA_DRIVE_NOSTREAM | 1601 chp->ch_drive[xfer->c_drive].drive_flags; 1602 else 1603 /* 1604 * Other data structure are opaque and should be transfered 1605 * as is. 1606 */ 1607 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1608 1609 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1610 /* both wait and poll, we can tsleep here */ 1611 wflags = AT_WAIT | AT_POLL; 1612 else 1613 wflags = AT_POLL; 1614 1615 again: 1616 DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n", 1617 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1618 1619 /* 1620 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1621 * Reselect again, it doesn't hurt for others commands, and the time 1622 * penalty for the extra register write is acceptable, 1623 * wdc_exec_command() isn't called often (mostly for autoconfig) 1624 */ 1625 if ((xfer->c_flags & C_ATAPI) != 0) { 1626 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1627 } 1628 if ((ata_c->flags & AT_XFDONE) != 0) { 1629 /* 1630 * We have completed a data xfer. The drive should now be 1631 * in its initial state 1632 */ 1633 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1634 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1635 wflags) == WDCWAIT_TOUT) { 1636 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1637 return 0; /* IRQ was not for us */ 1638 ata_c->flags |= AT_TIMEOU; 1639 } 1640 goto out; 1641 } 1642 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1643 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1644 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1645 return 0; /* IRQ was not for us */ 1646 ata_c->flags |= AT_TIMEOU; 1647 goto out; 1648 } 1649 if (ata_c->flags & AT_READ) { 1650 if ((chp->ch_status & WDCS_DRQ) == 0) { 1651 ata_c->flags |= AT_TIMEOU; 1652 goto out; 1653 } 1654 wdc->datain_pio(chp, drive_flags, data, bcount); 1655 /* at this point the drive should be in its initial state */ 1656 ata_c->flags |= AT_XFDONE; 1657 /* 1658 * XXX checking the status register again here cause some 1659 * hardware to timeout. 1660 */ 1661 } else if (ata_c->flags & AT_WRITE) { 1662 if ((chp->ch_status & WDCS_DRQ) == 0) { 1663 ata_c->flags |= AT_TIMEOU; 1664 goto out; 1665 } 1666 wdc->dataout_pio(chp, drive_flags, data, bcount); 1667 ata_c->flags |= AT_XFDONE; 1668 if ((ata_c->flags & AT_POLL) == 0) { 1669 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */ 1670 callout_reset(&chp->ch_callout, 1671 mstohz(ata_c->timeout), wdctimeout, chp); 1672 return 1; 1673 } else 1674 goto again; 1675 } 1676 out: 1677 mvsata_wdc_cmd_done(chp, xfer); 1678 return 1; 1679 } 1680 1681 static void 1682 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1683 int reason) 1684 { 1685 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1686 struct ata_command *ata_c = xfer->c_cmd; 1687 1688 DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1689 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1690 1691 switch (reason) { 1692 case KILL_GONE: 1693 ata_c->flags |= AT_GONE; 1694 break; 1695 case KILL_RESET: 1696 ata_c->flags |= AT_RESET; 1697 break; 1698 default: 1699 aprint_error_dev(MVSATA_DEV2(mvport), 1700 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1701 panic("mvsata_cmd_kill_xfer"); 1702 } 1703 mvsata_wdc_cmd_done_end(chp, xfer); 1704 } 1705 1706 static void 1707 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1708 { 1709 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1710 struct atac_softc *atac = chp->ch_atac; 1711 struct ata_command *ata_c = xfer->c_cmd; 1712 1713 DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1714 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1715 ata_c->flags)); 1716 1717 if (chp->ch_status & WDCS_DWF) 1718 ata_c->flags |= AT_DF; 1719 if (chp->ch_status & WDCS_ERR) { 1720 ata_c->flags |= AT_ERROR; 1721 ata_c->r_error = chp->ch_error; 1722 } 1723 if ((ata_c->flags & AT_READREG) != 0 && 1724 device_is_active(atac->atac_dev) && 1725 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1726 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1727 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1728 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1729 ata_c->r_lba = 1730 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1731 ata_c->r_lba |= 1732 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1733 ata_c->r_lba |= 1734 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1735 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1736 if ((ata_c->flags & AT_LBA48) != 0) { 1737 if ((ata_c->flags & AT_POLL) != 0) { 1738 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1739 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1740 } else { 1741 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1742 WDCTL_HOB|WDCTL_4BIT); 1743 } 1744 ata_c->r_count |= 1745 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1746 ata_c->r_lba |= 1747 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1748 ata_c->r_lba |= 1749 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1750 ata_c->r_lba |= 1751 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1752 if ((ata_c->flags & AT_POLL) != 0) { 1753 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1754 WDCTL_4BIT|WDCTL_IDS); 1755 } else { 1756 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1757 WDCTL_4BIT); 1758 } 1759 } else { 1760 ata_c->r_lba |= 1761 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1762 } 1763 } 1764 callout_stop(&chp->ch_callout); 1765 chp->ch_queue->active_xfer = NULL; 1766 if (ata_c->flags & AT_POLL) { 1767 /* enable interrupts */ 1768 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1769 delay(10); /* some drives need a little delay here */ 1770 } 1771 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1772 mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE); 1773 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1774 wakeup(&chp->ch_queue->active_xfer); 1775 } else 1776 mvsata_wdc_cmd_done_end(chp, xfer); 1777 } 1778 1779 static void 1780 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1781 { 1782 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1783 struct ata_command *ata_c = xfer->c_cmd; 1784 1785 /* EDMA restart, if enabled */ 1786 if (mvport->port_edmamode != nodma) { 1787 mvsata_edma_reset_qptr(mvport); 1788 mvsata_edma_enable(mvport); 1789 } 1790 1791 ata_c->flags |= AT_DONE; 1792 ata_free_xfer(chp, xfer); 1793 if (ata_c->flags & AT_WAIT) 1794 wakeup(ata_c); 1795 else if (ata_c->callback) 1796 ata_c->callback(ata_c->callback_arg); 1797 atastart(chp); 1798 1799 return; 1800 } 1801 1802 #if NATAPIBUS > 0 1803 static void 1804 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1805 { 1806 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 1807 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1808 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1809 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1810 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1811 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1812 const char *errstring; 1813 1814 DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 1815 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1816 xfer->c_drive, sc_xfer->xs_control)); 1817 1818 if (mvport->port_edmamode != nodma) 1819 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1820 1821 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 1822 drvp->n_xfers++; 1823 1824 /* Do control operations specially. */ 1825 if (__predict_false(drvp->state < READY)) { 1826 /* If it's not a polled command, we need the kernel thread */ 1827 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) { 1828 chp->ch_queue->queue_freeze++; 1829 wakeup(&chp->ch_thread); 1830 return; 1831 } 1832 /* 1833 * disable interrupts, all commands here should be quick 1834 * enough to be able to poll, and we don't go here that often 1835 */ 1836 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1837 1838 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1839 /* Don't try to set mode if controller can't be adjusted */ 1840 if (atac->atac_set_modes == NULL) 1841 goto ready; 1842 /* Also don't try if the drive didn't report its mode */ 1843 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1844 goto ready; 1845 errstring = "unbusy"; 1846 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) 1847 goto timeout; 1848 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1849 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1850 errstring = "piomode"; 1851 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1852 goto timeout; 1853 if (chp->ch_status & WDCS_ERR) { 1854 if (chp->ch_error == WDCE_ABRT) { 1855 /* 1856 * Some ATAPI drives reject PIO settings. 1857 * Fall back to PIO mode 3 since that's the 1858 * minimum for ATAPI. 1859 */ 1860 aprint_error_dev(atac->atac_dev, 1861 "channel %d drive %d: PIO mode %d rejected," 1862 " falling back to PIO mode 3\n", 1863 chp->ch_channel, xfer->c_drive, 1864 drvp->PIO_mode); 1865 if (drvp->PIO_mode > 3) 1866 drvp->PIO_mode = 3; 1867 } else 1868 goto error; 1869 } 1870 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1871 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1872 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1873 else 1874 if (drvp->drive_flags & ATA_DRIVE_DMA) 1875 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1876 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1877 else 1878 goto ready; 1879 errstring = "dmamode"; 1880 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1881 goto timeout; 1882 if (chp->ch_status & WDCS_ERR) { 1883 if (chp->ch_error == WDCE_ABRT) { 1884 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1885 goto error; 1886 else { 1887 /* 1888 * The drive rejected our DMA setting. 1889 * Fall back to mode 1. 1890 */ 1891 aprint_error_dev(atac->atac_dev, 1892 "channel %d drive %d:" 1893 " DMA mode %d rejected," 1894 " falling back to DMA mode 0\n", 1895 chp->ch_channel, xfer->c_drive, 1896 drvp->DMA_mode); 1897 if (drvp->DMA_mode > 0) 1898 drvp->DMA_mode = 0; 1899 } 1900 } else 1901 goto error; 1902 } 1903 ready: 1904 drvp->state = READY; 1905 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1906 delay(10); /* some drives need a little delay here */ 1907 } 1908 /* start timeout machinery */ 1909 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 1910 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1911 wdctimeout, chp); 1912 1913 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1914 switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) { 1915 case WDCWAIT_OK: 1916 break; 1917 case WDCWAIT_TOUT: 1918 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 1919 chp->ch_status); 1920 sc_xfer->error = XS_TIMEOUT; 1921 mvsata_atapi_reset(chp, xfer); 1922 return; 1923 case WDCWAIT_THR: 1924 return; 1925 } 1926 1927 /* 1928 * Even with WDCS_ERR, the device should accept a command packet 1929 * Limit length to what can be stuffed into the cylinder register 1930 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 1931 * but not all devices do that and it's not obvious from the 1932 * ATAPI spec that that behaviour should be expected. If more 1933 * data is necessary, multiple data transfer phases will be done. 1934 */ 1935 1936 wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD, 1937 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 1938 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1939 1940 /* 1941 * If there is no interrupt for CMD input, busy-wait for it (done in 1942 * the interrupt routine. If it is a polled command, call the interrupt 1943 * routine until command is done. 1944 */ 1945 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 1946 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) { 1947 /* Wait for at last 400ns for status bit to be valid */ 1948 DELAY(1); 1949 mvsata_atapi_intr(chp, xfer, 0); 1950 } else 1951 chp->ch_flags |= ATACH_IRQ_WAIT; 1952 if (sc_xfer->xs_control & XS_CTL_POLL) { 1953 if (chp->ch_flags & ATACH_DMA_WAIT) { 1954 wdc_dmawait(chp, xfer, sc_xfer->timeout); 1955 chp->ch_flags &= ~ATACH_DMA_WAIT; 1956 } 1957 while ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1958 /* Wait for at last 400ns for status bit to be valid */ 1959 DELAY(1); 1960 mvsata_atapi_intr(chp, xfer, 0); 1961 } 1962 } 1963 return; 1964 1965 timeout: 1966 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 1967 chp->ch_channel, xfer->c_drive, errstring); 1968 sc_xfer->error = XS_TIMEOUT; 1969 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1970 delay(10); /* some drives need a little delay here */ 1971 mvsata_atapi_reset(chp, xfer); 1972 return; 1973 1974 error: 1975 aprint_error_dev(atac->atac_dev, 1976 "channel %d drive %d: %s error (0x%x)\n", 1977 chp->ch_channel, xfer->c_drive, errstring, chp->ch_error); 1978 sc_xfer->error = XS_SHORTSENSE; 1979 sc_xfer->sense.atapi_sense = chp->ch_error; 1980 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1981 delay(10); /* some drives need a little delay here */ 1982 mvsata_atapi_reset(chp, xfer); 1983 return; 1984 } 1985 1986 static int 1987 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1988 { 1989 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1990 struct atac_softc *atac = chp->ch_atac; 1991 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1992 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1993 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1994 int len, phase, ire, error, retries=0, i; 1995 void *cmd; 1996 1997 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n", 1998 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1999 2000 /* Is it not a transfer, but a control operation? */ 2001 if (drvp->state < READY) { 2002 aprint_error_dev(atac->atac_dev, 2003 "channel %d drive %d: bad state %d\n", 2004 chp->ch_channel, xfer->c_drive, drvp->state); 2005 panic("mvsata_atapi_intr: bad state"); 2006 } 2007 /* 2008 * If we missed an interrupt in a PIO transfer, reset and restart. 2009 * Don't try to continue transfer, we may have missed cycles. 2010 */ 2011 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2012 sc_xfer->error = XS_TIMEOUT; 2013 mvsata_atapi_reset(chp, xfer); 2014 return 1; 2015 } 2016 2017 /* Ack interrupt done in wdc_wait_for_unbusy */ 2018 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2019 if (wdc_wait_for_unbusy(chp, 2020 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) { 2021 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 2022 return 0; /* IRQ was not for us */ 2023 aprint_error_dev(atac->atac_dev, 2024 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2025 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2026 if (xfer->c_flags & C_DMA) 2027 ata_dmaerr(drvp, 2028 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2029 sc_xfer->error = XS_TIMEOUT; 2030 mvsata_atapi_reset(chp, xfer); 2031 return 1; 2032 } 2033 2034 /* 2035 * If we missed an IRQ and were using DMA, flag it as a DMA error 2036 * and reset device. 2037 */ 2038 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2039 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2040 sc_xfer->error = XS_RESET; 2041 mvsata_atapi_reset(chp, xfer); 2042 return (1); 2043 } 2044 /* 2045 * if the request sense command was aborted, report the short sense 2046 * previously recorded, else continue normal processing 2047 */ 2048 2049 again: 2050 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2051 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2052 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2053 phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ); 2054 DPRINTF(( 2055 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2056 xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire)); 2057 2058 switch (phase) { 2059 case PHASE_CMDOUT: 2060 cmd = sc_xfer->cmd; 2061 DPRINTF(("PHASE_CMDOUT\n")); 2062 /* Init the DMA channel if necessary */ 2063 if (xfer->c_flags & C_DMA) { 2064 error = mvsata_bdma_init(mvport, sc_xfer, 2065 (char *)xfer->c_databuf + xfer->c_skip); 2066 if (error) { 2067 if (error == EINVAL) { 2068 /* 2069 * We can't do DMA on this transfer 2070 * for some reason. Fall back to PIO. 2071 */ 2072 xfer->c_flags &= ~C_DMA; 2073 error = 0; 2074 } else { 2075 sc_xfer->error = XS_DRIVER_STUFFUP; 2076 break; 2077 } 2078 } 2079 } 2080 2081 /* send packet command */ 2082 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2083 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2084 2085 /* Start the DMA channel if necessary */ 2086 if (xfer->c_flags & C_DMA) { 2087 mvsata_bdma_start(mvport); 2088 chp->ch_flags |= ATACH_DMA_WAIT; 2089 } 2090 2091 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2092 chp->ch_flags |= ATACH_IRQ_WAIT; 2093 return 1; 2094 2095 case PHASE_DATAOUT: 2096 /* write data */ 2097 DPRINTF(("PHASE_DATAOUT\n")); 2098 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2099 (xfer->c_flags & C_DMA) != 0) { 2100 aprint_error_dev(atac->atac_dev, 2101 "channel %d drive %d: bad data phase DATAOUT\n", 2102 chp->ch_channel, xfer->c_drive); 2103 if (xfer->c_flags & C_DMA) 2104 ata_dmaerr(drvp, 2105 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2106 sc_xfer->error = XS_TIMEOUT; 2107 mvsata_atapi_reset(chp, xfer); 2108 return 1; 2109 } 2110 xfer->c_lenoff = len - xfer->c_bcount; 2111 if (xfer->c_bcount < len) { 2112 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2113 " warning: write only %d of %d requested bytes\n", 2114 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2115 len); 2116 len = xfer->c_bcount; 2117 } 2118 2119 wdc->dataout_pio(chp, drvp->drive_flags, 2120 (char *)xfer->c_databuf + xfer->c_skip, len); 2121 2122 for (i = xfer->c_lenoff; i > 0; i -= 2) 2123 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2124 2125 xfer->c_skip += len; 2126 xfer->c_bcount -= len; 2127 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2128 chp->ch_flags |= ATACH_IRQ_WAIT; 2129 return 1; 2130 2131 case PHASE_DATAIN: 2132 /* Read data */ 2133 DPRINTF(("PHASE_DATAIN\n")); 2134 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2135 (xfer->c_flags & C_DMA) != 0) { 2136 aprint_error_dev(atac->atac_dev, 2137 "channel %d drive %d: bad data phase DATAIN\n", 2138 chp->ch_channel, xfer->c_drive); 2139 if (xfer->c_flags & C_DMA) 2140 ata_dmaerr(drvp, 2141 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2142 sc_xfer->error = XS_TIMEOUT; 2143 mvsata_atapi_reset(chp, xfer); 2144 return 1; 2145 } 2146 xfer->c_lenoff = len - xfer->c_bcount; 2147 if (xfer->c_bcount < len) { 2148 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2149 " warning: reading only %d of %d bytes\n", 2150 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2151 len); 2152 len = xfer->c_bcount; 2153 } 2154 2155 wdc->datain_pio(chp, drvp->drive_flags, 2156 (char *)xfer->c_databuf + xfer->c_skip, len); 2157 2158 if (xfer->c_lenoff > 0) 2159 wdcbit_bucket(chp, len - xfer->c_bcount); 2160 2161 xfer->c_skip += len; 2162 xfer->c_bcount -= len; 2163 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2164 chp->ch_flags |= ATACH_IRQ_WAIT; 2165 return 1; 2166 2167 case PHASE_ABORTED: 2168 case PHASE_COMPLETED: 2169 DPRINTF(("PHASE_COMPLETED\n")); 2170 if (xfer->c_flags & C_DMA) 2171 xfer->c_bcount -= sc_xfer->datalen; 2172 sc_xfer->resid = xfer->c_bcount; 2173 mvsata_atapi_phase_complete(xfer); 2174 return 1; 2175 2176 default: 2177 if (++retries<500) { 2178 DELAY(100); 2179 chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 2180 chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 2181 goto again; 2182 } 2183 aprint_error_dev(atac->atac_dev, 2184 "channel %d drive %d: unknown phase 0x%x\n", 2185 chp->ch_channel, xfer->c_drive, phase); 2186 if (chp->ch_status & WDCS_ERR) { 2187 sc_xfer->error = XS_SHORTSENSE; 2188 sc_xfer->sense.atapi_sense = chp->ch_error; 2189 } else { 2190 if (xfer->c_flags & C_DMA) 2191 ata_dmaerr(drvp, 2192 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2193 sc_xfer->error = XS_RESET; 2194 mvsata_atapi_reset(chp, xfer); 2195 return (1); 2196 } 2197 } 2198 DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x " 2199 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense)); 2200 mvsata_atapi_done(chp, xfer); 2201 return 1; 2202 } 2203 2204 static void 2205 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2206 int reason) 2207 { 2208 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2209 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2210 2211 /* remove this command from xfer queue */ 2212 switch (reason) { 2213 case KILL_GONE: 2214 sc_xfer->error = XS_DRIVER_STUFFUP; 2215 break; 2216 2217 case KILL_RESET: 2218 sc_xfer->error = XS_RESET; 2219 break; 2220 2221 default: 2222 aprint_error_dev(MVSATA_DEV2(mvport), 2223 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2224 panic("mvsata_atapi_kill_xfer"); 2225 } 2226 ata_free_xfer(chp, xfer); 2227 scsipi_done(sc_xfer); 2228 } 2229 2230 static void 2231 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2232 { 2233 struct atac_softc *atac = chp->ch_atac; 2234 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2235 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2236 2237 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 2238 drvp->state = 0; 2239 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) { 2240 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2241 chp->ch_channel, xfer->c_drive); 2242 sc_xfer->error = XS_SELTIMEOUT; 2243 } 2244 mvsata_atapi_done(chp, xfer); 2245 return; 2246 } 2247 2248 static void 2249 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2250 { 2251 struct ata_channel *chp = xfer->c_chp; 2252 struct atac_softc *atac = chp->ch_atac; 2253 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2254 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2255 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2256 2257 /* wait for DSC if needed */ 2258 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2259 DPRINTFN(1, 2260 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2261 device_xname(atac->atac_dev), chp->ch_channel, 2262 xfer->c_drive, xfer->c_dscpoll)); 2263 if (cold) 2264 panic("mvsata_atapi_phase_complete: cold"); 2265 2266 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) == 2267 WDCWAIT_TOUT) { 2268 /* 10ms not enough, try again in 1 tick */ 2269 if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) { 2270 aprint_error_dev(atac->atac_dev, 2271 "channel %d: wait_for_dsc failed\n", 2272 chp->ch_channel); 2273 sc_xfer->error = XS_TIMEOUT; 2274 mvsata_atapi_reset(chp, xfer); 2275 return; 2276 } else 2277 callout_reset(&chp->ch_callout, 1, 2278 mvsata_atapi_polldsc, xfer); 2279 return; 2280 } 2281 } 2282 2283 /* 2284 * Some drive occasionally set WDCS_ERR with 2285 * "ATA illegal length indication" in the error 2286 * register. If we read some data the sense is valid 2287 * anyway, so don't report the error. 2288 */ 2289 if (chp->ch_status & WDCS_ERR && 2290 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2291 sc_xfer->resid == sc_xfer->datalen)) { 2292 /* save the short sense */ 2293 sc_xfer->error = XS_SHORTSENSE; 2294 sc_xfer->sense.atapi_sense = chp->ch_error; 2295 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2296 /* ask scsipi to send a REQUEST_SENSE */ 2297 sc_xfer->error = XS_BUSY; 2298 sc_xfer->status = SCSI_CHECK; 2299 } else 2300 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2301 ata_dmaerr(drvp, 2302 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2303 sc_xfer->error = XS_RESET; 2304 mvsata_atapi_reset(chp, xfer); 2305 return; 2306 } 2307 } 2308 if (xfer->c_bcount != 0) 2309 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:" 2310 " bcount value is %d after io\n", 2311 device_xname(atac->atac_dev), chp->ch_channel, 2312 xfer->c_drive, xfer->c_bcount)); 2313 #ifdef DIAGNOSTIC 2314 if (xfer->c_bcount < 0) 2315 aprint_error_dev(atac->atac_dev, 2316 "channel %d drive %d: mvsata_atapi_intr:" 2317 " warning: bcount value is %d after io\n", 2318 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2319 #endif 2320 2321 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:" 2322 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2323 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2324 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2325 mvsata_atapi_done(chp, xfer); 2326 } 2327 2328 static void 2329 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2330 { 2331 struct atac_softc *atac = chp->ch_atac; 2332 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2333 int drive = xfer->c_drive; 2334 2335 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2336 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2337 (u_int)xfer->c_flags)); 2338 callout_stop(&chp->ch_callout); 2339 /* mark controller inactive and free the command */ 2340 chp->ch_queue->active_xfer = NULL; 2341 ata_free_xfer(chp, xfer); 2342 2343 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 2344 sc_xfer->error = XS_DRIVER_STUFFUP; 2345 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 2346 wakeup(&chp->ch_queue->active_xfer); 2347 } 2348 2349 DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2350 device_xname(atac->atac_dev), chp->ch_channel)); 2351 scsipi_done(sc_xfer); 2352 DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2353 device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags)); 2354 atastart(chp); 2355 } 2356 2357 static void 2358 mvsata_atapi_polldsc(void *arg) 2359 { 2360 2361 mvsata_atapi_phase_complete(arg); 2362 } 2363 #endif /* NATAPIBUS > 0 */ 2364 2365 2366 /* 2367 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2368 * if supported queuing command by atabus? The race condition will not happen 2369 * if this is called only to the thread of atabus. 2370 */ 2371 static int 2372 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio, 2373 void *databuf) 2374 { 2375 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2376 struct ata_channel *chp = &mvport->port_ata_channel; 2377 struct eprd *eprd; 2378 bus_addr_t crqb_base_addr; 2379 bus_dmamap_t data_dmamap; 2380 uint32_t reg; 2381 int quetag, erqqip, erqqop, next, rv, i; 2382 2383 DPRINTFN(2, ("%s:%d:%d: mvsata_edma_enqueue:" 2384 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2385 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2386 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2387 2388 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2389 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2390 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2391 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2392 next = erqqip; 2393 MVSATA_EDMAQ_INC(next); 2394 if (next == erqqop) 2395 /* queue full */ 2396 return EBUSY; 2397 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2398 /* tag nothing */ 2399 return EBUSY; 2400 DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag)); 2401 2402 rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes, 2403 ata_bio->flags); 2404 if (rv != 0) 2405 return rv; 2406 2407 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2408 KASSERT(chp->ch_queue->active_xfer != NULL); 2409 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2410 2411 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2412 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2413 eprd = mvport->port_reqtbl[quetag].eprd; 2414 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2415 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2416 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2417 2418 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2419 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2420 eprd->eot = htole16(0); 2421 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2422 eprd++; 2423 } 2424 (eprd - 1)->eot |= htole16(EPRD_EOT); 2425 #ifdef MVSATA_DEBUG 2426 if (mvsata_debug >= 3) 2427 mvsata_print_eprd(mvport, quetag); 2428 #endif 2429 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2430 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2431 BUS_DMASYNC_PREWRITE); 2432 2433 /* setup EDMA Command Request Block (CRQB) Data */ 2434 sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio); 2435 #ifdef MVSATA_DEBUG 2436 if (mvsata_debug >= 3) 2437 mvsata_print_crqb(mvport, erqqip); 2438 #endif 2439 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2440 erqqip * sizeof(union mvsata_crqb), 2441 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2442 2443 MVSATA_EDMAQ_INC(erqqip); 2444 2445 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2446 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2447 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2448 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2449 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2450 2451 return 0; 2452 } 2453 2454 static int 2455 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2456 { 2457 struct ata_channel *chp = &mvport->port_ata_channel; 2458 struct crpb *crpb; 2459 struct ata_bio *ata_bio; 2460 struct ata_xfer *xfer; 2461 uint32_t reg; 2462 int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2463 2464 /* First, Sync for Request Queue buffer */ 2465 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2466 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2467 if (mvport->port_prev_erqqop != erqqop) { 2468 const int s = sizeof(union mvsata_crqb); 2469 2470 if (mvport->port_prev_erqqop < erqqop) 2471 n = erqqop - mvport->port_prev_erqqop; 2472 else { 2473 if (erqqop > 0) 2474 bus_dmamap_sync(mvport->port_dmat, 2475 mvport->port_crqb_dmamap, 0, erqqop * s, 2476 BUS_DMASYNC_POSTWRITE); 2477 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2478 } 2479 if (n > 0) 2480 bus_dmamap_sync(mvport->port_dmat, 2481 mvport->port_crqb_dmamap, 2482 mvport->port_prev_erqqop * s, n * s, 2483 BUS_DMASYNC_POSTWRITE); 2484 mvport->port_prev_erqqop = erqqop; 2485 } 2486 2487 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2488 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2489 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2490 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2491 2492 DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2493 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2494 mvport->port, erpqip, erpqop)); 2495 2496 if (erpqop == erpqip) 2497 return 0; 2498 2499 if (erpqop < erpqip) 2500 n = erpqip - erpqop; 2501 else { 2502 if (erpqip > 0) 2503 bus_dmamap_sync(mvport->port_dmat, 2504 mvport->port_crpb_dmamap, 2505 0, erpqip * sizeof(struct crpb), 2506 BUS_DMASYNC_POSTREAD); 2507 n = MVSATA_EDMAQ_LEN - erpqop; 2508 } 2509 if (n > 0) 2510 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2511 erpqop * sizeof(struct crpb), 2512 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2513 2514 prev_erpqop = erpqop; 2515 while (erpqop != erpqip) { 2516 #ifdef MVSATA_DEBUG 2517 if (mvsata_debug >= 3) 2518 mvsata_print_crpb(mvport, erpqop); 2519 #endif 2520 crpb = mvport->port_crpb + erpqop; 2521 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2522 KASSERT(chp->ch_queue->active_xfer != NULL); 2523 xfer = chp->ch_queue->active_xfer; 2524 KASSERT(xfer == mvport->port_reqtbl[quetag].xfer); 2525 #ifdef DIAGNOSTIC 2526 if (xfer == NULL) 2527 panic("unknown response received: %s:%d:%d: tag 0x%x\n", 2528 device_xname(MVSATA_DEV2(mvport)), 2529 mvport->port_hc->hc, mvport->port, quetag); 2530 #endif 2531 2532 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2533 mvport->port_reqtbl[quetag].eprd_offset, 2534 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2535 2536 chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2537 chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2538 ata_bio = xfer->c_cmd; 2539 ata_bio->error = NOERROR; 2540 ata_bio->r_error = 0; 2541 if (chp->ch_status & WDCS_ERR) 2542 ata_bio->error = ERROR; 2543 if (chp->ch_status & WDCS_BSY) 2544 ata_bio->error = TIMEOUT; 2545 if (chp->ch_error) 2546 ata_bio->error = ERR_DMA; 2547 2548 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2549 mvport->port_reqtbl[quetag].xfer = NULL; 2550 mvsata_quetag_put(mvport, quetag); 2551 MVSATA_EDMAQ_INC(erpqop); 2552 2553 #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */ 2554 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2555 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2556 if (erpqop == erqqip) 2557 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2558 #endif 2559 mvsata_bio_intr(chp, xfer, 1); 2560 if (xfer1 == NULL) 2561 handled++; 2562 else if (xfer == xfer1) { 2563 handled = 1; 2564 break; 2565 } 2566 } 2567 if (prev_erpqop < erpqop) 2568 n = erpqop - prev_erpqop; 2569 else { 2570 if (erpqop > 0) 2571 bus_dmamap_sync(mvport->port_dmat, 2572 mvport->port_crpb_dmamap, 0, 2573 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2574 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2575 } 2576 if (n > 0) 2577 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2578 prev_erpqop * sizeof(struct crpb), 2579 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2580 2581 reg &= ~EDMA_RESQP_ERPQP_MASK; 2582 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2583 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2584 2585 #if 0 /* already cleared ago? */ 2586 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2587 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2588 if (erpqop == erqqip) 2589 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2590 #endif 2591 2592 return handled; 2593 } 2594 2595 static int 2596 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2597 { 2598 struct ata_bio *ata_bio = xfer->c_cmd; 2599 int xtime; 2600 2601 for (xtime = 0; xtime < timeout / 10; xtime++) { 2602 if (mvsata_edma_handle(mvport, xfer)) 2603 return 0; 2604 if (ata_bio->flags & ATA_NOSLEEP) 2605 delay(10000); 2606 else 2607 tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10)); 2608 } 2609 2610 DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer)); 2611 mvsata_edma_rqq_remove(mvport, xfer); 2612 xfer->c_flags |= C_TIMEOU; 2613 return 1; 2614 } 2615 2616 static void 2617 mvsata_edma_timeout(void *arg) 2618 { 2619 struct ata_xfer *xfer = (struct ata_xfer *)arg; 2620 struct ata_channel *chp = xfer->c_chp; 2621 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2622 int s; 2623 2624 s = splbio(); 2625 DPRINTF(("mvsata_edma_timeout: %p\n", xfer)); 2626 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 2627 mvsata_edma_rqq_remove(mvport, xfer); 2628 xfer->c_flags |= C_TIMEOU; 2629 mvsata_bio_intr(chp, xfer, 1); 2630 } 2631 splx(s); 2632 } 2633 2634 static void 2635 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2636 { 2637 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2638 struct ata_bio *ata_bio; 2639 bus_addr_t crqb_base_addr; 2640 int erqqip, i; 2641 2642 /* First, hardware reset, stop EDMA */ 2643 mvsata_hreset_port(mvport); 2644 2645 /* cleanup completed EDMA safely */ 2646 mvsata_edma_handle(mvport, NULL); 2647 2648 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2649 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2650 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2651 if (mvport->port_reqtbl[i].xfer == NULL) 2652 continue; 2653 2654 ata_bio = mvport->port_reqtbl[i].xfer->c_cmd; 2655 if (mvport->port_reqtbl[i].xfer == xfer) { 2656 /* remove xfer from EDMA request queue */ 2657 bus_dmamap_sync(mvport->port_dmat, 2658 mvport->port_eprd_dmamap, 2659 mvport->port_reqtbl[i].eprd_offset, 2660 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2661 mvsata_dma_bufunload(mvport, i, ata_bio->flags); 2662 mvport->port_reqtbl[i].xfer = NULL; 2663 mvsata_quetag_put(mvport, i); 2664 continue; 2665 } 2666 2667 sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio); 2668 erqqip++; 2669 } 2670 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2671 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2672 BUS_DMASYNC_POSTWRITE); 2673 2674 mvsata_edma_config(mvport, mvport->port_edmamode); 2675 mvsata_edma_reset_qptr(mvport); 2676 mvsata_edma_enable(mvport); 2677 2678 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2679 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2680 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2681 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2682 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2683 } 2684 2685 #if NATAPIBUS > 0 2686 static int 2687 mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer, 2688 void *databuf) 2689 { 2690 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2691 struct eprd *eprd; 2692 bus_dmamap_t data_dmamap; 2693 bus_addr_t eprd_addr; 2694 int quetag, rv; 2695 2696 DPRINTFN(2, 2697 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2698 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2699 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2700 2701 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2702 /* tag nothing */ 2703 return EBUSY; 2704 DPRINTFN(2, (" quetag=%d\n", quetag)); 2705 2706 rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen, 2707 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2708 if (rv != 0) 2709 return rv; 2710 2711 KASSERT(chp->ch_queue->active_xfer != NULL); 2712 KASSERT(mvport->port_reqtbl[quetag].xfer == NULL); 2713 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2714 2715 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2716 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2717 eprd = mvport->port_reqtbl[quetag].eprd; 2718 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2719 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2720 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2721 2722 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2723 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2724 eprd->eot = htole16(0); 2725 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2726 eprd++; 2727 } 2728 (eprd - 1)->eot |= htole16(EPRD_EOT); 2729 #ifdef MVSATA_DEBUG 2730 if (mvsata_debug >= 3) 2731 mvsata_print_eprd(mvport, quetag); 2732 #endif 2733 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2734 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2735 BUS_DMASYNC_PREWRITE); 2736 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2737 mvport->port_reqtbl[quetag].eprd_offset; 2738 2739 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2740 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2741 2742 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2743 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2744 else 2745 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2746 2747 return 0; 2748 } 2749 2750 static void 2751 mvsata_bdma_start(struct mvsata_port *mvport) 2752 { 2753 2754 #ifdef MVSATA_DEBUG 2755 if (mvsata_debug >= 3) 2756 mvsata_print_eprd(mvport, 0); 2757 #endif 2758 2759 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2760 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2761 } 2762 #endif 2763 #endif 2764 2765 2766 static int 2767 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2768 { 2769 struct mvsata_softc *sc = mvhc->hc_sc; 2770 struct mvsata_port *mvport; 2771 struct ata_channel *chp; 2772 int channel, rv, i; 2773 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2774 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2775 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2776 2777 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2778 M_ZERO | M_NOWAIT); 2779 if (mvport == NULL) { 2780 aprint_error("%s:%d: can't allocate memory for port %d\n", 2781 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2782 return ENOMEM; 2783 } 2784 2785 mvport->port = port; 2786 mvport->port_hc = mvhc; 2787 mvport->port_edmamode = nodma; 2788 2789 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2790 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 2791 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 2792 if (rv != 0) { 2793 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 2794 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2795 goto fail0; 2796 } 2797 mvport->port_iot = mvhc->hc_iot; 2798 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 2799 &mvport->port_sata_sstatus); 2800 if (rv != 0) { 2801 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 2802 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2803 goto fail0; 2804 } 2805 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 2806 &mvport->port_sata_serror); 2807 if (rv != 0) { 2808 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 2809 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2810 goto fail0; 2811 } 2812 if (sc->sc_rev == gen1) 2813 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2814 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 2815 else 2816 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2817 SATA_SC, 4, &mvport->port_sata_scontrol); 2818 if (rv != 0) { 2819 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 2820 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2821 goto fail0; 2822 } 2823 mvport->port_dmat = sc->sc_dmat; 2824 #ifndef MVSATA_WITHOUTDMA 2825 mvsata_quetag_init(mvport); 2826 #endif 2827 mvhc->hc_ports[port] = mvport; 2828 2829 channel = mvhc->hc * sc->sc_port + port; 2830 chp = &mvport->port_ata_channel; 2831 chp->ch_channel = channel; 2832 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 2833 chp->ch_queue = &mvport->port_ata_queue; 2834 sc->sc_ata_channels[channel] = chp; 2835 2836 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 2837 if (rv != 0) 2838 goto fail0; 2839 2840 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 2841 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 2842 if (rv != 0) { 2843 aprint_error( 2844 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 2845 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2846 goto fail0; 2847 } 2848 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 2849 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 2850 if (rv != 0) { 2851 aprint_error( 2852 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 2853 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2854 goto fail1; 2855 } 2856 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 2857 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 2858 if (rv != 0) { 2859 aprint_error( 2860 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 2861 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2862 goto fail2; 2863 } 2864 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 2865 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 2866 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 2867 &mvport->port_reqtbl[i].data_dmamap); 2868 if (rv != 0) { 2869 aprint_error("%s:%d:%d:" 2870 " EDMA data map(%d) create failed: error=%d\n", 2871 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 2872 rv); 2873 goto fail3; 2874 } 2875 } 2876 2877 return 0; 2878 2879 fail3: 2880 for (i--; i >= 0; i--) 2881 bus_dmamap_destroy(mvport->port_dmat, 2882 mvport->port_reqtbl[i].data_dmamap); 2883 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 2884 fail2: 2885 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 2886 fail1: 2887 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 2888 fail0: 2889 return rv; 2890 } 2891 2892 static int 2893 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 2894 { 2895 int hc, port, rv, i; 2896 2897 hc = mvport->port_hc->hc; 2898 port = mvport->port; 2899 2900 /* Create subregion for Shadow Registers Map */ 2901 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2902 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 2903 if (rv != 0) { 2904 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 2905 device_xname(MVSATA_DEV2(mvport)), hc, port); 2906 return rv; 2907 } 2908 wdr->cmd_iot = mvport->port_iot; 2909 2910 /* Once create subregion for each command registers */ 2911 for (i = 0; i < WDC_NREG; i++) { 2912 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2913 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 2914 if (rv != 0) { 2915 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2916 device_xname(MVSATA_DEV2(mvport)), hc, port); 2917 return rv; 2918 } 2919 } 2920 /* Create subregion for Alternate Status register */ 2921 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2922 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 2923 if (rv != 0) { 2924 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2925 device_xname(MVSATA_DEV2(mvport)), hc, port); 2926 return rv; 2927 } 2928 wdr->ctl_iot = mvport->port_iot; 2929 2930 wdc_init_shadow_regs(&mvport->port_ata_channel); 2931 2932 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2933 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 2934 if (rv != 0) { 2935 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 2936 device_xname(MVSATA_DEV2(mvport)), hc, port); 2937 return rv; 2938 } 2939 wdr->sata_iot = mvport->port_iot; 2940 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2941 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 2942 if (rv != 0) { 2943 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 2944 device_xname(MVSATA_DEV2(mvport)), hc, port); 2945 return rv; 2946 } 2947 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2948 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 2949 if (rv != 0) { 2950 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 2951 device_xname(MVSATA_DEV2(mvport)), hc, port); 2952 return rv; 2953 } 2954 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2955 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 2956 if (rv != 0) { 2957 aprint_error("%s:%d:%d: couldn't subregion SError\n", 2958 device_xname(MVSATA_DEV2(mvport)), hc, port); 2959 return rv; 2960 } 2961 2962 return 0; 2963 } 2964 2965 2966 #ifndef MVSATA_WITHOUTDMA 2967 /* 2968 * There are functions to determine Host Queue Tag. 2969 * XXXX: We hope to rotate Tag to facilitate debugging. 2970 */ 2971 2972 static inline void 2973 mvsata_quetag_init(struct mvsata_port *mvport) 2974 { 2975 2976 mvport->port_quetagidx = 0; 2977 } 2978 2979 static inline int 2980 mvsata_quetag_get(struct mvsata_port *mvport) 2981 { 2982 int begin = mvport->port_quetagidx; 2983 2984 do { 2985 if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) { 2986 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2987 return mvport->port_quetagidx; 2988 } 2989 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2990 } while (mvport->port_quetagidx != begin); 2991 2992 return -1; 2993 } 2994 2995 static inline void 2996 mvsata_quetag_put(struct mvsata_port *mvport, int quetag) 2997 { 2998 2999 /* nothing */ 3000 } 3001 3002 static void * 3003 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3004 bus_dmamap_t *dmamap, size_t size, int write) 3005 { 3006 bus_dma_segment_t seg; 3007 int nseg, rv; 3008 void *kva; 3009 3010 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3011 BUS_DMA_NOWAIT); 3012 if (rv != 0) { 3013 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3014 device_xname(MVSATA_DEV2(mvport)), 3015 mvport->port_hc->hc, mvport->port, rv); 3016 goto fail; 3017 } 3018 3019 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3020 if (rv != 0) { 3021 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3022 device_xname(MVSATA_DEV2(mvport)), 3023 mvport->port_hc->hc, mvport->port, rv); 3024 goto free; 3025 } 3026 3027 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3028 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3029 if (rv != 0) { 3030 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3031 device_xname(MVSATA_DEV2(mvport)), 3032 mvport->port_hc->hc, mvport->port, rv); 3033 goto unmap; 3034 } 3035 3036 if (!write) 3037 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3038 3039 return kva; 3040 3041 unmap: 3042 bus_dmamem_unmap(dmat, kva, size); 3043 free: 3044 bus_dmamem_free(dmat, &seg, nseg); 3045 fail: 3046 return NULL; 3047 } 3048 3049 /* ARGSUSED */ 3050 static void 3051 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3052 bus_dmamap_t dmamap, void *kva) 3053 { 3054 3055 bus_dmamap_unload(dmat, dmamap); 3056 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3057 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3058 } 3059 3060 static int 3061 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3062 size_t datalen, int flags) 3063 { 3064 int rv, lop, sop; 3065 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3066 3067 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3068 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3069 3070 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3071 NULL, BUS_DMA_NOWAIT | lop); 3072 if (rv) { 3073 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3074 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3075 mvport->port, rv); 3076 return rv; 3077 } 3078 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3079 data_dmamap->dm_mapsize, sop); 3080 3081 return 0; 3082 } 3083 3084 static inline void 3085 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3086 { 3087 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3088 3089 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3090 data_dmamap->dm_mapsize, 3091 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3092 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3093 } 3094 #endif 3095 3096 static void 3097 mvsata_hreset_port(struct mvsata_port *mvport) 3098 { 3099 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3100 3101 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3102 3103 delay(25); /* allow reset propagation */ 3104 3105 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3106 3107 mvport->_fix_phy_param._fix_phy(mvport); 3108 3109 if (sc->sc_gen == gen1) 3110 delay(1000); 3111 } 3112 3113 static void 3114 mvsata_reset_port(struct mvsata_port *mvport) 3115 { 3116 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3117 3118 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3119 3120 mvsata_hreset_port(mvport); 3121 3122 if (device_is_a(parent, "pci")) 3123 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3124 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3125 else /* SoC */ 3126 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3127 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3128 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3129 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3130 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3131 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3132 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3133 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3134 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3135 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3136 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3137 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3138 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3139 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3140 3141 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3142 } 3143 3144 static void 3145 mvsata_reset_hc(struct mvsata_hc *mvhc) 3146 { 3147 #if 0 3148 uint32_t val; 3149 #endif 3150 3151 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3152 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3153 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3154 3155 #if 0 /* XXXX needs? */ 3156 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3157 3158 /* 3159 * Keep the SS during power on and the reference clock bits (reset 3160 * sample) 3161 */ 3162 val = MVSATA_HC_READ_4(mvhc, 0x020); 3163 val &= 0x1c1c1c1c; 3164 val |= 0x03030303; 3165 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3166 #endif 3167 } 3168 3169 #ifndef MVSATA_WITHOUTDMA 3170 static void 3171 mvsata_softreset(struct mvsata_port *mvport, int waitok) 3172 { 3173 uint32_t stat; 3174 int i; 3175 3176 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS); 3177 delay(10); 3178 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS); 3179 delay(2000); 3180 3181 if (waitok) { 3182 /* wait maximum 31sec */ 3183 for (i = 31000; i > 0; i--) { 3184 stat = MVSATA_WDC_READ_1(mvport, SRB_CS); 3185 if (!(stat & WDCS_BSY)) 3186 break; 3187 delay(1000); 3188 } 3189 if (i == 0) 3190 aprint_error("%s:%d:%d: soft reset failed\n", 3191 device_xname(MVSATA_DEV2(mvport)), 3192 mvport->port_hc->hc, mvport->port); 3193 } 3194 } 3195 3196 static void 3197 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3198 { 3199 const bus_addr_t crpb_addr = 3200 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3201 const uint32_t crpb_addr_mask = 3202 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3203 3204 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3205 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3206 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3207 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3208 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3209 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3210 } 3211 3212 static inline void 3213 mvsata_edma_enable(struct mvsata_port *mvport) 3214 { 3215 3216 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3217 } 3218 3219 static int 3220 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok) 3221 { 3222 uint32_t status, command; 3223 int ms; 3224 3225 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3226 for (ms = 0; ms < timeout; ms++) { 3227 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3228 if (status & EDMA_S_EDMAIDLE) 3229 break; 3230 if (waitok) 3231 tsleep(&waitok, PRIBIO, "mvsata_edma1", 3232 mstohz(1)); 3233 else 3234 delay(1000); 3235 } 3236 if (ms == timeout) 3237 return EBUSY; 3238 3239 /* The diable bit (eDsEDMA) is self negated. */ 3240 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3241 3242 for ( ; ms < timeout; ms++) { 3243 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3244 if (!(command & EDMA_CMD_EENEDMA)) 3245 break; 3246 if (waitok) 3247 tsleep(&waitok, PRIBIO, "mvsata_edma2", 3248 mstohz(1)); 3249 else 3250 delay(1000); 3251 } 3252 if (ms == timeout) { 3253 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3254 device_xname(MVSATA_DEV2(mvport)), 3255 mvport->port_hc->hc, mvport->port); 3256 return EBUSY; 3257 } 3258 } 3259 return 0; 3260 } 3261 3262 /* 3263 * Set EDMA registers according to mode. 3264 * ex. NCQ/TCQ(queued)/non queued. 3265 */ 3266 static void 3267 mvsata_edma_config(struct mvsata_port *mvport, int mode) 3268 { 3269 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3270 uint32_t reg; 3271 3272 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3273 reg |= EDMA_CFG_RESERVED; 3274 3275 if (mode == ncq) { 3276 if (sc->sc_gen == gen1) { 3277 aprint_error_dev(MVSATA_DEV2(mvport), 3278 "GenI not support NCQ\n"); 3279 return; 3280 } else if (sc->sc_gen == gen2) 3281 reg |= EDMA_CFG_EDEVERR; 3282 reg |= EDMA_CFG_ESATANATVCMDQUE; 3283 } else if (mode == queued) { 3284 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3285 reg |= EDMA_CFG_EQUE; 3286 } else 3287 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3288 3289 if (sc->sc_gen == gen1) 3290 reg |= EDMA_CFG_ERDBSZ; 3291 else if (sc->sc_gen == gen2) 3292 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3293 else if (sc->sc_gen == gen2e) { 3294 device_t parent = device_parent(MVSATA_DEV(sc)); 3295 3296 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3297 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3298 3299 if (device_is_a(parent, "pci")) 3300 reg |= ( 3301 #if NATAPIBUS > 0 3302 EDMA_CFG_EEARLYCOMPLETIONEN | 3303 #endif 3304 EDMA_CFG_ECUTTHROUGHEN | 3305 EDMA_CFG_EWRBUFFERLEN | 3306 EDMA_CFG_ERDBSZEXT); 3307 } 3308 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3309 3310 reg = ( 3311 EDMA_IE_EIORDYERR | 3312 EDMA_IE_ETRANSINT | 3313 EDMA_IE_EDEVCON | 3314 EDMA_IE_EDEVDIS); 3315 if (sc->sc_gen != gen1) 3316 reg |= ( 3317 EDMA_IE_TRANSPROTERR | 3318 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3319 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3320 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3321 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3322 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3323 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3324 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3325 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3326 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3327 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3328 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3329 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3330 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3331 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3332 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3333 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3334 EDMA_IE_ESELFDIS); 3335 3336 if (mode == ncq) 3337 reg |= EDMA_IE_EDEVERR; 3338 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3339 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3340 reg &= ~EDMA_IE_EDEVERR; 3341 if (mode != ncq) 3342 reg |= EDMA_IE_EDEVERR; 3343 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3344 if (sc->sc_gen == gen2e) { 3345 /* 3346 * Clear FISWait4HostRdyEn[0] and [2]. 3347 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3348 * [2]: SDB FIS is received with <ERR> bit set to 1. 3349 */ 3350 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3351 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3352 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3353 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3354 } 3355 3356 mvport->port_edmamode = mode; 3357 } 3358 3359 3360 /* 3361 * Generation dependent functions 3362 */ 3363 3364 static void 3365 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag, 3366 struct ata_bio *ata_bio) 3367 { 3368 struct crqb *crqb; 3369 bus_addr_t eprd_addr; 3370 daddr_t blkno; 3371 uint32_t rw; 3372 uint8_t cmd, head; 3373 int i; 3374 const int drive = 3375 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3376 3377 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3378 mvport->port_reqtbl[quetag].eprd_offset; 3379 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3380 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3381 head = WDSD_LBA; 3382 blkno = ata_bio->blkno; 3383 if (ata_bio->flags & ATA_LBA48) 3384 cmd = atacmd_to48(cmd); 3385 else { 3386 head |= ((ata_bio->blkno >> 24) & 0xf); 3387 blkno &= 0xffffff; 3388 } 3389 crqb = &mvport->port_crqb->crqb + erqqip; 3390 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3391 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3392 crqb->ctrlflg = 3393 htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive)); 3394 i = 0; 3395 if (mvport->port_edmamode == dma) { 3396 if (ata_bio->flags & ATA_LBA48) 3397 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3398 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3399 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3400 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3401 } else { /* ncq/queued */ 3402 3403 /* 3404 * XXXX: Oops, ata command is not correct. And, atabus layer 3405 * has not been supported yet now. 3406 * Queued DMA read/write. 3407 * read/write FPDMAQueued. 3408 */ 3409 3410 if (ata_bio->flags & ATA_LBA48) 3411 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3412 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3413 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3414 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3415 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3416 CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3)); 3417 } 3418 if (ata_bio->flags & ATA_LBA48) { 3419 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3420 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3421 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3422 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3423 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3424 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3425 } 3426 crqb->atacommand[i++] = 3427 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3428 crqb->atacommand[i++] = 3429 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3430 crqb->atacommand[i++] = 3431 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3432 crqb->atacommand[i++] = 3433 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3434 crqb->atacommand[i++] = htole16( 3435 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3436 CRQB_ATACOMMAND_LAST); 3437 } 3438 #endif 3439 3440 static uint32_t 3441 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3442 { 3443 struct mvsata_hc *hc = mvport->port_hc; 3444 uint32_t reg; 3445 3446 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3447 /* 3448 * [12:11] : pre 3449 * [7:5] : amps 3450 */ 3451 return reg & 0x000018e0; 3452 } 3453 3454 static void 3455 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3456 { 3457 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3458 struct mvsata_hc *mvhc = mvport->port_hc; 3459 uint32_t reg; 3460 int port = mvport->port, fix_apm_sq = 0; 3461 3462 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3463 if (sc->sc_rev == 0x01) 3464 fix_apm_sq = 1; 3465 } else { 3466 if (sc->sc_rev == 0x00) 3467 fix_apm_sq = 1; 3468 } 3469 3470 if (fix_apm_sq) { 3471 /* 3472 * Disable auto-power management 3473 * 88SX50xx FEr SATA#12 3474 */ 3475 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3476 reg |= (1 << 19); 3477 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3478 3479 /* 3480 * Fix squelch threshold 3481 * 88SX50xx FEr SATA#9 3482 */ 3483 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3484 reg &= ~0x3; 3485 reg |= 0x1; 3486 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3487 } 3488 3489 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3490 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3491 reg &= ~0x000018e0; /* pre and amps mask */ 3492 reg |= mvport->_fix_phy_param.pre_amps; 3493 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3494 } 3495 3496 static void 3497 mvsata_devconn_gen1(struct mvsata_port *mvport) 3498 { 3499 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3500 3501 /* Fix for 88SX50xx FEr SATA#2 */ 3502 mvport->_fix_phy_param._fix_phy(mvport); 3503 3504 /* If disk is connected, then enable the activity LED */ 3505 if (sc->sc_rev == 0x03) { 3506 /* XXXXX */ 3507 } 3508 } 3509 3510 static uint32_t 3511 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3512 { 3513 uint32_t reg; 3514 3515 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3516 /* 3517 * [10:8] : amps 3518 * [7:5] : pre 3519 */ 3520 return reg & 0x000007e0; 3521 } 3522 3523 static void 3524 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3525 { 3526 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3527 uint32_t reg; 3528 3529 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3530 sc->sc_gen == gen2e) { 3531 /* 3532 * Fix for 3533 * 88SX60X1 FEr SATA #23 3534 * 88SX6042/88SX7042 FEr SATA #23 3535 * 88F5182 FEr #SATA-S13 3536 * 88F5082 FEr #SATA-S13 3537 */ 3538 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3539 reg &= ~(1 << 16); 3540 reg |= (1 << 31); 3541 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3542 3543 delay(200); 3544 3545 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3546 reg &= ~((1 << 16) | (1 << 31)); 3547 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3548 3549 delay(200); 3550 } 3551 3552 /* Fix values in PHY Mode 3 Register.*/ 3553 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3554 reg &= ~0x7F900000; 3555 reg |= 0x2A800000; 3556 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3557 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3558 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3559 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3560 reg &= ~0x0000001c; 3561 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3562 3563 /* 3564 * Fix values in PHY Mode 4 Register. 3565 * 88SX60x1 FEr SATA#10 3566 * 88F5182 GL #SATA-S10 3567 * 88F5082 GL #SATA-S10 3568 */ 3569 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3570 sc->sc_gen == gen2e) { 3571 uint32_t tmp = 0; 3572 3573 /* 88SX60x1 FEr SATA #13 */ 3574 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3575 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3576 3577 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3578 reg |= (1 << 0); 3579 reg &= ~(1 << 1); 3580 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3581 if (sc->sc_gen == gen2e) { 3582 reg &= ~0x5de3fffc; 3583 reg |= (1 << 2); 3584 } 3585 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3586 3587 /* 88SX60x1 FEr SATA #13 */ 3588 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3589 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3590 } 3591 3592 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3593 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3594 reg &= ~0x000007e0; /* pre and amps mask */ 3595 reg |= mvport->_fix_phy_param.pre_amps; 3596 reg &= ~(1 << 16); 3597 if (sc->sc_gen == gen2e) { 3598 /* 3599 * according to mvSata 3.6.1, some IIE values are fixed. 3600 * some reserved fields must be written with fixed values. 3601 */ 3602 reg &= ~0xC30FF01F; 3603 reg |= 0x0000900F; 3604 } 3605 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3606 } 3607 3608 #ifndef MVSATA_WITHOUTDMA 3609 static void 3610 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag, 3611 struct ata_bio *ata_bio) 3612 { 3613 struct crqb_gen2e *crqb; 3614 bus_addr_t eprd_addr; 3615 daddr_t blkno; 3616 uint32_t ctrlflg, rw; 3617 uint8_t cmd, head; 3618 const int drive = 3619 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3620 3621 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3622 mvport->port_reqtbl[quetag].eprd_offset; 3623 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3624 ctrlflg = (rw | CRQB_CDEVICEQUETAG(quetag) | CRQB_CPMPORT(drive) | 3625 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag)); 3626 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3627 head = WDSD_LBA; 3628 blkno = ata_bio->blkno; 3629 if (ata_bio->flags & ATA_LBA48) 3630 cmd = atacmd_to48(cmd); 3631 else { 3632 head |= ((ata_bio->blkno >> 24) & 0xf); 3633 blkno &= 0xffffff; 3634 } 3635 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3636 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3637 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3638 crqb->ctrlflg = htole32(ctrlflg); 3639 if (mvport->port_edmamode == dma) { 3640 crqb->atacommand[0] = htole32(cmd << 16); 3641 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3642 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff)); 3643 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3644 } else { /* ncq/queued */ 3645 3646 /* 3647 * XXXX: Oops, ata command is not correct. And, atabus layer 3648 * has not been supported yet now. 3649 * Queued DMA read/write. 3650 * read/write FPDMAQueued. 3651 */ 3652 3653 crqb->atacommand[0] = htole32( 3654 (cmd << 16) | ((ata_bio->nblks & 0xff) << 24)); 3655 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3656 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) | 3657 ((ata_bio->nblks >> 8) & 0xff)); 3658 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3659 crqb->atacommand[3] = htole32(quetag << 3); 3660 } 3661 } 3662 3663 3664 #ifdef MVSATA_DEBUG 3665 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3666 do { \ 3667 int _i; \ 3668 u_char *_p = (p); \ 3669 \ 3670 printf(#type "(%d)", (n)); \ 3671 for (_i = 0; _i < (size); _i++, _p++) { \ 3672 if (_i % 16 == 0) \ 3673 printf("\n "); \ 3674 printf(" %02x", *_p); \ 3675 } \ 3676 printf("\n"); \ 3677 } while (0 /* CONSTCOND */) 3678 3679 static void 3680 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3681 { 3682 3683 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3684 n, (u_char *)(mvport->port_crqb + n)); 3685 } 3686 3687 static void 3688 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3689 { 3690 3691 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3692 n, (u_char *)(mvport->port_crpb + n)); 3693 } 3694 3695 static void 3696 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3697 { 3698 struct eprd *eprd; 3699 int i = 0; 3700 3701 eprd = mvport->port_reqtbl[n].eprd; 3702 while (1 /*CONSTCOND*/) { 3703 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3704 i, (u_char *)eprd); 3705 if (eprd->eot & EPRD_EOT) 3706 break; 3707 eprd++; 3708 i++; 3709 } 3710 } 3711 #endif 3712 #endif 3713
Indexes created Wed Sep 24 22:09:59 GMT 2025