mvsata.c revision 1.41
1 /* $NetBSD: mvsata.c,v 1.41 2018/08/31 18:43:29 jdolecek Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.41 2018/08/31 18:43:29 jdolecek Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 #include <dev/ic/mvsatareg.h> 62 #include <dev/ic/mvsatavar.h> 63 64 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 65 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 66 67 #define MVSATA_HC_READ_4(hc, reg) \ 68 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 69 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 70 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 71 #define MVSATA_EDMA_READ_4(mvport, reg) \ 72 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 73 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 74 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 75 #define MVSATA_WDC_READ_2(mvport, reg) \ 76 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 77 SHADOW_REG_BLOCK_OFFSET + (reg)) 78 #define MVSATA_WDC_READ_1(mvport, reg) \ 79 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 80 SHADOW_REG_BLOCK_OFFSET + (reg)) 81 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 82 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 83 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 84 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 85 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 86 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 87 88 #ifdef MVSATA_DEBUG 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_FUNCS 0x08 93 #define DEBUG_PROBE 0x10 94 95 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 96 int mvsata_debug = 0; 97 #else 98 #define DPRINTF(n,x) 99 #endif 100 101 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 102 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 103 sending a cmd */ 104 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 105 106 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 107 108 109 static void mvsata_probe_drive(struct ata_channel *); 110 static void mvsata_reset_channel(struct ata_channel *, int); 111 112 #ifndef MVSATA_WITHOUTDMA 113 static int mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 114 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 115 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 116 static int mvsata_addref(struct ata_drive_datas *); 117 static void mvsata_delref(struct ata_drive_datas *); 118 static void mvsata_killpending(struct ata_drive_datas *); 119 120 #if NATAPIBUS > 0 121 static void mvsata_atapibus_attach(struct atabus_softc *); 122 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 123 scsipi_adapter_req_t, void *); 124 static void mvsata_atapi_minphys(struct buf *); 125 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 126 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 127 #endif 128 #endif 129 130 static void mvsata_setup_channel(struct ata_channel *); 131 132 #ifndef MVSATA_WITHOUTDMA 133 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 134 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 135 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 136 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 137 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 138 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 139 int); 140 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 141 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 142 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 143 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 144 int); 145 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 147 #if NATAPIBUS > 0 148 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 149 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 150 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 151 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 152 int); 153 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 154 static void mvsata_atapi_phase_complete(struct ata_xfer *); 155 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 156 static void mvsata_atapi_polldsc(void *); 157 #endif 158 159 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 160 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 161 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 162 static void mvsata_edma_timeout(void *); 163 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 164 #if NATAPIBUS > 0 165 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 166 static void mvsata_bdma_start(struct mvsata_port *); 167 #endif 168 #endif 169 170 static int mvsata_nondma_handle(struct mvsata_port *); 171 static void mvsata_channel_recover(struct mvsata_port *); 172 173 static int mvsata_port_init(struct mvsata_hc *, int); 174 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 175 #ifndef MVSATA_WITHOUTDMA 176 static inline void mvsata_quetag_get(struct mvsata_port *, uint8_t); 177 static inline void mvsata_quetag_put(struct mvsata_port *, uint8_t); 178 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 179 bus_dmamap_t *, size_t, int); 180 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 181 bus_dmamap_t, void *); 182 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 183 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 184 #endif 185 186 static void mvsata_hreset_port(struct mvsata_port *); 187 static void mvsata_reset_port(struct mvsata_port *); 188 static void mvsata_reset_hc(struct mvsata_hc *); 189 static uint32_t mvsata_softreset(struct mvsata_port *, int); 190 #ifndef MVSATA_WITHOUTDMA 191 static void mvsata_edma_reset_qptr(struct mvsata_port *); 192 static inline void mvsata_edma_enable(struct mvsata_port *); 193 static int mvsata_edma_disable(struct mvsata_port *, int, int); 194 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 195 196 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 197 struct ata_xfer *); 198 #endif 199 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 200 static void mvsata_fix_phy_gen1(struct mvsata_port *); 201 static void mvsata_devconn_gen1(struct mvsata_port *); 202 203 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 204 static void mvsata_fix_phy_gen2(struct mvsata_port *); 205 #ifndef MVSATA_WITHOUTDMA 206 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 207 struct ata_xfer *); 208 209 #ifdef MVSATA_DEBUG 210 static void mvsata_print_crqb(struct mvsata_port *, int); 211 static void mvsata_print_crpb(struct mvsata_port *, int); 212 static void mvsata_print_eprd(struct mvsata_port *, int); 213 #endif 214 215 static const struct ata_bustype mvsata_ata_bustype = { 216 SCSIPI_BUSTYPE_ATA, 217 mvsata_bio, 218 mvsata_reset_drive, 219 mvsata_reset_channel, 220 mvsata_exec_command, 221 ata_get_params, 222 mvsata_addref, 223 mvsata_delref, 224 mvsata_killpending 225 }; 226 227 #if NATAPIBUS > 0 228 static const struct scsipi_bustype mvsata_atapi_bustype = { 229 SCSIPI_BUSTYPE_ATAPI, 230 atapi_scsipi_cmd, 231 atapi_interpret_sense, 232 atapi_print_addr, 233 mvsata_atapi_kill_pending, 234 NULL, 235 }; 236 #endif /* NATAPIBUS */ 237 #endif 238 239 static void 240 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 241 { 242 uint32_t ifctl; 243 244 KASSERT(pmpport < PMP_MAX_DRIVES); 245 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 246 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 247 panic("EDMA enabled"); 248 } 249 #endif 250 251 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 252 ifctl &= ~0xf; 253 ifctl |= pmpport; 254 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 255 } 256 257 int 258 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 259 int (*mvsata_sreset)(struct mvsata_softc *), 260 int (*mvsata_misc_reset)(struct mvsata_softc *), 261 int read_pre_amps) 262 { 263 struct mvsata_hc *mvhc; 264 struct mvsata_port *mvport; 265 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 266 void (*_fix_phy)(struct mvsata_port *) = NULL; 267 #ifndef MVSATA_WITHOUTDMA 268 void (*edma_setup_crqb) 269 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 270 #endif 271 int hc, port, channel; 272 273 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 274 (product->generation == gen1) ? "I" : 275 ((product->generation == gen2) ? "II" : "IIe"), 276 product->hc, product->port); 277 278 279 switch (product->generation) { 280 case gen1: 281 mvsata_sreset = NULL; 282 read_pre_amps = 1; /* MUST */ 283 read_preamps = mvsata_read_preamps_gen1; 284 _fix_phy = mvsata_fix_phy_gen1; 285 #ifndef MVSATA_WITHOUTDMA 286 edma_setup_crqb = mvsata_edma_setup_crqb; 287 #endif 288 break; 289 290 case gen2: 291 read_preamps = mvsata_read_preamps_gen2; 292 _fix_phy = mvsata_fix_phy_gen2; 293 #ifndef MVSATA_WITHOUTDMA 294 edma_setup_crqb = mvsata_edma_setup_crqb; 295 #endif 296 break; 297 298 case gen2e: 299 read_preamps = mvsata_read_preamps_gen2; 300 _fix_phy = mvsata_fix_phy_gen2; 301 #ifndef MVSATA_WITHOUTDMA 302 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 303 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 304 #endif 305 break; 306 } 307 308 sc->sc_gen = product->generation; 309 sc->sc_hc = product->hc; 310 sc->sc_port = product->port; 311 sc->sc_flags = product->flags; 312 313 #ifdef MVSATA_WITHOUTDMA 314 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 315 #else 316 sc->sc_edma_setup_crqb = edma_setup_crqb; 317 sc->sc_wdcdev.sc_atac.atac_cap |= 318 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 319 #endif 320 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 321 #ifdef MVSATA_WITHOUTDMA 322 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 323 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 324 #else 325 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 326 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 327 #endif 328 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 329 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 330 #ifndef MVSATA_WITHOUTDMA 331 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 332 #if NATAPIBUS > 0 333 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 334 #endif 335 #endif 336 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 337 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 338 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 339 340 sc->sc_wdc_regs = 341 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 342 M_DEVBUF, M_NOWAIT); 343 if (sc->sc_wdc_regs == NULL) { 344 aprint_error_dev(MVSATA_DEV(sc), 345 "can't allocate wdc regs memory\n"); 346 return ENOMEM; 347 } 348 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 349 350 for (hc = 0; hc < sc->sc_hc; hc++) { 351 mvhc = &sc->sc_hcs[hc]; 352 mvhc->hc = hc; 353 mvhc->hc_sc = sc; 354 mvhc->hc_iot = sc->sc_iot; 355 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 356 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 357 &mvhc->hc_ioh)) { 358 aprint_error_dev(MVSATA_DEV(sc), 359 "can't subregion SATAHC %d registers\n", hc); 360 continue; 361 } 362 363 for (port = 0; port < sc->sc_port; port++) 364 if (mvsata_port_init(mvhc, port) == 0) { 365 int pre_amps; 366 367 mvport = mvhc->hc_ports[port]; 368 pre_amps = read_pre_amps ? 369 read_preamps(mvport) : 0x00000720; 370 mvport->_fix_phy_param.pre_amps = pre_amps; 371 mvport->_fix_phy_param._fix_phy = _fix_phy; 372 373 if (!mvsata_sreset) 374 mvsata_reset_port(mvport); 375 } 376 377 if (!mvsata_sreset) 378 mvsata_reset_hc(mvhc); 379 } 380 if (mvsata_sreset) 381 mvsata_sreset(sc); 382 383 if (mvsata_misc_reset) 384 mvsata_misc_reset(sc); 385 386 for (hc = 0; hc < sc->sc_hc; hc++) 387 for (port = 0; port < sc->sc_port; port++) { 388 mvport = sc->sc_hcs[hc].hc_ports[port]; 389 if (mvport == NULL) 390 continue; 391 if (mvsata_sreset) 392 mvport->_fix_phy_param._fix_phy(mvport); 393 } 394 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 395 wdcattach(sc->sc_ata_channels[channel]); 396 397 return 0; 398 } 399 400 int 401 mvsata_intr(struct mvsata_hc *mvhc) 402 { 403 struct mvsata_softc *sc = mvhc->hc_sc; 404 struct mvsata_port *mvport; 405 uint32_t cause; 406 int port, handled = 0; 407 408 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 409 410 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 411 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 412 413 if (cause & SATAHC_IC_SAINTCOAL) 414 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 415 cause &= ~SATAHC_IC_SAINTCOAL; 416 417 for (port = 0; port < sc->sc_port; port++) { 418 mvport = mvhc->hc_ports[port]; 419 420 if (cause & SATAHC_IC_DONE(port)) { 421 #ifndef MVSATA_WITHOUTDMA 422 handled = mvsata_edma_handle(mvport, NULL); 423 #endif 424 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 425 ~SATAHC_IC_DONE(port)); 426 } 427 428 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 429 (void) mvsata_nondma_handle(mvport); 430 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 431 ~SATAHC_IC_SADEVINTERRUPT(port)); 432 handled = 1; 433 } 434 } 435 436 return handled; 437 } 438 439 static int 440 mvsata_nondma_handle(struct mvsata_port *mvport) 441 { 442 struct ata_channel *chp = &mvport->port_ata_channel; 443 struct ata_xfer *xfer; 444 int ret; 445 446 /* 447 * The chip doesn't support several pending non-DMA commands, 448 * and the ata middle layer never issues several non-NCQ commands, 449 * so there must be exactly one active command at this moment. 450 */ 451 xfer = ata_queue_get_active_xfer(chp); 452 if (xfer == NULL) { 453 /* Can happen after error recovery, ignore */ 454 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 455 ("%s:%d: %s: intr without xfer\n", 456 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 457 __func__)); 458 return 0; 459 } 460 461 ret = xfer->c_intr(chp, xfer, 1); 462 return (ret); 463 } 464 465 int 466 mvsata_error(struct mvsata_port *mvport) 467 { 468 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 469 uint32_t cause; 470 471 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 472 /* 473 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 474 * in EDMA_IEC. 475 */ 476 if (cause & EDMA_IE_SERRINT) { 477 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 478 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 479 } 480 if (cause & EDMA_IE_ETRANSINT) { 481 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 482 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 483 } 484 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 485 486 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 487 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 488 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 489 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 490 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 491 492 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 493 if (!cause) 494 return 0; 495 496 if (cause & EDMA_IE_EDEVDIS) { 497 aprint_normal("%s:%d:%d: device disconnect\n", 498 device_xname(MVSATA_DEV2(mvport)), 499 mvport->port_hc->hc, mvport->port); 500 } 501 if (cause & EDMA_IE_EDEVCON) { 502 if (sc->sc_gen == gen1) 503 mvsata_devconn_gen1(mvport); 504 505 DPRINTF(DEBUG_INTR, (" device connected\n")); 506 } 507 508 #ifndef MVSATA_WITHOUTDMA 509 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 510 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 511 switch (mvport->port_edmamode_curr) { 512 case dma: 513 case queued: 514 case ncq: 515 mvsata_edma_reset_qptr(mvport); 516 mvsata_edma_enable(mvport); 517 if (cause & EDMA_IE_EDEVERR) 518 break; 519 520 /* FALLTHROUGH */ 521 522 case nodma: 523 default: 524 aprint_error( 525 "%s:%d:%d: EDMA self disable happen 0x%x\n", 526 device_xname(MVSATA_DEV2(mvport)), 527 mvport->port_hc->hc, mvport->port, cause); 528 break; 529 } 530 } 531 #endif 532 if (cause & EDMA_IE_ETRANSINT) { 533 /* hot plug the Port Multiplier */ 534 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 535 device_xname(MVSATA_DEV2(mvport)), 536 mvport->port_hc->hc, mvport->port); 537 } 538 if (cause & EDMA_IE_EDEVERR) { 539 aprint_error("%s:%d:%d: device error, recovering\n", 540 device_xname(MVSATA_DEV2(mvport)), 541 mvport->port_hc->hc, mvport->port); 542 543 if (!mvport->port_recovering) 544 mvsata_channel_recover(mvport); 545 } 546 547 return 1; 548 } 549 550 static void 551 mvsata_hold(struct mvsata_port *mvport) 552 { 553 mvport->port_hold_slots |= mvport->port_quetagidx; 554 mvport->port_quetagidx = 0; 555 } 556 557 static void 558 mvsata_unhold(struct mvsata_port *mvport) 559 { 560 mvport->port_quetagidx = mvport->port_hold_slots; 561 mvport->port_hold_slots = 0; 562 } 563 564 static void 565 mvsata_channel_recover(struct mvsata_port *mvport) 566 { 567 struct ata_channel *chp = &mvport->port_ata_channel; 568 struct ata_drive_datas *drvp; 569 int drive, error; 570 uint8_t eslot, slot, st, err; 571 struct ata_xfer *xfer; 572 573 KASSERT(!mvport->port_recovering); 574 575 mvport->port_recovering = true; 576 577 if (chp->ch_ndrives > PMP_PORT_CTL) { 578 /* Get PM port number for the device in error. This device 579 * doesn't seem to have dedicated register for this, so just 580 * assume last selected port was the one. */ 581 /* XXX FIS-based switching */ 582 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 583 } else 584 drive = 0; 585 586 drvp = &chp->ch_drive[drive]; 587 588 /* 589 * Controller doesn't need any special action. Simply execute 590 * READ LOG EXT for NCQ to unblock device processing, then continue 591 * as if nothing happened. 592 */ 593 KASSERT(drive >= 0); 594 595 mvsata_hold(mvport); 596 597 /* 598 * When running NCQ commands, READ LOG EXT is necessary to clear the 599 * error condition and unblock the device. 600 */ 601 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 602 603 mvsata_unhold(mvport); 604 605 switch (error) { 606 case 0: 607 /* Error out the particular NCQ xfer, then requeue the others */ 608 if ((mvport->port_quetagidx & (1 << eslot)) != 0) { 609 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 610 xfer->c_flags |= C_RECOVERED; 611 xfer->c_bio.error = ERROR; 612 xfer->c_bio.r_error = err; 613 xfer->c_intr(chp, xfer, 1); 614 } 615 break; 616 617 case EOPNOTSUPP: 618 /* 619 * Non-NCQ command error, just find the slot and end it with 620 * an error. Handler figures the error itself. 621 */ 622 for (slot = 0; slot < MVSATA_EDMAQ_LEN; slot++) { 623 if ((mvport->port_quetagidx & (1 << slot)) != 0) { 624 xfer = ata_queue_hwslot_to_xfer(chp, slot); 625 if (xfer->c_drive != drive) 626 continue; 627 628 xfer->c_intr(chp, xfer, 1); 629 } 630 } 631 break; 632 633 case EAGAIN: 634 /* 635 * Failed to get resources to run the recovery command, must 636 * reset the drive. This will also kill all still outstanding 637 * transfers. 638 */ 639 mvsata_reset_channel(chp, AT_POLL); 640 goto out; 641 /* NOTREACHED */ 642 643 default: 644 /* 645 * The command to get the slot failed. Kill outstanding 646 * commands for the same drive only. No need to reset 647 * the drive, it's unblocked nevertheless. 648 */ 649 break; 650 } 651 652 /* Requeue the non-errorred commands */ 653 for (slot = 0; slot < MVSATA_EDMAQ_LEN; slot++) { 654 if (((mvport->port_quetagidx >> slot) & 1) == 0) 655 continue; 656 657 xfer = ata_queue_hwslot_to_xfer(chp, slot); 658 if (xfer->c_drive != drive) 659 continue; 660 661 xfer->c_kill_xfer(chp, xfer, 662 (error == 0) ? KILL_REQUEUE : KILL_RESET); 663 } 664 665 out: 666 /* Drive unblocked, back to normal operation */ 667 mvport->port_recovering = false; 668 atastart(chp); 669 } 670 671 /* 672 * ATA callback entry points 673 */ 674 675 static void 676 mvsata_probe_drive(struct ata_channel *chp) 677 { 678 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 679 uint32_t sstat, sig; 680 681 ata_channel_lock(chp); 682 683 sstat = sata_reset_interface(chp, mvport->port_iot, 684 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 685 switch (sstat) { 686 case SStatus_DET_DEV: 687 mvsata_pmp_select(mvport, PMP_PORT_CTL); 688 sig = mvsata_softreset(mvport, AT_WAIT); 689 sata_interpret_sig(chp, 0, sig); 690 break; 691 default: 692 break; 693 } 694 695 ata_channel_unlock(chp); 696 } 697 698 #ifndef MVSATA_WITHOUTDMA 699 static void 700 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 701 { 702 struct ata_channel *chp = drvp->chnl_softc; 703 struct mvsata_port *mvport = (struct mvsata_port *)chp; 704 uint32_t edma_c; 705 uint32_t sig; 706 707 ata_channel_lock(chp); 708 709 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 710 711 DPRINTF(DEBUG_FUNCS, 712 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 713 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 714 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 715 716 if (edma_c & EDMA_CMD_EENEDMA) 717 mvsata_edma_disable(mvport, 10000, flags); 718 719 mvsata_pmp_select(mvport, drvp->drive); 720 721 sig = mvsata_softreset(mvport, flags); 722 723 if (sigp) 724 *sigp = sig; 725 726 if (edma_c & EDMA_CMD_EENEDMA) { 727 mvsata_edma_reset_qptr(mvport); 728 mvsata_edma_enable(mvport); 729 } 730 731 ata_channel_unlock(chp); 732 733 return; 734 } 735 #endif /* MVSATA_WITHOUTDMA */ 736 737 static void 738 mvsata_reset_channel(struct ata_channel *chp, int flags) 739 { 740 struct mvsata_port *mvport = (struct mvsata_port *)chp; 741 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 742 uint32_t sstat, ctrl; 743 744 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 745 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 746 747 ata_channel_lock(chp); 748 749 mvsata_hreset_port(mvport); 750 sstat = sata_reset_interface(chp, mvport->port_iot, 751 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 752 753 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 754 sc->sc_gen != gen1) { 755 /* Downgrade to GenI */ 756 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 757 SControl_DET_DISABLE; 758 759 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 760 761 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 762 ctrl &= ~(1 << 17); /* Disable GenII */ 763 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 764 765 mvsata_hreset_port(mvport); 766 sata_reset_interface(chp, mvport->port_iot, 767 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 768 flags); 769 } 770 771 ata_kill_active(chp, KILL_RESET, flags); 772 773 #ifndef MVSATA_WITHOUTDMA 774 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 775 mvsata_edma_reset_qptr(mvport); 776 mvsata_edma_enable(mvport); 777 #endif 778 779 ata_channel_unlock(chp); 780 781 return; 782 } 783 784 #ifndef MVSATA_WITHOUTDMA 785 static int 786 mvsata_addref(struct ata_drive_datas *drvp) 787 { 788 789 return 0; 790 } 791 792 static void 793 mvsata_delref(struct ata_drive_datas *drvp) 794 { 795 796 return; 797 } 798 799 static void 800 mvsata_killpending(struct ata_drive_datas *drvp) 801 { 802 803 return; 804 } 805 806 #if NATAPIBUS > 0 807 static void 808 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 809 { 810 struct ata_channel *chp = ata_sc->sc_chan; 811 struct atac_softc *atac = chp->ch_atac; 812 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 813 struct scsipi_channel *chan = &chp->ch_atapi_channel; 814 815 /* 816 * Fill in the scsipi_adapter. 817 */ 818 adapt->adapt_dev = atac->atac_dev; 819 adapt->adapt_nchannels = atac->atac_nchannels; 820 adapt->adapt_request = mvsata_atapi_scsipi_request; 821 adapt->adapt_minphys = mvsata_atapi_minphys; 822 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 823 824 /* 825 * Fill in the scsipi_channel. 826 */ 827 memset(chan, 0, sizeof(*chan)); 828 chan->chan_adapter = adapt; 829 chan->chan_bustype = &mvsata_atapi_bustype; 830 chan->chan_channel = chp->ch_channel; 831 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 832 chan->chan_openings = 1; 833 chan->chan_max_periph = 1; 834 chan->chan_ntargets = 1; 835 chan->chan_nluns = 1; 836 837 chp->atapibus = 838 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 839 } 840 841 static void 842 mvsata_atapi_minphys(struct buf *bp) 843 { 844 845 if (bp->b_bcount > MAXPHYS) 846 bp->b_bcount = MAXPHYS; 847 minphys(bp); 848 } 849 850 static void 851 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 852 { 853 struct scsipi_channel *chan = sc->sc_channel; 854 struct scsipi_periph *periph; 855 struct ataparams ids; 856 struct ataparams *id = &ids; 857 struct mvsata_softc *mvc = 858 device_private(chan->chan_adapter->adapt_dev); 859 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 860 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 861 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 862 struct scsipibus_attach_args sa; 863 char serial_number[21], model[41], firmware_revision[9]; 864 int s; 865 866 /* skip if already attached */ 867 if (scsipi_lookup_periph(chan, target, 0) != NULL) 868 return; 869 870 /* if no ATAPI device detected at attach time, skip */ 871 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 872 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 873 " drive %d not present\n", 874 device_xname(atac->atac_dev), chp->ch_channel, target)); 875 return; 876 } 877 878 /* Some ATAPI devices need a bit more time after software reset. */ 879 delay(5000); 880 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 881 #ifdef ATAPI_DEBUG_PROBE 882 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 883 device_xname(sc->sc_dev), target, 884 id->atap_config & ATAPI_CFG_CMD_MASK, 885 id->atap_config & ATAPI_CFG_DRQ_MASK); 886 #endif 887 periph = scsipi_alloc_periph(M_NOWAIT); 888 if (periph == NULL) { 889 aprint_error_dev(atac->atac_dev, 890 "unable to allocate periph" 891 " for channel %d drive %d\n", 892 chp->ch_channel, target); 893 return; 894 } 895 periph->periph_dev = NULL; 896 periph->periph_channel = chan; 897 periph->periph_switch = &atapi_probe_periphsw; 898 periph->periph_target = target; 899 periph->periph_lun = 0; 900 periph->periph_quirks = PQUIRK_ONLYBIG; 901 902 #ifdef SCSIPI_DEBUG 903 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 904 SCSIPI_DEBUG_TARGET == target) 905 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 906 #endif 907 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 908 if (id->atap_config & ATAPI_CFG_REMOV) 909 periph->periph_flags |= PERIPH_REMOVABLE; 910 if (periph->periph_type == T_SEQUENTIAL) { 911 s = splbio(); 912 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 913 splx(s); 914 } 915 916 sa.sa_periph = periph; 917 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 918 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 919 T_REMOV : T_FIXED; 920 strnvisx(model, sizeof(model), id->atap_model, 40, 921 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 922 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 923 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 924 strnvisx(firmware_revision, sizeof(firmware_revision), 925 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 926 sa.sa_inqbuf.vendor = model; 927 sa.sa_inqbuf.product = serial_number; 928 sa.sa_inqbuf.revision = firmware_revision; 929 930 /* 931 * Determine the operating mode capabilities of the device. 932 */ 933 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 934 periph->periph_cap |= PERIPH_CAP_CMD16; 935 /* XXX This is gross. */ 936 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 937 938 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 939 940 if (drvp->drv_softc) 941 ata_probe_caps(drvp); 942 else { 943 s = splbio(); 944 drvp->drive_type = ATA_DRIVET_NONE; 945 splx(s); 946 } 947 } else { 948 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 949 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 950 device_xname(atac->atac_dev), chp->ch_channel, target)); 951 s = splbio(); 952 drvp->drive_type = ATA_DRIVET_NONE; 953 splx(s); 954 } 955 } 956 957 /* 958 * Kill off all pending xfers for a periph. 959 * 960 * Must be called at splbio(). 961 */ 962 static void 963 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 964 { 965 struct atac_softc *atac = 966 device_private(periph->periph_channel->chan_adapter->adapt_dev); 967 struct ata_channel *chp = 968 atac->atac_channels[periph->periph_channel->chan_channel]; 969 970 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 971 } 972 #endif /* NATAPIBUS > 0 */ 973 #endif /* MVSATA_WITHOUTDMA */ 974 975 976 /* 977 * mvsata_setup_channel() 978 * Setup EDMA registers and prepare/purge DMA resources. 979 * We assuming already stopped the EDMA. 980 */ 981 static void 982 mvsata_setup_channel(struct ata_channel *chp) 983 { 984 #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG) 985 struct mvsata_port *mvport = (struct mvsata_port *)chp; 986 #endif 987 struct ata_drive_datas *drvp; 988 uint32_t edma_mode; 989 int drive, s; 990 #ifndef MVSATA_WITHOUTDMA 991 int i; 992 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 993 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 994 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 995 #endif 996 997 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 998 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 999 1000 edma_mode = nodma; 1001 for (drive = 0; drive < chp->ch_ndrives; drive++) { 1002 drvp = &chp->ch_drive[drive]; 1003 1004 /* If no drive, skip */ 1005 if (drvp->drive_type == ATA_DRIVET_NONE) 1006 continue; 1007 1008 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 1009 /* use Ultra/DMA */ 1010 s = splbio(); 1011 drvp->drive_flags &= ~ATA_DRIVE_DMA; 1012 splx(s); 1013 } 1014 1015 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 1016 if (drvp->drive_flags & ATA_DRIVE_NCQ) 1017 edma_mode = ncq; 1018 else if (drvp->drive_type == ATA_DRIVET_ATA) 1019 edma_mode = dma; 1020 } 1021 } 1022 1023 DPRINTF(DEBUG_FUNCS, 1024 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 1025 1026 #ifndef MVSATA_WITHOUTDMA 1027 if (edma_mode == nodma) { 1028 no_edma: 1029 if (mvport->port_crqb != NULL) 1030 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 1031 mvport->port_crqb_dmamap, mvport->port_crqb); 1032 if (mvport->port_crpb != NULL) 1033 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 1034 mvport->port_crpb_dmamap, mvport->port_crpb); 1035 if (mvport->port_eprd != NULL) 1036 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 1037 mvport->port_eprd_dmamap, mvport->port_eprd); 1038 1039 return; 1040 } 1041 1042 if (mvport->port_crqb == NULL) 1043 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 1044 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 1045 if (mvport->port_crpb == NULL) 1046 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 1047 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 1048 if (mvport->port_eprd == NULL) { 1049 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 1050 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 1051 1); 1052 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 1053 mvport->port_reqtbl[i].eprd_offset = 1054 i * MVSATA_EPRD_MAX_SIZE; 1055 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 1056 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 1057 } 1058 } 1059 1060 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 1061 mvport->port_eprd == NULL) { 1062 aprint_error_dev(MVSATA_DEV2(mvport), 1063 "channel %d: can't use EDMA\n", chp->ch_channel); 1064 s = splbio(); 1065 for (drive = 0; drive < chp->ch_ndrives; drive++) { 1066 drvp = &chp->ch_drive[drive]; 1067 1068 /* If no drive, skip */ 1069 if (drvp->drive_type == ATA_DRIVET_NONE) 1070 continue; 1071 1072 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 1073 } 1074 splx(s); 1075 goto no_edma; 1076 } 1077 1078 mvsata_edma_config(mvport, edma_mode); 1079 mvsata_edma_reset_qptr(mvport); 1080 mvsata_edma_enable(mvport); 1081 #endif 1082 } 1083 1084 #ifndef MVSATA_WITHOUTDMA 1085 static int 1086 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1087 { 1088 struct ata_channel *chp = drvp->chnl_softc; 1089 struct atac_softc *atac = chp->ch_atac; 1090 struct ata_bio *ata_bio = &xfer->c_bio; 1091 1092 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1093 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 1094 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 1095 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 1096 1097 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1098 ata_bio->flags |= ATA_POLL; 1099 if (ata_bio->flags & ATA_POLL) 1100 xfer->c_flags |= C_POLL; 1101 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1102 (ata_bio->flags & ATA_SINGLE) == 0) 1103 xfer->c_flags |= C_DMA; 1104 xfer->c_drive = drvp->drive; 1105 xfer->c_databuf = ata_bio->databuf; 1106 xfer->c_bcount = ata_bio->bcount; 1107 xfer->c_start = mvsata_bio_start; 1108 xfer->c_intr = mvsata_bio_intr; 1109 xfer->c_poll = mvsata_bio_poll; 1110 xfer->c_abort = mvsata_bio_done; 1111 xfer->c_kill_xfer = mvsata_bio_kill_xfer; 1112 ata_exec_xfer(chp, xfer); 1113 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1114 } 1115 1116 static int 1117 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1118 { 1119 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1120 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1121 struct atac_softc *atac = chp->ch_atac; 1122 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1123 struct ata_bio *ata_bio = &xfer->c_bio; 1124 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1125 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1126 u_int16_t cyl; 1127 u_int8_t head, sect, cmd = 0; 1128 int nblks, error, tfd; 1129 1130 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1131 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1132 1133 ata_channel_lock_owned(chp); 1134 1135 mvsata_quetag_get(mvport, xfer->c_slot); 1136 1137 if (xfer->c_flags & C_DMA) 1138 if (drvp->n_xfers <= NXFER) 1139 drvp->n_xfers++; 1140 1141 /* 1142 * 1143 * When starting a multi-sector transfer, or doing single-sector 1144 * transfers... 1145 */ 1146 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1147 if (ata_bio->flags & ATA_SINGLE) 1148 nblks = 1; 1149 else 1150 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1151 /* Check for bad sectors and adjust transfer, if necessary. */ 1152 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1153 long blkdiff; 1154 int i; 1155 1156 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1157 i++) { 1158 blkdiff -= ata_bio->blkno; 1159 if (blkdiff < 0) 1160 continue; 1161 if (blkdiff == 0) 1162 /* Replace current block of transfer. */ 1163 ata_bio->blkno = 1164 drvp->lp->d_secperunit - 1165 drvp->lp->d_nsectors - i - 1; 1166 if (blkdiff < nblks) { 1167 /* Bad block inside transfer. */ 1168 ata_bio->flags |= ATA_SINGLE; 1169 nblks = 1; 1170 } 1171 break; 1172 } 1173 /* Transfer is okay now. */ 1174 } 1175 if (xfer->c_flags & C_DMA) { 1176 enum mvsata_edmamode dmamode; 1177 1178 ata_bio->nblks = nblks; 1179 ata_bio->nbytes = xfer->c_bcount; 1180 1181 /* switch to appropriate dma mode if necessary */ 1182 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1183 if (mvport->port_edmamode_curr != dmamode) 1184 mvsata_edma_config(mvport, dmamode); 1185 1186 if (xfer->c_flags & C_POLL) 1187 sc->sc_enable_intr(mvport, 0 /*off*/); 1188 error = mvsata_edma_enqueue(mvport, xfer); 1189 if (error) { 1190 if (error == EINVAL) { 1191 /* 1192 * We can't do DMA on this transfer 1193 * for some reason. Fall back to 1194 * PIO. 1195 */ 1196 xfer->c_flags &= ~C_DMA; 1197 error = 0; 1198 goto do_pio; 1199 } 1200 if (error == EBUSY) { 1201 aprint_error_dev(atac->atac_dev, 1202 "channel %d: EDMA Queue full\n", 1203 chp->ch_channel); 1204 /* 1205 * XXX: Perhaps, after it waits for 1206 * a while, it is necessary to call 1207 * bio_start again. 1208 */ 1209 } 1210 ata_bio->error = ERR_DMA; 1211 ata_bio->r_error = 0; 1212 return ATASTART_ABORT; 1213 } 1214 chp->ch_flags |= ATACH_DMA_WAIT; 1215 /* start timeout machinery */ 1216 if ((xfer->c_flags & C_POLL) == 0) 1217 callout_reset(&xfer->c_timo_callout, 1218 mstohz(ATA_DELAY), 1219 mvsata_edma_timeout, xfer); 1220 /* wait for irq */ 1221 goto intr; 1222 } /* else not DMA */ 1223 do_pio: 1224 if (ata_bio->flags & ATA_LBA48) { 1225 sect = 0; 1226 cyl = 0; 1227 head = 0; 1228 } else if (ata_bio->flags & ATA_LBA) { 1229 sect = (ata_bio->blkno >> 0) & 0xff; 1230 cyl = (ata_bio->blkno >> 8) & 0xffff; 1231 head = (ata_bio->blkno >> 24) & 0x0f; 1232 head |= WDSD_LBA; 1233 } else { 1234 int blkno = ata_bio->blkno; 1235 sect = blkno % drvp->lp->d_nsectors; 1236 sect++; /* Sectors begin with 1, not 0. */ 1237 blkno /= drvp->lp->d_nsectors; 1238 head = blkno % drvp->lp->d_ntracks; 1239 blkno /= drvp->lp->d_ntracks; 1240 cyl = blkno; 1241 head |= WDSD_CHS; 1242 } 1243 ata_bio->nblks = min(nblks, drvp->multi); 1244 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1245 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1246 if (ata_bio->nblks > 1) 1247 cmd = (ata_bio->flags & ATA_READ) ? 1248 WDCC_READMULTI : WDCC_WRITEMULTI; 1249 else 1250 cmd = (ata_bio->flags & ATA_READ) ? 1251 WDCC_READ : WDCC_WRITE; 1252 1253 /* EDMA disable, if enabled this channel. */ 1254 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1255 if (mvport->port_edmamode_curr != nodma) 1256 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1257 1258 mvsata_pmp_select(mvport, xfer->c_drive); 1259 1260 /* Do control operations specially. */ 1261 if (__predict_false(drvp->state < READY)) { 1262 /* 1263 * Actually, we want to be careful not to mess with 1264 * the control state if the device is currently busy, 1265 * but we can assume that we never get to this point 1266 * if that's the case. 1267 */ 1268 /* 1269 * If it's not a polled command, we need the kernel 1270 * thread 1271 */ 1272 if ((xfer->c_flags & C_POLL) == 0 && 1273 (chp->ch_flags & ATACH_TH_RUN) == 0) { 1274 return ATASTART_TH; 1275 } 1276 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1277 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1278 return ATASTART_ABORT; 1279 } 1280 } 1281 1282 /* Initiate command! */ 1283 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1284 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1285 case WDCWAIT_OK: 1286 break; 1287 case WDCWAIT_TOUT: 1288 goto timeout; 1289 case WDCWAIT_THR: 1290 return ATASTART_TH; 1291 } 1292 if (ata_bio->flags & ATA_LBA48) 1293 wdccommandext(chp, 0, atacmd_to48(cmd), 1294 ata_bio->blkno, nblks, 0, WDSD_LBA); 1295 else 1296 wdccommand(chp, 0, cmd, cyl, 1297 head, sect, nblks, 1298 (drvp->lp->d_type == DKTYPE_ST506) ? 1299 drvp->lp->d_precompcyl / 4 : 0); 1300 1301 /* start timeout machinery */ 1302 if ((xfer->c_flags & C_POLL) == 0) 1303 callout_reset(&xfer->c_timo_callout, 1304 mstohz(ATA_DELAY), wdctimeout, xfer); 1305 } else if (ata_bio->nblks > 1) { 1306 /* The number of blocks in the last stretch may be smaller. */ 1307 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1308 if (ata_bio->nblks > nblks) { 1309 ata_bio->nblks = nblks; 1310 ata_bio->nbytes = xfer->c_bcount; 1311 } 1312 } 1313 /* If this was a write and not using DMA, push the data. */ 1314 if ((ata_bio->flags & ATA_READ) == 0) { 1315 /* 1316 * we have to busy-wait here, we can't rely on running in 1317 * thread context. 1318 */ 1319 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1320 aprint_error_dev(atac->atac_dev, 1321 "channel %d: drive %d timeout waiting for DRQ," 1322 " st=0x%02x, err=0x%02x\n", 1323 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1324 ATACH_ERR(tfd)); 1325 ata_bio->error = TIMEOUT; 1326 return ATASTART_ABORT; 1327 } 1328 if (ATACH_ST(tfd) & WDCS_ERR) { 1329 ata_bio->error = ERROR; 1330 ata_bio->r_error = ATACH_ERR(tfd); 1331 mvsata_bio_done(chp, xfer); 1332 return ATASTART_ABORT; 1333 } 1334 1335 wdc->dataout_pio(chp, drvp->drive_flags, 1336 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1337 } 1338 1339 intr: 1340 /* Wait for IRQ (either real or polled) */ 1341 if ((ata_bio->flags & ATA_POLL) != 0) 1342 return ATASTART_POLL; 1343 else 1344 return ATASTART_STARTED; 1345 1346 timeout: 1347 aprint_error_dev(atac->atac_dev, 1348 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1349 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1350 ata_bio->error = TIMEOUT; 1351 return ATASTART_ABORT; 1352 } 1353 1354 static void 1355 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1356 { 1357 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1358 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1359 1360 /* Wait for at last 400ns for status bit to be valid */ 1361 delay(1); 1362 if (chp->ch_flags & ATACH_DMA_WAIT) { 1363 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1364 sc->sc_enable_intr(mvport, 1 /*on*/); 1365 chp->ch_flags &= ~ATACH_DMA_WAIT; 1366 } 1367 1368 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) 1369 mvsata_bio_intr(chp, xfer, 0); 1370 } 1371 1372 static int 1373 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1374 { 1375 struct atac_softc *atac = chp->ch_atac; 1376 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1377 struct ata_bio *ata_bio = &xfer->c_bio; 1378 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1379 int tfd; 1380 1381 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1382 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1383 xfer->c_drive)); 1384 1385 ata_channel_lock(chp); 1386 1387 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1388 1389 /* 1390 * If we missed an interrupt transfer, reset and restart. 1391 * Don't try to continue transfer, we may have missed cycles. 1392 */ 1393 if (xfer->c_flags & C_TIMEOU) { 1394 ata_bio->error = TIMEOUT; 1395 ata_channel_unlock(chp); 1396 mvsata_bio_done(chp, xfer); 1397 return 1; 1398 } 1399 1400 /* Is it not a transfer, but a control operation? */ 1401 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1402 aprint_error_dev(atac->atac_dev, 1403 "channel %d: drive %d bad state %d in %s\n", 1404 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1405 panic("%s: bad state", __func__); 1406 } 1407 1408 /* Ack interrupt done by wdc_wait_for_unbusy */ 1409 if (!(xfer->c_flags & C_DMA) && 1410 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1411 == WDCWAIT_TOUT)) { 1412 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1413 ata_channel_unlock(chp); 1414 return 0; /* IRQ was not for us */ 1415 } 1416 aprint_error_dev(atac->atac_dev, 1417 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1418 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1419 xfer->c_skip); 1420 ata_bio->error = TIMEOUT; 1421 ata_channel_unlock(chp); 1422 mvsata_bio_done(chp, xfer); 1423 return 1; 1424 } 1425 1426 if (xfer->c_flags & C_DMA) { 1427 if (ata_bio->error == NOERROR) 1428 goto end; 1429 if (ata_bio->error == ERR_DMA) { 1430 ata_channel_unlock(chp); 1431 ata_dmaerr(drvp, 1432 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1433 goto err; 1434 } 1435 } 1436 1437 /* if we had an error, end */ 1438 if (ata_bio->error != NOERROR) { 1439 ata_channel_unlock(chp); 1440 err: 1441 mvsata_bio_done(chp, xfer); 1442 return 1; 1443 } 1444 1445 /* If this was a read and not using DMA, fetch the data. */ 1446 if ((ata_bio->flags & ATA_READ) != 0) { 1447 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1448 aprint_error_dev(atac->atac_dev, 1449 "channel %d: drive %d read intr before drq\n", 1450 chp->ch_channel, xfer->c_drive); 1451 ata_bio->error = TIMEOUT; 1452 ata_channel_unlock(chp); 1453 mvsata_bio_done(chp, xfer); 1454 return 1; 1455 } 1456 wdc->datain_pio(chp, drvp->drive_flags, 1457 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1458 } 1459 1460 end: 1461 ata_bio->blkno += ata_bio->nblks; 1462 ata_bio->blkdone += ata_bio->nblks; 1463 xfer->c_skip += ata_bio->nbytes; 1464 xfer->c_bcount -= ata_bio->nbytes; 1465 1466 /* See if this transfer is complete. */ 1467 if (xfer->c_bcount > 0) { 1468 if ((ata_bio->flags & ATA_POLL) == 0) { 1469 /* Start the next operation */ 1470 ata_xfer_start(xfer); 1471 } else { 1472 /* Let mvsata_bio_start do the loop */ 1473 } 1474 ata_channel_unlock(chp); 1475 } else { /* Done with this transfer */ 1476 ata_bio->error = NOERROR; 1477 ata_channel_unlock(chp); 1478 mvsata_bio_done(chp, xfer); 1479 } 1480 return 1; 1481 } 1482 1483 static void 1484 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1485 { 1486 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1487 struct atac_softc *atac = chp->ch_atac; 1488 struct ata_bio *ata_bio = &xfer->c_bio; 1489 int drive = xfer->c_drive; 1490 bool deactivate = true; 1491 1492 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1493 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1494 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1495 1496 /* EDMA restart, if enabled */ 1497 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1498 mvsata_edma_reset_qptr(mvport); 1499 mvsata_edma_enable(mvport); 1500 } 1501 1502 ata_bio->flags |= ATA_ITSDONE; 1503 switch (reason) { 1504 case KILL_GONE_INACTIVE: 1505 deactivate = false; 1506 /* FALLTHROUGH */ 1507 case KILL_GONE: 1508 ata_bio->error = ERR_NODEV; 1509 break; 1510 case KILL_RESET: 1511 ata_bio->error = ERR_RESET; 1512 break; 1513 case KILL_REQUEUE: 1514 ata_bio->error = REQUEUE; 1515 break; 1516 default: 1517 aprint_error_dev(atac->atac_dev, 1518 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1519 panic("mvsata_bio_kill_xfer"); 1520 } 1521 ata_bio->r_error = WDCE_ABRT; 1522 1523 if (deactivate) { 1524 mvsata_quetag_put(mvport, xfer->c_slot); 1525 ata_deactivate_xfer(chp, xfer); 1526 } 1527 1528 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1529 } 1530 1531 static void 1532 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1533 { 1534 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1535 struct ata_bio *ata_bio = &xfer->c_bio; 1536 int drive = xfer->c_drive; 1537 bool iserror = (ata_bio->error != NOERROR); 1538 1539 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1540 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1541 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1542 (u_int)xfer->c_flags)); 1543 1544 /* EDMA restart, if enabled */ 1545 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1546 mvsata_edma_reset_qptr(mvport); 1547 mvsata_edma_enable(mvport); 1548 } 1549 1550 if (ata_waitdrain_xfer_check(chp, xfer)) 1551 return; 1552 1553 /* feed back residual bcount to our caller */ 1554 ata_bio->bcount = xfer->c_bcount; 1555 1556 /* mark controller inactive and free xfer */ 1557 mvsata_quetag_put(mvport, xfer->c_slot); 1558 ata_deactivate_xfer(chp, xfer); 1559 1560 ata_bio->flags |= ATA_ITSDONE; 1561 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1562 if (!iserror) 1563 atastart(chp); 1564 } 1565 1566 static int 1567 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1568 int flags) 1569 { 1570 struct ata_channel *chp = &mvport->port_ata_channel; 1571 struct atac_softc *atac = chp->ch_atac; 1572 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1573 const char *errstring; 1574 int tfd; 1575 1576 flags |= AT_POLL; /* XXX */ 1577 1578 ata_channel_lock_owned(chp); 1579 1580 /* 1581 * disable interrupts, all commands here should be quick 1582 * enough to be able to poll, and we don't go here that often 1583 */ 1584 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1585 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1586 DELAY(10); 1587 errstring = "wait"; 1588 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1589 goto ctrltimeout; 1590 wdccommandshort(chp, 0, WDCC_RECAL); 1591 /* Wait for at least 400ns for status bit to be valid */ 1592 DELAY(1); 1593 errstring = "recal"; 1594 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1595 goto ctrltimeout; 1596 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1597 goto ctrlerror; 1598 /* Don't try to set modes if controller can't be adjusted */ 1599 if (atac->atac_set_modes == NULL) 1600 goto geometry; 1601 /* Also don't try if the drive didn't report its mode */ 1602 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1603 goto geometry; 1604 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1605 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1606 errstring = "piomode-bio"; 1607 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1608 goto ctrltimeout; 1609 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1610 goto ctrlerror; 1611 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1612 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1613 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1614 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1615 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1616 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1617 else 1618 goto geometry; 1619 errstring = "dmamode-bio"; 1620 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1621 goto ctrltimeout; 1622 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1623 goto ctrlerror; 1624 geometry: 1625 if (ata_bio->flags & ATA_LBA) 1626 goto multimode; 1627 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1628 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1629 (drvp->lp->d_type == DKTYPE_ST506) ? 1630 drvp->lp->d_precompcyl / 4 : 0); 1631 errstring = "geometry"; 1632 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1633 goto ctrltimeout; 1634 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1635 goto ctrlerror; 1636 multimode: 1637 if (drvp->multi == 1) 1638 goto ready; 1639 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1640 errstring = "setmulti"; 1641 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1642 goto ctrltimeout; 1643 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1644 goto ctrlerror; 1645 ready: 1646 drvp->state = READY; 1647 /* 1648 * The drive is usable now 1649 */ 1650 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1651 delay(10); /* some drives need a little delay here */ 1652 return 0; 1653 1654 ctrltimeout: 1655 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1656 chp->ch_channel, drive, errstring); 1657 ata_bio->error = TIMEOUT; 1658 goto ctrldone; 1659 ctrlerror: 1660 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1661 chp->ch_channel, drive, errstring); 1662 if (ATACH_ST(tfd) & WDCS_DWF) { 1663 aprint_error("drive fault\n"); 1664 ata_bio->error = ERR_DF; 1665 } else { 1666 ata_bio->r_error = ATACH_ERR(tfd); 1667 ata_bio->error = ERROR; 1668 aprint_error("error (%x)\n", ata_bio->r_error); 1669 } 1670 ctrldone: 1671 drvp->state = 0; 1672 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1673 return -1; 1674 } 1675 1676 static int 1677 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1678 { 1679 struct ata_channel *chp = drvp->chnl_softc; 1680 struct ata_command *ata_c = &xfer->c_ata_c; 1681 int rv, s; 1682 1683 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1684 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1685 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1686 " r_device=0x%02x, r_command=0x%02x\n", 1687 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1688 chp->ch_channel, 1689 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1690 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1691 1692 if (ata_c->flags & AT_POLL) 1693 xfer->c_flags |= C_POLL; 1694 if (ata_c->flags & AT_WAIT) 1695 xfer->c_flags |= C_WAIT; 1696 xfer->c_drive = drvp->drive; 1697 xfer->c_databuf = ata_c->data; 1698 xfer->c_bcount = ata_c->bcount; 1699 xfer->c_start = mvsata_wdc_cmd_start; 1700 xfer->c_intr = mvsata_wdc_cmd_intr; 1701 xfer->c_poll = mvsata_wdc_cmd_poll; 1702 xfer->c_abort = mvsata_wdc_cmd_done; 1703 xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer; 1704 s = splbio(); 1705 ata_exec_xfer(chp, xfer); 1706 #ifdef DIAGNOSTIC 1707 if ((ata_c->flags & AT_POLL) != 0 && 1708 (ata_c->flags & AT_DONE) == 0) 1709 panic("mvsata_exec_command: polled command not done"); 1710 #endif 1711 if (ata_c->flags & AT_DONE) 1712 rv = ATACMD_COMPLETE; 1713 else { 1714 if (ata_c->flags & AT_WAIT) { 1715 ata_channel_lock(chp); 1716 if ((ata_c->flags & AT_DONE) == 0) { 1717 ata_wait_xfer(chp, xfer); 1718 KASSERT((ata_c->flags & AT_DONE) != 0); 1719 } 1720 ata_channel_unlock(chp); 1721 rv = ATACMD_COMPLETE; 1722 } else 1723 rv = ATACMD_QUEUED; 1724 } 1725 splx(s); 1726 return rv; 1727 } 1728 1729 static int 1730 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1731 { 1732 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1733 int drive = xfer->c_drive; 1734 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1735 struct ata_command *ata_c = &xfer->c_ata_c; 1736 int tfd; 1737 1738 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1739 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1740 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1741 1742 ata_channel_lock_owned(chp); 1743 1744 mvsata_quetag_get(mvport, xfer->c_slot); 1745 1746 /* First, EDMA disable, if enabled this channel. */ 1747 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1748 if (mvport->port_edmamode_curr != nodma) 1749 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1750 1751 mvsata_pmp_select(mvport, drive); 1752 1753 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1754 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1755 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1756 case WDCWAIT_OK: 1757 break; 1758 case WDCWAIT_TOUT: 1759 ata_c->flags |= AT_TIMEOU; 1760 return ATASTART_ABORT; 1761 case WDCWAIT_THR: 1762 return ATASTART_TH; 1763 } 1764 if (ata_c->flags & AT_POLL) 1765 /* polled command, disable interrupts */ 1766 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1767 if ((ata_c->flags & AT_LBA48) != 0) { 1768 wdccommandext(chp, 0, ata_c->r_command, 1769 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1770 ata_c->r_device & ~0x10); 1771 } else { 1772 wdccommand(chp, 0, ata_c->r_command, 1773 (ata_c->r_lba >> 8) & 0xffff, 1774 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1775 ((ata_c->r_lba >> 24) & 0x0f), 1776 ata_c->r_lba & 0xff, 1777 ata_c->r_count & 0xff, 1778 ata_c->r_features & 0xff); 1779 } 1780 1781 if ((ata_c->flags & AT_POLL) == 0) { 1782 callout_reset(&xfer->c_timo_callout, ata_c->timeout / 1000 * hz, 1783 wdctimeout, xfer); 1784 return ATASTART_STARTED; 1785 } 1786 1787 return ATASTART_POLL; 1788 } 1789 1790 static void 1791 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1792 { 1793 /* 1794 * Polled command. Wait for drive ready or drq. Done in intr(). 1795 * Wait for at last 400ns for status bit to be valid. 1796 */ 1797 delay(10); /* 400ns delay */ 1798 mvsata_wdc_cmd_intr(chp, xfer, 0); 1799 } 1800 1801 static int 1802 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1803 { 1804 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1805 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1806 struct ata_command *ata_c = &xfer->c_ata_c; 1807 int bcount = ata_c->bcount; 1808 char *data = ata_c->data; 1809 int wflags; 1810 int drive_flags; 1811 int tfd; 1812 1813 ata_channel_lock(chp); 1814 1815 if (ata_c->r_command == WDCC_IDENTIFY || 1816 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1817 /* 1818 * The IDENTIFY data has been designed as an array of 1819 * u_int16_t, so we can byteswap it on the fly. 1820 * Historically it's what we have always done so keeping it 1821 * here ensure binary backward compatibility. 1822 */ 1823 drive_flags = ATA_DRIVE_NOSTREAM | 1824 chp->ch_drive[xfer->c_drive].drive_flags; 1825 else 1826 /* 1827 * Other data structure are opaque and should be transfered 1828 * as is. 1829 */ 1830 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1831 1832 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1833 /* both wait and poll, we can kpause here */ 1834 wflags = AT_WAIT | AT_POLL; 1835 else 1836 wflags = AT_POLL; 1837 1838 again: 1839 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1840 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1841 __func__, xfer->c_drive)); 1842 1843 /* 1844 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1845 * Reselect again, it doesn't hurt for others commands, and the time 1846 * penalty for the extra register write is acceptable, 1847 * wdc_exec_command() isn't called often (mostly for autoconfig) 1848 */ 1849 if ((xfer->c_flags & C_ATAPI) != 0) { 1850 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1851 } 1852 if ((ata_c->flags & AT_XFDONE) != 0) { 1853 /* 1854 * We have completed a data xfer. The drive should now be 1855 * in its initial state 1856 */ 1857 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1858 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1859 wflags, &tfd) == WDCWAIT_TOUT) { 1860 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1861 ata_channel_unlock(chp); 1862 return 0; /* IRQ was not for us */ 1863 } 1864 ata_c->flags |= AT_TIMEOU; 1865 } 1866 goto out; 1867 } 1868 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1869 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1870 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1871 ata_channel_unlock(chp); 1872 return 0; /* IRQ was not for us */ 1873 } 1874 ata_c->flags |= AT_TIMEOU; 1875 goto out; 1876 } 1877 delay(20); /* XXXXX: Delay more times. */ 1878 if (ata_c->flags & AT_READ) { 1879 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1880 ata_c->flags |= AT_TIMEOU; 1881 goto out; 1882 } 1883 wdc->datain_pio(chp, drive_flags, data, bcount); 1884 /* at this point the drive should be in its initial state */ 1885 ata_c->flags |= AT_XFDONE; 1886 /* 1887 * XXX checking the status register again here cause some 1888 * hardware to timeout. 1889 */ 1890 } else if (ata_c->flags & AT_WRITE) { 1891 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1892 ata_c->flags |= AT_TIMEOU; 1893 goto out; 1894 } 1895 wdc->dataout_pio(chp, drive_flags, data, bcount); 1896 ata_c->flags |= AT_XFDONE; 1897 if ((ata_c->flags & AT_POLL) == 0) { 1898 callout_reset(&xfer->c_timo_callout, 1899 mstohz(ata_c->timeout), wdctimeout, xfer); 1900 ata_channel_unlock(chp); 1901 return 1; 1902 } else 1903 goto again; 1904 } 1905 out: 1906 if (ATACH_ST(tfd) & WDCS_DWF) 1907 ata_c->flags |= AT_DF; 1908 if (ATACH_ST(tfd) & WDCS_ERR) { 1909 ata_c->flags |= AT_ERROR; 1910 ata_c->r_error = ATACH_ERR(tfd); 1911 } 1912 ata_channel_unlock(chp); 1913 mvsata_wdc_cmd_done(chp, xfer); 1914 1915 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1916 atastart(chp); 1917 1918 return 1; 1919 } 1920 1921 static void 1922 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1923 int reason) 1924 { 1925 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1926 struct ata_command *ata_c = &xfer->c_ata_c; 1927 bool deactivate = true; 1928 1929 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1930 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1931 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1932 1933 switch (reason) { 1934 case KILL_GONE_INACTIVE: 1935 deactivate = false; 1936 /* FALLTHROUGH */ 1937 case KILL_GONE: 1938 ata_c->flags |= AT_GONE; 1939 break; 1940 case KILL_RESET: 1941 ata_c->flags |= AT_RESET; 1942 break; 1943 case KILL_REQUEUE: 1944 panic("%s: not supposed to be requeued\n", __func__); 1945 break; 1946 default: 1947 aprint_error_dev(MVSATA_DEV2(mvport), 1948 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1949 panic("mvsata_cmd_kill_xfer"); 1950 } 1951 1952 if (deactivate) { 1953 mvsata_quetag_put(mvport, xfer->c_slot); 1954 ata_deactivate_xfer(chp, xfer); 1955 } 1956 1957 mvsata_wdc_cmd_done_end(chp, xfer); 1958 } 1959 1960 static void 1961 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1962 { 1963 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1964 struct atac_softc *atac = chp->ch_atac; 1965 struct ata_command *ata_c = &xfer->c_ata_c; 1966 1967 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1968 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1969 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1970 ata_c->flags)); 1971 1972 if (ata_waitdrain_xfer_check(chp, xfer)) 1973 return; 1974 1975 if ((ata_c->flags & AT_READREG) != 0 && 1976 device_is_active(atac->atac_dev) && 1977 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1978 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1979 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1980 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1981 ata_c->r_lba = 1982 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1983 ata_c->r_lba |= 1984 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1985 ata_c->r_lba |= 1986 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1987 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1988 if ((ata_c->flags & AT_LBA48) != 0) { 1989 if ((ata_c->flags & AT_POLL) != 0) { 1990 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1991 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1992 } else { 1993 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1994 WDCTL_HOB|WDCTL_4BIT); 1995 } 1996 ata_c->r_count |= 1997 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1998 ata_c->r_lba |= 1999 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 2000 ata_c->r_lba |= 2001 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 2002 ata_c->r_lba |= 2003 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 2004 if ((ata_c->flags & AT_POLL) != 0) { 2005 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 2006 WDCTL_4BIT|WDCTL_IDS); 2007 } else { 2008 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 2009 WDCTL_4BIT); 2010 } 2011 } else { 2012 ata_c->r_lba |= 2013 (uint64_t)(ata_c->r_device & 0x0f) << 24; 2014 } 2015 } 2016 2017 mvsata_quetag_put(mvport, xfer->c_slot); 2018 ata_deactivate_xfer(chp, xfer); 2019 2020 if (ata_c->flags & AT_POLL) { 2021 /* enable interrupts */ 2022 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2023 delay(10); /* some drives need a little delay here */ 2024 } 2025 2026 mvsata_wdc_cmd_done_end(chp, xfer); 2027 } 2028 2029 static void 2030 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 2031 { 2032 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2033 struct ata_command *ata_c = &xfer->c_ata_c; 2034 2035 /* EDMA restart, if enabled */ 2036 if (mvport->port_edmamode_curr != nodma) { 2037 mvsata_edma_reset_qptr(mvport); 2038 mvsata_edma_enable(mvport); 2039 } 2040 2041 ata_channel_lock(chp); 2042 ata_c->flags |= AT_DONE; 2043 if (ata_c->flags & AT_WAIT) 2044 ata_wake_xfer(chp, xfer); 2045 ata_channel_unlock(chp); 2046 } 2047 2048 #if NATAPIBUS > 0 2049 static void 2050 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 2051 scsipi_adapter_req_t req, void *arg) 2052 { 2053 struct scsipi_adapter *adapt = chan->chan_adapter; 2054 struct scsipi_periph *periph; 2055 struct scsipi_xfer *sc_xfer; 2056 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 2057 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2058 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 2059 struct ata_xfer *xfer; 2060 int drive, s; 2061 2062 switch (req) { 2063 case ADAPTER_REQ_RUN_XFER: 2064 sc_xfer = arg; 2065 periph = sc_xfer->xs_periph; 2066 drive = periph->periph_target; 2067 2068 if (!device_is_active(atac->atac_dev)) { 2069 sc_xfer->error = XS_DRIVER_STUFFUP; 2070 scsipi_done(sc_xfer); 2071 return; 2072 } 2073 xfer = ata_get_xfer_ext(chp, false, 0); 2074 if (xfer == NULL) { 2075 sc_xfer->error = XS_RESOURCE_SHORTAGE; 2076 scsipi_done(sc_xfer); 2077 return; 2078 } 2079 2080 if (sc_xfer->xs_control & XS_CTL_POLL) 2081 xfer->c_flags |= C_POLL; 2082 xfer->c_drive = drive; 2083 xfer->c_flags |= C_ATAPI; 2084 xfer->c_scsipi = sc_xfer; 2085 xfer->c_databuf = sc_xfer->data; 2086 xfer->c_bcount = sc_xfer->datalen; 2087 xfer->c_start = mvsata_atapi_start; 2088 xfer->c_intr = mvsata_atapi_intr; 2089 xfer->c_poll = mvsata_atapi_poll; 2090 xfer->c_abort = mvsata_atapi_reset; 2091 xfer->c_kill_xfer = mvsata_atapi_kill_xfer; 2092 xfer->c_dscpoll = 0; 2093 s = splbio(); 2094 ata_exec_xfer(chp, xfer); 2095 #ifdef DIAGNOSTIC 2096 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 2097 (sc_xfer->xs_status & XS_STS_DONE) == 0) 2098 panic("mvsata_atapi_scsipi_request:" 2099 " polled command not done"); 2100 #endif 2101 splx(s); 2102 return; 2103 2104 default: 2105 /* Not supported, nothing to do. */ 2106 ; 2107 } 2108 } 2109 2110 static int 2111 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2112 { 2113 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2114 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2115 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2116 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2117 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2118 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2119 const char *errstring; 2120 int tfd; 2121 2122 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2123 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2124 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2125 xfer->c_drive, sc_xfer->xs_control)); 2126 2127 ata_channel_lock_owned(chp); 2128 2129 mvsata_quetag_get(mvport, xfer->c_slot); 2130 2131 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2132 if (mvport->port_edmamode_curr != nodma) 2133 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2134 2135 mvsata_pmp_select(mvport, xfer->c_drive); 2136 2137 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2138 drvp->n_xfers++; 2139 2140 /* Do control operations specially. */ 2141 if (__predict_false(drvp->state < READY)) { 2142 /* If it's not a polled command, we need the kernel thread */ 2143 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && 2144 (chp->ch_flags & ATACH_TH_RUN) == 0) { 2145 return ATASTART_TH; 2146 } 2147 /* 2148 * disable interrupts, all commands here should be quick 2149 * enough to be able to poll, and we don't go here that often 2150 */ 2151 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2152 2153 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2154 /* Don't try to set mode if controller can't be adjusted */ 2155 if (atac->atac_set_modes == NULL) 2156 goto ready; 2157 /* Also don't try if the drive didn't report its mode */ 2158 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2159 goto ready; 2160 errstring = "unbusy"; 2161 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2162 goto timeout; 2163 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2164 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2165 errstring = "piomode-atapi"; 2166 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2167 &tfd)) 2168 goto timeout; 2169 if (ATACH_ST(tfd) & WDCS_ERR) { 2170 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2171 /* 2172 * Some ATAPI drives reject PIO settings. 2173 * Fall back to PIO mode 3 since that's the 2174 * minimum for ATAPI. 2175 */ 2176 aprint_error_dev(atac->atac_dev, 2177 "channel %d drive %d: PIO mode %d rejected," 2178 " falling back to PIO mode 3\n", 2179 chp->ch_channel, xfer->c_drive, 2180 drvp->PIO_mode); 2181 if (drvp->PIO_mode > 3) 2182 drvp->PIO_mode = 3; 2183 } else 2184 goto error; 2185 } 2186 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2187 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2188 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2189 else 2190 if (drvp->drive_flags & ATA_DRIVE_DMA) 2191 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2192 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2193 else 2194 goto ready; 2195 errstring = "dmamode-atapi"; 2196 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2197 &tfd)) 2198 goto timeout; 2199 if (ATACH_ST(tfd) & WDCS_ERR) { 2200 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2201 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2202 goto error; 2203 else { 2204 /* 2205 * The drive rejected our DMA setting. 2206 * Fall back to mode 1. 2207 */ 2208 aprint_error_dev(atac->atac_dev, 2209 "channel %d drive %d:" 2210 " DMA mode %d rejected," 2211 " falling back to DMA mode 0\n", 2212 chp->ch_channel, xfer->c_drive, 2213 drvp->DMA_mode); 2214 if (drvp->DMA_mode > 0) 2215 drvp->DMA_mode = 0; 2216 } 2217 } else 2218 goto error; 2219 } 2220 ready: 2221 drvp->state = READY; 2222 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2223 delay(10); /* some drives need a little delay here */ 2224 } 2225 /* start timeout machinery */ 2226 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2227 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 2228 wdctimeout, xfer); 2229 2230 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2231 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2232 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2233 ATACH_ST(tfd)); 2234 sc_xfer->error = XS_TIMEOUT; 2235 return ATASTART_ABORT; 2236 } 2237 2238 /* 2239 * Even with WDCS_ERR, the device should accept a command packet 2240 * Limit length to what can be stuffed into the cylinder register 2241 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2242 * but not all devices do that and it's not obvious from the 2243 * ATAPI spec that that behaviour should be expected. If more 2244 * data is necessary, multiple data transfer phases will be done. 2245 */ 2246 2247 wdccommand(chp, 0, ATAPI_PKT_CMD, 2248 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2249 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2250 2251 /* 2252 * If there is no interrupt for CMD input, busy-wait for it (done in 2253 * the interrupt routine. Poll routine will exit early in this case. 2254 */ 2255 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2256 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2257 return ATASTART_POLL; 2258 else 2259 return ATASTART_STARTED; 2260 2261 timeout: 2262 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2263 chp->ch_channel, xfer->c_drive, errstring); 2264 sc_xfer->error = XS_TIMEOUT; 2265 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2266 delay(10); /* some drives need a little delay here */ 2267 return ATASTART_ABORT; 2268 2269 error: 2270 aprint_error_dev(atac->atac_dev, 2271 "channel %d drive %d: %s error (0x%x)\n", 2272 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2273 sc_xfer->error = XS_SHORTSENSE; 2274 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2275 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2276 delay(10); /* some drives need a little delay here */ 2277 return ATASTART_ABORT; 2278 } 2279 2280 static void 2281 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2282 { 2283 /* 2284 * If there is no interrupt for CMD input, busy-wait for it (done in 2285 * the interrupt routine. If it is a polled command, call the interrupt 2286 * routine until command is done. 2287 */ 2288 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2289 2290 /* Wait for at last 400ns for status bit to be valid */ 2291 DELAY(1); 2292 mvsata_atapi_intr(chp, xfer, 0); 2293 2294 if (!poll) 2295 return; 2296 2297 if (chp->ch_flags & ATACH_DMA_WAIT) { 2298 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2299 chp->ch_flags &= ~ATACH_DMA_WAIT; 2300 } 2301 2302 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2303 /* Wait for at last 400ns for status bit to be valid */ 2304 DELAY(1); 2305 mvsata_atapi_intr(chp, xfer, 0); 2306 } 2307 } 2308 2309 static int 2310 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2311 { 2312 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2313 struct atac_softc *atac = chp->ch_atac; 2314 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2315 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2316 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2317 int len, phase, ire, error, retries=0, i; 2318 int tfd; 2319 void *cmd; 2320 2321 ata_channel_lock(chp); 2322 2323 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2324 ("%s:%d:%d: mvsata_atapi_intr\n", 2325 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2326 2327 /* Is it not a transfer, but a control operation? */ 2328 if (drvp->state < READY) { 2329 aprint_error_dev(atac->atac_dev, 2330 "channel %d drive %d: bad state %d\n", 2331 chp->ch_channel, xfer->c_drive, drvp->state); 2332 panic("mvsata_atapi_intr: bad state"); 2333 } 2334 /* 2335 * If we missed an interrupt in a PIO transfer, reset and restart. 2336 * Don't try to continue transfer, we may have missed cycles. 2337 */ 2338 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2339 ata_channel_unlock(chp); 2340 sc_xfer->error = XS_TIMEOUT; 2341 mvsata_atapi_reset(chp, xfer); 2342 return 1; 2343 } 2344 2345 /* Ack interrupt done in wdc_wait_for_unbusy */ 2346 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2347 if (wdc_wait_for_unbusy(chp, 2348 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2349 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2350 ata_channel_unlock(chp); 2351 return 0; /* IRQ was not for us */ 2352 } 2353 aprint_error_dev(atac->atac_dev, 2354 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2355 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2356 ata_channel_unlock(chp); 2357 if (xfer->c_flags & C_DMA) 2358 ata_dmaerr(drvp, 2359 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2360 sc_xfer->error = XS_TIMEOUT; 2361 mvsata_atapi_reset(chp, xfer); 2362 return 1; 2363 } 2364 2365 /* 2366 * If we missed an IRQ and were using DMA, flag it as a DMA error 2367 * and reset device. 2368 */ 2369 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2370 ata_channel_unlock(chp); 2371 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2372 sc_xfer->error = XS_RESET; 2373 mvsata_atapi_reset(chp, xfer); 2374 return (1); 2375 } 2376 /* 2377 * if the request sense command was aborted, report the short sense 2378 * previously recorded, else continue normal processing 2379 */ 2380 2381 again: 2382 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2383 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2384 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2385 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2386 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2387 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2388 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2389 2390 switch (phase) { 2391 case PHASE_CMDOUT: 2392 cmd = sc_xfer->cmd; 2393 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2394 /* Init the DMA channel if necessary */ 2395 if (xfer->c_flags & C_DMA) { 2396 error = mvsata_bdma_init(mvport, xfer); 2397 if (error) { 2398 if (error == EINVAL) { 2399 /* 2400 * We can't do DMA on this transfer 2401 * for some reason. Fall back to PIO. 2402 */ 2403 xfer->c_flags &= ~C_DMA; 2404 error = 0; 2405 } else { 2406 sc_xfer->error = XS_DRIVER_STUFFUP; 2407 break; 2408 } 2409 } 2410 } 2411 2412 /* send packet command */ 2413 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2414 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2415 2416 /* Start the DMA channel if necessary */ 2417 if (xfer->c_flags & C_DMA) { 2418 mvsata_bdma_start(mvport); 2419 chp->ch_flags |= ATACH_DMA_WAIT; 2420 } 2421 ata_channel_unlock(chp); 2422 return 1; 2423 2424 case PHASE_DATAOUT: 2425 /* write data */ 2426 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2427 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2428 (xfer->c_flags & C_DMA) != 0) { 2429 aprint_error_dev(atac->atac_dev, 2430 "channel %d drive %d: bad data phase DATAOUT\n", 2431 chp->ch_channel, xfer->c_drive); 2432 ata_channel_unlock(chp); 2433 if (xfer->c_flags & C_DMA) 2434 ata_dmaerr(drvp, 2435 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2436 sc_xfer->error = XS_TIMEOUT; 2437 mvsata_atapi_reset(chp, xfer); 2438 return 1; 2439 } 2440 xfer->c_lenoff = len - xfer->c_bcount; 2441 if (xfer->c_bcount < len) { 2442 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2443 " warning: write only %d of %d requested bytes\n", 2444 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2445 len); 2446 len = xfer->c_bcount; 2447 } 2448 2449 wdc->dataout_pio(chp, drvp->drive_flags, 2450 (char *)xfer->c_databuf + xfer->c_skip, len); 2451 2452 for (i = xfer->c_lenoff; i > 0; i -= 2) 2453 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2454 2455 xfer->c_skip += len; 2456 xfer->c_bcount -= len; 2457 ata_channel_unlock(chp); 2458 return 1; 2459 2460 case PHASE_DATAIN: 2461 /* Read data */ 2462 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2463 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2464 (xfer->c_flags & C_DMA) != 0) { 2465 aprint_error_dev(atac->atac_dev, 2466 "channel %d drive %d: bad data phase DATAIN\n", 2467 chp->ch_channel, xfer->c_drive); 2468 ata_channel_unlock(chp); 2469 if (xfer->c_flags & C_DMA) 2470 ata_dmaerr(drvp, 2471 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2472 sc_xfer->error = XS_TIMEOUT; 2473 mvsata_atapi_reset(chp, xfer); 2474 return 1; 2475 } 2476 xfer->c_lenoff = len - xfer->c_bcount; 2477 if (xfer->c_bcount < len) { 2478 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2479 " warning: reading only %d of %d bytes\n", 2480 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2481 len); 2482 len = xfer->c_bcount; 2483 } 2484 2485 wdc->datain_pio(chp, drvp->drive_flags, 2486 (char *)xfer->c_databuf + xfer->c_skip, len); 2487 2488 if (xfer->c_lenoff > 0) 2489 wdcbit_bucket(chp, len - xfer->c_bcount); 2490 2491 xfer->c_skip += len; 2492 xfer->c_bcount -= len; 2493 ata_channel_unlock(chp); 2494 return 1; 2495 2496 case PHASE_ABORTED: 2497 case PHASE_COMPLETED: 2498 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2499 if (xfer->c_flags & C_DMA) 2500 xfer->c_bcount -= sc_xfer->datalen; 2501 sc_xfer->resid = xfer->c_bcount; 2502 /* this will unlock channel lock too */ 2503 mvsata_atapi_phase_complete(xfer); 2504 return 1; 2505 2506 default: 2507 if (++retries<500) { 2508 DELAY(100); 2509 tfd = ATACH_ERR_ST( 2510 MVSATA_WDC_READ_1(mvport, SRB_FE), 2511 MVSATA_WDC_READ_1(mvport, SRB_CS) 2512 ); 2513 goto again; 2514 } 2515 aprint_error_dev(atac->atac_dev, 2516 "channel %d drive %d: unknown phase 0x%x\n", 2517 chp->ch_channel, xfer->c_drive, phase); 2518 if (ATACH_ST(tfd) & WDCS_ERR) { 2519 sc_xfer->error = XS_SHORTSENSE; 2520 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2521 } else { 2522 ata_channel_unlock(chp); 2523 if (xfer->c_flags & C_DMA) 2524 ata_dmaerr(drvp, 2525 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2526 sc_xfer->error = XS_RESET; 2527 mvsata_atapi_reset(chp, xfer); 2528 return (1); 2529 } 2530 } 2531 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2532 ("mvsata_atapi_intr: %s (end), error 0x%x " 2533 "sense 0x%x\n", __func__, 2534 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2535 ata_channel_unlock(chp); 2536 mvsata_atapi_done(chp, xfer); 2537 return 1; 2538 } 2539 2540 static void 2541 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2542 int reason) 2543 { 2544 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2545 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2546 bool deactivate = true; 2547 2548 /* remove this command from xfer queue */ 2549 switch (reason) { 2550 case KILL_GONE_INACTIVE: 2551 deactivate = false; 2552 /* FALLTHROUGH */ 2553 case KILL_GONE: 2554 sc_xfer->error = XS_DRIVER_STUFFUP; 2555 break; 2556 case KILL_RESET: 2557 sc_xfer->error = XS_RESET; 2558 break; 2559 case KILL_REQUEUE: 2560 sc_xfer->error = XS_REQUEUE; 2561 break; 2562 default: 2563 aprint_error_dev(MVSATA_DEV2(mvport), 2564 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2565 panic("mvsata_atapi_kill_xfer"); 2566 } 2567 2568 if (deactivate) { 2569 mvsata_quetag_put(mvport, xfer->c_slot); 2570 ata_deactivate_xfer(chp, xfer); 2571 } 2572 2573 ata_free_xfer(chp, xfer); 2574 scsipi_done(sc_xfer); 2575 } 2576 2577 static void 2578 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2579 { 2580 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2581 struct atac_softc *atac = chp->ch_atac; 2582 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2583 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2584 int tfd; 2585 2586 ata_channel_lock(chp); 2587 2588 mvsata_pmp_select(mvport, xfer->c_drive); 2589 2590 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2591 drvp->state = 0; 2592 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2593 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2594 chp->ch_channel, xfer->c_drive); 2595 sc_xfer->error = XS_SELTIMEOUT; 2596 } 2597 2598 ata_channel_unlock(chp); 2599 2600 mvsata_atapi_done(chp, xfer); 2601 return; 2602 } 2603 2604 static void 2605 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2606 { 2607 struct ata_channel *chp = xfer->c_chp; 2608 struct atac_softc *atac = chp->ch_atac; 2609 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2610 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2611 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2612 int tfd = 0; 2613 2614 ata_channel_lock_owned(chp); 2615 2616 /* wait for DSC if needed */ 2617 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2618 DPRINTF(DEBUG_XFERS, 2619 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2620 device_xname(atac->atac_dev), chp->ch_channel, 2621 xfer->c_drive, xfer->c_dscpoll)); 2622 if (cold) 2623 panic("mvsata_atapi_phase_complete: cold"); 2624 2625 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2626 WDCWAIT_TOUT) { 2627 /* 10ms not enough, try again in 1 tick */ 2628 if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) { 2629 aprint_error_dev(atac->atac_dev, 2630 "channel %d: wait_for_dsc failed\n", 2631 chp->ch_channel); 2632 ata_channel_unlock(chp); 2633 sc_xfer->error = XS_TIMEOUT; 2634 mvsata_atapi_reset(chp, xfer); 2635 } else { 2636 callout_reset(&xfer->c_timo_callout, 1, 2637 mvsata_atapi_polldsc, xfer); 2638 ata_channel_unlock(chp); 2639 } 2640 return; 2641 } 2642 } 2643 2644 /* 2645 * Some drive occasionally set WDCS_ERR with 2646 * "ATA illegal length indication" in the error 2647 * register. If we read some data the sense is valid 2648 * anyway, so don't report the error. 2649 */ 2650 if (ATACH_ST(tfd) & WDCS_ERR && 2651 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2652 sc_xfer->resid == sc_xfer->datalen)) { 2653 /* save the short sense */ 2654 sc_xfer->error = XS_SHORTSENSE; 2655 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2656 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2657 /* ask scsipi to send a REQUEST_SENSE */ 2658 sc_xfer->error = XS_BUSY; 2659 sc_xfer->status = SCSI_CHECK; 2660 } else 2661 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2662 ata_channel_unlock(chp); 2663 ata_dmaerr(drvp, 2664 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2665 sc_xfer->error = XS_RESET; 2666 mvsata_atapi_reset(chp, xfer); 2667 return; 2668 } 2669 } 2670 if (xfer->c_bcount != 0) { 2671 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2672 " bcount value is %d after io\n", 2673 device_xname(atac->atac_dev), chp->ch_channel, 2674 xfer->c_drive, xfer->c_bcount)); 2675 } 2676 #ifdef DIAGNOSTIC 2677 if (xfer->c_bcount < 0) { 2678 aprint_error_dev(atac->atac_dev, 2679 "channel %d drive %d: mvsata_atapi_intr:" 2680 " warning: bcount value is %d after io\n", 2681 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2682 } 2683 #endif 2684 2685 DPRINTF(DEBUG_XFERS, 2686 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2687 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2688 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2689 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2690 ata_channel_unlock(chp); 2691 mvsata_atapi_done(chp, xfer); 2692 } 2693 2694 static void 2695 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2696 { 2697 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2698 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2699 bool iserror = (sc_xfer->error != XS_NOERROR); 2700 2701 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2702 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2703 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2704 xfer->c_drive, (u_int)xfer->c_flags)); 2705 2706 if (ata_waitdrain_xfer_check(chp, xfer)) 2707 return; 2708 2709 /* mark controller inactive and free the command */ 2710 mvsata_quetag_put(mvport, xfer->c_slot); 2711 ata_deactivate_xfer(chp, xfer); 2712 2713 ata_free_xfer(chp, xfer); 2714 2715 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2716 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2717 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2718 scsipi_done(sc_xfer); 2719 DPRINTF(DEBUG_FUNCS, 2720 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2721 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2722 chp->ch_flags)); 2723 if (!iserror) 2724 atastart(chp); 2725 } 2726 2727 static void 2728 mvsata_atapi_polldsc(void *arg) 2729 { 2730 struct ata_xfer *xfer = arg; 2731 struct ata_channel *chp = xfer->c_chp; 2732 2733 ata_channel_lock(chp); 2734 2735 /* this will unlock channel lock too */ 2736 mvsata_atapi_phase_complete(xfer); 2737 } 2738 #endif /* NATAPIBUS > 0 */ 2739 2740 2741 /* 2742 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2743 * if supported queuing command by atabus? The race condition will not happen 2744 * if this is called only to the thread of atabus. 2745 */ 2746 static int 2747 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2748 { 2749 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2750 struct ata_bio *ata_bio = &xfer->c_bio; 2751 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2752 struct eprd *eprd; 2753 bus_addr_t crqb_base_addr; 2754 bus_dmamap_t data_dmamap; 2755 uint32_t reg; 2756 int erqqip, erqqop, next, rv, i; 2757 2758 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2759 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2760 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2761 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2762 2763 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2764 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2765 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2766 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2767 next = erqqip; 2768 MVSATA_EDMAQ_INC(next); 2769 if (next == erqqop) { 2770 /* queue full */ 2771 return EBUSY; 2772 } 2773 DPRINTF(DEBUG_XFERS, 2774 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2775 2776 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2777 ata_bio->flags); 2778 if (rv != 0) 2779 return rv; 2780 2781 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2782 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2783 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2784 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2785 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2786 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2787 2788 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2789 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2790 eprd->eot = htole16(0); 2791 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2792 eprd++; 2793 } 2794 (eprd - 1)->eot |= htole16(EPRD_EOT); 2795 #ifdef MVSATA_DEBUG 2796 if (mvsata_debug >= 3) 2797 mvsata_print_eprd(mvport, xfer->c_slot); 2798 #endif 2799 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2800 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2801 BUS_DMASYNC_PREWRITE); 2802 2803 /* setup EDMA Command Request Block (CRQB) Data */ 2804 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2805 #ifdef MVSATA_DEBUG 2806 if (mvsata_debug >= 3) 2807 mvsata_print_crqb(mvport, erqqip); 2808 #endif 2809 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2810 erqqip * sizeof(union mvsata_crqb), 2811 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2812 2813 MVSATA_EDMAQ_INC(erqqip); 2814 2815 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2816 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2817 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2818 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2819 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2820 2821 return 0; 2822 } 2823 2824 static int 2825 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2826 { 2827 struct ata_channel *chp = &mvport->port_ata_channel; 2828 struct crpb *crpb; 2829 struct ata_bio *ata_bio; 2830 struct ata_xfer *xfer; 2831 uint32_t reg; 2832 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2833 int st, dmaerr; 2834 2835 /* First, Sync for Request Queue buffer */ 2836 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2837 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2838 if (mvport->port_prev_erqqop != erqqop) { 2839 const int s = sizeof(union mvsata_crqb); 2840 2841 if (mvport->port_prev_erqqop < erqqop) 2842 n = erqqop - mvport->port_prev_erqqop; 2843 else { 2844 if (erqqop > 0) 2845 bus_dmamap_sync(mvport->port_dmat, 2846 mvport->port_crqb_dmamap, 0, erqqop * s, 2847 BUS_DMASYNC_POSTWRITE); 2848 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2849 } 2850 if (n > 0) 2851 bus_dmamap_sync(mvport->port_dmat, 2852 mvport->port_crqb_dmamap, 2853 mvport->port_prev_erqqop * s, n * s, 2854 BUS_DMASYNC_POSTWRITE); 2855 mvport->port_prev_erqqop = erqqop; 2856 } 2857 2858 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2859 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2860 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2861 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2862 2863 DPRINTF(DEBUG_XFERS, 2864 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2865 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2866 mvport->port, erpqip, erpqop)); 2867 2868 if (erpqop == erpqip) 2869 return 0; 2870 2871 if (erpqop < erpqip) 2872 n = erpqip - erpqop; 2873 else { 2874 if (erpqip > 0) 2875 bus_dmamap_sync(mvport->port_dmat, 2876 mvport->port_crpb_dmamap, 2877 0, erpqip * sizeof(struct crpb), 2878 BUS_DMASYNC_POSTREAD); 2879 n = MVSATA_EDMAQ_LEN - erpqop; 2880 } 2881 if (n > 0) 2882 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2883 erpqop * sizeof(struct crpb), 2884 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2885 2886 prev_erpqop = erpqop; 2887 while (erpqop != erpqip) { 2888 #ifdef MVSATA_DEBUG 2889 if (mvsata_debug >= 3) 2890 mvsata_print_crpb(mvport, erpqop); 2891 #endif 2892 crpb = mvport->port_crpb + erpqop; 2893 MVSATA_EDMAQ_INC(erpqop); 2894 2895 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2896 2897 if ((mvport->port_quetagidx & __BIT(quetag)) == 0) { 2898 /* not actually executing */ 2899 continue; 2900 } 2901 2902 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2903 2904 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2905 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2906 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2907 2908 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2909 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2910 2911 ata_bio = &xfer->c_bio; 2912 ata_bio->error = NOERROR; 2913 ata_bio->r_error = 0; 2914 if (st & WDCS_ERR) 2915 ata_bio->error = ERROR; 2916 if (st & WDCS_BSY) 2917 ata_bio->error = TIMEOUT; 2918 if (dmaerr != 0) 2919 ata_bio->error = ERR_DMA; 2920 2921 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2922 2923 mvsata_bio_intr(chp, xfer, 1); 2924 if (xfer1 == NULL) 2925 handled++; 2926 else if (xfer == xfer1) { 2927 handled = 1; 2928 break; 2929 } 2930 } 2931 if (prev_erpqop < erpqop) 2932 n = erpqop - prev_erpqop; 2933 else { 2934 if (erpqop > 0) 2935 bus_dmamap_sync(mvport->port_dmat, 2936 mvport->port_crpb_dmamap, 0, 2937 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2938 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2939 } 2940 if (n > 0) 2941 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2942 prev_erpqop * sizeof(struct crpb), 2943 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2944 2945 reg &= ~EDMA_RESQP_ERPQP_MASK; 2946 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2947 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2948 2949 return handled; 2950 } 2951 2952 static int 2953 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2954 { 2955 int xtime; 2956 2957 for (xtime = 0; xtime < timeout * 10; xtime++) { 2958 if (mvsata_edma_handle(mvport, xfer)) 2959 return 0; 2960 DELAY(100); 2961 } 2962 2963 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2964 mvsata_edma_rqq_remove(mvport, xfer); 2965 xfer->c_flags |= C_TIMEOU; 2966 return 1; 2967 } 2968 2969 static void 2970 mvsata_edma_timeout(void *arg) 2971 { 2972 struct ata_xfer *xfer = (struct ata_xfer *)arg; 2973 struct ata_channel *chp = xfer->c_chp; 2974 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2975 int s; 2976 2977 s = splbio(); 2978 DPRINTF(DEBUG_FUNCS, ("%s: %p\n", __func__, xfer)); 2979 2980 if (ata_timo_xfer_check(xfer)) { 2981 /* Already logged */ 2982 goto out; 2983 } 2984 2985 mvsata_edma_rqq_remove(mvport, xfer); 2986 xfer->c_flags |= C_TIMEOU; 2987 mvsata_bio_intr(chp, xfer, 0); 2988 2989 out: 2990 splx(s); 2991 } 2992 2993 static void 2994 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2995 { 2996 struct ata_channel *chp = &mvport->port_ata_channel; 2997 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2998 bus_addr_t crqb_base_addr; 2999 int erqqip, i; 3000 3001 /* First, hardware reset, stop EDMA */ 3002 mvsata_hreset_port(mvport); 3003 3004 /* cleanup completed EDMA safely */ 3005 mvsata_edma_handle(mvport, NULL); 3006 3007 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 3008 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 3009 3010 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 3011 struct ata_xfer *rqxfer; 3012 3013 if ((mvport->port_quetagidx & __BIT(i)) == 0) 3014 continue; 3015 3016 if (i == xfer->c_slot) { 3017 /* remove xfer from EDMA request queue */ 3018 bus_dmamap_sync(mvport->port_dmat, 3019 mvport->port_eprd_dmamap, 3020 mvport->port_reqtbl[i].eprd_offset, 3021 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 3022 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 3023 /* quetag freed by caller later */ 3024 continue; 3025 } 3026 3027 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 3028 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 3029 erqqip++; 3030 } 3031 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 3032 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 3033 BUS_DMASYNC_POSTWRITE); 3034 3035 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 3036 mvsata_edma_reset_qptr(mvport); 3037 mvsata_edma_enable(mvport); 3038 3039 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 3040 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 3041 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 3042 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 3043 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 3044 } 3045 3046 #if NATAPIBUS > 0 3047 static int 3048 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 3049 { 3050 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 3051 struct eprd *eprd; 3052 bus_dmamap_t data_dmamap; 3053 bus_addr_t eprd_addr; 3054 int i, rv; 3055 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 3056 3057 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 3058 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 3059 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3060 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 3061 3062 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 3063 sc_xfer->datalen, 3064 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 3065 if (rv != 0) 3066 return rv; 3067 3068 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 3069 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 3070 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 3071 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 3072 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 3073 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 3074 3075 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 3076 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 3077 eprd->eot = htole16(0); 3078 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 3079 eprd++; 3080 } 3081 (eprd - 1)->eot |= htole16(EPRD_EOT); 3082 #ifdef MVSATA_DEBUG 3083 if (mvsata_debug >= 3) 3084 mvsata_print_eprd(mvport, xfer->c_slot); 3085 #endif 3086 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 3087 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 3088 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 3089 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3090 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3091 3092 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 3093 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 3094 3095 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 3096 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 3097 else 3098 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 3099 3100 return 0; 3101 } 3102 3103 static void 3104 mvsata_bdma_start(struct mvsata_port *mvport) 3105 { 3106 3107 #ifdef MVSATA_DEBUG 3108 if (mvsata_debug >= 3) 3109 mvsata_print_eprd(mvport, 0); 3110 #endif 3111 3112 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 3113 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 3114 } 3115 #endif 3116 #endif 3117 3118 3119 static int 3120 mvsata_port_init(struct mvsata_hc *mvhc, int port) 3121 { 3122 struct mvsata_softc *sc = mvhc->hc_sc; 3123 struct mvsata_port *mvport; 3124 struct ata_channel *chp; 3125 int channel, rv, i; 3126 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 3127 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 3128 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 3129 3130 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 3131 M_ZERO | M_NOWAIT); 3132 if (mvport == NULL) { 3133 aprint_error("%s:%d: can't allocate memory for port %d\n", 3134 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3135 return ENOMEM; 3136 } 3137 3138 mvport->port = port; 3139 mvport->port_hc = mvhc; 3140 mvport->port_edmamode_negotiated = nodma; 3141 3142 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3143 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3144 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3145 if (rv != 0) { 3146 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3147 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3148 goto fail0; 3149 } 3150 mvport->port_iot = mvhc->hc_iot; 3151 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3152 &mvport->port_sata_sstatus); 3153 if (rv != 0) { 3154 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3155 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3156 goto fail0; 3157 } 3158 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3159 &mvport->port_sata_serror); 3160 if (rv != 0) { 3161 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3162 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3163 goto fail0; 3164 } 3165 if (sc->sc_rev == gen1) 3166 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3167 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3168 else 3169 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3170 SATA_SC, 4, &mvport->port_sata_scontrol); 3171 if (rv != 0) { 3172 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3173 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3174 goto fail0; 3175 } 3176 mvport->port_dmat = sc->sc_dmat; 3177 mvhc->hc_ports[port] = mvport; 3178 3179 channel = mvhc->hc * sc->sc_port + port; 3180 chp = &mvport->port_ata_channel; 3181 chp->ch_channel = channel; 3182 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3183 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3184 sc->sc_ata_channels[channel] = chp; 3185 3186 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3187 if (rv != 0) 3188 goto fail0; 3189 3190 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3191 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3192 if (rv != 0) { 3193 aprint_error( 3194 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3195 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3196 goto fail0; 3197 } 3198 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3199 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3200 if (rv != 0) { 3201 aprint_error( 3202 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3203 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3204 goto fail1; 3205 } 3206 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3207 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3208 if (rv != 0) { 3209 aprint_error( 3210 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3211 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3212 goto fail2; 3213 } 3214 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3215 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3216 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 3217 &mvport->port_reqtbl[i].data_dmamap); 3218 if (rv != 0) { 3219 aprint_error("%s:%d:%d:" 3220 " EDMA data map(%d) create failed: error=%d\n", 3221 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3222 rv); 3223 goto fail3; 3224 } 3225 } 3226 3227 return 0; 3228 3229 fail3: 3230 for (i--; i >= 0; i--) 3231 bus_dmamap_destroy(mvport->port_dmat, 3232 mvport->port_reqtbl[i].data_dmamap); 3233 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3234 fail2: 3235 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3236 fail1: 3237 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3238 fail0: 3239 return rv; 3240 } 3241 3242 static int 3243 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3244 { 3245 int hc, port, rv, i; 3246 3247 hc = mvport->port_hc->hc; 3248 port = mvport->port; 3249 3250 /* Create subregion for Shadow Registers Map */ 3251 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3252 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3253 if (rv != 0) { 3254 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3255 device_xname(MVSATA_DEV2(mvport)), hc, port); 3256 return rv; 3257 } 3258 wdr->cmd_iot = mvport->port_iot; 3259 3260 /* Once create subregion for each command registers */ 3261 for (i = 0; i < WDC_NREG; i++) { 3262 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3263 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3264 if (rv != 0) { 3265 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3266 device_xname(MVSATA_DEV2(mvport)), hc, port); 3267 return rv; 3268 } 3269 } 3270 /* Create subregion for Alternate Status register */ 3271 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3272 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3273 if (rv != 0) { 3274 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3275 device_xname(MVSATA_DEV2(mvport)), hc, port); 3276 return rv; 3277 } 3278 wdr->ctl_iot = mvport->port_iot; 3279 3280 wdc_init_shadow_regs(wdr); 3281 3282 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3283 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3284 if (rv != 0) { 3285 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3286 device_xname(MVSATA_DEV2(mvport)), hc, port); 3287 return rv; 3288 } 3289 wdr->sata_iot = mvport->port_iot; 3290 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3291 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3292 if (rv != 0) { 3293 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3294 device_xname(MVSATA_DEV2(mvport)), hc, port); 3295 return rv; 3296 } 3297 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3298 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3299 if (rv != 0) { 3300 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3301 device_xname(MVSATA_DEV2(mvport)), hc, port); 3302 return rv; 3303 } 3304 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3305 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3306 if (rv != 0) { 3307 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3308 device_xname(MVSATA_DEV2(mvport)), hc, port); 3309 return rv; 3310 } 3311 3312 return 0; 3313 } 3314 3315 3316 #ifndef MVSATA_WITHOUTDMA 3317 /* 3318 * There are functions to remember Host Queue Tag. 3319 */ 3320 3321 static inline void 3322 mvsata_quetag_get(struct mvsata_port *mvport, uint8_t quetag) 3323 { 3324 KASSERT(quetag <= 32); 3325 3326 /* 3327 * Do not check whether it's already set, can happen when 3328 * postponing bio or atapi xfer to thread. 3329 */ 3330 mvport->port_quetagidx |= __BIT(quetag); 3331 } 3332 3333 static inline void 3334 mvsata_quetag_put(struct mvsata_port *mvport, uint8_t quetag) 3335 { 3336 KASSERT(quetag <= 32); 3337 KASSERT((mvport->port_quetagidx & __BIT(quetag)) != 0); 3338 mvport->port_quetagidx &= ~__BIT(quetag); 3339 } 3340 3341 static void * 3342 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3343 bus_dmamap_t *dmamap, size_t size, int write) 3344 { 3345 bus_dma_segment_t seg; 3346 int nseg, rv; 3347 void *kva; 3348 3349 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3350 BUS_DMA_NOWAIT); 3351 if (rv != 0) { 3352 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3353 device_xname(MVSATA_DEV2(mvport)), 3354 mvport->port_hc->hc, mvport->port, rv); 3355 goto fail; 3356 } 3357 3358 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3359 if (rv != 0) { 3360 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3361 device_xname(MVSATA_DEV2(mvport)), 3362 mvport->port_hc->hc, mvport->port, rv); 3363 goto free; 3364 } 3365 3366 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3367 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3368 if (rv != 0) { 3369 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3370 device_xname(MVSATA_DEV2(mvport)), 3371 mvport->port_hc->hc, mvport->port, rv); 3372 goto unmap; 3373 } 3374 3375 if (!write) 3376 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3377 3378 return kva; 3379 3380 unmap: 3381 bus_dmamem_unmap(dmat, kva, size); 3382 free: 3383 bus_dmamem_free(dmat, &seg, nseg); 3384 fail: 3385 return NULL; 3386 } 3387 3388 /* ARGSUSED */ 3389 static void 3390 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3391 bus_dmamap_t dmamap, void *kva) 3392 { 3393 3394 bus_dmamap_unload(dmat, dmamap); 3395 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3396 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3397 } 3398 3399 static int 3400 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3401 size_t datalen, int flags) 3402 { 3403 int rv, lop, sop; 3404 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3405 3406 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3407 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3408 3409 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3410 NULL, BUS_DMA_NOWAIT | lop); 3411 if (rv) { 3412 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3413 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3414 mvport->port, rv); 3415 return rv; 3416 } 3417 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3418 data_dmamap->dm_mapsize, sop); 3419 3420 return 0; 3421 } 3422 3423 static inline void 3424 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3425 { 3426 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3427 3428 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3429 data_dmamap->dm_mapsize, 3430 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3431 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3432 } 3433 #endif 3434 3435 static void 3436 mvsata_hreset_port(struct mvsata_port *mvport) 3437 { 3438 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3439 3440 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3441 3442 delay(25); /* allow reset propagation */ 3443 3444 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3445 3446 mvport->_fix_phy_param._fix_phy(mvport); 3447 3448 if (sc->sc_gen == gen1) 3449 delay(1000); 3450 } 3451 3452 static void 3453 mvsata_reset_port(struct mvsata_port *mvport) 3454 { 3455 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3456 3457 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3458 3459 mvsata_hreset_port(mvport); 3460 3461 if (device_is_a(parent, "pci")) 3462 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3463 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3464 else /* SoC */ 3465 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3466 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3467 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3468 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3469 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3470 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3471 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3472 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3473 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3474 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3475 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3476 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3477 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3478 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3479 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3480 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3481 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3482 } 3483 3484 static void 3485 mvsata_reset_hc(struct mvsata_hc *mvhc) 3486 { 3487 #if 0 3488 uint32_t val; 3489 #endif 3490 3491 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3492 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3493 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3494 3495 #if 0 /* XXXX needs? */ 3496 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3497 3498 /* 3499 * Keep the SS during power on and the reference clock bits (reset 3500 * sample) 3501 */ 3502 val = MVSATA_HC_READ_4(mvhc, 0x020); 3503 val &= 0x1c1c1c1c; 3504 val |= 0x03030303; 3505 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3506 #endif 3507 } 3508 3509 static uint32_t 3510 mvsata_softreset(struct mvsata_port *mvport, int flags) 3511 { 3512 struct ata_channel *chp = &mvport->port_ata_channel; 3513 uint32_t sig0 = ~0; 3514 int timeout; 3515 uint8_t st0; 3516 3517 ata_channel_lock_owned(chp); 3518 3519 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3520 delay(10); 3521 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3522 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3523 delay(10); 3524 3525 /* wait for BSY to deassert */ 3526 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3527 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3528 3529 if ((st0 & WDCS_BSY) == 0) { 3530 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3531 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3532 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3533 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3534 goto out; 3535 } 3536 ata_delay(chp, 10, "atarst", flags); 3537 } 3538 3539 aprint_error("%s:%d:%d: %s: timeout\n", 3540 device_xname(MVSATA_DEV2(mvport)), 3541 mvport->port_hc->hc, mvport->port, __func__); 3542 3543 out: 3544 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3545 return sig0; 3546 } 3547 3548 #ifndef MVSATA_WITHOUTDMA 3549 static void 3550 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3551 { 3552 const bus_addr_t crpb_addr = 3553 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3554 const uint32_t crpb_addr_mask = 3555 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3556 3557 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3558 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3559 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3560 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3561 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3562 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3563 } 3564 3565 static inline void 3566 mvsata_edma_enable(struct mvsata_port *mvport) 3567 { 3568 3569 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3570 } 3571 3572 static int 3573 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3574 { 3575 struct ata_channel *chp = &mvport->port_ata_channel; 3576 uint32_t status, command; 3577 uint32_t idlestatus = EDMA_S_EDMAIDLE | EDMA_S_ECACHEEMPTY; 3578 int t; 3579 3580 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3581 3582 timeout = mstohz(timeout + hztoms(1) - 1); 3583 3584 for (t = 0; ; ++t) { 3585 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3586 if ((status & idlestatus) == idlestatus) 3587 break; 3588 if (t >= timeout) 3589 break; 3590 ata_delay(chp, hztoms(1), "mvsata_edma1", wflags); 3591 } 3592 if (t >= timeout) { 3593 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3594 device_xname(MVSATA_DEV2(mvport)), 3595 mvport->port_hc->hc, mvport->port); 3596 return EBUSY; 3597 } 3598 3599 /* The disable bit (eDsEDMA) is self negated. */ 3600 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3601 3602 for (t = 0; ; ++t) { 3603 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3604 if (!(command & EDMA_CMD_EENEDMA)) 3605 break; 3606 if (t >= timeout) 3607 break; 3608 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3609 } 3610 if (t >= timeout) { 3611 aprint_error("%s:%d:%d: unable to re-enable EDMA\n", 3612 device_xname(MVSATA_DEV2(mvport)), 3613 mvport->port_hc->hc, mvport->port); 3614 return EBUSY; 3615 } 3616 } 3617 return 0; 3618 } 3619 3620 /* 3621 * Set EDMA registers according to mode. 3622 * ex. NCQ/TCQ(queued)/non queued. 3623 */ 3624 static void 3625 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3626 { 3627 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3628 uint32_t reg; 3629 3630 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3631 reg |= EDMA_CFG_RESERVED; 3632 3633 if (mode == ncq) { 3634 if (sc->sc_gen == gen1) { 3635 aprint_error_dev(MVSATA_DEV2(mvport), 3636 "GenI not support NCQ\n"); 3637 return; 3638 } else if (sc->sc_gen == gen2) 3639 reg |= EDMA_CFG_EDEVERR; 3640 reg |= EDMA_CFG_ESATANATVCMDQUE; 3641 } else if (mode == queued) { 3642 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3643 reg |= EDMA_CFG_EQUE; 3644 } else 3645 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3646 3647 if (sc->sc_gen == gen1) 3648 reg |= EDMA_CFG_ERDBSZ; 3649 else if (sc->sc_gen == gen2) 3650 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3651 else if (sc->sc_gen == gen2e) { 3652 device_t parent = device_parent(MVSATA_DEV(sc)); 3653 3654 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3655 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3656 3657 if (device_is_a(parent, "pci")) 3658 reg |= ( 3659 #if NATAPIBUS > 0 3660 EDMA_CFG_EEARLYCOMPLETIONEN | 3661 #endif 3662 EDMA_CFG_ECUTTHROUGHEN | 3663 EDMA_CFG_EWRBUFFERLEN | 3664 EDMA_CFG_ERDBSZEXT); 3665 } 3666 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3667 3668 reg = ( 3669 EDMA_IE_EIORDYERR | 3670 EDMA_IE_ETRANSINT | 3671 EDMA_IE_EDEVCON | 3672 EDMA_IE_EDEVDIS); 3673 if (sc->sc_gen != gen1) 3674 reg |= ( 3675 EDMA_IE_TRANSPROTERR | 3676 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3677 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3678 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3679 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3680 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3681 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3682 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3683 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3684 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3685 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3686 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3687 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3688 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3689 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3690 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3691 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3692 EDMA_IE_ESELFDIS); 3693 3694 if (mode == ncq) 3695 reg |= EDMA_IE_EDEVERR; 3696 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3697 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3698 reg &= ~EDMA_IE_EDEVERR; 3699 if (mode != ncq) 3700 reg |= EDMA_IE_EDEVERR; 3701 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3702 if (sc->sc_gen == gen2e) { 3703 /* 3704 * Clear FISWait4HostRdyEn[0] and [2]. 3705 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3706 * [2]: SDB FIS is received with <ERR> bit set to 1. 3707 */ 3708 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3709 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3710 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3711 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3712 } 3713 3714 mvport->port_edmamode_curr = mode; 3715 } 3716 3717 3718 /* 3719 * Generation dependent functions 3720 */ 3721 3722 static void 3723 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3724 struct ata_xfer *xfer) 3725 { 3726 struct crqb *crqb; 3727 bus_addr_t eprd_addr; 3728 daddr_t blkno; 3729 uint32_t rw; 3730 uint8_t cmd, head; 3731 int i; 3732 struct ata_bio *ata_bio = &xfer->c_bio; 3733 3734 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3735 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3736 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3737 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3738 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3739 head = WDSD_LBA; 3740 } else { 3741 head = 0; 3742 } 3743 blkno = ata_bio->blkno; 3744 if (ata_bio->flags & ATA_LBA48) 3745 cmd = atacmd_to48(cmd); 3746 else { 3747 head |= ((ata_bio->blkno >> 24) & 0xf); 3748 blkno &= 0xffffff; 3749 } 3750 crqb = &mvport->port_crqb->crqb + erqqip; 3751 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3752 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3753 crqb->ctrlflg = 3754 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3755 CRQB_CPMPORT(xfer->c_drive)); 3756 i = 0; 3757 if (mvport->port_edmamode_curr == dma) { 3758 if (ata_bio->flags & ATA_LBA48) 3759 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3760 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3761 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3762 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3763 } else { /* ncq/queued */ 3764 3765 /* 3766 * XXXX: Oops, ata command is not correct. And, atabus layer 3767 * has not been supported yet now. 3768 * Queued DMA read/write. 3769 * read/write FPDMAQueued. 3770 */ 3771 3772 if (ata_bio->flags & ATA_LBA48) 3773 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3774 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3775 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3776 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3777 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3778 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3779 } 3780 if (ata_bio->flags & ATA_LBA48) { 3781 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3782 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3783 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3784 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3785 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3786 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3787 } 3788 crqb->atacommand[i++] = 3789 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3790 crqb->atacommand[i++] = 3791 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3792 crqb->atacommand[i++] = 3793 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3794 crqb->atacommand[i++] = 3795 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3796 crqb->atacommand[i++] = htole16( 3797 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3798 CRQB_ATACOMMAND_LAST); 3799 } 3800 #endif 3801 3802 static uint32_t 3803 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3804 { 3805 struct mvsata_hc *hc = mvport->port_hc; 3806 uint32_t reg; 3807 3808 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3809 /* 3810 * [12:11] : pre 3811 * [7:5] : amps 3812 */ 3813 return reg & 0x000018e0; 3814 } 3815 3816 static void 3817 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3818 { 3819 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3820 struct mvsata_hc *mvhc = mvport->port_hc; 3821 uint32_t reg; 3822 int port = mvport->port, fix_apm_sq = 0; 3823 3824 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3825 if (sc->sc_rev == 0x01) 3826 fix_apm_sq = 1; 3827 } else { 3828 if (sc->sc_rev == 0x00) 3829 fix_apm_sq = 1; 3830 } 3831 3832 if (fix_apm_sq) { 3833 /* 3834 * Disable auto-power management 3835 * 88SX50xx FEr SATA#12 3836 */ 3837 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3838 reg |= (1 << 19); 3839 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3840 3841 /* 3842 * Fix squelch threshold 3843 * 88SX50xx FEr SATA#9 3844 */ 3845 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3846 reg &= ~0x3; 3847 reg |= 0x1; 3848 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3849 } 3850 3851 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3852 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3853 reg &= ~0x000018e0; /* pre and amps mask */ 3854 reg |= mvport->_fix_phy_param.pre_amps; 3855 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3856 } 3857 3858 static void 3859 mvsata_devconn_gen1(struct mvsata_port *mvport) 3860 { 3861 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3862 3863 /* Fix for 88SX50xx FEr SATA#2 */ 3864 mvport->_fix_phy_param._fix_phy(mvport); 3865 3866 /* If disk is connected, then enable the activity LED */ 3867 if (sc->sc_rev == 0x03) { 3868 /* XXXXX */ 3869 } 3870 } 3871 3872 static uint32_t 3873 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3874 { 3875 uint32_t reg; 3876 3877 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3878 /* 3879 * [10:8] : amps 3880 * [7:5] : pre 3881 */ 3882 return reg & 0x000007e0; 3883 } 3884 3885 static void 3886 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3887 { 3888 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3889 uint32_t reg; 3890 3891 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3892 sc->sc_gen == gen2e) { 3893 /* 3894 * Fix for 3895 * 88SX60X1 FEr SATA #23 3896 * 88SX6042/88SX7042 FEr SATA #23 3897 * 88F5182 FEr #SATA-S13 3898 * 88F5082 FEr #SATA-S13 3899 */ 3900 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3901 reg &= ~(1 << 16); 3902 reg |= (1 << 31); 3903 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3904 3905 delay(200); 3906 3907 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3908 reg &= ~((1 << 16) | (1 << 31)); 3909 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3910 3911 delay(200); 3912 } 3913 3914 /* Fix values in PHY Mode 3 Register.*/ 3915 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3916 reg &= ~0x7F900000; 3917 reg |= 0x2A800000; 3918 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3919 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3920 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3921 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3922 reg &= ~0x0000001c; 3923 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3924 3925 /* 3926 * Fix values in PHY Mode 4 Register. 3927 * 88SX60x1 FEr SATA#10 3928 * 88F5182 GL #SATA-S10 3929 * 88F5082 GL #SATA-S10 3930 */ 3931 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3932 sc->sc_gen == gen2e) { 3933 uint32_t tmp = 0; 3934 3935 /* 88SX60x1 FEr SATA #13 */ 3936 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3937 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3938 3939 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3940 reg |= (1 << 0); 3941 reg &= ~(1 << 1); 3942 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3943 if (sc->sc_gen == gen2e) { 3944 reg &= ~0x5de3fffc; 3945 reg |= (1 << 2); 3946 } 3947 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3948 3949 /* 88SX60x1 FEr SATA #13 */ 3950 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3951 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3952 } 3953 3954 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3955 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3956 reg &= ~0x000007e0; /* pre and amps mask */ 3957 reg |= mvport->_fix_phy_param.pre_amps; 3958 reg &= ~(1 << 16); 3959 if (sc->sc_gen == gen2e) { 3960 /* 3961 * according to mvSata 3.6.1, some IIE values are fixed. 3962 * some reserved fields must be written with fixed values. 3963 */ 3964 reg &= ~0xC30FF01F; 3965 reg |= 0x0000900F; 3966 } 3967 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3968 } 3969 3970 #ifndef MVSATA_WITHOUTDMA 3971 static void 3972 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3973 struct ata_xfer *xfer) 3974 { 3975 struct crqb_gen2e *crqb; 3976 bus_addr_t eprd_addr; 3977 uint32_t ctrlflg, rw; 3978 uint8_t fis[RHD_FISLEN]; 3979 3980 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3981 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3982 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3983 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3984 CRQB_CPMPORT(xfer->c_drive) | 3985 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3986 3987 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3988 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3989 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3990 crqb->ctrlflg = htole32(ctrlflg); 3991 3992 satafis_rhd_construct_bio(xfer, fis); 3993 3994 crqb->atacommand[0] = 0; 3995 crqb->atacommand[1] = 0; 3996 /* copy over the ATA command part of the fis */ 3997 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3998 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3999 } 4000 4001 #ifdef MVSATA_DEBUG 4002 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 4003 do { \ 4004 int _i; \ 4005 u_char *_p = (p); \ 4006 \ 4007 printf(#type "(%d)", (n)); \ 4008 for (_i = 0; _i < (size); _i++, _p++) { \ 4009 if (_i % 16 == 0) \ 4010 printf("\n "); \ 4011 printf(" %02x", *_p); \ 4012 } \ 4013 printf("\n"); \ 4014 } while (0 /* CONSTCOND */) 4015 4016 static void 4017 mvsata_print_crqb(struct mvsata_port *mvport, int n) 4018 { 4019 4020 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 4021 n, (u_char *)(mvport->port_crqb + n)); 4022 } 4023 4024 static void 4025 mvsata_print_crpb(struct mvsata_port *mvport, int n) 4026 { 4027 4028 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 4029 n, (u_char *)(mvport->port_crpb + n)); 4030 } 4031 4032 static void 4033 mvsata_print_eprd(struct mvsata_port *mvport, int n) 4034 { 4035 struct eprd *eprd; 4036 int i = 0; 4037 4038 eprd = mvport->port_reqtbl[n].eprd; 4039 while (1 /*CONSTCOND*/) { 4040 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 4041 i, (u_char *)eprd); 4042 if (eprd->eot & EPRD_EOT) 4043 break; 4044 eprd++; 4045 i++; 4046 } 4047 } 4048 #endif 4049 #endif 4050
Indexes created Mon Sep 22 21:09:42 GMT 2025