mvsata.c revision 1.43
1 /* $NetBSD: mvsata.c,v 1.43 2018/10/22 20:13:47 jdolecek Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.43 2018/10/22 20:13:47 jdolecek Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 #include <dev/ic/mvsatareg.h> 62 #include <dev/ic/mvsatavar.h> 63 64 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 65 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 66 67 #define MVSATA_HC_READ_4(hc, reg) \ 68 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 69 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 70 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 71 #define MVSATA_EDMA_READ_4(mvport, reg) \ 72 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 73 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 74 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 75 #define MVSATA_WDC_READ_2(mvport, reg) \ 76 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 77 SHADOW_REG_BLOCK_OFFSET + (reg)) 78 #define MVSATA_WDC_READ_1(mvport, reg) \ 79 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 80 SHADOW_REG_BLOCK_OFFSET + (reg)) 81 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 82 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 83 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 84 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 85 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 86 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 87 88 #ifdef MVSATA_DEBUG 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_FUNCS 0x08 93 #define DEBUG_PROBE 0x10 94 95 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 96 int mvsata_debug = 0; 97 #else 98 #define DPRINTF(n,x) 99 #endif 100 101 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 102 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 103 sending a cmd */ 104 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 105 106 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 107 108 109 static void mvsata_probe_drive(struct ata_channel *); 110 111 #ifndef MVSATA_WITHOUTDMA 112 static void mvsata_reset_channel(struct ata_channel *, int); 113 static int mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 114 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 115 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 116 static int mvsata_addref(struct ata_drive_datas *); 117 static void mvsata_delref(struct ata_drive_datas *); 118 static void mvsata_killpending(struct ata_drive_datas *); 119 120 #if NATAPIBUS > 0 121 static void mvsata_atapibus_attach(struct atabus_softc *); 122 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 123 scsipi_adapter_req_t, void *); 124 static void mvsata_atapi_minphys(struct buf *); 125 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 126 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 127 #endif 128 #endif 129 130 static void mvsata_setup_channel(struct ata_channel *); 131 132 #ifndef MVSATA_WITHOUTDMA 133 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 134 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 135 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 136 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 137 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 138 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 139 int); 140 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 141 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 142 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 143 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 144 int); 145 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 147 #if NATAPIBUS > 0 148 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 149 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 150 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 151 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 152 int); 153 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 154 static void mvsata_atapi_phase_complete(struct ata_xfer *); 155 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 156 static void mvsata_atapi_polldsc(void *); 157 #endif 158 159 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 160 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 161 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 162 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 163 #if NATAPIBUS > 0 164 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 165 static void mvsata_bdma_start(struct mvsata_port *); 166 #endif 167 #endif 168 169 static int mvsata_nondma_handle(struct mvsata_port *); 170 171 static int mvsata_port_init(struct mvsata_hc *, int); 172 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 173 #ifndef MVSATA_WITHOUTDMA 174 static void mvsata_channel_recover(struct ata_channel *, int, uint32_t); 175 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 176 bus_dmamap_t *, size_t, int); 177 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 178 bus_dmamap_t, void *); 179 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 180 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 181 #endif 182 183 static void mvsata_hreset_port(struct mvsata_port *); 184 static void mvsata_reset_port(struct mvsata_port *); 185 static void mvsata_reset_hc(struct mvsata_hc *); 186 static uint32_t mvsata_softreset(struct mvsata_port *, int); 187 #ifndef MVSATA_WITHOUTDMA 188 static void mvsata_edma_reset_qptr(struct mvsata_port *); 189 static inline void mvsata_edma_enable(struct mvsata_port *); 190 static int mvsata_edma_disable(struct mvsata_port *, int, int); 191 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 192 193 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 194 struct ata_xfer *); 195 #endif 196 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 197 static void mvsata_fix_phy_gen1(struct mvsata_port *); 198 static void mvsata_devconn_gen1(struct mvsata_port *); 199 200 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 201 static void mvsata_fix_phy_gen2(struct mvsata_port *); 202 #ifndef MVSATA_WITHOUTDMA 203 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 204 struct ata_xfer *); 205 206 #ifdef MVSATA_DEBUG 207 static void mvsata_print_crqb(struct mvsata_port *, int); 208 static void mvsata_print_crpb(struct mvsata_port *, int); 209 static void mvsata_print_eprd(struct mvsata_port *, int); 210 #endif 211 212 static const struct ata_bustype mvsata_ata_bustype = { 213 SCSIPI_BUSTYPE_ATA, 214 mvsata_bio, 215 mvsata_reset_drive, 216 mvsata_reset_channel, 217 mvsata_exec_command, 218 ata_get_params, 219 mvsata_addref, 220 mvsata_delref, 221 mvsata_killpending, 222 mvsata_channel_recover, 223 }; 224 225 #if NATAPIBUS > 0 226 static const struct scsipi_bustype mvsata_atapi_bustype = { 227 SCSIPI_BUSTYPE_ATAPI, 228 atapi_scsipi_cmd, 229 atapi_interpret_sense, 230 atapi_print_addr, 231 mvsata_atapi_kill_pending, 232 NULL, 233 }; 234 #endif /* NATAPIBUS */ 235 #endif 236 237 static void 238 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 239 { 240 uint32_t ifctl; 241 242 KASSERT(pmpport < PMP_MAX_DRIVES); 243 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 244 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 245 panic("EDMA enabled"); 246 } 247 #endif 248 249 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 250 ifctl &= ~0xf; 251 ifctl |= pmpport; 252 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 253 } 254 255 int 256 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 257 int (*mvsata_sreset)(struct mvsata_softc *), 258 int (*mvsata_misc_reset)(struct mvsata_softc *), 259 int read_pre_amps) 260 { 261 struct mvsata_hc *mvhc; 262 struct mvsata_port *mvport; 263 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 264 void (*_fix_phy)(struct mvsata_port *) = NULL; 265 #ifndef MVSATA_WITHOUTDMA 266 void (*edma_setup_crqb) 267 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 268 #endif 269 int hc, port, channel; 270 271 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 272 (product->generation == gen1) ? "I" : 273 ((product->generation == gen2) ? "II" : "IIe"), 274 product->hc, product->port); 275 276 277 switch (product->generation) { 278 case gen1: 279 mvsata_sreset = NULL; 280 read_pre_amps = 1; /* MUST */ 281 read_preamps = mvsata_read_preamps_gen1; 282 _fix_phy = mvsata_fix_phy_gen1; 283 #ifndef MVSATA_WITHOUTDMA 284 edma_setup_crqb = mvsata_edma_setup_crqb; 285 #endif 286 break; 287 288 case gen2: 289 read_preamps = mvsata_read_preamps_gen2; 290 _fix_phy = mvsata_fix_phy_gen2; 291 #ifndef MVSATA_WITHOUTDMA 292 edma_setup_crqb = mvsata_edma_setup_crqb; 293 #endif 294 break; 295 296 case gen2e: 297 read_preamps = mvsata_read_preamps_gen2; 298 _fix_phy = mvsata_fix_phy_gen2; 299 #ifndef MVSATA_WITHOUTDMA 300 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 301 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 302 #endif 303 break; 304 } 305 306 sc->sc_gen = product->generation; 307 sc->sc_hc = product->hc; 308 sc->sc_port = product->port; 309 sc->sc_flags = product->flags; 310 311 #ifdef MVSATA_WITHOUTDMA 312 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 313 #else 314 sc->sc_edma_setup_crqb = edma_setup_crqb; 315 sc->sc_wdcdev.sc_atac.atac_cap |= 316 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 317 #endif 318 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 319 #ifdef MVSATA_WITHOUTDMA 320 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 321 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 322 #else 323 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 324 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 325 #endif 326 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 327 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 328 #ifndef MVSATA_WITHOUTDMA 329 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 330 #if NATAPIBUS > 0 331 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 332 #endif 333 #endif 334 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 335 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 336 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 337 338 sc->sc_wdc_regs = 339 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 340 M_DEVBUF, M_NOWAIT); 341 if (sc->sc_wdc_regs == NULL) { 342 aprint_error_dev(MVSATA_DEV(sc), 343 "can't allocate wdc regs memory\n"); 344 return ENOMEM; 345 } 346 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 347 348 for (hc = 0; hc < sc->sc_hc; hc++) { 349 mvhc = &sc->sc_hcs[hc]; 350 mvhc->hc = hc; 351 mvhc->hc_sc = sc; 352 mvhc->hc_iot = sc->sc_iot; 353 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 354 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 355 &mvhc->hc_ioh)) { 356 aprint_error_dev(MVSATA_DEV(sc), 357 "can't subregion SATAHC %d registers\n", hc); 358 continue; 359 } 360 361 for (port = 0; port < sc->sc_port; port++) 362 if (mvsata_port_init(mvhc, port) == 0) { 363 int pre_amps; 364 365 mvport = mvhc->hc_ports[port]; 366 pre_amps = read_pre_amps ? 367 read_preamps(mvport) : 0x00000720; 368 mvport->_fix_phy_param.pre_amps = pre_amps; 369 mvport->_fix_phy_param._fix_phy = _fix_phy; 370 371 if (!mvsata_sreset) 372 mvsata_reset_port(mvport); 373 } 374 375 if (!mvsata_sreset) 376 mvsata_reset_hc(mvhc); 377 } 378 if (mvsata_sreset) 379 mvsata_sreset(sc); 380 381 if (mvsata_misc_reset) 382 mvsata_misc_reset(sc); 383 384 for (hc = 0; hc < sc->sc_hc; hc++) 385 for (port = 0; port < sc->sc_port; port++) { 386 mvport = sc->sc_hcs[hc].hc_ports[port]; 387 if (mvport == NULL) 388 continue; 389 if (mvsata_sreset) 390 mvport->_fix_phy_param._fix_phy(mvport); 391 } 392 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 393 wdcattach(sc->sc_ata_channels[channel]); 394 395 return 0; 396 } 397 398 int 399 mvsata_intr(struct mvsata_hc *mvhc) 400 { 401 struct mvsata_softc *sc = mvhc->hc_sc; 402 struct mvsata_port *mvport; 403 uint32_t cause; 404 int port, handled = 0; 405 406 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 407 408 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 409 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 410 411 if (cause & SATAHC_IC_SAINTCOAL) 412 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 413 cause &= ~SATAHC_IC_SAINTCOAL; 414 415 for (port = 0; port < sc->sc_port; port++) { 416 mvport = mvhc->hc_ports[port]; 417 418 if (cause & SATAHC_IC_DONE(port)) { 419 #ifndef MVSATA_WITHOUTDMA 420 handled = mvsata_edma_handle(mvport, NULL); 421 #endif 422 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 423 ~SATAHC_IC_DONE(port)); 424 } 425 426 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 427 (void) mvsata_nondma_handle(mvport); 428 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 429 ~SATAHC_IC_SADEVINTERRUPT(port)); 430 handled = 1; 431 } 432 } 433 434 return handled; 435 } 436 437 static int 438 mvsata_nondma_handle(struct mvsata_port *mvport) 439 { 440 struct ata_channel *chp = &mvport->port_ata_channel; 441 struct ata_xfer *xfer; 442 int ret; 443 444 /* 445 * The chip doesn't support several pending non-DMA commands, 446 * and the ata middle layer never issues several non-NCQ commands, 447 * so there must be exactly one active command at this moment. 448 */ 449 xfer = ata_queue_get_active_xfer(chp); 450 if (xfer == NULL) { 451 /* Can happen after error recovery, ignore */ 452 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 453 ("%s:%d: %s: intr without xfer\n", 454 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 455 __func__)); 456 return 0; 457 } 458 459 ret = xfer->ops->c_intr(chp, xfer, 1); 460 return (ret); 461 } 462 463 int 464 mvsata_error(struct mvsata_port *mvport) 465 { 466 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 467 uint32_t cause; 468 469 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 470 /* 471 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 472 * in EDMA_IEC. 473 */ 474 if (cause & EDMA_IE_SERRINT) { 475 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 476 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 477 } 478 if (cause & EDMA_IE_ETRANSINT) { 479 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 480 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 481 } 482 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 483 484 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 485 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 486 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 487 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 488 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 489 490 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 491 if (!cause) 492 return 0; 493 494 if (cause & EDMA_IE_EDEVDIS) { 495 aprint_normal("%s:%d:%d: device disconnect\n", 496 device_xname(MVSATA_DEV2(mvport)), 497 mvport->port_hc->hc, mvport->port); 498 } 499 if (cause & EDMA_IE_EDEVCON) { 500 if (sc->sc_gen == gen1) 501 mvsata_devconn_gen1(mvport); 502 503 DPRINTF(DEBUG_INTR, (" device connected\n")); 504 } 505 506 #ifndef MVSATA_WITHOUTDMA 507 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 508 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 509 switch (mvport->port_edmamode_curr) { 510 case dma: 511 case queued: 512 case ncq: 513 mvsata_edma_reset_qptr(mvport); 514 mvsata_edma_enable(mvport); 515 if (cause & EDMA_IE_EDEVERR) 516 break; 517 518 /* FALLTHROUGH */ 519 520 case nodma: 521 default: 522 aprint_error( 523 "%s:%d:%d: EDMA self disable happen 0x%x\n", 524 device_xname(MVSATA_DEV2(mvport)), 525 mvport->port_hc->hc, mvport->port, cause); 526 break; 527 } 528 } 529 #endif 530 if (cause & EDMA_IE_ETRANSINT) { 531 /* hot plug the Port Multiplier */ 532 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 533 device_xname(MVSATA_DEV2(mvport)), 534 mvport->port_hc->hc, mvport->port); 535 } 536 if (cause & EDMA_IE_EDEVERR) { 537 struct ata_channel *chp = &mvport->port_ata_channel; 538 539 aprint_error("%s:%d:%d: device error, recovering\n", 540 device_xname(MVSATA_DEV2(mvport)), 541 mvport->port_hc->hc, mvport->port); 542 543 ata_channel_lock(chp); 544 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, 545 ATACH_ERR_ST(0, WDCS_ERR)); 546 ata_channel_unlock(chp); 547 } 548 549 return 1; 550 } 551 552 #ifndef MVSATA_WITHOUTDMA 553 static void 554 mvsata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 555 { 556 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 557 int drive; 558 559 ata_channel_lock_owned(chp); 560 561 if (chp->ch_ndrives > PMP_PORT_CTL) { 562 /* Get PM port number for the device in error. This device 563 * doesn't seem to have dedicated register for this, so just 564 * assume last selected port was the one. */ 565 /* XXX FIS-based switching */ 566 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 567 } else 568 drive = 0; 569 570 /* 571 * Controller doesn't need any special action. Simply execute 572 * READ LOG EXT for NCQ to unblock device processing, then continue 573 * as if nothing happened. 574 */ 575 576 ata_recovery_resume(chp, drive, tfd, AT_POLL); 577 578 /* Drive unblocked, back to normal operation */ 579 return; 580 } 581 #endif /* !MVSATA_WITHOUTDMA */ 582 583 /* 584 * ATA callback entry points 585 */ 586 587 static void 588 mvsata_probe_drive(struct ata_channel *chp) 589 { 590 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 591 uint32_t sstat, sig; 592 593 ata_channel_lock(chp); 594 595 sstat = sata_reset_interface(chp, mvport->port_iot, 596 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 597 switch (sstat) { 598 case SStatus_DET_DEV: 599 mvsata_pmp_select(mvport, PMP_PORT_CTL); 600 sig = mvsata_softreset(mvport, AT_WAIT); 601 sata_interpret_sig(chp, 0, sig); 602 break; 603 default: 604 break; 605 } 606 607 ata_channel_unlock(chp); 608 } 609 610 #ifndef MVSATA_WITHOUTDMA 611 static void 612 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 613 { 614 struct ata_channel *chp = drvp->chnl_softc; 615 struct mvsata_port *mvport = (struct mvsata_port *)chp; 616 uint32_t edma_c; 617 uint32_t sig; 618 619 ata_channel_lock_owned(chp); 620 621 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 622 623 DPRINTF(DEBUG_FUNCS, 624 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 625 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 626 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 627 628 if (edma_c & EDMA_CMD_EENEDMA) 629 mvsata_edma_disable(mvport, 10000, flags); 630 631 mvsata_pmp_select(mvport, drvp->drive); 632 633 sig = mvsata_softreset(mvport, flags); 634 635 if (sigp) 636 *sigp = sig; 637 638 if (edma_c & EDMA_CMD_EENEDMA) { 639 mvsata_edma_reset_qptr(mvport); 640 mvsata_edma_enable(mvport); 641 } 642 } 643 644 static void 645 mvsata_reset_channel(struct ata_channel *chp, int flags) 646 { 647 struct mvsata_port *mvport = (struct mvsata_port *)chp; 648 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 649 uint32_t sstat, ctrl; 650 651 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 652 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 653 654 ata_channel_lock_owned(chp); 655 656 mvsata_hreset_port(mvport); 657 sstat = sata_reset_interface(chp, mvport->port_iot, 658 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 659 660 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 661 sc->sc_gen != gen1) { 662 /* Downgrade to GenI */ 663 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 664 SControl_DET_DISABLE; 665 666 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 667 668 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 669 ctrl &= ~(1 << 17); /* Disable GenII */ 670 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 671 672 mvsata_hreset_port(mvport); 673 sata_reset_interface(chp, mvport->port_iot, 674 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 675 flags); 676 } 677 678 ata_kill_active(chp, KILL_RESET, flags); 679 680 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 681 mvsata_edma_reset_qptr(mvport); 682 mvsata_edma_enable(mvport); 683 } 684 685 static int 686 mvsata_addref(struct ata_drive_datas *drvp) 687 { 688 689 return 0; 690 } 691 692 static void 693 mvsata_delref(struct ata_drive_datas *drvp) 694 { 695 696 return; 697 } 698 699 static void 700 mvsata_killpending(struct ata_drive_datas *drvp) 701 { 702 703 return; 704 } 705 706 #if NATAPIBUS > 0 707 static void 708 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 709 { 710 struct ata_channel *chp = ata_sc->sc_chan; 711 struct atac_softc *atac = chp->ch_atac; 712 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 713 struct scsipi_channel *chan = &chp->ch_atapi_channel; 714 715 /* 716 * Fill in the scsipi_adapter. 717 */ 718 adapt->adapt_dev = atac->atac_dev; 719 adapt->adapt_nchannels = atac->atac_nchannels; 720 adapt->adapt_request = mvsata_atapi_scsipi_request; 721 adapt->adapt_minphys = mvsata_atapi_minphys; 722 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 723 724 /* 725 * Fill in the scsipi_channel. 726 */ 727 memset(chan, 0, sizeof(*chan)); 728 chan->chan_adapter = adapt; 729 chan->chan_bustype = &mvsata_atapi_bustype; 730 chan->chan_channel = chp->ch_channel; 731 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 732 chan->chan_openings = 1; 733 chan->chan_max_periph = 1; 734 chan->chan_ntargets = 1; 735 chan->chan_nluns = 1; 736 737 chp->atapibus = 738 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 739 } 740 741 static void 742 mvsata_atapi_minphys(struct buf *bp) 743 { 744 745 if (bp->b_bcount > MAXPHYS) 746 bp->b_bcount = MAXPHYS; 747 minphys(bp); 748 } 749 750 static void 751 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 752 { 753 struct scsipi_channel *chan = sc->sc_channel; 754 struct scsipi_periph *periph; 755 struct ataparams ids; 756 struct ataparams *id = &ids; 757 struct mvsata_softc *mvc = 758 device_private(chan->chan_adapter->adapt_dev); 759 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 760 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 761 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 762 struct scsipibus_attach_args sa; 763 char serial_number[21], model[41], firmware_revision[9]; 764 int s; 765 766 /* skip if already attached */ 767 if (scsipi_lookup_periph(chan, target, 0) != NULL) 768 return; 769 770 /* if no ATAPI device detected at attach time, skip */ 771 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 772 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 773 " drive %d not present\n", 774 device_xname(atac->atac_dev), chp->ch_channel, target)); 775 return; 776 } 777 778 /* Some ATAPI devices need a bit more time after software reset. */ 779 delay(5000); 780 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 781 #ifdef ATAPI_DEBUG_PROBE 782 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 783 device_xname(sc->sc_dev), target, 784 id->atap_config & ATAPI_CFG_CMD_MASK, 785 id->atap_config & ATAPI_CFG_DRQ_MASK); 786 #endif 787 periph = scsipi_alloc_periph(M_NOWAIT); 788 if (periph == NULL) { 789 aprint_error_dev(atac->atac_dev, 790 "unable to allocate periph" 791 " for channel %d drive %d\n", 792 chp->ch_channel, target); 793 return; 794 } 795 periph->periph_dev = NULL; 796 periph->periph_channel = chan; 797 periph->periph_switch = &atapi_probe_periphsw; 798 periph->periph_target = target; 799 periph->periph_lun = 0; 800 periph->periph_quirks = PQUIRK_ONLYBIG; 801 802 #ifdef SCSIPI_DEBUG 803 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 804 SCSIPI_DEBUG_TARGET == target) 805 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 806 #endif 807 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 808 if (id->atap_config & ATAPI_CFG_REMOV) 809 periph->periph_flags |= PERIPH_REMOVABLE; 810 if (periph->periph_type == T_SEQUENTIAL) { 811 s = splbio(); 812 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 813 splx(s); 814 } 815 816 sa.sa_periph = periph; 817 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 818 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 819 T_REMOV : T_FIXED; 820 strnvisx(model, sizeof(model), id->atap_model, 40, 821 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 822 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 823 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 824 strnvisx(firmware_revision, sizeof(firmware_revision), 825 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 826 sa.sa_inqbuf.vendor = model; 827 sa.sa_inqbuf.product = serial_number; 828 sa.sa_inqbuf.revision = firmware_revision; 829 830 /* 831 * Determine the operating mode capabilities of the device. 832 */ 833 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 834 periph->periph_cap |= PERIPH_CAP_CMD16; 835 /* XXX This is gross. */ 836 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 837 838 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 839 840 if (drvp->drv_softc) 841 ata_probe_caps(drvp); 842 else { 843 s = splbio(); 844 drvp->drive_type = ATA_DRIVET_NONE; 845 splx(s); 846 } 847 } else { 848 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 849 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 850 device_xname(atac->atac_dev), chp->ch_channel, target)); 851 s = splbio(); 852 drvp->drive_type = ATA_DRIVET_NONE; 853 splx(s); 854 } 855 } 856 857 /* 858 * Kill off all pending xfers for a periph. 859 * 860 * Must be called at splbio(). 861 */ 862 static void 863 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 864 { 865 struct atac_softc *atac = 866 device_private(periph->periph_channel->chan_adapter->adapt_dev); 867 struct ata_channel *chp = 868 atac->atac_channels[periph->periph_channel->chan_channel]; 869 870 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 871 } 872 #endif /* NATAPIBUS > 0 */ 873 #endif /* MVSATA_WITHOUTDMA */ 874 875 876 /* 877 * mvsata_setup_channel() 878 * Setup EDMA registers and prepare/purge DMA resources. 879 * We assuming already stopped the EDMA. 880 */ 881 static void 882 mvsata_setup_channel(struct ata_channel *chp) 883 { 884 #ifndef MVSATA_WITHOUTDMA 885 struct mvsata_port *mvport = (struct mvsata_port *)chp; 886 struct ata_drive_datas *drvp; 887 int drive, s; 888 uint32_t edma_mode = nodma; 889 int i; 890 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 891 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 892 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 893 894 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 895 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 896 897 for (drive = 0; drive < chp->ch_ndrives; drive++) { 898 drvp = &chp->ch_drive[drive]; 899 900 /* If no drive, skip */ 901 if (drvp->drive_type == ATA_DRIVET_NONE) 902 continue; 903 904 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 905 /* use Ultra/DMA */ 906 s = splbio(); 907 drvp->drive_flags &= ~ATA_DRIVE_DMA; 908 splx(s); 909 } 910 911 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 912 if (drvp->drive_flags & ATA_DRIVE_NCQ) 913 edma_mode = ncq; 914 else if (drvp->drive_type == ATA_DRIVET_ATA) 915 edma_mode = dma; 916 } 917 } 918 919 DPRINTF(DEBUG_FUNCS, 920 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 921 922 if (edma_mode == nodma) { 923 no_edma: 924 if (mvport->port_crqb != NULL) 925 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 926 mvport->port_crqb_dmamap, mvport->port_crqb); 927 if (mvport->port_crpb != NULL) 928 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 929 mvport->port_crpb_dmamap, mvport->port_crpb); 930 if (mvport->port_eprd != NULL) 931 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 932 mvport->port_eprd_dmamap, mvport->port_eprd); 933 934 return; 935 } 936 937 if (mvport->port_crqb == NULL) 938 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 939 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 940 if (mvport->port_crpb == NULL) 941 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 942 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 943 if (mvport->port_eprd == NULL) { 944 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 945 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 946 1); 947 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 948 mvport->port_reqtbl[i].eprd_offset = 949 i * MVSATA_EPRD_MAX_SIZE; 950 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 951 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 952 } 953 } 954 955 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 956 mvport->port_eprd == NULL) { 957 aprint_error_dev(MVSATA_DEV2(mvport), 958 "channel %d: can't use EDMA\n", chp->ch_channel); 959 s = splbio(); 960 for (drive = 0; drive < chp->ch_ndrives; drive++) { 961 drvp = &chp->ch_drive[drive]; 962 963 /* If no drive, skip */ 964 if (drvp->drive_type == ATA_DRIVET_NONE) 965 continue; 966 967 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 968 } 969 splx(s); 970 goto no_edma; 971 } 972 973 mvsata_edma_config(mvport, edma_mode); 974 mvsata_edma_reset_qptr(mvport); 975 mvsata_edma_enable(mvport); 976 #endif 977 } 978 979 #ifndef MVSATA_WITHOUTDMA 980 static const struct ata_xfer_ops mvsata_bio_xfer_ops = { 981 .c_start = mvsata_bio_start, 982 .c_intr = mvsata_bio_intr, 983 .c_poll = mvsata_bio_poll, 984 .c_abort = mvsata_bio_done, 985 .c_kill_xfer = mvsata_bio_kill_xfer, 986 }; 987 988 static int 989 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 990 { 991 struct ata_channel *chp = drvp->chnl_softc; 992 struct atac_softc *atac = chp->ch_atac; 993 struct ata_bio *ata_bio = &xfer->c_bio; 994 995 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 996 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 997 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 998 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 999 1000 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1001 ata_bio->flags |= ATA_POLL; 1002 if (ata_bio->flags & ATA_POLL) 1003 xfer->c_flags |= C_POLL; 1004 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1005 (ata_bio->flags & ATA_SINGLE) == 0) 1006 xfer->c_flags |= C_DMA; 1007 xfer->c_drive = drvp->drive; 1008 xfer->c_databuf = ata_bio->databuf; 1009 xfer->c_bcount = ata_bio->bcount; 1010 xfer->ops = &mvsata_bio_xfer_ops; 1011 ata_exec_xfer(chp, xfer); 1012 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1013 } 1014 1015 static int 1016 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1017 { 1018 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1019 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1020 struct atac_softc *atac = chp->ch_atac; 1021 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1022 struct ata_bio *ata_bio = &xfer->c_bio; 1023 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1024 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1025 u_int16_t cyl; 1026 u_int8_t head, sect, cmd = 0; 1027 int nblks, error, tfd; 1028 1029 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1030 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1031 1032 ata_channel_lock_owned(chp); 1033 1034 if (xfer->c_flags & C_DMA) 1035 if (drvp->n_xfers <= NXFER) 1036 drvp->n_xfers++; 1037 1038 /* 1039 * 1040 * When starting a multi-sector transfer, or doing single-sector 1041 * transfers... 1042 */ 1043 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1044 if (ata_bio->flags & ATA_SINGLE) 1045 nblks = 1; 1046 else 1047 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1048 /* Check for bad sectors and adjust transfer, if necessary. */ 1049 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1050 long blkdiff; 1051 int i; 1052 1053 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1054 i++) { 1055 blkdiff -= ata_bio->blkno; 1056 if (blkdiff < 0) 1057 continue; 1058 if (blkdiff == 0) 1059 /* Replace current block of transfer. */ 1060 ata_bio->blkno = 1061 drvp->lp->d_secperunit - 1062 drvp->lp->d_nsectors - i - 1; 1063 if (blkdiff < nblks) { 1064 /* Bad block inside transfer. */ 1065 ata_bio->flags |= ATA_SINGLE; 1066 nblks = 1; 1067 } 1068 break; 1069 } 1070 /* Transfer is okay now. */ 1071 } 1072 if (xfer->c_flags & C_DMA) { 1073 enum mvsata_edmamode dmamode; 1074 1075 ata_bio->nblks = nblks; 1076 ata_bio->nbytes = xfer->c_bcount; 1077 1078 /* switch to appropriate dma mode if necessary */ 1079 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1080 if (mvport->port_edmamode_curr != dmamode) 1081 mvsata_edma_config(mvport, dmamode); 1082 1083 if (xfer->c_flags & C_POLL) 1084 sc->sc_enable_intr(mvport, 0 /*off*/); 1085 error = mvsata_edma_enqueue(mvport, xfer); 1086 if (error) { 1087 if (error == EINVAL) { 1088 /* 1089 * We can't do DMA on this transfer 1090 * for some reason. Fall back to 1091 * PIO. 1092 */ 1093 xfer->c_flags &= ~C_DMA; 1094 error = 0; 1095 goto do_pio; 1096 } 1097 if (error == EBUSY) { 1098 aprint_error_dev(atac->atac_dev, 1099 "channel %d: EDMA Queue full\n", 1100 chp->ch_channel); 1101 /* 1102 * XXX: Perhaps, after it waits for 1103 * a while, it is necessary to call 1104 * bio_start again. 1105 */ 1106 } 1107 ata_bio->error = ERR_DMA; 1108 ata_bio->r_error = 0; 1109 return ATASTART_ABORT; 1110 } 1111 chp->ch_flags |= ATACH_DMA_WAIT; 1112 /* start timeout machinery */ 1113 if ((xfer->c_flags & C_POLL) == 0) 1114 callout_reset(&chp->c_timo_callout, 1115 mstohz(ATA_DELAY), ata_timeout, chp); 1116 /* wait for irq */ 1117 goto intr; 1118 } /* else not DMA */ 1119 do_pio: 1120 if (ata_bio->flags & ATA_LBA48) { 1121 sect = 0; 1122 cyl = 0; 1123 head = 0; 1124 } else if (ata_bio->flags & ATA_LBA) { 1125 sect = (ata_bio->blkno >> 0) & 0xff; 1126 cyl = (ata_bio->blkno >> 8) & 0xffff; 1127 head = (ata_bio->blkno >> 24) & 0x0f; 1128 head |= WDSD_LBA; 1129 } else { 1130 int blkno = ata_bio->blkno; 1131 sect = blkno % drvp->lp->d_nsectors; 1132 sect++; /* Sectors begin with 1, not 0. */ 1133 blkno /= drvp->lp->d_nsectors; 1134 head = blkno % drvp->lp->d_ntracks; 1135 blkno /= drvp->lp->d_ntracks; 1136 cyl = blkno; 1137 head |= WDSD_CHS; 1138 } 1139 ata_bio->nblks = uimin(nblks, drvp->multi); 1140 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1141 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1142 if (ata_bio->nblks > 1) 1143 cmd = (ata_bio->flags & ATA_READ) ? 1144 WDCC_READMULTI : WDCC_WRITEMULTI; 1145 else 1146 cmd = (ata_bio->flags & ATA_READ) ? 1147 WDCC_READ : WDCC_WRITE; 1148 1149 /* EDMA disable, if enabled this channel. */ 1150 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1151 if (mvport->port_edmamode_curr != nodma) 1152 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1153 1154 mvsata_pmp_select(mvport, xfer->c_drive); 1155 1156 /* Do control operations specially. */ 1157 if (__predict_false(drvp->state < READY)) { 1158 /* 1159 * Actually, we want to be careful not to mess with 1160 * the control state if the device is currently busy, 1161 * but we can assume that we never get to this point 1162 * if that's the case. 1163 */ 1164 /* 1165 * If it's not a polled command, we need the kernel 1166 * thread 1167 */ 1168 if ((xfer->c_flags & C_POLL) == 0 && 1169 (chp->ch_flags & ATACH_TH_RUN) == 0) { 1170 return ATASTART_TH; 1171 } 1172 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1173 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1174 return ATASTART_ABORT; 1175 } 1176 } 1177 1178 /* Initiate command! */ 1179 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1180 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1181 case WDCWAIT_OK: 1182 break; 1183 case WDCWAIT_TOUT: 1184 goto timeout; 1185 case WDCWAIT_THR: 1186 return ATASTART_TH; 1187 } 1188 if (ata_bio->flags & ATA_LBA48) 1189 wdccommandext(chp, 0, atacmd_to48(cmd), 1190 ata_bio->blkno, nblks, 0, WDSD_LBA); 1191 else 1192 wdccommand(chp, 0, cmd, cyl, 1193 head, sect, nblks, 1194 (drvp->lp->d_type == DKTYPE_ST506) ? 1195 drvp->lp->d_precompcyl / 4 : 0); 1196 1197 /* start timeout machinery */ 1198 if ((xfer->c_flags & C_POLL) == 0) 1199 callout_reset(&chp->c_timo_callout, 1200 mstohz(ATA_DELAY), wdctimeout, chp); 1201 } else if (ata_bio->nblks > 1) { 1202 /* The number of blocks in the last stretch may be smaller. */ 1203 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1204 if (ata_bio->nblks > nblks) { 1205 ata_bio->nblks = nblks; 1206 ata_bio->nbytes = xfer->c_bcount; 1207 } 1208 } 1209 /* If this was a write and not using DMA, push the data. */ 1210 if ((ata_bio->flags & ATA_READ) == 0) { 1211 /* 1212 * we have to busy-wait here, we can't rely on running in 1213 * thread context. 1214 */ 1215 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1216 aprint_error_dev(atac->atac_dev, 1217 "channel %d: drive %d timeout waiting for DRQ," 1218 " st=0x%02x, err=0x%02x\n", 1219 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1220 ATACH_ERR(tfd)); 1221 ata_bio->error = TIMEOUT; 1222 return ATASTART_ABORT; 1223 } 1224 if (ATACH_ST(tfd) & WDCS_ERR) { 1225 ata_bio->error = ERROR; 1226 ata_bio->r_error = ATACH_ERR(tfd); 1227 mvsata_bio_done(chp, xfer); 1228 return ATASTART_ABORT; 1229 } 1230 1231 wdc->dataout_pio(chp, drvp->drive_flags, 1232 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1233 } 1234 1235 intr: 1236 KASSERTMSG(((xfer->c_flags & C_DMA) != 0) 1237 == (mvport->port_edmamode_curr != nodma), 1238 "DMA mode mismatch: flags %x vs edmamode %d != %d", 1239 xfer->c_flags, mvport->port_edmamode_curr, nodma); 1240 1241 /* Wait for IRQ (either real or polled) */ 1242 if ((ata_bio->flags & ATA_POLL) != 0) 1243 return ATASTART_POLL; 1244 else 1245 return ATASTART_STARTED; 1246 1247 timeout: 1248 aprint_error_dev(atac->atac_dev, 1249 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1250 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1251 ata_bio->error = TIMEOUT; 1252 return ATASTART_ABORT; 1253 } 1254 1255 static void 1256 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1257 { 1258 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1259 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1260 1261 /* Wait for at last 400ns for status bit to be valid */ 1262 delay(1); 1263 if (chp->ch_flags & ATACH_DMA_WAIT) { 1264 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1265 sc->sc_enable_intr(mvport, 1 /*on*/); 1266 chp->ch_flags &= ~ATACH_DMA_WAIT; 1267 } 1268 1269 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1270 KASSERT(xfer->c_flags & C_TIMEOU); 1271 mvsata_bio_intr(chp, xfer, 0); 1272 } 1273 } 1274 1275 static int 1276 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int intr_arg) 1277 { 1278 struct atac_softc *atac = chp->ch_atac; 1279 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1280 struct ata_bio *ata_bio = &xfer->c_bio; 1281 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1282 int irq = ISSET(xfer->c_flags, (C_POLL|C_TIMEOU)) ? 0 : 1; 1283 int tfd = 0; 1284 1285 if (ISSET(xfer->c_flags, C_DMA|C_RECOVERED) && irq) { 1286 /* Invoked via mvsata_edma_handle() or recovery */ 1287 tfd = intr_arg; 1288 1289 if (tfd > 0 && ata_bio->error == NOERROR) { 1290 if (ATACH_ST(tfd) & WDCS_ERR) 1291 ata_bio->error = ERROR; 1292 if (ATACH_ST(tfd) & WDCS_BSY) 1293 ata_bio->error = TIMEOUT; 1294 ata_bio->r_error = ATACH_ERR(tfd); 1295 } 1296 } 1297 1298 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1299 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1300 xfer->c_drive)); 1301 1302 /* Cleanup EDMA if invoked from wdctimeout()/ata_timeout() */ 1303 if (ISSET(xfer->c_flags, C_TIMEOU) && ISSET(xfer->c_flags, C_DMA) 1304 && !ISSET(xfer->c_flags, C_POLL)) { 1305 mvsata_edma_rqq_remove((struct mvsata_port *)chp, xfer); 1306 } 1307 1308 ata_channel_lock(chp); 1309 1310 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1311 1312 /* 1313 * If we missed an interrupt transfer, reset and restart. 1314 * Don't try to continue transfer, we may have missed cycles. 1315 */ 1316 if (xfer->c_flags & C_TIMEOU) { 1317 ata_bio->error = TIMEOUT; 1318 ata_channel_unlock(chp); 1319 mvsata_bio_done(chp, xfer); 1320 return 1; 1321 } 1322 1323 /* Is it not a transfer, but a control operation? */ 1324 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1325 aprint_error_dev(atac->atac_dev, 1326 "channel %d: drive %d bad state %d in %s\n", 1327 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1328 panic("%s: bad state", __func__); 1329 } 1330 1331 /* Ack interrupt done by wdc_wait_for_unbusy */ 1332 if (!(xfer->c_flags & C_DMA) && 1333 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1334 == WDCWAIT_TOUT)) { 1335 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1336 ata_channel_unlock(chp); 1337 return 0; /* IRQ was not for us */ 1338 } 1339 aprint_error_dev(atac->atac_dev, 1340 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1341 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1342 xfer->c_skip); 1343 ata_bio->error = TIMEOUT; 1344 ata_channel_unlock(chp); 1345 mvsata_bio_done(chp, xfer); 1346 return 1; 1347 } 1348 1349 if (xfer->c_flags & C_DMA) { 1350 if (ata_bio->error == NOERROR) 1351 goto end; 1352 if (ata_bio->error == ERR_DMA) { 1353 ata_channel_unlock(chp); 1354 ata_dmaerr(drvp, 1355 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1356 goto err; 1357 } 1358 } 1359 1360 /* if we had an error, end */ 1361 if (ata_bio->error != NOERROR) { 1362 ata_channel_unlock(chp); 1363 err: 1364 mvsata_bio_done(chp, xfer); 1365 return 1; 1366 } 1367 1368 /* If this was a read and not using DMA, fetch the data. */ 1369 if ((ata_bio->flags & ATA_READ) != 0) { 1370 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1371 aprint_error_dev(atac->atac_dev, 1372 "channel %d: drive %d read intr before drq\n", 1373 chp->ch_channel, xfer->c_drive); 1374 ata_bio->error = TIMEOUT; 1375 ata_channel_unlock(chp); 1376 mvsata_bio_done(chp, xfer); 1377 return 1; 1378 } 1379 wdc->datain_pio(chp, drvp->drive_flags, 1380 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1381 } 1382 1383 end: 1384 ata_bio->blkno += ata_bio->nblks; 1385 ata_bio->blkdone += ata_bio->nblks; 1386 xfer->c_skip += ata_bio->nbytes; 1387 xfer->c_bcount -= ata_bio->nbytes; 1388 1389 /* See if this transfer is complete. */ 1390 if (xfer->c_bcount > 0) { 1391 if ((ata_bio->flags & ATA_POLL) == 0) { 1392 /* Start the next operation */ 1393 ata_xfer_start(xfer); 1394 } else { 1395 /* Let mvsata_bio_start do the loop */ 1396 } 1397 ata_channel_unlock(chp); 1398 } else { /* Done with this transfer */ 1399 ata_bio->error = NOERROR; 1400 ata_channel_unlock(chp); 1401 mvsata_bio_done(chp, xfer); 1402 } 1403 return 1; 1404 } 1405 1406 static void 1407 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1408 { 1409 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1410 struct atac_softc *atac = chp->ch_atac; 1411 struct ata_bio *ata_bio = &xfer->c_bio; 1412 int drive = xfer->c_drive; 1413 bool deactivate = true; 1414 1415 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1416 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1417 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1418 1419 /* EDMA restart, if enabled */ 1420 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1421 mvsata_edma_reset_qptr(mvport); 1422 mvsata_edma_enable(mvport); 1423 } 1424 1425 ata_bio->flags |= ATA_ITSDONE; 1426 switch (reason) { 1427 case KILL_GONE_INACTIVE: 1428 deactivate = false; 1429 /* FALLTHROUGH */ 1430 case KILL_GONE: 1431 ata_bio->error = ERR_NODEV; 1432 break; 1433 case KILL_RESET: 1434 ata_bio->error = ERR_RESET; 1435 break; 1436 case KILL_REQUEUE: 1437 ata_bio->error = REQUEUE; 1438 break; 1439 default: 1440 aprint_error_dev(atac->atac_dev, 1441 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1442 panic("mvsata_bio_kill_xfer"); 1443 } 1444 ata_bio->r_error = WDCE_ABRT; 1445 1446 if (deactivate) 1447 ata_deactivate_xfer(chp, xfer); 1448 1449 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1450 } 1451 1452 static void 1453 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1454 { 1455 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1456 struct ata_bio *ata_bio = &xfer->c_bio; 1457 int drive = xfer->c_drive; 1458 bool iserror = (ata_bio->error != NOERROR); 1459 1460 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1461 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1462 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1463 (u_int)xfer->c_flags)); 1464 1465 /* EDMA restart, if enabled */ 1466 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1467 mvsata_edma_reset_qptr(mvport); 1468 mvsata_edma_enable(mvport); 1469 } 1470 1471 if (ata_waitdrain_xfer_check(chp, xfer)) 1472 return; 1473 1474 /* feed back residual bcount to our caller */ 1475 ata_bio->bcount = xfer->c_bcount; 1476 1477 /* mark controller inactive and free xfer */ 1478 ata_deactivate_xfer(chp, xfer); 1479 1480 ata_bio->flags |= ATA_ITSDONE; 1481 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1482 if (!iserror) 1483 atastart(chp); 1484 } 1485 1486 static int 1487 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1488 int flags) 1489 { 1490 struct ata_channel *chp = &mvport->port_ata_channel; 1491 struct atac_softc *atac = chp->ch_atac; 1492 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1493 const char *errstring; 1494 int tfd; 1495 1496 flags |= AT_POLL; /* XXX */ 1497 1498 ata_channel_lock_owned(chp); 1499 1500 /* 1501 * disable interrupts, all commands here should be quick 1502 * enough to be able to poll, and we don't go here that often 1503 */ 1504 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1505 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1506 DELAY(10); 1507 errstring = "wait"; 1508 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1509 goto ctrltimeout; 1510 wdccommandshort(chp, 0, WDCC_RECAL); 1511 /* Wait for at least 400ns for status bit to be valid */ 1512 DELAY(1); 1513 errstring = "recal"; 1514 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1515 goto ctrltimeout; 1516 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1517 goto ctrlerror; 1518 /* Don't try to set modes if controller can't be adjusted */ 1519 if (atac->atac_set_modes == NULL) 1520 goto geometry; 1521 /* Also don't try if the drive didn't report its mode */ 1522 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1523 goto geometry; 1524 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1525 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1526 errstring = "piomode-bio"; 1527 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1528 goto ctrltimeout; 1529 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1530 goto ctrlerror; 1531 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1532 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1533 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1534 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1535 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1536 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1537 else 1538 goto geometry; 1539 errstring = "dmamode-bio"; 1540 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1541 goto ctrltimeout; 1542 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1543 goto ctrlerror; 1544 geometry: 1545 if (ata_bio->flags & ATA_LBA) 1546 goto multimode; 1547 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1548 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1549 (drvp->lp->d_type == DKTYPE_ST506) ? 1550 drvp->lp->d_precompcyl / 4 : 0); 1551 errstring = "geometry"; 1552 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1553 goto ctrltimeout; 1554 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1555 goto ctrlerror; 1556 multimode: 1557 if (drvp->multi == 1) 1558 goto ready; 1559 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1560 errstring = "setmulti"; 1561 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1562 goto ctrltimeout; 1563 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1564 goto ctrlerror; 1565 ready: 1566 drvp->state = READY; 1567 /* 1568 * The drive is usable now 1569 */ 1570 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1571 delay(10); /* some drives need a little delay here */ 1572 return 0; 1573 1574 ctrltimeout: 1575 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1576 chp->ch_channel, drive, errstring); 1577 ata_bio->error = TIMEOUT; 1578 goto ctrldone; 1579 ctrlerror: 1580 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1581 chp->ch_channel, drive, errstring); 1582 if (ATACH_ST(tfd) & WDCS_DWF) { 1583 aprint_error("drive fault\n"); 1584 ata_bio->error = ERR_DF; 1585 } else { 1586 ata_bio->r_error = ATACH_ERR(tfd); 1587 ata_bio->error = ERROR; 1588 aprint_error("error (%x)\n", ata_bio->r_error); 1589 } 1590 ctrldone: 1591 drvp->state = 0; 1592 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1593 return -1; 1594 } 1595 1596 static const struct ata_xfer_ops mvsata_wdc_cmd_xfer_ops = { 1597 .c_start = mvsata_wdc_cmd_start, 1598 .c_intr = mvsata_wdc_cmd_intr, 1599 .c_poll = mvsata_wdc_cmd_poll, 1600 .c_abort = mvsata_wdc_cmd_done, 1601 .c_kill_xfer = mvsata_wdc_cmd_kill_xfer, 1602 }; 1603 1604 static int 1605 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1606 { 1607 struct ata_channel *chp = drvp->chnl_softc; 1608 struct ata_command *ata_c = &xfer->c_ata_c; 1609 int rv, s; 1610 1611 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1612 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1613 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1614 " r_device=0x%02x, r_command=0x%02x\n", 1615 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1616 chp->ch_channel, 1617 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1618 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1619 1620 if (ata_c->flags & AT_POLL) 1621 xfer->c_flags |= C_POLL; 1622 if (ata_c->flags & AT_WAIT) 1623 xfer->c_flags |= C_WAIT; 1624 xfer->c_drive = drvp->drive; 1625 xfer->c_databuf = ata_c->data; 1626 xfer->c_bcount = ata_c->bcount; 1627 xfer->ops = &mvsata_wdc_cmd_xfer_ops; 1628 s = splbio(); 1629 ata_exec_xfer(chp, xfer); 1630 #ifdef DIAGNOSTIC 1631 if ((ata_c->flags & AT_POLL) != 0 && 1632 (ata_c->flags & AT_DONE) == 0) 1633 panic("mvsata_exec_command: polled command not done"); 1634 #endif 1635 if (ata_c->flags & AT_DONE) 1636 rv = ATACMD_COMPLETE; 1637 else { 1638 if (ata_c->flags & AT_WAIT) { 1639 ata_wait_cmd(chp, xfer); 1640 rv = ATACMD_COMPLETE; 1641 } else 1642 rv = ATACMD_QUEUED; 1643 } 1644 splx(s); 1645 return rv; 1646 } 1647 1648 static int 1649 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1650 { 1651 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1652 int drive = xfer->c_drive; 1653 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1654 struct ata_command *ata_c = &xfer->c_ata_c; 1655 int tfd; 1656 1657 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1658 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1659 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1660 1661 ata_channel_lock_owned(chp); 1662 1663 /* First, EDMA disable, if enabled this channel. */ 1664 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1665 if (mvport->port_edmamode_curr != nodma) 1666 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1667 1668 mvsata_pmp_select(mvport, drive); 1669 1670 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1671 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1672 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1673 case WDCWAIT_OK: 1674 break; 1675 case WDCWAIT_TOUT: 1676 ata_c->flags |= AT_TIMEOU; 1677 return ATASTART_ABORT; 1678 case WDCWAIT_THR: 1679 return ATASTART_TH; 1680 } 1681 if (ata_c->flags & AT_POLL) 1682 /* polled command, disable interrupts */ 1683 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1684 if ((ata_c->flags & AT_LBA48) != 0) { 1685 wdccommandext(chp, 0, ata_c->r_command, 1686 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1687 ata_c->r_device & ~0x10); 1688 } else { 1689 wdccommand(chp, 0, ata_c->r_command, 1690 (ata_c->r_lba >> 8) & 0xffff, 1691 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1692 ((ata_c->r_lba >> 24) & 0x0f), 1693 ata_c->r_lba & 0xff, 1694 ata_c->r_count & 0xff, 1695 ata_c->r_features & 0xff); 1696 } 1697 1698 if ((ata_c->flags & AT_POLL) == 0) { 1699 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1700 wdctimeout, chp); 1701 return ATASTART_STARTED; 1702 } 1703 1704 return ATASTART_POLL; 1705 } 1706 1707 static void 1708 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1709 { 1710 /* 1711 * Polled command. Wait for drive ready or drq. Done in intr(). 1712 * Wait for at last 400ns for status bit to be valid. 1713 */ 1714 delay(10); /* 400ns delay */ 1715 mvsata_wdc_cmd_intr(chp, xfer, 0); 1716 } 1717 1718 static int 1719 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1720 { 1721 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1722 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1723 struct ata_command *ata_c = &xfer->c_ata_c; 1724 int bcount = ata_c->bcount; 1725 char *data = ata_c->data; 1726 int wflags; 1727 int drive_flags; 1728 int tfd; 1729 1730 ata_channel_lock(chp); 1731 1732 if (ata_c->r_command == WDCC_IDENTIFY || 1733 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1734 /* 1735 * The IDENTIFY data has been designed as an array of 1736 * u_int16_t, so we can byteswap it on the fly. 1737 * Historically it's what we have always done so keeping it 1738 * here ensure binary backward compatibility. 1739 */ 1740 drive_flags = ATA_DRIVE_NOSTREAM | 1741 chp->ch_drive[xfer->c_drive].drive_flags; 1742 else 1743 /* 1744 * Other data structure are opaque and should be transfered 1745 * as is. 1746 */ 1747 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1748 1749 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1750 /* both wait and poll, we can kpause here */ 1751 wflags = AT_WAIT | AT_POLL; 1752 else 1753 wflags = AT_POLL; 1754 1755 again: 1756 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1757 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1758 __func__, xfer->c_drive)); 1759 1760 /* 1761 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1762 * Reselect again, it doesn't hurt for others commands, and the time 1763 * penalty for the extra register write is acceptable, 1764 * wdc_exec_command() isn't called often (mostly for autoconfig) 1765 */ 1766 if ((xfer->c_flags & C_ATAPI) != 0) { 1767 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1768 } 1769 if ((ata_c->flags & AT_XFDONE) != 0) { 1770 /* 1771 * We have completed a data xfer. The drive should now be 1772 * in its initial state 1773 */ 1774 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1775 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1776 wflags, &tfd) == WDCWAIT_TOUT) { 1777 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1778 ata_channel_unlock(chp); 1779 return 0; /* IRQ was not for us */ 1780 } 1781 ata_c->flags |= AT_TIMEOU; 1782 } 1783 goto out; 1784 } 1785 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1786 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1787 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1788 ata_channel_unlock(chp); 1789 return 0; /* IRQ was not for us */ 1790 } 1791 ata_c->flags |= AT_TIMEOU; 1792 goto out; 1793 } 1794 delay(20); /* XXXXX: Delay more times. */ 1795 if (ata_c->flags & AT_READ) { 1796 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1797 ata_c->flags |= AT_TIMEOU; 1798 goto out; 1799 } 1800 wdc->datain_pio(chp, drive_flags, data, bcount); 1801 /* at this point the drive should be in its initial state */ 1802 ata_c->flags |= AT_XFDONE; 1803 /* 1804 * XXX checking the status register again here cause some 1805 * hardware to timeout. 1806 */ 1807 } else if (ata_c->flags & AT_WRITE) { 1808 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1809 ata_c->flags |= AT_TIMEOU; 1810 goto out; 1811 } 1812 wdc->dataout_pio(chp, drive_flags, data, bcount); 1813 ata_c->flags |= AT_XFDONE; 1814 if ((ata_c->flags & AT_POLL) == 0) { 1815 callout_reset(&chp->c_timo_callout, 1816 mstohz(ata_c->timeout), wdctimeout, chp); 1817 ata_channel_unlock(chp); 1818 return 1; 1819 } else 1820 goto again; 1821 } 1822 out: 1823 if (ATACH_ST(tfd) & WDCS_DWF) 1824 ata_c->flags |= AT_DF; 1825 if (ATACH_ST(tfd) & WDCS_ERR) { 1826 ata_c->flags |= AT_ERROR; 1827 ata_c->r_error = ATACH_ERR(tfd); 1828 } 1829 ata_channel_unlock(chp); 1830 mvsata_wdc_cmd_done(chp, xfer); 1831 1832 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1833 atastart(chp); 1834 1835 return 1; 1836 } 1837 1838 static void 1839 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1840 int reason) 1841 { 1842 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1843 struct ata_command *ata_c = &xfer->c_ata_c; 1844 bool deactivate = true; 1845 1846 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1847 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1848 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1849 1850 switch (reason) { 1851 case KILL_GONE_INACTIVE: 1852 deactivate = false; 1853 /* FALLTHROUGH */ 1854 case KILL_GONE: 1855 ata_c->flags |= AT_GONE; 1856 break; 1857 case KILL_RESET: 1858 ata_c->flags |= AT_RESET; 1859 break; 1860 case KILL_REQUEUE: 1861 panic("%s: not supposed to be requeued\n", __func__); 1862 break; 1863 default: 1864 aprint_error_dev(MVSATA_DEV2(mvport), 1865 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1866 panic("mvsata_cmd_kill_xfer"); 1867 } 1868 1869 mvsata_wdc_cmd_done_end(chp, xfer); 1870 1871 if (deactivate) 1872 ata_deactivate_xfer(chp, xfer); 1873 } 1874 1875 static void 1876 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1877 { 1878 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1879 struct atac_softc *atac = chp->ch_atac; 1880 struct ata_command *ata_c = &xfer->c_ata_c; 1881 1882 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1883 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1884 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1885 ata_c->flags)); 1886 1887 if (ata_waitdrain_xfer_check(chp, xfer)) 1888 return; 1889 1890 if ((ata_c->flags & AT_READREG) != 0 && 1891 device_is_active(atac->atac_dev) && 1892 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1893 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1894 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1895 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1896 ata_c->r_lba = 1897 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1898 ata_c->r_lba |= 1899 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1900 ata_c->r_lba |= 1901 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1902 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1903 if ((ata_c->flags & AT_LBA48) != 0) { 1904 if ((ata_c->flags & AT_POLL) != 0) { 1905 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1906 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1907 } else { 1908 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1909 WDCTL_HOB|WDCTL_4BIT); 1910 } 1911 ata_c->r_count |= 1912 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1913 ata_c->r_lba |= 1914 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1915 ata_c->r_lba |= 1916 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1917 ata_c->r_lba |= 1918 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1919 if ((ata_c->flags & AT_POLL) != 0) { 1920 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1921 WDCTL_4BIT|WDCTL_IDS); 1922 } else { 1923 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1924 WDCTL_4BIT); 1925 } 1926 } else { 1927 ata_c->r_lba |= 1928 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1929 } 1930 } 1931 1932 if (ata_c->flags & AT_POLL) { 1933 /* enable interrupts */ 1934 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1935 delay(10); /* some drives need a little delay here */ 1936 } 1937 1938 mvsata_wdc_cmd_done_end(chp, xfer); 1939 1940 ata_deactivate_xfer(chp, xfer); 1941 } 1942 1943 static void 1944 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1945 { 1946 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1947 struct ata_command *ata_c = &xfer->c_ata_c; 1948 1949 /* EDMA restart, if enabled */ 1950 if (mvport->port_edmamode_curr != nodma) { 1951 mvsata_edma_reset_qptr(mvport); 1952 mvsata_edma_enable(mvport); 1953 } 1954 1955 ata_c->flags |= AT_DONE; 1956 } 1957 1958 #if NATAPIBUS > 0 1959 static const struct ata_xfer_ops mvsata_atapi_xfer_ops = { 1960 .c_start = mvsata_atapi_start, 1961 .c_intr = mvsata_atapi_intr, 1962 .c_poll = mvsata_atapi_poll, 1963 .c_abort = mvsata_atapi_reset, 1964 .c_kill_xfer = mvsata_atapi_kill_xfer, 1965 }; 1966 1967 static void 1968 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 1969 scsipi_adapter_req_t req, void *arg) 1970 { 1971 struct scsipi_adapter *adapt = chan->chan_adapter; 1972 struct scsipi_periph *periph; 1973 struct scsipi_xfer *sc_xfer; 1974 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 1975 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1976 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1977 struct ata_xfer *xfer; 1978 int drive, s; 1979 1980 switch (req) { 1981 case ADAPTER_REQ_RUN_XFER: 1982 sc_xfer = arg; 1983 periph = sc_xfer->xs_periph; 1984 drive = periph->periph_target; 1985 1986 if (!device_is_active(atac->atac_dev)) { 1987 sc_xfer->error = XS_DRIVER_STUFFUP; 1988 scsipi_done(sc_xfer); 1989 return; 1990 } 1991 xfer = ata_get_xfer(chp, false); 1992 if (xfer == NULL) { 1993 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1994 scsipi_done(sc_xfer); 1995 return; 1996 } 1997 1998 if (sc_xfer->xs_control & XS_CTL_POLL) 1999 xfer->c_flags |= C_POLL; 2000 xfer->c_drive = drive; 2001 xfer->c_flags |= C_ATAPI; 2002 xfer->c_databuf = sc_xfer->data; 2003 xfer->c_bcount = sc_xfer->datalen; 2004 xfer->ops = &mvsata_atapi_xfer_ops; 2005 xfer->c_scsipi = sc_xfer; 2006 xfer->c_atapi.c_dscpoll = 0; 2007 s = splbio(); 2008 ata_exec_xfer(chp, xfer); 2009 #ifdef DIAGNOSTIC 2010 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 2011 (sc_xfer->xs_status & XS_STS_DONE) == 0) 2012 panic("mvsata_atapi_scsipi_request:" 2013 " polled command not done"); 2014 #endif 2015 splx(s); 2016 return; 2017 2018 default: 2019 /* Not supported, nothing to do. */ 2020 ; 2021 } 2022 } 2023 2024 static int 2025 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2026 { 2027 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2028 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2029 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2030 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2031 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2032 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2033 const char *errstring; 2034 int tfd; 2035 2036 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2037 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2038 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2039 xfer->c_drive, sc_xfer->xs_control)); 2040 2041 ata_channel_lock_owned(chp); 2042 2043 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2044 if (mvport->port_edmamode_curr != nodma) 2045 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2046 2047 mvsata_pmp_select(mvport, xfer->c_drive); 2048 2049 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2050 drvp->n_xfers++; 2051 2052 /* Do control operations specially. */ 2053 if (__predict_false(drvp->state < READY)) { 2054 /* If it's not a polled command, we need the kernel thread */ 2055 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && 2056 (chp->ch_flags & ATACH_TH_RUN) == 0) { 2057 return ATASTART_TH; 2058 } 2059 /* 2060 * disable interrupts, all commands here should be quick 2061 * enough to be able to poll, and we don't go here that often 2062 */ 2063 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2064 2065 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2066 /* Don't try to set mode if controller can't be adjusted */ 2067 if (atac->atac_set_modes == NULL) 2068 goto ready; 2069 /* Also don't try if the drive didn't report its mode */ 2070 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2071 goto ready; 2072 errstring = "unbusy"; 2073 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2074 goto timeout; 2075 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2076 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2077 errstring = "piomode-atapi"; 2078 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2079 &tfd)) 2080 goto timeout; 2081 if (ATACH_ST(tfd) & WDCS_ERR) { 2082 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2083 /* 2084 * Some ATAPI drives reject PIO settings. 2085 * Fall back to PIO mode 3 since that's the 2086 * minimum for ATAPI. 2087 */ 2088 aprint_error_dev(atac->atac_dev, 2089 "channel %d drive %d: PIO mode %d rejected," 2090 " falling back to PIO mode 3\n", 2091 chp->ch_channel, xfer->c_drive, 2092 drvp->PIO_mode); 2093 if (drvp->PIO_mode > 3) 2094 drvp->PIO_mode = 3; 2095 } else 2096 goto error; 2097 } 2098 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2099 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2100 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2101 else 2102 if (drvp->drive_flags & ATA_DRIVE_DMA) 2103 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2104 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2105 else 2106 goto ready; 2107 errstring = "dmamode-atapi"; 2108 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2109 &tfd)) 2110 goto timeout; 2111 if (ATACH_ST(tfd) & WDCS_ERR) { 2112 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2113 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2114 goto error; 2115 else { 2116 /* 2117 * The drive rejected our DMA setting. 2118 * Fall back to mode 1. 2119 */ 2120 aprint_error_dev(atac->atac_dev, 2121 "channel %d drive %d:" 2122 " DMA mode %d rejected," 2123 " falling back to DMA mode 0\n", 2124 chp->ch_channel, xfer->c_drive, 2125 drvp->DMA_mode); 2126 if (drvp->DMA_mode > 0) 2127 drvp->DMA_mode = 0; 2128 } 2129 } else 2130 goto error; 2131 } 2132 ready: 2133 drvp->state = READY; 2134 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2135 delay(10); /* some drives need a little delay here */ 2136 } 2137 /* start timeout machinery */ 2138 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2139 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 2140 wdctimeout, chp); 2141 2142 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2143 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2144 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2145 ATACH_ST(tfd)); 2146 sc_xfer->error = XS_TIMEOUT; 2147 return ATASTART_ABORT; 2148 } 2149 2150 /* 2151 * Even with WDCS_ERR, the device should accept a command packet 2152 * Limit length to what can be stuffed into the cylinder register 2153 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2154 * but not all devices do that and it's not obvious from the 2155 * ATAPI spec that that behaviour should be expected. If more 2156 * data is necessary, multiple data transfer phases will be done. 2157 */ 2158 2159 wdccommand(chp, 0, ATAPI_PKT_CMD, 2160 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2161 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2162 2163 /* 2164 * If there is no interrupt for CMD input, busy-wait for it (done in 2165 * the interrupt routine. Poll routine will exit early in this case. 2166 */ 2167 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2168 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2169 return ATASTART_POLL; 2170 else 2171 return ATASTART_STARTED; 2172 2173 timeout: 2174 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2175 chp->ch_channel, xfer->c_drive, errstring); 2176 sc_xfer->error = XS_TIMEOUT; 2177 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2178 delay(10); /* some drives need a little delay here */ 2179 return ATASTART_ABORT; 2180 2181 error: 2182 aprint_error_dev(atac->atac_dev, 2183 "channel %d drive %d: %s error (0x%x)\n", 2184 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2185 sc_xfer->error = XS_SHORTSENSE; 2186 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2187 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2188 delay(10); /* some drives need a little delay here */ 2189 return ATASTART_ABORT; 2190 } 2191 2192 static void 2193 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2194 { 2195 /* 2196 * If there is no interrupt for CMD input, busy-wait for it (done in 2197 * the interrupt routine. If it is a polled command, call the interrupt 2198 * routine until command is done. 2199 */ 2200 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2201 2202 /* Wait for at last 400ns for status bit to be valid */ 2203 DELAY(1); 2204 mvsata_atapi_intr(chp, xfer, 0); 2205 2206 if (!poll) 2207 return; 2208 2209 if (chp->ch_flags & ATACH_DMA_WAIT) { 2210 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2211 chp->ch_flags &= ~ATACH_DMA_WAIT; 2212 } 2213 2214 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2215 /* Wait for at last 400ns for status bit to be valid */ 2216 DELAY(1); 2217 mvsata_atapi_intr(chp, xfer, 0); 2218 } 2219 } 2220 2221 static int 2222 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2223 { 2224 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2225 struct atac_softc *atac = chp->ch_atac; 2226 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2227 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2228 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2229 int len, phase, ire, error, retries=0, i; 2230 int tfd; 2231 void *cmd; 2232 2233 ata_channel_lock(chp); 2234 2235 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2236 ("%s:%d:%d: mvsata_atapi_intr\n", 2237 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2238 2239 /* Is it not a transfer, but a control operation? */ 2240 if (drvp->state < READY) { 2241 aprint_error_dev(atac->atac_dev, 2242 "channel %d drive %d: bad state %d\n", 2243 chp->ch_channel, xfer->c_drive, drvp->state); 2244 panic("mvsata_atapi_intr: bad state"); 2245 } 2246 /* 2247 * If we missed an interrupt in a PIO transfer, reset and restart. 2248 * Don't try to continue transfer, we may have missed cycles. 2249 */ 2250 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2251 ata_channel_unlock(chp); 2252 sc_xfer->error = XS_TIMEOUT; 2253 mvsata_atapi_reset(chp, xfer); 2254 return 1; 2255 } 2256 2257 /* Ack interrupt done in wdc_wait_for_unbusy */ 2258 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2259 if (wdc_wait_for_unbusy(chp, 2260 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2261 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2262 ata_channel_unlock(chp); 2263 return 0; /* IRQ was not for us */ 2264 } 2265 aprint_error_dev(atac->atac_dev, 2266 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2267 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2268 ata_channel_unlock(chp); 2269 if (xfer->c_flags & C_DMA) 2270 ata_dmaerr(drvp, 2271 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2272 sc_xfer->error = XS_TIMEOUT; 2273 mvsata_atapi_reset(chp, xfer); 2274 return 1; 2275 } 2276 2277 /* 2278 * If we missed an IRQ and were using DMA, flag it as a DMA error 2279 * and reset device. 2280 */ 2281 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2282 ata_channel_unlock(chp); 2283 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2284 sc_xfer->error = XS_RESET; 2285 mvsata_atapi_reset(chp, xfer); 2286 return (1); 2287 } 2288 /* 2289 * if the request sense command was aborted, report the short sense 2290 * previously recorded, else continue normal processing 2291 */ 2292 2293 again: 2294 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2295 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2296 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2297 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2298 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2299 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2300 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2301 2302 switch (phase) { 2303 case PHASE_CMDOUT: 2304 cmd = sc_xfer->cmd; 2305 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2306 /* Init the DMA channel if necessary */ 2307 if (xfer->c_flags & C_DMA) { 2308 error = mvsata_bdma_init(mvport, xfer); 2309 if (error) { 2310 if (error == EINVAL) { 2311 /* 2312 * We can't do DMA on this transfer 2313 * for some reason. Fall back to PIO. 2314 */ 2315 xfer->c_flags &= ~C_DMA; 2316 error = 0; 2317 } else { 2318 sc_xfer->error = XS_DRIVER_STUFFUP; 2319 break; 2320 } 2321 } 2322 } 2323 2324 /* send packet command */ 2325 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2326 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2327 2328 /* Start the DMA channel if necessary */ 2329 if (xfer->c_flags & C_DMA) { 2330 mvsata_bdma_start(mvport); 2331 chp->ch_flags |= ATACH_DMA_WAIT; 2332 } 2333 ata_channel_unlock(chp); 2334 return 1; 2335 2336 case PHASE_DATAOUT: 2337 /* write data */ 2338 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2339 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2340 (xfer->c_flags & C_DMA) != 0) { 2341 aprint_error_dev(atac->atac_dev, 2342 "channel %d drive %d: bad data phase DATAOUT\n", 2343 chp->ch_channel, xfer->c_drive); 2344 ata_channel_unlock(chp); 2345 if (xfer->c_flags & C_DMA) 2346 ata_dmaerr(drvp, 2347 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2348 sc_xfer->error = XS_TIMEOUT; 2349 mvsata_atapi_reset(chp, xfer); 2350 return 1; 2351 } 2352 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2353 if (xfer->c_bcount < len) { 2354 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2355 " warning: write only %d of %d requested bytes\n", 2356 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2357 len); 2358 len = xfer->c_bcount; 2359 } 2360 2361 wdc->dataout_pio(chp, drvp->drive_flags, 2362 (char *)xfer->c_databuf + xfer->c_skip, len); 2363 2364 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 2365 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2366 2367 xfer->c_skip += len; 2368 xfer->c_bcount -= len; 2369 ata_channel_unlock(chp); 2370 return 1; 2371 2372 case PHASE_DATAIN: 2373 /* Read data */ 2374 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2375 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2376 (xfer->c_flags & C_DMA) != 0) { 2377 aprint_error_dev(atac->atac_dev, 2378 "channel %d drive %d: bad data phase DATAIN\n", 2379 chp->ch_channel, xfer->c_drive); 2380 ata_channel_unlock(chp); 2381 if (xfer->c_flags & C_DMA) 2382 ata_dmaerr(drvp, 2383 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2384 sc_xfer->error = XS_TIMEOUT; 2385 mvsata_atapi_reset(chp, xfer); 2386 return 1; 2387 } 2388 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2389 if (xfer->c_bcount < len) { 2390 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2391 " warning: reading only %d of %d bytes\n", 2392 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2393 len); 2394 len = xfer->c_bcount; 2395 } 2396 2397 wdc->datain_pio(chp, drvp->drive_flags, 2398 (char *)xfer->c_databuf + xfer->c_skip, len); 2399 2400 if (xfer->c_atapi.c_lenoff > 0) 2401 wdcbit_bucket(chp, len - xfer->c_bcount); 2402 2403 xfer->c_skip += len; 2404 xfer->c_bcount -= len; 2405 ata_channel_unlock(chp); 2406 return 1; 2407 2408 case PHASE_ABORTED: 2409 case PHASE_COMPLETED: 2410 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2411 if (xfer->c_flags & C_DMA) 2412 xfer->c_bcount -= sc_xfer->datalen; 2413 sc_xfer->resid = xfer->c_bcount; 2414 /* this will unlock channel lock too */ 2415 mvsata_atapi_phase_complete(xfer); 2416 return 1; 2417 2418 default: 2419 if (++retries<500) { 2420 DELAY(100); 2421 tfd = ATACH_ERR_ST( 2422 MVSATA_WDC_READ_1(mvport, SRB_FE), 2423 MVSATA_WDC_READ_1(mvport, SRB_CS) 2424 ); 2425 goto again; 2426 } 2427 aprint_error_dev(atac->atac_dev, 2428 "channel %d drive %d: unknown phase 0x%x\n", 2429 chp->ch_channel, xfer->c_drive, phase); 2430 if (ATACH_ST(tfd) & WDCS_ERR) { 2431 sc_xfer->error = XS_SHORTSENSE; 2432 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2433 } else { 2434 ata_channel_unlock(chp); 2435 if (xfer->c_flags & C_DMA) 2436 ata_dmaerr(drvp, 2437 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2438 sc_xfer->error = XS_RESET; 2439 mvsata_atapi_reset(chp, xfer); 2440 return (1); 2441 } 2442 } 2443 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2444 ("mvsata_atapi_intr: %s (end), error 0x%x " 2445 "sense 0x%x\n", __func__, 2446 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2447 ata_channel_unlock(chp); 2448 mvsata_atapi_done(chp, xfer); 2449 return 1; 2450 } 2451 2452 static void 2453 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2454 int reason) 2455 { 2456 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2457 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2458 bool deactivate = true; 2459 2460 /* remove this command from xfer queue */ 2461 switch (reason) { 2462 case KILL_GONE_INACTIVE: 2463 deactivate = false; 2464 /* FALLTHROUGH */ 2465 case KILL_GONE: 2466 sc_xfer->error = XS_DRIVER_STUFFUP; 2467 break; 2468 case KILL_RESET: 2469 sc_xfer->error = XS_RESET; 2470 break; 2471 case KILL_REQUEUE: 2472 sc_xfer->error = XS_REQUEUE; 2473 break; 2474 default: 2475 aprint_error_dev(MVSATA_DEV2(mvport), 2476 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2477 panic("mvsata_atapi_kill_xfer"); 2478 } 2479 2480 if (deactivate) 2481 ata_deactivate_xfer(chp, xfer); 2482 2483 ata_free_xfer(chp, xfer); 2484 scsipi_done(sc_xfer); 2485 } 2486 2487 static void 2488 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2489 { 2490 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2491 struct atac_softc *atac = chp->ch_atac; 2492 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2493 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2494 int tfd; 2495 2496 ata_channel_lock(chp); 2497 2498 mvsata_pmp_select(mvport, xfer->c_drive); 2499 2500 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2501 drvp->state = 0; 2502 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2503 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2504 chp->ch_channel, xfer->c_drive); 2505 sc_xfer->error = XS_SELTIMEOUT; 2506 } 2507 2508 ata_channel_unlock(chp); 2509 2510 mvsata_atapi_done(chp, xfer); 2511 return; 2512 } 2513 2514 static void 2515 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2516 { 2517 struct ata_channel *chp = xfer->c_chp; 2518 struct atac_softc *atac = chp->ch_atac; 2519 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2520 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2521 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2522 int tfd = 0; 2523 2524 ata_channel_lock_owned(chp); 2525 2526 /* wait for DSC if needed */ 2527 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2528 DPRINTF(DEBUG_XFERS, 2529 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2530 device_xname(atac->atac_dev), chp->ch_channel, 2531 xfer->c_drive, xfer->c_atapi.c_dscpoll)); 2532 if (cold) 2533 panic("mvsata_atapi_phase_complete: cold"); 2534 2535 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2536 WDCWAIT_TOUT) { 2537 /* 10ms not enough, try again in 1 tick */ 2538 if (xfer->c_atapi.c_dscpoll++ > 2539 mstohz(sc_xfer->timeout)) { 2540 aprint_error_dev(atac->atac_dev, 2541 "channel %d: wait_for_dsc failed\n", 2542 chp->ch_channel); 2543 ata_channel_unlock(chp); 2544 sc_xfer->error = XS_TIMEOUT; 2545 mvsata_atapi_reset(chp, xfer); 2546 } else { 2547 callout_reset(&chp->c_timo_callout, 1, 2548 mvsata_atapi_polldsc, chp); 2549 ata_channel_unlock(chp); 2550 } 2551 return; 2552 } 2553 } 2554 2555 /* 2556 * Some drive occasionally set WDCS_ERR with 2557 * "ATA illegal length indication" in the error 2558 * register. If we read some data the sense is valid 2559 * anyway, so don't report the error. 2560 */ 2561 if (ATACH_ST(tfd) & WDCS_ERR && 2562 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2563 sc_xfer->resid == sc_xfer->datalen)) { 2564 /* save the short sense */ 2565 sc_xfer->error = XS_SHORTSENSE; 2566 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2567 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2568 /* ask scsipi to send a REQUEST_SENSE */ 2569 sc_xfer->error = XS_BUSY; 2570 sc_xfer->status = SCSI_CHECK; 2571 } else 2572 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2573 ata_channel_unlock(chp); 2574 ata_dmaerr(drvp, 2575 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2576 sc_xfer->error = XS_RESET; 2577 mvsata_atapi_reset(chp, xfer); 2578 return; 2579 } 2580 } 2581 if (xfer->c_bcount != 0) { 2582 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2583 " bcount value is %d after io\n", 2584 device_xname(atac->atac_dev), chp->ch_channel, 2585 xfer->c_drive, xfer->c_bcount)); 2586 } 2587 #ifdef DIAGNOSTIC 2588 if (xfer->c_bcount < 0) { 2589 aprint_error_dev(atac->atac_dev, 2590 "channel %d drive %d: mvsata_atapi_intr:" 2591 " warning: bcount value is %d after io\n", 2592 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2593 } 2594 #endif 2595 2596 DPRINTF(DEBUG_XFERS, 2597 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2598 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2599 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2600 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2601 ata_channel_unlock(chp); 2602 mvsata_atapi_done(chp, xfer); 2603 } 2604 2605 static void 2606 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2607 { 2608 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2609 bool iserror = (sc_xfer->error != XS_NOERROR); 2610 2611 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2612 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2613 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2614 xfer->c_drive, (u_int)xfer->c_flags)); 2615 2616 if (ata_waitdrain_xfer_check(chp, xfer)) 2617 return; 2618 2619 /* mark controller inactive and free the command */ 2620 ata_deactivate_xfer(chp, xfer); 2621 2622 ata_free_xfer(chp, xfer); 2623 2624 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2625 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2626 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2627 scsipi_done(sc_xfer); 2628 DPRINTF(DEBUG_FUNCS, 2629 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2630 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2631 chp->ch_flags)); 2632 if (!iserror) 2633 atastart(chp); 2634 } 2635 2636 static void 2637 mvsata_atapi_polldsc(void *arg) 2638 { 2639 struct ata_channel *chp = arg; 2640 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 2641 2642 KASSERT(xfer != NULL); 2643 2644 ata_channel_lock(chp); 2645 2646 /* this will unlock channel lock too */ 2647 mvsata_atapi_phase_complete(xfer); 2648 } 2649 #endif /* NATAPIBUS > 0 */ 2650 2651 2652 /* 2653 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2654 * if supported queuing command by atabus? The race condition will not happen 2655 * if this is called only to the thread of atabus. 2656 */ 2657 static int 2658 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2659 { 2660 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2661 struct ata_bio *ata_bio = &xfer->c_bio; 2662 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2663 struct eprd *eprd; 2664 bus_addr_t crqb_base_addr; 2665 bus_dmamap_t data_dmamap; 2666 uint32_t reg; 2667 int erqqip, erqqop, next, rv, i; 2668 2669 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2670 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2671 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2672 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2673 2674 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2675 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2676 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2677 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2678 next = erqqip; 2679 MVSATA_EDMAQ_INC(next); 2680 if (next == erqqop) { 2681 /* queue full */ 2682 return EBUSY; 2683 } 2684 DPRINTF(DEBUG_XFERS, 2685 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2686 2687 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2688 ata_bio->flags); 2689 if (rv != 0) 2690 return rv; 2691 2692 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2693 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2694 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2695 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2696 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2697 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2698 2699 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2700 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2701 eprd->eot = htole16(0); 2702 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2703 eprd++; 2704 } 2705 (eprd - 1)->eot |= htole16(EPRD_EOT); 2706 #ifdef MVSATA_DEBUG 2707 if (mvsata_debug >= 3) 2708 mvsata_print_eprd(mvport, xfer->c_slot); 2709 #endif 2710 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2711 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2712 BUS_DMASYNC_PREWRITE); 2713 2714 /* setup EDMA Command Request Block (CRQB) Data */ 2715 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2716 #ifdef MVSATA_DEBUG 2717 if (mvsata_debug >= 3) 2718 mvsata_print_crqb(mvport, erqqip); 2719 #endif 2720 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2721 erqqip * sizeof(union mvsata_crqb), 2722 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2723 2724 MVSATA_EDMAQ_INC(erqqip); 2725 2726 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2727 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2728 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2729 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2730 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2731 2732 return 0; 2733 } 2734 2735 static int 2736 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2737 { 2738 struct ata_channel *chp = &mvport->port_ata_channel; 2739 struct crpb *crpb; 2740 struct ata_bio *ata_bio; 2741 struct ata_xfer *xfer; 2742 uint32_t reg; 2743 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2744 int st, dmaerr; 2745 2746 /* First, Sync for Request Queue buffer */ 2747 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2748 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2749 if (mvport->port_prev_erqqop != erqqop) { 2750 const int s = sizeof(union mvsata_crqb); 2751 2752 if (mvport->port_prev_erqqop < erqqop) 2753 n = erqqop - mvport->port_prev_erqqop; 2754 else { 2755 if (erqqop > 0) 2756 bus_dmamap_sync(mvport->port_dmat, 2757 mvport->port_crqb_dmamap, 0, erqqop * s, 2758 BUS_DMASYNC_POSTWRITE); 2759 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2760 } 2761 if (n > 0) 2762 bus_dmamap_sync(mvport->port_dmat, 2763 mvport->port_crqb_dmamap, 2764 mvport->port_prev_erqqop * s, n * s, 2765 BUS_DMASYNC_POSTWRITE); 2766 mvport->port_prev_erqqop = erqqop; 2767 } 2768 2769 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2770 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2771 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2772 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2773 2774 DPRINTF(DEBUG_XFERS, 2775 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2776 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2777 mvport->port, erpqip, erpqop)); 2778 2779 if (erpqop == erpqip) 2780 return 0; 2781 2782 if (erpqop < erpqip) 2783 n = erpqip - erpqop; 2784 else { 2785 if (erpqip > 0) 2786 bus_dmamap_sync(mvport->port_dmat, 2787 mvport->port_crpb_dmamap, 2788 0, erpqip * sizeof(struct crpb), 2789 BUS_DMASYNC_POSTREAD); 2790 n = MVSATA_EDMAQ_LEN - erpqop; 2791 } 2792 if (n > 0) 2793 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2794 erpqop * sizeof(struct crpb), 2795 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2796 2797 uint32_t aslots = ata_queue_active(chp); 2798 2799 prev_erpqop = erpqop; 2800 while (erpqop != erpqip) { 2801 #ifdef MVSATA_DEBUG 2802 if (mvsata_debug >= 3) 2803 mvsata_print_crpb(mvport, erpqop); 2804 #endif 2805 crpb = mvport->port_crpb + erpqop; 2806 MVSATA_EDMAQ_INC(erpqop); 2807 2808 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2809 2810 if ((aslots & __BIT(quetag)) == 0) { 2811 /* not actually executing */ 2812 continue; 2813 } 2814 2815 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2816 2817 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2818 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2819 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2820 2821 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2822 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2823 2824 ata_bio = &xfer->c_bio; 2825 ata_bio->error = NOERROR; 2826 if (dmaerr != 0) 2827 ata_bio->error = ERR_DMA; 2828 2829 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2830 2831 KASSERT(xfer->c_flags & C_DMA); 2832 mvsata_bio_intr(chp, xfer, ATACH_ERR_ST(0, st)); 2833 2834 if (xfer1 == NULL) 2835 handled++; 2836 else if (xfer == xfer1) { 2837 handled = 1; 2838 break; 2839 } 2840 } 2841 if (prev_erpqop < erpqop) 2842 n = erpqop - prev_erpqop; 2843 else { 2844 if (erpqop > 0) 2845 bus_dmamap_sync(mvport->port_dmat, 2846 mvport->port_crpb_dmamap, 0, 2847 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2848 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2849 } 2850 if (n > 0) 2851 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2852 prev_erpqop * sizeof(struct crpb), 2853 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2854 2855 reg &= ~EDMA_RESQP_ERPQP_MASK; 2856 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2857 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2858 2859 return handled; 2860 } 2861 2862 static int 2863 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2864 { 2865 int xtime; 2866 2867 for (xtime = 0; xtime < timeout * 10; xtime++) { 2868 if (mvsata_edma_handle(mvport, xfer)) 2869 return 0; 2870 DELAY(100); 2871 } 2872 2873 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2874 mvsata_edma_rqq_remove(mvport, xfer); 2875 xfer->c_flags |= C_TIMEOU; 2876 return 1; 2877 } 2878 2879 static void 2880 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2881 { 2882 struct ata_channel *chp = &mvport->port_ata_channel; 2883 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2884 bus_addr_t crqb_base_addr; 2885 int erqqip, i; 2886 2887 /* First, hardware reset, stop EDMA */ 2888 mvsata_hreset_port(mvport); 2889 2890 /* cleanup completed EDMA safely */ 2891 mvsata_edma_handle(mvport, NULL); 2892 2893 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2894 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2895 2896 uint32_t aslots = ata_queue_active(chp); 2897 2898 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2899 struct ata_xfer *rqxfer; 2900 2901 if ((aslots & __BIT(i)) == 0) 2902 continue; 2903 2904 if (i == xfer->c_slot) { 2905 /* remove xfer from EDMA request queue */ 2906 bus_dmamap_sync(mvport->port_dmat, 2907 mvport->port_eprd_dmamap, 2908 mvport->port_reqtbl[i].eprd_offset, 2909 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2910 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 2911 /* quetag freed by caller later */ 2912 continue; 2913 } 2914 2915 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 2916 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 2917 erqqip++; 2918 } 2919 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2920 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2921 BUS_DMASYNC_POSTWRITE); 2922 2923 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 2924 mvsata_edma_reset_qptr(mvport); 2925 mvsata_edma_enable(mvport); 2926 2927 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2928 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2929 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2930 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2931 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2932 } 2933 2934 #if NATAPIBUS > 0 2935 static int 2936 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 2937 { 2938 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2939 struct eprd *eprd; 2940 bus_dmamap_t data_dmamap; 2941 bus_addr_t eprd_addr; 2942 int i, rv; 2943 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2944 2945 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2946 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2947 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2948 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2949 2950 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 2951 sc_xfer->datalen, 2952 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2953 if (rv != 0) 2954 return rv; 2955 2956 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2957 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2958 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2959 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2960 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2961 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2962 2963 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2964 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2965 eprd->eot = htole16(0); 2966 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2967 eprd++; 2968 } 2969 (eprd - 1)->eot |= htole16(EPRD_EOT); 2970 #ifdef MVSATA_DEBUG 2971 if (mvsata_debug >= 3) 2972 mvsata_print_eprd(mvport, xfer->c_slot); 2973 #endif 2974 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2975 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2976 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 2977 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2978 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 2979 2980 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2981 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2982 2983 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2984 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2985 else 2986 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2987 2988 return 0; 2989 } 2990 2991 static void 2992 mvsata_bdma_start(struct mvsata_port *mvport) 2993 { 2994 2995 #ifdef MVSATA_DEBUG 2996 if (mvsata_debug >= 3) 2997 mvsata_print_eprd(mvport, 0); 2998 #endif 2999 3000 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 3001 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 3002 } 3003 #endif 3004 #endif 3005 3006 3007 static int 3008 mvsata_port_init(struct mvsata_hc *mvhc, int port) 3009 { 3010 struct mvsata_softc *sc = mvhc->hc_sc; 3011 struct mvsata_port *mvport; 3012 struct ata_channel *chp; 3013 int channel, rv, i; 3014 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 3015 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 3016 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 3017 3018 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 3019 M_ZERO | M_NOWAIT); 3020 if (mvport == NULL) { 3021 aprint_error("%s:%d: can't allocate memory for port %d\n", 3022 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3023 return ENOMEM; 3024 } 3025 3026 mvport->port = port; 3027 mvport->port_hc = mvhc; 3028 mvport->port_edmamode_negotiated = nodma; 3029 3030 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3031 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3032 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3033 if (rv != 0) { 3034 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3035 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3036 goto fail0; 3037 } 3038 mvport->port_iot = mvhc->hc_iot; 3039 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3040 &mvport->port_sata_sstatus); 3041 if (rv != 0) { 3042 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3043 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3044 goto fail0; 3045 } 3046 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3047 &mvport->port_sata_serror); 3048 if (rv != 0) { 3049 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3050 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3051 goto fail0; 3052 } 3053 if (sc->sc_rev == gen1) 3054 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3055 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3056 else 3057 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3058 SATA_SC, 4, &mvport->port_sata_scontrol); 3059 if (rv != 0) { 3060 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3061 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3062 goto fail0; 3063 } 3064 mvport->port_dmat = sc->sc_dmat; 3065 mvhc->hc_ports[port] = mvport; 3066 3067 channel = mvhc->hc * sc->sc_port + port; 3068 chp = &mvport->port_ata_channel; 3069 chp->ch_channel = channel; 3070 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3071 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3072 sc->sc_ata_channels[channel] = chp; 3073 3074 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3075 if (rv != 0) 3076 goto fail0; 3077 3078 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3079 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3080 if (rv != 0) { 3081 aprint_error( 3082 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3083 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3084 goto fail0; 3085 } 3086 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3087 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3088 if (rv != 0) { 3089 aprint_error( 3090 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3091 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3092 goto fail1; 3093 } 3094 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3095 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3096 if (rv != 0) { 3097 aprint_error( 3098 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3099 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3100 goto fail2; 3101 } 3102 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3103 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3104 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 3105 &mvport->port_reqtbl[i].data_dmamap); 3106 if (rv != 0) { 3107 aprint_error("%s:%d:%d:" 3108 " EDMA data map(%d) create failed: error=%d\n", 3109 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3110 rv); 3111 goto fail3; 3112 } 3113 } 3114 3115 return 0; 3116 3117 fail3: 3118 for (i--; i >= 0; i--) 3119 bus_dmamap_destroy(mvport->port_dmat, 3120 mvport->port_reqtbl[i].data_dmamap); 3121 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3122 fail2: 3123 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3124 fail1: 3125 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3126 fail0: 3127 return rv; 3128 } 3129 3130 static int 3131 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3132 { 3133 int hc, port, rv, i; 3134 3135 hc = mvport->port_hc->hc; 3136 port = mvport->port; 3137 3138 /* Create subregion for Shadow Registers Map */ 3139 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3140 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3141 if (rv != 0) { 3142 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3143 device_xname(MVSATA_DEV2(mvport)), hc, port); 3144 return rv; 3145 } 3146 wdr->cmd_iot = mvport->port_iot; 3147 3148 /* Once create subregion for each command registers */ 3149 for (i = 0; i < WDC_NREG; i++) { 3150 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3151 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3152 if (rv != 0) { 3153 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3154 device_xname(MVSATA_DEV2(mvport)), hc, port); 3155 return rv; 3156 } 3157 } 3158 /* Create subregion for Alternate Status register */ 3159 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3160 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3161 if (rv != 0) { 3162 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3163 device_xname(MVSATA_DEV2(mvport)), hc, port); 3164 return rv; 3165 } 3166 wdr->ctl_iot = mvport->port_iot; 3167 3168 wdc_init_shadow_regs(wdr); 3169 3170 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3171 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3172 if (rv != 0) { 3173 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3174 device_xname(MVSATA_DEV2(mvport)), hc, port); 3175 return rv; 3176 } 3177 wdr->sata_iot = mvport->port_iot; 3178 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3179 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3180 if (rv != 0) { 3181 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3182 device_xname(MVSATA_DEV2(mvport)), hc, port); 3183 return rv; 3184 } 3185 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3186 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3187 if (rv != 0) { 3188 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3189 device_xname(MVSATA_DEV2(mvport)), hc, port); 3190 return rv; 3191 } 3192 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3193 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3194 if (rv != 0) { 3195 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3196 device_xname(MVSATA_DEV2(mvport)), hc, port); 3197 return rv; 3198 } 3199 3200 return 0; 3201 } 3202 3203 3204 #ifndef MVSATA_WITHOUTDMA 3205 static void * 3206 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3207 bus_dmamap_t *dmamap, size_t size, int write) 3208 { 3209 bus_dma_segment_t seg; 3210 int nseg, rv; 3211 void *kva; 3212 3213 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3214 BUS_DMA_NOWAIT); 3215 if (rv != 0) { 3216 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3217 device_xname(MVSATA_DEV2(mvport)), 3218 mvport->port_hc->hc, mvport->port, rv); 3219 goto fail; 3220 } 3221 3222 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3223 if (rv != 0) { 3224 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3225 device_xname(MVSATA_DEV2(mvport)), 3226 mvport->port_hc->hc, mvport->port, rv); 3227 goto free; 3228 } 3229 3230 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3231 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3232 if (rv != 0) { 3233 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3234 device_xname(MVSATA_DEV2(mvport)), 3235 mvport->port_hc->hc, mvport->port, rv); 3236 goto unmap; 3237 } 3238 3239 if (!write) 3240 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3241 3242 return kva; 3243 3244 unmap: 3245 bus_dmamem_unmap(dmat, kva, size); 3246 free: 3247 bus_dmamem_free(dmat, &seg, nseg); 3248 fail: 3249 return NULL; 3250 } 3251 3252 /* ARGSUSED */ 3253 static void 3254 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3255 bus_dmamap_t dmamap, void *kva) 3256 { 3257 3258 bus_dmamap_unload(dmat, dmamap); 3259 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3260 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3261 } 3262 3263 static int 3264 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3265 size_t datalen, int flags) 3266 { 3267 int rv, lop, sop; 3268 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3269 3270 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3271 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3272 3273 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3274 NULL, BUS_DMA_NOWAIT | lop); 3275 if (rv) { 3276 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3277 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3278 mvport->port, rv); 3279 return rv; 3280 } 3281 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3282 data_dmamap->dm_mapsize, sop); 3283 3284 return 0; 3285 } 3286 3287 static inline void 3288 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3289 { 3290 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3291 3292 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3293 data_dmamap->dm_mapsize, 3294 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3295 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3296 } 3297 #endif 3298 3299 static void 3300 mvsata_hreset_port(struct mvsata_port *mvport) 3301 { 3302 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3303 3304 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3305 3306 delay(25); /* allow reset propagation */ 3307 3308 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3309 3310 mvport->_fix_phy_param._fix_phy(mvport); 3311 3312 if (sc->sc_gen == gen1) 3313 delay(1000); 3314 } 3315 3316 static void 3317 mvsata_reset_port(struct mvsata_port *mvport) 3318 { 3319 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3320 3321 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3322 3323 mvsata_hreset_port(mvport); 3324 3325 if (device_is_a(parent, "pci")) 3326 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3327 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3328 else /* SoC */ 3329 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3330 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3331 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3332 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3333 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3334 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3335 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3336 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3337 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3338 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3339 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3340 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3341 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3342 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3343 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3344 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3345 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3346 } 3347 3348 static void 3349 mvsata_reset_hc(struct mvsata_hc *mvhc) 3350 { 3351 #if 0 3352 uint32_t val; 3353 #endif 3354 3355 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3356 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3357 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3358 3359 #if 0 /* XXXX needs? */ 3360 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3361 3362 /* 3363 * Keep the SS during power on and the reference clock bits (reset 3364 * sample) 3365 */ 3366 val = MVSATA_HC_READ_4(mvhc, 0x020); 3367 val &= 0x1c1c1c1c; 3368 val |= 0x03030303; 3369 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3370 #endif 3371 } 3372 3373 static uint32_t 3374 mvsata_softreset(struct mvsata_port *mvport, int flags) 3375 { 3376 struct ata_channel *chp = &mvport->port_ata_channel; 3377 uint32_t sig0 = ~0; 3378 int timeout; 3379 uint8_t st0; 3380 3381 ata_channel_lock_owned(chp); 3382 3383 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3384 delay(10); 3385 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3386 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3387 delay(10); 3388 3389 /* wait for BSY to deassert */ 3390 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3391 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3392 3393 if ((st0 & WDCS_BSY) == 0) { 3394 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3395 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3396 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3397 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3398 goto out; 3399 } 3400 ata_delay(chp, 10, "atarst", flags); 3401 } 3402 3403 aprint_error("%s:%d:%d: %s: timeout\n", 3404 device_xname(MVSATA_DEV2(mvport)), 3405 mvport->port_hc->hc, mvport->port, __func__); 3406 3407 out: 3408 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3409 return sig0; 3410 } 3411 3412 #ifndef MVSATA_WITHOUTDMA 3413 static void 3414 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3415 { 3416 const bus_addr_t crpb_addr = 3417 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3418 const uint32_t crpb_addr_mask = 3419 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3420 3421 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3422 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3423 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3424 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3425 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3426 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3427 } 3428 3429 static inline void 3430 mvsata_edma_enable(struct mvsata_port *mvport) 3431 { 3432 3433 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3434 } 3435 3436 static int 3437 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3438 { 3439 struct ata_channel *chp = &mvport->port_ata_channel; 3440 uint32_t status, command; 3441 uint32_t idlestatus = EDMA_S_EDMAIDLE | EDMA_S_ECACHEEMPTY; 3442 int t; 3443 3444 ata_channel_lock_owned(chp); 3445 3446 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3447 3448 timeout = mstohz(timeout + hztoms(1) - 1); 3449 3450 for (t = 0; ; ++t) { 3451 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3452 if ((status & idlestatus) == idlestatus) 3453 break; 3454 if (t >= timeout) 3455 break; 3456 ata_delay(chp, hztoms(1), "mvsata_edma1", wflags); 3457 } 3458 if (t >= timeout) { 3459 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3460 device_xname(MVSATA_DEV2(mvport)), 3461 mvport->port_hc->hc, mvport->port); 3462 return EBUSY; 3463 } 3464 3465 /* The disable bit (eDsEDMA) is self negated. */ 3466 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3467 3468 for (t = 0; ; ++t) { 3469 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3470 if (!(command & EDMA_CMD_EENEDMA)) 3471 break; 3472 if (t >= timeout) 3473 break; 3474 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3475 } 3476 if (t >= timeout) { 3477 aprint_error("%s:%d:%d: unable to re-enable EDMA\n", 3478 device_xname(MVSATA_DEV2(mvport)), 3479 mvport->port_hc->hc, mvport->port); 3480 return EBUSY; 3481 } 3482 } 3483 return 0; 3484 } 3485 3486 /* 3487 * Set EDMA registers according to mode. 3488 * ex. NCQ/TCQ(queued)/non queued. 3489 */ 3490 static void 3491 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3492 { 3493 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3494 uint32_t reg; 3495 3496 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3497 reg |= EDMA_CFG_RESERVED; 3498 3499 if (mode == ncq) { 3500 if (sc->sc_gen == gen1) { 3501 aprint_error_dev(MVSATA_DEV2(mvport), 3502 "GenI not support NCQ\n"); 3503 return; 3504 } else if (sc->sc_gen == gen2) 3505 reg |= EDMA_CFG_EDEVERR; 3506 reg |= EDMA_CFG_ESATANATVCMDQUE; 3507 } else if (mode == queued) { 3508 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3509 reg |= EDMA_CFG_EQUE; 3510 } else 3511 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3512 3513 if (sc->sc_gen == gen1) 3514 reg |= EDMA_CFG_ERDBSZ; 3515 else if (sc->sc_gen == gen2) 3516 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3517 else if (sc->sc_gen == gen2e) { 3518 device_t parent = device_parent(MVSATA_DEV(sc)); 3519 3520 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3521 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3522 3523 if (device_is_a(parent, "pci")) 3524 reg |= ( 3525 #if NATAPIBUS > 0 3526 EDMA_CFG_EEARLYCOMPLETIONEN | 3527 #endif 3528 EDMA_CFG_ECUTTHROUGHEN | 3529 EDMA_CFG_EWRBUFFERLEN | 3530 EDMA_CFG_ERDBSZEXT); 3531 } 3532 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3533 3534 reg = ( 3535 EDMA_IE_EIORDYERR | 3536 EDMA_IE_ETRANSINT | 3537 EDMA_IE_EDEVCON | 3538 EDMA_IE_EDEVDIS); 3539 if (sc->sc_gen != gen1) 3540 reg |= ( 3541 EDMA_IE_TRANSPROTERR | 3542 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3543 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3544 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3545 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3546 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3547 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3548 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3549 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3550 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3551 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3552 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3553 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3554 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3555 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3556 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3557 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3558 EDMA_IE_ESELFDIS); 3559 3560 if (mode == ncq) 3561 reg |= EDMA_IE_EDEVERR; 3562 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3563 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3564 reg &= ~EDMA_IE_EDEVERR; 3565 if (mode != ncq) 3566 reg |= EDMA_IE_EDEVERR; 3567 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3568 if (sc->sc_gen == gen2e) { 3569 /* 3570 * Clear FISWait4HostRdyEn[0] and [2]. 3571 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3572 * [2]: SDB FIS is received with <ERR> bit set to 1. 3573 */ 3574 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3575 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3576 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3577 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3578 } 3579 3580 mvport->port_edmamode_curr = mode; 3581 } 3582 3583 3584 /* 3585 * Generation dependent functions 3586 */ 3587 3588 static void 3589 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3590 struct ata_xfer *xfer) 3591 { 3592 struct crqb *crqb; 3593 bus_addr_t eprd_addr; 3594 daddr_t blkno; 3595 uint32_t rw; 3596 uint8_t cmd, head; 3597 int i; 3598 struct ata_bio *ata_bio = &xfer->c_bio; 3599 3600 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3601 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3602 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3603 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3604 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3605 head = WDSD_LBA; 3606 } else { 3607 head = 0; 3608 } 3609 blkno = ata_bio->blkno; 3610 if (ata_bio->flags & ATA_LBA48) 3611 cmd = atacmd_to48(cmd); 3612 else { 3613 head |= ((ata_bio->blkno >> 24) & 0xf); 3614 blkno &= 0xffffff; 3615 } 3616 crqb = &mvport->port_crqb->crqb + erqqip; 3617 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3618 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3619 crqb->ctrlflg = 3620 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3621 CRQB_CPMPORT(xfer->c_drive)); 3622 i = 0; 3623 if (mvport->port_edmamode_curr == dma) { 3624 if (ata_bio->flags & ATA_LBA48) 3625 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3626 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3627 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3628 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3629 } else { /* ncq/queued */ 3630 3631 /* 3632 * XXXX: Oops, ata command is not correct. And, atabus layer 3633 * has not been supported yet now. 3634 * Queued DMA read/write. 3635 * read/write FPDMAQueued. 3636 */ 3637 3638 if (ata_bio->flags & ATA_LBA48) 3639 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3640 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3641 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3642 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3643 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3644 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3645 } 3646 if (ata_bio->flags & ATA_LBA48) { 3647 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3648 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3649 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3650 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3651 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3652 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3653 } 3654 crqb->atacommand[i++] = 3655 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3656 crqb->atacommand[i++] = 3657 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3658 crqb->atacommand[i++] = 3659 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3660 crqb->atacommand[i++] = 3661 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3662 crqb->atacommand[i++] = htole16( 3663 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3664 CRQB_ATACOMMAND_LAST); 3665 } 3666 #endif 3667 3668 static uint32_t 3669 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3670 { 3671 struct mvsata_hc *hc = mvport->port_hc; 3672 uint32_t reg; 3673 3674 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3675 /* 3676 * [12:11] : pre 3677 * [7:5] : amps 3678 */ 3679 return reg & 0x000018e0; 3680 } 3681 3682 static void 3683 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3684 { 3685 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3686 struct mvsata_hc *mvhc = mvport->port_hc; 3687 uint32_t reg; 3688 int port = mvport->port, fix_apm_sq = 0; 3689 3690 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3691 if (sc->sc_rev == 0x01) 3692 fix_apm_sq = 1; 3693 } else { 3694 if (sc->sc_rev == 0x00) 3695 fix_apm_sq = 1; 3696 } 3697 3698 if (fix_apm_sq) { 3699 /* 3700 * Disable auto-power management 3701 * 88SX50xx FEr SATA#12 3702 */ 3703 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3704 reg |= (1 << 19); 3705 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3706 3707 /* 3708 * Fix squelch threshold 3709 * 88SX50xx FEr SATA#9 3710 */ 3711 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3712 reg &= ~0x3; 3713 reg |= 0x1; 3714 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3715 } 3716 3717 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3718 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3719 reg &= ~0x000018e0; /* pre and amps mask */ 3720 reg |= mvport->_fix_phy_param.pre_amps; 3721 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3722 } 3723 3724 static void 3725 mvsata_devconn_gen1(struct mvsata_port *mvport) 3726 { 3727 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3728 3729 /* Fix for 88SX50xx FEr SATA#2 */ 3730 mvport->_fix_phy_param._fix_phy(mvport); 3731 3732 /* If disk is connected, then enable the activity LED */ 3733 if (sc->sc_rev == 0x03) { 3734 /* XXXXX */ 3735 } 3736 } 3737 3738 static uint32_t 3739 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3740 { 3741 uint32_t reg; 3742 3743 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3744 /* 3745 * [10:8] : amps 3746 * [7:5] : pre 3747 */ 3748 return reg & 0x000007e0; 3749 } 3750 3751 static void 3752 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3753 { 3754 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3755 uint32_t reg; 3756 3757 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3758 sc->sc_gen == gen2e) { 3759 /* 3760 * Fix for 3761 * 88SX60X1 FEr SATA #23 3762 * 88SX6042/88SX7042 FEr SATA #23 3763 * 88F5182 FEr #SATA-S13 3764 * 88F5082 FEr #SATA-S13 3765 */ 3766 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3767 reg &= ~(1 << 16); 3768 reg |= (1 << 31); 3769 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3770 3771 delay(200); 3772 3773 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3774 reg &= ~((1 << 16) | (1 << 31)); 3775 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3776 3777 delay(200); 3778 } 3779 3780 /* Fix values in PHY Mode 3 Register.*/ 3781 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3782 reg &= ~0x7F900000; 3783 reg |= 0x2A800000; 3784 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3785 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3786 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3787 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3788 reg &= ~0x0000001c; 3789 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3790 3791 /* 3792 * Fix values in PHY Mode 4 Register. 3793 * 88SX60x1 FEr SATA#10 3794 * 88F5182 GL #SATA-S10 3795 * 88F5082 GL #SATA-S10 3796 */ 3797 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3798 sc->sc_gen == gen2e) { 3799 uint32_t tmp = 0; 3800 3801 /* 88SX60x1 FEr SATA #13 */ 3802 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3803 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3804 3805 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3806 reg |= (1 << 0); 3807 reg &= ~(1 << 1); 3808 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3809 if (sc->sc_gen == gen2e) { 3810 reg &= ~0x5de3fffc; 3811 reg |= (1 << 2); 3812 } 3813 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3814 3815 /* 88SX60x1 FEr SATA #13 */ 3816 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3817 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3818 } 3819 3820 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3821 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3822 reg &= ~0x000007e0; /* pre and amps mask */ 3823 reg |= mvport->_fix_phy_param.pre_amps; 3824 reg &= ~(1 << 16); 3825 if (sc->sc_gen == gen2e) { 3826 /* 3827 * according to mvSata 3.6.1, some IIE values are fixed. 3828 * some reserved fields must be written with fixed values. 3829 */ 3830 reg &= ~0xC30FF01F; 3831 reg |= 0x0000900F; 3832 } 3833 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3834 } 3835 3836 #ifndef MVSATA_WITHOUTDMA 3837 static void 3838 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3839 struct ata_xfer *xfer) 3840 { 3841 struct crqb_gen2e *crqb; 3842 bus_addr_t eprd_addr; 3843 uint32_t ctrlflg, rw; 3844 uint8_t fis[RHD_FISLEN]; 3845 3846 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3847 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3848 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3849 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3850 CRQB_CPMPORT(xfer->c_drive) | 3851 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3852 3853 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3854 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3855 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3856 crqb->ctrlflg = htole32(ctrlflg); 3857 3858 satafis_rhd_construct_bio(xfer, fis); 3859 3860 crqb->atacommand[0] = 0; 3861 crqb->atacommand[1] = 0; 3862 /* copy over the ATA command part of the fis */ 3863 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3864 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3865 } 3866 3867 #ifdef MVSATA_DEBUG 3868 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3869 do { \ 3870 int _i; \ 3871 u_char *_p = (p); \ 3872 \ 3873 printf(#type "(%d)", (n)); \ 3874 for (_i = 0; _i < (size); _i++, _p++) { \ 3875 if (_i % 16 == 0) \ 3876 printf("\n "); \ 3877 printf(" %02x", *_p); \ 3878 } \ 3879 printf("\n"); \ 3880 } while (0 /* CONSTCOND */) 3881 3882 static void 3883 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3884 { 3885 3886 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3887 n, (u_char *)(mvport->port_crqb + n)); 3888 } 3889 3890 static void 3891 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3892 { 3893 3894 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3895 n, (u_char *)(mvport->port_crpb + n)); 3896 } 3897 3898 static void 3899 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3900 { 3901 struct eprd *eprd; 3902 int i = 0; 3903 3904 eprd = mvport->port_reqtbl[n].eprd; 3905 while (1 /*CONSTCOND*/) { 3906 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3907 i, (u_char *)eprd); 3908 if (eprd->eot & EPRD_EOT) 3909 break; 3910 eprd++; 3911 i++; 3912 } 3913 } 3914 #endif 3915 #endif 3916
Indexes created Tue Sep 23 14:10:03 GMT 2025