mvsata.c revision 1.45
1 /* $NetBSD: mvsata.c,v 1.45 2018/11/12 18:51:01 jdolecek Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.45 2018/11/12 18:51:01 jdolecek Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 /* 62 * Nice things to do: 63 * 64 * - MSI/MSI-X support - though on some models MSI actually doesn't work 65 * even when hardware claims to support it, according to FreeBSD/OpenBSD 66 * - move pci-specific code to the pci attach code 67 * - mvsata(4) use 64-bit DMA on hardware which claims to support it 68 * - e.g. AHA1430SA does not really work, crash in mvsata_intr() on boot 69 */ 70 71 #include <dev/ic/mvsatareg.h> 72 #include <dev/ic/mvsatavar.h> 73 74 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 75 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 76 77 #define MVSATA_HC_READ_4(hc, reg) \ 78 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 79 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 80 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 81 #define MVSATA_EDMA_READ_4(mvport, reg) \ 82 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 83 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 84 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 85 #define MVSATA_WDC_READ_2(mvport, reg) \ 86 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 87 SHADOW_REG_BLOCK_OFFSET + (reg)) 88 #define MVSATA_WDC_READ_1(mvport, reg) \ 89 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 90 SHADOW_REG_BLOCK_OFFSET + (reg)) 91 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 92 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 93 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 94 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 95 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 96 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 97 98 #ifdef MVSATA_DEBUG 99 100 #define DEBUG_INTR 0x01 101 #define DEBUG_XFERS 0x02 102 #define DEBUG_FUNCS 0x08 103 #define DEBUG_PROBE 0x10 104 105 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 106 int mvsata_debug = 0; 107 #else 108 #define DPRINTF(n,x) 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 113 sending a cmd */ 114 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 115 116 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 117 118 119 static void mvsata_probe_drive(struct ata_channel *); 120 121 #ifndef MVSATA_WITHOUTDMA 122 static void mvsata_reset_channel(struct ata_channel *, int); 123 static int mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 124 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 125 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 126 static int mvsata_addref(struct ata_drive_datas *); 127 static void mvsata_delref(struct ata_drive_datas *); 128 static void mvsata_killpending(struct ata_drive_datas *); 129 130 #if NATAPIBUS > 0 131 static void mvsata_atapibus_attach(struct atabus_softc *); 132 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 133 scsipi_adapter_req_t, void *); 134 static void mvsata_atapi_minphys(struct buf *); 135 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 136 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 137 #endif 138 #endif 139 140 static void mvsata_setup_channel(struct ata_channel *); 141 142 #ifndef MVSATA_WITHOUTDMA 143 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 144 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 145 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 147 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 148 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 149 int); 150 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 151 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 152 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 154 int); 155 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 156 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 157 #if NATAPIBUS > 0 158 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 159 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 160 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 161 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 162 int); 163 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 164 static void mvsata_atapi_phase_complete(struct ata_xfer *); 165 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 166 static void mvsata_atapi_polldsc(void *); 167 #endif 168 169 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 170 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 171 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 172 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 173 #if NATAPIBUS > 0 174 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 175 static void mvsata_bdma_start(struct mvsata_port *); 176 #endif 177 #endif 178 179 static int mvsata_nondma_handle(struct mvsata_port *); 180 181 static int mvsata_port_init(struct mvsata_hc *, int); 182 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 183 #ifndef MVSATA_WITHOUTDMA 184 static void mvsata_channel_recover(struct ata_channel *, int, uint32_t); 185 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 186 bus_dmamap_t *, size_t, int); 187 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 188 bus_dmamap_t, void *); 189 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 190 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 191 #endif 192 193 static void mvsata_hreset_port(struct mvsata_port *); 194 static void mvsata_reset_port(struct mvsata_port *); 195 static void mvsata_reset_hc(struct mvsata_hc *); 196 static uint32_t mvsata_softreset(struct mvsata_port *, int); 197 #ifndef MVSATA_WITHOUTDMA 198 static void mvsata_edma_reset_qptr(struct mvsata_port *); 199 static inline void mvsata_edma_enable(struct mvsata_port *); 200 static int mvsata_edma_disable(struct mvsata_port *, int, int); 201 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 202 203 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 204 struct ata_xfer *); 205 #endif 206 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 207 static void mvsata_fix_phy_gen1(struct mvsata_port *); 208 static void mvsata_devconn_gen1(struct mvsata_port *); 209 210 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 211 static void mvsata_fix_phy_gen2(struct mvsata_port *); 212 #ifndef MVSATA_WITHOUTDMA 213 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 214 struct ata_xfer *); 215 216 #ifdef MVSATA_DEBUG 217 static void mvsata_print_crqb(struct mvsata_port *, int); 218 static void mvsata_print_crpb(struct mvsata_port *, int); 219 static void mvsata_print_eprd(struct mvsata_port *, int); 220 #endif 221 222 static const struct ata_bustype mvsata_ata_bustype = { 223 SCSIPI_BUSTYPE_ATA, 224 mvsata_bio, 225 mvsata_reset_drive, 226 mvsata_reset_channel, 227 mvsata_exec_command, 228 ata_get_params, 229 mvsata_addref, 230 mvsata_delref, 231 mvsata_killpending, 232 mvsata_channel_recover, 233 }; 234 235 #if NATAPIBUS > 0 236 static const struct scsipi_bustype mvsata_atapi_bustype = { 237 SCSIPI_BUSTYPE_ATAPI, 238 atapi_scsipi_cmd, 239 atapi_interpret_sense, 240 atapi_print_addr, 241 mvsata_atapi_kill_pending, 242 NULL, 243 }; 244 #endif /* NATAPIBUS */ 245 #endif 246 247 static void 248 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 249 { 250 uint32_t ifctl; 251 252 KASSERT(pmpport < PMP_MAX_DRIVES); 253 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 254 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 255 panic("EDMA enabled"); 256 } 257 #endif 258 259 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 260 ifctl &= ~0xf; 261 ifctl |= pmpport; 262 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 263 } 264 265 int 266 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 267 int (*mvsata_sreset)(struct mvsata_softc *), 268 int (*mvsata_misc_reset)(struct mvsata_softc *), 269 int read_pre_amps) 270 { 271 struct mvsata_hc *mvhc; 272 struct mvsata_port *mvport; 273 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 274 void (*_fix_phy)(struct mvsata_port *) = NULL; 275 #ifndef MVSATA_WITHOUTDMA 276 void (*edma_setup_crqb) 277 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 278 #endif 279 int hc, port, channel; 280 281 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 282 (product->generation == gen1) ? "I" : 283 ((product->generation == gen2) ? "II" : "IIe"), 284 product->hc, product->port); 285 286 287 switch (product->generation) { 288 case gen1: 289 mvsata_sreset = NULL; 290 read_pre_amps = 1; /* MUST */ 291 read_preamps = mvsata_read_preamps_gen1; 292 _fix_phy = mvsata_fix_phy_gen1; 293 #ifndef MVSATA_WITHOUTDMA 294 edma_setup_crqb = mvsata_edma_setup_crqb; 295 #endif 296 break; 297 298 case gen2: 299 read_preamps = mvsata_read_preamps_gen2; 300 _fix_phy = mvsata_fix_phy_gen2; 301 #ifndef MVSATA_WITHOUTDMA 302 edma_setup_crqb = mvsata_edma_setup_crqb; 303 #endif 304 break; 305 306 case gen2e: 307 read_preamps = mvsata_read_preamps_gen2; 308 _fix_phy = mvsata_fix_phy_gen2; 309 #ifndef MVSATA_WITHOUTDMA 310 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 311 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 312 #endif 313 break; 314 } 315 316 sc->sc_gen = product->generation; 317 sc->sc_hc = product->hc; 318 sc->sc_port = product->port; 319 sc->sc_flags = product->flags; 320 321 #ifdef MVSATA_WITHOUTDMA 322 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 323 #else 324 sc->sc_edma_setup_crqb = edma_setup_crqb; 325 sc->sc_wdcdev.sc_atac.atac_cap |= 326 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 327 #endif 328 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 329 #ifdef MVSATA_WITHOUTDMA 330 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 331 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 332 #else 333 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 334 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 335 #endif 336 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 337 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 338 #ifndef MVSATA_WITHOUTDMA 339 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 340 #if NATAPIBUS > 0 341 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 342 #endif 343 #endif 344 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 345 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 346 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 347 348 sc->sc_wdc_regs = 349 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 350 M_DEVBUF, M_NOWAIT); 351 if (sc->sc_wdc_regs == NULL) { 352 aprint_error_dev(MVSATA_DEV(sc), 353 "can't allocate wdc regs memory\n"); 354 return ENOMEM; 355 } 356 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 357 358 for (hc = 0; hc < sc->sc_hc; hc++) { 359 mvhc = &sc->sc_hcs[hc]; 360 mvhc->hc = hc; 361 mvhc->hc_sc = sc; 362 mvhc->hc_iot = sc->sc_iot; 363 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 364 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 365 &mvhc->hc_ioh)) { 366 aprint_error_dev(MVSATA_DEV(sc), 367 "can't subregion SATAHC %d registers\n", hc); 368 continue; 369 } 370 371 for (port = 0; port < sc->sc_port; port++) 372 if (mvsata_port_init(mvhc, port) == 0) { 373 int pre_amps; 374 375 mvport = mvhc->hc_ports[port]; 376 pre_amps = read_pre_amps ? 377 read_preamps(mvport) : 0x00000720; 378 mvport->_fix_phy_param.pre_amps = pre_amps; 379 mvport->_fix_phy_param._fix_phy = _fix_phy; 380 381 if (!mvsata_sreset) 382 mvsata_reset_port(mvport); 383 } 384 385 if (!mvsata_sreset) 386 mvsata_reset_hc(mvhc); 387 } 388 if (mvsata_sreset) 389 mvsata_sreset(sc); 390 391 if (mvsata_misc_reset) 392 mvsata_misc_reset(sc); 393 394 for (hc = 0; hc < sc->sc_hc; hc++) 395 for (port = 0; port < sc->sc_port; port++) { 396 mvport = sc->sc_hcs[hc].hc_ports[port]; 397 if (mvport == NULL) 398 continue; 399 if (mvsata_sreset) 400 mvport->_fix_phy_param._fix_phy(mvport); 401 } 402 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 403 wdcattach(sc->sc_ata_channels[channel]); 404 405 return 0; 406 } 407 408 int 409 mvsata_intr(struct mvsata_hc *mvhc) 410 { 411 struct mvsata_softc *sc = mvhc->hc_sc; 412 struct mvsata_port *mvport; 413 uint32_t cause; 414 int port, handled = 0; 415 416 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 417 418 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 419 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 420 421 if (cause & SATAHC_IC_SAINTCOAL) 422 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 423 cause &= ~SATAHC_IC_SAINTCOAL; 424 425 for (port = 0; port < sc->sc_port; port++) { 426 mvport = mvhc->hc_ports[port]; 427 428 if (cause & SATAHC_IC_DONE(port)) { 429 #ifndef MVSATA_WITHOUTDMA 430 handled = mvsata_edma_handle(mvport, NULL); 431 #endif 432 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 433 ~SATAHC_IC_DONE(port)); 434 } 435 436 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 437 (void) mvsata_nondma_handle(mvport); 438 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 439 ~SATAHC_IC_SADEVINTERRUPT(port)); 440 handled = 1; 441 } 442 } 443 444 return handled; 445 } 446 447 static int 448 mvsata_nondma_handle(struct mvsata_port *mvport) 449 { 450 struct ata_channel *chp = &mvport->port_ata_channel; 451 struct ata_xfer *xfer; 452 int ret; 453 454 /* 455 * The chip doesn't support several pending non-DMA commands, 456 * and the ata middle layer never issues several non-NCQ commands, 457 * so there must be exactly one active command at this moment. 458 */ 459 xfer = ata_queue_get_active_xfer(chp); 460 if (xfer == NULL) { 461 /* Can happen after error recovery, ignore */ 462 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 463 ("%s:%d: %s: intr without xfer\n", 464 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 465 __func__)); 466 return 0; 467 } 468 469 ret = xfer->ops->c_intr(chp, xfer, 1); 470 return (ret); 471 } 472 473 int 474 mvsata_error(struct mvsata_port *mvport) 475 { 476 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 477 uint32_t cause; 478 479 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 480 /* 481 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 482 * in EDMA_IEC. 483 */ 484 if (cause & EDMA_IE_SERRINT) { 485 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 486 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 487 } 488 if (cause & EDMA_IE_ETRANSINT) { 489 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 490 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 491 } 492 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 493 494 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 495 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 496 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 497 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 498 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 499 500 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 501 if (!cause) 502 return 0; 503 504 if (cause & EDMA_IE_EDEVDIS) { 505 aprint_normal("%s:%d:%d: device disconnect\n", 506 device_xname(MVSATA_DEV2(mvport)), 507 mvport->port_hc->hc, mvport->port); 508 } 509 if (cause & EDMA_IE_EDEVCON) { 510 if (sc->sc_gen == gen1) 511 mvsata_devconn_gen1(mvport); 512 513 DPRINTF(DEBUG_INTR, (" device connected\n")); 514 } 515 516 #ifndef MVSATA_WITHOUTDMA 517 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 518 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 519 switch (mvport->port_edmamode_curr) { 520 case dma: 521 case queued: 522 case ncq: 523 mvsata_edma_reset_qptr(mvport); 524 mvsata_edma_enable(mvport); 525 if (cause & EDMA_IE_EDEVERR) 526 break; 527 528 /* FALLTHROUGH */ 529 530 case nodma: 531 default: 532 aprint_error( 533 "%s:%d:%d: EDMA self disable happen 0x%x\n", 534 device_xname(MVSATA_DEV2(mvport)), 535 mvport->port_hc->hc, mvport->port, cause); 536 break; 537 } 538 } 539 #endif 540 if (cause & EDMA_IE_ETRANSINT) { 541 /* hot plug the Port Multiplier */ 542 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 543 device_xname(MVSATA_DEV2(mvport)), 544 mvport->port_hc->hc, mvport->port); 545 } 546 if (cause & EDMA_IE_EDEVERR) { 547 struct ata_channel *chp = &mvport->port_ata_channel; 548 549 aprint_error("%s:%d:%d: device error, recovering\n", 550 device_xname(MVSATA_DEV2(mvport)), 551 mvport->port_hc->hc, mvport->port); 552 553 ata_channel_lock(chp); 554 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, 555 ATACH_ERR_ST(0, WDCS_ERR)); 556 ata_channel_unlock(chp); 557 } 558 559 return 1; 560 } 561 562 #ifndef MVSATA_WITHOUTDMA 563 static void 564 mvsata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 565 { 566 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 567 int drive; 568 569 ata_channel_lock_owned(chp); 570 571 if (chp->ch_ndrives > PMP_PORT_CTL) { 572 /* Get PM port number for the device in error. This device 573 * doesn't seem to have dedicated register for this, so just 574 * assume last selected port was the one. */ 575 /* XXX FIS-based switching */ 576 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 577 } else 578 drive = 0; 579 580 /* 581 * Controller doesn't need any special action. Simply execute 582 * READ LOG EXT for NCQ to unblock device processing, then continue 583 * as if nothing happened. 584 */ 585 586 ata_recovery_resume(chp, drive, tfd, AT_POLL); 587 588 /* Drive unblocked, back to normal operation */ 589 return; 590 } 591 #endif /* !MVSATA_WITHOUTDMA */ 592 593 /* 594 * ATA callback entry points 595 */ 596 597 static void 598 mvsata_probe_drive(struct ata_channel *chp) 599 { 600 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 601 uint32_t sstat, sig; 602 603 ata_channel_lock(chp); 604 605 sstat = sata_reset_interface(chp, mvport->port_iot, 606 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 607 switch (sstat) { 608 case SStatus_DET_DEV: 609 mvsata_pmp_select(mvport, PMP_PORT_CTL); 610 sig = mvsata_softreset(mvport, AT_WAIT); 611 sata_interpret_sig(chp, 0, sig); 612 break; 613 default: 614 break; 615 } 616 617 ata_channel_unlock(chp); 618 } 619 620 #ifndef MVSATA_WITHOUTDMA 621 static void 622 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 623 { 624 struct ata_channel *chp = drvp->chnl_softc; 625 struct mvsata_port *mvport = (struct mvsata_port *)chp; 626 uint32_t edma_c; 627 uint32_t sig; 628 629 ata_channel_lock_owned(chp); 630 631 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 632 633 DPRINTF(DEBUG_FUNCS, 634 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 635 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 636 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 637 638 if (edma_c & EDMA_CMD_EENEDMA) 639 mvsata_edma_disable(mvport, 10000, flags); 640 641 mvsata_pmp_select(mvport, drvp->drive); 642 643 sig = mvsata_softreset(mvport, flags); 644 645 if (sigp) 646 *sigp = sig; 647 648 if (edma_c & EDMA_CMD_EENEDMA) { 649 mvsata_edma_reset_qptr(mvport); 650 mvsata_edma_enable(mvport); 651 } 652 } 653 654 static void 655 mvsata_reset_channel(struct ata_channel *chp, int flags) 656 { 657 struct mvsata_port *mvport = (struct mvsata_port *)chp; 658 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 659 uint32_t sstat, ctrl; 660 661 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 662 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 663 664 ata_channel_lock_owned(chp); 665 666 mvsata_hreset_port(mvport); 667 sstat = sata_reset_interface(chp, mvport->port_iot, 668 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 669 670 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 671 sc->sc_gen != gen1) { 672 /* Downgrade to GenI */ 673 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 674 SControl_DET_DISABLE; 675 676 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 677 678 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 679 ctrl &= ~(1 << 17); /* Disable GenII */ 680 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 681 682 mvsata_hreset_port(mvport); 683 sata_reset_interface(chp, mvport->port_iot, 684 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 685 flags); 686 } 687 688 ata_kill_active(chp, KILL_RESET, flags); 689 690 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 691 mvsata_edma_reset_qptr(mvport); 692 mvsata_edma_enable(mvport); 693 } 694 695 static int 696 mvsata_addref(struct ata_drive_datas *drvp) 697 { 698 699 return 0; 700 } 701 702 static void 703 mvsata_delref(struct ata_drive_datas *drvp) 704 { 705 706 return; 707 } 708 709 static void 710 mvsata_killpending(struct ata_drive_datas *drvp) 711 { 712 713 return; 714 } 715 716 #if NATAPIBUS > 0 717 static void 718 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 719 { 720 struct ata_channel *chp = ata_sc->sc_chan; 721 struct atac_softc *atac = chp->ch_atac; 722 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 723 struct scsipi_channel *chan = &chp->ch_atapi_channel; 724 725 /* 726 * Fill in the scsipi_adapter. 727 */ 728 adapt->adapt_dev = atac->atac_dev; 729 adapt->adapt_nchannels = atac->atac_nchannels; 730 adapt->adapt_request = mvsata_atapi_scsipi_request; 731 adapt->adapt_minphys = mvsata_atapi_minphys; 732 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 733 734 /* 735 * Fill in the scsipi_channel. 736 */ 737 memset(chan, 0, sizeof(*chan)); 738 chan->chan_adapter = adapt; 739 chan->chan_bustype = &mvsata_atapi_bustype; 740 chan->chan_channel = chp->ch_channel; 741 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 742 chan->chan_openings = 1; 743 chan->chan_max_periph = 1; 744 chan->chan_ntargets = 1; 745 chan->chan_nluns = 1; 746 747 chp->atapibus = 748 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 749 } 750 751 static void 752 mvsata_atapi_minphys(struct buf *bp) 753 { 754 755 if (bp->b_bcount > MAXPHYS) 756 bp->b_bcount = MAXPHYS; 757 minphys(bp); 758 } 759 760 static void 761 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 762 { 763 struct scsipi_channel *chan = sc->sc_channel; 764 struct scsipi_periph *periph; 765 struct ataparams ids; 766 struct ataparams *id = &ids; 767 struct mvsata_softc *mvc = 768 device_private(chan->chan_adapter->adapt_dev); 769 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 770 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 771 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 772 struct scsipibus_attach_args sa; 773 char serial_number[21], model[41], firmware_revision[9]; 774 int s; 775 776 /* skip if already attached */ 777 if (scsipi_lookup_periph(chan, target, 0) != NULL) 778 return; 779 780 /* if no ATAPI device detected at attach time, skip */ 781 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 782 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 783 " drive %d not present\n", 784 device_xname(atac->atac_dev), chp->ch_channel, target)); 785 return; 786 } 787 788 /* Some ATAPI devices need a bit more time after software reset. */ 789 delay(5000); 790 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 791 #ifdef ATAPI_DEBUG_PROBE 792 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 793 device_xname(sc->sc_dev), target, 794 id->atap_config & ATAPI_CFG_CMD_MASK, 795 id->atap_config & ATAPI_CFG_DRQ_MASK); 796 #endif 797 periph = scsipi_alloc_periph(M_NOWAIT); 798 if (periph == NULL) { 799 aprint_error_dev(atac->atac_dev, 800 "unable to allocate periph" 801 " for channel %d drive %d\n", 802 chp->ch_channel, target); 803 return; 804 } 805 periph->periph_dev = NULL; 806 periph->periph_channel = chan; 807 periph->periph_switch = &atapi_probe_periphsw; 808 periph->periph_target = target; 809 periph->periph_lun = 0; 810 periph->periph_quirks = PQUIRK_ONLYBIG; 811 812 #ifdef SCSIPI_DEBUG 813 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 814 SCSIPI_DEBUG_TARGET == target) 815 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 816 #endif 817 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 818 if (id->atap_config & ATAPI_CFG_REMOV) 819 periph->periph_flags |= PERIPH_REMOVABLE; 820 if (periph->periph_type == T_SEQUENTIAL) { 821 s = splbio(); 822 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 823 splx(s); 824 } 825 826 sa.sa_periph = periph; 827 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 828 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 829 T_REMOV : T_FIXED; 830 strnvisx(model, sizeof(model), id->atap_model, 40, 831 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 832 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 833 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 834 strnvisx(firmware_revision, sizeof(firmware_revision), 835 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 836 sa.sa_inqbuf.vendor = model; 837 sa.sa_inqbuf.product = serial_number; 838 sa.sa_inqbuf.revision = firmware_revision; 839 840 /* 841 * Determine the operating mode capabilities of the device. 842 */ 843 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 844 periph->periph_cap |= PERIPH_CAP_CMD16; 845 /* XXX This is gross. */ 846 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 847 848 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 849 850 if (drvp->drv_softc) 851 ata_probe_caps(drvp); 852 else { 853 s = splbio(); 854 drvp->drive_type = ATA_DRIVET_NONE; 855 splx(s); 856 } 857 } else { 858 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 859 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 860 device_xname(atac->atac_dev), chp->ch_channel, target)); 861 s = splbio(); 862 drvp->drive_type = ATA_DRIVET_NONE; 863 splx(s); 864 } 865 } 866 867 /* 868 * Kill off all pending xfers for a periph. 869 * 870 * Must be called at splbio(). 871 */ 872 static void 873 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 874 { 875 struct atac_softc *atac = 876 device_private(periph->periph_channel->chan_adapter->adapt_dev); 877 struct ata_channel *chp = 878 atac->atac_channels[periph->periph_channel->chan_channel]; 879 880 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 881 } 882 #endif /* NATAPIBUS > 0 */ 883 #endif /* MVSATA_WITHOUTDMA */ 884 885 886 /* 887 * mvsata_setup_channel() 888 * Setup EDMA registers and prepare/purge DMA resources. 889 * We assuming already stopped the EDMA. 890 */ 891 static void 892 mvsata_setup_channel(struct ata_channel *chp) 893 { 894 #ifndef MVSATA_WITHOUTDMA 895 struct mvsata_port *mvport = (struct mvsata_port *)chp; 896 struct ata_drive_datas *drvp; 897 int drive, s; 898 uint32_t edma_mode = nodma; 899 int i; 900 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 901 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 902 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 903 904 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 905 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 906 907 for (drive = 0; drive < chp->ch_ndrives; drive++) { 908 drvp = &chp->ch_drive[drive]; 909 910 /* If no drive, skip */ 911 if (drvp->drive_type == ATA_DRIVET_NONE) 912 continue; 913 914 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 915 /* use Ultra/DMA */ 916 s = splbio(); 917 drvp->drive_flags &= ~ATA_DRIVE_DMA; 918 splx(s); 919 } 920 921 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 922 if (drvp->drive_flags & ATA_DRIVE_NCQ) 923 edma_mode = ncq; 924 else if (drvp->drive_type == ATA_DRIVET_ATA) 925 edma_mode = dma; 926 } 927 } 928 929 DPRINTF(DEBUG_FUNCS, 930 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 931 932 if (edma_mode == nodma) { 933 no_edma: 934 if (mvport->port_crqb != NULL) 935 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 936 mvport->port_crqb_dmamap, mvport->port_crqb); 937 if (mvport->port_crpb != NULL) 938 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 939 mvport->port_crpb_dmamap, mvport->port_crpb); 940 if (mvport->port_eprd != NULL) 941 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 942 mvport->port_eprd_dmamap, mvport->port_eprd); 943 944 return; 945 } 946 947 if (mvport->port_crqb == NULL) 948 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 949 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 950 if (mvport->port_crpb == NULL) 951 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 952 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 953 if (mvport->port_eprd == NULL) { 954 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 955 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 956 1); 957 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 958 mvport->port_reqtbl[i].eprd_offset = 959 i * MVSATA_EPRD_MAX_SIZE; 960 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 961 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 962 } 963 } 964 965 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 966 mvport->port_eprd == NULL) { 967 aprint_error_dev(MVSATA_DEV2(mvport), 968 "channel %d: can't use EDMA\n", chp->ch_channel); 969 s = splbio(); 970 for (drive = 0; drive < chp->ch_ndrives; drive++) { 971 drvp = &chp->ch_drive[drive]; 972 973 /* If no drive, skip */ 974 if (drvp->drive_type == ATA_DRIVET_NONE) 975 continue; 976 977 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 978 } 979 splx(s); 980 goto no_edma; 981 } 982 983 mvsata_edma_config(mvport, edma_mode); 984 mvsata_edma_reset_qptr(mvport); 985 mvsata_edma_enable(mvport); 986 #endif 987 } 988 989 #ifndef MVSATA_WITHOUTDMA 990 static const struct ata_xfer_ops mvsata_bio_xfer_ops = { 991 .c_start = mvsata_bio_start, 992 .c_intr = mvsata_bio_intr, 993 .c_poll = mvsata_bio_poll, 994 .c_abort = mvsata_bio_done, 995 .c_kill_xfer = mvsata_bio_kill_xfer, 996 }; 997 998 static int 999 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1000 { 1001 struct ata_channel *chp = drvp->chnl_softc; 1002 struct atac_softc *atac = chp->ch_atac; 1003 struct ata_bio *ata_bio = &xfer->c_bio; 1004 1005 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1006 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 1007 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 1008 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 1009 1010 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1011 ata_bio->flags |= ATA_POLL; 1012 if (ata_bio->flags & ATA_POLL) 1013 xfer->c_flags |= C_POLL; 1014 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1015 (ata_bio->flags & ATA_SINGLE) == 0) 1016 xfer->c_flags |= C_DMA; 1017 xfer->c_drive = drvp->drive; 1018 xfer->c_databuf = ata_bio->databuf; 1019 xfer->c_bcount = ata_bio->bcount; 1020 xfer->ops = &mvsata_bio_xfer_ops; 1021 ata_exec_xfer(chp, xfer); 1022 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1023 } 1024 1025 static int 1026 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1027 { 1028 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1029 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1030 struct atac_softc *atac = chp->ch_atac; 1031 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1032 struct ata_bio *ata_bio = &xfer->c_bio; 1033 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1034 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1035 u_int16_t cyl; 1036 u_int8_t head, sect, cmd = 0; 1037 int nblks, error, tfd; 1038 1039 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1040 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1041 1042 ata_channel_lock_owned(chp); 1043 1044 if (xfer->c_flags & C_DMA) 1045 if (drvp->n_xfers <= NXFER) 1046 drvp->n_xfers++; 1047 1048 /* 1049 * 1050 * When starting a multi-sector transfer, or doing single-sector 1051 * transfers... 1052 */ 1053 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1054 if (ata_bio->flags & ATA_SINGLE) 1055 nblks = 1; 1056 else 1057 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1058 /* Check for bad sectors and adjust transfer, if necessary. */ 1059 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1060 long blkdiff; 1061 int i; 1062 1063 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1064 i++) { 1065 blkdiff -= ata_bio->blkno; 1066 if (blkdiff < 0) 1067 continue; 1068 if (blkdiff == 0) 1069 /* Replace current block of transfer. */ 1070 ata_bio->blkno = 1071 drvp->lp->d_secperunit - 1072 drvp->lp->d_nsectors - i - 1; 1073 if (blkdiff < nblks) { 1074 /* Bad block inside transfer. */ 1075 ata_bio->flags |= ATA_SINGLE; 1076 nblks = 1; 1077 } 1078 break; 1079 } 1080 /* Transfer is okay now. */ 1081 } 1082 if (xfer->c_flags & C_DMA) { 1083 enum mvsata_edmamode dmamode; 1084 1085 ata_bio->nblks = nblks; 1086 ata_bio->nbytes = xfer->c_bcount; 1087 1088 /* switch to appropriate dma mode if necessary */ 1089 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1090 if (mvport->port_edmamode_curr != dmamode) 1091 mvsata_edma_config(mvport, dmamode); 1092 1093 if (xfer->c_flags & C_POLL) 1094 sc->sc_enable_intr(mvport, 0 /*off*/); 1095 error = mvsata_edma_enqueue(mvport, xfer); 1096 if (error) { 1097 if (error == EINVAL) { 1098 /* 1099 * We can't do DMA on this transfer 1100 * for some reason. Fall back to 1101 * PIO. 1102 */ 1103 xfer->c_flags &= ~C_DMA; 1104 error = 0; 1105 goto do_pio; 1106 } 1107 if (error == EBUSY) { 1108 aprint_error_dev(atac->atac_dev, 1109 "channel %d: EDMA Queue full\n", 1110 chp->ch_channel); 1111 /* 1112 * XXX: Perhaps, after it waits for 1113 * a while, it is necessary to call 1114 * bio_start again. 1115 */ 1116 } 1117 ata_bio->error = ERR_DMA; 1118 ata_bio->r_error = 0; 1119 return ATASTART_ABORT; 1120 } 1121 chp->ch_flags |= ATACH_DMA_WAIT; 1122 /* start timeout machinery */ 1123 if ((xfer->c_flags & C_POLL) == 0) 1124 callout_reset(&chp->c_timo_callout, 1125 mstohz(ATA_DELAY), ata_timeout, chp); 1126 /* wait for irq */ 1127 goto intr; 1128 } /* else not DMA */ 1129 do_pio: 1130 if (ata_bio->flags & ATA_LBA48) { 1131 sect = 0; 1132 cyl = 0; 1133 head = 0; 1134 } else if (ata_bio->flags & ATA_LBA) { 1135 sect = (ata_bio->blkno >> 0) & 0xff; 1136 cyl = (ata_bio->blkno >> 8) & 0xffff; 1137 head = (ata_bio->blkno >> 24) & 0x0f; 1138 head |= WDSD_LBA; 1139 } else { 1140 int blkno = ata_bio->blkno; 1141 sect = blkno % drvp->lp->d_nsectors; 1142 sect++; /* Sectors begin with 1, not 0. */ 1143 blkno /= drvp->lp->d_nsectors; 1144 head = blkno % drvp->lp->d_ntracks; 1145 blkno /= drvp->lp->d_ntracks; 1146 cyl = blkno; 1147 head |= WDSD_CHS; 1148 } 1149 ata_bio->nblks = uimin(nblks, drvp->multi); 1150 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1151 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1152 if (ata_bio->nblks > 1) 1153 cmd = (ata_bio->flags & ATA_READ) ? 1154 WDCC_READMULTI : WDCC_WRITEMULTI; 1155 else 1156 cmd = (ata_bio->flags & ATA_READ) ? 1157 WDCC_READ : WDCC_WRITE; 1158 1159 /* EDMA disable, if enabled this channel. */ 1160 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1161 if (mvport->port_edmamode_curr != nodma) 1162 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1163 1164 mvsata_pmp_select(mvport, xfer->c_drive); 1165 1166 /* Do control operations specially. */ 1167 if (__predict_false(drvp->state < READY)) { 1168 /* 1169 * Actually, we want to be careful not to mess with 1170 * the control state if the device is currently busy, 1171 * but we can assume that we never get to this point 1172 * if that's the case. 1173 */ 1174 /* 1175 * If it's not a polled command, we need the kernel 1176 * thread 1177 */ 1178 if ((xfer->c_flags & C_POLL) == 0 && 1179 (chp->ch_flags & ATACH_TH_RUN) == 0) { 1180 return ATASTART_TH; 1181 } 1182 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1183 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1184 return ATASTART_ABORT; 1185 } 1186 } 1187 1188 /* Initiate command! */ 1189 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1190 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1191 case WDCWAIT_OK: 1192 break; 1193 case WDCWAIT_TOUT: 1194 goto timeout; 1195 case WDCWAIT_THR: 1196 return ATASTART_TH; 1197 } 1198 if (ata_bio->flags & ATA_LBA48) 1199 wdccommandext(chp, 0, atacmd_to48(cmd), 1200 ata_bio->blkno, nblks, 0, WDSD_LBA); 1201 else 1202 wdccommand(chp, 0, cmd, cyl, 1203 head, sect, nblks, 1204 (drvp->lp->d_type == DKTYPE_ST506) ? 1205 drvp->lp->d_precompcyl / 4 : 0); 1206 1207 /* start timeout machinery */ 1208 if ((xfer->c_flags & C_POLL) == 0) 1209 callout_reset(&chp->c_timo_callout, 1210 mstohz(ATA_DELAY), wdctimeout, chp); 1211 } else if (ata_bio->nblks > 1) { 1212 /* The number of blocks in the last stretch may be smaller. */ 1213 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1214 if (ata_bio->nblks > nblks) { 1215 ata_bio->nblks = nblks; 1216 ata_bio->nbytes = xfer->c_bcount; 1217 } 1218 } 1219 /* If this was a write and not using DMA, push the data. */ 1220 if ((ata_bio->flags & ATA_READ) == 0) { 1221 /* 1222 * we have to busy-wait here, we can't rely on running in 1223 * thread context. 1224 */ 1225 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1226 aprint_error_dev(atac->atac_dev, 1227 "channel %d: drive %d timeout waiting for DRQ," 1228 " st=0x%02x, err=0x%02x\n", 1229 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1230 ATACH_ERR(tfd)); 1231 ata_bio->error = TIMEOUT; 1232 return ATASTART_ABORT; 1233 } 1234 if (ATACH_ST(tfd) & WDCS_ERR) { 1235 ata_bio->error = ERROR; 1236 ata_bio->r_error = ATACH_ERR(tfd); 1237 mvsata_bio_done(chp, xfer); 1238 return ATASTART_ABORT; 1239 } 1240 1241 wdc->dataout_pio(chp, drvp->drive_flags, 1242 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1243 } 1244 1245 intr: 1246 KASSERTMSG(((xfer->c_flags & C_DMA) != 0) 1247 == (mvport->port_edmamode_curr != nodma), 1248 "DMA mode mismatch: flags %x vs edmamode %d != %d", 1249 xfer->c_flags, mvport->port_edmamode_curr, nodma); 1250 1251 /* Wait for IRQ (either real or polled) */ 1252 if ((ata_bio->flags & ATA_POLL) != 0) 1253 return ATASTART_POLL; 1254 else 1255 return ATASTART_STARTED; 1256 1257 timeout: 1258 aprint_error_dev(atac->atac_dev, 1259 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1260 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1261 ata_bio->error = TIMEOUT; 1262 return ATASTART_ABORT; 1263 } 1264 1265 static void 1266 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1267 { 1268 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1269 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1270 1271 /* Wait for at last 400ns for status bit to be valid */ 1272 delay(1); 1273 if (chp->ch_flags & ATACH_DMA_WAIT) { 1274 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1275 sc->sc_enable_intr(mvport, 1 /*on*/); 1276 chp->ch_flags &= ~ATACH_DMA_WAIT; 1277 } 1278 1279 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1280 KASSERT(xfer->c_flags & C_TIMEOU); 1281 mvsata_bio_intr(chp, xfer, 0); 1282 } 1283 } 1284 1285 static int 1286 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int intr_arg) 1287 { 1288 struct atac_softc *atac = chp->ch_atac; 1289 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1290 struct ata_bio *ata_bio = &xfer->c_bio; 1291 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1292 int irq = ISSET(xfer->c_flags, (C_POLL|C_TIMEOU)) ? 0 : 1; 1293 int tfd = 0; 1294 1295 if (ISSET(xfer->c_flags, C_DMA|C_RECOVERED) && irq) { 1296 /* Invoked via mvsata_edma_handle() or recovery */ 1297 tfd = intr_arg; 1298 1299 if (tfd > 0 && ata_bio->error == NOERROR) { 1300 if (ATACH_ST(tfd) & WDCS_ERR) 1301 ata_bio->error = ERROR; 1302 if (ATACH_ST(tfd) & WDCS_BSY) 1303 ata_bio->error = TIMEOUT; 1304 ata_bio->r_error = ATACH_ERR(tfd); 1305 } 1306 } 1307 1308 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1309 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1310 xfer->c_drive)); 1311 1312 /* Cleanup EDMA if invoked from wdctimeout()/ata_timeout() */ 1313 if (ISSET(xfer->c_flags, C_TIMEOU) && ISSET(xfer->c_flags, C_DMA) 1314 && !ISSET(xfer->c_flags, C_POLL)) { 1315 mvsata_edma_rqq_remove((struct mvsata_port *)chp, xfer); 1316 } 1317 1318 ata_channel_lock(chp); 1319 1320 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1321 1322 /* 1323 * If we missed an interrupt transfer, reset and restart. 1324 * Don't try to continue transfer, we may have missed cycles. 1325 */ 1326 if (xfer->c_flags & C_TIMEOU) { 1327 ata_bio->error = TIMEOUT; 1328 ata_channel_unlock(chp); 1329 mvsata_bio_done(chp, xfer); 1330 return 1; 1331 } 1332 1333 /* Is it not a transfer, but a control operation? */ 1334 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1335 aprint_error_dev(atac->atac_dev, 1336 "channel %d: drive %d bad state %d in %s\n", 1337 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1338 panic("%s: bad state", __func__); 1339 } 1340 1341 /* Ack interrupt done by wdc_wait_for_unbusy */ 1342 if (!(xfer->c_flags & C_DMA) && 1343 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1344 == WDCWAIT_TOUT)) { 1345 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1346 ata_channel_unlock(chp); 1347 return 0; /* IRQ was not for us */ 1348 } 1349 aprint_error_dev(atac->atac_dev, 1350 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1351 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1352 xfer->c_skip); 1353 ata_bio->error = TIMEOUT; 1354 ata_channel_unlock(chp); 1355 mvsata_bio_done(chp, xfer); 1356 return 1; 1357 } 1358 1359 if (xfer->c_flags & C_DMA) { 1360 if (ata_bio->error == NOERROR) 1361 goto end; 1362 if (ata_bio->error == ERR_DMA) { 1363 ata_dmaerr(drvp, 1364 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1365 ata_channel_unlock(chp); 1366 goto err; 1367 } 1368 } 1369 1370 /* if we had an error, end */ 1371 if (ata_bio->error != NOERROR) { 1372 ata_channel_unlock(chp); 1373 err: 1374 mvsata_bio_done(chp, xfer); 1375 return 1; 1376 } 1377 1378 /* If this was a read and not using DMA, fetch the data. */ 1379 if ((ata_bio->flags & ATA_READ) != 0) { 1380 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1381 aprint_error_dev(atac->atac_dev, 1382 "channel %d: drive %d read intr before drq\n", 1383 chp->ch_channel, xfer->c_drive); 1384 ata_bio->error = TIMEOUT; 1385 ata_channel_unlock(chp); 1386 mvsata_bio_done(chp, xfer); 1387 return 1; 1388 } 1389 wdc->datain_pio(chp, drvp->drive_flags, 1390 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1391 } 1392 1393 end: 1394 ata_bio->blkno += ata_bio->nblks; 1395 ata_bio->blkdone += ata_bio->nblks; 1396 xfer->c_skip += ata_bio->nbytes; 1397 xfer->c_bcount -= ata_bio->nbytes; 1398 1399 /* See if this transfer is complete. */ 1400 if (xfer->c_bcount > 0) { 1401 if ((ata_bio->flags & ATA_POLL) == 0) { 1402 /* Start the next operation */ 1403 ata_xfer_start(xfer); 1404 } else { 1405 /* Let mvsata_bio_start do the loop */ 1406 } 1407 ata_channel_unlock(chp); 1408 } else { /* Done with this transfer */ 1409 ata_bio->error = NOERROR; 1410 ata_channel_unlock(chp); 1411 mvsata_bio_done(chp, xfer); 1412 } 1413 return 1; 1414 } 1415 1416 static void 1417 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1418 { 1419 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1420 struct atac_softc *atac = chp->ch_atac; 1421 struct ata_bio *ata_bio = &xfer->c_bio; 1422 int drive = xfer->c_drive; 1423 bool deactivate = true; 1424 1425 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1426 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1427 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1428 1429 /* EDMA restart, if enabled */ 1430 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1431 mvsata_edma_reset_qptr(mvport); 1432 mvsata_edma_enable(mvport); 1433 } 1434 1435 ata_bio->flags |= ATA_ITSDONE; 1436 switch (reason) { 1437 case KILL_GONE_INACTIVE: 1438 deactivate = false; 1439 /* FALLTHROUGH */ 1440 case KILL_GONE: 1441 ata_bio->error = ERR_NODEV; 1442 break; 1443 case KILL_RESET: 1444 ata_bio->error = ERR_RESET; 1445 break; 1446 case KILL_REQUEUE: 1447 ata_bio->error = REQUEUE; 1448 break; 1449 default: 1450 aprint_error_dev(atac->atac_dev, 1451 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1452 panic("mvsata_bio_kill_xfer"); 1453 } 1454 ata_bio->r_error = WDCE_ABRT; 1455 1456 if (deactivate) 1457 ata_deactivate_xfer(chp, xfer); 1458 1459 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1460 } 1461 1462 static void 1463 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1464 { 1465 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1466 struct ata_bio *ata_bio = &xfer->c_bio; 1467 int drive = xfer->c_drive; 1468 bool iserror = (ata_bio->error != NOERROR); 1469 1470 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1471 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1472 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1473 (u_int)xfer->c_flags)); 1474 1475 /* EDMA restart, if enabled */ 1476 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1477 mvsata_edma_reset_qptr(mvport); 1478 mvsata_edma_enable(mvport); 1479 } 1480 1481 if (ata_waitdrain_xfer_check(chp, xfer)) 1482 return; 1483 1484 /* feed back residual bcount to our caller */ 1485 ata_bio->bcount = xfer->c_bcount; 1486 1487 /* mark controller inactive and free xfer */ 1488 ata_deactivate_xfer(chp, xfer); 1489 1490 ata_bio->flags |= ATA_ITSDONE; 1491 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1492 if (!iserror) 1493 atastart(chp); 1494 } 1495 1496 static int 1497 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1498 int flags) 1499 { 1500 struct ata_channel *chp = &mvport->port_ata_channel; 1501 struct atac_softc *atac = chp->ch_atac; 1502 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1503 const char *errstring; 1504 int tfd; 1505 1506 flags |= AT_POLL; /* XXX */ 1507 1508 ata_channel_lock_owned(chp); 1509 1510 /* 1511 * disable interrupts, all commands here should be quick 1512 * enough to be able to poll, and we don't go here that often 1513 */ 1514 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1515 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1516 DELAY(10); 1517 errstring = "wait"; 1518 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1519 goto ctrltimeout; 1520 wdccommandshort(chp, 0, WDCC_RECAL); 1521 /* Wait for at least 400ns for status bit to be valid */ 1522 DELAY(1); 1523 errstring = "recal"; 1524 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1525 goto ctrltimeout; 1526 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1527 goto ctrlerror; 1528 /* Don't try to set modes if controller can't be adjusted */ 1529 if (atac->atac_set_modes == NULL) 1530 goto geometry; 1531 /* Also don't try if the drive didn't report its mode */ 1532 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1533 goto geometry; 1534 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1535 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1536 errstring = "piomode-bio"; 1537 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1538 goto ctrltimeout; 1539 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1540 goto ctrlerror; 1541 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1542 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1543 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1544 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1545 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1546 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1547 else 1548 goto geometry; 1549 errstring = "dmamode-bio"; 1550 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1551 goto ctrltimeout; 1552 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1553 goto ctrlerror; 1554 geometry: 1555 if (ata_bio->flags & ATA_LBA) 1556 goto multimode; 1557 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1558 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1559 (drvp->lp->d_type == DKTYPE_ST506) ? 1560 drvp->lp->d_precompcyl / 4 : 0); 1561 errstring = "geometry"; 1562 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1563 goto ctrltimeout; 1564 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1565 goto ctrlerror; 1566 multimode: 1567 if (drvp->multi == 1) 1568 goto ready; 1569 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1570 errstring = "setmulti"; 1571 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1572 goto ctrltimeout; 1573 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1574 goto ctrlerror; 1575 ready: 1576 drvp->state = READY; 1577 /* 1578 * The drive is usable now 1579 */ 1580 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1581 delay(10); /* some drives need a little delay here */ 1582 return 0; 1583 1584 ctrltimeout: 1585 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1586 chp->ch_channel, drive, errstring); 1587 ata_bio->error = TIMEOUT; 1588 goto ctrldone; 1589 ctrlerror: 1590 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1591 chp->ch_channel, drive, errstring); 1592 if (ATACH_ST(tfd) & WDCS_DWF) { 1593 aprint_error("drive fault\n"); 1594 ata_bio->error = ERR_DF; 1595 } else { 1596 ata_bio->r_error = ATACH_ERR(tfd); 1597 ata_bio->error = ERROR; 1598 aprint_error("error (%x)\n", ata_bio->r_error); 1599 } 1600 ctrldone: 1601 drvp->state = 0; 1602 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1603 return -1; 1604 } 1605 1606 static const struct ata_xfer_ops mvsata_wdc_cmd_xfer_ops = { 1607 .c_start = mvsata_wdc_cmd_start, 1608 .c_intr = mvsata_wdc_cmd_intr, 1609 .c_poll = mvsata_wdc_cmd_poll, 1610 .c_abort = mvsata_wdc_cmd_done, 1611 .c_kill_xfer = mvsata_wdc_cmd_kill_xfer, 1612 }; 1613 1614 static int 1615 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1616 { 1617 struct ata_channel *chp = drvp->chnl_softc; 1618 struct ata_command *ata_c = &xfer->c_ata_c; 1619 int rv, s; 1620 1621 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1622 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1623 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1624 " r_device=0x%02x, r_command=0x%02x\n", 1625 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1626 chp->ch_channel, 1627 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1628 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1629 1630 if (ata_c->flags & AT_POLL) 1631 xfer->c_flags |= C_POLL; 1632 if (ata_c->flags & AT_WAIT) 1633 xfer->c_flags |= C_WAIT; 1634 xfer->c_drive = drvp->drive; 1635 xfer->c_databuf = ata_c->data; 1636 xfer->c_bcount = ata_c->bcount; 1637 xfer->ops = &mvsata_wdc_cmd_xfer_ops; 1638 s = splbio(); 1639 ata_exec_xfer(chp, xfer); 1640 #ifdef DIAGNOSTIC 1641 if ((ata_c->flags & AT_POLL) != 0 && 1642 (ata_c->flags & AT_DONE) == 0) 1643 panic("mvsata_exec_command: polled command not done"); 1644 #endif 1645 if (ata_c->flags & AT_DONE) 1646 rv = ATACMD_COMPLETE; 1647 else { 1648 if (ata_c->flags & AT_WAIT) { 1649 ata_wait_cmd(chp, xfer); 1650 rv = ATACMD_COMPLETE; 1651 } else 1652 rv = ATACMD_QUEUED; 1653 } 1654 splx(s); 1655 return rv; 1656 } 1657 1658 static int 1659 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1660 { 1661 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1662 int drive = xfer->c_drive; 1663 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1664 struct ata_command *ata_c = &xfer->c_ata_c; 1665 int tfd; 1666 1667 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1668 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1669 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1670 1671 ata_channel_lock_owned(chp); 1672 1673 /* First, EDMA disable, if enabled this channel. */ 1674 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1675 if (mvport->port_edmamode_curr != nodma) 1676 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1677 1678 mvsata_pmp_select(mvport, drive); 1679 1680 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1681 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1682 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1683 case WDCWAIT_OK: 1684 break; 1685 case WDCWAIT_TOUT: 1686 ata_c->flags |= AT_TIMEOU; 1687 return ATASTART_ABORT; 1688 case WDCWAIT_THR: 1689 return ATASTART_TH; 1690 } 1691 if (ata_c->flags & AT_POLL) 1692 /* polled command, disable interrupts */ 1693 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1694 if ((ata_c->flags & AT_LBA48) != 0) { 1695 wdccommandext(chp, 0, ata_c->r_command, 1696 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1697 ata_c->r_device & ~0x10); 1698 } else { 1699 wdccommand(chp, 0, ata_c->r_command, 1700 (ata_c->r_lba >> 8) & 0xffff, 1701 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1702 ((ata_c->r_lba >> 24) & 0x0f), 1703 ata_c->r_lba & 0xff, 1704 ata_c->r_count & 0xff, 1705 ata_c->r_features & 0xff); 1706 } 1707 1708 if ((ata_c->flags & AT_POLL) == 0) { 1709 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1710 wdctimeout, chp); 1711 return ATASTART_STARTED; 1712 } 1713 1714 return ATASTART_POLL; 1715 } 1716 1717 static void 1718 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1719 { 1720 /* 1721 * Polled command. Wait for drive ready or drq. Done in intr(). 1722 * Wait for at last 400ns for status bit to be valid. 1723 */ 1724 delay(10); /* 400ns delay */ 1725 mvsata_wdc_cmd_intr(chp, xfer, 0); 1726 } 1727 1728 static int 1729 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1730 { 1731 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1732 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1733 struct ata_command *ata_c = &xfer->c_ata_c; 1734 int bcount = ata_c->bcount; 1735 char *data = ata_c->data; 1736 int wflags; 1737 int drive_flags; 1738 int tfd; 1739 1740 ata_channel_lock(chp); 1741 1742 if (ata_c->r_command == WDCC_IDENTIFY || 1743 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1744 /* 1745 * The IDENTIFY data has been designed as an array of 1746 * u_int16_t, so we can byteswap it on the fly. 1747 * Historically it's what we have always done so keeping it 1748 * here ensure binary backward compatibility. 1749 */ 1750 drive_flags = ATA_DRIVE_NOSTREAM | 1751 chp->ch_drive[xfer->c_drive].drive_flags; 1752 else 1753 /* 1754 * Other data structure are opaque and should be transfered 1755 * as is. 1756 */ 1757 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1758 1759 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1760 /* both wait and poll, we can kpause here */ 1761 wflags = AT_WAIT | AT_POLL; 1762 else 1763 wflags = AT_POLL; 1764 1765 again: 1766 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1767 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1768 __func__, xfer->c_drive)); 1769 1770 /* 1771 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1772 * Reselect again, it doesn't hurt for others commands, and the time 1773 * penalty for the extra register write is acceptable, 1774 * wdc_exec_command() isn't called often (mostly for autoconfig) 1775 */ 1776 if ((xfer->c_flags & C_ATAPI) != 0) { 1777 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1778 } 1779 if ((ata_c->flags & AT_XFDONE) != 0) { 1780 /* 1781 * We have completed a data xfer. The drive should now be 1782 * in its initial state 1783 */ 1784 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1785 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1786 wflags, &tfd) == WDCWAIT_TOUT) { 1787 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1788 ata_channel_unlock(chp); 1789 return 0; /* IRQ was not for us */ 1790 } 1791 ata_c->flags |= AT_TIMEOU; 1792 } 1793 goto out; 1794 } 1795 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1796 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1797 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1798 ata_channel_unlock(chp); 1799 return 0; /* IRQ was not for us */ 1800 } 1801 ata_c->flags |= AT_TIMEOU; 1802 goto out; 1803 } 1804 delay(20); /* XXXXX: Delay more times. */ 1805 if (ata_c->flags & AT_READ) { 1806 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1807 ata_c->flags |= AT_TIMEOU; 1808 goto out; 1809 } 1810 wdc->datain_pio(chp, drive_flags, data, bcount); 1811 /* at this point the drive should be in its initial state */ 1812 ata_c->flags |= AT_XFDONE; 1813 /* 1814 * XXX checking the status register again here cause some 1815 * hardware to timeout. 1816 */ 1817 } else if (ata_c->flags & AT_WRITE) { 1818 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1819 ata_c->flags |= AT_TIMEOU; 1820 goto out; 1821 } 1822 wdc->dataout_pio(chp, drive_flags, data, bcount); 1823 ata_c->flags |= AT_XFDONE; 1824 if ((ata_c->flags & AT_POLL) == 0) { 1825 callout_reset(&chp->c_timo_callout, 1826 mstohz(ata_c->timeout), wdctimeout, chp); 1827 ata_channel_unlock(chp); 1828 return 1; 1829 } else 1830 goto again; 1831 } 1832 out: 1833 if (ATACH_ST(tfd) & WDCS_DWF) 1834 ata_c->flags |= AT_DF; 1835 if (ATACH_ST(tfd) & WDCS_ERR) { 1836 ata_c->flags |= AT_ERROR; 1837 ata_c->r_error = ATACH_ERR(tfd); 1838 } 1839 ata_channel_unlock(chp); 1840 mvsata_wdc_cmd_done(chp, xfer); 1841 1842 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1843 atastart(chp); 1844 1845 return 1; 1846 } 1847 1848 static void 1849 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1850 int reason) 1851 { 1852 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1853 struct ata_command *ata_c = &xfer->c_ata_c; 1854 bool deactivate = true; 1855 1856 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1857 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1858 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1859 1860 switch (reason) { 1861 case KILL_GONE_INACTIVE: 1862 deactivate = false; 1863 /* FALLTHROUGH */ 1864 case KILL_GONE: 1865 ata_c->flags |= AT_GONE; 1866 break; 1867 case KILL_RESET: 1868 ata_c->flags |= AT_RESET; 1869 break; 1870 case KILL_REQUEUE: 1871 panic("%s: not supposed to be requeued\n", __func__); 1872 break; 1873 default: 1874 aprint_error_dev(MVSATA_DEV2(mvport), 1875 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1876 panic("mvsata_cmd_kill_xfer"); 1877 } 1878 1879 mvsata_wdc_cmd_done_end(chp, xfer); 1880 1881 if (deactivate) 1882 ata_deactivate_xfer(chp, xfer); 1883 } 1884 1885 static void 1886 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1887 { 1888 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1889 struct atac_softc *atac = chp->ch_atac; 1890 struct ata_command *ata_c = &xfer->c_ata_c; 1891 1892 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1893 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1894 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1895 ata_c->flags)); 1896 1897 if (ata_waitdrain_xfer_check(chp, xfer)) 1898 return; 1899 1900 if ((ata_c->flags & AT_READREG) != 0 && 1901 device_is_active(atac->atac_dev) && 1902 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1903 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1904 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1905 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1906 ata_c->r_lba = 1907 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1908 ata_c->r_lba |= 1909 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1910 ata_c->r_lba |= 1911 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1912 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1913 if ((ata_c->flags & AT_LBA48) != 0) { 1914 if ((ata_c->flags & AT_POLL) != 0) { 1915 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1916 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1917 } else { 1918 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1919 WDCTL_HOB|WDCTL_4BIT); 1920 } 1921 ata_c->r_count |= 1922 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1923 ata_c->r_lba |= 1924 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1925 ata_c->r_lba |= 1926 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1927 ata_c->r_lba |= 1928 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1929 if ((ata_c->flags & AT_POLL) != 0) { 1930 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1931 WDCTL_4BIT|WDCTL_IDS); 1932 } else { 1933 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1934 WDCTL_4BIT); 1935 } 1936 } else { 1937 ata_c->r_lba |= 1938 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1939 } 1940 } 1941 1942 if (ata_c->flags & AT_POLL) { 1943 /* enable interrupts */ 1944 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1945 delay(10); /* some drives need a little delay here */ 1946 } 1947 1948 mvsata_wdc_cmd_done_end(chp, xfer); 1949 1950 ata_deactivate_xfer(chp, xfer); 1951 } 1952 1953 static void 1954 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1955 { 1956 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1957 struct ata_command *ata_c = &xfer->c_ata_c; 1958 1959 /* EDMA restart, if enabled */ 1960 if (mvport->port_edmamode_curr != nodma) { 1961 mvsata_edma_reset_qptr(mvport); 1962 mvsata_edma_enable(mvport); 1963 } 1964 1965 ata_c->flags |= AT_DONE; 1966 } 1967 1968 #if NATAPIBUS > 0 1969 static const struct ata_xfer_ops mvsata_atapi_xfer_ops = { 1970 .c_start = mvsata_atapi_start, 1971 .c_intr = mvsata_atapi_intr, 1972 .c_poll = mvsata_atapi_poll, 1973 .c_abort = mvsata_atapi_reset, 1974 .c_kill_xfer = mvsata_atapi_kill_xfer, 1975 }; 1976 1977 static void 1978 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 1979 scsipi_adapter_req_t req, void *arg) 1980 { 1981 struct scsipi_adapter *adapt = chan->chan_adapter; 1982 struct scsipi_periph *periph; 1983 struct scsipi_xfer *sc_xfer; 1984 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 1985 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1986 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1987 struct ata_xfer *xfer; 1988 int drive, s; 1989 1990 switch (req) { 1991 case ADAPTER_REQ_RUN_XFER: 1992 sc_xfer = arg; 1993 periph = sc_xfer->xs_periph; 1994 drive = periph->periph_target; 1995 1996 if (!device_is_active(atac->atac_dev)) { 1997 sc_xfer->error = XS_DRIVER_STUFFUP; 1998 scsipi_done(sc_xfer); 1999 return; 2000 } 2001 xfer = ata_get_xfer(chp, false); 2002 if (xfer == NULL) { 2003 sc_xfer->error = XS_RESOURCE_SHORTAGE; 2004 scsipi_done(sc_xfer); 2005 return; 2006 } 2007 2008 if (sc_xfer->xs_control & XS_CTL_POLL) 2009 xfer->c_flags |= C_POLL; 2010 xfer->c_drive = drive; 2011 xfer->c_flags |= C_ATAPI; 2012 xfer->c_databuf = sc_xfer->data; 2013 xfer->c_bcount = sc_xfer->datalen; 2014 xfer->ops = &mvsata_atapi_xfer_ops; 2015 xfer->c_scsipi = sc_xfer; 2016 xfer->c_atapi.c_dscpoll = 0; 2017 s = splbio(); 2018 ata_exec_xfer(chp, xfer); 2019 #ifdef DIAGNOSTIC 2020 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 2021 (sc_xfer->xs_status & XS_STS_DONE) == 0) 2022 panic("mvsata_atapi_scsipi_request:" 2023 " polled command not done"); 2024 #endif 2025 splx(s); 2026 return; 2027 2028 default: 2029 /* Not supported, nothing to do. */ 2030 ; 2031 } 2032 } 2033 2034 static int 2035 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2036 { 2037 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2038 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2039 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2040 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2041 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2042 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2043 const char *errstring; 2044 int tfd; 2045 2046 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2047 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2048 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2049 xfer->c_drive, sc_xfer->xs_control)); 2050 2051 ata_channel_lock_owned(chp); 2052 2053 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2054 if (mvport->port_edmamode_curr != nodma) 2055 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2056 2057 mvsata_pmp_select(mvport, xfer->c_drive); 2058 2059 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2060 drvp->n_xfers++; 2061 2062 /* Do control operations specially. */ 2063 if (__predict_false(drvp->state < READY)) { 2064 /* If it's not a polled command, we need the kernel thread */ 2065 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && 2066 (chp->ch_flags & ATACH_TH_RUN) == 0) { 2067 return ATASTART_TH; 2068 } 2069 /* 2070 * disable interrupts, all commands here should be quick 2071 * enough to be able to poll, and we don't go here that often 2072 */ 2073 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2074 2075 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2076 /* Don't try to set mode if controller can't be adjusted */ 2077 if (atac->atac_set_modes == NULL) 2078 goto ready; 2079 /* Also don't try if the drive didn't report its mode */ 2080 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2081 goto ready; 2082 errstring = "unbusy"; 2083 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2084 goto timeout; 2085 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2086 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2087 errstring = "piomode-atapi"; 2088 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2089 &tfd)) 2090 goto timeout; 2091 if (ATACH_ST(tfd) & WDCS_ERR) { 2092 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2093 /* 2094 * Some ATAPI drives reject PIO settings. 2095 * Fall back to PIO mode 3 since that's the 2096 * minimum for ATAPI. 2097 */ 2098 aprint_error_dev(atac->atac_dev, 2099 "channel %d drive %d: PIO mode %d rejected," 2100 " falling back to PIO mode 3\n", 2101 chp->ch_channel, xfer->c_drive, 2102 drvp->PIO_mode); 2103 if (drvp->PIO_mode > 3) 2104 drvp->PIO_mode = 3; 2105 } else 2106 goto error; 2107 } 2108 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2109 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2110 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2111 else 2112 if (drvp->drive_flags & ATA_DRIVE_DMA) 2113 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2114 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2115 else 2116 goto ready; 2117 errstring = "dmamode-atapi"; 2118 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2119 &tfd)) 2120 goto timeout; 2121 if (ATACH_ST(tfd) & WDCS_ERR) { 2122 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2123 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2124 goto error; 2125 else { 2126 /* 2127 * The drive rejected our DMA setting. 2128 * Fall back to mode 1. 2129 */ 2130 aprint_error_dev(atac->atac_dev, 2131 "channel %d drive %d:" 2132 " DMA mode %d rejected," 2133 " falling back to DMA mode 0\n", 2134 chp->ch_channel, xfer->c_drive, 2135 drvp->DMA_mode); 2136 if (drvp->DMA_mode > 0) 2137 drvp->DMA_mode = 0; 2138 } 2139 } else 2140 goto error; 2141 } 2142 ready: 2143 drvp->state = READY; 2144 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2145 delay(10); /* some drives need a little delay here */ 2146 } 2147 /* start timeout machinery */ 2148 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2149 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 2150 wdctimeout, chp); 2151 2152 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2153 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2154 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2155 ATACH_ST(tfd)); 2156 sc_xfer->error = XS_TIMEOUT; 2157 return ATASTART_ABORT; 2158 } 2159 2160 /* 2161 * Even with WDCS_ERR, the device should accept a command packet 2162 * Limit length to what can be stuffed into the cylinder register 2163 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2164 * but not all devices do that and it's not obvious from the 2165 * ATAPI spec that that behaviour should be expected. If more 2166 * data is necessary, multiple data transfer phases will be done. 2167 */ 2168 2169 wdccommand(chp, 0, ATAPI_PKT_CMD, 2170 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2171 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2172 2173 /* 2174 * If there is no interrupt for CMD input, busy-wait for it (done in 2175 * the interrupt routine. Poll routine will exit early in this case. 2176 */ 2177 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2178 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2179 return ATASTART_POLL; 2180 else 2181 return ATASTART_STARTED; 2182 2183 timeout: 2184 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2185 chp->ch_channel, xfer->c_drive, errstring); 2186 sc_xfer->error = XS_TIMEOUT; 2187 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2188 delay(10); /* some drives need a little delay here */ 2189 return ATASTART_ABORT; 2190 2191 error: 2192 aprint_error_dev(atac->atac_dev, 2193 "channel %d drive %d: %s error (0x%x)\n", 2194 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2195 sc_xfer->error = XS_SHORTSENSE; 2196 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2197 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2198 delay(10); /* some drives need a little delay here */ 2199 return ATASTART_ABORT; 2200 } 2201 2202 static void 2203 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2204 { 2205 /* 2206 * If there is no interrupt for CMD input, busy-wait for it (done in 2207 * the interrupt routine. If it is a polled command, call the interrupt 2208 * routine until command is done. 2209 */ 2210 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2211 2212 /* Wait for at last 400ns for status bit to be valid */ 2213 DELAY(1); 2214 mvsata_atapi_intr(chp, xfer, 0); 2215 2216 if (!poll) 2217 return; 2218 2219 if (chp->ch_flags & ATACH_DMA_WAIT) { 2220 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2221 chp->ch_flags &= ~ATACH_DMA_WAIT; 2222 } 2223 2224 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2225 /* Wait for at last 400ns for status bit to be valid */ 2226 DELAY(1); 2227 mvsata_atapi_intr(chp, xfer, 0); 2228 } 2229 } 2230 2231 static int 2232 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2233 { 2234 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2235 struct atac_softc *atac = chp->ch_atac; 2236 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2237 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2238 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2239 int len, phase, ire, error, retries=0, i; 2240 int tfd; 2241 void *cmd; 2242 2243 ata_channel_lock(chp); 2244 2245 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2246 ("%s:%d:%d: mvsata_atapi_intr\n", 2247 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2248 2249 /* Is it not a transfer, but a control operation? */ 2250 if (drvp->state < READY) { 2251 aprint_error_dev(atac->atac_dev, 2252 "channel %d drive %d: bad state %d\n", 2253 chp->ch_channel, xfer->c_drive, drvp->state); 2254 panic("mvsata_atapi_intr: bad state"); 2255 } 2256 /* 2257 * If we missed an interrupt in a PIO transfer, reset and restart. 2258 * Don't try to continue transfer, we may have missed cycles. 2259 */ 2260 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2261 ata_channel_unlock(chp); 2262 sc_xfer->error = XS_TIMEOUT; 2263 mvsata_atapi_reset(chp, xfer); 2264 return 1; 2265 } 2266 2267 /* Ack interrupt done in wdc_wait_for_unbusy */ 2268 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2269 if (wdc_wait_for_unbusy(chp, 2270 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2271 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2272 ata_channel_unlock(chp); 2273 return 0; /* IRQ was not for us */ 2274 } 2275 aprint_error_dev(atac->atac_dev, 2276 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2277 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2278 if (xfer->c_flags & C_DMA) 2279 ata_dmaerr(drvp, 2280 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2281 sc_xfer->error = XS_TIMEOUT; 2282 ata_channel_unlock(chp); 2283 mvsata_atapi_reset(chp, xfer); 2284 return 1; 2285 } 2286 2287 /* 2288 * If we missed an IRQ and were using DMA, flag it as a DMA error 2289 * and reset device. 2290 */ 2291 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2292 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2293 sc_xfer->error = XS_RESET; 2294 ata_channel_unlock(chp); 2295 mvsata_atapi_reset(chp, xfer); 2296 return (1); 2297 } 2298 /* 2299 * if the request sense command was aborted, report the short sense 2300 * previously recorded, else continue normal processing 2301 */ 2302 2303 again: 2304 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2305 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2306 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2307 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2308 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2309 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2310 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2311 2312 switch (phase) { 2313 case PHASE_CMDOUT: 2314 cmd = sc_xfer->cmd; 2315 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2316 /* Init the DMA channel if necessary */ 2317 if (xfer->c_flags & C_DMA) { 2318 error = mvsata_bdma_init(mvport, xfer); 2319 if (error) { 2320 if (error == EINVAL) { 2321 /* 2322 * We can't do DMA on this transfer 2323 * for some reason. Fall back to PIO. 2324 */ 2325 xfer->c_flags &= ~C_DMA; 2326 error = 0; 2327 } else { 2328 sc_xfer->error = XS_DRIVER_STUFFUP; 2329 break; 2330 } 2331 } 2332 } 2333 2334 /* send packet command */ 2335 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2336 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2337 2338 /* Start the DMA channel if necessary */ 2339 if (xfer->c_flags & C_DMA) { 2340 mvsata_bdma_start(mvport); 2341 chp->ch_flags |= ATACH_DMA_WAIT; 2342 } 2343 ata_channel_unlock(chp); 2344 return 1; 2345 2346 case PHASE_DATAOUT: 2347 /* write data */ 2348 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2349 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2350 (xfer->c_flags & C_DMA) != 0) { 2351 aprint_error_dev(atac->atac_dev, 2352 "channel %d drive %d: bad data phase DATAOUT\n", 2353 chp->ch_channel, xfer->c_drive); 2354 if (xfer->c_flags & C_DMA) 2355 ata_dmaerr(drvp, 2356 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2357 sc_xfer->error = XS_TIMEOUT; 2358 ata_channel_unlock(chp); 2359 mvsata_atapi_reset(chp, xfer); 2360 return 1; 2361 } 2362 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2363 if (xfer->c_bcount < len) { 2364 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2365 " warning: write only %d of %d requested bytes\n", 2366 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2367 len); 2368 len = xfer->c_bcount; 2369 } 2370 2371 wdc->dataout_pio(chp, drvp->drive_flags, 2372 (char *)xfer->c_databuf + xfer->c_skip, len); 2373 2374 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 2375 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2376 2377 xfer->c_skip += len; 2378 xfer->c_bcount -= len; 2379 ata_channel_unlock(chp); 2380 return 1; 2381 2382 case PHASE_DATAIN: 2383 /* Read data */ 2384 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2385 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2386 (xfer->c_flags & C_DMA) != 0) { 2387 aprint_error_dev(atac->atac_dev, 2388 "channel %d drive %d: bad data phase DATAIN\n", 2389 chp->ch_channel, xfer->c_drive); 2390 if (xfer->c_flags & C_DMA) 2391 ata_dmaerr(drvp, 2392 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2393 ata_channel_unlock(chp); 2394 sc_xfer->error = XS_TIMEOUT; 2395 mvsata_atapi_reset(chp, xfer); 2396 return 1; 2397 } 2398 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2399 if (xfer->c_bcount < len) { 2400 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2401 " warning: reading only %d of %d bytes\n", 2402 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2403 len); 2404 len = xfer->c_bcount; 2405 } 2406 2407 wdc->datain_pio(chp, drvp->drive_flags, 2408 (char *)xfer->c_databuf + xfer->c_skip, len); 2409 2410 if (xfer->c_atapi.c_lenoff > 0) 2411 wdcbit_bucket(chp, len - xfer->c_bcount); 2412 2413 xfer->c_skip += len; 2414 xfer->c_bcount -= len; 2415 ata_channel_unlock(chp); 2416 return 1; 2417 2418 case PHASE_ABORTED: 2419 case PHASE_COMPLETED: 2420 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2421 if (xfer->c_flags & C_DMA) 2422 xfer->c_bcount -= sc_xfer->datalen; 2423 sc_xfer->resid = xfer->c_bcount; 2424 /* this will unlock channel lock too */ 2425 mvsata_atapi_phase_complete(xfer); 2426 return 1; 2427 2428 default: 2429 if (++retries<500) { 2430 DELAY(100); 2431 tfd = ATACH_ERR_ST( 2432 MVSATA_WDC_READ_1(mvport, SRB_FE), 2433 MVSATA_WDC_READ_1(mvport, SRB_CS) 2434 ); 2435 goto again; 2436 } 2437 aprint_error_dev(atac->atac_dev, 2438 "channel %d drive %d: unknown phase 0x%x\n", 2439 chp->ch_channel, xfer->c_drive, phase); 2440 if (ATACH_ST(tfd) & WDCS_ERR) { 2441 sc_xfer->error = XS_SHORTSENSE; 2442 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2443 } else { 2444 if (xfer->c_flags & C_DMA) 2445 ata_dmaerr(drvp, 2446 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2447 sc_xfer->error = XS_RESET; 2448 ata_channel_unlock(chp); 2449 mvsata_atapi_reset(chp, xfer); 2450 return (1); 2451 } 2452 } 2453 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2454 ("mvsata_atapi_intr: %s (end), error 0x%x " 2455 "sense 0x%x\n", __func__, 2456 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2457 ata_channel_unlock(chp); 2458 mvsata_atapi_done(chp, xfer); 2459 return 1; 2460 } 2461 2462 static void 2463 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2464 int reason) 2465 { 2466 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2467 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2468 bool deactivate = true; 2469 2470 /* remove this command from xfer queue */ 2471 switch (reason) { 2472 case KILL_GONE_INACTIVE: 2473 deactivate = false; 2474 /* FALLTHROUGH */ 2475 case KILL_GONE: 2476 sc_xfer->error = XS_DRIVER_STUFFUP; 2477 break; 2478 case KILL_RESET: 2479 sc_xfer->error = XS_RESET; 2480 break; 2481 case KILL_REQUEUE: 2482 sc_xfer->error = XS_REQUEUE; 2483 break; 2484 default: 2485 aprint_error_dev(MVSATA_DEV2(mvport), 2486 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2487 panic("mvsata_atapi_kill_xfer"); 2488 } 2489 2490 if (deactivate) 2491 ata_deactivate_xfer(chp, xfer); 2492 2493 ata_free_xfer(chp, xfer); 2494 scsipi_done(sc_xfer); 2495 } 2496 2497 static void 2498 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2499 { 2500 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2501 struct atac_softc *atac = chp->ch_atac; 2502 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2503 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2504 int tfd; 2505 2506 ata_channel_lock(chp); 2507 2508 mvsata_pmp_select(mvport, xfer->c_drive); 2509 2510 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2511 drvp->state = 0; 2512 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2513 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2514 chp->ch_channel, xfer->c_drive); 2515 sc_xfer->error = XS_SELTIMEOUT; 2516 } 2517 2518 ata_channel_unlock(chp); 2519 2520 mvsata_atapi_done(chp, xfer); 2521 return; 2522 } 2523 2524 static void 2525 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2526 { 2527 struct ata_channel *chp = xfer->c_chp; 2528 struct atac_softc *atac = chp->ch_atac; 2529 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2530 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2531 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2532 int tfd = 0; 2533 2534 ata_channel_lock_owned(chp); 2535 2536 /* wait for DSC if needed */ 2537 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2538 DPRINTF(DEBUG_XFERS, 2539 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2540 device_xname(atac->atac_dev), chp->ch_channel, 2541 xfer->c_drive, xfer->c_atapi.c_dscpoll)); 2542 if (cold) 2543 panic("mvsata_atapi_phase_complete: cold"); 2544 2545 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2546 WDCWAIT_TOUT) { 2547 /* 10ms not enough, try again in 1 tick */ 2548 if (xfer->c_atapi.c_dscpoll++ > 2549 mstohz(sc_xfer->timeout)) { 2550 aprint_error_dev(atac->atac_dev, 2551 "channel %d: wait_for_dsc failed\n", 2552 chp->ch_channel); 2553 ata_channel_unlock(chp); 2554 sc_xfer->error = XS_TIMEOUT; 2555 mvsata_atapi_reset(chp, xfer); 2556 } else { 2557 callout_reset(&chp->c_timo_callout, 1, 2558 mvsata_atapi_polldsc, chp); 2559 ata_channel_unlock(chp); 2560 } 2561 return; 2562 } 2563 } 2564 2565 /* 2566 * Some drive occasionally set WDCS_ERR with 2567 * "ATA illegal length indication" in the error 2568 * register. If we read some data the sense is valid 2569 * anyway, so don't report the error. 2570 */ 2571 if (ATACH_ST(tfd) & WDCS_ERR && 2572 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2573 sc_xfer->resid == sc_xfer->datalen)) { 2574 /* save the short sense */ 2575 sc_xfer->error = XS_SHORTSENSE; 2576 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2577 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2578 /* ask scsipi to send a REQUEST_SENSE */ 2579 sc_xfer->error = XS_BUSY; 2580 sc_xfer->status = SCSI_CHECK; 2581 } else 2582 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2583 ata_dmaerr(drvp, 2584 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2585 sc_xfer->error = XS_RESET; 2586 ata_channel_unlock(chp); 2587 mvsata_atapi_reset(chp, xfer); 2588 return; 2589 } 2590 } 2591 if (xfer->c_bcount != 0) { 2592 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2593 " bcount value is %d after io\n", 2594 device_xname(atac->atac_dev), chp->ch_channel, 2595 xfer->c_drive, xfer->c_bcount)); 2596 } 2597 #ifdef DIAGNOSTIC 2598 if (xfer->c_bcount < 0) { 2599 aprint_error_dev(atac->atac_dev, 2600 "channel %d drive %d: mvsata_atapi_intr:" 2601 " warning: bcount value is %d after io\n", 2602 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2603 } 2604 #endif 2605 2606 DPRINTF(DEBUG_XFERS, 2607 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2608 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2609 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2610 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2611 ata_channel_unlock(chp); 2612 mvsata_atapi_done(chp, xfer); 2613 } 2614 2615 static void 2616 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2617 { 2618 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2619 bool iserror = (sc_xfer->error != XS_NOERROR); 2620 2621 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2622 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2623 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2624 xfer->c_drive, (u_int)xfer->c_flags)); 2625 2626 if (ata_waitdrain_xfer_check(chp, xfer)) 2627 return; 2628 2629 /* mark controller inactive and free the command */ 2630 ata_deactivate_xfer(chp, xfer); 2631 2632 ata_free_xfer(chp, xfer); 2633 2634 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2635 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2636 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2637 scsipi_done(sc_xfer); 2638 DPRINTF(DEBUG_FUNCS, 2639 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2640 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2641 chp->ch_flags)); 2642 if (!iserror) 2643 atastart(chp); 2644 } 2645 2646 static void 2647 mvsata_atapi_polldsc(void *arg) 2648 { 2649 struct ata_channel *chp = arg; 2650 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 2651 2652 KASSERT(xfer != NULL); 2653 2654 ata_channel_lock(chp); 2655 2656 /* this will unlock channel lock too */ 2657 mvsata_atapi_phase_complete(xfer); 2658 } 2659 #endif /* NATAPIBUS > 0 */ 2660 2661 2662 /* 2663 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2664 * if supported queuing command by atabus? The race condition will not happen 2665 * if this is called only to the thread of atabus. 2666 */ 2667 static int 2668 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2669 { 2670 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2671 struct ata_bio *ata_bio = &xfer->c_bio; 2672 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2673 struct eprd *eprd; 2674 bus_addr_t crqb_base_addr; 2675 bus_dmamap_t data_dmamap; 2676 uint32_t reg; 2677 int erqqip, erqqop, next, rv, i; 2678 2679 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2680 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2681 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2682 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2683 2684 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2685 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2686 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2687 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2688 next = erqqip; 2689 MVSATA_EDMAQ_INC(next); 2690 if (next == erqqop) { 2691 /* queue full */ 2692 return EBUSY; 2693 } 2694 DPRINTF(DEBUG_XFERS, 2695 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2696 2697 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2698 ata_bio->flags); 2699 if (rv != 0) 2700 return rv; 2701 2702 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2703 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2704 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2705 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2706 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2707 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2708 2709 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2710 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2711 eprd->eot = htole16(0); 2712 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2713 eprd++; 2714 } 2715 (eprd - 1)->eot |= htole16(EPRD_EOT); 2716 #ifdef MVSATA_DEBUG 2717 if (mvsata_debug >= 3) 2718 mvsata_print_eprd(mvport, xfer->c_slot); 2719 #endif 2720 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2721 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2722 BUS_DMASYNC_PREWRITE); 2723 2724 /* setup EDMA Command Request Block (CRQB) Data */ 2725 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2726 #ifdef MVSATA_DEBUG 2727 if (mvsata_debug >= 3) 2728 mvsata_print_crqb(mvport, erqqip); 2729 #endif 2730 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2731 erqqip * sizeof(union mvsata_crqb), 2732 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2733 2734 MVSATA_EDMAQ_INC(erqqip); 2735 2736 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2737 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2738 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2739 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2740 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2741 2742 return 0; 2743 } 2744 2745 static int 2746 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2747 { 2748 struct ata_channel *chp = &mvport->port_ata_channel; 2749 struct crpb *crpb; 2750 struct ata_bio *ata_bio; 2751 struct ata_xfer *xfer; 2752 uint32_t reg; 2753 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2754 int st, dmaerr; 2755 2756 /* First, Sync for Request Queue buffer */ 2757 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2758 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2759 if (mvport->port_prev_erqqop != erqqop) { 2760 const int s = sizeof(union mvsata_crqb); 2761 2762 if (mvport->port_prev_erqqop < erqqop) 2763 n = erqqop - mvport->port_prev_erqqop; 2764 else { 2765 if (erqqop > 0) 2766 bus_dmamap_sync(mvport->port_dmat, 2767 mvport->port_crqb_dmamap, 0, erqqop * s, 2768 BUS_DMASYNC_POSTWRITE); 2769 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2770 } 2771 if (n > 0) 2772 bus_dmamap_sync(mvport->port_dmat, 2773 mvport->port_crqb_dmamap, 2774 mvport->port_prev_erqqop * s, n * s, 2775 BUS_DMASYNC_POSTWRITE); 2776 mvport->port_prev_erqqop = erqqop; 2777 } 2778 2779 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2780 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2781 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2782 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2783 2784 DPRINTF(DEBUG_XFERS, 2785 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2786 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2787 mvport->port, erpqip, erpqop)); 2788 2789 if (erpqop == erpqip) 2790 return 0; 2791 2792 if (erpqop < erpqip) 2793 n = erpqip - erpqop; 2794 else { 2795 if (erpqip > 0) 2796 bus_dmamap_sync(mvport->port_dmat, 2797 mvport->port_crpb_dmamap, 2798 0, erpqip * sizeof(struct crpb), 2799 BUS_DMASYNC_POSTREAD); 2800 n = MVSATA_EDMAQ_LEN - erpqop; 2801 } 2802 if (n > 0) 2803 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2804 erpqop * sizeof(struct crpb), 2805 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2806 2807 uint32_t aslots = ata_queue_active(chp); 2808 2809 prev_erpqop = erpqop; 2810 while (erpqop != erpqip) { 2811 #ifdef MVSATA_DEBUG 2812 if (mvsata_debug >= 3) 2813 mvsata_print_crpb(mvport, erpqop); 2814 #endif 2815 crpb = mvport->port_crpb + erpqop; 2816 MVSATA_EDMAQ_INC(erpqop); 2817 2818 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2819 2820 if ((aslots & __BIT(quetag)) == 0) { 2821 /* not actually executing */ 2822 continue; 2823 } 2824 2825 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2826 2827 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2828 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2829 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2830 2831 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2832 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2833 2834 ata_bio = &xfer->c_bio; 2835 ata_bio->error = NOERROR; 2836 if (dmaerr != 0) 2837 ata_bio->error = ERR_DMA; 2838 2839 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2840 2841 KASSERT(xfer->c_flags & C_DMA); 2842 mvsata_bio_intr(chp, xfer, ATACH_ERR_ST(0, st)); 2843 2844 if (xfer1 == NULL) 2845 handled++; 2846 else if (xfer == xfer1) { 2847 handled = 1; 2848 break; 2849 } 2850 } 2851 if (prev_erpqop < erpqop) 2852 n = erpqop - prev_erpqop; 2853 else { 2854 if (erpqop > 0) 2855 bus_dmamap_sync(mvport->port_dmat, 2856 mvport->port_crpb_dmamap, 0, 2857 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2858 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2859 } 2860 if (n > 0) 2861 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2862 prev_erpqop * sizeof(struct crpb), 2863 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2864 2865 reg &= ~EDMA_RESQP_ERPQP_MASK; 2866 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2867 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2868 2869 return handled; 2870 } 2871 2872 static int 2873 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2874 { 2875 int xtime; 2876 2877 for (xtime = 0; xtime < timeout * 10; xtime++) { 2878 if (mvsata_edma_handle(mvport, xfer)) 2879 return 0; 2880 DELAY(100); 2881 } 2882 2883 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2884 mvsata_edma_rqq_remove(mvport, xfer); 2885 xfer->c_flags |= C_TIMEOU; 2886 return 1; 2887 } 2888 2889 static void 2890 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2891 { 2892 struct ata_channel *chp = &mvport->port_ata_channel; 2893 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2894 bus_addr_t crqb_base_addr; 2895 int erqqip, i; 2896 2897 /* First, hardware reset, stop EDMA */ 2898 mvsata_hreset_port(mvport); 2899 2900 /* cleanup completed EDMA safely */ 2901 mvsata_edma_handle(mvport, NULL); 2902 2903 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2904 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2905 2906 uint32_t aslots = ata_queue_active(chp); 2907 2908 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2909 struct ata_xfer *rqxfer; 2910 2911 if ((aslots & __BIT(i)) == 0) 2912 continue; 2913 2914 if (i == xfer->c_slot) { 2915 /* remove xfer from EDMA request queue */ 2916 bus_dmamap_sync(mvport->port_dmat, 2917 mvport->port_eprd_dmamap, 2918 mvport->port_reqtbl[i].eprd_offset, 2919 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2920 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 2921 /* quetag freed by caller later */ 2922 continue; 2923 } 2924 2925 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 2926 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 2927 erqqip++; 2928 } 2929 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2930 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2931 BUS_DMASYNC_POSTWRITE); 2932 2933 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 2934 mvsata_edma_reset_qptr(mvport); 2935 mvsata_edma_enable(mvport); 2936 2937 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2938 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2939 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2940 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2941 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2942 } 2943 2944 #if NATAPIBUS > 0 2945 static int 2946 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 2947 { 2948 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2949 struct eprd *eprd; 2950 bus_dmamap_t data_dmamap; 2951 bus_addr_t eprd_addr; 2952 int i, rv; 2953 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2954 2955 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2956 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2957 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2958 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2959 2960 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 2961 sc_xfer->datalen, 2962 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2963 if (rv != 0) 2964 return rv; 2965 2966 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2967 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2968 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2969 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2970 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2971 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2972 2973 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2974 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2975 eprd->eot = htole16(0); 2976 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2977 eprd++; 2978 } 2979 (eprd - 1)->eot |= htole16(EPRD_EOT); 2980 #ifdef MVSATA_DEBUG 2981 if (mvsata_debug >= 3) 2982 mvsata_print_eprd(mvport, xfer->c_slot); 2983 #endif 2984 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2985 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2986 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 2987 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2988 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 2989 2990 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2991 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2992 2993 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2994 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2995 else 2996 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2997 2998 return 0; 2999 } 3000 3001 static void 3002 mvsata_bdma_start(struct mvsata_port *mvport) 3003 { 3004 3005 #ifdef MVSATA_DEBUG 3006 if (mvsata_debug >= 3) 3007 mvsata_print_eprd(mvport, 0); 3008 #endif 3009 3010 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 3011 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 3012 } 3013 #endif 3014 #endif 3015 3016 3017 static int 3018 mvsata_port_init(struct mvsata_hc *mvhc, int port) 3019 { 3020 struct mvsata_softc *sc = mvhc->hc_sc; 3021 struct mvsata_port *mvport; 3022 struct ata_channel *chp; 3023 int channel, rv, i; 3024 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 3025 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 3026 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 3027 3028 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 3029 M_ZERO | M_NOWAIT); 3030 if (mvport == NULL) { 3031 aprint_error("%s:%d: can't allocate memory for port %d\n", 3032 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3033 return ENOMEM; 3034 } 3035 3036 mvport->port = port; 3037 mvport->port_hc = mvhc; 3038 mvport->port_edmamode_negotiated = nodma; 3039 3040 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3041 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3042 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3043 if (rv != 0) { 3044 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3045 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3046 goto fail0; 3047 } 3048 mvport->port_iot = mvhc->hc_iot; 3049 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3050 &mvport->port_sata_sstatus); 3051 if (rv != 0) { 3052 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3053 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3054 goto fail0; 3055 } 3056 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3057 &mvport->port_sata_serror); 3058 if (rv != 0) { 3059 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3060 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3061 goto fail0; 3062 } 3063 if (sc->sc_rev == gen1) 3064 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3065 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3066 else 3067 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3068 SATA_SC, 4, &mvport->port_sata_scontrol); 3069 if (rv != 0) { 3070 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3071 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3072 goto fail0; 3073 } 3074 mvport->port_dmat = sc->sc_dmat; 3075 mvhc->hc_ports[port] = mvport; 3076 3077 channel = mvhc->hc * sc->sc_port + port; 3078 chp = &mvport->port_ata_channel; 3079 chp->ch_channel = channel; 3080 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3081 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3082 sc->sc_ata_channels[channel] = chp; 3083 3084 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3085 if (rv != 0) 3086 goto fail0; 3087 3088 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3089 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3090 if (rv != 0) { 3091 aprint_error( 3092 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3093 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3094 goto fail0; 3095 } 3096 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3097 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3098 if (rv != 0) { 3099 aprint_error( 3100 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3101 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3102 goto fail1; 3103 } 3104 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3105 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3106 if (rv != 0) { 3107 aprint_error( 3108 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3109 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3110 goto fail2; 3111 } 3112 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3113 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3114 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 3115 &mvport->port_reqtbl[i].data_dmamap); 3116 if (rv != 0) { 3117 aprint_error("%s:%d:%d:" 3118 " EDMA data map(%d) create failed: error=%d\n", 3119 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3120 rv); 3121 goto fail3; 3122 } 3123 } 3124 3125 return 0; 3126 3127 fail3: 3128 for (i--; i >= 0; i--) 3129 bus_dmamap_destroy(mvport->port_dmat, 3130 mvport->port_reqtbl[i].data_dmamap); 3131 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3132 fail2: 3133 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3134 fail1: 3135 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3136 fail0: 3137 return rv; 3138 } 3139 3140 static int 3141 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3142 { 3143 int hc, port, rv, i; 3144 3145 hc = mvport->port_hc->hc; 3146 port = mvport->port; 3147 3148 /* Create subregion for Shadow Registers Map */ 3149 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3150 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3151 if (rv != 0) { 3152 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3153 device_xname(MVSATA_DEV2(mvport)), hc, port); 3154 return rv; 3155 } 3156 wdr->cmd_iot = mvport->port_iot; 3157 3158 /* Once create subregion for each command registers */ 3159 for (i = 0; i < WDC_NREG; i++) { 3160 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3161 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3162 if (rv != 0) { 3163 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3164 device_xname(MVSATA_DEV2(mvport)), hc, port); 3165 return rv; 3166 } 3167 } 3168 /* Create subregion for Alternate Status register */ 3169 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3170 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3171 if (rv != 0) { 3172 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3173 device_xname(MVSATA_DEV2(mvport)), hc, port); 3174 return rv; 3175 } 3176 wdr->ctl_iot = mvport->port_iot; 3177 3178 wdc_init_shadow_regs(wdr); 3179 3180 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3181 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3182 if (rv != 0) { 3183 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3184 device_xname(MVSATA_DEV2(mvport)), hc, port); 3185 return rv; 3186 } 3187 wdr->sata_iot = mvport->port_iot; 3188 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3189 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3190 if (rv != 0) { 3191 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3192 device_xname(MVSATA_DEV2(mvport)), hc, port); 3193 return rv; 3194 } 3195 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3196 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3197 if (rv != 0) { 3198 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3199 device_xname(MVSATA_DEV2(mvport)), hc, port); 3200 return rv; 3201 } 3202 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3203 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3204 if (rv != 0) { 3205 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3206 device_xname(MVSATA_DEV2(mvport)), hc, port); 3207 return rv; 3208 } 3209 3210 return 0; 3211 } 3212 3213 3214 #ifndef MVSATA_WITHOUTDMA 3215 static void * 3216 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3217 bus_dmamap_t *dmamap, size_t size, int write) 3218 { 3219 bus_dma_segment_t seg; 3220 int nseg, rv; 3221 void *kva; 3222 3223 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3224 BUS_DMA_NOWAIT); 3225 if (rv != 0) { 3226 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3227 device_xname(MVSATA_DEV2(mvport)), 3228 mvport->port_hc->hc, mvport->port, rv); 3229 goto fail; 3230 } 3231 3232 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3233 if (rv != 0) { 3234 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3235 device_xname(MVSATA_DEV2(mvport)), 3236 mvport->port_hc->hc, mvport->port, rv); 3237 goto free; 3238 } 3239 3240 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3241 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3242 if (rv != 0) { 3243 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3244 device_xname(MVSATA_DEV2(mvport)), 3245 mvport->port_hc->hc, mvport->port, rv); 3246 goto unmap; 3247 } 3248 3249 if (!write) 3250 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3251 3252 return kva; 3253 3254 unmap: 3255 bus_dmamem_unmap(dmat, kva, size); 3256 free: 3257 bus_dmamem_free(dmat, &seg, nseg); 3258 fail: 3259 return NULL; 3260 } 3261 3262 /* ARGSUSED */ 3263 static void 3264 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3265 bus_dmamap_t dmamap, void *kva) 3266 { 3267 3268 bus_dmamap_unload(dmat, dmamap); 3269 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3270 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3271 } 3272 3273 static int 3274 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3275 size_t datalen, int flags) 3276 { 3277 int rv, lop, sop; 3278 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3279 3280 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3281 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3282 3283 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3284 NULL, BUS_DMA_NOWAIT | lop); 3285 if (rv) { 3286 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3287 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3288 mvport->port, rv); 3289 return rv; 3290 } 3291 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3292 data_dmamap->dm_mapsize, sop); 3293 3294 return 0; 3295 } 3296 3297 static inline void 3298 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3299 { 3300 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3301 3302 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3303 data_dmamap->dm_mapsize, 3304 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3305 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3306 } 3307 #endif 3308 3309 static void 3310 mvsata_hreset_port(struct mvsata_port *mvport) 3311 { 3312 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3313 3314 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3315 3316 delay(25); /* allow reset propagation */ 3317 3318 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3319 3320 mvport->_fix_phy_param._fix_phy(mvport); 3321 3322 if (sc->sc_gen == gen1) 3323 delay(1000); 3324 } 3325 3326 static void 3327 mvsata_reset_port(struct mvsata_port *mvport) 3328 { 3329 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3330 3331 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3332 3333 mvsata_hreset_port(mvport); 3334 3335 if (device_is_a(parent, "pci")) 3336 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3337 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3338 else /* SoC */ 3339 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3340 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3341 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3342 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3343 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3344 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3345 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3346 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3347 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3348 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3349 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3350 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3351 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3352 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3353 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3354 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3355 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3356 } 3357 3358 static void 3359 mvsata_reset_hc(struct mvsata_hc *mvhc) 3360 { 3361 #if 0 3362 uint32_t val; 3363 #endif 3364 3365 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3366 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3367 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3368 3369 #if 0 /* XXXX needs? */ 3370 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3371 3372 /* 3373 * Keep the SS during power on and the reference clock bits (reset 3374 * sample) 3375 */ 3376 val = MVSATA_HC_READ_4(mvhc, 0x020); 3377 val &= 0x1c1c1c1c; 3378 val |= 0x03030303; 3379 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3380 #endif 3381 } 3382 3383 static uint32_t 3384 mvsata_softreset(struct mvsata_port *mvport, int flags) 3385 { 3386 struct ata_channel *chp = &mvport->port_ata_channel; 3387 uint32_t sig0 = ~0; 3388 int timeout; 3389 uint8_t st0; 3390 3391 ata_channel_lock_owned(chp); 3392 3393 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3394 delay(10); 3395 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3396 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3397 delay(10); 3398 3399 /* wait for BSY to deassert */ 3400 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3401 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3402 3403 if ((st0 & WDCS_BSY) == 0) { 3404 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3405 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3406 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3407 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3408 goto out; 3409 } 3410 ata_delay(chp, 10, "atarst", flags); 3411 } 3412 3413 aprint_error("%s:%d:%d: %s: timeout\n", 3414 device_xname(MVSATA_DEV2(mvport)), 3415 mvport->port_hc->hc, mvport->port, __func__); 3416 3417 out: 3418 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3419 return sig0; 3420 } 3421 3422 #ifndef MVSATA_WITHOUTDMA 3423 static void 3424 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3425 { 3426 const bus_addr_t crpb_addr = 3427 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3428 const uint32_t crpb_addr_mask = 3429 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3430 3431 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3432 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3433 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3434 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3435 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3436 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3437 } 3438 3439 static inline void 3440 mvsata_edma_enable(struct mvsata_port *mvport) 3441 { 3442 3443 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3444 } 3445 3446 static int 3447 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3448 { 3449 struct ata_channel *chp = &mvport->port_ata_channel; 3450 uint32_t status, command; 3451 uint32_t idlestatus = EDMA_S_EDMAIDLE | EDMA_S_ECACHEEMPTY; 3452 int t; 3453 3454 ata_channel_lock_owned(chp); 3455 3456 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3457 3458 timeout = mstohz(timeout + hztoms(1) - 1); 3459 3460 for (t = 0; ; ++t) { 3461 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3462 if ((status & idlestatus) == idlestatus) 3463 break; 3464 if (t >= timeout) 3465 break; 3466 ata_delay(chp, hztoms(1), "mvsata_edma1", wflags); 3467 } 3468 if (t >= timeout) { 3469 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3470 device_xname(MVSATA_DEV2(mvport)), 3471 mvport->port_hc->hc, mvport->port); 3472 return EBUSY; 3473 } 3474 3475 /* The disable bit (eDsEDMA) is self negated. */ 3476 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3477 3478 for (t = 0; ; ++t) { 3479 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3480 if (!(command & EDMA_CMD_EENEDMA)) 3481 break; 3482 if (t >= timeout) 3483 break; 3484 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3485 } 3486 if (t >= timeout) { 3487 aprint_error("%s:%d:%d: unable to re-enable EDMA\n", 3488 device_xname(MVSATA_DEV2(mvport)), 3489 mvport->port_hc->hc, mvport->port); 3490 return EBUSY; 3491 } 3492 } 3493 return 0; 3494 } 3495 3496 /* 3497 * Set EDMA registers according to mode. 3498 * ex. NCQ/TCQ(queued)/non queued. 3499 */ 3500 static void 3501 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3502 { 3503 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3504 uint32_t reg; 3505 3506 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3507 reg |= EDMA_CFG_RESERVED; 3508 3509 if (mode == ncq) { 3510 if (sc->sc_gen == gen1) { 3511 aprint_error_dev(MVSATA_DEV2(mvport), 3512 "GenI not support NCQ\n"); 3513 return; 3514 } else if (sc->sc_gen == gen2) 3515 reg |= EDMA_CFG_EDEVERR; 3516 reg |= EDMA_CFG_ESATANATVCMDQUE; 3517 } else if (mode == queued) { 3518 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3519 reg |= EDMA_CFG_EQUE; 3520 } else 3521 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3522 3523 if (sc->sc_gen == gen1) 3524 reg |= EDMA_CFG_ERDBSZ; 3525 else if (sc->sc_gen == gen2) 3526 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3527 else if (sc->sc_gen == gen2e) { 3528 device_t parent = device_parent(MVSATA_DEV(sc)); 3529 3530 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3531 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3532 3533 if (device_is_a(parent, "pci")) 3534 reg |= ( 3535 #if NATAPIBUS > 0 3536 EDMA_CFG_EEARLYCOMPLETIONEN | 3537 #endif 3538 EDMA_CFG_ECUTTHROUGHEN | 3539 EDMA_CFG_EWRBUFFERLEN | 3540 EDMA_CFG_ERDBSZEXT); 3541 } 3542 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3543 3544 reg = ( 3545 EDMA_IE_EIORDYERR | 3546 EDMA_IE_ETRANSINT | 3547 EDMA_IE_EDEVCON | 3548 EDMA_IE_EDEVDIS); 3549 if (sc->sc_gen != gen1) 3550 reg |= ( 3551 EDMA_IE_TRANSPROTERR | 3552 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3553 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3554 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3555 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3556 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3557 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3558 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3559 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3560 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3561 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3562 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3563 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3564 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3565 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3566 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3567 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3568 EDMA_IE_ESELFDIS); 3569 3570 if (mode == ncq) 3571 reg |= EDMA_IE_EDEVERR; 3572 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3573 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3574 reg &= ~EDMA_IE_EDEVERR; 3575 if (mode != ncq) 3576 reg |= EDMA_IE_EDEVERR; 3577 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3578 if (sc->sc_gen == gen2e) { 3579 /* 3580 * Clear FISWait4HostRdyEn[0] and [2]. 3581 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3582 * [2]: SDB FIS is received with <ERR> bit set to 1. 3583 */ 3584 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3585 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3586 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3587 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3588 } 3589 3590 mvport->port_edmamode_curr = mode; 3591 } 3592 3593 3594 /* 3595 * Generation dependent functions 3596 */ 3597 3598 static void 3599 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3600 struct ata_xfer *xfer) 3601 { 3602 struct crqb *crqb; 3603 bus_addr_t eprd_addr; 3604 daddr_t blkno; 3605 uint32_t rw; 3606 uint8_t cmd, head; 3607 int i; 3608 struct ata_bio *ata_bio = &xfer->c_bio; 3609 3610 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3611 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3612 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3613 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3614 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3615 head = WDSD_LBA; 3616 } else { 3617 head = 0; 3618 } 3619 blkno = ata_bio->blkno; 3620 if (ata_bio->flags & ATA_LBA48) 3621 cmd = atacmd_to48(cmd); 3622 else { 3623 head |= ((ata_bio->blkno >> 24) & 0xf); 3624 blkno &= 0xffffff; 3625 } 3626 crqb = &mvport->port_crqb->crqb + erqqip; 3627 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3628 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3629 crqb->ctrlflg = 3630 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3631 CRQB_CPMPORT(xfer->c_drive)); 3632 i = 0; 3633 if (mvport->port_edmamode_curr == dma) { 3634 if (ata_bio->flags & ATA_LBA48) 3635 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3636 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3637 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3638 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3639 } else { /* ncq/queued */ 3640 3641 /* 3642 * XXXX: Oops, ata command is not correct. And, atabus layer 3643 * has not been supported yet now. 3644 * Queued DMA read/write. 3645 * read/write FPDMAQueued. 3646 */ 3647 3648 if (ata_bio->flags & ATA_LBA48) 3649 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3650 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3651 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3652 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3653 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3654 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3655 } 3656 if (ata_bio->flags & ATA_LBA48) { 3657 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3658 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3659 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3660 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3661 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3662 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3663 } 3664 crqb->atacommand[i++] = 3665 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3666 crqb->atacommand[i++] = 3667 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3668 crqb->atacommand[i++] = 3669 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3670 crqb->atacommand[i++] = 3671 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3672 crqb->atacommand[i++] = htole16( 3673 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3674 CRQB_ATACOMMAND_LAST); 3675 } 3676 #endif 3677 3678 static uint32_t 3679 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3680 { 3681 struct mvsata_hc *hc = mvport->port_hc; 3682 uint32_t reg; 3683 3684 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3685 /* 3686 * [12:11] : pre 3687 * [7:5] : amps 3688 */ 3689 return reg & 0x000018e0; 3690 } 3691 3692 static void 3693 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3694 { 3695 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3696 struct mvsata_hc *mvhc = mvport->port_hc; 3697 uint32_t reg; 3698 int port = mvport->port, fix_apm_sq = 0; 3699 3700 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3701 if (sc->sc_rev == 0x01) 3702 fix_apm_sq = 1; 3703 } else { 3704 if (sc->sc_rev == 0x00) 3705 fix_apm_sq = 1; 3706 } 3707 3708 if (fix_apm_sq) { 3709 /* 3710 * Disable auto-power management 3711 * 88SX50xx FEr SATA#12 3712 */ 3713 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3714 reg |= (1 << 19); 3715 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3716 3717 /* 3718 * Fix squelch threshold 3719 * 88SX50xx FEr SATA#9 3720 */ 3721 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3722 reg &= ~0x3; 3723 reg |= 0x1; 3724 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3725 } 3726 3727 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3728 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3729 reg &= ~0x000018e0; /* pre and amps mask */ 3730 reg |= mvport->_fix_phy_param.pre_amps; 3731 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3732 } 3733 3734 static void 3735 mvsata_devconn_gen1(struct mvsata_port *mvport) 3736 { 3737 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3738 3739 /* Fix for 88SX50xx FEr SATA#2 */ 3740 mvport->_fix_phy_param._fix_phy(mvport); 3741 3742 /* If disk is connected, then enable the activity LED */ 3743 if (sc->sc_rev == 0x03) { 3744 /* XXXXX */ 3745 } 3746 } 3747 3748 static uint32_t 3749 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3750 { 3751 uint32_t reg; 3752 3753 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3754 /* 3755 * [10:8] : amps 3756 * [7:5] : pre 3757 */ 3758 return reg & 0x000007e0; 3759 } 3760 3761 static void 3762 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3763 { 3764 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3765 uint32_t reg; 3766 3767 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3768 sc->sc_gen == gen2e) { 3769 /* 3770 * Fix for 3771 * 88SX60X1 FEr SATA #23 3772 * 88SX6042/88SX7042 FEr SATA #23 3773 * 88F5182 FEr #SATA-S13 3774 * 88F5082 FEr #SATA-S13 3775 */ 3776 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3777 reg &= ~(1 << 16); 3778 reg |= (1 << 31); 3779 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3780 3781 delay(200); 3782 3783 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3784 reg &= ~((1 << 16) | (1 << 31)); 3785 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3786 3787 delay(200); 3788 } 3789 3790 /* Fix values in PHY Mode 3 Register.*/ 3791 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3792 reg &= ~0x7F900000; 3793 reg |= 0x2A800000; 3794 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3795 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3796 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3797 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3798 reg &= ~0x0000001c; 3799 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3800 3801 /* 3802 * Fix values in PHY Mode 4 Register. 3803 * 88SX60x1 FEr SATA#10 3804 * 88F5182 GL #SATA-S10 3805 * 88F5082 GL #SATA-S10 3806 */ 3807 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3808 sc->sc_gen == gen2e) { 3809 uint32_t tmp = 0; 3810 3811 /* 88SX60x1 FEr SATA #13 */ 3812 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3813 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3814 3815 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3816 reg |= (1 << 0); 3817 reg &= ~(1 << 1); 3818 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3819 if (sc->sc_gen == gen2e) { 3820 reg &= ~0x5de3fffc; 3821 reg |= (1 << 2); 3822 } 3823 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3824 3825 /* 88SX60x1 FEr SATA #13 */ 3826 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3827 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3828 } 3829 3830 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3831 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3832 reg &= ~0x000007e0; /* pre and amps mask */ 3833 reg |= mvport->_fix_phy_param.pre_amps; 3834 reg &= ~(1 << 16); 3835 if (sc->sc_gen == gen2e) { 3836 /* 3837 * according to mvSata 3.6.1, some IIE values are fixed. 3838 * some reserved fields must be written with fixed values. 3839 */ 3840 reg &= ~0xC30FF01F; 3841 reg |= 0x0000900F; 3842 } 3843 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3844 } 3845 3846 #ifndef MVSATA_WITHOUTDMA 3847 static void 3848 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3849 struct ata_xfer *xfer) 3850 { 3851 struct crqb_gen2e *crqb; 3852 bus_addr_t eprd_addr; 3853 uint32_t ctrlflg, rw; 3854 uint8_t fis[RHD_FISLEN]; 3855 3856 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3857 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3858 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3859 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3860 CRQB_CPMPORT(xfer->c_drive) | 3861 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3862 3863 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3864 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3865 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3866 crqb->ctrlflg = htole32(ctrlflg); 3867 3868 satafis_rhd_construct_bio(xfer, fis); 3869 3870 crqb->atacommand[0] = 0; 3871 crqb->atacommand[1] = 0; 3872 /* copy over the ATA command part of the fis */ 3873 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3874 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3875 } 3876 3877 #ifdef MVSATA_DEBUG 3878 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3879 do { \ 3880 int _i; \ 3881 u_char *_p = (p); \ 3882 \ 3883 printf(#type "(%d)", (n)); \ 3884 for (_i = 0; _i < (size); _i++, _p++) { \ 3885 if (_i % 16 == 0) \ 3886 printf("\n "); \ 3887 printf(" %02x", *_p); \ 3888 } \ 3889 printf("\n"); \ 3890 } while (0 /* CONSTCOND */) 3891 3892 static void 3893 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3894 { 3895 3896 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3897 n, (u_char *)(mvport->port_crqb + n)); 3898 } 3899 3900 static void 3901 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3902 { 3903 3904 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3905 n, (u_char *)(mvport->port_crpb + n)); 3906 } 3907 3908 static void 3909 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3910 { 3911 struct eprd *eprd; 3912 int i = 0; 3913 3914 eprd = mvport->port_reqtbl[n].eprd; 3915 while (1 /*CONSTCOND*/) { 3916 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3917 i, (u_char *)eprd); 3918 if (eprd->eot & EPRD_EOT) 3919 break; 3920 eprd++; 3921 i++; 3922 } 3923 } 3924 #endif 3925 #endif 3926
Indexes created Sat Sep 27 22:09:54 GMT 2025