mvsata.c revision 1.47
1 /* $NetBSD: mvsata.c,v 1.47 2019/06/23 06:29:22 tsutsui Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.47 2019/06/23 06:29:22 tsutsui Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 /* 62 * Nice things to do: 63 * 64 * - MSI/MSI-X support - though on some models MSI actually doesn't work 65 * even when hardware claims to support it, according to FreeBSD/OpenBSD 66 * - move pci-specific code to the pci attach code 67 * - mvsata(4) use 64-bit DMA on hardware which claims to support it 68 * - e.g. AHA1430SA does not really work, crash in mvsata_intr() on boot 69 */ 70 71 #include <dev/ic/mvsatareg.h> 72 #include <dev/ic/mvsatavar.h> 73 74 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 75 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 76 77 #define MVSATA_HC_READ_4(hc, reg) \ 78 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 79 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 80 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 81 #define MVSATA_EDMA_READ_4(mvport, reg) \ 82 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 83 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 84 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 85 #define MVSATA_WDC_READ_2(mvport, reg) \ 86 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 87 SHADOW_REG_BLOCK_OFFSET + (reg)) 88 #define MVSATA_WDC_READ_1(mvport, reg) \ 89 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 90 SHADOW_REG_BLOCK_OFFSET + (reg)) 91 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 92 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 93 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 94 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 95 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 96 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 97 98 #ifdef MVSATA_DEBUG 99 100 #define DEBUG_INTR 0x01 101 #define DEBUG_XFERS 0x02 102 #define DEBUG_FUNCS 0x08 103 #define DEBUG_PROBE 0x10 104 105 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 106 int mvsata_debug = 0; 107 #else 108 #define DPRINTF(n,x) 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 113 sending a cmd */ 114 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 115 116 #define MVSATA_MAX_SEGS (MAXPHYS / PAGE_SIZE + 1) 117 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * MVSATA_MAX_SEGS) 118 119 120 static void mvsata_probe_drive(struct ata_channel *); 121 122 #ifndef MVSATA_WITHOUTDMA 123 static void mvsata_reset_channel(struct ata_channel *, int); 124 static int mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 125 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 126 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 127 static int mvsata_addref(struct ata_drive_datas *); 128 static void mvsata_delref(struct ata_drive_datas *); 129 static void mvsata_killpending(struct ata_drive_datas *); 130 131 #if NATAPIBUS > 0 132 static void mvsata_atapibus_attach(struct atabus_softc *); 133 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 134 scsipi_adapter_req_t, void *); 135 static void mvsata_atapi_minphys(struct buf *); 136 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 137 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 138 #endif 139 #endif 140 141 static void mvsata_setup_channel(struct ata_channel *); 142 143 #ifndef MVSATA_WITHOUTDMA 144 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 145 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 146 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 147 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 148 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 149 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 150 int); 151 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 152 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 153 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 154 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 155 int); 156 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 157 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 158 #if NATAPIBUS > 0 159 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 160 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 161 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 162 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 163 int); 164 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 165 static void mvsata_atapi_phase_complete(struct ata_xfer *, int); 166 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 167 static void mvsata_atapi_polldsc(void *); 168 #endif 169 170 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 171 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 172 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 173 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 174 #if NATAPIBUS > 0 175 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 176 static void mvsata_bdma_start(struct mvsata_port *); 177 #endif 178 #endif 179 180 static int mvsata_nondma_handle(struct mvsata_port *); 181 182 static int mvsata_port_init(struct mvsata_hc *, int); 183 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 184 #ifndef MVSATA_WITHOUTDMA 185 static void mvsata_channel_recover(struct ata_channel *, int, uint32_t); 186 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 187 bus_dmamap_t *, size_t, int); 188 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 189 bus_dmamap_t, void *); 190 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 191 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 192 #endif 193 194 static void mvsata_hreset_port(struct mvsata_port *); 195 static void mvsata_reset_port(struct mvsata_port *); 196 static void mvsata_reset_hc(struct mvsata_hc *); 197 static uint32_t mvsata_softreset(struct mvsata_port *, int); 198 #ifndef MVSATA_WITHOUTDMA 199 static void mvsata_edma_reset_qptr(struct mvsata_port *); 200 static inline void mvsata_edma_enable(struct mvsata_port *); 201 static int mvsata_edma_disable(struct mvsata_port *, int, int); 202 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 203 204 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 205 struct ata_xfer *); 206 #endif 207 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 208 static void mvsata_fix_phy_gen1(struct mvsata_port *); 209 static void mvsata_devconn_gen1(struct mvsata_port *); 210 211 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 212 static void mvsata_fix_phy_gen2(struct mvsata_port *); 213 #ifndef MVSATA_WITHOUTDMA 214 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 215 struct ata_xfer *); 216 217 #ifdef MVSATA_DEBUG 218 static void mvsata_print_crqb(struct mvsata_port *, int); 219 static void mvsata_print_crpb(struct mvsata_port *, int); 220 static void mvsata_print_eprd(struct mvsata_port *, int); 221 #endif 222 223 static const struct ata_bustype mvsata_ata_bustype = { 224 SCSIPI_BUSTYPE_ATA, 225 mvsata_bio, 226 mvsata_reset_drive, 227 mvsata_reset_channel, 228 mvsata_exec_command, 229 ata_get_params, 230 mvsata_addref, 231 mvsata_delref, 232 mvsata_killpending, 233 mvsata_channel_recover, 234 }; 235 236 #if NATAPIBUS > 0 237 static const struct scsipi_bustype mvsata_atapi_bustype = { 238 SCSIPI_BUSTYPE_ATAPI, 239 atapi_scsipi_cmd, 240 atapi_interpret_sense, 241 atapi_print_addr, 242 mvsata_atapi_kill_pending, 243 NULL, 244 }; 245 #endif /* NATAPIBUS */ 246 #endif 247 248 static void 249 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 250 { 251 uint32_t ifctl; 252 253 KASSERT(pmpport < PMP_MAX_DRIVES); 254 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 255 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 256 panic("EDMA enabled"); 257 } 258 #endif 259 260 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 261 ifctl &= ~0xf; 262 ifctl |= pmpport; 263 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 264 } 265 266 int 267 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 268 int (*mvsata_sreset)(struct mvsata_softc *), 269 int (*mvsata_misc_reset)(struct mvsata_softc *), 270 int read_pre_amps) 271 { 272 struct mvsata_hc *mvhc; 273 struct mvsata_port *mvport; 274 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 275 void (*_fix_phy)(struct mvsata_port *) = NULL; 276 #ifndef MVSATA_WITHOUTDMA 277 void (*edma_setup_crqb) 278 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 279 #endif 280 int hc, port, channel; 281 282 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 283 (product->generation == gen1) ? "I" : 284 ((product->generation == gen2) ? "II" : "IIe"), 285 product->hc, product->port); 286 287 288 switch (product->generation) { 289 case gen1: 290 mvsata_sreset = NULL; 291 read_pre_amps = 1; /* MUST */ 292 read_preamps = mvsata_read_preamps_gen1; 293 _fix_phy = mvsata_fix_phy_gen1; 294 #ifndef MVSATA_WITHOUTDMA 295 edma_setup_crqb = mvsata_edma_setup_crqb; 296 #endif 297 break; 298 299 case gen2: 300 read_preamps = mvsata_read_preamps_gen2; 301 _fix_phy = mvsata_fix_phy_gen2; 302 #ifndef MVSATA_WITHOUTDMA 303 edma_setup_crqb = mvsata_edma_setup_crqb; 304 #endif 305 break; 306 307 case gen2e: 308 read_preamps = mvsata_read_preamps_gen2; 309 _fix_phy = mvsata_fix_phy_gen2; 310 #ifndef MVSATA_WITHOUTDMA 311 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 312 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 313 #endif 314 break; 315 } 316 317 sc->sc_gen = product->generation; 318 sc->sc_hc = product->hc; 319 sc->sc_port = product->port; 320 sc->sc_flags = product->flags; 321 322 #ifdef MVSATA_WITHOUTDMA 323 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 324 #else 325 sc->sc_edma_setup_crqb = edma_setup_crqb; 326 sc->sc_wdcdev.sc_atac.atac_cap |= 327 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 328 #endif 329 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 330 #ifdef MVSATA_WITHOUTDMA 331 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 333 #else 334 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 335 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 336 #endif 337 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 338 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 339 #ifndef MVSATA_WITHOUTDMA 340 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 341 #if NATAPIBUS > 0 342 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 343 #endif 344 #endif 345 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 346 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 347 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 348 349 sc->sc_wdc_regs = 350 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 351 M_DEVBUF, M_NOWAIT); 352 if (sc->sc_wdc_regs == NULL) { 353 aprint_error_dev(MVSATA_DEV(sc), 354 "can't allocate wdc regs memory\n"); 355 return ENOMEM; 356 } 357 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 358 359 for (hc = 0; hc < sc->sc_hc; hc++) { 360 mvhc = &sc->sc_hcs[hc]; 361 mvhc->hc = hc; 362 mvhc->hc_sc = sc; 363 mvhc->hc_iot = sc->sc_iot; 364 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 365 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 366 &mvhc->hc_ioh)) { 367 aprint_error_dev(MVSATA_DEV(sc), 368 "can't subregion SATAHC %d registers\n", hc); 369 continue; 370 } 371 372 for (port = 0; port < sc->sc_port; port++) 373 if (mvsata_port_init(mvhc, port) == 0) { 374 int pre_amps; 375 376 mvport = mvhc->hc_ports[port]; 377 pre_amps = read_pre_amps ? 378 read_preamps(mvport) : 0x00000720; 379 mvport->_fix_phy_param.pre_amps = pre_amps; 380 mvport->_fix_phy_param._fix_phy = _fix_phy; 381 382 if (!mvsata_sreset) 383 mvsata_reset_port(mvport); 384 } 385 386 if (!mvsata_sreset) 387 mvsata_reset_hc(mvhc); 388 } 389 if (mvsata_sreset) 390 mvsata_sreset(sc); 391 392 if (mvsata_misc_reset) 393 mvsata_misc_reset(sc); 394 395 for (hc = 0; hc < sc->sc_hc; hc++) 396 for (port = 0; port < sc->sc_port; port++) { 397 mvport = sc->sc_hcs[hc].hc_ports[port]; 398 if (mvport == NULL) 399 continue; 400 if (mvsata_sreset) 401 mvport->_fix_phy_param._fix_phy(mvport); 402 } 403 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 404 wdcattach(sc->sc_ata_channels[channel]); 405 406 return 0; 407 } 408 409 int 410 mvsata_intr(struct mvsata_hc *mvhc) 411 { 412 struct mvsata_softc *sc = mvhc->hc_sc; 413 struct mvsata_port *mvport; 414 uint32_t cause; 415 int port, handled = 0; 416 417 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 418 419 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 420 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 421 422 if (cause & SATAHC_IC_SAINTCOAL) 423 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 424 cause &= ~SATAHC_IC_SAINTCOAL; 425 426 for (port = 0; port < sc->sc_port; port++) { 427 mvport = mvhc->hc_ports[port]; 428 429 if (cause & SATAHC_IC_DONE(port)) { 430 #ifndef MVSATA_WITHOUTDMA 431 handled = mvsata_edma_handle(mvport, NULL); 432 #endif 433 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 434 ~SATAHC_IC_DONE(port)); 435 } 436 437 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 438 (void) mvsata_nondma_handle(mvport); 439 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 440 ~SATAHC_IC_SADEVINTERRUPT(port)); 441 handled = 1; 442 } 443 } 444 445 return handled; 446 } 447 448 static int 449 mvsata_nondma_handle(struct mvsata_port *mvport) 450 { 451 struct ata_channel *chp = &mvport->port_ata_channel; 452 struct ata_xfer *xfer; 453 int ret; 454 455 /* 456 * The chip doesn't support several pending non-DMA commands, 457 * and the ata middle layer never issues several non-NCQ commands, 458 * so there must be exactly one active command at this moment. 459 */ 460 xfer = ata_queue_get_active_xfer(chp); 461 if (xfer == NULL) { 462 /* Can happen after error recovery, ignore */ 463 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 464 ("%s:%d: %s: intr without xfer\n", 465 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 466 __func__)); 467 return 0; 468 } 469 470 ret = xfer->ops->c_intr(chp, xfer, 1); 471 return (ret); 472 } 473 474 int 475 mvsata_error(struct mvsata_port *mvport) 476 { 477 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 478 uint32_t cause; 479 480 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 481 /* 482 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 483 * in EDMA_IEC. 484 */ 485 if (cause & EDMA_IE_SERRINT) { 486 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 487 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 488 } 489 if (cause & EDMA_IE_ETRANSINT) { 490 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 491 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 492 } 493 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 494 495 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 496 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 497 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 498 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 499 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 500 501 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 502 if (!cause) 503 return 0; 504 505 if (cause & EDMA_IE_EDEVDIS) { 506 aprint_normal("%s:%d:%d: device disconnect\n", 507 device_xname(MVSATA_DEV2(mvport)), 508 mvport->port_hc->hc, mvport->port); 509 } 510 if (cause & EDMA_IE_EDEVCON) { 511 if (sc->sc_gen == gen1) 512 mvsata_devconn_gen1(mvport); 513 514 DPRINTF(DEBUG_INTR, (" device connected\n")); 515 } 516 517 #ifndef MVSATA_WITHOUTDMA 518 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 519 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 520 switch (mvport->port_edmamode_curr) { 521 case dma: 522 case queued: 523 case ncq: 524 mvsata_edma_reset_qptr(mvport); 525 mvsata_edma_enable(mvport); 526 if (cause & EDMA_IE_EDEVERR) 527 break; 528 529 /* FALLTHROUGH */ 530 531 case nodma: 532 default: 533 aprint_error( 534 "%s:%d:%d: EDMA self disable happen 0x%x\n", 535 device_xname(MVSATA_DEV2(mvport)), 536 mvport->port_hc->hc, mvport->port, cause); 537 break; 538 } 539 } 540 #endif 541 if (cause & EDMA_IE_ETRANSINT) { 542 /* hot plug the Port Multiplier */ 543 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 544 device_xname(MVSATA_DEV2(mvport)), 545 mvport->port_hc->hc, mvport->port); 546 } 547 if (cause & EDMA_IE_EDEVERR) { 548 struct ata_channel *chp = &mvport->port_ata_channel; 549 550 aprint_error("%s:%d:%d: device error, recovering\n", 551 device_xname(MVSATA_DEV2(mvport)), 552 mvport->port_hc->hc, mvport->port); 553 554 ata_channel_lock(chp); 555 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, 556 ATACH_ERR_ST(0, WDCS_ERR)); 557 ata_channel_unlock(chp); 558 } 559 560 return 1; 561 } 562 563 #ifndef MVSATA_WITHOUTDMA 564 static void 565 mvsata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 566 { 567 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 568 int drive; 569 570 ata_channel_lock_owned(chp); 571 572 if (chp->ch_ndrives > PMP_PORT_CTL) { 573 /* Get PM port number for the device in error. This device 574 * doesn't seem to have dedicated register for this, so just 575 * assume last selected port was the one. */ 576 /* XXX FIS-based switching */ 577 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 578 } else 579 drive = 0; 580 581 /* 582 * Controller doesn't need any special action. Simply execute 583 * READ LOG EXT for NCQ to unblock device processing, then continue 584 * as if nothing happened. 585 */ 586 587 ata_recovery_resume(chp, drive, tfd, AT_POLL); 588 589 /* Drive unblocked, back to normal operation */ 590 return; 591 } 592 #endif /* !MVSATA_WITHOUTDMA */ 593 594 /* 595 * ATA callback entry points 596 */ 597 598 static void 599 mvsata_probe_drive(struct ata_channel *chp) 600 { 601 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 602 uint32_t sstat, sig; 603 604 ata_channel_lock(chp); 605 606 sstat = sata_reset_interface(chp, mvport->port_iot, 607 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 608 switch (sstat) { 609 case SStatus_DET_DEV: 610 mvsata_pmp_select(mvport, PMP_PORT_CTL); 611 sig = mvsata_softreset(mvport, AT_WAIT); 612 sata_interpret_sig(chp, 0, sig); 613 break; 614 default: 615 break; 616 } 617 618 ata_channel_unlock(chp); 619 } 620 621 #ifndef MVSATA_WITHOUTDMA 622 static void 623 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 624 { 625 struct ata_channel *chp = drvp->chnl_softc; 626 struct mvsata_port *mvport = (struct mvsata_port *)chp; 627 uint32_t edma_c; 628 uint32_t sig; 629 630 ata_channel_lock_owned(chp); 631 632 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 633 634 DPRINTF(DEBUG_FUNCS, 635 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 636 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 637 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 638 639 if (edma_c & EDMA_CMD_EENEDMA) 640 mvsata_edma_disable(mvport, 10000, flags); 641 642 mvsata_pmp_select(mvport, drvp->drive); 643 644 sig = mvsata_softreset(mvport, flags); 645 646 if (sigp) 647 *sigp = sig; 648 649 if (edma_c & EDMA_CMD_EENEDMA) { 650 mvsata_edma_reset_qptr(mvport); 651 mvsata_edma_enable(mvport); 652 } 653 } 654 655 static void 656 mvsata_reset_channel(struct ata_channel *chp, int flags) 657 { 658 struct mvsata_port *mvport = (struct mvsata_port *)chp; 659 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 660 uint32_t sstat, ctrl; 661 662 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 663 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 664 665 ata_channel_lock_owned(chp); 666 667 mvsata_hreset_port(mvport); 668 sstat = sata_reset_interface(chp, mvport->port_iot, 669 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 670 671 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 672 sc->sc_gen != gen1) { 673 /* Downgrade to GenI */ 674 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 675 SControl_DET_DISABLE; 676 677 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 678 679 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 680 ctrl &= ~(1 << 17); /* Disable GenII */ 681 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 682 683 mvsata_hreset_port(mvport); 684 sata_reset_interface(chp, mvport->port_iot, 685 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 686 flags); 687 } 688 689 ata_kill_active(chp, KILL_RESET, flags); 690 691 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 692 mvsata_edma_reset_qptr(mvport); 693 mvsata_edma_enable(mvport); 694 } 695 696 static int 697 mvsata_addref(struct ata_drive_datas *drvp) 698 { 699 700 return 0; 701 } 702 703 static void 704 mvsata_delref(struct ata_drive_datas *drvp) 705 { 706 707 return; 708 } 709 710 static void 711 mvsata_killpending(struct ata_drive_datas *drvp) 712 { 713 714 return; 715 } 716 717 #if NATAPIBUS > 0 718 static void 719 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 720 { 721 struct ata_channel *chp = ata_sc->sc_chan; 722 struct atac_softc *atac = chp->ch_atac; 723 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 724 struct scsipi_channel *chan = &chp->ch_atapi_channel; 725 726 /* 727 * Fill in the scsipi_adapter. 728 */ 729 adapt->adapt_dev = atac->atac_dev; 730 adapt->adapt_nchannels = atac->atac_nchannels; 731 adapt->adapt_request = mvsata_atapi_scsipi_request; 732 adapt->adapt_minphys = mvsata_atapi_minphys; 733 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 734 735 /* 736 * Fill in the scsipi_channel. 737 */ 738 memset(chan, 0, sizeof(*chan)); 739 chan->chan_adapter = adapt; 740 chan->chan_bustype = &mvsata_atapi_bustype; 741 chan->chan_channel = chp->ch_channel; 742 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 743 chan->chan_openings = 1; 744 chan->chan_max_periph = 1; 745 chan->chan_ntargets = 1; 746 chan->chan_nluns = 1; 747 748 chp->atapibus = 749 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 750 } 751 752 static void 753 mvsata_atapi_minphys(struct buf *bp) 754 { 755 756 if (bp->b_bcount > MAXPHYS) 757 bp->b_bcount = MAXPHYS; 758 minphys(bp); 759 } 760 761 static void 762 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 763 { 764 struct scsipi_channel *chan = sc->sc_channel; 765 struct scsipi_periph *periph; 766 struct ataparams ids; 767 struct ataparams *id = &ids; 768 struct mvsata_softc *mvc = 769 device_private(chan->chan_adapter->adapt_dev); 770 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 771 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 772 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 773 struct scsipibus_attach_args sa; 774 char serial_number[21], model[41], firmware_revision[9]; 775 int s; 776 777 /* skip if already attached */ 778 if (scsipi_lookup_periph(chan, target, 0) != NULL) 779 return; 780 781 /* if no ATAPI device detected at attach time, skip */ 782 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 783 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 784 " drive %d not present\n", 785 device_xname(atac->atac_dev), chp->ch_channel, target)); 786 return; 787 } 788 789 /* Some ATAPI devices need a bit more time after software reset. */ 790 delay(5000); 791 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 792 #ifdef ATAPI_DEBUG_PROBE 793 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 794 device_xname(sc->sc_dev), target, 795 id->atap_config & ATAPI_CFG_CMD_MASK, 796 id->atap_config & ATAPI_CFG_DRQ_MASK); 797 #endif 798 periph = scsipi_alloc_periph(M_NOWAIT); 799 if (periph == NULL) { 800 aprint_error_dev(atac->atac_dev, 801 "unable to allocate periph" 802 " for channel %d drive %d\n", 803 chp->ch_channel, target); 804 return; 805 } 806 periph->periph_dev = NULL; 807 periph->periph_channel = chan; 808 periph->periph_switch = &atapi_probe_periphsw; 809 periph->periph_target = target; 810 periph->periph_lun = 0; 811 periph->periph_quirks = PQUIRK_ONLYBIG; 812 813 #ifdef SCSIPI_DEBUG 814 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 815 SCSIPI_DEBUG_TARGET == target) 816 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 817 #endif 818 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 819 if (id->atap_config & ATAPI_CFG_REMOV) 820 periph->periph_flags |= PERIPH_REMOVABLE; 821 if (periph->periph_type == T_SEQUENTIAL) { 822 s = splbio(); 823 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 824 splx(s); 825 } 826 827 sa.sa_periph = periph; 828 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 829 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 830 T_REMOV : T_FIXED; 831 strnvisx(model, sizeof(model), id->atap_model, 40, 832 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 833 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 834 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 835 strnvisx(firmware_revision, sizeof(firmware_revision), 836 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 837 sa.sa_inqbuf.vendor = model; 838 sa.sa_inqbuf.product = serial_number; 839 sa.sa_inqbuf.revision = firmware_revision; 840 841 /* 842 * Determine the operating mode capabilities of the device. 843 */ 844 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 845 periph->periph_cap |= PERIPH_CAP_CMD16; 846 /* XXX This is gross. */ 847 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 848 849 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 850 851 if (drvp->drv_softc) 852 ata_probe_caps(drvp); 853 else { 854 s = splbio(); 855 drvp->drive_type = ATA_DRIVET_NONE; 856 splx(s); 857 } 858 } else { 859 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 860 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 861 device_xname(atac->atac_dev), chp->ch_channel, target)); 862 s = splbio(); 863 drvp->drive_type = ATA_DRIVET_NONE; 864 splx(s); 865 } 866 } 867 868 /* 869 * Kill off all pending xfers for a periph. 870 * 871 * Must be called at splbio(). 872 */ 873 static void 874 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 875 { 876 struct atac_softc *atac = 877 device_private(periph->periph_channel->chan_adapter->adapt_dev); 878 struct ata_channel *chp = 879 atac->atac_channels[periph->periph_channel->chan_channel]; 880 881 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 882 } 883 #endif /* NATAPIBUS > 0 */ 884 #endif /* MVSATA_WITHOUTDMA */ 885 886 887 /* 888 * mvsata_setup_channel() 889 * Setup EDMA registers and prepare/purge DMA resources. 890 * We assuming already stopped the EDMA. 891 */ 892 static void 893 mvsata_setup_channel(struct ata_channel *chp) 894 { 895 #ifndef MVSATA_WITHOUTDMA 896 struct mvsata_port *mvport = (struct mvsata_port *)chp; 897 struct ata_drive_datas *drvp; 898 int drive, s; 899 uint32_t edma_mode = nodma; 900 int i; 901 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 902 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 903 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 904 905 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 906 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 907 908 for (drive = 0; drive < chp->ch_ndrives; drive++) { 909 drvp = &chp->ch_drive[drive]; 910 911 /* If no drive, skip */ 912 if (drvp->drive_type == ATA_DRIVET_NONE) 913 continue; 914 915 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 916 /* use Ultra/DMA */ 917 s = splbio(); 918 drvp->drive_flags &= ~ATA_DRIVE_DMA; 919 splx(s); 920 } 921 922 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 923 if (drvp->drive_flags & ATA_DRIVE_NCQ) 924 edma_mode = ncq; 925 else if (drvp->drive_type == ATA_DRIVET_ATA) 926 edma_mode = dma; 927 } 928 } 929 930 DPRINTF(DEBUG_FUNCS, 931 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 932 933 if (edma_mode == nodma) { 934 no_edma: 935 if (mvport->port_crqb != NULL) 936 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 937 mvport->port_crqb_dmamap, mvport->port_crqb); 938 if (mvport->port_crpb != NULL) 939 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 940 mvport->port_crpb_dmamap, mvport->port_crpb); 941 if (mvport->port_eprd != NULL) 942 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 943 mvport->port_eprd_dmamap, mvport->port_eprd); 944 945 return; 946 } 947 948 if (mvport->port_crqb == NULL) 949 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 950 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 951 if (mvport->port_crpb == NULL) 952 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 953 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 954 if (mvport->port_eprd == NULL) { 955 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 956 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 957 1); 958 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 959 mvport->port_reqtbl[i].eprd_offset = 960 i * MVSATA_EPRD_MAX_SIZE; 961 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 962 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 963 } 964 } 965 966 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 967 mvport->port_eprd == NULL) { 968 aprint_error_dev(MVSATA_DEV2(mvport), 969 "channel %d: can't use EDMA\n", chp->ch_channel); 970 s = splbio(); 971 for (drive = 0; drive < chp->ch_ndrives; drive++) { 972 drvp = &chp->ch_drive[drive]; 973 974 /* If no drive, skip */ 975 if (drvp->drive_type == ATA_DRIVET_NONE) 976 continue; 977 978 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 979 } 980 splx(s); 981 goto no_edma; 982 } 983 984 mvsata_edma_config(mvport, edma_mode); 985 mvsata_edma_reset_qptr(mvport); 986 mvsata_edma_enable(mvport); 987 #endif 988 } 989 990 #ifndef MVSATA_WITHOUTDMA 991 static const struct ata_xfer_ops mvsata_bio_xfer_ops = { 992 .c_start = mvsata_bio_start, 993 .c_intr = mvsata_bio_intr, 994 .c_poll = mvsata_bio_poll, 995 .c_abort = mvsata_bio_done, 996 .c_kill_xfer = mvsata_bio_kill_xfer, 997 }; 998 999 static int 1000 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1001 { 1002 struct ata_channel *chp = drvp->chnl_softc; 1003 struct atac_softc *atac = chp->ch_atac; 1004 struct ata_bio *ata_bio = &xfer->c_bio; 1005 1006 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1007 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 1008 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 1009 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 1010 1011 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1012 ata_bio->flags |= ATA_POLL; 1013 if (ata_bio->flags & ATA_POLL) 1014 xfer->c_flags |= C_POLL; 1015 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1016 (ata_bio->flags & ATA_SINGLE) == 0) 1017 xfer->c_flags |= C_DMA; 1018 xfer->c_drive = drvp->drive; 1019 xfer->c_databuf = ata_bio->databuf; 1020 xfer->c_bcount = ata_bio->bcount; 1021 xfer->ops = &mvsata_bio_xfer_ops; 1022 ata_exec_xfer(chp, xfer); 1023 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1024 } 1025 1026 static int 1027 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1028 { 1029 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1030 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1031 struct atac_softc *atac = chp->ch_atac; 1032 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1033 struct ata_bio *ata_bio = &xfer->c_bio; 1034 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1035 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1036 u_int16_t cyl; 1037 u_int8_t head, sect, cmd = 0; 1038 int nblks, error, tfd; 1039 1040 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1041 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1042 1043 ata_channel_lock_owned(chp); 1044 1045 if (xfer->c_flags & C_DMA) 1046 if (drvp->n_xfers <= NXFER) 1047 drvp->n_xfers++; 1048 1049 /* 1050 * 1051 * When starting a multi-sector transfer, or doing single-sector 1052 * transfers... 1053 */ 1054 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1055 if (ata_bio->flags & ATA_SINGLE) 1056 nblks = 1; 1057 else 1058 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1059 /* Check for bad sectors and adjust transfer, if necessary. */ 1060 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1061 long blkdiff; 1062 int i; 1063 1064 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1065 i++) { 1066 blkdiff -= ata_bio->blkno; 1067 if (blkdiff < 0) 1068 continue; 1069 if (blkdiff == 0) 1070 /* Replace current block of transfer. */ 1071 ata_bio->blkno = 1072 drvp->lp->d_secperunit - 1073 drvp->lp->d_nsectors - i - 1; 1074 if (blkdiff < nblks) { 1075 /* Bad block inside transfer. */ 1076 ata_bio->flags |= ATA_SINGLE; 1077 nblks = 1; 1078 } 1079 break; 1080 } 1081 /* Transfer is okay now. */ 1082 } 1083 if (xfer->c_flags & C_DMA) { 1084 enum mvsata_edmamode dmamode; 1085 1086 ata_bio->nblks = nblks; 1087 ata_bio->nbytes = xfer->c_bcount; 1088 1089 /* switch to appropriate dma mode if necessary */ 1090 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1091 if (mvport->port_edmamode_curr != dmamode) 1092 mvsata_edma_config(mvport, dmamode); 1093 1094 if (xfer->c_flags & C_POLL) 1095 sc->sc_enable_intr(mvport, 0 /*off*/); 1096 error = mvsata_edma_enqueue(mvport, xfer); 1097 if (error) { 1098 if (error == EINVAL) { 1099 /* 1100 * We can't do DMA on this transfer 1101 * for some reason. Fall back to 1102 * PIO. 1103 */ 1104 xfer->c_flags &= ~C_DMA; 1105 error = 0; 1106 goto do_pio; 1107 } 1108 if (error == EBUSY) { 1109 aprint_error_dev(atac->atac_dev, 1110 "channel %d: EDMA Queue full\n", 1111 chp->ch_channel); 1112 /* 1113 * XXX: Perhaps, after it waits for 1114 * a while, it is necessary to call 1115 * bio_start again. 1116 */ 1117 } 1118 ata_bio->error = ERR_DMA; 1119 ata_bio->r_error = 0; 1120 return ATASTART_ABORT; 1121 } 1122 chp->ch_flags |= ATACH_DMA_WAIT; 1123 /* start timeout machinery */ 1124 if ((xfer->c_flags & C_POLL) == 0) 1125 callout_reset(&chp->c_timo_callout, 1126 mstohz(ATA_DELAY), ata_timeout, chp); 1127 /* wait for irq */ 1128 goto intr; 1129 } /* else not DMA */ 1130 do_pio: 1131 if (ata_bio->flags & ATA_LBA48) { 1132 sect = 0; 1133 cyl = 0; 1134 head = 0; 1135 } else if (ata_bio->flags & ATA_LBA) { 1136 sect = (ata_bio->blkno >> 0) & 0xff; 1137 cyl = (ata_bio->blkno >> 8) & 0xffff; 1138 head = (ata_bio->blkno >> 24) & 0x0f; 1139 head |= WDSD_LBA; 1140 } else { 1141 int blkno = ata_bio->blkno; 1142 sect = blkno % drvp->lp->d_nsectors; 1143 sect++; /* Sectors begin with 1, not 0. */ 1144 blkno /= drvp->lp->d_nsectors; 1145 head = blkno % drvp->lp->d_ntracks; 1146 blkno /= drvp->lp->d_ntracks; 1147 cyl = blkno; 1148 head |= WDSD_CHS; 1149 } 1150 ata_bio->nblks = uimin(nblks, drvp->multi); 1151 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1152 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1153 if (ata_bio->nblks > 1) 1154 cmd = (ata_bio->flags & ATA_READ) ? 1155 WDCC_READMULTI : WDCC_WRITEMULTI; 1156 else 1157 cmd = (ata_bio->flags & ATA_READ) ? 1158 WDCC_READ : WDCC_WRITE; 1159 1160 /* EDMA disable, if enabled this channel. */ 1161 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1162 if (mvport->port_edmamode_curr != nodma) 1163 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1164 1165 mvsata_pmp_select(mvport, xfer->c_drive); 1166 1167 /* Do control operations specially. */ 1168 if (__predict_false(drvp->state < READY)) { 1169 /* 1170 * Actually, we want to be careful not to mess with 1171 * the control state if the device is currently busy, 1172 * but we can assume that we never get to this point 1173 * if that's the case. 1174 */ 1175 /* 1176 * If it's not a polled command, we need the kernel 1177 * thread 1178 */ 1179 if ((xfer->c_flags & C_POLL) == 0 && 1180 (chp->ch_flags & ATACH_TH_RUN) == 0) { 1181 return ATASTART_TH; 1182 } 1183 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1184 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1185 return ATASTART_ABORT; 1186 } 1187 } 1188 1189 /* Initiate command! */ 1190 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1191 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1192 case WDCWAIT_OK: 1193 break; 1194 case WDCWAIT_TOUT: 1195 goto timeout; 1196 case WDCWAIT_THR: 1197 return ATASTART_TH; 1198 } 1199 if (ata_bio->flags & ATA_LBA48) 1200 wdccommandext(chp, 0, atacmd_to48(cmd), 1201 ata_bio->blkno, nblks, 0, WDSD_LBA); 1202 else 1203 wdccommand(chp, 0, cmd, cyl, 1204 head, sect, nblks, 1205 (drvp->lp->d_type == DKTYPE_ST506) ? 1206 drvp->lp->d_precompcyl / 4 : 0); 1207 1208 /* start timeout machinery */ 1209 if ((xfer->c_flags & C_POLL) == 0) 1210 callout_reset(&chp->c_timo_callout, 1211 mstohz(ATA_DELAY), wdctimeout, chp); 1212 } else if (ata_bio->nblks > 1) { 1213 /* The number of blocks in the last stretch may be smaller. */ 1214 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1215 if (ata_bio->nblks > nblks) { 1216 ata_bio->nblks = nblks; 1217 ata_bio->nbytes = xfer->c_bcount; 1218 } 1219 } 1220 /* If this was a write and not using DMA, push the data. */ 1221 if ((ata_bio->flags & ATA_READ) == 0) { 1222 /* 1223 * we have to busy-wait here, we can't rely on running in 1224 * thread context. 1225 */ 1226 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1227 aprint_error_dev(atac->atac_dev, 1228 "channel %d: drive %d timeout waiting for DRQ," 1229 " st=0x%02x, err=0x%02x\n", 1230 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1231 ATACH_ERR(tfd)); 1232 ata_bio->error = TIMEOUT; 1233 return ATASTART_ABORT; 1234 } 1235 if (ATACH_ST(tfd) & WDCS_ERR) { 1236 ata_bio->error = ERROR; 1237 ata_bio->r_error = ATACH_ERR(tfd); 1238 mvsata_bio_done(chp, xfer); 1239 return ATASTART_ABORT; 1240 } 1241 1242 wdc->dataout_pio(chp, drvp->drive_flags, 1243 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1244 } 1245 1246 intr: 1247 KASSERTMSG(((xfer->c_flags & C_DMA) != 0) 1248 == (mvport->port_edmamode_curr != nodma), 1249 "DMA mode mismatch: flags %x vs edmamode %d != %d", 1250 xfer->c_flags, mvport->port_edmamode_curr, nodma); 1251 1252 /* Wait for IRQ (either real or polled) */ 1253 if ((ata_bio->flags & ATA_POLL) != 0) 1254 return ATASTART_POLL; 1255 else 1256 return ATASTART_STARTED; 1257 1258 timeout: 1259 aprint_error_dev(atac->atac_dev, 1260 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1261 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1262 ata_bio->error = TIMEOUT; 1263 return ATASTART_ABORT; 1264 } 1265 1266 static void 1267 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1268 { 1269 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1270 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1271 1272 /* Wait for at last 400ns for status bit to be valid */ 1273 delay(1); 1274 if (chp->ch_flags & ATACH_DMA_WAIT) { 1275 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1276 sc->sc_enable_intr(mvport, 1 /*on*/); 1277 chp->ch_flags &= ~ATACH_DMA_WAIT; 1278 } 1279 1280 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1281 KASSERT(xfer->c_flags & C_TIMEOU); 1282 mvsata_bio_intr(chp, xfer, 0); 1283 } 1284 } 1285 1286 static int 1287 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int intr_arg) 1288 { 1289 struct atac_softc *atac = chp->ch_atac; 1290 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1291 struct ata_bio *ata_bio = &xfer->c_bio; 1292 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1293 int irq = ISSET(xfer->c_flags, (C_POLL|C_TIMEOU)) ? 0 : 1; 1294 int tfd = 0; 1295 1296 if (ISSET(xfer->c_flags, C_DMA|C_RECOVERED) && irq) { 1297 /* Invoked via mvsata_edma_handle() or recovery */ 1298 tfd = intr_arg; 1299 1300 if (tfd > 0 && ata_bio->error == NOERROR) { 1301 if (ATACH_ST(tfd) & WDCS_ERR) 1302 ata_bio->error = ERROR; 1303 if (ATACH_ST(tfd) & WDCS_BSY) 1304 ata_bio->error = TIMEOUT; 1305 ata_bio->r_error = ATACH_ERR(tfd); 1306 } 1307 } 1308 1309 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1310 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1311 xfer->c_drive)); 1312 1313 /* Cleanup EDMA if invoked from wdctimeout()/ata_timeout() */ 1314 if (ISSET(xfer->c_flags, C_TIMEOU) && ISSET(xfer->c_flags, C_DMA) 1315 && !ISSET(xfer->c_flags, C_POLL)) { 1316 mvsata_edma_rqq_remove((struct mvsata_port *)chp, xfer); 1317 } 1318 1319 ata_channel_lock(chp); 1320 1321 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1322 1323 /* 1324 * If we missed an interrupt transfer, reset and restart. 1325 * Don't try to continue transfer, we may have missed cycles. 1326 */ 1327 if (xfer->c_flags & C_TIMEOU) { 1328 ata_bio->error = TIMEOUT; 1329 ata_channel_unlock(chp); 1330 mvsata_bio_done(chp, xfer); 1331 return 1; 1332 } 1333 1334 /* Is it not a transfer, but a control operation? */ 1335 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1336 aprint_error_dev(atac->atac_dev, 1337 "channel %d: drive %d bad state %d in %s\n", 1338 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1339 panic("%s: bad state", __func__); 1340 } 1341 1342 /* Ack interrupt done by wdc_wait_for_unbusy */ 1343 if (!(xfer->c_flags & C_DMA) && 1344 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1345 == WDCWAIT_TOUT)) { 1346 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1347 ata_channel_unlock(chp); 1348 return 0; /* IRQ was not for us */ 1349 } 1350 aprint_error_dev(atac->atac_dev, 1351 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1352 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1353 xfer->c_skip); 1354 ata_bio->error = TIMEOUT; 1355 ata_channel_unlock(chp); 1356 mvsata_bio_done(chp, xfer); 1357 return 1; 1358 } 1359 1360 if (xfer->c_flags & C_DMA) { 1361 if (ata_bio->error == NOERROR) 1362 goto end; 1363 if (ata_bio->error == ERR_DMA) { 1364 ata_dmaerr(drvp, 1365 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1366 ata_channel_unlock(chp); 1367 goto err; 1368 } 1369 } 1370 1371 /* if we had an error, end */ 1372 if (ata_bio->error != NOERROR) { 1373 ata_channel_unlock(chp); 1374 err: 1375 mvsata_bio_done(chp, xfer); 1376 return 1; 1377 } 1378 1379 /* If this was a read and not using DMA, fetch the data. */ 1380 if ((ata_bio->flags & ATA_READ) != 0) { 1381 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1382 aprint_error_dev(atac->atac_dev, 1383 "channel %d: drive %d read intr before drq\n", 1384 chp->ch_channel, xfer->c_drive); 1385 ata_bio->error = TIMEOUT; 1386 ata_channel_unlock(chp); 1387 mvsata_bio_done(chp, xfer); 1388 return 1; 1389 } 1390 wdc->datain_pio(chp, drvp->drive_flags, 1391 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1392 } 1393 1394 end: 1395 ata_bio->blkno += ata_bio->nblks; 1396 ata_bio->blkdone += ata_bio->nblks; 1397 xfer->c_skip += ata_bio->nbytes; 1398 xfer->c_bcount -= ata_bio->nbytes; 1399 1400 /* See if this transfer is complete. */ 1401 if (xfer->c_bcount > 0) { 1402 if ((ata_bio->flags & ATA_POLL) == 0) { 1403 /* Start the next operation */ 1404 ata_xfer_start(xfer); 1405 } else { 1406 /* Let mvsata_bio_start do the loop */ 1407 } 1408 ata_channel_unlock(chp); 1409 } else { /* Done with this transfer */ 1410 ata_bio->error = NOERROR; 1411 ata_channel_unlock(chp); 1412 mvsata_bio_done(chp, xfer); 1413 } 1414 return 1; 1415 } 1416 1417 static void 1418 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1419 { 1420 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1421 struct atac_softc *atac = chp->ch_atac; 1422 struct ata_bio *ata_bio = &xfer->c_bio; 1423 int drive = xfer->c_drive; 1424 bool deactivate = true; 1425 1426 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1427 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1428 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1429 1430 /* EDMA restart, if enabled */ 1431 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1432 mvsata_edma_reset_qptr(mvport); 1433 mvsata_edma_enable(mvport); 1434 } 1435 1436 ata_bio->flags |= ATA_ITSDONE; 1437 switch (reason) { 1438 case KILL_GONE_INACTIVE: 1439 deactivate = false; 1440 /* FALLTHROUGH */ 1441 case KILL_GONE: 1442 ata_bio->error = ERR_NODEV; 1443 break; 1444 case KILL_RESET: 1445 ata_bio->error = ERR_RESET; 1446 break; 1447 case KILL_REQUEUE: 1448 ata_bio->error = REQUEUE; 1449 break; 1450 default: 1451 aprint_error_dev(atac->atac_dev, 1452 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1453 panic("mvsata_bio_kill_xfer"); 1454 } 1455 ata_bio->r_error = WDCE_ABRT; 1456 1457 if (deactivate) 1458 ata_deactivate_xfer(chp, xfer); 1459 1460 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1461 } 1462 1463 static void 1464 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1465 { 1466 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1467 struct ata_bio *ata_bio = &xfer->c_bio; 1468 int drive = xfer->c_drive; 1469 bool iserror = (ata_bio->error != NOERROR); 1470 1471 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1472 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1473 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1474 (u_int)xfer->c_flags)); 1475 1476 /* EDMA restart, if enabled */ 1477 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1478 mvsata_edma_reset_qptr(mvport); 1479 mvsata_edma_enable(mvport); 1480 } 1481 1482 if (ata_waitdrain_xfer_check(chp, xfer)) 1483 return; 1484 1485 /* feed back residual bcount to our caller */ 1486 ata_bio->bcount = xfer->c_bcount; 1487 1488 /* mark controller inactive and free xfer */ 1489 ata_deactivate_xfer(chp, xfer); 1490 1491 ata_bio->flags |= ATA_ITSDONE; 1492 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1493 if (!iserror) 1494 atastart(chp); 1495 } 1496 1497 static int 1498 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1499 int flags) 1500 { 1501 struct ata_channel *chp = &mvport->port_ata_channel; 1502 struct atac_softc *atac = chp->ch_atac; 1503 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1504 const char *errstring; 1505 int tfd; 1506 1507 flags |= AT_POLL; /* XXX */ 1508 1509 ata_channel_lock_owned(chp); 1510 1511 /* 1512 * disable interrupts, all commands here should be quick 1513 * enough to be able to poll, and we don't go here that often 1514 */ 1515 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1516 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1517 DELAY(10); 1518 errstring = "wait"; 1519 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1520 goto ctrltimeout; 1521 wdccommandshort(chp, 0, WDCC_RECAL); 1522 /* Wait for at least 400ns for status bit to be valid */ 1523 DELAY(1); 1524 errstring = "recal"; 1525 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1526 goto ctrltimeout; 1527 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1528 goto ctrlerror; 1529 /* Don't try to set modes if controller can't be adjusted */ 1530 if (atac->atac_set_modes == NULL) 1531 goto geometry; 1532 /* Also don't try if the drive didn't report its mode */ 1533 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1534 goto geometry; 1535 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1536 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1537 errstring = "piomode-bio"; 1538 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1539 goto ctrltimeout; 1540 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1541 goto ctrlerror; 1542 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1543 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1544 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1545 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1546 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1547 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1548 else 1549 goto geometry; 1550 errstring = "dmamode-bio"; 1551 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1552 goto ctrltimeout; 1553 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1554 goto ctrlerror; 1555 geometry: 1556 if (ata_bio->flags & ATA_LBA) 1557 goto multimode; 1558 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1559 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1560 (drvp->lp->d_type == DKTYPE_ST506) ? 1561 drvp->lp->d_precompcyl / 4 : 0); 1562 errstring = "geometry"; 1563 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1564 goto ctrltimeout; 1565 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1566 goto ctrlerror; 1567 multimode: 1568 if (drvp->multi == 1) 1569 goto ready; 1570 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1571 errstring = "setmulti"; 1572 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1573 goto ctrltimeout; 1574 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1575 goto ctrlerror; 1576 ready: 1577 drvp->state = READY; 1578 /* 1579 * The drive is usable now 1580 */ 1581 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1582 delay(10); /* some drives need a little delay here */ 1583 return 0; 1584 1585 ctrltimeout: 1586 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1587 chp->ch_channel, drive, errstring); 1588 ata_bio->error = TIMEOUT; 1589 goto ctrldone; 1590 ctrlerror: 1591 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1592 chp->ch_channel, drive, errstring); 1593 if (ATACH_ST(tfd) & WDCS_DWF) { 1594 aprint_error("drive fault\n"); 1595 ata_bio->error = ERR_DF; 1596 } else { 1597 ata_bio->r_error = ATACH_ERR(tfd); 1598 ata_bio->error = ERROR; 1599 aprint_error("error (%x)\n", ata_bio->r_error); 1600 } 1601 ctrldone: 1602 drvp->state = 0; 1603 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1604 return -1; 1605 } 1606 1607 static const struct ata_xfer_ops mvsata_wdc_cmd_xfer_ops = { 1608 .c_start = mvsata_wdc_cmd_start, 1609 .c_intr = mvsata_wdc_cmd_intr, 1610 .c_poll = mvsata_wdc_cmd_poll, 1611 .c_abort = mvsata_wdc_cmd_done, 1612 .c_kill_xfer = mvsata_wdc_cmd_kill_xfer, 1613 }; 1614 1615 static int 1616 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1617 { 1618 struct ata_channel *chp = drvp->chnl_softc; 1619 struct ata_command *ata_c = &xfer->c_ata_c; 1620 int rv, s; 1621 1622 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1623 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1624 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1625 " r_device=0x%02x, r_command=0x%02x\n", 1626 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1627 chp->ch_channel, 1628 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1629 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1630 1631 if (ata_c->flags & AT_POLL) 1632 xfer->c_flags |= C_POLL; 1633 if (ata_c->flags & AT_WAIT) 1634 xfer->c_flags |= C_WAIT; 1635 xfer->c_drive = drvp->drive; 1636 xfer->c_databuf = ata_c->data; 1637 xfer->c_bcount = ata_c->bcount; 1638 xfer->ops = &mvsata_wdc_cmd_xfer_ops; 1639 s = splbio(); 1640 ata_exec_xfer(chp, xfer); 1641 #ifdef DIAGNOSTIC 1642 if ((ata_c->flags & AT_POLL) != 0 && 1643 (ata_c->flags & AT_DONE) == 0) 1644 panic("mvsata_exec_command: polled command not done"); 1645 #endif 1646 if (ata_c->flags & AT_DONE) 1647 rv = ATACMD_COMPLETE; 1648 else { 1649 if (ata_c->flags & AT_WAIT) { 1650 ata_wait_cmd(chp, xfer); 1651 rv = ATACMD_COMPLETE; 1652 } else 1653 rv = ATACMD_QUEUED; 1654 } 1655 splx(s); 1656 return rv; 1657 } 1658 1659 static int 1660 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1661 { 1662 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1663 int drive = xfer->c_drive; 1664 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1665 struct ata_command *ata_c = &xfer->c_ata_c; 1666 int tfd; 1667 1668 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1669 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1670 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1671 1672 ata_channel_lock_owned(chp); 1673 1674 /* First, EDMA disable, if enabled this channel. */ 1675 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1676 if (mvport->port_edmamode_curr != nodma) 1677 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1678 1679 mvsata_pmp_select(mvport, drive); 1680 1681 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1682 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1683 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1684 case WDCWAIT_OK: 1685 break; 1686 case WDCWAIT_TOUT: 1687 ata_c->flags |= AT_TIMEOU; 1688 return ATASTART_ABORT; 1689 case WDCWAIT_THR: 1690 return ATASTART_TH; 1691 } 1692 if (ata_c->flags & AT_POLL) 1693 /* polled command, disable interrupts */ 1694 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1695 if ((ata_c->flags & AT_LBA48) != 0) { 1696 wdccommandext(chp, 0, ata_c->r_command, 1697 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1698 ata_c->r_device & ~0x10); 1699 } else { 1700 wdccommand(chp, 0, ata_c->r_command, 1701 (ata_c->r_lba >> 8) & 0xffff, 1702 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1703 ((ata_c->r_lba >> 24) & 0x0f), 1704 ata_c->r_lba & 0xff, 1705 ata_c->r_count & 0xff, 1706 ata_c->r_features & 0xff); 1707 } 1708 1709 if ((ata_c->flags & AT_POLL) == 0) { 1710 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1711 wdctimeout, chp); 1712 return ATASTART_STARTED; 1713 } 1714 1715 return ATASTART_POLL; 1716 } 1717 1718 static void 1719 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1720 { 1721 /* 1722 * Polled command. Wait for drive ready or drq. Done in intr(). 1723 * Wait for at last 400ns for status bit to be valid. 1724 */ 1725 delay(10); /* 400ns delay */ 1726 mvsata_wdc_cmd_intr(chp, xfer, 0); 1727 } 1728 1729 static int 1730 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1731 { 1732 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1733 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1734 struct ata_command *ata_c = &xfer->c_ata_c; 1735 int bcount = ata_c->bcount; 1736 char *data = ata_c->data; 1737 int wflags; 1738 int drive_flags; 1739 int tfd; 1740 1741 ata_channel_lock(chp); 1742 1743 if (ata_c->r_command == WDCC_IDENTIFY || 1744 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1745 /* 1746 * The IDENTIFY data has been designed as an array of 1747 * u_int16_t, so we can byteswap it on the fly. 1748 * Historically it's what we have always done so keeping it 1749 * here ensure binary backward compatibility. 1750 */ 1751 drive_flags = ATA_DRIVE_NOSTREAM | 1752 chp->ch_drive[xfer->c_drive].drive_flags; 1753 else 1754 /* 1755 * Other data structure are opaque and should be transfered 1756 * as is. 1757 */ 1758 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1759 1760 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1761 /* both wait and poll, we can kpause here */ 1762 wflags = AT_WAIT | AT_POLL; 1763 else 1764 wflags = AT_POLL; 1765 1766 again: 1767 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1768 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1769 __func__, xfer->c_drive)); 1770 1771 /* 1772 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1773 * Reselect again, it doesn't hurt for others commands, and the time 1774 * penalty for the extra register write is acceptable, 1775 * wdc_exec_command() isn't called often (mostly for autoconfig) 1776 */ 1777 if ((xfer->c_flags & C_ATAPI) != 0) { 1778 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1779 } 1780 if ((ata_c->flags & AT_XFDONE) != 0) { 1781 /* 1782 * We have completed a data xfer. The drive should now be 1783 * in its initial state 1784 */ 1785 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1786 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1787 wflags, &tfd) == WDCWAIT_TOUT) { 1788 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1789 ata_channel_unlock(chp); 1790 return 0; /* IRQ was not for us */ 1791 } 1792 ata_c->flags |= AT_TIMEOU; 1793 } 1794 goto out; 1795 } 1796 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1797 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1798 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1799 ata_channel_unlock(chp); 1800 return 0; /* IRQ was not for us */ 1801 } 1802 ata_c->flags |= AT_TIMEOU; 1803 goto out; 1804 } 1805 delay(20); /* XXXXX: Delay more times. */ 1806 if (ata_c->flags & AT_READ) { 1807 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1808 ata_c->flags |= AT_TIMEOU; 1809 goto out; 1810 } 1811 wdc->datain_pio(chp, drive_flags, data, bcount); 1812 /* at this point the drive should be in its initial state */ 1813 ata_c->flags |= AT_XFDONE; 1814 /* 1815 * XXX checking the status register again here cause some 1816 * hardware to timeout. 1817 */ 1818 } else if (ata_c->flags & AT_WRITE) { 1819 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1820 ata_c->flags |= AT_TIMEOU; 1821 goto out; 1822 } 1823 wdc->dataout_pio(chp, drive_flags, data, bcount); 1824 ata_c->flags |= AT_XFDONE; 1825 if ((ata_c->flags & AT_POLL) == 0) { 1826 callout_reset(&chp->c_timo_callout, 1827 mstohz(ata_c->timeout), wdctimeout, chp); 1828 ata_channel_unlock(chp); 1829 return 1; 1830 } else 1831 goto again; 1832 } 1833 out: 1834 if (ATACH_ST(tfd) & WDCS_DWF) 1835 ata_c->flags |= AT_DF; 1836 if (ATACH_ST(tfd) & WDCS_ERR) { 1837 ata_c->flags |= AT_ERROR; 1838 ata_c->r_error = ATACH_ERR(tfd); 1839 } 1840 ata_channel_unlock(chp); 1841 mvsata_wdc_cmd_done(chp, xfer); 1842 1843 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1844 atastart(chp); 1845 1846 return 1; 1847 } 1848 1849 static void 1850 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1851 int reason) 1852 { 1853 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1854 struct ata_command *ata_c = &xfer->c_ata_c; 1855 bool deactivate = true; 1856 1857 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1858 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1859 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1860 1861 switch (reason) { 1862 case KILL_GONE_INACTIVE: 1863 deactivate = false; 1864 /* FALLTHROUGH */ 1865 case KILL_GONE: 1866 ata_c->flags |= AT_GONE; 1867 break; 1868 case KILL_RESET: 1869 ata_c->flags |= AT_RESET; 1870 break; 1871 case KILL_REQUEUE: 1872 panic("%s: not supposed to be requeued\n", __func__); 1873 break; 1874 default: 1875 aprint_error_dev(MVSATA_DEV2(mvport), 1876 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1877 panic("mvsata_cmd_kill_xfer"); 1878 } 1879 1880 mvsata_wdc_cmd_done_end(chp, xfer); 1881 1882 if (deactivate) 1883 ata_deactivate_xfer(chp, xfer); 1884 } 1885 1886 static void 1887 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1888 { 1889 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1890 struct atac_softc *atac = chp->ch_atac; 1891 struct ata_command *ata_c = &xfer->c_ata_c; 1892 1893 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1894 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1895 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1896 ata_c->flags)); 1897 1898 if (ata_waitdrain_xfer_check(chp, xfer)) 1899 return; 1900 1901 if ((ata_c->flags & AT_READREG) != 0 && 1902 device_is_active(atac->atac_dev) && 1903 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1904 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1905 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1906 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1907 ata_c->r_lba = 1908 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1909 ata_c->r_lba |= 1910 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1911 ata_c->r_lba |= 1912 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1913 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1914 if ((ata_c->flags & AT_LBA48) != 0) { 1915 if ((ata_c->flags & AT_POLL) != 0) { 1916 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1917 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1918 } else { 1919 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1920 WDCTL_HOB|WDCTL_4BIT); 1921 } 1922 ata_c->r_count |= 1923 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1924 ata_c->r_lba |= 1925 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1926 ata_c->r_lba |= 1927 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1928 ata_c->r_lba |= 1929 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1930 if ((ata_c->flags & AT_POLL) != 0) { 1931 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1932 WDCTL_4BIT|WDCTL_IDS); 1933 } else { 1934 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1935 WDCTL_4BIT); 1936 } 1937 } else { 1938 ata_c->r_lba |= 1939 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1940 } 1941 } 1942 1943 if (ata_c->flags & AT_POLL) { 1944 /* enable interrupts */ 1945 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1946 delay(10); /* some drives need a little delay here */ 1947 } 1948 1949 mvsata_wdc_cmd_done_end(chp, xfer); 1950 1951 ata_deactivate_xfer(chp, xfer); 1952 } 1953 1954 static void 1955 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1956 { 1957 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1958 struct ata_command *ata_c = &xfer->c_ata_c; 1959 1960 /* EDMA restart, if enabled */ 1961 if (mvport->port_edmamode_curr != nodma) { 1962 mvsata_edma_reset_qptr(mvport); 1963 mvsata_edma_enable(mvport); 1964 } 1965 1966 ata_c->flags |= AT_DONE; 1967 } 1968 1969 #if NATAPIBUS > 0 1970 static const struct ata_xfer_ops mvsata_atapi_xfer_ops = { 1971 .c_start = mvsata_atapi_start, 1972 .c_intr = mvsata_atapi_intr, 1973 .c_poll = mvsata_atapi_poll, 1974 .c_abort = mvsata_atapi_reset, 1975 .c_kill_xfer = mvsata_atapi_kill_xfer, 1976 }; 1977 1978 static void 1979 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 1980 scsipi_adapter_req_t req, void *arg) 1981 { 1982 struct scsipi_adapter *adapt = chan->chan_adapter; 1983 struct scsipi_periph *periph; 1984 struct scsipi_xfer *sc_xfer; 1985 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 1986 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1987 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1988 struct ata_xfer *xfer; 1989 int drive, s; 1990 1991 switch (req) { 1992 case ADAPTER_REQ_RUN_XFER: 1993 sc_xfer = arg; 1994 periph = sc_xfer->xs_periph; 1995 drive = periph->periph_target; 1996 1997 if (!device_is_active(atac->atac_dev)) { 1998 sc_xfer->error = XS_DRIVER_STUFFUP; 1999 scsipi_done(sc_xfer); 2000 return; 2001 } 2002 xfer = ata_get_xfer(chp, false); 2003 if (xfer == NULL) { 2004 sc_xfer->error = XS_RESOURCE_SHORTAGE; 2005 scsipi_done(sc_xfer); 2006 return; 2007 } 2008 2009 if (sc_xfer->xs_control & XS_CTL_POLL) 2010 xfer->c_flags |= C_POLL; 2011 xfer->c_drive = drive; 2012 xfer->c_flags |= C_ATAPI; 2013 xfer->c_databuf = sc_xfer->data; 2014 xfer->c_bcount = sc_xfer->datalen; 2015 xfer->ops = &mvsata_atapi_xfer_ops; 2016 xfer->c_scsipi = sc_xfer; 2017 xfer->c_atapi.c_dscpoll = 0; 2018 s = splbio(); 2019 ata_exec_xfer(chp, xfer); 2020 #ifdef DIAGNOSTIC 2021 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 2022 (sc_xfer->xs_status & XS_STS_DONE) == 0) 2023 panic("mvsata_atapi_scsipi_request:" 2024 " polled command not done"); 2025 #endif 2026 splx(s); 2027 return; 2028 2029 default: 2030 /* Not supported, nothing to do. */ 2031 ; 2032 } 2033 } 2034 2035 static int 2036 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2037 { 2038 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2039 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2040 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2041 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2042 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2043 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2044 const char *errstring; 2045 int tfd; 2046 2047 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2048 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2049 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2050 xfer->c_drive, sc_xfer->xs_control)); 2051 2052 ata_channel_lock_owned(chp); 2053 2054 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2055 if (mvport->port_edmamode_curr != nodma) 2056 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2057 2058 mvsata_pmp_select(mvport, xfer->c_drive); 2059 2060 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2061 drvp->n_xfers++; 2062 2063 /* Do control operations specially. */ 2064 if (__predict_false(drvp->state < READY)) { 2065 /* If it's not a polled command, we need the kernel thread */ 2066 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && 2067 (chp->ch_flags & ATACH_TH_RUN) == 0) { 2068 return ATASTART_TH; 2069 } 2070 /* 2071 * disable interrupts, all commands here should be quick 2072 * enough to be able to poll, and we don't go here that often 2073 */ 2074 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2075 2076 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2077 /* Don't try to set mode if controller can't be adjusted */ 2078 if (atac->atac_set_modes == NULL) 2079 goto ready; 2080 /* Also don't try if the drive didn't report its mode */ 2081 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2082 goto ready; 2083 errstring = "unbusy"; 2084 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2085 goto timeout; 2086 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2087 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2088 errstring = "piomode-atapi"; 2089 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2090 &tfd)) 2091 goto timeout; 2092 if (ATACH_ST(tfd) & WDCS_ERR) { 2093 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2094 /* 2095 * Some ATAPI drives reject PIO settings. 2096 * Fall back to PIO mode 3 since that's the 2097 * minimum for ATAPI. 2098 */ 2099 aprint_error_dev(atac->atac_dev, 2100 "channel %d drive %d: PIO mode %d rejected," 2101 " falling back to PIO mode 3\n", 2102 chp->ch_channel, xfer->c_drive, 2103 drvp->PIO_mode); 2104 if (drvp->PIO_mode > 3) 2105 drvp->PIO_mode = 3; 2106 } else 2107 goto error; 2108 } 2109 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2110 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2111 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2112 else 2113 if (drvp->drive_flags & ATA_DRIVE_DMA) 2114 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2115 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2116 else 2117 goto ready; 2118 errstring = "dmamode-atapi"; 2119 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2120 &tfd)) 2121 goto timeout; 2122 if (ATACH_ST(tfd) & WDCS_ERR) { 2123 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2124 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2125 goto error; 2126 else { 2127 /* 2128 * The drive rejected our DMA setting. 2129 * Fall back to mode 1. 2130 */ 2131 aprint_error_dev(atac->atac_dev, 2132 "channel %d drive %d:" 2133 " DMA mode %d rejected," 2134 " falling back to DMA mode 0\n", 2135 chp->ch_channel, xfer->c_drive, 2136 drvp->DMA_mode); 2137 if (drvp->DMA_mode > 0) 2138 drvp->DMA_mode = 0; 2139 } 2140 } else 2141 goto error; 2142 } 2143 ready: 2144 drvp->state = READY; 2145 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2146 delay(10); /* some drives need a little delay here */ 2147 } 2148 /* start timeout machinery */ 2149 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2150 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 2151 wdctimeout, chp); 2152 2153 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2154 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2155 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2156 ATACH_ST(tfd)); 2157 sc_xfer->error = XS_TIMEOUT; 2158 return ATASTART_ABORT; 2159 } 2160 2161 /* 2162 * Even with WDCS_ERR, the device should accept a command packet 2163 * Limit length to what can be stuffed into the cylinder register 2164 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2165 * but not all devices do that and it's not obvious from the 2166 * ATAPI spec that that behaviour should be expected. If more 2167 * data is necessary, multiple data transfer phases will be done. 2168 */ 2169 2170 wdccommand(chp, 0, ATAPI_PKT_CMD, 2171 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2172 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2173 2174 /* 2175 * If there is no interrupt for CMD input, busy-wait for it (done in 2176 * the interrupt routine. Poll routine will exit early in this case. 2177 */ 2178 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2179 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2180 return ATASTART_POLL; 2181 else 2182 return ATASTART_STARTED; 2183 2184 timeout: 2185 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2186 chp->ch_channel, xfer->c_drive, errstring); 2187 sc_xfer->error = XS_TIMEOUT; 2188 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2189 delay(10); /* some drives need a little delay here */ 2190 return ATASTART_ABORT; 2191 2192 error: 2193 aprint_error_dev(atac->atac_dev, 2194 "channel %d drive %d: %s error (0x%x)\n", 2195 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2196 sc_xfer->error = XS_SHORTSENSE; 2197 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2198 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2199 delay(10); /* some drives need a little delay here */ 2200 return ATASTART_ABORT; 2201 } 2202 2203 static void 2204 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2205 { 2206 /* 2207 * If there is no interrupt for CMD input, busy-wait for it (done in 2208 * the interrupt routine. If it is a polled command, call the interrupt 2209 * routine until command is done. 2210 */ 2211 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2212 2213 /* Wait for at last 400ns for status bit to be valid */ 2214 DELAY(1); 2215 mvsata_atapi_intr(chp, xfer, 0); 2216 2217 if (!poll) 2218 return; 2219 2220 if (chp->ch_flags & ATACH_DMA_WAIT) { 2221 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2222 chp->ch_flags &= ~ATACH_DMA_WAIT; 2223 } 2224 2225 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2226 /* Wait for at last 400ns for status bit to be valid */ 2227 DELAY(1); 2228 mvsata_atapi_intr(chp, xfer, 0); 2229 } 2230 } 2231 2232 static int 2233 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2234 { 2235 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2236 struct atac_softc *atac = chp->ch_atac; 2237 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2238 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2239 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2240 int len, phase, ire, error, retries=0, i; 2241 int tfd; 2242 void *cmd; 2243 2244 ata_channel_lock(chp); 2245 2246 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2247 ("%s:%d:%d: mvsata_atapi_intr\n", 2248 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2249 2250 /* Is it not a transfer, but a control operation? */ 2251 if (drvp->state < READY) { 2252 aprint_error_dev(atac->atac_dev, 2253 "channel %d drive %d: bad state %d\n", 2254 chp->ch_channel, xfer->c_drive, drvp->state); 2255 panic("mvsata_atapi_intr: bad state"); 2256 } 2257 /* 2258 * If we missed an interrupt in a PIO transfer, reset and restart. 2259 * Don't try to continue transfer, we may have missed cycles. 2260 */ 2261 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2262 ata_channel_unlock(chp); 2263 sc_xfer->error = XS_TIMEOUT; 2264 mvsata_atapi_reset(chp, xfer); 2265 return 1; 2266 } 2267 2268 /* Ack interrupt done in wdc_wait_for_unbusy */ 2269 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2270 if (wdc_wait_for_unbusy(chp, 2271 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2272 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2273 ata_channel_unlock(chp); 2274 return 0; /* IRQ was not for us */ 2275 } 2276 aprint_error_dev(atac->atac_dev, 2277 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2278 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2279 if (xfer->c_flags & C_DMA) 2280 ata_dmaerr(drvp, 2281 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2282 sc_xfer->error = XS_TIMEOUT; 2283 ata_channel_unlock(chp); 2284 mvsata_atapi_reset(chp, xfer); 2285 return 1; 2286 } 2287 2288 /* 2289 * If we missed an IRQ and were using DMA, flag it as a DMA error 2290 * and reset device. 2291 */ 2292 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2293 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2294 sc_xfer->error = XS_RESET; 2295 ata_channel_unlock(chp); 2296 mvsata_atapi_reset(chp, xfer); 2297 return (1); 2298 } 2299 /* 2300 * if the request sense command was aborted, report the short sense 2301 * previously recorded, else continue normal processing 2302 */ 2303 2304 again: 2305 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2306 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2307 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2308 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2309 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2310 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2311 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2312 2313 switch (phase) { 2314 case PHASE_CMDOUT: 2315 cmd = sc_xfer->cmd; 2316 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2317 /* Init the DMA channel if necessary */ 2318 if (xfer->c_flags & C_DMA) { 2319 error = mvsata_bdma_init(mvport, xfer); 2320 if (error) { 2321 if (error == EINVAL) { 2322 /* 2323 * We can't do DMA on this transfer 2324 * for some reason. Fall back to PIO. 2325 */ 2326 xfer->c_flags &= ~C_DMA; 2327 error = 0; 2328 } else { 2329 sc_xfer->error = XS_DRIVER_STUFFUP; 2330 break; 2331 } 2332 } 2333 } 2334 2335 /* send packet command */ 2336 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2337 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2338 2339 /* Start the DMA channel if necessary */ 2340 if (xfer->c_flags & C_DMA) { 2341 mvsata_bdma_start(mvport); 2342 chp->ch_flags |= ATACH_DMA_WAIT; 2343 } 2344 ata_channel_unlock(chp); 2345 return 1; 2346 2347 case PHASE_DATAOUT: 2348 /* write data */ 2349 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2350 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2351 (xfer->c_flags & C_DMA) != 0) { 2352 aprint_error_dev(atac->atac_dev, 2353 "channel %d drive %d: bad data phase DATAOUT\n", 2354 chp->ch_channel, xfer->c_drive); 2355 if (xfer->c_flags & C_DMA) 2356 ata_dmaerr(drvp, 2357 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2358 sc_xfer->error = XS_TIMEOUT; 2359 ata_channel_unlock(chp); 2360 mvsata_atapi_reset(chp, xfer); 2361 return 1; 2362 } 2363 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2364 if (xfer->c_bcount < len) { 2365 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2366 " warning: write only %d of %d requested bytes\n", 2367 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2368 len); 2369 len = xfer->c_bcount; 2370 } 2371 2372 wdc->dataout_pio(chp, drvp->drive_flags, 2373 (char *)xfer->c_databuf + xfer->c_skip, len); 2374 2375 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 2376 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2377 2378 xfer->c_skip += len; 2379 xfer->c_bcount -= len; 2380 ata_channel_unlock(chp); 2381 return 1; 2382 2383 case PHASE_DATAIN: 2384 /* Read data */ 2385 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2386 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2387 (xfer->c_flags & C_DMA) != 0) { 2388 aprint_error_dev(atac->atac_dev, 2389 "channel %d drive %d: bad data phase DATAIN\n", 2390 chp->ch_channel, xfer->c_drive); 2391 if (xfer->c_flags & C_DMA) 2392 ata_dmaerr(drvp, 2393 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2394 ata_channel_unlock(chp); 2395 sc_xfer->error = XS_TIMEOUT; 2396 mvsata_atapi_reset(chp, xfer); 2397 return 1; 2398 } 2399 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2400 if (xfer->c_bcount < len) { 2401 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2402 " warning: reading only %d of %d bytes\n", 2403 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2404 len); 2405 len = xfer->c_bcount; 2406 } 2407 2408 wdc->datain_pio(chp, drvp->drive_flags, 2409 (char *)xfer->c_databuf + xfer->c_skip, len); 2410 2411 if (xfer->c_atapi.c_lenoff > 0) 2412 wdcbit_bucket(chp, len - xfer->c_bcount); 2413 2414 xfer->c_skip += len; 2415 xfer->c_bcount -= len; 2416 ata_channel_unlock(chp); 2417 return 1; 2418 2419 case PHASE_ABORTED: 2420 case PHASE_COMPLETED: 2421 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2422 if (xfer->c_flags & C_DMA) 2423 xfer->c_bcount -= sc_xfer->datalen; 2424 sc_xfer->resid = xfer->c_bcount; 2425 /* this will unlock channel lock too */ 2426 mvsata_atapi_phase_complete(xfer, tfd); 2427 return 1; 2428 2429 default: 2430 if (++retries<500) { 2431 DELAY(100); 2432 tfd = ATACH_ERR_ST( 2433 MVSATA_WDC_READ_1(mvport, SRB_FE), 2434 MVSATA_WDC_READ_1(mvport, SRB_CS) 2435 ); 2436 goto again; 2437 } 2438 aprint_error_dev(atac->atac_dev, 2439 "channel %d drive %d: unknown phase 0x%x\n", 2440 chp->ch_channel, xfer->c_drive, phase); 2441 if (ATACH_ST(tfd) & WDCS_ERR) { 2442 sc_xfer->error = XS_SHORTSENSE; 2443 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2444 } else { 2445 if (xfer->c_flags & C_DMA) 2446 ata_dmaerr(drvp, 2447 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2448 sc_xfer->error = XS_RESET; 2449 ata_channel_unlock(chp); 2450 mvsata_atapi_reset(chp, xfer); 2451 return (1); 2452 } 2453 } 2454 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2455 ("mvsata_atapi_intr: %s (end), error 0x%x " 2456 "sense 0x%x\n", __func__, 2457 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2458 ata_channel_unlock(chp); 2459 mvsata_atapi_done(chp, xfer); 2460 return 1; 2461 } 2462 2463 static void 2464 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2465 int reason) 2466 { 2467 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2468 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2469 bool deactivate = true; 2470 2471 /* remove this command from xfer queue */ 2472 switch (reason) { 2473 case KILL_GONE_INACTIVE: 2474 deactivate = false; 2475 /* FALLTHROUGH */ 2476 case KILL_GONE: 2477 sc_xfer->error = XS_DRIVER_STUFFUP; 2478 break; 2479 case KILL_RESET: 2480 sc_xfer->error = XS_RESET; 2481 break; 2482 case KILL_REQUEUE: 2483 sc_xfer->error = XS_REQUEUE; 2484 break; 2485 default: 2486 aprint_error_dev(MVSATA_DEV2(mvport), 2487 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2488 panic("mvsata_atapi_kill_xfer"); 2489 } 2490 2491 if (deactivate) 2492 ata_deactivate_xfer(chp, xfer); 2493 2494 ata_free_xfer(chp, xfer); 2495 scsipi_done(sc_xfer); 2496 } 2497 2498 static void 2499 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2500 { 2501 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2502 struct atac_softc *atac = chp->ch_atac; 2503 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2504 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2505 int tfd; 2506 2507 ata_channel_lock(chp); 2508 2509 mvsata_pmp_select(mvport, xfer->c_drive); 2510 2511 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2512 drvp->state = 0; 2513 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2514 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2515 chp->ch_channel, xfer->c_drive); 2516 sc_xfer->error = XS_SELTIMEOUT; 2517 } 2518 2519 ata_channel_unlock(chp); 2520 2521 mvsata_atapi_done(chp, xfer); 2522 return; 2523 } 2524 2525 static void 2526 mvsata_atapi_phase_complete(struct ata_xfer *xfer, int tfd) 2527 { 2528 struct ata_channel *chp = xfer->c_chp; 2529 struct atac_softc *atac = chp->ch_atac; 2530 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2531 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2532 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2533 2534 ata_channel_lock_owned(chp); 2535 2536 /* wait for DSC if needed */ 2537 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2538 DPRINTF(DEBUG_XFERS, 2539 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2540 device_xname(atac->atac_dev), chp->ch_channel, 2541 xfer->c_drive, xfer->c_atapi.c_dscpoll)); 2542 if (cold) 2543 panic("mvsata_atapi_phase_complete: cold"); 2544 2545 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2546 WDCWAIT_TOUT) { 2547 /* 10ms not enough, try again in 1 tick */ 2548 if (xfer->c_atapi.c_dscpoll++ > 2549 mstohz(sc_xfer->timeout)) { 2550 aprint_error_dev(atac->atac_dev, 2551 "channel %d: wait_for_dsc failed\n", 2552 chp->ch_channel); 2553 ata_channel_unlock(chp); 2554 sc_xfer->error = XS_TIMEOUT; 2555 mvsata_atapi_reset(chp, xfer); 2556 } else { 2557 callout_reset(&chp->c_timo_callout, 1, 2558 mvsata_atapi_polldsc, chp); 2559 ata_channel_unlock(chp); 2560 } 2561 return; 2562 } 2563 } 2564 2565 /* 2566 * Some drive occasionally set WDCS_ERR with 2567 * "ATA illegal length indication" in the error 2568 * register. If we read some data the sense is valid 2569 * anyway, so don't report the error. 2570 */ 2571 if (ATACH_ST(tfd) & WDCS_ERR && 2572 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2573 sc_xfer->resid == sc_xfer->datalen)) { 2574 /* save the short sense */ 2575 sc_xfer->error = XS_SHORTSENSE; 2576 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2577 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2578 /* ask scsipi to send a REQUEST_SENSE */ 2579 sc_xfer->error = XS_BUSY; 2580 sc_xfer->status = SCSI_CHECK; 2581 } else 2582 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2583 ata_dmaerr(drvp, 2584 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2585 sc_xfer->error = XS_RESET; 2586 ata_channel_unlock(chp); 2587 mvsata_atapi_reset(chp, xfer); 2588 return; 2589 } 2590 } 2591 if (xfer->c_bcount != 0) { 2592 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2593 " bcount value is %d after io\n", 2594 device_xname(atac->atac_dev), chp->ch_channel, 2595 xfer->c_drive, xfer->c_bcount)); 2596 } 2597 #ifdef DIAGNOSTIC 2598 if (xfer->c_bcount < 0) { 2599 aprint_error_dev(atac->atac_dev, 2600 "channel %d drive %d: mvsata_atapi_intr:" 2601 " warning: bcount value is %d after io\n", 2602 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2603 } 2604 #endif 2605 2606 DPRINTF(DEBUG_XFERS, 2607 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2608 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2609 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2610 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2611 ata_channel_unlock(chp); 2612 mvsata_atapi_done(chp, xfer); 2613 } 2614 2615 static void 2616 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2617 { 2618 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2619 bool iserror = (sc_xfer->error != XS_NOERROR); 2620 2621 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2622 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2623 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2624 xfer->c_drive, (u_int)xfer->c_flags)); 2625 2626 if (ata_waitdrain_xfer_check(chp, xfer)) 2627 return; 2628 2629 /* mark controller inactive and free the command */ 2630 ata_deactivate_xfer(chp, xfer); 2631 2632 ata_free_xfer(chp, xfer); 2633 2634 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2635 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2636 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2637 scsipi_done(sc_xfer); 2638 DPRINTF(DEBUG_FUNCS, 2639 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2640 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2641 chp->ch_flags)); 2642 if (!iserror) 2643 atastart(chp); 2644 } 2645 2646 static void 2647 mvsata_atapi_polldsc(void *arg) 2648 { 2649 struct ata_channel *chp = arg; 2650 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 2651 2652 KASSERT(xfer != NULL); 2653 2654 ata_channel_lock(chp); 2655 2656 /* this will unlock channel lock too */ 2657 mvsata_atapi_phase_complete(xfer, 0); 2658 } 2659 #endif /* NATAPIBUS > 0 */ 2660 2661 2662 /* 2663 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2664 * if supported queuing command by atabus? The race condition will not happen 2665 * if this is called only to the thread of atabus. 2666 */ 2667 static int 2668 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2669 { 2670 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2671 struct ata_bio *ata_bio = &xfer->c_bio; 2672 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2673 struct eprd *eprd; 2674 bus_addr_t crqb_base_addr; 2675 bus_dmamap_t data_dmamap; 2676 uint32_t reg; 2677 int erqqip, erqqop, next, rv, i; 2678 2679 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2680 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2681 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2682 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2683 2684 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2685 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2686 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2687 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2688 next = erqqip; 2689 MVSATA_EDMAQ_INC(next); 2690 if (next == erqqop) { 2691 /* queue full */ 2692 return EBUSY; 2693 } 2694 DPRINTF(DEBUG_XFERS, 2695 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2696 2697 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2698 ata_bio->flags); 2699 if (rv != 0) 2700 return rv; 2701 2702 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2703 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2704 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2705 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2706 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2707 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2708 2709 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2710 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2711 eprd->eot = htole16(0); 2712 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2713 eprd++; 2714 } 2715 (eprd - 1)->eot |= htole16(EPRD_EOT); 2716 #ifdef MVSATA_DEBUG 2717 if (mvsata_debug >= 3) 2718 mvsata_print_eprd(mvport, xfer->c_slot); 2719 #endif 2720 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2721 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2722 BUS_DMASYNC_PREWRITE); 2723 2724 /* setup EDMA Command Request Block (CRQB) Data */ 2725 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2726 #ifdef MVSATA_DEBUG 2727 if (mvsata_debug >= 3) 2728 mvsata_print_crqb(mvport, erqqip); 2729 #endif 2730 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2731 erqqip * sizeof(union mvsata_crqb), 2732 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2733 2734 MVSATA_EDMAQ_INC(erqqip); 2735 2736 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2737 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2738 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2739 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2740 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2741 2742 return 0; 2743 } 2744 2745 static int 2746 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2747 { 2748 struct ata_channel *chp = &mvport->port_ata_channel; 2749 struct crpb *crpb; 2750 struct ata_bio *ata_bio; 2751 struct ata_xfer *xfer; 2752 uint32_t reg; 2753 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2754 int st, dmaerr; 2755 2756 /* First, Sync for Request Queue buffer */ 2757 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2758 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2759 if (mvport->port_prev_erqqop != erqqop) { 2760 const int s = sizeof(union mvsata_crqb); 2761 2762 if (mvport->port_prev_erqqop < erqqop) 2763 n = erqqop - mvport->port_prev_erqqop; 2764 else { 2765 if (erqqop > 0) 2766 bus_dmamap_sync(mvport->port_dmat, 2767 mvport->port_crqb_dmamap, 0, erqqop * s, 2768 BUS_DMASYNC_POSTWRITE); 2769 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2770 } 2771 if (n > 0) 2772 bus_dmamap_sync(mvport->port_dmat, 2773 mvport->port_crqb_dmamap, 2774 mvport->port_prev_erqqop * s, n * s, 2775 BUS_DMASYNC_POSTWRITE); 2776 mvport->port_prev_erqqop = erqqop; 2777 } 2778 2779 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2780 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2781 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2782 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2783 2784 DPRINTF(DEBUG_XFERS, 2785 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2786 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2787 mvport->port, erpqip, erpqop)); 2788 2789 if (erpqop == erpqip) 2790 return 0; 2791 2792 if (erpqop < erpqip) 2793 n = erpqip - erpqop; 2794 else { 2795 if (erpqip > 0) 2796 bus_dmamap_sync(mvport->port_dmat, 2797 mvport->port_crpb_dmamap, 2798 0, erpqip * sizeof(struct crpb), 2799 BUS_DMASYNC_POSTREAD); 2800 n = MVSATA_EDMAQ_LEN - erpqop; 2801 } 2802 if (n > 0) 2803 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2804 erpqop * sizeof(struct crpb), 2805 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2806 2807 uint32_t aslots = ata_queue_active(chp); 2808 2809 prev_erpqop = erpqop; 2810 while (erpqop != erpqip) { 2811 #ifdef MVSATA_DEBUG 2812 if (mvsata_debug >= 3) 2813 mvsata_print_crpb(mvport, erpqop); 2814 #endif 2815 crpb = mvport->port_crpb + erpqop; 2816 MVSATA_EDMAQ_INC(erpqop); 2817 2818 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2819 2820 if ((aslots & __BIT(quetag)) == 0) { 2821 /* not actually executing */ 2822 continue; 2823 } 2824 2825 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2826 2827 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2828 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2829 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2830 2831 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2832 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2833 2834 ata_bio = &xfer->c_bio; 2835 ata_bio->error = NOERROR; 2836 if (dmaerr != 0) 2837 ata_bio->error = ERR_DMA; 2838 2839 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2840 2841 KASSERT(xfer->c_flags & C_DMA); 2842 mvsata_bio_intr(chp, xfer, ATACH_ERR_ST(0, st)); 2843 2844 if (xfer1 == NULL) 2845 handled++; 2846 else if (xfer == xfer1) { 2847 handled = 1; 2848 break; 2849 } 2850 } 2851 if (prev_erpqop < erpqop) 2852 n = erpqop - prev_erpqop; 2853 else { 2854 if (erpqop > 0) 2855 bus_dmamap_sync(mvport->port_dmat, 2856 mvport->port_crpb_dmamap, 0, 2857 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2858 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2859 } 2860 if (n > 0) 2861 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2862 prev_erpqop * sizeof(struct crpb), 2863 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2864 2865 reg &= ~EDMA_RESQP_ERPQP_MASK; 2866 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2867 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2868 2869 return handled; 2870 } 2871 2872 static int 2873 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2874 { 2875 int xtime; 2876 2877 for (xtime = 0; xtime < timeout * 10; xtime++) { 2878 if (mvsata_edma_handle(mvport, xfer)) 2879 return 0; 2880 DELAY(100); 2881 } 2882 2883 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2884 mvsata_edma_rqq_remove(mvport, xfer); 2885 xfer->c_flags |= C_TIMEOU; 2886 return 1; 2887 } 2888 2889 static void 2890 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2891 { 2892 struct ata_channel *chp = &mvport->port_ata_channel; 2893 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2894 bus_addr_t crqb_base_addr; 2895 int erqqip, i; 2896 2897 /* First, hardware reset, stop EDMA */ 2898 mvsata_hreset_port(mvport); 2899 2900 /* cleanup completed EDMA safely */ 2901 mvsata_edma_handle(mvport, NULL); 2902 2903 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2904 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2905 2906 uint32_t aslots = ata_queue_active(chp); 2907 2908 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2909 struct ata_xfer *rqxfer; 2910 2911 if ((aslots & __BIT(i)) == 0) 2912 continue; 2913 2914 if (i == xfer->c_slot) { 2915 /* remove xfer from EDMA request queue */ 2916 bus_dmamap_sync(mvport->port_dmat, 2917 mvport->port_eprd_dmamap, 2918 mvport->port_reqtbl[i].eprd_offset, 2919 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2920 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 2921 /* quetag freed by caller later */ 2922 continue; 2923 } 2924 2925 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 2926 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 2927 erqqip++; 2928 } 2929 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2930 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2931 BUS_DMASYNC_POSTWRITE); 2932 2933 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 2934 mvsata_edma_reset_qptr(mvport); 2935 mvsata_edma_enable(mvport); 2936 2937 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2938 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2939 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2940 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2941 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2942 } 2943 2944 #if NATAPIBUS > 0 2945 static int 2946 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 2947 { 2948 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2949 struct eprd *eprd; 2950 bus_dmamap_t data_dmamap; 2951 bus_addr_t eprd_addr; 2952 int i, rv; 2953 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2954 2955 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2956 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2957 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2958 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2959 2960 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 2961 sc_xfer->datalen, 2962 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2963 if (rv != 0) 2964 return rv; 2965 2966 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2967 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2968 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2969 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2970 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2971 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2972 2973 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2974 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2975 eprd->eot = htole16(0); 2976 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2977 eprd++; 2978 } 2979 (eprd - 1)->eot |= htole16(EPRD_EOT); 2980 #ifdef MVSATA_DEBUG 2981 if (mvsata_debug >= 3) 2982 mvsata_print_eprd(mvport, xfer->c_slot); 2983 #endif 2984 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2985 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2986 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 2987 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2988 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 2989 2990 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2991 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2992 2993 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2994 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2995 else 2996 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2997 2998 return 0; 2999 } 3000 3001 static void 3002 mvsata_bdma_start(struct mvsata_port *mvport) 3003 { 3004 3005 #ifdef MVSATA_DEBUG 3006 if (mvsata_debug >= 3) 3007 mvsata_print_eprd(mvport, 0); 3008 #endif 3009 3010 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 3011 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 3012 } 3013 #endif 3014 #endif 3015 3016 3017 static int 3018 mvsata_port_init(struct mvsata_hc *mvhc, int port) 3019 { 3020 struct mvsata_softc *sc = mvhc->hc_sc; 3021 struct mvsata_port *mvport; 3022 struct ata_channel *chp; 3023 int channel, rv, i; 3024 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 3025 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 3026 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 3027 3028 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 3029 M_ZERO | M_NOWAIT); 3030 if (mvport == NULL) { 3031 aprint_error("%s:%d: can't allocate memory for port %d\n", 3032 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3033 return ENOMEM; 3034 } 3035 3036 mvport->port = port; 3037 mvport->port_hc = mvhc; 3038 mvport->port_edmamode_negotiated = nodma; 3039 3040 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3041 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3042 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3043 if (rv != 0) { 3044 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3045 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3046 goto fail0; 3047 } 3048 mvport->port_iot = mvhc->hc_iot; 3049 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3050 &mvport->port_sata_sstatus); 3051 if (rv != 0) { 3052 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3053 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3054 goto fail0; 3055 } 3056 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3057 &mvport->port_sata_serror); 3058 if (rv != 0) { 3059 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3060 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3061 goto fail0; 3062 } 3063 if (sc->sc_rev == gen1) 3064 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3065 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3066 else 3067 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3068 SATA_SC, 4, &mvport->port_sata_scontrol); 3069 if (rv != 0) { 3070 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3071 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3072 goto fail0; 3073 } 3074 mvport->port_dmat = sc->sc_dmat; 3075 mvhc->hc_ports[port] = mvport; 3076 3077 channel = mvhc->hc * sc->sc_port + port; 3078 chp = &mvport->port_ata_channel; 3079 chp->ch_channel = channel; 3080 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3081 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3082 sc->sc_ata_channels[channel] = chp; 3083 3084 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3085 if (rv != 0) 3086 goto fail0; 3087 3088 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3089 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3090 if (rv != 0) { 3091 aprint_error( 3092 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3093 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3094 goto fail0; 3095 } 3096 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3097 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3098 if (rv != 0) { 3099 aprint_error( 3100 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3101 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3102 goto fail1; 3103 } 3104 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3105 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3106 if (rv != 0) { 3107 aprint_error( 3108 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3109 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3110 goto fail2; 3111 } 3112 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3113 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3114 MVSATA_MAX_SEGS, MAXPHYS, 0, BUS_DMA_NOWAIT, 3115 &mvport->port_reqtbl[i].data_dmamap); 3116 if (rv != 0) { 3117 aprint_error("%s:%d:%d:" 3118 " EDMA data map(%d) create failed: error=%d\n", 3119 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3120 rv); 3121 goto fail3; 3122 } 3123 } 3124 3125 return 0; 3126 3127 fail3: 3128 for (i--; i >= 0; i--) 3129 bus_dmamap_destroy(mvport->port_dmat, 3130 mvport->port_reqtbl[i].data_dmamap); 3131 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3132 fail2: 3133 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3134 fail1: 3135 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3136 fail0: 3137 return rv; 3138 } 3139 3140 static int 3141 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3142 { 3143 int hc, port, rv, i; 3144 3145 hc = mvport->port_hc->hc; 3146 port = mvport->port; 3147 3148 /* Create subregion for Shadow Registers Map */ 3149 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3150 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3151 if (rv != 0) { 3152 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3153 device_xname(MVSATA_DEV2(mvport)), hc, port); 3154 return rv; 3155 } 3156 wdr->cmd_iot = mvport->port_iot; 3157 3158 /* Once create subregion for each command registers */ 3159 for (i = 0; i < WDC_NREG; i++) { 3160 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3161 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3162 if (rv != 0) { 3163 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3164 device_xname(MVSATA_DEV2(mvport)), hc, port); 3165 return rv; 3166 } 3167 } 3168 /* Create subregion for Alternate Status register */ 3169 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3170 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3171 if (rv != 0) { 3172 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3173 device_xname(MVSATA_DEV2(mvport)), hc, port); 3174 return rv; 3175 } 3176 wdr->ctl_iot = mvport->port_iot; 3177 3178 wdc_init_shadow_regs(wdr); 3179 3180 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3181 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3182 if (rv != 0) { 3183 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3184 device_xname(MVSATA_DEV2(mvport)), hc, port); 3185 return rv; 3186 } 3187 wdr->sata_iot = mvport->port_iot; 3188 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3189 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3190 if (rv != 0) { 3191 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3192 device_xname(MVSATA_DEV2(mvport)), hc, port); 3193 return rv; 3194 } 3195 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3196 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3197 if (rv != 0) { 3198 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3199 device_xname(MVSATA_DEV2(mvport)), hc, port); 3200 return rv; 3201 } 3202 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3203 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3204 if (rv != 0) { 3205 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3206 device_xname(MVSATA_DEV2(mvport)), hc, port); 3207 return rv; 3208 } 3209 3210 return 0; 3211 } 3212 3213 3214 #ifndef MVSATA_WITHOUTDMA 3215 static void * 3216 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3217 bus_dmamap_t *dmamap, size_t size, int write) 3218 { 3219 bus_dma_segment_t seg; 3220 int nseg, rv; 3221 void *kva; 3222 3223 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3224 BUS_DMA_NOWAIT); 3225 if (rv != 0) { 3226 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3227 device_xname(MVSATA_DEV2(mvport)), 3228 mvport->port_hc->hc, mvport->port, rv); 3229 goto fail; 3230 } 3231 3232 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3233 if (rv != 0) { 3234 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3235 device_xname(MVSATA_DEV2(mvport)), 3236 mvport->port_hc->hc, mvport->port, rv); 3237 goto free; 3238 } 3239 3240 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3241 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3242 if (rv != 0) { 3243 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3244 device_xname(MVSATA_DEV2(mvport)), 3245 mvport->port_hc->hc, mvport->port, rv); 3246 goto unmap; 3247 } 3248 3249 if (!write) 3250 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3251 3252 return kva; 3253 3254 unmap: 3255 bus_dmamem_unmap(dmat, kva, size); 3256 free: 3257 bus_dmamem_free(dmat, &seg, nseg); 3258 fail: 3259 return NULL; 3260 } 3261 3262 /* ARGSUSED */ 3263 static void 3264 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3265 bus_dmamap_t dmamap, void *kva) 3266 { 3267 3268 bus_dmamap_unload(dmat, dmamap); 3269 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3270 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3271 } 3272 3273 static int 3274 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3275 size_t datalen, int flags) 3276 { 3277 int rv, lop, sop; 3278 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3279 3280 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3281 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3282 3283 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3284 NULL, BUS_DMA_NOWAIT | lop); 3285 if (rv) { 3286 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3287 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3288 mvport->port, rv); 3289 return rv; 3290 } 3291 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3292 data_dmamap->dm_mapsize, sop); 3293 3294 return 0; 3295 } 3296 3297 static inline void 3298 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3299 { 3300 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3301 3302 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3303 data_dmamap->dm_mapsize, 3304 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3305 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3306 } 3307 #endif 3308 3309 static void 3310 mvsata_hreset_port(struct mvsata_port *mvport) 3311 { 3312 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3313 3314 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3315 3316 delay(25); /* allow reset propagation */ 3317 3318 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3319 3320 mvport->_fix_phy_param._fix_phy(mvport); 3321 3322 if (sc->sc_gen == gen1) 3323 delay(1000); 3324 } 3325 3326 static void 3327 mvsata_reset_port(struct mvsata_port *mvport) 3328 { 3329 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3330 3331 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3332 3333 mvsata_hreset_port(mvport); 3334 3335 if (device_is_a(parent, "pci")) 3336 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3337 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3338 else /* SoC */ 3339 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3340 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3341 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3342 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3343 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3344 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3345 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3346 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3347 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3348 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3349 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3350 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3351 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3352 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3353 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3354 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3355 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3356 } 3357 3358 static void 3359 mvsata_reset_hc(struct mvsata_hc *mvhc) 3360 { 3361 #if 0 3362 uint32_t val; 3363 #endif 3364 3365 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3366 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3367 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3368 3369 #if 0 /* XXXX needs? */ 3370 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3371 3372 /* 3373 * Keep the SS during power on and the reference clock bits (reset 3374 * sample) 3375 */ 3376 val = MVSATA_HC_READ_4(mvhc, 0x020); 3377 val &= 0x1c1c1c1c; 3378 val |= 0x03030303; 3379 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3380 #endif 3381 } 3382 3383 static uint32_t 3384 mvsata_softreset(struct mvsata_port *mvport, int flags) 3385 { 3386 struct ata_channel *chp = &mvport->port_ata_channel; 3387 uint32_t sig0 = ~0; 3388 int timeout; 3389 uint8_t st0; 3390 3391 ata_channel_lock_owned(chp); 3392 3393 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3394 delay(10); 3395 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3396 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3397 delay(10); 3398 3399 /* wait for BSY to deassert */ 3400 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3401 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3402 3403 if ((st0 & WDCS_BSY) == 0) { 3404 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3405 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3406 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3407 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3408 goto out; 3409 } 3410 ata_delay(chp, 10, "atarst", flags); 3411 } 3412 3413 aprint_error("%s:%d:%d: %s: timeout\n", 3414 device_xname(MVSATA_DEV2(mvport)), 3415 mvport->port_hc->hc, mvport->port, __func__); 3416 3417 out: 3418 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3419 return sig0; 3420 } 3421 3422 #ifndef MVSATA_WITHOUTDMA 3423 static void 3424 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3425 { 3426 const bus_addr_t crpb_addr = 3427 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3428 const uint32_t crpb_addr_mask = 3429 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3430 3431 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3432 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3433 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3434 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3435 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3436 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3437 } 3438 3439 static inline void 3440 mvsata_edma_enable(struct mvsata_port *mvport) 3441 { 3442 3443 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3444 } 3445 3446 static int 3447 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3448 { 3449 struct ata_channel *chp = &mvport->port_ata_channel; 3450 uint32_t status, command; 3451 uint32_t idlestatus = EDMA_S_EDMAIDLE | EDMA_S_ECACHEEMPTY; 3452 int t; 3453 3454 ata_channel_lock_owned(chp); 3455 3456 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3457 3458 timeout = mstohz(timeout + hztoms(1) - 1); 3459 3460 for (t = 0; ; ++t) { 3461 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3462 if ((status & idlestatus) == idlestatus) 3463 break; 3464 if (t >= timeout) 3465 break; 3466 ata_delay(chp, hztoms(1), "mvsata_edma1", wflags); 3467 } 3468 if (t >= timeout) { 3469 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3470 device_xname(MVSATA_DEV2(mvport)), 3471 mvport->port_hc->hc, mvport->port); 3472 return EBUSY; 3473 } 3474 3475 /* The disable bit (eDsEDMA) is self negated. */ 3476 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3477 3478 for (t = 0; ; ++t) { 3479 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3480 if (!(command & EDMA_CMD_EENEDMA)) 3481 break; 3482 if (t >= timeout) 3483 break; 3484 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3485 } 3486 if (t >= timeout) { 3487 aprint_error("%s:%d:%d: unable to re-enable EDMA\n", 3488 device_xname(MVSATA_DEV2(mvport)), 3489 mvport->port_hc->hc, mvport->port); 3490 return EBUSY; 3491 } 3492 } 3493 return 0; 3494 } 3495 3496 /* 3497 * Set EDMA registers according to mode. 3498 * ex. NCQ/TCQ(queued)/non queued. 3499 */ 3500 static void 3501 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3502 { 3503 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3504 uint32_t reg; 3505 3506 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3507 reg |= EDMA_CFG_RESERVED; 3508 3509 if (mode == ncq) { 3510 if (sc->sc_gen == gen1) { 3511 aprint_error_dev(MVSATA_DEV2(mvport), 3512 "GenI not support NCQ\n"); 3513 return; 3514 } else if (sc->sc_gen == gen2) 3515 reg |= EDMA_CFG_EDEVERR; 3516 reg |= EDMA_CFG_ESATANATVCMDQUE; 3517 } else if (mode == queued) { 3518 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3519 reg |= EDMA_CFG_EQUE; 3520 } else 3521 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3522 3523 if (sc->sc_gen == gen1) 3524 reg |= EDMA_CFG_ERDBSZ; 3525 else if (sc->sc_gen == gen2) 3526 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3527 else if (sc->sc_gen == gen2e) { 3528 device_t parent = device_parent(MVSATA_DEV(sc)); 3529 3530 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3531 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3532 3533 if (device_is_a(parent, "pci")) 3534 reg |= ( 3535 #if NATAPIBUS > 0 3536 EDMA_CFG_EEARLYCOMPLETIONEN | 3537 #endif 3538 EDMA_CFG_ECUTTHROUGHEN | 3539 EDMA_CFG_EWRBUFFERLEN | 3540 EDMA_CFG_ERDBSZEXT); 3541 } 3542 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3543 3544 reg = ( 3545 EDMA_IE_EIORDYERR | 3546 EDMA_IE_ETRANSINT | 3547 EDMA_IE_EDEVCON | 3548 EDMA_IE_EDEVDIS); 3549 if (sc->sc_gen != gen1) 3550 reg |= ( 3551 EDMA_IE_TRANSPROTERR | 3552 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3553 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3554 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3555 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3556 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3557 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3558 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3559 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3560 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3561 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3562 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3563 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3564 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3565 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3566 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3567 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3568 EDMA_IE_ESELFDIS); 3569 3570 if (mode == ncq) 3571 reg |= EDMA_IE_EDEVERR; 3572 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3573 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3574 reg &= ~EDMA_IE_EDEVERR; 3575 if (mode != ncq) 3576 reg |= EDMA_IE_EDEVERR; 3577 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3578 if (sc->sc_gen == gen2e) { 3579 /* 3580 * Clear FISWait4HostRdyEn[0] and [2]. 3581 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3582 * [2]: SDB FIS is received with <ERR> bit set to 1. 3583 */ 3584 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3585 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3586 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3587 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3588 } 3589 3590 mvport->port_edmamode_curr = mode; 3591 } 3592 3593 3594 /* 3595 * Generation dependent functions 3596 */ 3597 3598 static void 3599 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3600 struct ata_xfer *xfer) 3601 { 3602 struct crqb *crqb; 3603 bus_addr_t eprd_addr; 3604 daddr_t blkno; 3605 uint32_t rw; 3606 uint8_t cmd, head; 3607 int i; 3608 struct ata_bio *ata_bio = &xfer->c_bio; 3609 3610 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3611 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3612 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3613 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3614 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3615 head = WDSD_LBA; 3616 } else { 3617 head = 0; 3618 } 3619 blkno = ata_bio->blkno; 3620 if (ata_bio->flags & ATA_LBA48) 3621 cmd = atacmd_to48(cmd); 3622 else { 3623 head |= ((ata_bio->blkno >> 24) & 0xf); 3624 blkno &= 0xffffff; 3625 } 3626 crqb = &mvport->port_crqb->crqb + erqqip; 3627 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3628 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3629 crqb->ctrlflg = 3630 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3631 CRQB_CPMPORT(xfer->c_drive)); 3632 i = 0; 3633 if (mvport->port_edmamode_curr == dma) { 3634 if (ata_bio->flags & ATA_LBA48) 3635 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3636 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3637 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3638 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3639 } else { /* ncq/queued */ 3640 3641 /* 3642 * XXXX: Oops, ata command is not correct. And, atabus layer 3643 * has not been supported yet now. 3644 * Queued DMA read/write. 3645 * read/write FPDMAQueued. 3646 */ 3647 3648 if (ata_bio->flags & ATA_LBA48) 3649 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3650 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3651 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3652 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3653 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3654 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3655 } 3656 if (ata_bio->flags & ATA_LBA48) { 3657 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3658 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3659 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3660 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3661 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3662 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3663 } 3664 crqb->atacommand[i++] = 3665 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3666 crqb->atacommand[i++] = 3667 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3668 crqb->atacommand[i++] = 3669 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3670 crqb->atacommand[i++] = 3671 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3672 crqb->atacommand[i++] = htole16( 3673 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3674 CRQB_ATACOMMAND_LAST); 3675 } 3676 #endif 3677 3678 static uint32_t 3679 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3680 { 3681 struct mvsata_hc *hc = mvport->port_hc; 3682 uint32_t reg; 3683 3684 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3685 /* 3686 * [12:11] : pre 3687 * [7:5] : amps 3688 */ 3689 return reg & 0x000018e0; 3690 } 3691 3692 static void 3693 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3694 { 3695 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3696 struct mvsata_hc *mvhc = mvport->port_hc; 3697 uint32_t reg; 3698 int port = mvport->port, fix_apm_sq = 0; 3699 3700 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3701 if (sc->sc_rev == 0x01) 3702 fix_apm_sq = 1; 3703 } else { 3704 if (sc->sc_rev == 0x00) 3705 fix_apm_sq = 1; 3706 } 3707 3708 if (fix_apm_sq) { 3709 /* 3710 * Disable auto-power management 3711 * 88SX50xx FEr SATA#12 3712 */ 3713 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3714 reg |= (1 << 19); 3715 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3716 3717 /* 3718 * Fix squelch threshold 3719 * 88SX50xx FEr SATA#9 3720 */ 3721 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3722 reg &= ~0x3; 3723 reg |= 0x1; 3724 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3725 } 3726 3727 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3728 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3729 reg &= ~0x000018e0; /* pre and amps mask */ 3730 reg |= mvport->_fix_phy_param.pre_amps; 3731 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3732 } 3733 3734 static void 3735 mvsata_devconn_gen1(struct mvsata_port *mvport) 3736 { 3737 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3738 3739 /* Fix for 88SX50xx FEr SATA#2 */ 3740 mvport->_fix_phy_param._fix_phy(mvport); 3741 3742 /* If disk is connected, then enable the activity LED */ 3743 if (sc->sc_rev == 0x03) { 3744 /* XXXXX */ 3745 } 3746 } 3747 3748 static uint32_t 3749 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3750 { 3751 uint32_t reg; 3752 3753 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3754 /* 3755 * [10:8] : amps 3756 * [7:5] : pre 3757 */ 3758 return reg & 0x000007e0; 3759 } 3760 3761 static void 3762 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3763 { 3764 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3765 uint32_t reg; 3766 3767 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3768 sc->sc_gen == gen2e) { 3769 /* 3770 * Fix for 3771 * 88SX60X1 FEr SATA #23 3772 * 88SX6042/88SX7042 FEr SATA #23 3773 * 88F5182 FEr #SATA-S13 3774 * 88F5082 FEr #SATA-S13 3775 */ 3776 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3777 reg &= ~(1 << 16); 3778 reg |= (1 << 31); 3779 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3780 3781 delay(200); 3782 3783 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3784 reg &= ~((1 << 16) | (1 << 31)); 3785 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3786 3787 delay(200); 3788 } 3789 3790 /* Fix values in PHY Mode 3 Register.*/ 3791 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3792 reg &= ~0x7F900000; 3793 reg |= 0x2A800000; 3794 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3795 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3796 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3797 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3798 reg &= ~0x0000001c; 3799 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3800 3801 /* 3802 * Fix values in PHY Mode 4 Register. 3803 * 88SX60x1 FEr SATA#10 3804 * 88F5182 GL #SATA-S10 3805 * 88F5082 GL #SATA-S10 3806 */ 3807 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3808 sc->sc_gen == gen2e) { 3809 uint32_t tmp = 0; 3810 3811 /* 88SX60x1 FEr SATA #13 */ 3812 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3813 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3814 3815 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3816 reg |= (1 << 0); 3817 reg &= ~(1 << 1); 3818 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3819 if (sc->sc_gen == gen2e) { 3820 reg &= ~0x5de3fffc; 3821 reg |= (1 << 2); 3822 } 3823 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3824 3825 /* 88SX60x1 FEr SATA #13 */ 3826 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3827 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3828 } 3829 3830 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3831 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3832 reg &= ~0x000007e0; /* pre and amps mask */ 3833 reg |= mvport->_fix_phy_param.pre_amps; 3834 reg &= ~(1 << 16); 3835 if (sc->sc_gen == gen2e) { 3836 /* 3837 * according to mvSata 3.6.1, some IIE values are fixed. 3838 * some reserved fields must be written with fixed values. 3839 */ 3840 reg &= ~0xC30FF01F; 3841 reg |= 0x0000900F; 3842 } 3843 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3844 } 3845 3846 #ifndef MVSATA_WITHOUTDMA 3847 static void 3848 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3849 struct ata_xfer *xfer) 3850 { 3851 struct crqb_gen2e *crqb; 3852 bus_addr_t eprd_addr; 3853 uint32_t ctrlflg, rw; 3854 uint8_t fis[RHD_FISLEN]; 3855 3856 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3857 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3858 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3859 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3860 CRQB_CPMPORT(xfer->c_drive) | 3861 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3862 3863 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3864 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3865 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3866 crqb->ctrlflg = htole32(ctrlflg); 3867 3868 satafis_rhd_construct_bio(xfer, fis); 3869 3870 crqb->atacommand[0] = 0; 3871 crqb->atacommand[1] = 0; 3872 /* copy over the ATA command part of the fis */ 3873 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3874 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3875 } 3876 3877 #ifdef MVSATA_DEBUG 3878 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3879 do { \ 3880 int _i; \ 3881 u_char *_p = (p); \ 3882 \ 3883 printf(#type "(%d)", (n)); \ 3884 for (_i = 0; _i < (size); _i++, _p++) { \ 3885 if (_i % 16 == 0) \ 3886 printf("\n "); \ 3887 printf(" %02x", *_p); \ 3888 } \ 3889 printf("\n"); \ 3890 } while (0 /* CONSTCOND */) 3891 3892 static void 3893 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3894 { 3895 3896 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3897 n, (u_char *)(mvport->port_crqb + n)); 3898 } 3899 3900 static void 3901 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3902 { 3903 3904 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3905 n, (u_char *)(mvport->port_crpb + n)); 3906 } 3907 3908 static void 3909 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3910 { 3911 struct eprd *eprd; 3912 int i = 0; 3913 3914 eprd = mvport->port_reqtbl[n].eprd; 3915 while (1 /*CONSTCOND*/) { 3916 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3917 i, (u_char *)eprd); 3918 if (eprd->eot & EPRD_EOT) 3919 break; 3920 eprd++; 3921 i++; 3922 } 3923 } 3924 #endif 3925 #endif 3926
Indexes created Thu Sep 25 06:09:39 GMT 2025