mvsata.c revision 1.49
1 /* $NetBSD: mvsata.c,v 1.49 2019/11/10 21:16:35 chs Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.49 2019/11/10 21:16:35 chs Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 /* 62 * Nice things to do: 63 * 64 * - MSI/MSI-X support - though on some models MSI actually doesn't work 65 * even when hardware claims to support it, according to FreeBSD/OpenBSD 66 * - move pci-specific code to the pci attach code 67 * - mvsata(4) use 64-bit DMA on hardware which claims to support it 68 * - e.g. AHA1430SA does not really work, crash in mvsata_intr() on boot 69 */ 70 71 #include <dev/ic/mvsatareg.h> 72 #include <dev/ic/mvsatavar.h> 73 74 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 75 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 76 77 #define MVSATA_HC_READ_4(hc, reg) \ 78 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 79 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 80 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 81 #define MVSATA_EDMA_READ_4(mvport, reg) \ 82 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 83 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 84 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 85 #define MVSATA_WDC_READ_2(mvport, reg) \ 86 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 87 SHADOW_REG_BLOCK_OFFSET + (reg)) 88 #define MVSATA_WDC_READ_1(mvport, reg) \ 89 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 90 SHADOW_REG_BLOCK_OFFSET + (reg)) 91 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 92 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 93 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 94 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 95 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 96 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 97 98 #ifdef MVSATA_DEBUG 99 100 #define DEBUG_INTR 0x01 101 #define DEBUG_XFERS 0x02 102 #define DEBUG_FUNCS 0x08 103 #define DEBUG_PROBE 0x10 104 105 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 106 int mvsata_debug = 0; 107 #else 108 #define DPRINTF(n,x) 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 113 sending a cmd */ 114 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 115 116 #define MVSATA_MAX_SEGS (MAXPHYS / PAGE_SIZE + 1) 117 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * MVSATA_MAX_SEGS) 118 119 120 static void mvsata_probe_drive(struct ata_channel *); 121 122 #ifndef MVSATA_WITHOUTDMA 123 static void mvsata_reset_channel(struct ata_channel *, int); 124 static int mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 125 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 126 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 127 static int mvsata_addref(struct ata_drive_datas *); 128 static void mvsata_delref(struct ata_drive_datas *); 129 static void mvsata_killpending(struct ata_drive_datas *); 130 131 #if NATAPIBUS > 0 132 static void mvsata_atapibus_attach(struct atabus_softc *); 133 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 134 scsipi_adapter_req_t, void *); 135 static void mvsata_atapi_minphys(struct buf *); 136 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 137 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 138 #endif 139 #endif 140 141 static void mvsata_setup_channel(struct ata_channel *); 142 143 #ifndef MVSATA_WITHOUTDMA 144 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 145 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 146 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 147 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 148 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 149 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 150 int); 151 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 152 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 153 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 154 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 155 int); 156 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 157 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 158 #if NATAPIBUS > 0 159 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 160 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 161 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 162 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 163 int); 164 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 165 static void mvsata_atapi_phase_complete(struct ata_xfer *, int); 166 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 167 static void mvsata_atapi_polldsc(void *); 168 #endif 169 170 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 171 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 172 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 173 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 174 #if NATAPIBUS > 0 175 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 176 static void mvsata_bdma_start(struct mvsata_port *); 177 #endif 178 #endif 179 180 static int mvsata_nondma_handle(struct mvsata_port *); 181 182 static int mvsata_port_init(struct mvsata_hc *, int); 183 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 184 #ifndef MVSATA_WITHOUTDMA 185 static void mvsata_channel_recover(struct ata_channel *, int, uint32_t); 186 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 187 bus_dmamap_t *, size_t, int); 188 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 189 bus_dmamap_t, void *); 190 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 191 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 192 #endif 193 194 static void mvsata_hreset_port(struct mvsata_port *); 195 static void mvsata_reset_port(struct mvsata_port *); 196 static void mvsata_reset_hc(struct mvsata_hc *); 197 static uint32_t mvsata_softreset(struct mvsata_port *, int); 198 #ifndef MVSATA_WITHOUTDMA 199 static void mvsata_edma_reset_qptr(struct mvsata_port *); 200 static inline void mvsata_edma_enable(struct mvsata_port *); 201 static int mvsata_edma_disable(struct mvsata_port *, int, int); 202 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 203 204 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 205 struct ata_xfer *); 206 #endif 207 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 208 static void mvsata_fix_phy_gen1(struct mvsata_port *); 209 static void mvsata_devconn_gen1(struct mvsata_port *); 210 211 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 212 static void mvsata_fix_phy_gen2(struct mvsata_port *); 213 #ifndef MVSATA_WITHOUTDMA 214 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 215 struct ata_xfer *); 216 217 #ifdef MVSATA_DEBUG 218 static void mvsata_print_crqb(struct mvsata_port *, int); 219 static void mvsata_print_crpb(struct mvsata_port *, int); 220 static void mvsata_print_eprd(struct mvsata_port *, int); 221 #endif 222 223 static const struct ata_bustype mvsata_ata_bustype = { 224 SCSIPI_BUSTYPE_ATA, 225 mvsata_bio, 226 mvsata_reset_drive, 227 mvsata_reset_channel, 228 mvsata_exec_command, 229 ata_get_params, 230 mvsata_addref, 231 mvsata_delref, 232 mvsata_killpending, 233 mvsata_channel_recover, 234 }; 235 236 #if NATAPIBUS > 0 237 static const struct scsipi_bustype mvsata_atapi_bustype = { 238 SCSIPI_BUSTYPE_ATAPI, 239 atapi_scsipi_cmd, 240 atapi_interpret_sense, 241 atapi_print_addr, 242 mvsata_atapi_kill_pending, 243 NULL, 244 }; 245 #endif /* NATAPIBUS */ 246 #endif 247 248 static void 249 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 250 { 251 uint32_t ifctl; 252 253 KASSERT(pmpport < PMP_MAX_DRIVES); 254 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 255 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 256 panic("EDMA enabled"); 257 } 258 #endif 259 260 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 261 ifctl &= ~0xf; 262 ifctl |= pmpport; 263 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 264 } 265 266 int 267 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 268 int (*mvsata_sreset)(struct mvsata_softc *), 269 int (*mvsata_misc_reset)(struct mvsata_softc *), 270 int read_pre_amps) 271 { 272 struct mvsata_hc *mvhc; 273 struct mvsata_port *mvport; 274 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 275 void (*_fix_phy)(struct mvsata_port *) = NULL; 276 #ifndef MVSATA_WITHOUTDMA 277 void (*edma_setup_crqb) 278 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 279 #endif 280 int hc, port, channel; 281 282 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 283 (product->generation == gen1) ? "I" : 284 ((product->generation == gen2) ? "II" : "IIe"), 285 product->hc, product->port); 286 287 288 switch (product->generation) { 289 case gen1: 290 mvsata_sreset = NULL; 291 read_pre_amps = 1; /* MUST */ 292 read_preamps = mvsata_read_preamps_gen1; 293 _fix_phy = mvsata_fix_phy_gen1; 294 #ifndef MVSATA_WITHOUTDMA 295 edma_setup_crqb = mvsata_edma_setup_crqb; 296 #endif 297 break; 298 299 case gen2: 300 read_preamps = mvsata_read_preamps_gen2; 301 _fix_phy = mvsata_fix_phy_gen2; 302 #ifndef MVSATA_WITHOUTDMA 303 edma_setup_crqb = mvsata_edma_setup_crqb; 304 #endif 305 break; 306 307 case gen2e: 308 read_preamps = mvsata_read_preamps_gen2; 309 _fix_phy = mvsata_fix_phy_gen2; 310 #ifndef MVSATA_WITHOUTDMA 311 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 312 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 313 #endif 314 break; 315 } 316 317 sc->sc_gen = product->generation; 318 sc->sc_hc = product->hc; 319 sc->sc_port = product->port; 320 sc->sc_flags = product->flags; 321 322 #ifdef MVSATA_WITHOUTDMA 323 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 324 #else 325 sc->sc_edma_setup_crqb = edma_setup_crqb; 326 sc->sc_wdcdev.sc_atac.atac_cap |= 327 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 328 #endif 329 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 330 #ifdef MVSATA_WITHOUTDMA 331 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 333 #else 334 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 335 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 336 #endif 337 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 338 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 339 #ifndef MVSATA_WITHOUTDMA 340 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 341 #if NATAPIBUS > 0 342 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 343 #endif 344 #endif 345 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 346 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 347 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 348 349 sc->sc_wdc_regs = 350 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 351 M_DEVBUF, M_WAITOK); 352 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 353 354 for (hc = 0; hc < sc->sc_hc; hc++) { 355 mvhc = &sc->sc_hcs[hc]; 356 mvhc->hc = hc; 357 mvhc->hc_sc = sc; 358 mvhc->hc_iot = sc->sc_iot; 359 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 360 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 361 &mvhc->hc_ioh)) { 362 aprint_error_dev(MVSATA_DEV(sc), 363 "can't subregion SATAHC %d registers\n", hc); 364 continue; 365 } 366 367 for (port = 0; port < sc->sc_port; port++) 368 if (mvsata_port_init(mvhc, port) == 0) { 369 int pre_amps; 370 371 mvport = mvhc->hc_ports[port]; 372 pre_amps = read_pre_amps ? 373 read_preamps(mvport) : 0x00000720; 374 mvport->_fix_phy_param.pre_amps = pre_amps; 375 mvport->_fix_phy_param._fix_phy = _fix_phy; 376 377 if (!mvsata_sreset) 378 mvsata_reset_port(mvport); 379 } 380 381 if (!mvsata_sreset) 382 mvsata_reset_hc(mvhc); 383 } 384 if (mvsata_sreset) 385 mvsata_sreset(sc); 386 387 if (mvsata_misc_reset) 388 mvsata_misc_reset(sc); 389 390 for (hc = 0; hc < sc->sc_hc; hc++) 391 for (port = 0; port < sc->sc_port; port++) { 392 mvport = sc->sc_hcs[hc].hc_ports[port]; 393 if (mvport == NULL) 394 continue; 395 if (mvsata_sreset) 396 mvport->_fix_phy_param._fix_phy(mvport); 397 } 398 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 399 wdcattach(sc->sc_ata_channels[channel]); 400 401 return 0; 402 } 403 404 int 405 mvsata_intr(struct mvsata_hc *mvhc) 406 { 407 struct mvsata_softc *sc = mvhc->hc_sc; 408 struct mvsata_port *mvport; 409 uint32_t cause; 410 int port, handled = 0; 411 412 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 413 414 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 415 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 416 417 if (cause & SATAHC_IC_SAINTCOAL) 418 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 419 cause &= ~SATAHC_IC_SAINTCOAL; 420 421 for (port = 0; port < sc->sc_port; port++) { 422 mvport = mvhc->hc_ports[port]; 423 424 if (cause & SATAHC_IC_DONE(port)) { 425 #ifndef MVSATA_WITHOUTDMA 426 handled = mvsata_edma_handle(mvport, NULL); 427 #endif 428 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 429 ~SATAHC_IC_DONE(port)); 430 } 431 432 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 433 (void) mvsata_nondma_handle(mvport); 434 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 435 ~SATAHC_IC_SADEVINTERRUPT(port)); 436 handled = 1; 437 } 438 } 439 440 return handled; 441 } 442 443 static int 444 mvsata_nondma_handle(struct mvsata_port *mvport) 445 { 446 struct ata_channel *chp = &mvport->port_ata_channel; 447 struct ata_xfer *xfer; 448 int ret; 449 450 /* 451 * The chip doesn't support several pending non-DMA commands, 452 * and the ata middle layer never issues several non-NCQ commands, 453 * so there must be exactly one active command at this moment. 454 */ 455 xfer = ata_queue_get_active_xfer(chp); 456 if (xfer == NULL) { 457 /* Can happen after error recovery, ignore */ 458 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 459 ("%s:%d: %s: intr without xfer\n", 460 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 461 __func__)); 462 return 0; 463 } 464 465 ret = xfer->ops->c_intr(chp, xfer, 1); 466 return (ret); 467 } 468 469 int 470 mvsata_error(struct mvsata_port *mvport) 471 { 472 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 473 uint32_t cause; 474 475 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 476 /* 477 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 478 * in EDMA_IEC. 479 */ 480 if (cause & EDMA_IE_SERRINT) { 481 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 482 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 483 } 484 if (cause & EDMA_IE_ETRANSINT) { 485 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 486 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 487 } 488 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 489 490 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 491 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 492 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 493 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 494 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 495 496 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 497 if (!cause) 498 return 0; 499 500 if (cause & EDMA_IE_EDEVDIS) { 501 aprint_normal("%s:%d:%d: device disconnect\n", 502 device_xname(MVSATA_DEV2(mvport)), 503 mvport->port_hc->hc, mvport->port); 504 } 505 if (cause & EDMA_IE_EDEVCON) { 506 if (sc->sc_gen == gen1) 507 mvsata_devconn_gen1(mvport); 508 509 DPRINTF(DEBUG_INTR, (" device connected\n")); 510 } 511 512 #ifndef MVSATA_WITHOUTDMA 513 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 514 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 515 switch (mvport->port_edmamode_curr) { 516 case dma: 517 case queued: 518 case ncq: 519 mvsata_edma_reset_qptr(mvport); 520 mvsata_edma_enable(mvport); 521 if (cause & EDMA_IE_EDEVERR) 522 break; 523 524 /* FALLTHROUGH */ 525 526 case nodma: 527 default: 528 aprint_error( 529 "%s:%d:%d: EDMA self disable happen 0x%x\n", 530 device_xname(MVSATA_DEV2(mvport)), 531 mvport->port_hc->hc, mvport->port, cause); 532 break; 533 } 534 } 535 #endif 536 if (cause & EDMA_IE_ETRANSINT) { 537 /* hot plug the Port Multiplier */ 538 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 539 device_xname(MVSATA_DEV2(mvport)), 540 mvport->port_hc->hc, mvport->port); 541 } 542 if (cause & EDMA_IE_EDEVERR) { 543 struct ata_channel *chp = &mvport->port_ata_channel; 544 545 aprint_error("%s:%d:%d: device error, recovering\n", 546 device_xname(MVSATA_DEV2(mvport)), 547 mvport->port_hc->hc, mvport->port); 548 549 ata_channel_lock(chp); 550 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, 551 ATACH_ERR_ST(0, WDCS_ERR)); 552 ata_channel_unlock(chp); 553 } 554 555 return 1; 556 } 557 558 #ifndef MVSATA_WITHOUTDMA 559 static void 560 mvsata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 561 { 562 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 563 int drive; 564 565 ata_channel_lock_owned(chp); 566 567 if (chp->ch_ndrives > PMP_PORT_CTL) { 568 /* Get PM port number for the device in error. This device 569 * doesn't seem to have dedicated register for this, so just 570 * assume last selected port was the one. */ 571 /* XXX FIS-based switching */ 572 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 573 } else 574 drive = 0; 575 576 /* 577 * Controller doesn't need any special action. Simply execute 578 * READ LOG EXT for NCQ to unblock device processing, then continue 579 * as if nothing happened. 580 */ 581 582 ata_recovery_resume(chp, drive, tfd, AT_POLL); 583 584 /* Drive unblocked, back to normal operation */ 585 return; 586 } 587 #endif /* !MVSATA_WITHOUTDMA */ 588 589 /* 590 * ATA callback entry points 591 */ 592 593 static void 594 mvsata_probe_drive(struct ata_channel *chp) 595 { 596 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 597 uint32_t sstat, sig; 598 599 ata_channel_lock(chp); 600 601 sstat = sata_reset_interface(chp, mvport->port_iot, 602 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 603 switch (sstat) { 604 case SStatus_DET_DEV: 605 mvsata_pmp_select(mvport, PMP_PORT_CTL); 606 sig = mvsata_softreset(mvport, AT_WAIT); 607 sata_interpret_sig(chp, 0, sig); 608 break; 609 default: 610 break; 611 } 612 613 ata_channel_unlock(chp); 614 } 615 616 #ifndef MVSATA_WITHOUTDMA 617 static void 618 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 619 { 620 struct ata_channel *chp = drvp->chnl_softc; 621 struct mvsata_port *mvport = (struct mvsata_port *)chp; 622 uint32_t edma_c; 623 uint32_t sig; 624 625 ata_channel_lock_owned(chp); 626 627 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 628 629 DPRINTF(DEBUG_FUNCS, 630 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 631 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 632 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 633 634 if (edma_c & EDMA_CMD_EENEDMA) 635 mvsata_edma_disable(mvport, 10000, flags); 636 637 mvsata_pmp_select(mvport, drvp->drive); 638 639 sig = mvsata_softreset(mvport, flags); 640 641 if (sigp) 642 *sigp = sig; 643 644 if (edma_c & EDMA_CMD_EENEDMA) { 645 mvsata_edma_reset_qptr(mvport); 646 mvsata_edma_enable(mvport); 647 } 648 } 649 650 static void 651 mvsata_reset_channel(struct ata_channel *chp, int flags) 652 { 653 struct mvsata_port *mvport = (struct mvsata_port *)chp; 654 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 655 uint32_t sstat, ctrl; 656 657 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 658 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 659 660 ata_channel_lock_owned(chp); 661 662 mvsata_hreset_port(mvport); 663 sstat = sata_reset_interface(chp, mvport->port_iot, 664 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 665 666 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 667 sc->sc_gen != gen1) { 668 /* Downgrade to GenI */ 669 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 670 SControl_DET_DISABLE; 671 672 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 673 674 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 675 ctrl &= ~(1 << 17); /* Disable GenII */ 676 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 677 678 mvsata_hreset_port(mvport); 679 sata_reset_interface(chp, mvport->port_iot, 680 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 681 flags); 682 } 683 684 ata_kill_active(chp, KILL_RESET, flags); 685 686 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 687 mvsata_edma_reset_qptr(mvport); 688 mvsata_edma_enable(mvport); 689 } 690 691 static int 692 mvsata_addref(struct ata_drive_datas *drvp) 693 { 694 695 return 0; 696 } 697 698 static void 699 mvsata_delref(struct ata_drive_datas *drvp) 700 { 701 702 return; 703 } 704 705 static void 706 mvsata_killpending(struct ata_drive_datas *drvp) 707 { 708 709 return; 710 } 711 712 #if NATAPIBUS > 0 713 static void 714 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 715 { 716 struct ata_channel *chp = ata_sc->sc_chan; 717 struct atac_softc *atac = chp->ch_atac; 718 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 719 struct scsipi_channel *chan = &chp->ch_atapi_channel; 720 721 /* 722 * Fill in the scsipi_adapter. 723 */ 724 adapt->adapt_dev = atac->atac_dev; 725 adapt->adapt_nchannels = atac->atac_nchannels; 726 adapt->adapt_request = mvsata_atapi_scsipi_request; 727 adapt->adapt_minphys = mvsata_atapi_minphys; 728 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 729 730 /* 731 * Fill in the scsipi_channel. 732 */ 733 memset(chan, 0, sizeof(*chan)); 734 chan->chan_adapter = adapt; 735 chan->chan_bustype = &mvsata_atapi_bustype; 736 chan->chan_channel = chp->ch_channel; 737 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 738 chan->chan_openings = 1; 739 chan->chan_max_periph = 1; 740 chan->chan_ntargets = 1; 741 chan->chan_nluns = 1; 742 743 chp->atapibus = 744 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 745 } 746 747 static void 748 mvsata_atapi_minphys(struct buf *bp) 749 { 750 751 if (bp->b_bcount > MAXPHYS) 752 bp->b_bcount = MAXPHYS; 753 minphys(bp); 754 } 755 756 static void 757 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 758 { 759 struct scsipi_channel *chan = sc->sc_channel; 760 struct scsipi_periph *periph; 761 struct ataparams ids; 762 struct ataparams *id = &ids; 763 struct mvsata_softc *mvc = 764 device_private(chan->chan_adapter->adapt_dev); 765 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 766 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 767 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 768 struct scsipibus_attach_args sa; 769 char serial_number[21], model[41], firmware_revision[9]; 770 int s; 771 772 /* skip if already attached */ 773 if (scsipi_lookup_periph(chan, target, 0) != NULL) 774 return; 775 776 /* if no ATAPI device detected at attach time, skip */ 777 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 778 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 779 " drive %d not present\n", 780 device_xname(atac->atac_dev), chp->ch_channel, target)); 781 return; 782 } 783 784 /* Some ATAPI devices need a bit more time after software reset. */ 785 delay(5000); 786 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 787 #ifdef ATAPI_DEBUG_PROBE 788 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 789 device_xname(sc->sc_dev), target, 790 id->atap_config & ATAPI_CFG_CMD_MASK, 791 id->atap_config & ATAPI_CFG_DRQ_MASK); 792 #endif 793 periph = scsipi_alloc_periph(M_WAITOK); 794 periph->periph_dev = NULL; 795 periph->periph_channel = chan; 796 periph->periph_switch = &atapi_probe_periphsw; 797 periph->periph_target = target; 798 periph->periph_lun = 0; 799 periph->periph_quirks = PQUIRK_ONLYBIG; 800 801 #ifdef SCSIPI_DEBUG 802 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 803 SCSIPI_DEBUG_TARGET == target) 804 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 805 #endif 806 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 807 if (id->atap_config & ATAPI_CFG_REMOV) 808 periph->periph_flags |= PERIPH_REMOVABLE; 809 if (periph->periph_type == T_SEQUENTIAL) { 810 s = splbio(); 811 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 812 splx(s); 813 } 814 815 sa.sa_periph = periph; 816 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 817 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 818 T_REMOV : T_FIXED; 819 strnvisx(model, sizeof(model), id->atap_model, 40, 820 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 821 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 822 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 823 strnvisx(firmware_revision, sizeof(firmware_revision), 824 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 825 sa.sa_inqbuf.vendor = model; 826 sa.sa_inqbuf.product = serial_number; 827 sa.sa_inqbuf.revision = firmware_revision; 828 829 /* 830 * Determine the operating mode capabilities of the device. 831 */ 832 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 833 periph->periph_cap |= PERIPH_CAP_CMD16; 834 /* XXX This is gross. */ 835 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 836 837 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 838 839 if (drvp->drv_softc) 840 ata_probe_caps(drvp); 841 else { 842 s = splbio(); 843 drvp->drive_type = ATA_DRIVET_NONE; 844 splx(s); 845 } 846 } else { 847 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 848 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 849 device_xname(atac->atac_dev), chp->ch_channel, target)); 850 s = splbio(); 851 drvp->drive_type = ATA_DRIVET_NONE; 852 splx(s); 853 } 854 } 855 856 /* 857 * Kill off all pending xfers for a periph. 858 * 859 * Must be called at splbio(). 860 */ 861 static void 862 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 863 { 864 struct atac_softc *atac = 865 device_private(periph->periph_channel->chan_adapter->adapt_dev); 866 struct ata_channel *chp = 867 atac->atac_channels[periph->periph_channel->chan_channel]; 868 869 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 870 } 871 #endif /* NATAPIBUS > 0 */ 872 #endif /* MVSATA_WITHOUTDMA */ 873 874 875 /* 876 * mvsata_setup_channel() 877 * Setup EDMA registers and prepare/purge DMA resources. 878 * We assuming already stopped the EDMA. 879 */ 880 static void 881 mvsata_setup_channel(struct ata_channel *chp) 882 { 883 #ifndef MVSATA_WITHOUTDMA 884 struct mvsata_port *mvport = (struct mvsata_port *)chp; 885 struct ata_drive_datas *drvp; 886 int drive, s; 887 uint32_t edma_mode = nodma; 888 int i; 889 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 890 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 891 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 892 893 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 894 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 895 896 for (drive = 0; drive < chp->ch_ndrives; drive++) { 897 drvp = &chp->ch_drive[drive]; 898 899 /* If no drive, skip */ 900 if (drvp->drive_type == ATA_DRIVET_NONE) 901 continue; 902 903 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 904 /* use Ultra/DMA */ 905 s = splbio(); 906 drvp->drive_flags &= ~ATA_DRIVE_DMA; 907 splx(s); 908 } 909 910 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 911 if (drvp->drive_flags & ATA_DRIVE_NCQ) 912 edma_mode = ncq; 913 else if (drvp->drive_type == ATA_DRIVET_ATA) 914 edma_mode = dma; 915 } 916 } 917 918 DPRINTF(DEBUG_FUNCS, 919 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 920 921 if (edma_mode == nodma) { 922 no_edma: 923 if (mvport->port_crqb != NULL) 924 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 925 mvport->port_crqb_dmamap, mvport->port_crqb); 926 if (mvport->port_crpb != NULL) 927 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 928 mvport->port_crpb_dmamap, mvport->port_crpb); 929 if (mvport->port_eprd != NULL) 930 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 931 mvport->port_eprd_dmamap, mvport->port_eprd); 932 933 return; 934 } 935 936 if (mvport->port_crqb == NULL) 937 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 938 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 939 if (mvport->port_crpb == NULL) 940 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 941 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 942 if (mvport->port_eprd == NULL) { 943 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 944 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 945 1); 946 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 947 mvport->port_reqtbl[i].eprd_offset = 948 i * MVSATA_EPRD_MAX_SIZE; 949 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 950 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 951 } 952 } 953 954 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 955 mvport->port_eprd == NULL) { 956 aprint_error_dev(MVSATA_DEV2(mvport), 957 "channel %d: can't use EDMA\n", chp->ch_channel); 958 s = splbio(); 959 for (drive = 0; drive < chp->ch_ndrives; drive++) { 960 drvp = &chp->ch_drive[drive]; 961 962 /* If no drive, skip */ 963 if (drvp->drive_type == ATA_DRIVET_NONE) 964 continue; 965 966 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 967 } 968 splx(s); 969 goto no_edma; 970 } 971 972 mvsata_edma_config(mvport, edma_mode); 973 mvsata_edma_reset_qptr(mvport); 974 mvsata_edma_enable(mvport); 975 #endif 976 } 977 978 #ifndef MVSATA_WITHOUTDMA 979 static const struct ata_xfer_ops mvsata_bio_xfer_ops = { 980 .c_start = mvsata_bio_start, 981 .c_intr = mvsata_bio_intr, 982 .c_poll = mvsata_bio_poll, 983 .c_abort = mvsata_bio_done, 984 .c_kill_xfer = mvsata_bio_kill_xfer, 985 }; 986 987 static int 988 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 989 { 990 struct ata_channel *chp = drvp->chnl_softc; 991 struct atac_softc *atac = chp->ch_atac; 992 struct ata_bio *ata_bio = &xfer->c_bio; 993 994 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 995 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 996 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 997 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 998 999 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1000 ata_bio->flags |= ATA_POLL; 1001 if (ata_bio->flags & ATA_POLL) 1002 xfer->c_flags |= C_POLL; 1003 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1004 (ata_bio->flags & ATA_SINGLE) == 0) 1005 xfer->c_flags |= C_DMA; 1006 xfer->c_drive = drvp->drive; 1007 xfer->c_databuf = ata_bio->databuf; 1008 xfer->c_bcount = ata_bio->bcount; 1009 xfer->ops = &mvsata_bio_xfer_ops; 1010 ata_exec_xfer(chp, xfer); 1011 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 1012 } 1013 1014 static int 1015 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1016 { 1017 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1018 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1019 struct atac_softc *atac = chp->ch_atac; 1020 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1021 struct ata_bio *ata_bio = &xfer->c_bio; 1022 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1023 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1024 u_int16_t cyl; 1025 u_int8_t head, sect, cmd = 0; 1026 int nblks, error, tfd; 1027 1028 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1029 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1030 1031 ata_channel_lock_owned(chp); 1032 1033 if (xfer->c_flags & C_DMA) 1034 if (drvp->n_xfers <= NXFER) 1035 drvp->n_xfers++; 1036 1037 /* 1038 * 1039 * When starting a multi-sector transfer, or doing single-sector 1040 * transfers... 1041 */ 1042 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1043 if (ata_bio->flags & ATA_SINGLE) 1044 nblks = 1; 1045 else 1046 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1047 /* Check for bad sectors and adjust transfer, if necessary. */ 1048 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1049 long blkdiff; 1050 int i; 1051 1052 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1053 i++) { 1054 blkdiff -= ata_bio->blkno; 1055 if (blkdiff < 0) 1056 continue; 1057 if (blkdiff == 0) 1058 /* Replace current block of transfer. */ 1059 ata_bio->blkno = 1060 drvp->lp->d_secperunit - 1061 drvp->lp->d_nsectors - i - 1; 1062 if (blkdiff < nblks) { 1063 /* Bad block inside transfer. */ 1064 ata_bio->flags |= ATA_SINGLE; 1065 nblks = 1; 1066 } 1067 break; 1068 } 1069 /* Transfer is okay now. */ 1070 } 1071 if (xfer->c_flags & C_DMA) { 1072 enum mvsata_edmamode dmamode; 1073 1074 ata_bio->nblks = nblks; 1075 ata_bio->nbytes = xfer->c_bcount; 1076 1077 /* switch to appropriate dma mode if necessary */ 1078 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1079 if (mvport->port_edmamode_curr != dmamode) 1080 mvsata_edma_config(mvport, dmamode); 1081 1082 if (xfer->c_flags & C_POLL) 1083 sc->sc_enable_intr(mvport, 0 /*off*/); 1084 error = mvsata_edma_enqueue(mvport, xfer); 1085 if (error) { 1086 if (error == EINVAL) { 1087 /* 1088 * We can't do DMA on this transfer 1089 * for some reason. Fall back to 1090 * PIO. 1091 */ 1092 xfer->c_flags &= ~C_DMA; 1093 error = 0; 1094 goto do_pio; 1095 } 1096 if (error == EBUSY) { 1097 aprint_error_dev(atac->atac_dev, 1098 "channel %d: EDMA Queue full\n", 1099 chp->ch_channel); 1100 /* 1101 * XXX: Perhaps, after it waits for 1102 * a while, it is necessary to call 1103 * bio_start again. 1104 */ 1105 } 1106 ata_bio->error = ERR_DMA; 1107 ata_bio->r_error = 0; 1108 return ATASTART_ABORT; 1109 } 1110 chp->ch_flags |= ATACH_DMA_WAIT; 1111 /* start timeout machinery */ 1112 if ((xfer->c_flags & C_POLL) == 0) 1113 callout_reset(&chp->c_timo_callout, 1114 mstohz(ATA_DELAY), ata_timeout, chp); 1115 /* wait for irq */ 1116 goto intr; 1117 } /* else not DMA */ 1118 do_pio: 1119 if (ata_bio->flags & ATA_LBA48) { 1120 sect = 0; 1121 cyl = 0; 1122 head = 0; 1123 } else if (ata_bio->flags & ATA_LBA) { 1124 sect = (ata_bio->blkno >> 0) & 0xff; 1125 cyl = (ata_bio->blkno >> 8) & 0xffff; 1126 head = (ata_bio->blkno >> 24) & 0x0f; 1127 head |= WDSD_LBA; 1128 } else { 1129 int blkno = ata_bio->blkno; 1130 sect = blkno % drvp->lp->d_nsectors; 1131 sect++; /* Sectors begin with 1, not 0. */ 1132 blkno /= drvp->lp->d_nsectors; 1133 head = blkno % drvp->lp->d_ntracks; 1134 blkno /= drvp->lp->d_ntracks; 1135 cyl = blkno; 1136 head |= WDSD_CHS; 1137 } 1138 ata_bio->nblks = uimin(nblks, drvp->multi); 1139 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1140 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1141 if (ata_bio->nblks > 1) 1142 cmd = (ata_bio->flags & ATA_READ) ? 1143 WDCC_READMULTI : WDCC_WRITEMULTI; 1144 else 1145 cmd = (ata_bio->flags & ATA_READ) ? 1146 WDCC_READ : WDCC_WRITE; 1147 1148 /* EDMA disable, if enabled this channel. */ 1149 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1150 if (mvport->port_edmamode_curr != nodma) 1151 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1152 1153 mvsata_pmp_select(mvport, xfer->c_drive); 1154 1155 /* Do control operations specially. */ 1156 if (__predict_false(drvp->state < READY)) { 1157 /* 1158 * Actually, we want to be careful not to mess with 1159 * the control state if the device is currently busy, 1160 * but we can assume that we never get to this point 1161 * if that's the case. 1162 */ 1163 /* 1164 * If it's not a polled command, we need the kernel 1165 * thread 1166 */ 1167 if ((xfer->c_flags & C_POLL) == 0 && 1168 (chp->ch_flags & ATACH_TH_RUN) == 0) { 1169 return ATASTART_TH; 1170 } 1171 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1172 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1173 return ATASTART_ABORT; 1174 } 1175 } 1176 1177 /* Initiate command! */ 1178 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1179 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1180 case WDCWAIT_OK: 1181 break; 1182 case WDCWAIT_TOUT: 1183 goto timeout; 1184 case WDCWAIT_THR: 1185 return ATASTART_TH; 1186 } 1187 if (ata_bio->flags & ATA_LBA48) 1188 wdccommandext(chp, 0, atacmd_to48(cmd), 1189 ata_bio->blkno, nblks, 0, WDSD_LBA); 1190 else 1191 wdccommand(chp, 0, cmd, cyl, 1192 head, sect, nblks, 1193 (drvp->lp->d_type == DKTYPE_ST506) ? 1194 drvp->lp->d_precompcyl / 4 : 0); 1195 1196 /* start timeout machinery */ 1197 if ((xfer->c_flags & C_POLL) == 0) 1198 callout_reset(&chp->c_timo_callout, 1199 mstohz(ATA_DELAY), wdctimeout, chp); 1200 } else if (ata_bio->nblks > 1) { 1201 /* The number of blocks in the last stretch may be smaller. */ 1202 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1203 if (ata_bio->nblks > nblks) { 1204 ata_bio->nblks = nblks; 1205 ata_bio->nbytes = xfer->c_bcount; 1206 } 1207 } 1208 /* If this was a write and not using DMA, push the data. */ 1209 if ((ata_bio->flags & ATA_READ) == 0) { 1210 /* 1211 * we have to busy-wait here, we can't rely on running in 1212 * thread context. 1213 */ 1214 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1215 aprint_error_dev(atac->atac_dev, 1216 "channel %d: drive %d timeout waiting for DRQ," 1217 " st=0x%02x, err=0x%02x\n", 1218 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1219 ATACH_ERR(tfd)); 1220 ata_bio->error = TIMEOUT; 1221 return ATASTART_ABORT; 1222 } 1223 if (ATACH_ST(tfd) & WDCS_ERR) { 1224 ata_bio->error = ERROR; 1225 ata_bio->r_error = ATACH_ERR(tfd); 1226 mvsata_bio_done(chp, xfer); 1227 return ATASTART_ABORT; 1228 } 1229 1230 wdc->dataout_pio(chp, drvp->drive_flags, 1231 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1232 } 1233 1234 intr: 1235 KASSERTMSG(((xfer->c_flags & C_DMA) != 0) 1236 == (mvport->port_edmamode_curr != nodma), 1237 "DMA mode mismatch: flags %x vs edmamode %d != %d", 1238 xfer->c_flags, mvport->port_edmamode_curr, nodma); 1239 1240 /* Wait for IRQ (either real or polled) */ 1241 if ((ata_bio->flags & ATA_POLL) != 0) 1242 return ATASTART_POLL; 1243 else 1244 return ATASTART_STARTED; 1245 1246 timeout: 1247 aprint_error_dev(atac->atac_dev, 1248 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1249 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1250 ata_bio->error = TIMEOUT; 1251 return ATASTART_ABORT; 1252 } 1253 1254 static void 1255 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1256 { 1257 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1258 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1259 1260 /* Wait for at last 400ns for status bit to be valid */ 1261 delay(1); 1262 if (chp->ch_flags & ATACH_DMA_WAIT) { 1263 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1264 sc->sc_enable_intr(mvport, 1 /*on*/); 1265 chp->ch_flags &= ~ATACH_DMA_WAIT; 1266 } 1267 1268 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1269 KASSERT(xfer->c_flags & C_TIMEOU); 1270 mvsata_bio_intr(chp, xfer, 0); 1271 } 1272 } 1273 1274 static int 1275 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int intr_arg) 1276 { 1277 struct atac_softc *atac = chp->ch_atac; 1278 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1279 struct ata_bio *ata_bio = &xfer->c_bio; 1280 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1281 int irq = ISSET(xfer->c_flags, (C_POLL|C_TIMEOU)) ? 0 : 1; 1282 int tfd = 0; 1283 1284 if (ISSET(xfer->c_flags, C_DMA|C_RECOVERED) && irq) { 1285 /* Invoked via mvsata_edma_handle() or recovery */ 1286 tfd = intr_arg; 1287 1288 if (tfd > 0 && ata_bio->error == NOERROR) { 1289 if (ATACH_ST(tfd) & WDCS_ERR) 1290 ata_bio->error = ERROR; 1291 if (ATACH_ST(tfd) & WDCS_BSY) 1292 ata_bio->error = TIMEOUT; 1293 ata_bio->r_error = ATACH_ERR(tfd); 1294 } 1295 } 1296 1297 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1298 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1299 xfer->c_drive)); 1300 1301 /* Cleanup EDMA if invoked from wdctimeout()/ata_timeout() */ 1302 if (ISSET(xfer->c_flags, C_TIMEOU) && ISSET(xfer->c_flags, C_DMA) 1303 && !ISSET(xfer->c_flags, C_POLL)) { 1304 mvsata_edma_rqq_remove((struct mvsata_port *)chp, xfer); 1305 } 1306 1307 ata_channel_lock(chp); 1308 1309 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1310 1311 /* 1312 * If we missed an interrupt transfer, reset and restart. 1313 * Don't try to continue transfer, we may have missed cycles. 1314 */ 1315 if (xfer->c_flags & C_TIMEOU) { 1316 ata_bio->error = TIMEOUT; 1317 ata_channel_unlock(chp); 1318 mvsata_bio_done(chp, xfer); 1319 return 1; 1320 } 1321 1322 /* Is it not a transfer, but a control operation? */ 1323 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1324 aprint_error_dev(atac->atac_dev, 1325 "channel %d: drive %d bad state %d in %s\n", 1326 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1327 panic("%s: bad state", __func__); 1328 } 1329 1330 /* Ack interrupt done by wdc_wait_for_unbusy */ 1331 if (!(xfer->c_flags & C_DMA) && 1332 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1333 == WDCWAIT_TOUT)) { 1334 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1335 ata_channel_unlock(chp); 1336 return 0; /* IRQ was not for us */ 1337 } 1338 aprint_error_dev(atac->atac_dev, 1339 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1340 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1341 xfer->c_skip); 1342 ata_bio->error = TIMEOUT; 1343 ata_channel_unlock(chp); 1344 mvsata_bio_done(chp, xfer); 1345 return 1; 1346 } 1347 1348 if (xfer->c_flags & C_DMA) { 1349 if (ata_bio->error == NOERROR) 1350 goto end; 1351 if (ata_bio->error == ERR_DMA) { 1352 ata_dmaerr(drvp, 1353 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1354 ata_channel_unlock(chp); 1355 goto err; 1356 } 1357 } 1358 1359 /* if we had an error, end */ 1360 if (ata_bio->error != NOERROR) { 1361 ata_channel_unlock(chp); 1362 err: 1363 mvsata_bio_done(chp, xfer); 1364 return 1; 1365 } 1366 1367 /* If this was a read and not using DMA, fetch the data. */ 1368 if ((ata_bio->flags & ATA_READ) != 0) { 1369 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1370 aprint_error_dev(atac->atac_dev, 1371 "channel %d: drive %d read intr before drq\n", 1372 chp->ch_channel, xfer->c_drive); 1373 ata_bio->error = TIMEOUT; 1374 ata_channel_unlock(chp); 1375 mvsata_bio_done(chp, xfer); 1376 return 1; 1377 } 1378 wdc->datain_pio(chp, drvp->drive_flags, 1379 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1380 } 1381 1382 end: 1383 ata_bio->blkno += ata_bio->nblks; 1384 ata_bio->blkdone += ata_bio->nblks; 1385 xfer->c_skip += ata_bio->nbytes; 1386 xfer->c_bcount -= ata_bio->nbytes; 1387 1388 /* See if this transfer is complete. */ 1389 if (xfer->c_bcount > 0) { 1390 if ((ata_bio->flags & ATA_POLL) == 0) { 1391 /* Start the next operation */ 1392 ata_xfer_start(xfer); 1393 } else { 1394 /* Let mvsata_bio_start do the loop */ 1395 } 1396 ata_channel_unlock(chp); 1397 } else { /* Done with this transfer */ 1398 ata_bio->error = NOERROR; 1399 ata_channel_unlock(chp); 1400 mvsata_bio_done(chp, xfer); 1401 } 1402 return 1; 1403 } 1404 1405 static void 1406 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1407 { 1408 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1409 struct atac_softc *atac = chp->ch_atac; 1410 struct ata_bio *ata_bio = &xfer->c_bio; 1411 int drive = xfer->c_drive; 1412 bool deactivate = true; 1413 1414 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1415 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1416 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1417 1418 /* EDMA restart, if enabled */ 1419 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1420 mvsata_edma_reset_qptr(mvport); 1421 mvsata_edma_enable(mvport); 1422 } 1423 1424 ata_bio->flags |= ATA_ITSDONE; 1425 switch (reason) { 1426 case KILL_GONE_INACTIVE: 1427 deactivate = false; 1428 /* FALLTHROUGH */ 1429 case KILL_GONE: 1430 ata_bio->error = ERR_NODEV; 1431 break; 1432 case KILL_RESET: 1433 ata_bio->error = ERR_RESET; 1434 break; 1435 case KILL_REQUEUE: 1436 ata_bio->error = REQUEUE; 1437 break; 1438 default: 1439 aprint_error_dev(atac->atac_dev, 1440 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1441 panic("mvsata_bio_kill_xfer"); 1442 } 1443 ata_bio->r_error = WDCE_ABRT; 1444 1445 if (deactivate) 1446 ata_deactivate_xfer(chp, xfer); 1447 1448 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1449 } 1450 1451 static void 1452 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1453 { 1454 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1455 struct ata_bio *ata_bio = &xfer->c_bio; 1456 int drive = xfer->c_drive; 1457 bool iserror = (ata_bio->error != NOERROR); 1458 1459 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1460 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1461 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1462 (u_int)xfer->c_flags)); 1463 1464 /* EDMA restart, if enabled */ 1465 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1466 mvsata_edma_reset_qptr(mvport); 1467 mvsata_edma_enable(mvport); 1468 } 1469 1470 if (ata_waitdrain_xfer_check(chp, xfer)) 1471 return; 1472 1473 /* feed back residual bcount to our caller */ 1474 ata_bio->bcount = xfer->c_bcount; 1475 1476 /* mark controller inactive and free xfer */ 1477 ata_deactivate_xfer(chp, xfer); 1478 1479 ata_bio->flags |= ATA_ITSDONE; 1480 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1481 if (!iserror) 1482 atastart(chp); 1483 } 1484 1485 static int 1486 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1487 int flags) 1488 { 1489 struct ata_channel *chp = &mvport->port_ata_channel; 1490 struct atac_softc *atac = chp->ch_atac; 1491 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1492 const char *errstring; 1493 int tfd; 1494 1495 flags |= AT_POLL; /* XXX */ 1496 1497 ata_channel_lock_owned(chp); 1498 1499 /* 1500 * disable interrupts, all commands here should be quick 1501 * enough to be able to poll, and we don't go here that often 1502 */ 1503 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1504 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1505 DELAY(10); 1506 errstring = "wait"; 1507 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1508 goto ctrltimeout; 1509 wdccommandshort(chp, 0, WDCC_RECAL); 1510 /* Wait for at least 400ns for status bit to be valid */ 1511 DELAY(1); 1512 errstring = "recal"; 1513 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1514 goto ctrltimeout; 1515 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1516 goto ctrlerror; 1517 /* Don't try to set modes if controller can't be adjusted */ 1518 if (atac->atac_set_modes == NULL) 1519 goto geometry; 1520 /* Also don't try if the drive didn't report its mode */ 1521 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1522 goto geometry; 1523 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1524 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1525 errstring = "piomode-bio"; 1526 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1527 goto ctrltimeout; 1528 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1529 goto ctrlerror; 1530 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1531 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1532 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1533 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1534 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1535 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1536 else 1537 goto geometry; 1538 errstring = "dmamode-bio"; 1539 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1540 goto ctrltimeout; 1541 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1542 goto ctrlerror; 1543 geometry: 1544 if (ata_bio->flags & ATA_LBA) 1545 goto multimode; 1546 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1547 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1548 (drvp->lp->d_type == DKTYPE_ST506) ? 1549 drvp->lp->d_precompcyl / 4 : 0); 1550 errstring = "geometry"; 1551 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1552 goto ctrltimeout; 1553 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1554 goto ctrlerror; 1555 multimode: 1556 if (drvp->multi == 1) 1557 goto ready; 1558 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1559 errstring = "setmulti"; 1560 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1561 goto ctrltimeout; 1562 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1563 goto ctrlerror; 1564 ready: 1565 drvp->state = READY; 1566 /* 1567 * The drive is usable now 1568 */ 1569 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1570 delay(10); /* some drives need a little delay here */ 1571 return 0; 1572 1573 ctrltimeout: 1574 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1575 chp->ch_channel, drive, errstring); 1576 ata_bio->error = TIMEOUT; 1577 goto ctrldone; 1578 ctrlerror: 1579 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1580 chp->ch_channel, drive, errstring); 1581 if (ATACH_ST(tfd) & WDCS_DWF) { 1582 aprint_error("drive fault\n"); 1583 ata_bio->error = ERR_DF; 1584 } else { 1585 ata_bio->r_error = ATACH_ERR(tfd); 1586 ata_bio->error = ERROR; 1587 aprint_error("error (%x)\n", ata_bio->r_error); 1588 } 1589 ctrldone: 1590 drvp->state = 0; 1591 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1592 return -1; 1593 } 1594 1595 static const struct ata_xfer_ops mvsata_wdc_cmd_xfer_ops = { 1596 .c_start = mvsata_wdc_cmd_start, 1597 .c_intr = mvsata_wdc_cmd_intr, 1598 .c_poll = mvsata_wdc_cmd_poll, 1599 .c_abort = mvsata_wdc_cmd_done, 1600 .c_kill_xfer = mvsata_wdc_cmd_kill_xfer, 1601 }; 1602 1603 static int 1604 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1605 { 1606 struct ata_channel *chp = drvp->chnl_softc; 1607 struct ata_command *ata_c = &xfer->c_ata_c; 1608 int rv, s; 1609 1610 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1611 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1612 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1613 " r_device=0x%02x, r_command=0x%02x\n", 1614 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1615 chp->ch_channel, 1616 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1617 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1618 1619 if (ata_c->flags & AT_POLL) 1620 xfer->c_flags |= C_POLL; 1621 if (ata_c->flags & AT_WAIT) 1622 xfer->c_flags |= C_WAIT; 1623 xfer->c_drive = drvp->drive; 1624 xfer->c_databuf = ata_c->data; 1625 xfer->c_bcount = ata_c->bcount; 1626 xfer->ops = &mvsata_wdc_cmd_xfer_ops; 1627 s = splbio(); 1628 ata_exec_xfer(chp, xfer); 1629 #ifdef DIAGNOSTIC 1630 if ((ata_c->flags & AT_POLL) != 0 && 1631 (ata_c->flags & AT_DONE) == 0) 1632 panic("mvsata_exec_command: polled command not done"); 1633 #endif 1634 if (ata_c->flags & AT_DONE) 1635 rv = ATACMD_COMPLETE; 1636 else { 1637 if (ata_c->flags & AT_WAIT) { 1638 ata_wait_cmd(chp, xfer); 1639 rv = ATACMD_COMPLETE; 1640 } else 1641 rv = ATACMD_QUEUED; 1642 } 1643 splx(s); 1644 return rv; 1645 } 1646 1647 static int 1648 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1649 { 1650 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1651 int drive = xfer->c_drive; 1652 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1653 struct ata_command *ata_c = &xfer->c_ata_c; 1654 int tfd; 1655 1656 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1657 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1658 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1659 1660 ata_channel_lock_owned(chp); 1661 1662 /* First, EDMA disable, if enabled this channel. */ 1663 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1664 if (mvport->port_edmamode_curr != nodma) 1665 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1666 1667 mvsata_pmp_select(mvport, drive); 1668 1669 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1670 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1671 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1672 case WDCWAIT_OK: 1673 break; 1674 case WDCWAIT_TOUT: 1675 ata_c->flags |= AT_TIMEOU; 1676 return ATASTART_ABORT; 1677 case WDCWAIT_THR: 1678 return ATASTART_TH; 1679 } 1680 if (ata_c->flags & AT_POLL) 1681 /* polled command, disable interrupts */ 1682 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1683 if ((ata_c->flags & AT_LBA48) != 0) { 1684 wdccommandext(chp, 0, ata_c->r_command, 1685 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1686 ata_c->r_device & ~0x10); 1687 } else { 1688 wdccommand(chp, 0, ata_c->r_command, 1689 (ata_c->r_lba >> 8) & 0xffff, 1690 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1691 ((ata_c->r_lba >> 24) & 0x0f), 1692 ata_c->r_lba & 0xff, 1693 ata_c->r_count & 0xff, 1694 ata_c->r_features & 0xff); 1695 } 1696 1697 if ((ata_c->flags & AT_POLL) == 0) { 1698 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1699 wdctimeout, chp); 1700 return ATASTART_STARTED; 1701 } 1702 1703 return ATASTART_POLL; 1704 } 1705 1706 static void 1707 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1708 { 1709 /* 1710 * Polled command. Wait for drive ready or drq. Done in intr(). 1711 * Wait for at last 400ns for status bit to be valid. 1712 */ 1713 delay(10); /* 400ns delay */ 1714 mvsata_wdc_cmd_intr(chp, xfer, 0); 1715 } 1716 1717 static int 1718 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1719 { 1720 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1721 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1722 struct ata_command *ata_c = &xfer->c_ata_c; 1723 int bcount = ata_c->bcount; 1724 char *data = ata_c->data; 1725 int wflags; 1726 int drive_flags; 1727 int tfd; 1728 1729 ata_channel_lock(chp); 1730 1731 if (ata_c->r_command == WDCC_IDENTIFY || 1732 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1733 /* 1734 * The IDENTIFY data has been designed as an array of 1735 * u_int16_t, so we can byteswap it on the fly. 1736 * Historically it's what we have always done so keeping it 1737 * here ensure binary backward compatibility. 1738 */ 1739 drive_flags = ATA_DRIVE_NOSTREAM | 1740 chp->ch_drive[xfer->c_drive].drive_flags; 1741 else 1742 /* 1743 * Other data structure are opaque and should be transfered 1744 * as is. 1745 */ 1746 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1747 1748 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1749 /* both wait and poll, we can kpause here */ 1750 wflags = AT_WAIT | AT_POLL; 1751 else 1752 wflags = AT_POLL; 1753 1754 again: 1755 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1756 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1757 __func__, xfer->c_drive)); 1758 1759 /* 1760 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1761 * Reselect again, it doesn't hurt for others commands, and the time 1762 * penalty for the extra register write is acceptable, 1763 * wdc_exec_command() isn't called often (mostly for autoconfig) 1764 */ 1765 if ((xfer->c_flags & C_ATAPI) != 0) { 1766 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1767 } 1768 if ((ata_c->flags & AT_XFDONE) != 0) { 1769 /* 1770 * We have completed a data xfer. The drive should now be 1771 * in its initial state 1772 */ 1773 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1774 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1775 wflags, &tfd) == WDCWAIT_TOUT) { 1776 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1777 ata_channel_unlock(chp); 1778 return 0; /* IRQ was not for us */ 1779 } 1780 ata_c->flags |= AT_TIMEOU; 1781 } 1782 goto out; 1783 } 1784 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1785 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1786 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1787 ata_channel_unlock(chp); 1788 return 0; /* IRQ was not for us */ 1789 } 1790 ata_c->flags |= AT_TIMEOU; 1791 goto out; 1792 } 1793 delay(20); /* XXXXX: Delay more times. */ 1794 if (ata_c->flags & AT_READ) { 1795 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1796 ata_c->flags |= AT_TIMEOU; 1797 goto out; 1798 } 1799 wdc->datain_pio(chp, drive_flags, data, bcount); 1800 /* at this point the drive should be in its initial state */ 1801 ata_c->flags |= AT_XFDONE; 1802 /* 1803 * XXX checking the status register again here cause some 1804 * hardware to timeout. 1805 */ 1806 } else if (ata_c->flags & AT_WRITE) { 1807 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1808 ata_c->flags |= AT_TIMEOU; 1809 goto out; 1810 } 1811 wdc->dataout_pio(chp, drive_flags, data, bcount); 1812 ata_c->flags |= AT_XFDONE; 1813 if ((ata_c->flags & AT_POLL) == 0) { 1814 callout_reset(&chp->c_timo_callout, 1815 mstohz(ata_c->timeout), wdctimeout, chp); 1816 ata_channel_unlock(chp); 1817 return 1; 1818 } else 1819 goto again; 1820 } 1821 out: 1822 if (ATACH_ST(tfd) & WDCS_DWF) 1823 ata_c->flags |= AT_DF; 1824 if (ATACH_ST(tfd) & WDCS_ERR) { 1825 ata_c->flags |= AT_ERROR; 1826 ata_c->r_error = ATACH_ERR(tfd); 1827 } 1828 ata_channel_unlock(chp); 1829 mvsata_wdc_cmd_done(chp, xfer); 1830 1831 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1832 atastart(chp); 1833 1834 return 1; 1835 } 1836 1837 static void 1838 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1839 int reason) 1840 { 1841 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1842 struct ata_command *ata_c = &xfer->c_ata_c; 1843 bool deactivate = true; 1844 1845 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1846 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1847 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1848 1849 switch (reason) { 1850 case KILL_GONE_INACTIVE: 1851 deactivate = false; 1852 /* FALLTHROUGH */ 1853 case KILL_GONE: 1854 ata_c->flags |= AT_GONE; 1855 break; 1856 case KILL_RESET: 1857 ata_c->flags |= AT_RESET; 1858 break; 1859 case KILL_REQUEUE: 1860 panic("%s: not supposed to be requeued\n", __func__); 1861 break; 1862 default: 1863 aprint_error_dev(MVSATA_DEV2(mvport), 1864 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1865 panic("mvsata_cmd_kill_xfer"); 1866 } 1867 1868 mvsata_wdc_cmd_done_end(chp, xfer); 1869 1870 if (deactivate) 1871 ata_deactivate_xfer(chp, xfer); 1872 } 1873 1874 static void 1875 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1876 { 1877 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1878 struct atac_softc *atac = chp->ch_atac; 1879 struct ata_command *ata_c = &xfer->c_ata_c; 1880 1881 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1882 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1883 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1884 ata_c->flags)); 1885 1886 if (ata_waitdrain_xfer_check(chp, xfer)) 1887 return; 1888 1889 if ((ata_c->flags & AT_READREG) != 0 && 1890 device_is_active(atac->atac_dev) && 1891 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1892 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1893 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1894 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1895 ata_c->r_lba = 1896 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1897 ata_c->r_lba |= 1898 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1899 ata_c->r_lba |= 1900 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1901 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1902 if ((ata_c->flags & AT_LBA48) != 0) { 1903 if ((ata_c->flags & AT_POLL) != 0) { 1904 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1905 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1906 } else { 1907 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1908 WDCTL_HOB|WDCTL_4BIT); 1909 } 1910 ata_c->r_count |= 1911 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1912 ata_c->r_lba |= 1913 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1914 ata_c->r_lba |= 1915 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1916 ata_c->r_lba |= 1917 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1918 if ((ata_c->flags & AT_POLL) != 0) { 1919 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1920 WDCTL_4BIT|WDCTL_IDS); 1921 } else { 1922 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1923 WDCTL_4BIT); 1924 } 1925 } else { 1926 ata_c->r_lba |= 1927 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1928 } 1929 } 1930 1931 if (ata_c->flags & AT_POLL) { 1932 /* enable interrupts */ 1933 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1934 delay(10); /* some drives need a little delay here */ 1935 } 1936 1937 mvsata_wdc_cmd_done_end(chp, xfer); 1938 1939 ata_deactivate_xfer(chp, xfer); 1940 } 1941 1942 static void 1943 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1944 { 1945 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1946 struct ata_command *ata_c = &xfer->c_ata_c; 1947 1948 /* EDMA restart, if enabled */ 1949 if (mvport->port_edmamode_curr != nodma) { 1950 mvsata_edma_reset_qptr(mvport); 1951 mvsata_edma_enable(mvport); 1952 } 1953 1954 ata_c->flags |= AT_DONE; 1955 } 1956 1957 #if NATAPIBUS > 0 1958 static const struct ata_xfer_ops mvsata_atapi_xfer_ops = { 1959 .c_start = mvsata_atapi_start, 1960 .c_intr = mvsata_atapi_intr, 1961 .c_poll = mvsata_atapi_poll, 1962 .c_abort = mvsata_atapi_reset, 1963 .c_kill_xfer = mvsata_atapi_kill_xfer, 1964 }; 1965 1966 static void 1967 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 1968 scsipi_adapter_req_t req, void *arg) 1969 { 1970 struct scsipi_adapter *adapt = chan->chan_adapter; 1971 struct scsipi_periph *periph; 1972 struct scsipi_xfer *sc_xfer; 1973 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 1974 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1975 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1976 struct ata_xfer *xfer; 1977 int drive, s; 1978 1979 switch (req) { 1980 case ADAPTER_REQ_RUN_XFER: 1981 sc_xfer = arg; 1982 periph = sc_xfer->xs_periph; 1983 drive = periph->periph_target; 1984 1985 if (!device_is_active(atac->atac_dev)) { 1986 sc_xfer->error = XS_DRIVER_STUFFUP; 1987 scsipi_done(sc_xfer); 1988 return; 1989 } 1990 xfer = ata_get_xfer(chp, false); 1991 if (xfer == NULL) { 1992 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1993 scsipi_done(sc_xfer); 1994 return; 1995 } 1996 1997 if (sc_xfer->xs_control & XS_CTL_POLL) 1998 xfer->c_flags |= C_POLL; 1999 xfer->c_drive = drive; 2000 xfer->c_flags |= C_ATAPI; 2001 xfer->c_databuf = sc_xfer->data; 2002 xfer->c_bcount = sc_xfer->datalen; 2003 xfer->ops = &mvsata_atapi_xfer_ops; 2004 xfer->c_scsipi = sc_xfer; 2005 xfer->c_atapi.c_dscpoll = 0; 2006 s = splbio(); 2007 ata_exec_xfer(chp, xfer); 2008 #ifdef DIAGNOSTIC 2009 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 2010 (sc_xfer->xs_status & XS_STS_DONE) == 0) 2011 panic("mvsata_atapi_scsipi_request:" 2012 " polled command not done"); 2013 #endif 2014 splx(s); 2015 return; 2016 2017 default: 2018 /* Not supported, nothing to do. */ 2019 ; 2020 } 2021 } 2022 2023 static int 2024 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2025 { 2026 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2027 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2028 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2029 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2030 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2031 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2032 const char *errstring; 2033 int tfd; 2034 2035 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2036 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2037 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2038 xfer->c_drive, sc_xfer->xs_control)); 2039 2040 ata_channel_lock_owned(chp); 2041 2042 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2043 if (mvport->port_edmamode_curr != nodma) 2044 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2045 2046 mvsata_pmp_select(mvport, xfer->c_drive); 2047 2048 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2049 drvp->n_xfers++; 2050 2051 /* Do control operations specially. */ 2052 if (__predict_false(drvp->state < READY)) { 2053 /* If it's not a polled command, we need the kernel thread */ 2054 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && 2055 (chp->ch_flags & ATACH_TH_RUN) == 0) { 2056 return ATASTART_TH; 2057 } 2058 /* 2059 * disable interrupts, all commands here should be quick 2060 * enough to be able to poll, and we don't go here that often 2061 */ 2062 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2063 2064 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2065 /* Don't try to set mode if controller can't be adjusted */ 2066 if (atac->atac_set_modes == NULL) 2067 goto ready; 2068 /* Also don't try if the drive didn't report its mode */ 2069 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2070 goto ready; 2071 errstring = "unbusy"; 2072 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2073 goto timeout; 2074 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2075 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2076 errstring = "piomode-atapi"; 2077 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2078 &tfd)) 2079 goto timeout; 2080 if (ATACH_ST(tfd) & WDCS_ERR) { 2081 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2082 /* 2083 * Some ATAPI drives reject PIO settings. 2084 * Fall back to PIO mode 3 since that's the 2085 * minimum for ATAPI. 2086 */ 2087 aprint_error_dev(atac->atac_dev, 2088 "channel %d drive %d: PIO mode %d rejected," 2089 " falling back to PIO mode 3\n", 2090 chp->ch_channel, xfer->c_drive, 2091 drvp->PIO_mode); 2092 if (drvp->PIO_mode > 3) 2093 drvp->PIO_mode = 3; 2094 } else 2095 goto error; 2096 } 2097 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2098 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2099 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2100 else 2101 if (drvp->drive_flags & ATA_DRIVE_DMA) 2102 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2103 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2104 else 2105 goto ready; 2106 errstring = "dmamode-atapi"; 2107 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2108 &tfd)) 2109 goto timeout; 2110 if (ATACH_ST(tfd) & WDCS_ERR) { 2111 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2112 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2113 goto error; 2114 else { 2115 /* 2116 * The drive rejected our DMA setting. 2117 * Fall back to mode 1. 2118 */ 2119 aprint_error_dev(atac->atac_dev, 2120 "channel %d drive %d:" 2121 " DMA mode %d rejected," 2122 " falling back to DMA mode 0\n", 2123 chp->ch_channel, xfer->c_drive, 2124 drvp->DMA_mode); 2125 if (drvp->DMA_mode > 0) 2126 drvp->DMA_mode = 0; 2127 } 2128 } else 2129 goto error; 2130 } 2131 ready: 2132 drvp->state = READY; 2133 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2134 delay(10); /* some drives need a little delay here */ 2135 } 2136 /* start timeout machinery */ 2137 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2138 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 2139 wdctimeout, chp); 2140 2141 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2142 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2143 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2144 ATACH_ST(tfd)); 2145 sc_xfer->error = XS_TIMEOUT; 2146 return ATASTART_ABORT; 2147 } 2148 2149 /* 2150 * Even with WDCS_ERR, the device should accept a command packet 2151 * Limit length to what can be stuffed into the cylinder register 2152 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2153 * but not all devices do that and it's not obvious from the 2154 * ATAPI spec that that behaviour should be expected. If more 2155 * data is necessary, multiple data transfer phases will be done. 2156 */ 2157 2158 wdccommand(chp, 0, ATAPI_PKT_CMD, 2159 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2160 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2161 2162 /* 2163 * If there is no interrupt for CMD input, busy-wait for it (done in 2164 * the interrupt routine. Poll routine will exit early in this case. 2165 */ 2166 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2167 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2168 return ATASTART_POLL; 2169 else 2170 return ATASTART_STARTED; 2171 2172 timeout: 2173 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2174 chp->ch_channel, xfer->c_drive, errstring); 2175 sc_xfer->error = XS_TIMEOUT; 2176 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2177 delay(10); /* some drives need a little delay here */ 2178 return ATASTART_ABORT; 2179 2180 error: 2181 aprint_error_dev(atac->atac_dev, 2182 "channel %d drive %d: %s error (0x%x)\n", 2183 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2184 sc_xfer->error = XS_SHORTSENSE; 2185 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2186 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2187 delay(10); /* some drives need a little delay here */ 2188 return ATASTART_ABORT; 2189 } 2190 2191 static void 2192 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2193 { 2194 /* 2195 * If there is no interrupt for CMD input, busy-wait for it (done in 2196 * the interrupt routine. If it is a polled command, call the interrupt 2197 * routine until command is done. 2198 */ 2199 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2200 2201 /* Wait for at last 400ns for status bit to be valid */ 2202 DELAY(1); 2203 mvsata_atapi_intr(chp, xfer, 0); 2204 2205 if (!poll) 2206 return; 2207 2208 if (chp->ch_flags & ATACH_DMA_WAIT) { 2209 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2210 chp->ch_flags &= ~ATACH_DMA_WAIT; 2211 } 2212 2213 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2214 /* Wait for at last 400ns for status bit to be valid */ 2215 DELAY(1); 2216 mvsata_atapi_intr(chp, xfer, 0); 2217 } 2218 } 2219 2220 static int 2221 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2222 { 2223 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2224 struct atac_softc *atac = chp->ch_atac; 2225 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2226 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2227 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2228 int len, phase, ire, error, retries=0, i; 2229 int tfd; 2230 void *cmd; 2231 2232 ata_channel_lock(chp); 2233 2234 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2235 ("%s:%d:%d: mvsata_atapi_intr\n", 2236 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2237 2238 /* Is it not a transfer, but a control operation? */ 2239 if (drvp->state < READY) { 2240 aprint_error_dev(atac->atac_dev, 2241 "channel %d drive %d: bad state %d\n", 2242 chp->ch_channel, xfer->c_drive, drvp->state); 2243 panic("mvsata_atapi_intr: bad state"); 2244 } 2245 /* 2246 * If we missed an interrupt in a PIO transfer, reset and restart. 2247 * Don't try to continue transfer, we may have missed cycles. 2248 */ 2249 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2250 ata_channel_unlock(chp); 2251 sc_xfer->error = XS_TIMEOUT; 2252 mvsata_atapi_reset(chp, xfer); 2253 return 1; 2254 } 2255 2256 /* Ack interrupt done in wdc_wait_for_unbusy */ 2257 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2258 if (wdc_wait_for_unbusy(chp, 2259 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2260 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2261 ata_channel_unlock(chp); 2262 return 0; /* IRQ was not for us */ 2263 } 2264 aprint_error_dev(atac->atac_dev, 2265 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2266 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2267 if (xfer->c_flags & C_DMA) 2268 ata_dmaerr(drvp, 2269 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2270 sc_xfer->error = XS_TIMEOUT; 2271 ata_channel_unlock(chp); 2272 mvsata_atapi_reset(chp, xfer); 2273 return 1; 2274 } 2275 2276 /* 2277 * If we missed an IRQ and were using DMA, flag it as a DMA error 2278 * and reset device. 2279 */ 2280 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2281 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2282 sc_xfer->error = XS_RESET; 2283 ata_channel_unlock(chp); 2284 mvsata_atapi_reset(chp, xfer); 2285 return (1); 2286 } 2287 /* 2288 * if the request sense command was aborted, report the short sense 2289 * previously recorded, else continue normal processing 2290 */ 2291 2292 again: 2293 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2294 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2295 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2296 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2297 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2298 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2299 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2300 2301 switch (phase) { 2302 case PHASE_CMDOUT: 2303 cmd = sc_xfer->cmd; 2304 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2305 /* Init the DMA channel if necessary */ 2306 if (xfer->c_flags & C_DMA) { 2307 error = mvsata_bdma_init(mvport, xfer); 2308 if (error) { 2309 if (error == EINVAL) { 2310 /* 2311 * We can't do DMA on this transfer 2312 * for some reason. Fall back to PIO. 2313 */ 2314 xfer->c_flags &= ~C_DMA; 2315 error = 0; 2316 } else { 2317 sc_xfer->error = XS_DRIVER_STUFFUP; 2318 break; 2319 } 2320 } 2321 } 2322 2323 /* send packet command */ 2324 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2325 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2326 2327 /* Start the DMA channel if necessary */ 2328 if (xfer->c_flags & C_DMA) { 2329 mvsata_bdma_start(mvport); 2330 chp->ch_flags |= ATACH_DMA_WAIT; 2331 } 2332 ata_channel_unlock(chp); 2333 return 1; 2334 2335 case PHASE_DATAOUT: 2336 /* write data */ 2337 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2338 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2339 (xfer->c_flags & C_DMA) != 0) { 2340 aprint_error_dev(atac->atac_dev, 2341 "channel %d drive %d: bad data phase DATAOUT\n", 2342 chp->ch_channel, xfer->c_drive); 2343 if (xfer->c_flags & C_DMA) 2344 ata_dmaerr(drvp, 2345 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2346 sc_xfer->error = XS_TIMEOUT; 2347 ata_channel_unlock(chp); 2348 mvsata_atapi_reset(chp, xfer); 2349 return 1; 2350 } 2351 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2352 if (xfer->c_bcount < len) { 2353 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2354 " warning: write only %d of %d requested bytes\n", 2355 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2356 len); 2357 len = xfer->c_bcount; 2358 } 2359 2360 wdc->dataout_pio(chp, drvp->drive_flags, 2361 (char *)xfer->c_databuf + xfer->c_skip, len); 2362 2363 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 2364 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2365 2366 xfer->c_skip += len; 2367 xfer->c_bcount -= len; 2368 ata_channel_unlock(chp); 2369 return 1; 2370 2371 case PHASE_DATAIN: 2372 /* Read data */ 2373 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2374 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2375 (xfer->c_flags & C_DMA) != 0) { 2376 aprint_error_dev(atac->atac_dev, 2377 "channel %d drive %d: bad data phase DATAIN\n", 2378 chp->ch_channel, xfer->c_drive); 2379 if (xfer->c_flags & C_DMA) 2380 ata_dmaerr(drvp, 2381 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2382 ata_channel_unlock(chp); 2383 sc_xfer->error = XS_TIMEOUT; 2384 mvsata_atapi_reset(chp, xfer); 2385 return 1; 2386 } 2387 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2388 if (xfer->c_bcount < len) { 2389 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2390 " warning: reading only %d of %d bytes\n", 2391 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2392 len); 2393 len = xfer->c_bcount; 2394 } 2395 2396 wdc->datain_pio(chp, drvp->drive_flags, 2397 (char *)xfer->c_databuf + xfer->c_skip, len); 2398 2399 if (xfer->c_atapi.c_lenoff > 0) 2400 wdcbit_bucket(chp, len - xfer->c_bcount); 2401 2402 xfer->c_skip += len; 2403 xfer->c_bcount -= len; 2404 ata_channel_unlock(chp); 2405 return 1; 2406 2407 case PHASE_ABORTED: 2408 case PHASE_COMPLETED: 2409 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2410 if (xfer->c_flags & C_DMA) 2411 xfer->c_bcount -= sc_xfer->datalen; 2412 sc_xfer->resid = xfer->c_bcount; 2413 /* this will unlock channel lock too */ 2414 mvsata_atapi_phase_complete(xfer, tfd); 2415 return 1; 2416 2417 default: 2418 if (++retries<500) { 2419 DELAY(100); 2420 tfd = ATACH_ERR_ST( 2421 MVSATA_WDC_READ_1(mvport, SRB_FE), 2422 MVSATA_WDC_READ_1(mvport, SRB_CS) 2423 ); 2424 goto again; 2425 } 2426 aprint_error_dev(atac->atac_dev, 2427 "channel %d drive %d: unknown phase 0x%x\n", 2428 chp->ch_channel, xfer->c_drive, phase); 2429 if (ATACH_ST(tfd) & WDCS_ERR) { 2430 sc_xfer->error = XS_SHORTSENSE; 2431 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2432 } else { 2433 if (xfer->c_flags & C_DMA) 2434 ata_dmaerr(drvp, 2435 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2436 sc_xfer->error = XS_RESET; 2437 ata_channel_unlock(chp); 2438 mvsata_atapi_reset(chp, xfer); 2439 return (1); 2440 } 2441 } 2442 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2443 ("mvsata_atapi_intr: %s (end), error 0x%x " 2444 "sense 0x%x\n", __func__, 2445 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2446 ata_channel_unlock(chp); 2447 mvsata_atapi_done(chp, xfer); 2448 return 1; 2449 } 2450 2451 static void 2452 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2453 int reason) 2454 { 2455 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2456 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2457 bool deactivate = true; 2458 2459 /* remove this command from xfer queue */ 2460 switch (reason) { 2461 case KILL_GONE_INACTIVE: 2462 deactivate = false; 2463 /* FALLTHROUGH */ 2464 case KILL_GONE: 2465 sc_xfer->error = XS_DRIVER_STUFFUP; 2466 break; 2467 case KILL_RESET: 2468 sc_xfer->error = XS_RESET; 2469 break; 2470 case KILL_REQUEUE: 2471 sc_xfer->error = XS_REQUEUE; 2472 break; 2473 default: 2474 aprint_error_dev(MVSATA_DEV2(mvport), 2475 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2476 panic("mvsata_atapi_kill_xfer"); 2477 } 2478 2479 if (deactivate) 2480 ata_deactivate_xfer(chp, xfer); 2481 2482 ata_free_xfer(chp, xfer); 2483 scsipi_done(sc_xfer); 2484 } 2485 2486 static void 2487 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2488 { 2489 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2490 struct atac_softc *atac = chp->ch_atac; 2491 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2492 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2493 int tfd; 2494 2495 ata_channel_lock(chp); 2496 2497 mvsata_pmp_select(mvport, xfer->c_drive); 2498 2499 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2500 drvp->state = 0; 2501 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2502 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2503 chp->ch_channel, xfer->c_drive); 2504 sc_xfer->error = XS_SELTIMEOUT; 2505 } 2506 2507 ata_channel_unlock(chp); 2508 2509 mvsata_atapi_done(chp, xfer); 2510 return; 2511 } 2512 2513 static void 2514 mvsata_atapi_phase_complete(struct ata_xfer *xfer, int tfd) 2515 { 2516 struct ata_channel *chp = xfer->c_chp; 2517 struct atac_softc *atac = chp->ch_atac; 2518 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2519 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2520 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2521 2522 ata_channel_lock_owned(chp); 2523 2524 /* wait for DSC if needed */ 2525 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2526 DPRINTF(DEBUG_XFERS, 2527 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2528 device_xname(atac->atac_dev), chp->ch_channel, 2529 xfer->c_drive, xfer->c_atapi.c_dscpoll)); 2530 if (cold) 2531 panic("mvsata_atapi_phase_complete: cold"); 2532 2533 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2534 WDCWAIT_TOUT) { 2535 /* 10ms not enough, try again in 1 tick */ 2536 if (xfer->c_atapi.c_dscpoll++ > 2537 mstohz(sc_xfer->timeout)) { 2538 aprint_error_dev(atac->atac_dev, 2539 "channel %d: wait_for_dsc failed\n", 2540 chp->ch_channel); 2541 ata_channel_unlock(chp); 2542 sc_xfer->error = XS_TIMEOUT; 2543 mvsata_atapi_reset(chp, xfer); 2544 } else { 2545 callout_reset(&chp->c_timo_callout, 1, 2546 mvsata_atapi_polldsc, chp); 2547 ata_channel_unlock(chp); 2548 } 2549 return; 2550 } 2551 } 2552 2553 /* 2554 * Some drive occasionally set WDCS_ERR with 2555 * "ATA illegal length indication" in the error 2556 * register. If we read some data the sense is valid 2557 * anyway, so don't report the error. 2558 */ 2559 if (ATACH_ST(tfd) & WDCS_ERR && 2560 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2561 sc_xfer->resid == sc_xfer->datalen)) { 2562 /* save the short sense */ 2563 sc_xfer->error = XS_SHORTSENSE; 2564 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2565 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2566 /* ask scsipi to send a REQUEST_SENSE */ 2567 sc_xfer->error = XS_BUSY; 2568 sc_xfer->status = SCSI_CHECK; 2569 } else 2570 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2571 ata_dmaerr(drvp, 2572 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2573 sc_xfer->error = XS_RESET; 2574 ata_channel_unlock(chp); 2575 mvsata_atapi_reset(chp, xfer); 2576 return; 2577 } 2578 } 2579 if (xfer->c_bcount != 0) { 2580 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2581 " bcount value is %d after io\n", 2582 device_xname(atac->atac_dev), chp->ch_channel, 2583 xfer->c_drive, xfer->c_bcount)); 2584 } 2585 #ifdef DIAGNOSTIC 2586 if (xfer->c_bcount < 0) { 2587 aprint_error_dev(atac->atac_dev, 2588 "channel %d drive %d: mvsata_atapi_intr:" 2589 " warning: bcount value is %d after io\n", 2590 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2591 } 2592 #endif 2593 2594 DPRINTF(DEBUG_XFERS, 2595 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2596 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2597 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2598 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2599 ata_channel_unlock(chp); 2600 mvsata_atapi_done(chp, xfer); 2601 } 2602 2603 static void 2604 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2605 { 2606 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2607 bool iserror = (sc_xfer->error != XS_NOERROR); 2608 2609 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2610 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2611 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2612 xfer->c_drive, (u_int)xfer->c_flags)); 2613 2614 if (ata_waitdrain_xfer_check(chp, xfer)) 2615 return; 2616 2617 /* mark controller inactive and free the command */ 2618 ata_deactivate_xfer(chp, xfer); 2619 2620 ata_free_xfer(chp, xfer); 2621 2622 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2623 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2624 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2625 scsipi_done(sc_xfer); 2626 DPRINTF(DEBUG_FUNCS, 2627 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2628 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2629 chp->ch_flags)); 2630 if (!iserror) 2631 atastart(chp); 2632 } 2633 2634 static void 2635 mvsata_atapi_polldsc(void *arg) 2636 { 2637 struct ata_channel *chp = arg; 2638 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 2639 2640 KASSERT(xfer != NULL); 2641 2642 ata_channel_lock(chp); 2643 2644 /* this will unlock channel lock too */ 2645 mvsata_atapi_phase_complete(xfer, 0); 2646 } 2647 #endif /* NATAPIBUS > 0 */ 2648 2649 2650 /* 2651 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2652 * if supported queuing command by atabus? The race condition will not happen 2653 * if this is called only to the thread of atabus. 2654 */ 2655 static int 2656 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2657 { 2658 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2659 struct ata_bio *ata_bio = &xfer->c_bio; 2660 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2661 struct eprd *eprd; 2662 bus_addr_t crqb_base_addr; 2663 bus_dmamap_t data_dmamap; 2664 uint32_t reg; 2665 int erqqip, erqqop, next, rv, i; 2666 2667 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2668 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2669 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2670 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2671 2672 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2673 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2674 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2675 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2676 next = erqqip; 2677 MVSATA_EDMAQ_INC(next); 2678 if (next == erqqop) { 2679 /* queue full */ 2680 return EBUSY; 2681 } 2682 DPRINTF(DEBUG_XFERS, 2683 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2684 2685 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2686 ata_bio->flags); 2687 if (rv != 0) 2688 return rv; 2689 2690 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2691 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2692 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2693 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2694 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2695 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2696 2697 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2698 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2699 eprd->eot = htole16(0); 2700 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2701 eprd++; 2702 } 2703 (eprd - 1)->eot |= htole16(EPRD_EOT); 2704 #ifdef MVSATA_DEBUG 2705 if (mvsata_debug >= 3) 2706 mvsata_print_eprd(mvport, xfer->c_slot); 2707 #endif 2708 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2709 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2710 BUS_DMASYNC_PREWRITE); 2711 2712 /* setup EDMA Command Request Block (CRQB) Data */ 2713 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2714 #ifdef MVSATA_DEBUG 2715 if (mvsata_debug >= 3) 2716 mvsata_print_crqb(mvport, erqqip); 2717 #endif 2718 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2719 erqqip * sizeof(union mvsata_crqb), 2720 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2721 2722 MVSATA_EDMAQ_INC(erqqip); 2723 2724 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2725 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2726 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2727 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2728 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2729 2730 return 0; 2731 } 2732 2733 static int 2734 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2735 { 2736 struct ata_channel *chp = &mvport->port_ata_channel; 2737 struct crpb *crpb; 2738 struct ata_bio *ata_bio; 2739 struct ata_xfer *xfer; 2740 uint32_t reg; 2741 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2742 int st, dmaerr; 2743 2744 /* First, Sync for Request Queue buffer */ 2745 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2746 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2747 if (mvport->port_prev_erqqop != erqqop) { 2748 const int s = sizeof(union mvsata_crqb); 2749 2750 if (mvport->port_prev_erqqop < erqqop) 2751 n = erqqop - mvport->port_prev_erqqop; 2752 else { 2753 if (erqqop > 0) 2754 bus_dmamap_sync(mvport->port_dmat, 2755 mvport->port_crqb_dmamap, 0, erqqop * s, 2756 BUS_DMASYNC_POSTWRITE); 2757 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2758 } 2759 if (n > 0) 2760 bus_dmamap_sync(mvport->port_dmat, 2761 mvport->port_crqb_dmamap, 2762 mvport->port_prev_erqqop * s, n * s, 2763 BUS_DMASYNC_POSTWRITE); 2764 mvport->port_prev_erqqop = erqqop; 2765 } 2766 2767 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2768 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2769 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2770 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2771 2772 DPRINTF(DEBUG_XFERS, 2773 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2774 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2775 mvport->port, erpqip, erpqop)); 2776 2777 if (erpqop == erpqip) 2778 return 0; 2779 2780 if (erpqop < erpqip) 2781 n = erpqip - erpqop; 2782 else { 2783 if (erpqip > 0) 2784 bus_dmamap_sync(mvport->port_dmat, 2785 mvport->port_crpb_dmamap, 2786 0, erpqip * sizeof(struct crpb), 2787 BUS_DMASYNC_POSTREAD); 2788 n = MVSATA_EDMAQ_LEN - erpqop; 2789 } 2790 if (n > 0) 2791 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2792 erpqop * sizeof(struct crpb), 2793 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2794 2795 uint32_t aslots = ata_queue_active(chp); 2796 2797 prev_erpqop = erpqop; 2798 while (erpqop != erpqip) { 2799 #ifdef MVSATA_DEBUG 2800 if (mvsata_debug >= 3) 2801 mvsata_print_crpb(mvport, erpqop); 2802 #endif 2803 crpb = mvport->port_crpb + erpqop; 2804 MVSATA_EDMAQ_INC(erpqop); 2805 2806 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2807 2808 if ((aslots & __BIT(quetag)) == 0) { 2809 /* not actually executing */ 2810 continue; 2811 } 2812 2813 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2814 2815 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2816 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2817 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2818 2819 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2820 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2821 2822 ata_bio = &xfer->c_bio; 2823 ata_bio->error = NOERROR; 2824 if (dmaerr != 0) 2825 ata_bio->error = ERR_DMA; 2826 2827 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2828 2829 KASSERT(xfer->c_flags & C_DMA); 2830 mvsata_bio_intr(chp, xfer, ATACH_ERR_ST(0, st)); 2831 2832 if (xfer1 == NULL) 2833 handled++; 2834 else if (xfer == xfer1) { 2835 handled = 1; 2836 break; 2837 } 2838 } 2839 if (prev_erpqop < erpqop) 2840 n = erpqop - prev_erpqop; 2841 else { 2842 if (erpqop > 0) 2843 bus_dmamap_sync(mvport->port_dmat, 2844 mvport->port_crpb_dmamap, 0, 2845 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2846 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2847 } 2848 if (n > 0) 2849 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2850 prev_erpqop * sizeof(struct crpb), 2851 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2852 2853 reg &= ~EDMA_RESQP_ERPQP_MASK; 2854 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2855 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2856 2857 return handled; 2858 } 2859 2860 static int 2861 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2862 { 2863 int xtime; 2864 2865 for (xtime = 0; xtime < timeout * 10; xtime++) { 2866 if (mvsata_edma_handle(mvport, xfer)) 2867 return 0; 2868 DELAY(100); 2869 } 2870 2871 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2872 mvsata_edma_rqq_remove(mvport, xfer); 2873 xfer->c_flags |= C_TIMEOU; 2874 return 1; 2875 } 2876 2877 static void 2878 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2879 { 2880 struct ata_channel *chp = &mvport->port_ata_channel; 2881 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2882 bus_addr_t crqb_base_addr; 2883 int erqqip, i; 2884 2885 /* First, hardware reset, stop EDMA */ 2886 mvsata_hreset_port(mvport); 2887 2888 /* cleanup completed EDMA safely */ 2889 mvsata_edma_handle(mvport, NULL); 2890 2891 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2892 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2893 2894 uint32_t aslots = ata_queue_active(chp); 2895 2896 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2897 struct ata_xfer *rqxfer; 2898 2899 if ((aslots & __BIT(i)) == 0) 2900 continue; 2901 2902 if (i == xfer->c_slot) { 2903 /* remove xfer from EDMA request queue */ 2904 bus_dmamap_sync(mvport->port_dmat, 2905 mvport->port_eprd_dmamap, 2906 mvport->port_reqtbl[i].eprd_offset, 2907 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2908 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 2909 /* quetag freed by caller later */ 2910 continue; 2911 } 2912 2913 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 2914 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 2915 erqqip++; 2916 } 2917 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2918 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2919 BUS_DMASYNC_POSTWRITE); 2920 2921 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 2922 mvsata_edma_reset_qptr(mvport); 2923 mvsata_edma_enable(mvport); 2924 2925 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2926 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2927 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2928 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2929 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2930 } 2931 2932 #if NATAPIBUS > 0 2933 static int 2934 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 2935 { 2936 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2937 struct eprd *eprd; 2938 bus_dmamap_t data_dmamap; 2939 bus_addr_t eprd_addr; 2940 int i, rv; 2941 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2942 2943 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2944 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2945 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2946 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2947 2948 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 2949 sc_xfer->datalen, 2950 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2951 if (rv != 0) 2952 return rv; 2953 2954 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2955 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2956 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2957 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2958 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2959 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2960 2961 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2962 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2963 eprd->eot = htole16(0); 2964 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2965 eprd++; 2966 } 2967 (eprd - 1)->eot |= htole16(EPRD_EOT); 2968 #ifdef MVSATA_DEBUG 2969 if (mvsata_debug >= 3) 2970 mvsata_print_eprd(mvport, xfer->c_slot); 2971 #endif 2972 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2973 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2974 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 2975 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2976 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 2977 2978 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2979 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2980 2981 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2982 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2983 else 2984 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2985 2986 return 0; 2987 } 2988 2989 static void 2990 mvsata_bdma_start(struct mvsata_port *mvport) 2991 { 2992 2993 #ifdef MVSATA_DEBUG 2994 if (mvsata_debug >= 3) 2995 mvsata_print_eprd(mvport, 0); 2996 #endif 2997 2998 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2999 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 3000 } 3001 #endif 3002 #endif 3003 3004 3005 static int 3006 mvsata_port_init(struct mvsata_hc *mvhc, int port) 3007 { 3008 struct mvsata_softc *sc = mvhc->hc_sc; 3009 struct mvsata_port *mvport; 3010 struct ata_channel *chp; 3011 int channel, rv, i; 3012 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 3013 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 3014 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 3015 3016 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 3017 M_ZERO | M_WAITOK); 3018 mvport->port = port; 3019 mvport->port_hc = mvhc; 3020 mvport->port_edmamode_negotiated = nodma; 3021 3022 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3023 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3024 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3025 if (rv != 0) { 3026 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3027 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3028 goto fail0; 3029 } 3030 mvport->port_iot = mvhc->hc_iot; 3031 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3032 &mvport->port_sata_sstatus); 3033 if (rv != 0) { 3034 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3035 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3036 goto fail0; 3037 } 3038 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3039 &mvport->port_sata_serror); 3040 if (rv != 0) { 3041 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3042 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3043 goto fail0; 3044 } 3045 if (sc->sc_rev == gen1) 3046 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3047 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3048 else 3049 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3050 SATA_SC, 4, &mvport->port_sata_scontrol); 3051 if (rv != 0) { 3052 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3053 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3054 goto fail0; 3055 } 3056 mvport->port_dmat = sc->sc_dmat; 3057 mvhc->hc_ports[port] = mvport; 3058 3059 channel = mvhc->hc * sc->sc_port + port; 3060 chp = &mvport->port_ata_channel; 3061 chp->ch_channel = channel; 3062 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3063 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3064 sc->sc_ata_channels[channel] = chp; 3065 3066 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3067 if (rv != 0) 3068 goto fail0; 3069 3070 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3071 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3072 if (rv != 0) { 3073 aprint_error( 3074 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3075 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3076 goto fail0; 3077 } 3078 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3079 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3080 if (rv != 0) { 3081 aprint_error( 3082 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3083 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3084 goto fail1; 3085 } 3086 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3087 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3088 if (rv != 0) { 3089 aprint_error( 3090 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3091 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3092 goto fail2; 3093 } 3094 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3095 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3096 MVSATA_MAX_SEGS, MAXPHYS, 0, BUS_DMA_NOWAIT, 3097 &mvport->port_reqtbl[i].data_dmamap); 3098 if (rv != 0) { 3099 aprint_error("%s:%d:%d:" 3100 " EDMA data map(%d) create failed: error=%d\n", 3101 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3102 rv); 3103 goto fail3; 3104 } 3105 } 3106 3107 return 0; 3108 3109 fail3: 3110 for (i--; i >= 0; i--) 3111 bus_dmamap_destroy(mvport->port_dmat, 3112 mvport->port_reqtbl[i].data_dmamap); 3113 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3114 fail2: 3115 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3116 fail1: 3117 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3118 fail0: 3119 return rv; 3120 } 3121 3122 static int 3123 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3124 { 3125 int hc, port, rv, i; 3126 3127 hc = mvport->port_hc->hc; 3128 port = mvport->port; 3129 3130 /* Create subregion for Shadow Registers Map */ 3131 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3132 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3133 if (rv != 0) { 3134 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3135 device_xname(MVSATA_DEV2(mvport)), hc, port); 3136 return rv; 3137 } 3138 wdr->cmd_iot = mvport->port_iot; 3139 3140 /* Once create subregion for each command registers */ 3141 for (i = 0; i < WDC_NREG; i++) { 3142 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3143 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3144 if (rv != 0) { 3145 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3146 device_xname(MVSATA_DEV2(mvport)), hc, port); 3147 return rv; 3148 } 3149 } 3150 /* Create subregion for Alternate Status register */ 3151 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3152 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3153 if (rv != 0) { 3154 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3155 device_xname(MVSATA_DEV2(mvport)), hc, port); 3156 return rv; 3157 } 3158 wdr->ctl_iot = mvport->port_iot; 3159 3160 wdc_init_shadow_regs(wdr); 3161 3162 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3163 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3164 if (rv != 0) { 3165 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3166 device_xname(MVSATA_DEV2(mvport)), hc, port); 3167 return rv; 3168 } 3169 wdr->sata_iot = mvport->port_iot; 3170 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3171 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3172 if (rv != 0) { 3173 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3174 device_xname(MVSATA_DEV2(mvport)), hc, port); 3175 return rv; 3176 } 3177 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3178 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3179 if (rv != 0) { 3180 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3181 device_xname(MVSATA_DEV2(mvport)), hc, port); 3182 return rv; 3183 } 3184 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3185 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3186 if (rv != 0) { 3187 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3188 device_xname(MVSATA_DEV2(mvport)), hc, port); 3189 return rv; 3190 } 3191 3192 return 0; 3193 } 3194 3195 3196 #ifndef MVSATA_WITHOUTDMA 3197 static void * 3198 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3199 bus_dmamap_t *dmamap, size_t size, int write) 3200 { 3201 bus_dma_segment_t seg; 3202 int nseg, rv; 3203 void *kva; 3204 3205 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3206 BUS_DMA_NOWAIT); 3207 if (rv != 0) { 3208 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3209 device_xname(MVSATA_DEV2(mvport)), 3210 mvport->port_hc->hc, mvport->port, rv); 3211 goto fail; 3212 } 3213 3214 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3215 if (rv != 0) { 3216 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3217 device_xname(MVSATA_DEV2(mvport)), 3218 mvport->port_hc->hc, mvport->port, rv); 3219 goto free; 3220 } 3221 3222 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3223 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3224 if (rv != 0) { 3225 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3226 device_xname(MVSATA_DEV2(mvport)), 3227 mvport->port_hc->hc, mvport->port, rv); 3228 goto unmap; 3229 } 3230 3231 if (!write) 3232 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3233 3234 return kva; 3235 3236 unmap: 3237 bus_dmamem_unmap(dmat, kva, size); 3238 free: 3239 bus_dmamem_free(dmat, &seg, nseg); 3240 fail: 3241 return NULL; 3242 } 3243 3244 /* ARGSUSED */ 3245 static void 3246 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3247 bus_dmamap_t dmamap, void *kva) 3248 { 3249 3250 bus_dmamap_unload(dmat, dmamap); 3251 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3252 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3253 } 3254 3255 static int 3256 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3257 size_t datalen, int flags) 3258 { 3259 int rv, lop, sop; 3260 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3261 3262 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3263 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3264 3265 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3266 NULL, BUS_DMA_NOWAIT | lop); 3267 if (rv) { 3268 aprint_error("%s:%d:%d: buffer load failed: error=%d\n", 3269 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3270 mvport->port, rv); 3271 return rv; 3272 } 3273 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3274 data_dmamap->dm_mapsize, sop); 3275 3276 return 0; 3277 } 3278 3279 static inline void 3280 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3281 { 3282 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3283 3284 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3285 data_dmamap->dm_mapsize, 3286 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3287 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3288 } 3289 #endif 3290 3291 static void 3292 mvsata_hreset_port(struct mvsata_port *mvport) 3293 { 3294 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3295 3296 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3297 3298 delay(25); /* allow reset propagation */ 3299 3300 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3301 3302 mvport->_fix_phy_param._fix_phy(mvport); 3303 3304 if (sc->sc_gen == gen1) 3305 delay(1000); 3306 } 3307 3308 static void 3309 mvsata_reset_port(struct mvsata_port *mvport) 3310 { 3311 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3312 3313 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3314 3315 mvsata_hreset_port(mvport); 3316 3317 if (device_is_a(parent, "pci")) 3318 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3319 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3320 else /* SoC */ 3321 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3322 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3323 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3324 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3325 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3326 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3327 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3328 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3329 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3330 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3331 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3332 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3333 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3334 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3335 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3336 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3337 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3338 } 3339 3340 static void 3341 mvsata_reset_hc(struct mvsata_hc *mvhc) 3342 { 3343 #if 0 3344 uint32_t val; 3345 #endif 3346 3347 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3348 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3349 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3350 3351 #if 0 /* XXXX needs? */ 3352 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3353 3354 /* 3355 * Keep the SS during power on and the reference clock bits (reset 3356 * sample) 3357 */ 3358 val = MVSATA_HC_READ_4(mvhc, 0x020); 3359 val &= 0x1c1c1c1c; 3360 val |= 0x03030303; 3361 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3362 #endif 3363 } 3364 3365 static uint32_t 3366 mvsata_softreset(struct mvsata_port *mvport, int flags) 3367 { 3368 struct ata_channel *chp = &mvport->port_ata_channel; 3369 uint32_t sig0 = ~0; 3370 int timeout; 3371 uint8_t st0; 3372 3373 ata_channel_lock_owned(chp); 3374 3375 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3376 delay(10); 3377 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3378 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3379 delay(10); 3380 3381 /* wait for BSY to deassert */ 3382 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3383 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3384 3385 if ((st0 & WDCS_BSY) == 0) { 3386 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3387 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3388 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3389 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3390 goto out; 3391 } 3392 ata_delay(chp, 10, "atarst", flags); 3393 } 3394 3395 aprint_error("%s:%d:%d: %s: timeout\n", 3396 device_xname(MVSATA_DEV2(mvport)), 3397 mvport->port_hc->hc, mvport->port, __func__); 3398 3399 out: 3400 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3401 return sig0; 3402 } 3403 3404 #ifndef MVSATA_WITHOUTDMA 3405 static void 3406 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3407 { 3408 const bus_addr_t crpb_addr = 3409 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3410 const uint32_t crpb_addr_mask = 3411 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3412 3413 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3414 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3415 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3416 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3417 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3418 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3419 } 3420 3421 static inline void 3422 mvsata_edma_enable(struct mvsata_port *mvport) 3423 { 3424 3425 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3426 } 3427 3428 static int 3429 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3430 { 3431 struct ata_channel *chp = &mvport->port_ata_channel; 3432 uint32_t status, command; 3433 uint32_t idlestatus = EDMA_S_EDMAIDLE | EDMA_S_ECACHEEMPTY; 3434 int t; 3435 3436 ata_channel_lock_owned(chp); 3437 3438 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3439 3440 timeout = mstohz(timeout + hztoms(1) - 1); 3441 3442 for (t = 0; ; ++t) { 3443 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3444 if ((status & idlestatus) == idlestatus) 3445 break; 3446 if (t >= timeout) 3447 break; 3448 ata_delay(chp, hztoms(1), "mvsata_edma1", wflags); 3449 } 3450 if (t >= timeout) { 3451 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3452 device_xname(MVSATA_DEV2(mvport)), 3453 mvport->port_hc->hc, mvport->port); 3454 return EBUSY; 3455 } 3456 3457 /* The disable bit (eDsEDMA) is self negated. */ 3458 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3459 3460 for (t = 0; ; ++t) { 3461 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3462 if (!(command & EDMA_CMD_EENEDMA)) 3463 break; 3464 if (t >= timeout) 3465 break; 3466 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3467 } 3468 if (t >= timeout) { 3469 aprint_error("%s:%d:%d: unable to re-enable EDMA\n", 3470 device_xname(MVSATA_DEV2(mvport)), 3471 mvport->port_hc->hc, mvport->port); 3472 return EBUSY; 3473 } 3474 } 3475 return 0; 3476 } 3477 3478 /* 3479 * Set EDMA registers according to mode. 3480 * ex. NCQ/TCQ(queued)/non queued. 3481 */ 3482 static void 3483 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3484 { 3485 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3486 uint32_t reg; 3487 3488 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3489 reg |= EDMA_CFG_RESERVED; 3490 3491 if (mode == ncq) { 3492 if (sc->sc_gen == gen1) { 3493 aprint_error_dev(MVSATA_DEV2(mvport), 3494 "GenI not support NCQ\n"); 3495 return; 3496 } else if (sc->sc_gen == gen2) 3497 reg |= EDMA_CFG_EDEVERR; 3498 reg |= EDMA_CFG_ESATANATVCMDQUE; 3499 } else if (mode == queued) { 3500 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3501 reg |= EDMA_CFG_EQUE; 3502 } else 3503 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3504 3505 if (sc->sc_gen == gen1) 3506 reg |= EDMA_CFG_ERDBSZ; 3507 else if (sc->sc_gen == gen2) 3508 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3509 else if (sc->sc_gen == gen2e) { 3510 device_t parent = device_parent(MVSATA_DEV(sc)); 3511 3512 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3513 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3514 3515 if (device_is_a(parent, "pci")) 3516 reg |= ( 3517 #if NATAPIBUS > 0 3518 EDMA_CFG_EEARLYCOMPLETIONEN | 3519 #endif 3520 EDMA_CFG_ECUTTHROUGHEN | 3521 EDMA_CFG_EWRBUFFERLEN | 3522 EDMA_CFG_ERDBSZEXT); 3523 } 3524 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3525 3526 reg = ( 3527 EDMA_IE_EIORDYERR | 3528 EDMA_IE_ETRANSINT | 3529 EDMA_IE_EDEVCON | 3530 EDMA_IE_EDEVDIS); 3531 if (sc->sc_gen != gen1) 3532 reg |= ( 3533 EDMA_IE_TRANSPROTERR | 3534 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3535 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3536 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3537 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3538 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3539 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3540 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3541 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3542 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3543 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3544 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3545 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3546 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3547 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3548 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3549 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3550 EDMA_IE_ESELFDIS); 3551 3552 if (mode == ncq) 3553 reg |= EDMA_IE_EDEVERR; 3554 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3555 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3556 reg &= ~EDMA_IE_EDEVERR; 3557 if (mode != ncq) 3558 reg |= EDMA_IE_EDEVERR; 3559 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3560 if (sc->sc_gen == gen2e) { 3561 /* 3562 * Clear FISWait4HostRdyEn[0] and [2]. 3563 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3564 * [2]: SDB FIS is received with <ERR> bit set to 1. 3565 */ 3566 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3567 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3568 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3569 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3570 } 3571 3572 mvport->port_edmamode_curr = mode; 3573 } 3574 3575 3576 /* 3577 * Generation dependent functions 3578 */ 3579 3580 static void 3581 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3582 struct ata_xfer *xfer) 3583 { 3584 struct crqb *crqb; 3585 bus_addr_t eprd_addr; 3586 daddr_t blkno; 3587 uint32_t rw; 3588 uint8_t cmd, head; 3589 int i; 3590 struct ata_bio *ata_bio = &xfer->c_bio; 3591 3592 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3593 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3594 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3595 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3596 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3597 head = WDSD_LBA; 3598 } else { 3599 head = 0; 3600 } 3601 blkno = ata_bio->blkno; 3602 if (ata_bio->flags & ATA_LBA48) 3603 cmd = atacmd_to48(cmd); 3604 else { 3605 head |= ((ata_bio->blkno >> 24) & 0xf); 3606 blkno &= 0xffffff; 3607 } 3608 crqb = &mvport->port_crqb->crqb + erqqip; 3609 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3610 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3611 crqb->ctrlflg = 3612 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3613 CRQB_CPMPORT(xfer->c_drive)); 3614 i = 0; 3615 if (mvport->port_edmamode_curr == dma) { 3616 if (ata_bio->flags & ATA_LBA48) 3617 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3618 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3619 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3620 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3621 } else { /* ncq/queued */ 3622 3623 /* 3624 * XXXX: Oops, ata command is not correct. And, atabus layer 3625 * has not been supported yet now. 3626 * Queued DMA read/write. 3627 * read/write FPDMAQueued. 3628 */ 3629 3630 if (ata_bio->flags & ATA_LBA48) 3631 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3632 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3633 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3634 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3635 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3636 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3637 } 3638 if (ata_bio->flags & ATA_LBA48) { 3639 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3640 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3641 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3642 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3643 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3644 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3645 } 3646 crqb->atacommand[i++] = 3647 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3648 crqb->atacommand[i++] = 3649 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3650 crqb->atacommand[i++] = 3651 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3652 crqb->atacommand[i++] = 3653 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3654 crqb->atacommand[i++] = htole16( 3655 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3656 CRQB_ATACOMMAND_LAST); 3657 } 3658 #endif 3659 3660 static uint32_t 3661 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3662 { 3663 struct mvsata_hc *hc = mvport->port_hc; 3664 uint32_t reg; 3665 3666 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3667 /* 3668 * [12:11] : pre 3669 * [7:5] : amps 3670 */ 3671 return reg & 0x000018e0; 3672 } 3673 3674 static void 3675 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3676 { 3677 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3678 struct mvsata_hc *mvhc = mvport->port_hc; 3679 uint32_t reg; 3680 int port = mvport->port, fix_apm_sq = 0; 3681 3682 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3683 if (sc->sc_rev == 0x01) 3684 fix_apm_sq = 1; 3685 } else { 3686 if (sc->sc_rev == 0x00) 3687 fix_apm_sq = 1; 3688 } 3689 3690 if (fix_apm_sq) { 3691 /* 3692 * Disable auto-power management 3693 * 88SX50xx FEr SATA#12 3694 */ 3695 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3696 reg |= (1 << 19); 3697 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3698 3699 /* 3700 * Fix squelch threshold 3701 * 88SX50xx FEr SATA#9 3702 */ 3703 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3704 reg &= ~0x3; 3705 reg |= 0x1; 3706 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3707 } 3708 3709 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3710 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3711 reg &= ~0x000018e0; /* pre and amps mask */ 3712 reg |= mvport->_fix_phy_param.pre_amps; 3713 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3714 } 3715 3716 static void 3717 mvsata_devconn_gen1(struct mvsata_port *mvport) 3718 { 3719 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3720 3721 /* Fix for 88SX50xx FEr SATA#2 */ 3722 mvport->_fix_phy_param._fix_phy(mvport); 3723 3724 /* If disk is connected, then enable the activity LED */ 3725 if (sc->sc_rev == 0x03) { 3726 /* XXXXX */ 3727 } 3728 } 3729 3730 static uint32_t 3731 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3732 { 3733 uint32_t reg; 3734 3735 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3736 /* 3737 * [10:8] : amps 3738 * [7:5] : pre 3739 */ 3740 return reg & 0x000007e0; 3741 } 3742 3743 static void 3744 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3745 { 3746 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3747 uint32_t reg; 3748 3749 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3750 sc->sc_gen == gen2e) { 3751 /* 3752 * Fix for 3753 * 88SX60X1 FEr SATA #23 3754 * 88SX6042/88SX7042 FEr SATA #23 3755 * 88F5182 FEr #SATA-S13 3756 * 88F5082 FEr #SATA-S13 3757 */ 3758 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3759 reg &= ~(1 << 16); 3760 reg |= (1 << 31); 3761 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3762 3763 delay(200); 3764 3765 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3766 reg &= ~((1 << 16) | (1 << 31)); 3767 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3768 3769 delay(200); 3770 } 3771 3772 /* Fix values in PHY Mode 3 Register.*/ 3773 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3774 reg &= ~0x7F900000; 3775 reg |= 0x2A800000; 3776 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3777 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3778 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3779 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3780 reg &= ~0x0000001c; 3781 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3782 3783 /* 3784 * Fix values in PHY Mode 4 Register. 3785 * 88SX60x1 FEr SATA#10 3786 * 88F5182 GL #SATA-S10 3787 * 88F5082 GL #SATA-S10 3788 */ 3789 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3790 sc->sc_gen == gen2e) { 3791 uint32_t tmp = 0; 3792 3793 /* 88SX60x1 FEr SATA #13 */ 3794 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3795 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3796 3797 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3798 reg |= (1 << 0); 3799 reg &= ~(1 << 1); 3800 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3801 if (sc->sc_gen == gen2e) { 3802 reg &= ~0x5de3fffc; 3803 reg |= (1 << 2); 3804 } 3805 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3806 3807 /* 88SX60x1 FEr SATA #13 */ 3808 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3809 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3810 } 3811 3812 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3813 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3814 reg &= ~0x000007e0; /* pre and amps mask */ 3815 reg |= mvport->_fix_phy_param.pre_amps; 3816 reg &= ~(1 << 16); 3817 if (sc->sc_gen == gen2e) { 3818 /* 3819 * according to mvSata 3.6.1, some IIE values are fixed. 3820 * some reserved fields must be written with fixed values. 3821 */ 3822 reg &= ~0xC30FF01F; 3823 reg |= 0x0000900F; 3824 } 3825 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3826 } 3827 3828 #ifndef MVSATA_WITHOUTDMA 3829 static void 3830 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3831 struct ata_xfer *xfer) 3832 { 3833 struct crqb_gen2e *crqb; 3834 bus_addr_t eprd_addr; 3835 uint32_t ctrlflg, rw; 3836 uint8_t fis[RHD_FISLEN]; 3837 3838 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3839 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3840 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3841 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3842 CRQB_CPMPORT(xfer->c_drive) | 3843 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3844 3845 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3846 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3847 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3848 crqb->ctrlflg = htole32(ctrlflg); 3849 3850 satafis_rhd_construct_bio(xfer, fis); 3851 3852 crqb->atacommand[0] = 0; 3853 crqb->atacommand[1] = 0; 3854 /* copy over the ATA command part of the fis */ 3855 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3856 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3857 } 3858 3859 #ifdef MVSATA_DEBUG 3860 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3861 do { \ 3862 int _i; \ 3863 u_char *_p = (p); \ 3864 \ 3865 printf(#type "(%d)", (n)); \ 3866 for (_i = 0; _i < (size); _i++, _p++) { \ 3867 if (_i % 16 == 0) \ 3868 printf("\n "); \ 3869 printf(" %02x", *_p); \ 3870 } \ 3871 printf("\n"); \ 3872 } while (0 /* CONSTCOND */) 3873 3874 static void 3875 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3876 { 3877 3878 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3879 n, (u_char *)(mvport->port_crqb + n)); 3880 } 3881 3882 static void 3883 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3884 { 3885 3886 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3887 n, (u_char *)(mvport->port_crpb + n)); 3888 } 3889 3890 static void 3891 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3892 { 3893 struct eprd *eprd; 3894 int i = 0; 3895 3896 eprd = mvport->port_reqtbl[n].eprd; 3897 while (1 /*CONSTCOND*/) { 3898 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3899 i, (u_char *)eprd); 3900 if (eprd->eot & EPRD_EOT) 3901 break; 3902 eprd++; 3903 i++; 3904 } 3905 } 3906 #endif 3907 #endif 3908
Indexes created Mon Sep 22 05:09:51 GMT 2025