mvsata.c revision 1.5
1 /* $NetBSD: mvsata.c,v 1.5 2010/07/13 12:53:42 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.5 2010/07/13 12:53:42 kiyohara Exp $"); 30 31 #include "opt_mvsata.h" 32 33 /* ATAPI implementation not finished. Also don't work shadow registers? */ 34 //#include "atapibus.h" 35 36 #include <sys/param.h> 37 #if NATAPIBUS > 0 38 #include <sys/buf.h> 39 #endif 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/disklabel.h> 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 49 #include <machine/vmparam.h> 50 51 #include <dev/ata/atareg.h> 52 #include <dev/ata/atavar.h> 53 #include <dev/ic/wdcvar.h> 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 57 #if NATAPIBUS > 0 58 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 59 #endif 60 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ic/mvsatareg.h> 64 #include <dev/ic/mvsatavar.h> 65 66 67 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 68 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 69 70 #define MVSATA_HC_READ_4(hc, reg) \ 71 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 72 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 73 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 74 #define MVSATA_EDMA_READ_4(mvport, reg) \ 75 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 76 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 77 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 78 #define MVSATA_WDC_READ_2(mvport, reg) \ 79 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, (reg)) 80 #define MVSATA_WDC_READ_1(mvport, reg) \ 81 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, (reg)) 82 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 83 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 84 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 85 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 86 87 #ifdef MVSATA_DEBUG 88 #define DPRINTF(x) if (mvsata_debug) printf x 89 #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x 90 int mvsata_debug = 3; 91 #else 92 #define DPRINTF(x) 93 #define DPRINTFN(n,x) 94 #endif 95 96 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 97 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 98 sending a cmd */ 99 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 100 101 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 102 103 104 #ifndef MVSATA_WITHOUTDMA 105 static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *); 106 static void mvsata_reset_drive(struct ata_drive_datas *, int); 107 static void mvsata_reset_channel(struct ata_channel *, int); 108 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *); 109 static int mvsata_addref(struct ata_drive_datas *); 110 static void mvsata_delref(struct ata_drive_datas *); 111 static void mvsata_killpending(struct ata_drive_datas *); 112 113 #if NATAPIBUS > 0 114 static void mvsata_atapibus_attach(struct atabus_softc *); 115 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 116 scsipi_adapter_req_t, void *); 117 static void mvsata_atapi_minphys(struct buf *); 118 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 119 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 120 #endif 121 #endif 122 123 static void mvsata_setup_channel(struct ata_channel *); 124 125 #ifndef MVSATA_WITHOUTDMA 126 static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 127 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 128 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 129 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 130 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 131 int); 132 static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 133 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 134 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 135 int); 136 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 137 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 138 #if NATAPIBUS > 0 139 static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 140 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 141 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 142 int); 143 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 144 static void mvsata_atapi_phase_complete(struct ata_xfer *); 145 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_atapi_polldsc(void *); 147 #endif 148 149 static int mvsata_edma_inqueue(struct mvsata_port *, struct ata_bio *, void *); 150 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 151 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 152 static void mvsata_edma_timeout(void *); 153 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 154 #if NATAPIBUS > 0 155 static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *); 156 static void mvsata_bdma_start(struct mvsata_port *); 157 #endif 158 #endif 159 160 static int mvsata_port_init(struct mvsata_hc *, int); 161 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 162 #ifndef MVSATA_WITHOUTDMA 163 static inline void mvsata_quetag_init(struct mvsata_port *); 164 static inline int mvsata_quetag_get(struct mvsata_port *); 165 static inline void mvsata_quetag_put(struct mvsata_port *, int); 166 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 167 bus_dmamap_t *, size_t, int); 168 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 169 bus_dmamap_t, void *); 170 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 171 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 172 #endif 173 174 static void mvsata_hreset_port(struct mvsata_port *); 175 static void mvsata_reset_port(struct mvsata_port *); 176 static void mvsata_reset_hc(struct mvsata_hc *); 177 #ifndef MVSATA_WITHOUTDMA 178 static void mvsata_softreset(struct mvsata_port *, int); 179 static void mvsata_edma_reset_qptr(struct mvsata_port *); 180 static inline void mvsata_edma_enable(struct mvsata_port *); 181 static int mvsata_edma_disable(struct mvsata_port *, int, int); 182 static void mvsata_edma_config(struct mvsata_port *, int); 183 184 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int, 185 struct ata_bio *); 186 #endif 187 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 188 static void mvsata_fix_phy_gen1(struct mvsata_port *); 189 static void mvsata_devconn_gen1(struct mvsata_port *); 190 191 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 192 static void mvsata_fix_phy_gen2(struct mvsata_port *); 193 #ifndef MVSATA_WITHOUTDMA 194 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int, 195 struct ata_bio *); 196 197 #ifdef MVSATA_DEBUG 198 static void mvsata_print_crqb(struct mvsata_port *, int); 199 static void mvsata_print_crpb(struct mvsata_port *, int); 200 static void mvsata_print_eprd(struct mvsata_port *, int); 201 #endif 202 #endif 203 204 205 #ifndef MVSATA_WITHOUTDMA 206 struct ata_bustype mvsata_ata_bustype = { 207 SCSIPI_BUSTYPE_ATA, 208 mvsata_bio, 209 mvsata_reset_drive, 210 mvsata_reset_channel, 211 mvsata_exec_command, 212 ata_get_params, 213 mvsata_addref, 214 mvsata_delref, 215 mvsata_killpending 216 }; 217 218 #if NATAPIBUS > 0 219 static const struct scsipi_bustype mvsata_atapi_bustype = { 220 SCSIPI_BUSTYPE_ATAPI, 221 atapi_scsipi_cmd, 222 atapi_interpret_sense, 223 atapi_print_addr, 224 mvsata_atapi_kill_pending, 225 }; 226 #endif /* NATAPIBUS */ 227 #endif 228 229 230 int 231 mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product, 232 int (*mvsata_sreset)(struct mvsata_softc *), 233 int (*mvsata_misc_reset)(struct mvsata_softc *), 234 int read_pre_amps) 235 { 236 struct mvsata_hc *mvhc; 237 struct mvsata_port *mvport; 238 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 239 void (*_fix_phy)(struct mvsata_port *) = NULL; 240 #ifndef MVSATA_WITHOUTDMA 241 void (*edma_setup_crqb) 242 (struct mvsata_port *, int, int, struct ata_bio *) = NULL; 243 #endif 244 int hc, port, channel; 245 246 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 247 (product->generation == gen1) ? "I" : 248 ((product->generation == gen2) ? "II" : "IIe"), 249 product->hc, product->port); 250 251 252 switch (product->generation) { 253 case gen1: 254 mvsata_sreset = NULL; 255 read_pre_amps = 1; /* MUST */ 256 read_preamps = mvsata_read_preamps_gen1; 257 _fix_phy = mvsata_fix_phy_gen1; 258 #ifndef MVSATA_WITHOUTDMA 259 edma_setup_crqb = mvsata_edma_setup_crqb; 260 #endif 261 break; 262 263 case gen2: 264 read_preamps = mvsata_read_preamps_gen2; 265 _fix_phy = mvsata_fix_phy_gen2; 266 #ifndef MVSATA_WITHOUTDMA 267 edma_setup_crqb = mvsata_edma_setup_crqb; 268 #endif 269 break; 270 271 case gen2e: 272 read_preamps = mvsata_read_preamps_gen2; 273 _fix_phy = mvsata_fix_phy_gen2; 274 #ifndef MVSATA_WITHOUTDMA 275 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 276 #endif 277 break; 278 } 279 280 sc->sc_gen = product->generation; 281 sc->sc_hc = product->hc; 282 sc->sc_port = product->port; 283 sc->sc_flags = product->flags; 284 285 #ifdef MVSATA_WITHOUTDMA 286 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 287 #else 288 sc->sc_edma_setup_crqb = edma_setup_crqb; 289 sc->sc_wdcdev.sc_atac.atac_cap |= 290 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 291 #endif 292 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 293 #ifndef MVSATA_WITHOUTDMA 294 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 295 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 296 #else 297 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 298 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 299 #endif 300 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 301 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 302 #ifndef MVSATA_WITHOUTDMA 303 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 304 #if NATAPIBUS > 0 305 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 306 #endif 307 #endif 308 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 309 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 310 311 sc->sc_wdc_regs = 312 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 313 M_DEVBUF, M_NOWAIT); 314 if (sc->sc_wdc_regs == NULL) { 315 aprint_error_dev(MVSATA_DEV(sc), 316 "can't allocate wdc regs memory\n"); 317 return ENOMEM; 318 } 319 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 320 321 for (hc = 0; hc < sc->sc_hc; hc++) { 322 mvhc = &sc->sc_hcs[hc]; 323 mvhc->hc = hc; 324 mvhc->hc_sc = sc; 325 mvhc->hc_iot = sc->sc_iot; 326 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 327 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 328 &mvhc->hc_ioh)) { 329 aprint_error_dev(MVSATA_DEV(sc), 330 "can't subregion SATAHC %d registers\n", hc); 331 continue; 332 } 333 334 for (port = 0; port < sc->sc_port; port++) 335 if (mvsata_port_init(mvhc, port) == 0) { 336 int pre_amps; 337 338 mvport = mvhc->hc_ports[port]; 339 pre_amps = read_pre_amps ? 340 read_preamps(mvport) : 0x00000720; 341 mvport->_fix_phy_param.pre_amps = pre_amps; 342 mvport->_fix_phy_param._fix_phy = _fix_phy; 343 344 if (!mvsata_sreset) 345 mvsata_reset_port(mvport); 346 } 347 348 if (!mvsata_sreset) 349 mvsata_reset_hc(mvhc); 350 } 351 if (mvsata_sreset) 352 mvsata_sreset(sc); 353 354 if (mvsata_misc_reset) 355 mvsata_misc_reset(sc); 356 357 for (hc = 0; hc < sc->sc_hc; hc++) 358 for (port = 0; port < sc->sc_port; port++) { 359 mvport = sc->sc_hcs[hc].hc_ports[port]; 360 if (mvport == NULL) 361 continue; 362 if (mvsata_sreset) 363 mvport->_fix_phy_param._fix_phy(mvport); 364 } 365 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 366 wdcattach(sc->sc_ata_channels[channel]); 367 368 return 0; 369 } 370 371 int 372 mvsata_intr(struct mvsata_hc *mvhc) 373 { 374 struct mvsata_softc *sc = mvhc->hc_sc; 375 struct mvsata_port *mvport; 376 uint32_t cause; 377 int port, handled = 0; 378 379 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 380 381 DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n", 382 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 383 384 if (cause & SATAHC_IC_SAINTCOAL) 385 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 386 cause &= ~SATAHC_IC_SAINTCOAL; 387 for (port = 0; port < sc->sc_port; port++) { 388 mvport = mvhc->hc_ports[port]; 389 390 if (cause & SATAHC_IC_DONE(port)) { 391 #ifndef MVSATA_WITHOUTDMA 392 handled = mvsata_edma_handle(mvport, NULL); 393 #endif 394 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 395 ~SATAHC_IC_DONE(port)); 396 } 397 398 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 399 wdcintr(&mvport->port_ata_channel); 400 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 401 ~SATAHC_IC_SADEVINTERRUPT(port)); 402 handled = 1; 403 } 404 } 405 406 return handled; 407 } 408 409 int 410 mvsata_error(struct mvsata_port *mvport) 411 { 412 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 413 uint32_t cause; 414 int handled = 0; 415 416 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 417 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 418 419 DPRINTFN(3, ("%s:%d:%d:" 420 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 421 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 422 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 423 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 424 425 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 426 if (!cause) 427 return 0; 428 429 /* If PM connected, connect/disconnect interrupts storm could happen */ 430 if (MVSATA_EDMA_READ_4(mvport, EDMA_IEC) & 431 (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) 432 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 433 delay(20 * 1000); 434 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 435 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 436 } 437 438 if (cause & EDMA_IE_EDEVDIS) 439 aprint_normal("%s:%d:%d: device disconnect\n", 440 device_xname(MVSATA_DEV2(mvport)), 441 mvport->port_hc->hc, mvport->port); 442 if (cause & EDMA_IE_EDEVCON) { 443 if (sc->sc_gen == gen1) 444 mvsata_devconn_gen1(mvport); 445 446 DPRINTFN(3, (" device connected\n")); 447 handled = 1; 448 } 449 #ifndef MVSATA_WITHOUTDMA 450 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 451 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 452 switch (mvport->port_edmamode) { 453 case dma: 454 case queued: 455 case ncq: 456 mvsata_edma_reset_qptr(mvport); 457 mvsata_edma_enable(mvport); 458 if (cause & EDMA_IE_EDEVERR) 459 break; 460 461 /* FALLTHROUGH */ 462 463 case nodma: 464 default: 465 aprint_error( 466 "%s:%d:%d: EDMA self disable happen 0x%x\n", 467 device_xname(MVSATA_DEV2(mvport)), 468 mvport->port_hc->hc, mvport->port, cause); 469 break; 470 } 471 handled = 1; 472 } 473 #endif 474 if (cause & EDMA_IE_ETRANSINT) { 475 /* hot plug the Port Multiplier */ 476 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 477 device_xname(MVSATA_DEV2(mvport)), 478 mvport->port_hc->hc, mvport->port); 479 } 480 481 return handled; 482 } 483 484 485 /* 486 * ATA callback entry points 487 */ 488 489 #ifndef MVSATA_WITHOUTDMA 490 static int 491 mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 492 { 493 struct ata_channel *chp = drvp->chnl_softc; 494 struct atac_softc *atac = chp->ch_atac; 495 struct ata_xfer *xfer; 496 497 DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%lld, bcount=%ld\n", 498 device_xname(atac->atac_dev), chp->ch_channel, drvp->drive, 499 ata_bio->blkno, ata_bio->bcount)); 500 501 xfer = ata_get_xfer(ATAXF_NOSLEEP); 502 if (xfer == NULL) 503 return ATACMD_TRY_AGAIN; 504 if (atac->atac_cap & ATAC_CAP_NOIRQ) 505 ata_bio->flags |= ATA_POLL; 506 if (ata_bio->flags & ATA_POLL) 507 xfer->c_flags |= C_POLL; 508 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 509 (ata_bio->flags & ATA_SINGLE) == 0) 510 xfer->c_flags |= C_DMA; 511 xfer->c_drive = drvp->drive; 512 xfer->c_cmd = ata_bio; 513 xfer->c_databuf = ata_bio->databuf; 514 xfer->c_bcount = ata_bio->bcount; 515 xfer->c_start = mvsata_bio_start; 516 xfer->c_intr = mvsata_bio_intr; 517 xfer->c_kill_xfer = mvsata_bio_kill_xfer; 518 ata_exec_xfer(chp, xfer); 519 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 520 } 521 522 static void 523 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags) 524 { 525 struct ata_channel *chp = drvp->chnl_softc; 526 struct mvsata_port *mvport = (struct mvsata_port *)chp; 527 uint32_t edma_c; 528 529 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 530 531 DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 532 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 533 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 534 535 if (edma_c & EDMA_CMD_EENEDMA) 536 mvsata_edma_disable(mvport, 10000, flags & AT_WAIT); 537 538 mvsata_softreset(mvport, flags & AT_WAIT); 539 540 if (edma_c & EDMA_CMD_EENEDMA) { 541 mvsata_edma_reset_qptr(mvport); 542 mvsata_edma_enable(mvport); 543 } 544 return; 545 } 546 547 static void 548 mvsata_reset_channel(struct ata_channel *chp, int flags) 549 { 550 struct mvsata_port *mvport = (struct mvsata_port *)chp; 551 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 552 struct ata_xfer *xfer; 553 uint32_t sstat, ctrl; 554 int i; 555 556 DPRINTF(("%s: mvsata_reset_channel: channel=%d\n", 557 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 558 559 mvsata_hreset_port(mvport); 560 sstat = sata_reset_interface(chp, mvport->port_iot, 561 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 562 563 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 564 sc->sc_gen != gen1) { 565 /* Downgrade to GenI */ 566 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 567 SControl_DET_DISABLE; 568 569 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 570 571 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 572 ctrl &= ~(1 << 17); /* Disable GenII */ 573 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 574 575 mvsata_hreset_port(mvport); 576 sata_reset_interface(chp, mvport->port_iot, 577 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 578 } 579 580 for (i = 0; MVSATA_EDMAQ_LEN; i++) { 581 xfer = mvport->port_reqtbl[i].xfer; 582 if (xfer == NULL) 583 continue; 584 chp->ch_queue->active_xfer = xfer; 585 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 586 } 587 588 mvsata_edma_config(mvport, mvport->port_edmamode); 589 mvsata_edma_reset_qptr(mvport); 590 mvsata_edma_enable(mvport); 591 return; 592 } 593 594 595 static int 596 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 597 { 598 struct ata_channel *chp = drvp->chnl_softc; 599 #ifdef MVSATA_DEBUG 600 struct mvsata_port *mvport = (struct mvsata_port *)chp; 601 #endif 602 struct ata_xfer *xfer; 603 int rv, s; 604 605 DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 606 " r_command=0x%x, r_head=0x%x, r_cyl=0x%x, r_sector=0x%x," 607 " r_count=0x%x, r_features=0x%x\n", 608 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 609 drvp->drive, ata_c->bcount, ata_c->r_command, ata_c->r_head, 610 ata_c->r_cyl, ata_c->r_sector, ata_c->r_count, ata_c->r_features)); 611 612 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 613 ATAXF_NOSLEEP); 614 if (xfer == NULL) 615 return ATACMD_TRY_AGAIN; 616 if (ata_c->flags & AT_POLL) 617 xfer->c_flags |= C_POLL; 618 if (ata_c->flags & AT_WAIT) 619 xfer->c_flags |= C_WAIT; 620 xfer->c_drive = drvp->drive; 621 xfer->c_databuf = ata_c->data; 622 xfer->c_bcount = ata_c->bcount; 623 xfer->c_cmd = ata_c; 624 xfer->c_start = mvsata_wdc_cmd_start; 625 xfer->c_intr = mvsata_wdc_cmd_intr; 626 xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer; 627 s = splbio(); 628 ata_exec_xfer(chp, xfer); 629 #ifdef DIAGNOSTIC 630 if ((ata_c->flags & AT_POLL) != 0 && 631 (ata_c->flags & AT_DONE) == 0) 632 panic("mvsata_exec_command: polled command not done"); 633 #endif 634 if (ata_c->flags & AT_DONE) 635 rv = ATACMD_COMPLETE; 636 else { 637 if (ata_c->flags & AT_WAIT) { 638 while ((ata_c->flags & AT_DONE) == 0) 639 tsleep(ata_c, PRIBIO, "mvsatacmd", 0); 640 rv = ATACMD_COMPLETE; 641 } else 642 rv = ATACMD_QUEUED; 643 } 644 splx(s); 645 return rv; 646 } 647 648 static int 649 mvsata_addref(struct ata_drive_datas *drvp) 650 { 651 652 return 0; 653 } 654 655 static void 656 mvsata_delref(struct ata_drive_datas *drvp) 657 { 658 659 return; 660 } 661 662 static void 663 mvsata_killpending(struct ata_drive_datas *drvp) 664 { 665 666 return; 667 } 668 669 #if NATAPIBUS > 0 670 static void 671 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 672 { 673 struct ata_channel *chp = ata_sc->sc_chan; 674 struct atac_softc *atac = chp->ch_atac; 675 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 676 struct scsipi_channel *chan = &chp->ch_atapi_channel; 677 678 /* 679 * Fill in the scsipi_adapter. 680 */ 681 adapt->adapt_dev = atac->atac_dev; 682 adapt->adapt_nchannels = atac->atac_nchannels; 683 adapt->adapt_request = mvsata_atapi_scsipi_request; 684 adapt->adapt_minphys = mvsata_atapi_minphys; 685 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 686 687 /* 688 * Fill in the scsipi_channel. 689 */ 690 memset(chan, 0, sizeof(*chan)); 691 chan->chan_adapter = adapt; 692 chan->chan_bustype = &mvsata_atapi_bustype; 693 chan->chan_channel = chp->ch_channel; 694 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 695 chan->chan_openings = 1; 696 chan->chan_max_periph = 1; 697 chan->chan_ntargets = 1; 698 chan->chan_nluns = 1; 699 700 chp->atapibus = 701 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 702 } 703 704 static void 705 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 706 scsipi_adapter_req_t req, void *arg) 707 { 708 struct scsipi_adapter *adapt = chan->chan_adapter; 709 struct scsipi_periph *periph; 710 struct scsipi_xfer *sc_xfer; 711 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 712 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 713 struct ata_xfer *xfer; 714 int channel = chan->chan_channel; 715 int drive, s; 716 717 switch (req) { 718 case ADAPTER_REQ_RUN_XFER: 719 sc_xfer = arg; 720 periph = sc_xfer->xs_periph; 721 drive = periph->periph_target; 722 723 if (!device_is_active(atac->atac_dev)) { 724 sc_xfer->error = XS_DRIVER_STUFFUP; 725 scsipi_done(sc_xfer); 726 return; 727 } 728 xfer = ata_get_xfer(ATAXF_NOSLEEP); 729 if (xfer == NULL) { 730 sc_xfer->error = XS_RESOURCE_SHORTAGE; 731 scsipi_done(sc_xfer); 732 return; 733 } 734 735 if (sc_xfer->xs_control & XS_CTL_POLL) 736 xfer->c_flags |= C_POLL; 737 xfer->c_drive = drive; 738 xfer->c_flags |= C_ATAPI; 739 xfer->c_cmd = sc_xfer; 740 xfer->c_databuf = sc_xfer->data; 741 xfer->c_bcount = sc_xfer->datalen; 742 xfer->c_start = mvsata_atapi_start; 743 xfer->c_intr = mvsata_atapi_intr; 744 xfer->c_kill_xfer = mvsata_atapi_kill_xfer; 745 xfer->c_dscpoll = 0; 746 s = splbio(); 747 ata_exec_xfer(atac->atac_channels[channel], xfer); 748 #ifdef DIAGNOSTIC 749 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 750 (sc_xfer->xs_status & XS_STS_DONE) == 0) 751 panic("mvsata_atapi_scsipi_request:" 752 " polled command not done"); 753 #endif 754 splx(s); 755 return; 756 757 default: 758 /* Not supported, nothing to do. */ 759 ; 760 } 761 } 762 763 static void 764 mvsata_atapi_minphys(struct buf *bp) 765 { 766 767 if (bp->b_bcount > MAXPHYS) 768 bp->b_bcount = MAXPHYS; 769 minphys(bp); 770 } 771 772 static void 773 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 774 { 775 struct scsipi_channel *chan = sc->sc_channel; 776 struct scsipi_periph *periph; 777 struct ataparams ids; 778 struct ataparams *id = &ids; 779 struct mvsata_softc *mvc = 780 device_private(chan->chan_adapter->adapt_dev); 781 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 782 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 783 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 784 struct scsipibus_attach_args sa; 785 char serial_number[21], model[41], firmware_revision[9]; 786 int s; 787 788 /* skip if already attached */ 789 if (scsipi_lookup_periph(chan, target, 0) != NULL) 790 return; 791 792 /* if no ATAPI device detected at attach time, skip */ 793 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 794 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 795 " drive %d not present\n", 796 device_xname(atac->atac_dev), chp->ch_channel, target)); 797 return; 798 } 799 800 /* Some ATAPI devices need a bit more time after software reset. */ 801 delay(5000); 802 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 803 #ifdef ATAPI_DEBUG_PROBE 804 log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n", 805 device_xname(atac->atac_dev), chp->ch_channel, target, 806 id->atap_config & ATAPI_CFG_CMD_MASK, 807 id->atap_config & ATAPI_CFG_DRQ_MASK); 808 #endif 809 periph = scsipi_alloc_periph(M_NOWAIT); 810 if (periph == NULL) { 811 aprint_error_dev(atac->atac_dev, 812 "unable to allocate periph" 813 " for channel %d drive %d\n", 814 chp->ch_channel, target); 815 return; 816 } 817 periph->periph_dev = NULL; 818 periph->periph_channel = chan; 819 periph->periph_switch = &atapi_probe_periphsw; 820 periph->periph_target = target; 821 periph->periph_lun = 0; 822 periph->periph_quirks = PQUIRK_ONLYBIG; 823 824 #ifdef SCSIPI_DEBUG 825 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 826 SCSIPI_DEBUG_TARGET == target) 827 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 828 #endif 829 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 830 if (id->atap_config & ATAPI_CFG_REMOV) 831 periph->periph_flags |= PERIPH_REMOVABLE; 832 if (periph->periph_type == T_SEQUENTIAL) { 833 s = splbio(); 834 drvp->drive_flags |= DRIVE_ATAPIST; 835 splx(s); 836 } 837 838 sa.sa_periph = periph; 839 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 840 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 841 T_REMOV : T_FIXED; 842 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 843 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 20); 844 scsipi_strvis((u_char *)firmware_revision, 8, id->atap_revision, 845 8); 846 sa.sa_inqbuf.vendor = model; 847 sa.sa_inqbuf.product = serial_number; 848 sa.sa_inqbuf.revision = firmware_revision; 849 850 /* 851 * Determine the operating mode capabilities of the device. 852 */ 853 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 854 periph->periph_cap |= PERIPH_CAP_CMD16; 855 /* XXX This is gross. */ 856 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 857 858 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 859 860 if (drvp->drv_softc) 861 ata_probe_caps(drvp); 862 else { 863 s = splbio(); 864 drvp->drive_flags &= ~DRIVE_ATAPI; 865 splx(s); 866 } 867 } else { 868 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 869 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n", 870 device_xname(atac->atac_dev), chp->ch_channel, target, 871 chp->ch_error)); 872 s = splbio(); 873 drvp->drive_flags &= ~DRIVE_ATAPI; 874 splx(s); 875 } 876 } 877 878 /* 879 * Kill off all pending xfers for a periph. 880 * 881 * Must be called at splbio(). 882 */ 883 static void 884 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 885 { 886 struct atac_softc *atac = 887 device_private(periph->periph_channel->chan_adapter->adapt_dev); 888 struct ata_channel *chp = 889 atac->atac_channels[periph->periph_channel->chan_channel]; 890 891 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 892 } 893 #endif /* NATAPIBUS > 0 */ 894 #endif /* MVSATA_WITHOUTDMA */ 895 896 897 /* 898 * mvsata_setup_channel() 899 * Setup EDMA registers and prepare/purge DMA resources. 900 * We assuming already stopped the EDMA. 901 */ 902 static void 903 mvsata_setup_channel(struct ata_channel *chp) 904 { 905 #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG) 906 struct mvsata_port *mvport = (struct mvsata_port *)chp; 907 #endif 908 struct ata_drive_datas *drvp; 909 uint32_t edma_mode; 910 int drive, s; 911 #ifndef MVSATA_WITHOUTDMA 912 int i; 913 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 914 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 915 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 916 #endif 917 918 DPRINTF(("%s:%d: mvsata_setup_channel: ", 919 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 920 921 edma_mode = nodma; 922 for (drive = 0; drive < chp->ch_ndrive; drive++) { 923 drvp = &chp->ch_drive[drive]; 924 925 /* If no drive, skip */ 926 if (!(drvp->drive_flags & DRIVE)) 927 continue; 928 929 if (drvp->drive_flags & DRIVE_UDMA) { 930 /* use Ultra/DMA */ 931 s = splbio(); 932 drvp->drive_flags &= ~DRIVE_DMA; 933 splx(s); 934 } 935 936 if (drvp->drive_flags & (DRIVE_UDMA | DRIVE_DMA)) 937 if (drvp->drive_flags & DRIVE_ATA) 938 edma_mode = dma; 939 } 940 941 DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 942 943 #ifndef MVSATA_WITHOUTDMA 944 if (edma_mode == nodma) { 945 no_edma: 946 if (mvport->port_crqb != NULL) 947 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 948 mvport->port_crqb_dmamap, mvport->port_crqb); 949 if (mvport->port_crpb != NULL) 950 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 951 mvport->port_crpb_dmamap, mvport->port_crpb); 952 if (mvport->port_eprd != NULL) 953 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 954 mvport->port_eprd_dmamap, mvport->port_eprd); 955 956 return; 957 } 958 959 if (mvport->port_crqb == NULL) 960 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 961 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 962 if (mvport->port_crpb == NULL) 963 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 964 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 965 if (mvport->port_eprd == NULL) { 966 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 967 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 968 1); 969 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 970 mvport->port_reqtbl[i].eprd_offset = 971 i * MVSATA_EPRD_MAX_SIZE; 972 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 973 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 974 } 975 } 976 977 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 978 mvport->port_eprd == NULL) { 979 aprint_error_dev(MVSATA_DEV2(mvport), 980 "channel %d: can't use EDMA\n", chp->ch_channel); 981 s = splbio(); 982 for (drive = 0; drive < chp->ch_ndrive; drive++) { 983 drvp = &chp->ch_drive[drive]; 984 985 /* If no drive, skip */ 986 if (!(drvp->drive_flags & DRIVE)) 987 continue; 988 989 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 990 } 991 splx(s); 992 goto no_edma; 993 } 994 995 mvsata_edma_config(mvport, edma_mode); 996 mvsata_edma_reset_qptr(mvport); 997 mvsata_edma_enable(mvport); 998 #endif 999 } 1000 1001 #ifndef MVSATA_WITHOUTDMA 1002 static void 1003 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1004 { 1005 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1006 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1007 struct atac_softc *atac = chp->ch_atac; 1008 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1009 struct ata_bio *ata_bio = xfer->c_cmd; 1010 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1011 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1012 u_int16_t cyl; 1013 u_int8_t head, sect, cmd = 0; 1014 int nblks, error; 1015 1016 DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n", 1017 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1018 1019 if (xfer->c_flags & C_DMA) 1020 if (drvp->n_xfers <= NXFER) 1021 drvp->n_xfers++; 1022 1023 again: 1024 /* 1025 * 1026 * When starting a multi-sector transfer, or doing single-sector 1027 * transfers... 1028 */ 1029 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1030 if (ata_bio->flags & ATA_SINGLE) 1031 nblks = 1; 1032 else 1033 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1034 /* Check for bad sectors and adjust transfer, if necessary. */ 1035 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 1036 long blkdiff; 1037 int i; 1038 1039 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 1040 i++) { 1041 blkdiff -= ata_bio->blkno; 1042 if (blkdiff < 0) 1043 continue; 1044 if (blkdiff == 0) 1045 /* Replace current block of transfer. */ 1046 ata_bio->blkno = 1047 ata_bio->lp->d_secperunit - 1048 ata_bio->lp->d_nsectors - i - 1; 1049 if (blkdiff < nblks) { 1050 /* Bad block inside transfer. */ 1051 ata_bio->flags |= ATA_SINGLE; 1052 nblks = 1; 1053 } 1054 break; 1055 } 1056 /* Transfer is okay now. */ 1057 } 1058 if (xfer->c_flags & C_DMA) { 1059 ata_bio->nblks = nblks; 1060 ata_bio->nbytes = xfer->c_bcount; 1061 1062 if (xfer->c_flags & C_POLL) 1063 sc->sc_enable_intr(mvport, 0 /*off*/); 1064 error = mvsata_edma_inqueue(mvport, ata_bio, 1065 (char *)xfer->c_databuf + xfer->c_skip); 1066 if (error) { 1067 if (error == EINVAL) { 1068 /* 1069 * We can't do DMA on this transfer 1070 * for some reason. Fall back to 1071 * PIO. 1072 */ 1073 xfer->c_flags &= ~C_DMA; 1074 error = 0; 1075 goto do_pio; 1076 } 1077 if (error == EBUSY) { 1078 aprint_error_dev(atac->atac_dev, 1079 "channel %d: EDMA Queue full\n", 1080 chp->ch_channel); 1081 /* 1082 * XXXX: Perhaps, after it waits for 1083 * a while, it is necessary to call 1084 * bio_start again. 1085 */ 1086 } 1087 ata_bio->error = ERR_DMA; 1088 ata_bio->r_error = 0; 1089 mvsata_bio_done(chp, xfer); 1090 return; 1091 } 1092 chp->ch_flags |= ATACH_DMA_WAIT; 1093 /* start timeout machinery */ 1094 if ((xfer->c_flags & C_POLL) == 0) 1095 callout_reset(&chp->ch_callout, 1096 ATA_DELAY / 1000 * hz, 1097 mvsata_edma_timeout, xfer); 1098 /* wait for irq */ 1099 goto intr; 1100 } /* else not DMA */ 1101 do_pio: 1102 if (ata_bio->flags & ATA_LBA48) { 1103 sect = 0; 1104 cyl = 0; 1105 head = 0; 1106 } else if (ata_bio->flags & ATA_LBA) { 1107 sect = (ata_bio->blkno >> 0) & 0xff; 1108 cyl = (ata_bio->blkno >> 8) & 0xffff; 1109 head = (ata_bio->blkno >> 24) & 0x0f; 1110 head |= WDSD_LBA; 1111 } else { 1112 int blkno = ata_bio->blkno; 1113 sect = blkno % ata_bio->lp->d_nsectors; 1114 sect++; /* Sectors begin with 1, not 0. */ 1115 blkno /= ata_bio->lp->d_nsectors; 1116 head = blkno % ata_bio->lp->d_ntracks; 1117 blkno /= ata_bio->lp->d_ntracks; 1118 cyl = blkno; 1119 head |= WDSD_CHS; 1120 } 1121 ata_bio->nblks = min(nblks, ata_bio->multi); 1122 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 1123 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1124 if (ata_bio->nblks > 1) 1125 cmd = (ata_bio->flags & ATA_READ) ? 1126 WDCC_READMULTI : WDCC_WRITEMULTI; 1127 else 1128 cmd = (ata_bio->flags & ATA_READ) ? 1129 WDCC_READ : WDCC_WRITE; 1130 1131 /* EDMA disable, if enabled this channel. */ 1132 if (mvport->port_edmamode != nodma) 1133 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1134 1135 /* Do control operations specially. */ 1136 if (__predict_false(drvp->state < READY)) { 1137 /* 1138 * Actually, we want to be careful not to mess with 1139 * the control state if the device is currently busy, 1140 * but we can assume that we never get to this point 1141 * if that's the case. 1142 */ 1143 /* 1144 * If it's not a polled command, we need the kernel 1145 * thread 1146 */ 1147 if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) { 1148 chp->ch_queue->queue_freeze++; 1149 wakeup(&chp->ch_thread); 1150 return; 1151 } 1152 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1153 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1154 mvsata_bio_done(chp, xfer); 1155 return; 1156 } 1157 } 1158 1159 /* Initiate command! */ 1160 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1161 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 1162 case WDCWAIT_OK: 1163 break; 1164 case WDCWAIT_TOUT: 1165 goto timeout; 1166 case WDCWAIT_THR: 1167 return; 1168 } 1169 if (ata_bio->flags & ATA_LBA48) 1170 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 1171 (u_int64_t)ata_bio->blkno, nblks); 1172 else 1173 wdccommand(chp, xfer->c_drive, cmd, cyl, 1174 head, sect, nblks, 1175 (ata_bio->lp->d_type == DTYPE_ST506) ? 1176 ata_bio->lp->d_precompcyl / 4 : 0); 1177 1178 /* start timeout machinery */ 1179 if ((xfer->c_flags & C_POLL) == 0) 1180 callout_reset(&chp->ch_callout, 1181 ATA_DELAY / 1000 * hz, wdctimeout, chp); 1182 } else if (ata_bio->nblks > 1) { 1183 /* The number of blocks in the last stretch may be smaller. */ 1184 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1185 if (ata_bio->nblks > nblks) { 1186 ata_bio->nblks = nblks; 1187 ata_bio->nbytes = xfer->c_bcount; 1188 } 1189 } 1190 /* If this was a write and not using DMA, push the data. */ 1191 if ((ata_bio->flags & ATA_READ) == 0) { 1192 /* 1193 * we have to busy-wait here, we can't rely on running in 1194 * thread context. 1195 */ 1196 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 1197 aprint_error_dev(atac->atac_dev, 1198 "channel %d: drive %d timeout waiting for DRQ," 1199 " st=0x%02x, err=0x%02x\n", 1200 chp->ch_channel, xfer->c_drive, chp->ch_status, 1201 chp->ch_error); 1202 ata_bio->error = TIMEOUT; 1203 mvsata_bio_done(chp, xfer); 1204 return; 1205 } 1206 if (chp->ch_status & WDCS_ERR) { 1207 ata_bio->error = ERROR; 1208 ata_bio->r_error = chp->ch_error; 1209 mvsata_bio_done(chp, xfer); 1210 return; 1211 } 1212 1213 wdc->dataout_pio(chp, drvp->drive_flags, 1214 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1215 } 1216 1217 intr: 1218 /* Wait for IRQ (either real or polled) */ 1219 if ((ata_bio->flags & ATA_POLL) == 0) { 1220 chp->ch_flags |= ATACH_IRQ_WAIT; 1221 1222 #if 1 /* XXXXX: Marvell SATA and mvsata(4) can accept next xfer. */ 1223 chp->ch_queue->active_xfer = NULL; 1224 #endif 1225 } else { 1226 /* Wait for at last 400ns for status bit to be valid */ 1227 delay(1); 1228 if (chp->ch_flags & ATACH_DMA_WAIT) { 1229 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1230 sc->sc_enable_intr(mvport, 1 /*on*/); 1231 chp->ch_flags &= ~ATACH_DMA_WAIT; 1232 } 1233 mvsata_bio_intr(chp, xfer, 0); 1234 if ((ata_bio->flags & ATA_ITSDONE) == 0) 1235 goto again; 1236 } 1237 return; 1238 1239 timeout: 1240 aprint_error_dev(atac->atac_dev, 1241 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1242 chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error); 1243 ata_bio->error = TIMEOUT; 1244 mvsata_bio_done(chp, xfer); 1245 return; 1246 } 1247 1248 static int 1249 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1250 { 1251 struct atac_softc *atac = chp->ch_atac; 1252 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1253 struct ata_bio *ata_bio = xfer->c_cmd; 1254 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1255 1256 DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n", 1257 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1258 1259 /* Is it not a transfer, but a control operation? */ 1260 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1261 aprint_error_dev(atac->atac_dev, 1262 "channel %d: drive %d bad state %d in mvsata_bio_intr\n", 1263 chp->ch_channel, xfer->c_drive, drvp->state); 1264 panic("mvsata_bio_intr: bad state"); 1265 } 1266 1267 /* 1268 * if we missed an interrupt transfer, reset and restart. 1269 * Don't try to continue transfer, we may have missed cycles. 1270 */ 1271 if (xfer->c_flags & C_TIMEOU) { 1272 ata_bio->error = TIMEOUT; 1273 mvsata_bio_done(chp, xfer); 1274 return 1; 1275 } 1276 1277 /* Ack interrupt done by wdc_wait_for_unbusy */ 1278 if (!(xfer->c_flags & C_DMA) && 1279 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) 1280 == WDCWAIT_TOUT)) { 1281 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1282 return 0; /* IRQ was not for us */ 1283 aprint_error_dev(atac->atac_dev, 1284 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1285 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1286 xfer->c_skip); 1287 ata_bio->error = TIMEOUT; 1288 mvsata_bio_done(chp, xfer); 1289 return 1; 1290 } 1291 1292 if (xfer->c_flags & C_DMA) { 1293 if (ata_bio->error == NOERROR) 1294 goto end; 1295 if (ata_bio->error == ERR_DMA) 1296 ata_dmaerr(drvp, 1297 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1298 } 1299 1300 /* if we had an error, end */ 1301 if (ata_bio->error != NOERROR) { 1302 mvsata_bio_done(chp, xfer); 1303 return 1; 1304 } 1305 1306 /* If this was a read and not using DMA, fetch the data. */ 1307 if ((ata_bio->flags & ATA_READ) != 0) { 1308 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 1309 aprint_error_dev(atac->atac_dev, 1310 "channel %d: drive %d read intr before drq\n", 1311 chp->ch_channel, xfer->c_drive); 1312 ata_bio->error = TIMEOUT; 1313 mvsata_bio_done(chp, xfer); 1314 return 1; 1315 } 1316 wdc->datain_pio(chp, drvp->drive_flags, 1317 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1318 } 1319 1320 end: 1321 ata_bio->blkno += ata_bio->nblks; 1322 ata_bio->blkdone += ata_bio->nblks; 1323 xfer->c_skip += ata_bio->nbytes; 1324 xfer->c_bcount -= ata_bio->nbytes; 1325 /* See if this transfer is complete. */ 1326 if (xfer->c_bcount > 0) { 1327 if ((ata_bio->flags & ATA_POLL) == 0) 1328 /* Start the next operation */ 1329 mvsata_bio_start(chp, xfer); 1330 else 1331 /* Let mvsata_bio_start do the loop */ 1332 return 1; 1333 } else { /* Done with this transfer */ 1334 ata_bio->error = NOERROR; 1335 mvsata_bio_done(chp, xfer); 1336 } 1337 return 1; 1338 } 1339 1340 static void 1341 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1342 { 1343 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1344 struct atac_softc *atac = chp->ch_atac; 1345 struct ata_bio *ata_bio = xfer->c_cmd; 1346 int drive = xfer->c_drive; 1347 1348 DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1349 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1350 1351 /* EDMA restart, if enabled */ 1352 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1353 mvsata_edma_reset_qptr(mvport); 1354 mvsata_edma_enable(mvport); 1355 } 1356 1357 ata_free_xfer(chp, xfer); 1358 1359 ata_bio->flags |= ATA_ITSDONE; 1360 switch (reason) { 1361 case KILL_GONE: 1362 ata_bio->error = ERR_NODEV; 1363 break; 1364 case KILL_RESET: 1365 ata_bio->error = ERR_RESET; 1366 break; 1367 default: 1368 aprint_error_dev(atac->atac_dev, 1369 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1370 panic("mvsata_bio_kill_xfer"); 1371 } 1372 ata_bio->r_error = WDCE_ABRT; 1373 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1374 } 1375 1376 static void 1377 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1378 { 1379 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1380 struct ata_bio *ata_bio = xfer->c_cmd; 1381 int drive = xfer->c_drive; 1382 1383 DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1384 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1385 (u_int)xfer->c_flags)); 1386 1387 callout_stop(&chp->ch_callout); 1388 1389 /* EDMA restart, if enabled */ 1390 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1391 mvsata_edma_reset_qptr(mvport); 1392 mvsata_edma_enable(mvport); 1393 } 1394 1395 /* feed back residual bcount to our caller */ 1396 ata_bio->bcount = xfer->c_bcount; 1397 1398 /* mark controller inactive and free xfer */ 1399 chp->ch_queue->active_xfer = NULL; 1400 ata_free_xfer(chp, xfer); 1401 1402 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1403 ata_bio->error = ERR_NODEV; 1404 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1405 wakeup(&chp->ch_queue->active_xfer); 1406 } 1407 ata_bio->flags |= ATA_ITSDONE; 1408 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1409 atastart(chp); 1410 } 1411 1412 static int 1413 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1414 int flags) 1415 { 1416 struct ata_channel *chp = &mvport->port_ata_channel; 1417 struct atac_softc *atac = chp->ch_atac; 1418 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1419 const char *errstring; 1420 1421 /* 1422 * disable interrupts, all commands here should be quick 1423 * enough to be able to poll, and we don't go here that often 1424 */ 1425 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1426 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1427 DELAY(10); 1428 errstring = "wait"; 1429 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1430 goto ctrltimeout; 1431 wdccommandshort(chp, drive, WDCC_RECAL); 1432 /* Wait for at last 400ns for status bit to be valid */ 1433 DELAY(1); 1434 errstring = "recal"; 1435 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1436 goto ctrltimeout; 1437 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1438 goto ctrlerror; 1439 /* Don't try to set modes if controller can't be adjusted */ 1440 if (atac->atac_set_modes == NULL) 1441 goto geometry; 1442 /* Also don't try if the drive didn't report its mode */ 1443 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1444 goto geometry; 1445 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1446 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1447 errstring = "piomode"; 1448 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1449 goto ctrltimeout; 1450 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1451 goto ctrlerror; 1452 if (drvp->drive_flags & DRIVE_UDMA) 1453 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1454 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1455 else if (drvp->drive_flags & DRIVE_DMA) 1456 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1457 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1458 else 1459 goto geometry; 1460 errstring = "dmamode"; 1461 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1462 goto ctrltimeout; 1463 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1464 goto ctrlerror; 1465 geometry: 1466 if (ata_bio->flags & ATA_LBA) 1467 goto multimode; 1468 wdccommand(chp, drive, WDCC_IDP, ata_bio->lp->d_ncylinders, 1469 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 1470 (ata_bio->lp->d_type == DTYPE_ST506) ? 1471 ata_bio->lp->d_precompcyl / 4 : 0); 1472 errstring = "geometry"; 1473 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1474 goto ctrltimeout; 1475 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1476 goto ctrlerror; 1477 multimode: 1478 if (ata_bio->multi == 1) 1479 goto ready; 1480 wdccommand(chp, drive, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0); 1481 errstring = "setmulti"; 1482 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1483 goto ctrltimeout; 1484 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1485 goto ctrlerror; 1486 ready: 1487 drvp->state = READY; 1488 /* 1489 * The drive is usable now 1490 */ 1491 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1492 delay(10); /* some drives need a little delay here */ 1493 return 0; 1494 1495 ctrltimeout: 1496 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1497 chp->ch_channel, drive, errstring); 1498 ata_bio->error = TIMEOUT; 1499 goto ctrldone; 1500 ctrlerror: 1501 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1502 chp->ch_channel, drive, errstring); 1503 if (chp->ch_status & WDCS_DWF) { 1504 aprint_error("drive fault\n"); 1505 ata_bio->error = ERR_DF; 1506 } else { 1507 aprint_error("error (%x)\n", chp->ch_error); 1508 ata_bio->r_error = chp->ch_error; 1509 ata_bio->error = ERROR; 1510 } 1511 ctrldone: 1512 drvp->state = 0; 1513 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1514 return -1; 1515 } 1516 1517 static void 1518 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1519 { 1520 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1521 int drive = xfer->c_drive; 1522 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1523 struct ata_command *ata_c = xfer->c_cmd; 1524 1525 DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n", 1526 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1527 1528 /* First, EDMA disable, if enabled this channel. */ 1529 if (mvport->port_edmamode != nodma) 1530 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1531 1532 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1533 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1534 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1535 case WDCWAIT_OK: 1536 break; 1537 case WDCWAIT_TOUT: 1538 ata_c->flags |= AT_TIMEOU; 1539 mvsata_wdc_cmd_done(chp, xfer); 1540 return; 1541 case WDCWAIT_THR: 1542 return; 1543 } 1544 if (ata_c->flags & AT_POLL) 1545 /* polled command, disable interrupts */ 1546 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1547 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1548 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1549 1550 if ((ata_c->flags & AT_POLL) == 0) { 1551 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1552 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1553 wdctimeout, chp); 1554 return; 1555 } 1556 /* 1557 * Polled command. Wait for drive ready or drq. Done in intr(). 1558 * Wait for at last 400ns for status bit to be valid. 1559 */ 1560 delay(10); /* 400ns delay */ 1561 mvsata_wdc_cmd_intr(chp, xfer, 0); 1562 } 1563 1564 static int 1565 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1566 { 1567 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1568 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1569 struct ata_command *ata_c = xfer->c_cmd; 1570 int bcount = ata_c->bcount; 1571 char *data = ata_c->data; 1572 int wflags; 1573 int drive_flags; 1574 1575 if (ata_c->r_command == WDCC_IDENTIFY || 1576 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1577 /* 1578 * The IDENTIFY data has been designed as an array of 1579 * u_int16_t, so we can byteswap it on the fly. 1580 * Historically it's what we have always done so keeping it 1581 * here ensure binary backward compatibility. 1582 */ 1583 drive_flags = DRIVE_NOSTREAM | 1584 chp->ch_drive[xfer->c_drive].drive_flags; 1585 else 1586 /* 1587 * Other data structure are opaque and should be transfered 1588 * as is. 1589 */ 1590 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1591 1592 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1593 /* both wait and poll, we can tsleep here */ 1594 wflags = AT_WAIT | AT_POLL; 1595 else 1596 wflags = AT_POLL; 1597 1598 again: 1599 DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n", 1600 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1601 1602 /* 1603 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1604 * Reselect again, it doesn't hurt for others commands, and the time 1605 * penalty for the extra regiter write is acceptable, 1606 * wdc_exec_command() isn't called often (mosly for autoconfig) 1607 */ 1608 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1609 if ((ata_c->flags & AT_XFDONE) != 0) { 1610 /* 1611 * We have completed a data xfer. The drive should now be 1612 * in its initial state 1613 */ 1614 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1615 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1616 wflags) == WDCWAIT_TOUT) { 1617 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1618 return 0; /* IRQ was not for us */ 1619 ata_c->flags |= AT_TIMEOU; 1620 } 1621 goto out; 1622 } 1623 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1624 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1625 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1626 return 0; /* IRQ was not for us */ 1627 ata_c->flags |= AT_TIMEOU; 1628 goto out; 1629 } 1630 if (ata_c->flags & AT_READ) { 1631 if ((chp->ch_status & WDCS_DRQ) == 0) { 1632 ata_c->flags |= AT_TIMEOU; 1633 goto out; 1634 } 1635 wdc->datain_pio(chp, drive_flags, data, bcount); 1636 /* at this point the drive should be in its initial state */ 1637 ata_c->flags |= AT_XFDONE; 1638 /* 1639 * XXX checking the status register again here cause some 1640 * hardware to timeout. 1641 */ 1642 } else if (ata_c->flags & AT_WRITE) { 1643 if ((chp->ch_status & WDCS_DRQ) == 0) { 1644 ata_c->flags |= AT_TIMEOU; 1645 goto out; 1646 } 1647 wdc->dataout_pio(chp, drive_flags, data, bcount); 1648 ata_c->flags |= AT_XFDONE; 1649 if ((ata_c->flags & AT_POLL) == 0) { 1650 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */ 1651 callout_reset(&chp->ch_callout, 1652 mstohz(ata_c->timeout), wdctimeout, chp); 1653 return 1; 1654 } else 1655 goto again; 1656 } 1657 out: 1658 mvsata_wdc_cmd_done(chp, xfer); 1659 return 1; 1660 } 1661 1662 static void 1663 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1664 int reason) 1665 { 1666 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1667 struct ata_command *ata_c = xfer->c_cmd; 1668 1669 DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1670 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1671 1672 switch (reason) { 1673 case KILL_GONE: 1674 ata_c->flags |= AT_GONE; 1675 break; 1676 case KILL_RESET: 1677 ata_c->flags |= AT_RESET; 1678 break; 1679 default: 1680 aprint_error_dev(MVSATA_DEV2(mvport), 1681 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1682 panic("mvsata_cmd_kill_xfer"); 1683 } 1684 mvsata_wdc_cmd_done_end(chp, xfer); 1685 } 1686 1687 static void 1688 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1689 { 1690 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1691 struct atac_softc *atac = chp->ch_atac; 1692 struct ata_command *ata_c = xfer->c_cmd; 1693 1694 DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1695 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1696 ata_c->flags)); 1697 1698 if (chp->ch_status & WDCS_DWF) 1699 ata_c->flags |= AT_DF; 1700 if (chp->ch_status & WDCS_ERR) { 1701 ata_c->flags |= AT_ERROR; 1702 ata_c->r_error = chp->ch_error; 1703 } 1704 if ((ata_c->flags & AT_READREG) != 0 && 1705 device_is_active(atac->atac_dev) && 1706 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1707 ata_c->r_head = MVSATA_WDC_READ_1(mvport, SRB_H); 1708 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1709 ata_c->r_sector = MVSATA_WDC_READ_1(mvport, SRB_LBAL); 1710 ata_c->r_cyl = MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1711 ata_c->r_cyl |= MVSATA_WDC_READ_1(mvport, SRB_LBAH); 1712 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1713 ata_c->r_features = ata_c->r_error; 1714 } 1715 callout_stop(&chp->ch_callout); 1716 chp->ch_queue->active_xfer = NULL; 1717 if (ata_c->flags & AT_POLL) { 1718 /* enable interrupts */ 1719 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1720 delay(10); /* some drives need a little delay here */ 1721 } 1722 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1723 mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE); 1724 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1725 wakeup(&chp->ch_queue->active_xfer); 1726 } else 1727 mvsata_wdc_cmd_done_end(chp, xfer); 1728 } 1729 1730 static void 1731 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1732 { 1733 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1734 struct ata_command *ata_c = xfer->c_cmd; 1735 1736 /* EDMA restart, if enabled */ 1737 if (mvport->port_edmamode != nodma) { 1738 mvsata_edma_reset_qptr(mvport); 1739 mvsata_edma_enable(mvport); 1740 } 1741 1742 ata_c->flags |= AT_DONE; 1743 ata_free_xfer(chp, xfer); 1744 if (ata_c->flags & AT_WAIT) 1745 wakeup(ata_c); 1746 else if (ata_c->callback) 1747 ata_c->callback(ata_c->callback_arg); 1748 atastart(chp); 1749 1750 return; 1751 } 1752 1753 #if NATAPIBUS > 0 1754 static void 1755 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1756 { 1757 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 1758 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1759 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1760 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1761 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1762 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1763 const char *errstring; 1764 1765 DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 1766 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1767 xfer->c_drive, sc_xfer->xs_control)); 1768 1769 if (mvport->port_edmamode != nodma) 1770 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1771 1772 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 1773 drvp->n_xfers++; 1774 1775 /* Do control operations specially. */ 1776 if (__predict_false(drvp->state < READY)) { 1777 /* If it's not a polled command, we need the kernel thread */ 1778 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) { 1779 chp->ch_queue->queue_freeze++; 1780 wakeup(&chp->ch_thread); 1781 return; 1782 } 1783 /* 1784 * disable interrupts, all commands here should be quick 1785 * enough to be able to poll, and we don't go here that often 1786 */ 1787 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1788 1789 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1790 /* Don't try to set mode if controller can't be adjusted */ 1791 if (atac->atac_set_modes == NULL) 1792 goto ready; 1793 /* Also don't try if the drive didn't report its mode */ 1794 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1795 goto ready; 1796 errstring = "unbusy"; 1797 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) 1798 goto timeout; 1799 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1800 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1801 errstring = "piomode"; 1802 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1803 goto timeout; 1804 if (chp->ch_status & WDCS_ERR) { 1805 if (chp->ch_error == WDCE_ABRT) { 1806 /* 1807 * Some ATAPI drives reject PIO settings. 1808 * Fall back to PIO mode 3 since that's the 1809 * minimum for ATAPI. 1810 */ 1811 aprint_error_dev(atac->atac_dev, 1812 "channel %d drive %d: PIO mode %d rejected," 1813 " falling back to PIO mode 3\n", 1814 chp->ch_channel, xfer->c_drive, 1815 drvp->PIO_mode); 1816 if (drvp->PIO_mode > 3) 1817 drvp->PIO_mode = 3; 1818 } else 1819 goto error; 1820 } 1821 if (drvp->drive_flags & DRIVE_UDMA) 1822 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1823 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1824 else 1825 if (drvp->drive_flags & DRIVE_DMA) 1826 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1827 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1828 else 1829 goto ready; 1830 errstring = "dmamode"; 1831 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1832 goto timeout; 1833 if (chp->ch_status & WDCS_ERR) { 1834 if (chp->ch_error == WDCE_ABRT) { 1835 if (drvp->drive_flags & DRIVE_UDMA) 1836 goto error; 1837 else { 1838 /* 1839 * The drive rejected our DMA setting. 1840 * Fall back to mode 1. 1841 */ 1842 aprint_error_dev(atac->atac_dev, 1843 "channel %d drive %d:" 1844 " DMA mode %d rejected," 1845 " falling back to DMA mode 0\n", 1846 chp->ch_channel, xfer->c_drive, 1847 drvp->DMA_mode); 1848 if (drvp->DMA_mode > 0) 1849 drvp->DMA_mode = 0; 1850 } 1851 } else 1852 goto error; 1853 } 1854 ready: 1855 drvp->state = READY; 1856 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1857 delay(10); /* some drives need a little delay here */ 1858 } 1859 /* start timeout machinery */ 1860 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 1861 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1862 wdctimeout, chp); 1863 1864 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1865 switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) { 1866 case WDCWAIT_OK: 1867 break; 1868 case WDCWAIT_TOUT: 1869 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 1870 chp->ch_status); 1871 sc_xfer->error = XS_TIMEOUT; 1872 mvsata_atapi_reset(chp, xfer); 1873 return; 1874 case WDCWAIT_THR: 1875 return; 1876 } 1877 1878 /* 1879 * Even with WDCS_ERR, the device should accept a command packet 1880 * Limit length to what can be stuffed into the cylinder register 1881 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 1882 * but not all devices do that and it's not obvious from the 1883 * ATAPI spec that that behaviour should be expected. If more 1884 * data is necessary, multiple data transfer phases will be done. 1885 */ 1886 1887 wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD, 1888 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 1889 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1890 1891 /* 1892 * If there is no interrupt for CMD input, busy-wait for it (done in 1893 * the interrupt routine. If it is a polled command, call the interrupt 1894 * routine until command is done. 1895 */ 1896 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 1897 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) { 1898 /* Wait for at last 400ns for status bit to be valid */ 1899 DELAY(1); 1900 mvsata_atapi_intr(chp, xfer, 0); 1901 } else 1902 chp->ch_flags |= ATACH_IRQ_WAIT; 1903 if (sc_xfer->xs_control & XS_CTL_POLL) { 1904 if (chp->ch_flags & ATACH_DMA_WAIT) { 1905 wdc_dmawait(chp, xfer, sc_xfer->timeout); 1906 chp->ch_flags &= ~ATACH_DMA_WAIT; 1907 } 1908 while ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1909 /* Wait for at last 400ns for status bit to be valid */ 1910 DELAY(1); 1911 mvsata_atapi_intr(chp, xfer, 0); 1912 } 1913 } 1914 return; 1915 1916 timeout: 1917 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 1918 chp->ch_channel, xfer->c_drive, errstring); 1919 sc_xfer->error = XS_TIMEOUT; 1920 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1921 delay(10); /* some drives need a little delay here */ 1922 mvsata_atapi_reset(chp, xfer); 1923 return; 1924 1925 error: 1926 aprint_error_dev(atac->atac_dev, 1927 "channel %d drive %d: %s error (0x%x)\n", 1928 chp->ch_channel, xfer->c_drive, errstring, chp->ch_error); 1929 sc_xfer->error = XS_SHORTSENSE; 1930 sc_xfer->sense.atapi_sense = chp->ch_error; 1931 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1932 delay(10); /* some drives need a little delay here */ 1933 mvsata_atapi_reset(chp, xfer); 1934 return; 1935 } 1936 1937 static int 1938 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1939 { 1940 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1941 struct atac_softc *atac = chp->ch_atac; 1942 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1943 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1944 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1945 int len, phase, ire, error, retries=0, i; 1946 void *cmd; 1947 1948 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n", 1949 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1950 1951 /* Is it not a transfer, but a control operation? */ 1952 if (drvp->state < READY) { 1953 aprint_error_dev(atac->atac_dev, 1954 "channel %d drive %d: bad state %d\n", 1955 chp->ch_channel, xfer->c_drive, drvp->state); 1956 panic("mvsata_atapi_intr: bad state"); 1957 } 1958 /* 1959 * If we missed an interrupt in a PIO transfer, reset and restart. 1960 * Don't try to continue transfer, we may have missed cycles. 1961 */ 1962 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 1963 sc_xfer->error = XS_TIMEOUT; 1964 mvsata_atapi_reset(chp, xfer); 1965 return 1; 1966 } 1967 1968 /* Ack interrupt done in wdc_wait_for_unbusy */ 1969 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1970 if (wdc_wait_for_unbusy(chp, 1971 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) { 1972 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1973 return 0; /* IRQ was not for us */ 1974 aprint_error_dev(atac->atac_dev, 1975 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 1976 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 1977 if (xfer->c_flags & C_DMA) 1978 ata_dmaerr(drvp, 1979 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1980 sc_xfer->error = XS_TIMEOUT; 1981 mvsata_atapi_reset(chp, xfer); 1982 return 1; 1983 } 1984 1985 /* 1986 * If we missed an IRQ and were using DMA, flag it as a DMA error 1987 * and reset device. 1988 */ 1989 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 1990 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1991 sc_xfer->error = XS_RESET; 1992 mvsata_atapi_reset(chp, xfer); 1993 return (1); 1994 } 1995 /* 1996 * if the request sense command was aborted, report the short sense 1997 * previously recorded, else continue normal processing 1998 */ 1999 2000 again: 2001 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2002 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2003 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2004 phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ); 2005 DPRINTF(( 2006 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2007 xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire)); 2008 2009 switch (phase) { 2010 case PHASE_CMDOUT: 2011 cmd = sc_xfer->cmd; 2012 DPRINTF(("PHASE_CMDOUT\n")); 2013 /* Init the DMA channel if necessary */ 2014 if (xfer->c_flags & C_DMA) { 2015 error = mvsata_bdma_init(mvport, sc_xfer, 2016 (char *)xfer->c_databuf + xfer->c_skip); 2017 if (error) { 2018 if (error == EINVAL) { 2019 /* 2020 * We can't do DMA on this transfer 2021 * for some reason. Fall back to PIO. 2022 */ 2023 xfer->c_flags &= ~C_DMA; 2024 error = 0; 2025 } else { 2026 sc_xfer->error = XS_DRIVER_STUFFUP; 2027 break; 2028 } 2029 } 2030 } 2031 2032 /* send packet command */ 2033 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2034 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2035 2036 /* Start the DMA channel if necessary */ 2037 if (xfer->c_flags & C_DMA) { 2038 mvsata_bdma_start(mvport); 2039 chp->ch_flags |= ATACH_DMA_WAIT; 2040 } 2041 2042 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2043 chp->ch_flags |= ATACH_IRQ_WAIT; 2044 return 1; 2045 2046 case PHASE_DATAOUT: 2047 /* write data */ 2048 DPRINTF(("PHASE_DATAOUT\n")); 2049 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2050 (xfer->c_flags & C_DMA) != 0) { 2051 aprint_error_dev(atac->atac_dev, 2052 "channel %d drive %d: bad data phase DATAOUT\n", 2053 chp->ch_channel, xfer->c_drive); 2054 if (xfer->c_flags & C_DMA) 2055 ata_dmaerr(drvp, 2056 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2057 sc_xfer->error = XS_TIMEOUT; 2058 mvsata_atapi_reset(chp, xfer); 2059 return 1; 2060 } 2061 xfer->c_lenoff = len - xfer->c_bcount; 2062 if (xfer->c_bcount < len) { 2063 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2064 " warning: write only %d of %d requested bytes\n", 2065 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2066 len); 2067 len = xfer->c_bcount; 2068 } 2069 2070 wdc->dataout_pio(chp, drvp->drive_flags, 2071 (char *)xfer->c_databuf + xfer->c_skip, len); 2072 2073 for (i = xfer->c_lenoff; i > 0; i -= 2) 2074 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2075 2076 xfer->c_skip += len; 2077 xfer->c_bcount -= len; 2078 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2079 chp->ch_flags |= ATACH_IRQ_WAIT; 2080 return 1; 2081 2082 case PHASE_DATAIN: 2083 /* Read data */ 2084 DPRINTF(("PHASE_DATAIN\n")); 2085 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2086 (xfer->c_flags & C_DMA) != 0) { 2087 aprint_error_dev(atac->atac_dev, 2088 "channel %d drive %d: bad data phase DATAIN\n", 2089 chp->ch_channel, xfer->c_drive); 2090 if (xfer->c_flags & C_DMA) 2091 ata_dmaerr(drvp, 2092 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2093 sc_xfer->error = XS_TIMEOUT; 2094 mvsata_atapi_reset(chp, xfer); 2095 return 1; 2096 } 2097 xfer->c_lenoff = len - xfer->c_bcount; 2098 if (xfer->c_bcount < len) { 2099 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2100 " warning: reading only %d of %d bytes\n", 2101 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2102 len); 2103 len = xfer->c_bcount; 2104 } 2105 2106 wdc->datain_pio(chp, drvp->drive_flags, 2107 (char *)xfer->c_databuf + xfer->c_skip, len); 2108 2109 if (xfer->c_lenoff > 0) 2110 wdcbit_bucket(chp, len - xfer->c_bcount); 2111 2112 xfer->c_skip += len; 2113 xfer->c_bcount -= len; 2114 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2115 chp->ch_flags |= ATACH_IRQ_WAIT; 2116 return 1; 2117 2118 case PHASE_ABORTED: 2119 case PHASE_COMPLETED: 2120 DPRINTF(("PHASE_COMPLETED\n")); 2121 if (xfer->c_flags & C_DMA) 2122 xfer->c_bcount -= sc_xfer->datalen; 2123 sc_xfer->resid = xfer->c_bcount; 2124 mvsata_atapi_phase_complete(xfer); 2125 return 1; 2126 2127 default: 2128 if (++retries<500) { 2129 DELAY(100); 2130 chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 2131 chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 2132 goto again; 2133 } 2134 aprint_error_dev(atac->atac_dev, 2135 "channel %d drive %d: unknown phase 0x%x\n", 2136 chp->ch_channel, xfer->c_drive, phase); 2137 if (chp->ch_status & WDCS_ERR) { 2138 sc_xfer->error = XS_SHORTSENSE; 2139 sc_xfer->sense.atapi_sense = chp->ch_error; 2140 } else { 2141 if (xfer->c_flags & C_DMA) 2142 ata_dmaerr(drvp, 2143 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2144 sc_xfer->error = XS_RESET; 2145 mvsata_atapi_reset(chp, xfer); 2146 return (1); 2147 } 2148 } 2149 DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x " 2150 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense)); 2151 mvsata_atapi_done(chp, xfer); 2152 return 1; 2153 } 2154 2155 static void 2156 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2157 int reason) 2158 { 2159 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2160 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2161 2162 /* remove this command from xfer queue */ 2163 switch (reason) { 2164 case KILL_GONE: 2165 sc_xfer->error = XS_DRIVER_STUFFUP; 2166 break; 2167 2168 case KILL_RESET: 2169 sc_xfer->error = XS_RESET; 2170 break; 2171 2172 default: 2173 aprint_error_dev(MVSATA_DEV2(mvport), 2174 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2175 panic("mvsata_atapi_kill_xfer"); 2176 } 2177 ata_free_xfer(chp, xfer); 2178 scsipi_done(sc_xfer); 2179 } 2180 2181 static void 2182 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2183 { 2184 struct atac_softc *atac = chp->ch_atac; 2185 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2186 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2187 2188 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 2189 drvp->state = 0; 2190 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) { 2191 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2192 chp->ch_channel, xfer->c_drive); 2193 sc_xfer->error = XS_SELTIMEOUT; 2194 } 2195 mvsata_atapi_done(chp, xfer); 2196 return; 2197 } 2198 2199 static void 2200 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2201 { 2202 struct ata_channel *chp = xfer->c_chp; 2203 struct atac_softc *atac = chp->ch_atac; 2204 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2205 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2206 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2207 2208 /* wait for DSC if needed */ 2209 if (drvp->drive_flags & DRIVE_ATAPIST) { 2210 DPRINTFN(1, 2211 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2212 device_xname(atac->atac_dev), chp->ch_channel, 2213 xfer->c_drive, xfer->c_dscpoll)); 2214 if (cold) 2215 panic("mvsata_atapi_phase_complete: cold"); 2216 2217 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) == 2218 WDCWAIT_TOUT) { 2219 /* 10ms not enough, try again in 1 tick */ 2220 if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) { 2221 aprint_error_dev(atac->atac_dev, 2222 "channel %d: wait_for_dsc failed\n", 2223 chp->ch_channel); 2224 sc_xfer->error = XS_TIMEOUT; 2225 mvsata_atapi_reset(chp, xfer); 2226 return; 2227 } else 2228 callout_reset(&chp->ch_callout, 1, 2229 mvsata_atapi_polldsc, xfer); 2230 return; 2231 } 2232 } 2233 2234 /* 2235 * Some drive occasionally set WDCS_ERR with 2236 * "ATA illegal length indication" in the error 2237 * register. If we read some data the sense is valid 2238 * anyway, so don't report the error. 2239 */ 2240 if (chp->ch_status & WDCS_ERR && 2241 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2242 sc_xfer->resid == sc_xfer->datalen)) { 2243 /* save the short sense */ 2244 sc_xfer->error = XS_SHORTSENSE; 2245 sc_xfer->sense.atapi_sense = chp->ch_error; 2246 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2247 /* ask scsipi to send a REQUEST_SENSE */ 2248 sc_xfer->error = XS_BUSY; 2249 sc_xfer->status = SCSI_CHECK; 2250 } else 2251 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2252 ata_dmaerr(drvp, 2253 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2254 sc_xfer->error = XS_RESET; 2255 mvsata_atapi_reset(chp, xfer); 2256 return; 2257 } 2258 } 2259 if (xfer->c_bcount != 0) 2260 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:" 2261 " bcount value is %d after io\n", 2262 device_xname(atac->atac_dev), chp->ch_channel, 2263 xfer->c_drive, xfer->c_bcount)); 2264 #ifdef DIAGNOSTIC 2265 if (xfer->c_bcount < 0) 2266 aprint_error_dev(atac->atac_dev, 2267 "channel %d drive %d: mvsata_atapi_intr:" 2268 " warning: bcount value is %d after io\n", 2269 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2270 #endif 2271 2272 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:" 2273 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2274 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2275 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2276 mvsata_atapi_done(chp, xfer); 2277 } 2278 2279 static void 2280 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2281 { 2282 struct atac_softc *atac = chp->ch_atac; 2283 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2284 int drive = xfer->c_drive; 2285 2286 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2287 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2288 (u_int)xfer->c_flags)); 2289 callout_stop(&chp->ch_callout); 2290 /* mark controller inactive and free the command */ 2291 chp->ch_queue->active_xfer = NULL; 2292 ata_free_xfer(chp, xfer); 2293 2294 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 2295 sc_xfer->error = XS_DRIVER_STUFFUP; 2296 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 2297 wakeup(&chp->ch_queue->active_xfer); 2298 } 2299 2300 DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2301 device_xname(atac->atac_dev), chp->ch_channel)); 2302 scsipi_done(sc_xfer); 2303 DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2304 device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags)); 2305 atastart(chp); 2306 } 2307 2308 static void 2309 mvsata_atapi_polldsc(void *arg) 2310 { 2311 2312 mvsata_atapi_phase_complete(arg); 2313 } 2314 #endif /* NATAPIBUS > 0 */ 2315 2316 2317 /* 2318 * XXXX: Shall we need lock for race condition in mvsata_edma_inqueue{,_gen2}(), 2319 * if supported queuing command by atabus? The race condition will not happen 2320 * if this is called only to the thread of atabus. 2321 */ 2322 static int 2323 mvsata_edma_inqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio, 2324 void *databuf) 2325 { 2326 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2327 struct ata_channel *chp = &mvport->port_ata_channel; 2328 struct eprd *eprd; 2329 bus_addr_t crqb_base_addr; 2330 bus_dmamap_t data_dmamap; 2331 uint32_t reg; 2332 int quetag, erqqip, erqqop, next, rv, i; 2333 2334 DPRINTFN(2, ("%s:%d:%d: mvsata_edma_inqueue:" 2335 " blkno=0x%llx, nbytes=%d, flags=0x%x\n", 2336 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2337 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2338 2339 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2340 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2341 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2342 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2343 next = erqqip; 2344 MVSATA_EDMAQ_INC(next); 2345 if (next == erqqop) 2346 /* queue full */ 2347 return EBUSY; 2348 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2349 /* tag nothing */ 2350 return EBUSY; 2351 DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag)); 2352 2353 rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes, 2354 ata_bio->flags); 2355 if (rv != 0) 2356 return rv; 2357 2358 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2359 2360 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2361 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2362 eprd = mvport->port_reqtbl[quetag].eprd; 2363 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2364 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2365 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2366 2367 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2368 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2369 eprd->eot = htole16(0); 2370 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2371 eprd++; 2372 } 2373 (eprd - 1)->eot |= htole16(EPRD_EOT); 2374 #ifdef MVSATA_DEBUG 2375 if (mvsata_debug >= 3) 2376 mvsata_print_eprd(mvport, quetag); 2377 #endif 2378 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2379 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2380 BUS_DMASYNC_PREWRITE); 2381 2382 /* setup EDMA Command Request Block (CRQB) Data */ 2383 sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio); 2384 #ifdef MVSATA_DEBUG 2385 if (mvsata_debug >= 3) 2386 mvsata_print_crqb(mvport, erqqip); 2387 #endif 2388 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2389 erqqip * sizeof(union mvsata_crqb), 2390 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2391 2392 MVSATA_EDMAQ_INC(erqqip); 2393 2394 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2395 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2396 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2397 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2398 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2399 2400 return 0; 2401 } 2402 2403 static int 2404 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2405 { 2406 struct ata_channel *chp = &mvport->port_ata_channel; 2407 struct crpb *crpb; 2408 struct ata_bio *ata_bio; 2409 struct ata_xfer *xfer; 2410 uint32_t reg; 2411 int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2412 2413 /* First, Sync for Request Queue buffer */ 2414 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2415 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2416 if (mvport->port_prev_erqqop != erqqop) { 2417 const int s = sizeof(union mvsata_crqb); 2418 2419 if (mvport->port_prev_erqqop < erqqop) 2420 n = erqqop - mvport->port_prev_erqqop; 2421 else { 2422 if (erqqop > 0) 2423 bus_dmamap_sync(mvport->port_dmat, 2424 mvport->port_crqb_dmamap, 0, erqqop * s, 2425 BUS_DMASYNC_POSTWRITE); 2426 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2427 } 2428 if (n > 0) 2429 bus_dmamap_sync(mvport->port_dmat, 2430 mvport->port_crqb_dmamap, 2431 mvport->port_prev_erqqop * s, n * s, 2432 BUS_DMASYNC_POSTWRITE); 2433 mvport->port_prev_erqqop = erqqop; 2434 } 2435 2436 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2437 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2438 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2439 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2440 2441 DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2442 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2443 mvport->port, erpqip, erpqop)); 2444 2445 if (erpqop == erpqip) 2446 return 0; 2447 2448 if (erpqop < erpqip) 2449 n = erpqip - erpqop; 2450 else { 2451 if (erpqip > 0) 2452 bus_dmamap_sync(mvport->port_dmat, 2453 mvport->port_crpb_dmamap, 2454 0, erpqip * sizeof(struct crpb), 2455 BUS_DMASYNC_POSTREAD); 2456 n = MVSATA_EDMAQ_LEN - erpqop; 2457 } 2458 if (n > 0) 2459 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2460 erpqop * sizeof(struct crpb), 2461 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2462 2463 prev_erpqop = erpqop; 2464 while (erpqop != erpqip) { 2465 #ifdef MVSATA_DEBUG 2466 if (mvsata_debug >= 3) 2467 mvsata_print_crpb(mvport, erpqop); 2468 #endif 2469 crpb = mvport->port_crpb + erpqop; 2470 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2471 xfer = chp->ch_queue->active_xfer = 2472 mvport->port_reqtbl[quetag].xfer; 2473 #ifdef DIAGNOSTIC 2474 if (xfer == NULL) 2475 panic("unknwon response received: %s:%d:%d: tag 0x%x\n", 2476 device_xname(MVSATA_DEV2(mvport)), 2477 mvport->port_hc->hc, mvport->port, quetag); 2478 #endif 2479 2480 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2481 mvport->port_reqtbl[quetag].eprd_offset, 2482 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2483 2484 chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2485 chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2486 ata_bio = xfer->c_cmd; 2487 ata_bio->error = NOERROR; 2488 ata_bio->r_error = 0; 2489 if (chp->ch_status & WDCS_ERR) 2490 ata_bio->error = ERROR; 2491 if (chp->ch_status & WDCS_BSY) 2492 ata_bio->error = TIMEOUT; 2493 if (chp->ch_error) 2494 ata_bio->error = ERR_DMA; 2495 2496 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2497 mvport->port_reqtbl[quetag].xfer = NULL; 2498 mvsata_quetag_put(mvport, quetag); 2499 MVSATA_EDMAQ_INC(erpqop); 2500 2501 #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */ 2502 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2503 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2504 if (erpqop == erqqip) 2505 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2506 #endif 2507 mvsata_bio_intr(chp, xfer, 1); 2508 if (xfer1 == NULL) 2509 handled++; 2510 else if (xfer == xfer1) { 2511 handled = 1; 2512 break; 2513 } 2514 } 2515 if (prev_erpqop < erpqop) 2516 n = erpqop - prev_erpqop; 2517 else { 2518 if (erpqop > 0) 2519 bus_dmamap_sync(mvport->port_dmat, 2520 mvport->port_crpb_dmamap, 0, 2521 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2522 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2523 } 2524 if (n > 0) 2525 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2526 prev_erpqop * sizeof(struct crpb), 2527 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2528 2529 reg &= ~EDMA_RESQP_ERPQP_MASK; 2530 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2531 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2532 2533 #if 0 /* already cleared ago? */ 2534 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2535 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2536 if (erpqop == erqqip) 2537 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2538 #endif 2539 2540 return handled; 2541 } 2542 2543 static int 2544 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2545 { 2546 struct ata_bio *ata_bio = xfer->c_cmd; 2547 int xtime; 2548 2549 for (xtime = 0; xtime < timeout / 10; xtime++) { 2550 if (mvsata_edma_handle(mvport, xfer)) 2551 return 0; 2552 if (ata_bio->flags & ATA_NOSLEEP) 2553 delay(10000); 2554 else 2555 tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10)); 2556 } 2557 2558 DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer)); 2559 mvsata_edma_rqq_remove(mvport, xfer); 2560 xfer->c_flags |= C_TIMEOU; 2561 return 1; 2562 } 2563 2564 static void 2565 mvsata_edma_timeout(void *arg) 2566 { 2567 struct ata_xfer *xfer = (struct ata_xfer *)arg; 2568 struct ata_channel *chp = xfer->c_chp; 2569 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2570 int s; 2571 2572 s = splbio(); 2573 DPRINTF(("mvsata_edma_timeout: %p\n", xfer)); 2574 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 2575 mvsata_edma_rqq_remove(mvport, xfer); 2576 xfer->c_flags |= C_TIMEOU; 2577 mvsata_bio_intr(chp, xfer, 1); 2578 } 2579 splx(s); 2580 } 2581 2582 static void 2583 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2584 { 2585 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2586 struct ata_bio *ata_bio; 2587 bus_addr_t crqb_base_addr; 2588 int erqqip, i; 2589 2590 /* First, hardware reset, stop EDMA */ 2591 mvsata_hreset_port(mvport); 2592 2593 /* cleanup completed EDMA safely */ 2594 mvsata_edma_handle(mvport, NULL); 2595 2596 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2597 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2598 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2599 if (mvport->port_reqtbl[i].xfer == NULL) 2600 continue; 2601 2602 ata_bio = mvport->port_reqtbl[i].xfer->c_cmd; 2603 if (mvport->port_reqtbl[i].xfer == xfer) { 2604 /* remove xfer from EDMA request queue */ 2605 bus_dmamap_sync(mvport->port_dmat, 2606 mvport->port_eprd_dmamap, 2607 mvport->port_reqtbl[i].eprd_offset, 2608 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2609 mvsata_dma_bufunload(mvport, i, ata_bio->flags); 2610 mvport->port_reqtbl[i].xfer = NULL; 2611 mvsata_quetag_put(mvport, i); 2612 continue; 2613 } 2614 2615 sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio); 2616 erqqip++; 2617 } 2618 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2619 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2620 BUS_DMASYNC_POSTWRITE); 2621 2622 mvsata_edma_config(mvport, mvport->port_edmamode); 2623 mvsata_edma_reset_qptr(mvport); 2624 mvsata_edma_enable(mvport); 2625 2626 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2627 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2628 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2629 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2630 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2631 } 2632 2633 #if NATAPIBUS > 0 2634 static int 2635 mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer, 2636 void *databuf) 2637 { 2638 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2639 struct eprd *eprd; 2640 bus_dmamap_t data_dmamap; 2641 bus_addr_t eprd_addr; 2642 int quetag, rv; 2643 2644 DPRINTFN(2, 2645 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2646 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2647 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2648 2649 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2650 /* tag nothing */ 2651 return EBUSY; 2652 DPRINTFN(2, (" quetag=%d\n", quetag)); 2653 2654 rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen, 2655 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2656 if (rv != 0) 2657 return rv; 2658 2659 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2660 2661 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2662 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2663 eprd = mvport->port_reqtbl[quetag].eprd; 2664 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2665 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2666 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2667 2668 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2669 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2670 eprd->eot = htole16(0); 2671 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2672 eprd++; 2673 } 2674 (eprd - 1)->eot |= htole16(EPRD_EOT); 2675 #ifdef MVSATA_DEBUG 2676 if (mvsata_debug >= 3) 2677 mvsata_print_eprd(mvport, quetag); 2678 #endif 2679 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2680 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2681 BUS_DMASYNC_PREWRITE); 2682 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2683 mvport->port_reqtbl[quetag].eprd_offset; 2684 2685 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2686 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2687 2688 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2689 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2690 else 2691 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2692 2693 return 0; 2694 } 2695 2696 static void 2697 mvsata_bdma_start(struct mvsata_port *mvport) 2698 { 2699 2700 #ifdef MVSATA_DEBUG 2701 if (mvsata_debug >= 3) 2702 mvsata_print_eprd(mvport, 0); 2703 #endif 2704 2705 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2706 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2707 } 2708 #endif 2709 #endif 2710 2711 2712 static int 2713 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2714 { 2715 struct mvsata_softc *sc = mvhc->hc_sc; 2716 struct mvsata_port *mvport; 2717 struct ata_channel *chp; 2718 int channel, rv, i; 2719 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2720 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2721 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2722 2723 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2724 M_ZERO | M_NOWAIT); 2725 if (mvport == NULL) { 2726 aprint_error("%s:%d: can't allocate memory for port %d\n", 2727 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2728 return ENOMEM; 2729 } 2730 2731 mvport->port = port; 2732 mvport->port_hc = mvhc; 2733 mvport->port_edmamode = nodma; 2734 2735 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2736 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 2737 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 2738 if (rv != 0) { 2739 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 2740 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2741 goto fail0; 2742 } 2743 mvport->port_iot = mvhc->hc_iot; 2744 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 2745 &mvport->port_sata_sstatus); 2746 if (rv != 0) { 2747 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 2748 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2749 goto fail0; 2750 } 2751 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 2752 &mvport->port_sata_serror); 2753 if (rv != 0) { 2754 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 2755 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2756 goto fail0; 2757 } 2758 if (sc->sc_rev == gen1) 2759 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2760 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 2761 else 2762 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2763 SATA_SC, 4, &mvport->port_sata_scontrol); 2764 if (rv != 0) { 2765 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 2766 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2767 goto fail0; 2768 } 2769 mvport->port_dmat = sc->sc_dmat; 2770 #ifndef MVSATA_WITHOUTDMA 2771 mvsata_quetag_init(mvport); 2772 #endif 2773 mvhc->hc_ports[port] = mvport; 2774 2775 channel = mvhc->hc * sc->sc_port + port; 2776 chp = &mvport->port_ata_channel; 2777 chp->ch_channel = channel; 2778 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 2779 chp->ch_ndrive = 1; /* SATA is always 1 drive */ 2780 chp->ch_queue = &mvport->port_ata_queue; 2781 sc->sc_ata_channels[channel] = chp; 2782 2783 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 2784 if (rv != 0) 2785 goto fail0; 2786 2787 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 2788 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 2789 if (rv != 0) { 2790 aprint_error( 2791 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 2792 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2793 goto fail0; 2794 } 2795 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 2796 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 2797 if (rv != 0) { 2798 aprint_error( 2799 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 2800 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2801 goto fail1; 2802 } 2803 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 2804 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 2805 if (rv != 0) { 2806 aprint_error( 2807 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 2808 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2809 goto fail2; 2810 } 2811 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 2812 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 2813 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 2814 &mvport->port_reqtbl[i].data_dmamap); 2815 if (rv != 0) { 2816 aprint_error("%s:%d:%d:" 2817 " EDMA data map(%d) create failed: error=%d\n", 2818 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 2819 rv); 2820 goto fail3; 2821 } 2822 } 2823 2824 return 0; 2825 2826 fail3: 2827 for (i--; i >= 0; i--) 2828 bus_dmamap_destroy(mvport->port_dmat, 2829 mvport->port_reqtbl[i].data_dmamap); 2830 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 2831 fail2: 2832 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 2833 fail1: 2834 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 2835 fail0: 2836 return rv; 2837 } 2838 2839 static int 2840 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 2841 { 2842 int hc, port, rv, i; 2843 2844 hc = mvport->port_hc->hc; 2845 port = mvport->port; 2846 2847 /* Create subregion for Shadow Registers Map */ 2848 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2849 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 2850 if (rv != 0) { 2851 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 2852 device_xname(MVSATA_DEV2(mvport)), hc, port); 2853 return rv; 2854 } 2855 wdr->cmd_iot = mvport->port_iot; 2856 2857 /* Once create subregion for each command registers */ 2858 for (i = 0; i < WDC_NREG; i++) { 2859 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2860 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 2861 if (rv != 0) { 2862 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2863 device_xname(MVSATA_DEV2(mvport)), hc, port); 2864 return rv; 2865 } 2866 } 2867 /* Create subregion for Alternate Status register */ 2868 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2869 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 2870 if (rv != 0) { 2871 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2872 device_xname(MVSATA_DEV2(mvport)), hc, port); 2873 return rv; 2874 } 2875 wdr->ctl_iot = mvport->port_iot; 2876 2877 wdc_init_shadow_regs(&mvport->port_ata_channel); 2878 2879 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2880 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 2881 if (rv != 0) { 2882 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 2883 device_xname(MVSATA_DEV2(mvport)), hc, port); 2884 return rv; 2885 } 2886 wdr->sata_iot = mvport->port_iot; 2887 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2888 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 2889 if (rv != 0) { 2890 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 2891 device_xname(MVSATA_DEV2(mvport)), hc, port); 2892 return rv; 2893 } 2894 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2895 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 2896 if (rv != 0) { 2897 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 2898 device_xname(MVSATA_DEV2(mvport)), hc, port); 2899 return rv; 2900 } 2901 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2902 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 2903 if (rv != 0) { 2904 aprint_error("%s:%d:%d: couldn't subregion SError\n", 2905 device_xname(MVSATA_DEV2(mvport)), hc, port); 2906 return rv; 2907 } 2908 2909 return 0; 2910 } 2911 2912 2913 #ifndef MVSATA_WITHOUTDMA 2914 /* 2915 * There are functions to determine Host Queue Tag. 2916 * XXXX: We hope to rotate Tag to facilitate debugging. 2917 */ 2918 2919 static inline void 2920 mvsata_quetag_init(struct mvsata_port *mvport) 2921 { 2922 2923 mvport->port_quetagidx = 0; 2924 } 2925 2926 static inline int 2927 mvsata_quetag_get(struct mvsata_port *mvport) 2928 { 2929 int begin = mvport->port_quetagidx; 2930 2931 do { 2932 if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) { 2933 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2934 return mvport->port_quetagidx; 2935 } 2936 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2937 } while (mvport->port_quetagidx != begin); 2938 2939 return -1; 2940 } 2941 2942 static inline void 2943 mvsata_quetag_put(struct mvsata_port *mvport, int quetag) 2944 { 2945 2946 /* nothing */ 2947 } 2948 2949 static void * 2950 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 2951 bus_dmamap_t *dmamap, size_t size, int write) 2952 { 2953 bus_dma_segment_t seg; 2954 int nseg, rv; 2955 void *kva; 2956 2957 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 2958 BUS_DMA_NOWAIT); 2959 if (rv != 0) { 2960 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 2961 device_xname(MVSATA_DEV2(mvport)), 2962 mvport->port_hc->hc, mvport->port, rv); 2963 goto fail; 2964 } 2965 2966 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 2967 if (rv != 0) { 2968 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 2969 device_xname(MVSATA_DEV2(mvport)), 2970 mvport->port_hc->hc, mvport->port, rv); 2971 goto free; 2972 } 2973 2974 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 2975 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 2976 if (rv != 0) { 2977 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 2978 device_xname(MVSATA_DEV2(mvport)), 2979 mvport->port_hc->hc, mvport->port, rv); 2980 goto unmap; 2981 } 2982 2983 if (!write) 2984 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 2985 2986 return kva; 2987 2988 unmap: 2989 bus_dmamem_unmap(dmat, kva, size); 2990 free: 2991 bus_dmamem_free(dmat, &seg, nseg); 2992 fail: 2993 return NULL; 2994 } 2995 2996 /* ARGSUSED */ 2997 static void 2998 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 2999 bus_dmamap_t dmamap, void *kva) 3000 { 3001 3002 bus_dmamap_unload(dmat, dmamap); 3003 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3004 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3005 } 3006 3007 static int 3008 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3009 size_t datalen, int flags) 3010 { 3011 int rv, lop, sop; 3012 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3013 3014 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3015 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3016 3017 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3018 NULL, BUS_DMA_NOWAIT | lop); 3019 if (rv) { 3020 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3021 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3022 mvport->port, rv); 3023 return rv; 3024 } 3025 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3026 data_dmamap->dm_mapsize, sop); 3027 3028 return 0; 3029 } 3030 3031 static inline void 3032 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3033 { 3034 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3035 3036 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3037 data_dmamap->dm_mapsize, 3038 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3039 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3040 } 3041 #endif 3042 3043 static void 3044 mvsata_hreset_port(struct mvsata_port *mvport) 3045 { 3046 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3047 3048 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3049 3050 delay(25); /* allow reset propagation */ 3051 3052 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3053 3054 mvport->_fix_phy_param._fix_phy(mvport); 3055 3056 if (sc->sc_gen == gen1) 3057 delay(1000); 3058 } 3059 3060 static void 3061 mvsata_reset_port(struct mvsata_port *mvport) 3062 { 3063 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3064 3065 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3066 3067 mvsata_hreset_port(mvport); 3068 3069 if (device_is_a(parent, "pci")) 3070 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3071 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3072 else /* SoC */ 3073 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3074 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3075 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3076 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3077 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3078 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3079 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3080 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3081 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3082 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3083 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3084 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3085 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3086 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3087 3088 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3089 } 3090 3091 static void 3092 mvsata_reset_hc(struct mvsata_hc *mvhc) 3093 { 3094 #if 0 3095 uint32_t val; 3096 #endif 3097 3098 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3099 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3100 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3101 3102 #if 0 /* XXXX needs? */ 3103 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3104 3105 /* 3106 * Keep the SS during power on and the reference clock bits (reset 3107 * sample) 3108 */ 3109 val = MVSATA_HC_READ_4(mvhc, 0x020); 3110 val &= 0x1c1c1c1c; 3111 val |= 0x03030303; 3112 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3113 #endif 3114 } 3115 3116 #ifndef MVSATA_WITHOUTDMA 3117 static void 3118 mvsata_softreset(struct mvsata_port *mvport, int waitok) 3119 { 3120 uint32_t stat; 3121 int i; 3122 3123 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS); 3124 delay(10); 3125 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS); 3126 delay(2000); 3127 3128 if (waitok) { 3129 /* wait maximum 31sec */ 3130 for (i = 31000; i > 0; i--) { 3131 stat = MVSATA_WDC_READ_1(mvport, SRB_CS); 3132 if (!(stat & WDCS_BSY)) 3133 break; 3134 delay(1000); 3135 } 3136 if (i == 0) 3137 aprint_error("%s:%d:%d: soft reset failed\n", 3138 device_xname(MVSATA_DEV2(mvport)), 3139 mvport->port_hc->hc, mvport->port); 3140 } 3141 } 3142 3143 static void 3144 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3145 { 3146 const bus_addr_t crpb_addr = 3147 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3148 const uint32_t crpb_addr_mask = 3149 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3150 3151 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3152 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3153 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3154 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3155 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3156 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3157 } 3158 3159 static inline void 3160 mvsata_edma_enable(struct mvsata_port *mvport) 3161 { 3162 3163 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3164 } 3165 3166 static int 3167 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok) 3168 { 3169 uint32_t status, command; 3170 int ms; 3171 3172 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3173 for (ms = 0; ms < timeout; ms++) { 3174 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3175 if (status & EDMA_S_EDMAIDLE) 3176 break; 3177 if (waitok) 3178 tsleep(&waitok, PRIBIO, "mvsata_edma1", 3179 mstohz(1)); 3180 else 3181 delay(1000); 3182 } 3183 if (ms == timeout) 3184 return EBUSY; 3185 3186 /* The diable bit (eDsEDMA) is self negated. */ 3187 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3188 3189 for ( ; ms < timeout; ms++) { 3190 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3191 if (!(command & EDMA_CMD_EENEDMA)) 3192 break; 3193 if (waitok) 3194 tsleep(&waitok, PRIBIO, "mvsata_edma2", 3195 mstohz(1)); 3196 else 3197 delay(1000); 3198 } 3199 if (ms == timeout) { 3200 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3201 device_xname(MVSATA_DEV2(mvport)), 3202 mvport->port_hc->hc, mvport->port); 3203 return EBUSY; 3204 } 3205 } 3206 return 0; 3207 } 3208 3209 /* 3210 * Set EDMA registers according to mode. 3211 * ex. NCQ/TCQ(queued)/non queued. 3212 */ 3213 static void 3214 mvsata_edma_config(struct mvsata_port *mvport, int mode) 3215 { 3216 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3217 uint32_t reg; 3218 3219 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3220 reg |= EDMA_CFG_RESERVED; 3221 3222 if (mode == ncq) { 3223 if (sc->sc_gen == gen1) { 3224 aprint_error_dev(MVSATA_DEV2(mvport), 3225 "GenI not support NCQ\n"); 3226 return; 3227 } else if (sc->sc_gen == gen2) 3228 reg |= EDMA_CFG_EDEVERR; 3229 reg |= EDMA_CFG_ESATANATVCMDQUE; 3230 } else if (mode == queued) { 3231 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3232 reg |= EDMA_CFG_EQUE; 3233 } else 3234 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3235 3236 if (sc->sc_gen == gen1) 3237 reg |= EDMA_CFG_ERDBSZ; 3238 else if (sc->sc_gen == gen2) 3239 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3240 else if (sc->sc_gen == gen2e) { 3241 device_t parent = device_parent(MVSATA_DEV(sc)); 3242 3243 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3244 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3245 3246 if (device_is_a(parent, "pci")) 3247 reg |= ( 3248 #if NATAPIBUS > 0 3249 EDMA_CFG_EEARLYCOMPLETIONEN | 3250 #endif 3251 EDMA_CFG_ECUTTHROUGHEN | 3252 EDMA_CFG_EWRBUFFERLEN | 3253 EDMA_CFG_ERDBSZEXT); 3254 } 3255 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3256 3257 reg = ( 3258 EDMA_IE_EIORDYERR | 3259 EDMA_IE_ETRANSINT | 3260 EDMA_IE_EDEVCON | 3261 EDMA_IE_EDEVDIS); 3262 if (sc->sc_gen != gen1) 3263 reg |= ( 3264 EDMA_IE_TRANSPROTERR | 3265 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3266 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3267 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3268 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3269 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3270 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3271 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3272 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3273 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3274 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3275 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3276 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3277 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3278 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3279 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3280 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3281 EDMA_IE_ESELFDIS); 3282 3283 if (mode == ncq) 3284 reg |= EDMA_IE_EDEVERR; 3285 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3286 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3287 reg &= ~EDMA_IE_EDEVERR; 3288 if (mode != ncq) 3289 reg |= EDMA_IE_EDEVERR; 3290 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3291 if (sc->sc_gen == gen2e) { 3292 /* 3293 * Clear FISWait4HostRdyEn[0] and [2]. 3294 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3295 * [2]: SDB FIS is received with <ERR> bit set to 1. 3296 */ 3297 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3298 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3299 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3300 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3301 } 3302 3303 mvport->port_edmamode = mode; 3304 } 3305 3306 3307 /* 3308 * Generation dependent functions 3309 */ 3310 3311 static void 3312 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag, 3313 struct ata_bio *ata_bio) 3314 { 3315 struct crqb *crqb; 3316 bus_addr_t eprd_addr; 3317 daddr_t blkno; 3318 uint32_t rw; 3319 uint8_t cmd, head; 3320 int i; 3321 const int drive = 3322 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3323 3324 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3325 mvport->port_reqtbl[quetag].eprd_offset; 3326 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3327 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3328 head = WDSD_LBA; 3329 blkno = ata_bio->blkno; 3330 if (ata_bio->flags & ATA_LBA48) 3331 cmd = atacmd_to48(cmd); 3332 else { 3333 head |= ((ata_bio->blkno >> 24) & 0xf); 3334 blkno &= 0xffffff; 3335 } 3336 crqb = &mvport->port_crqb->crqb + erqqip; 3337 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3338 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3339 crqb->ctrlflg = 3340 htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive)); 3341 i = 0; 3342 if (mvport->port_edmamode == dma) { 3343 if (ata_bio->flags & ATA_LBA48) 3344 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3345 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3346 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3347 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3348 } else { /* ncq/queued */ 3349 3350 /* 3351 * XXXX: Oops, ata command is not correct. And, atabus layer 3352 * has not been supported yet now. 3353 * Queued DMA read/write. 3354 * read/write FPDMAQueued. 3355 */ 3356 3357 if (ata_bio->flags & ATA_LBA48) 3358 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3359 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3360 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3361 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3362 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3363 CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3)); 3364 } 3365 if (ata_bio->flags & ATA_LBA48) { 3366 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3367 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3368 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3369 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3370 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3371 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3372 } 3373 crqb->atacommand[i++] = 3374 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3375 crqb->atacommand[i++] = 3376 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3377 crqb->atacommand[i++] = 3378 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3379 crqb->atacommand[i++] = 3380 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3381 crqb->atacommand[i++] = htole16( 3382 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3383 CRQB_ATACOMMAND_LAST); 3384 } 3385 #endif 3386 3387 static uint32_t 3388 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3389 { 3390 struct mvsata_hc *hc = mvport->port_hc; 3391 uint32_t reg; 3392 3393 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3394 /* 3395 * [12:11] : pre 3396 * [7:5] : amps 3397 */ 3398 return reg & 0x000018e0; 3399 } 3400 3401 static void 3402 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3403 { 3404 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3405 struct mvsata_hc *mvhc = mvport->port_hc; 3406 uint32_t reg; 3407 int port = mvport->port, fix_apm_sq = 0; 3408 3409 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3410 if (sc->sc_rev == 0x01) 3411 fix_apm_sq = 1; 3412 } else { 3413 if (sc->sc_rev == 0x00) 3414 fix_apm_sq = 1; 3415 } 3416 3417 if (fix_apm_sq) { 3418 /* 3419 * Disable auto-power management 3420 * 88SX50xx FEr SATA#12 3421 */ 3422 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3423 reg |= (1 << 19); 3424 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3425 3426 /* 3427 * Fix squelch threshold 3428 * 88SX50xx FEr SATA#9 3429 */ 3430 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3431 reg &= ~0x3; 3432 reg |= 0x1; 3433 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3434 } 3435 3436 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3437 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3438 reg &= ~0x000018e0; /* pre and amps mask */ 3439 reg |= mvport->_fix_phy_param.pre_amps; 3440 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3441 } 3442 3443 static void 3444 mvsata_devconn_gen1(struct mvsata_port *mvport) 3445 { 3446 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3447 3448 /* Fix for 88SX50xx FEr SATA#2 */ 3449 mvport->_fix_phy_param._fix_phy(mvport); 3450 3451 /* If disk is connected, then enable the activity LED */ 3452 if (sc->sc_rev == 0x03) { 3453 /* XXXXX */ 3454 } 3455 } 3456 3457 static uint32_t 3458 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3459 { 3460 uint32_t reg; 3461 3462 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3463 /* 3464 * [10:8] : amps 3465 * [7:5] : pre 3466 */ 3467 return reg & 0x000007e0; 3468 } 3469 3470 static void 3471 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3472 { 3473 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3474 uint32_t reg; 3475 3476 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3477 sc->sc_gen == gen2e) { 3478 /* 3479 * Fix for 3480 * 88SX60X1 FEr SATA #23 3481 * 88SX6042/88SX7042 FEr SATA #23 3482 * 88F5182 FEr #SATA-S13 3483 * 88F5082 FEr #SATA-S13 3484 */ 3485 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3486 reg &= ~(1 << 16); 3487 reg |= (1 << 31); 3488 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3489 3490 delay(200); 3491 3492 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3493 reg &= ~((1 << 16) | (1 << 31)); 3494 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3495 3496 delay(200); 3497 } 3498 3499 /* Fix values in PHY Mode 3 Register.*/ 3500 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3501 reg &= ~0x7F900000; 3502 reg |= 0x2A800000; 3503 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3504 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3505 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3506 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3507 reg &= ~0x0000001c; 3508 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3509 3510 /* 3511 * Fix values in PHY Mode 4 Register. 3512 * 88SX60x1 FEr SATA#10 3513 * 88F5182 GL #SATA-S10 3514 * 88F5082 GL #SATA-S10 3515 */ 3516 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3517 sc->sc_gen == gen2e) { 3518 uint32_t tmp = 0; 3519 3520 /* 88SX60x1 FEr SATA #13 */ 3521 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3522 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3523 3524 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3525 reg |= (1 << 0); 3526 reg &= ~(1 << 1); 3527 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3528 if (sc->sc_gen == gen2e) { 3529 reg &= ~0x5de3fffc; 3530 reg |= (1 << 2); 3531 } 3532 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3533 3534 /* 88SX60x1 FEr SATA #13 */ 3535 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3536 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3537 } 3538 3539 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3540 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3541 reg &= ~0x000007e0; /* pre and amps mask */ 3542 reg |= mvport->_fix_phy_param.pre_amps; 3543 reg &= ~(1 << 16); 3544 if (sc->sc_gen == gen2e) { 3545 /* 3546 * according to mvSata 3.6.1, some IIE values are fixed. 3547 * some reserved fields must be written with fixed values. 3548 */ 3549 reg &= ~0xC30FF01F; 3550 reg |= 0x0000900F; 3551 } 3552 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3553 } 3554 3555 #ifndef MVSATA_WITHOUTDMA 3556 static void 3557 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag, 3558 struct ata_bio *ata_bio) 3559 { 3560 struct crqb_gen2e *crqb; 3561 bus_addr_t eprd_addr; 3562 daddr_t blkno; 3563 uint32_t ctrlflg, rw; 3564 uint8_t cmd, head; 3565 const int drive = 3566 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3567 3568 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3569 mvport->port_reqtbl[quetag].eprd_offset; 3570 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3571 ctrlflg = (rw | CRQB_CDEVICEQUETAG(quetag) | CRQB_CPMPORT(drive) | 3572 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag)); 3573 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3574 head = WDSD_LBA; 3575 blkno = ata_bio->blkno; 3576 if (ata_bio->flags & ATA_LBA48) 3577 cmd = atacmd_to48(cmd); 3578 else { 3579 head |= ((ata_bio->blkno >> 24) & 0xf); 3580 blkno &= 0xffffff; 3581 } 3582 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3583 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3584 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3585 crqb->ctrlflg = htole32(ctrlflg); 3586 if (mvport->port_edmamode == dma) { 3587 crqb->atacommand[0] = htole32(cmd << 16); 3588 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3589 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff)); 3590 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3591 } else { /* ncq/queued */ 3592 3593 /* 3594 * XXXX: Oops, ata command is not correct. And, atabus layer 3595 * has not been supported yet now. 3596 * Queued DMA read/write. 3597 * read/write FPDMAQueued. 3598 */ 3599 3600 crqb->atacommand[0] = htole32( 3601 (cmd << 16) | ((ata_bio->nblks & 0xff) << 24)); 3602 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3603 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) | 3604 ((ata_bio->nblks >> 8) & 0xff)); 3605 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3606 crqb->atacommand[3] = htole32(quetag << 3); 3607 } 3608 } 3609 3610 3611 #ifdef MVSATA_DEBUG 3612 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3613 do { \ 3614 int _i; \ 3615 u_char *_p = (p); \ 3616 \ 3617 printf(#type "(%d)", (n)); \ 3618 for (_i = 0; _i < (size); _i++, _p++) { \ 3619 if (_i % 16 == 0) \ 3620 printf("\n "); \ 3621 printf(" %02x", *_p); \ 3622 } \ 3623 printf("\n"); \ 3624 } while (0 /* CONSTCOND */) 3625 3626 static void 3627 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3628 { 3629 3630 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3631 n, (u_char *)(mvport->port_crqb + n)); 3632 } 3633 3634 static void 3635 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3636 { 3637 3638 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3639 n, (u_char *)(mvport->port_crpb + n)); 3640 } 3641 3642 static void 3643 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3644 { 3645 struct eprd *eprd; 3646 int i = 0; 3647 3648 eprd = mvport->port_reqtbl[n].eprd; 3649 while (1 /*CONSTCOND*/) { 3650 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3651 i, (u_char *)eprd); 3652 if (eprd->eot & EPRD_EOT) 3653 break; 3654 eprd++; 3655 i++; 3656 } 3657 } 3658 #endif 3659 #endif 3660
Indexes created Wed Sep 24 14:09:57 GMT 2025