mvsata.c revision 1.56
1 /* $NetBSD: mvsata.c,v 1.56 2020/04/13 10:49:34 jdolecek Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.56 2020/04/13 10:49:34 jdolecek Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 /* 62 * Nice things to do: 63 * 64 * - MSI/MSI-X support - though on some models MSI actually doesn't work 65 * even when hardware claims to support it, according to FreeBSD/OpenBSD 66 * - move pci-specific code to the pci attach code 67 * - mvsata(4) use 64-bit DMA on hardware which claims to support it 68 * - e.g. AHA1430SA does not really work, crash in mvsata_intr() on boot 69 */ 70 71 #include <dev/ic/mvsatareg.h> 72 #include <dev/ic/mvsatavar.h> 73 74 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 75 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 76 77 #define MVSATA_HC_READ_4(hc, reg) \ 78 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 79 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 80 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 81 #define MVSATA_EDMA_READ_4(mvport, reg) \ 82 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 83 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 84 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 85 #define MVSATA_WDC_READ_2(mvport, reg) \ 86 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 87 SHADOW_REG_BLOCK_OFFSET + (reg)) 88 #define MVSATA_WDC_READ_1(mvport, reg) \ 89 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 90 SHADOW_REG_BLOCK_OFFSET + (reg)) 91 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 92 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 93 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 94 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 95 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 96 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 97 98 #ifdef MVSATA_DEBUG 99 100 #define DEBUG_INTR 0x01 101 #define DEBUG_XFERS 0x02 102 #define DEBUG_FUNCS 0x08 103 #define DEBUG_PROBE 0x10 104 105 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 106 int mvsata_debug = 0; 107 #else 108 #define DPRINTF(n,x) 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 113 sending a cmd */ 114 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 115 116 #define MVSATA_MAX_SEGS (MAXPHYS / PAGE_SIZE + 1) 117 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * MVSATA_MAX_SEGS) 118 119 120 static void mvsata_probe_drive(struct ata_channel *); 121 122 #ifndef MVSATA_WITHOUTDMA 123 static void mvsata_reset_channel(struct ata_channel *, int); 124 static void mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 125 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 126 static void mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 127 static int mvsata_addref(struct ata_drive_datas *); 128 static void mvsata_delref(struct ata_drive_datas *); 129 static void mvsata_killpending(struct ata_drive_datas *); 130 131 #if NATAPIBUS > 0 132 static void mvsata_atapibus_attach(struct atabus_softc *); 133 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 134 scsipi_adapter_req_t, void *); 135 static void mvsata_atapi_minphys(struct buf *); 136 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 137 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 138 #endif 139 #endif 140 141 static void mvsata_setup_channel(struct ata_channel *); 142 143 #ifndef MVSATA_WITHOUTDMA 144 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 145 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 146 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 147 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 148 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 149 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 150 int); 151 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 152 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 153 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 154 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 155 int); 156 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 157 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 158 #if NATAPIBUS > 0 159 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 160 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 161 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 162 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 163 int); 164 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 165 static void mvsata_atapi_phase_complete(struct ata_xfer *, int); 166 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 167 static void mvsata_atapi_polldsc(void *); 168 #endif 169 170 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 171 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 172 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 173 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 174 #if NATAPIBUS > 0 175 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 176 static void mvsata_bdma_start(struct mvsata_port *); 177 #endif 178 #endif 179 180 static int mvsata_nondma_handle(struct mvsata_port *); 181 182 static int mvsata_port_init(struct mvsata_hc *, int); 183 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 184 #ifndef MVSATA_WITHOUTDMA 185 static void mvsata_channel_recover(struct ata_channel *, int, uint32_t); 186 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 187 bus_dmamap_t *, size_t, int); 188 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 189 bus_dmamap_t, void *); 190 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 191 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 192 #endif 193 194 static void mvsata_hreset_port(struct mvsata_port *); 195 static void mvsata_reset_port(struct mvsata_port *); 196 static void mvsata_reset_hc(struct mvsata_hc *); 197 static uint32_t mvsata_softreset(struct mvsata_port *, int); 198 #ifndef MVSATA_WITHOUTDMA 199 static void mvsata_edma_reset_qptr(struct mvsata_port *); 200 static inline void mvsata_edma_enable(struct mvsata_port *); 201 static void mvsata_edma_disable(struct mvsata_port *, int, int); 202 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 203 204 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 205 struct ata_xfer *); 206 #endif 207 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 208 static void mvsata_fix_phy_gen1(struct mvsata_port *); 209 static void mvsata_devconn_gen1(struct mvsata_port *); 210 211 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 212 static void mvsata_fix_phy_gen2(struct mvsata_port *); 213 #ifndef MVSATA_WITHOUTDMA 214 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 215 struct ata_xfer *); 216 217 #ifdef MVSATA_DEBUG 218 static void mvsata_print_crqb(struct mvsata_port *, int); 219 static void mvsata_print_crpb(struct mvsata_port *, int); 220 static void mvsata_print_eprd(struct mvsata_port *, int); 221 #endif 222 223 static const struct ata_bustype mvsata_ata_bustype = { 224 SCSIPI_BUSTYPE_ATA, 225 mvsata_bio, 226 mvsata_reset_drive, 227 mvsata_reset_channel, 228 mvsata_exec_command, 229 ata_get_params, 230 mvsata_addref, 231 mvsata_delref, 232 mvsata_killpending, 233 mvsata_channel_recover, 234 }; 235 236 #if NATAPIBUS > 0 237 static const struct scsipi_bustype mvsata_atapi_bustype = { 238 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 239 .bustype_cmd = atapi_scsipi_cmd, 240 .bustype_interpret_sense = atapi_interpret_sense, 241 .bustype_printaddr = atapi_print_addr, 242 .bustype_kill_pending = mvsata_atapi_kill_pending, 243 .bustype_async_event_xfer_mode = NULL, 244 }; 245 #endif /* NATAPIBUS */ 246 #endif 247 248 static void 249 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 250 { 251 uint32_t ifctl; 252 253 KASSERT(pmpport < PMP_MAX_DRIVES); 254 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 255 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 256 panic("EDMA enabled"); 257 } 258 #endif 259 260 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 261 ifctl &= ~0xf; 262 ifctl |= pmpport; 263 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 264 } 265 266 int 267 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 268 int (*mvsata_sreset)(struct mvsata_softc *), 269 int (*mvsata_misc_reset)(struct mvsata_softc *), 270 int read_pre_amps) 271 { 272 struct mvsata_hc *mvhc; 273 struct mvsata_port *mvport; 274 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 275 void (*_fix_phy)(struct mvsata_port *) = NULL; 276 #ifndef MVSATA_WITHOUTDMA 277 void (*edma_setup_crqb) 278 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 279 #endif 280 int hc, port, channel; 281 282 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 283 (product->generation == gen1) ? "I" : 284 ((product->generation == gen2) ? "II" : "IIe"), 285 product->hc, product->port); 286 287 288 switch (product->generation) { 289 case gen1: 290 mvsata_sreset = NULL; 291 read_pre_amps = 1; /* MUST */ 292 read_preamps = mvsata_read_preamps_gen1; 293 _fix_phy = mvsata_fix_phy_gen1; 294 #ifndef MVSATA_WITHOUTDMA 295 edma_setup_crqb = mvsata_edma_setup_crqb; 296 #endif 297 break; 298 299 case gen2: 300 read_preamps = mvsata_read_preamps_gen2; 301 _fix_phy = mvsata_fix_phy_gen2; 302 #ifndef MVSATA_WITHOUTDMA 303 edma_setup_crqb = mvsata_edma_setup_crqb; 304 #endif 305 break; 306 307 case gen2e: 308 read_preamps = mvsata_read_preamps_gen2; 309 _fix_phy = mvsata_fix_phy_gen2; 310 #ifndef MVSATA_WITHOUTDMA 311 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 312 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 313 #endif 314 break; 315 } 316 317 sc->sc_gen = product->generation; 318 sc->sc_hc = product->hc; 319 sc->sc_port = product->port; 320 sc->sc_flags = product->flags; 321 322 #ifdef MVSATA_WITHOUTDMA 323 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 324 #else 325 sc->sc_edma_setup_crqb = edma_setup_crqb; 326 sc->sc_wdcdev.sc_atac.atac_cap |= 327 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 328 #endif 329 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 330 #ifdef MVSATA_WITHOUTDMA 331 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 333 #else 334 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 335 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 336 #endif 337 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 338 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 339 #ifndef MVSATA_WITHOUTDMA 340 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 341 #if NATAPIBUS > 0 342 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 343 #endif 344 #endif 345 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 346 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 347 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 348 349 sc->sc_wdc_regs = 350 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 351 M_DEVBUF, M_WAITOK); 352 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 353 354 for (hc = 0; hc < sc->sc_hc; hc++) { 355 mvhc = &sc->sc_hcs[hc]; 356 mvhc->hc = hc; 357 mvhc->hc_sc = sc; 358 mvhc->hc_iot = sc->sc_iot; 359 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 360 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 361 &mvhc->hc_ioh)) { 362 aprint_error_dev(MVSATA_DEV(sc), 363 "can't subregion SATAHC %d registers\n", hc); 364 continue; 365 } 366 367 for (port = 0; port < sc->sc_port; port++) 368 if (mvsata_port_init(mvhc, port) == 0) { 369 int pre_amps; 370 371 mvport = mvhc->hc_ports[port]; 372 pre_amps = read_pre_amps ? 373 read_preamps(mvport) : 0x00000720; 374 mvport->_fix_phy_param.pre_amps = pre_amps; 375 mvport->_fix_phy_param._fix_phy = _fix_phy; 376 377 if (!mvsata_sreset) 378 mvsata_reset_port(mvport); 379 } 380 381 if (!mvsata_sreset) 382 mvsata_reset_hc(mvhc); 383 } 384 if (mvsata_sreset) 385 mvsata_sreset(sc); 386 387 if (mvsata_misc_reset) 388 mvsata_misc_reset(sc); 389 390 for (hc = 0; hc < sc->sc_hc; hc++) 391 for (port = 0; port < sc->sc_port; port++) { 392 mvport = sc->sc_hcs[hc].hc_ports[port]; 393 if (mvport == NULL) 394 continue; 395 if (mvsata_sreset) 396 mvport->_fix_phy_param._fix_phy(mvport); 397 } 398 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 399 wdcattach(sc->sc_ata_channels[channel]); 400 401 return 0; 402 } 403 404 int 405 mvsata_intr(struct mvsata_hc *mvhc) 406 { 407 struct mvsata_softc *sc = mvhc->hc_sc; 408 struct mvsata_port *mvport; 409 uint32_t cause; 410 int port, handled = 0; 411 412 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 413 414 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 415 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 416 417 if (cause & SATAHC_IC_SAINTCOAL) 418 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 419 cause &= ~SATAHC_IC_SAINTCOAL; 420 421 for (port = 0; port < sc->sc_port; port++) { 422 mvport = mvhc->hc_ports[port]; 423 424 if (cause & SATAHC_IC_DONE(port)) { 425 #ifndef MVSATA_WITHOUTDMA 426 handled = mvsata_edma_handle(mvport, NULL); 427 #endif 428 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 429 ~SATAHC_IC_DONE(port)); 430 } 431 432 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 433 (void) mvsata_nondma_handle(mvport); 434 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 435 ~SATAHC_IC_SADEVINTERRUPT(port)); 436 handled = 1; 437 } 438 } 439 440 return handled; 441 } 442 443 static int 444 mvsata_nondma_handle(struct mvsata_port *mvport) 445 { 446 struct ata_channel *chp = &mvport->port_ata_channel; 447 struct ata_xfer *xfer; 448 int ret; 449 450 /* 451 * The chip doesn't support several pending non-DMA commands, 452 * and the ata middle layer never issues several non-NCQ commands, 453 * so there must be exactly one active command at this moment. 454 */ 455 xfer = ata_queue_get_active_xfer(chp); 456 if (xfer == NULL) { 457 /* Can happen after error recovery, ignore */ 458 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 459 ("%s:%d: %s: intr without xfer\n", 460 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 461 __func__)); 462 return 0; 463 } 464 465 ret = xfer->ops->c_intr(chp, xfer, 1); 466 return (ret); 467 } 468 469 int 470 mvsata_error(struct mvsata_port *mvport) 471 { 472 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 473 uint32_t cause; 474 475 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 476 /* 477 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 478 * in EDMA_IEC. 479 */ 480 if (cause & EDMA_IE_SERRINT) { 481 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 482 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 483 } 484 if (cause & EDMA_IE_ETRANSINT) { 485 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 486 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 487 } 488 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 489 490 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 491 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 492 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 493 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 494 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 495 496 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 497 if (!cause) 498 return 0; 499 500 if (cause & EDMA_IE_EDEVDIS) { 501 aprint_normal("%s:%d:%d: device disconnect\n", 502 device_xname(MVSATA_DEV2(mvport)), 503 mvport->port_hc->hc, mvport->port); 504 } 505 if (cause & EDMA_IE_EDEVCON) { 506 if (sc->sc_gen == gen1) 507 mvsata_devconn_gen1(mvport); 508 509 DPRINTF(DEBUG_INTR, (" device connected\n")); 510 } 511 512 #ifndef MVSATA_WITHOUTDMA 513 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 514 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 515 switch (mvport->port_edmamode_curr) { 516 case dma: 517 case queued: 518 case ncq: 519 mvsata_edma_reset_qptr(mvport); 520 mvsata_edma_enable(mvport); 521 if (cause & EDMA_IE_EDEVERR) 522 break; 523 524 /* FALLTHROUGH */ 525 526 case nodma: 527 default: 528 DPRINTF(DEBUG_INTR, 529 ("%s:%d:%d: EDMA self disable happen 0x%x\n", 530 device_xname(MVSATA_DEV2(mvport)), 531 mvport->port_hc->hc, mvport->port, cause)); 532 break; 533 } 534 } 535 #endif 536 if (cause & EDMA_IE_ETRANSINT) { 537 /* hot plug the Port Multiplier */ 538 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 539 device_xname(MVSATA_DEV2(mvport)), 540 mvport->port_hc->hc, mvport->port); 541 } 542 if (cause & EDMA_IE_EDEVERR) { 543 struct ata_channel *chp = &mvport->port_ata_channel; 544 545 aprint_error("%s:%d:%d: device error, recovering\n", 546 device_xname(MVSATA_DEV2(mvport)), 547 mvport->port_hc->hc, mvport->port); 548 549 ata_channel_lock(chp); 550 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, 551 ATACH_ERR_ST(0, WDCS_ERR)); 552 ata_channel_unlock(chp); 553 } 554 555 return 1; 556 } 557 558 #ifndef MVSATA_WITHOUTDMA 559 static void 560 mvsata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 561 { 562 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 563 int drive; 564 565 ata_channel_lock_owned(chp); 566 567 if (chp->ch_ndrives > PMP_PORT_CTL) { 568 /* Get PM port number for the device in error. This device 569 * doesn't seem to have dedicated register for this, so just 570 * assume last selected port was the one. */ 571 /* XXX FIS-based switching */ 572 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 573 } else 574 drive = 0; 575 576 /* 577 * Controller doesn't need any special action. Simply execute 578 * READ LOG EXT for NCQ to unblock device processing, then continue 579 * as if nothing happened. 580 */ 581 582 ata_recovery_resume(chp, drive, tfd, AT_POLL); 583 584 /* Drive unblocked, back to normal operation */ 585 return; 586 } 587 #endif /* !MVSATA_WITHOUTDMA */ 588 589 /* 590 * ATA callback entry points 591 */ 592 593 static void 594 mvsata_probe_drive(struct ata_channel *chp) 595 { 596 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 597 uint32_t sstat, sig; 598 599 ata_channel_lock(chp); 600 601 sstat = sata_reset_interface(chp, mvport->port_iot, 602 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 603 switch (sstat) { 604 case SStatus_DET_DEV: 605 mvsata_pmp_select(mvport, PMP_PORT_CTL); 606 sig = mvsata_softreset(mvport, AT_WAIT); 607 sata_interpret_sig(chp, 0, sig); 608 break; 609 default: 610 break; 611 } 612 613 ata_channel_unlock(chp); 614 } 615 616 #ifndef MVSATA_WITHOUTDMA 617 static void 618 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 619 { 620 struct ata_channel *chp = drvp->chnl_softc; 621 struct mvsata_port *mvport = (struct mvsata_port *)chp; 622 uint32_t edma_c; 623 uint32_t sig; 624 625 ata_channel_lock_owned(chp); 626 627 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 628 629 DPRINTF(DEBUG_FUNCS, 630 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 631 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 632 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 633 634 if (edma_c & EDMA_CMD_EENEDMA) 635 mvsata_edma_disable(mvport, 10000, flags); 636 637 mvsata_pmp_select(mvport, drvp->drive); 638 639 sig = mvsata_softreset(mvport, flags); 640 641 if (sigp) 642 *sigp = sig; 643 644 if (edma_c & EDMA_CMD_EENEDMA) { 645 mvsata_edma_reset_qptr(mvport); 646 mvsata_edma_enable(mvport); 647 } 648 } 649 650 static void 651 mvsata_reset_channel(struct ata_channel *chp, int flags) 652 { 653 struct mvsata_port *mvport = (struct mvsata_port *)chp; 654 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 655 uint32_t sstat, ctrl; 656 657 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 658 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 659 660 ata_channel_lock_owned(chp); 661 662 mvsata_hreset_port(mvport); 663 sstat = sata_reset_interface(chp, mvport->port_iot, 664 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 665 666 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 667 sc->sc_gen != gen1) { 668 /* Downgrade to GenI */ 669 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 670 SControl_DET_DISABLE; 671 672 bus_space_write_4(mvport->port_iot, 673 mvport->port_sata_scontrol, 0, val); 674 675 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 676 ctrl &= ~(1 << 17); /* Disable GenII */ 677 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 678 679 mvsata_hreset_port(mvport); 680 sata_reset_interface(chp, mvport->port_iot, 681 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 682 flags); 683 } 684 685 ata_kill_active(chp, KILL_RESET, flags); 686 687 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 688 mvsata_edma_reset_qptr(mvport); 689 mvsata_edma_enable(mvport); 690 } 691 692 static int 693 mvsata_addref(struct ata_drive_datas *drvp) 694 { 695 696 return 0; 697 } 698 699 static void 700 mvsata_delref(struct ata_drive_datas *drvp) 701 { 702 703 return; 704 } 705 706 static void 707 mvsata_killpending(struct ata_drive_datas *drvp) 708 { 709 710 return; 711 } 712 713 #if NATAPIBUS > 0 714 static void 715 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 716 { 717 struct ata_channel *chp = ata_sc->sc_chan; 718 struct atac_softc *atac = chp->ch_atac; 719 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 720 struct scsipi_channel *chan = &chp->ch_atapi_channel; 721 722 /* 723 * Fill in the scsipi_adapter. 724 */ 725 adapt->adapt_dev = atac->atac_dev; 726 adapt->adapt_nchannels = atac->atac_nchannels; 727 adapt->adapt_request = mvsata_atapi_scsipi_request; 728 adapt->adapt_minphys = mvsata_atapi_minphys; 729 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 730 731 /* 732 * Fill in the scsipi_channel. 733 */ 734 memset(chan, 0, sizeof(*chan)); 735 chan->chan_adapter = adapt; 736 chan->chan_bustype = &mvsata_atapi_bustype; 737 chan->chan_channel = chp->ch_channel; 738 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 739 chan->chan_openings = 1; 740 chan->chan_max_periph = 1; 741 chan->chan_ntargets = 1; 742 chan->chan_nluns = 1; 743 744 chp->atapibus = 745 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 746 } 747 748 static void 749 mvsata_atapi_minphys(struct buf *bp) 750 { 751 752 if (bp->b_bcount > MAXPHYS) 753 bp->b_bcount = MAXPHYS; 754 minphys(bp); 755 } 756 757 static void 758 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 759 { 760 struct scsipi_channel *chan = sc->sc_channel; 761 struct scsipi_periph *periph; 762 struct ataparams ids; 763 struct ataparams *id = &ids; 764 struct mvsata_softc *mvc = 765 device_private(chan->chan_adapter->adapt_dev); 766 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 767 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 768 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 769 struct scsipibus_attach_args sa; 770 char serial_number[21], model[41], firmware_revision[9]; 771 int s; 772 773 /* skip if already attached */ 774 if (scsipi_lookup_periph(chan, target, 0) != NULL) 775 return; 776 777 /* if no ATAPI device detected at attach time, skip */ 778 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 779 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 780 " drive %d not present\n", 781 device_xname(atac->atac_dev), chp->ch_channel, target)); 782 return; 783 } 784 785 /* Some ATAPI devices need a bit more time after software reset. */ 786 delay(5000); 787 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 788 #ifdef ATAPI_DEBUG_PROBE 789 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 790 device_xname(sc->sc_dev), target, 791 id->atap_config & ATAPI_CFG_CMD_MASK, 792 id->atap_config & ATAPI_CFG_DRQ_MASK); 793 #endif 794 periph = scsipi_alloc_periph(M_WAITOK); 795 periph->periph_dev = NULL; 796 periph->periph_channel = chan; 797 periph->periph_switch = &atapi_probe_periphsw; 798 periph->periph_target = target; 799 periph->periph_lun = 0; 800 periph->periph_quirks = PQUIRK_ONLYBIG; 801 802 #ifdef SCSIPI_DEBUG 803 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 804 SCSIPI_DEBUG_TARGET == target) 805 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 806 #endif 807 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 808 if (id->atap_config & ATAPI_CFG_REMOV) 809 periph->periph_flags |= PERIPH_REMOVABLE; 810 if (periph->periph_type == T_SEQUENTIAL) { 811 s = splbio(); 812 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 813 splx(s); 814 } 815 816 sa.sa_periph = periph; 817 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 818 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 819 T_REMOV : T_FIXED; 820 strnvisx(model, sizeof(model), id->atap_model, 40, 821 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 822 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 823 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 824 strnvisx(firmware_revision, sizeof(firmware_revision), 825 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 826 sa.sa_inqbuf.vendor = model; 827 sa.sa_inqbuf.product = serial_number; 828 sa.sa_inqbuf.revision = firmware_revision; 829 830 /* 831 * Determine the operating mode capabilities of the device. 832 */ 833 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 834 periph->periph_cap |= PERIPH_CAP_CMD16; 835 /* XXX This is gross. */ 836 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 837 838 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 839 840 if (drvp->drv_softc) 841 ata_probe_caps(drvp); 842 else { 843 s = splbio(); 844 drvp->drive_type = ATA_DRIVET_NONE; 845 splx(s); 846 } 847 } else { 848 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 849 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 850 device_xname(atac->atac_dev), chp->ch_channel, target)); 851 s = splbio(); 852 drvp->drive_type = ATA_DRIVET_NONE; 853 splx(s); 854 } 855 } 856 857 /* 858 * Kill off all pending xfers for a periph. 859 * 860 * Must be called at splbio(). 861 */ 862 static void 863 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 864 { 865 struct atac_softc *atac = 866 device_private(periph->periph_channel->chan_adapter->adapt_dev); 867 struct ata_channel *chp = 868 atac->atac_channels[periph->periph_channel->chan_channel]; 869 870 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 871 } 872 #endif /* NATAPIBUS > 0 */ 873 #endif /* MVSATA_WITHOUTDMA */ 874 875 876 /* 877 * mvsata_setup_channel() 878 * Setup EDMA registers and prepare/purge DMA resources. 879 * We assuming already stopped the EDMA. 880 */ 881 static void 882 mvsata_setup_channel(struct ata_channel *chp) 883 { 884 #ifndef MVSATA_WITHOUTDMA 885 struct mvsata_port *mvport = (struct mvsata_port *)chp; 886 struct ata_drive_datas *drvp; 887 int drive, s; 888 uint32_t edma_mode = nodma; 889 int i; 890 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 891 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 892 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 893 894 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 895 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 896 897 for (drive = 0; drive < chp->ch_ndrives; drive++) { 898 drvp = &chp->ch_drive[drive]; 899 900 /* If no drive, skip */ 901 if (drvp->drive_type == ATA_DRIVET_NONE) 902 continue; 903 904 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 905 /* use Ultra/DMA */ 906 s = splbio(); 907 drvp->drive_flags &= ~ATA_DRIVE_DMA; 908 splx(s); 909 } 910 911 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 912 if (drvp->drive_flags & ATA_DRIVE_NCQ) 913 edma_mode = ncq; 914 else if (drvp->drive_type == ATA_DRIVET_ATA) 915 edma_mode = dma; 916 } 917 } 918 919 DPRINTF(DEBUG_FUNCS, 920 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 921 922 if (edma_mode == nodma) { 923 no_edma: 924 if (mvport->port_crqb != NULL) 925 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 926 mvport->port_crqb_dmamap, mvport->port_crqb); 927 if (mvport->port_crpb != NULL) 928 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 929 mvport->port_crpb_dmamap, mvport->port_crpb); 930 if (mvport->port_eprd != NULL) 931 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 932 mvport->port_eprd_dmamap, mvport->port_eprd); 933 934 return; 935 } 936 937 if (mvport->port_crqb == NULL) 938 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 939 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 940 if (mvport->port_crpb == NULL) 941 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 942 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 943 if (mvport->port_eprd == NULL) { 944 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 945 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 946 1); 947 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 948 mvport->port_reqtbl[i].eprd_offset = 949 i * MVSATA_EPRD_MAX_SIZE; 950 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 951 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 952 } 953 } 954 955 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 956 mvport->port_eprd == NULL) { 957 aprint_error_dev(MVSATA_DEV2(mvport), 958 "channel %d: can't use EDMA\n", chp->ch_channel); 959 s = splbio(); 960 for (drive = 0; drive < chp->ch_ndrives; drive++) { 961 drvp = &chp->ch_drive[drive]; 962 963 /* If no drive, skip */ 964 if (drvp->drive_type == ATA_DRIVET_NONE) 965 continue; 966 967 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 968 } 969 splx(s); 970 goto no_edma; 971 } 972 973 mvsata_edma_config(mvport, edma_mode); 974 mvsata_edma_reset_qptr(mvport); 975 mvsata_edma_enable(mvport); 976 #endif 977 } 978 979 #ifndef MVSATA_WITHOUTDMA 980 static const struct ata_xfer_ops mvsata_bio_xfer_ops = { 981 .c_start = mvsata_bio_start, 982 .c_intr = mvsata_bio_intr, 983 .c_poll = mvsata_bio_poll, 984 .c_abort = mvsata_bio_done, 985 .c_kill_xfer = mvsata_bio_kill_xfer, 986 }; 987 988 static void 989 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 990 { 991 struct ata_channel *chp = drvp->chnl_softc; 992 struct atac_softc *atac = chp->ch_atac; 993 struct ata_bio *ata_bio = &xfer->c_bio; 994 995 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 996 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 997 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 998 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 999 1000 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1001 ata_bio->flags |= ATA_POLL; 1002 if (ata_bio->flags & ATA_POLL) 1003 xfer->c_flags |= C_POLL; 1004 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1005 (ata_bio->flags & ATA_SINGLE) == 0) 1006 xfer->c_flags |= C_DMA; 1007 xfer->c_drive = drvp->drive; 1008 xfer->c_databuf = ata_bio->databuf; 1009 xfer->c_bcount = ata_bio->bcount; 1010 xfer->ops = &mvsata_bio_xfer_ops; 1011 ata_exec_xfer(chp, xfer); 1012 } 1013 1014 static int 1015 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1016 { 1017 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1018 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1019 struct atac_softc *atac = chp->ch_atac; 1020 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1021 struct ata_bio *ata_bio = &xfer->c_bio; 1022 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1023 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1024 u_int16_t cyl; 1025 u_int8_t head, sect, cmd = 0; 1026 int nblks, error, tfd; 1027 1028 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1029 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1030 1031 ata_channel_lock_owned(chp); 1032 1033 if (xfer->c_flags & C_DMA) 1034 if (drvp->n_xfers <= NXFER) 1035 drvp->n_xfers++; 1036 1037 /* 1038 * 1039 * When starting a multi-sector transfer, or doing single-sector 1040 * transfers... 1041 */ 1042 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1043 if (ata_bio->flags & ATA_SINGLE) 1044 nblks = 1; 1045 else 1046 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1047 /* Check for bad sectors and adjust transfer, if necessary. */ 1048 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1049 long blkdiff; 1050 int i; 1051 1052 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1053 i++) { 1054 blkdiff -= ata_bio->blkno; 1055 if (blkdiff < 0) 1056 continue; 1057 if (blkdiff == 0) 1058 /* Replace current block of transfer. */ 1059 ata_bio->blkno = 1060 drvp->lp->d_secperunit - 1061 drvp->lp->d_nsectors - i - 1; 1062 if (blkdiff < nblks) { 1063 /* Bad block inside transfer. */ 1064 ata_bio->flags |= ATA_SINGLE; 1065 nblks = 1; 1066 } 1067 break; 1068 } 1069 /* Transfer is okay now. */ 1070 } 1071 if (xfer->c_flags & C_DMA) { 1072 enum mvsata_edmamode dmamode; 1073 1074 ata_bio->nblks = nblks; 1075 ata_bio->nbytes = xfer->c_bcount; 1076 1077 /* switch to appropriate dma mode if necessary */ 1078 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1079 if (mvport->port_edmamode_curr != dmamode) 1080 mvsata_edma_config(mvport, dmamode); 1081 1082 if (xfer->c_flags & C_POLL) 1083 sc->sc_enable_intr(mvport, 0 /*off*/); 1084 error = mvsata_edma_enqueue(mvport, xfer); 1085 if (error) { 1086 if (error == EINVAL) { 1087 /* 1088 * We can't do DMA on this transfer 1089 * for some reason. Fall back to 1090 * PIO. 1091 */ 1092 xfer->c_flags &= ~C_DMA; 1093 error = 0; 1094 goto do_pio; 1095 } 1096 if (error == EBUSY) { 1097 aprint_error_dev(atac->atac_dev, 1098 "channel %d: EDMA Queue full\n", 1099 chp->ch_channel); 1100 /* 1101 * XXX: Perhaps, after it waits for 1102 * a while, it is necessary to call 1103 * bio_start again. 1104 */ 1105 } 1106 ata_bio->error = ERR_DMA; 1107 ata_bio->r_error = 0; 1108 return ATASTART_ABORT; 1109 } 1110 chp->ch_flags |= ATACH_DMA_WAIT; 1111 /* start timeout machinery */ 1112 if ((xfer->c_flags & C_POLL) == 0) 1113 callout_reset(&chp->c_timo_callout, 1114 mstohz(ATA_DELAY), ata_timeout, chp); 1115 /* wait for irq */ 1116 goto intr; 1117 } /* else not DMA */ 1118 do_pio: 1119 if (ata_bio->flags & ATA_LBA48) { 1120 sect = 0; 1121 cyl = 0; 1122 head = 0; 1123 } else if (ata_bio->flags & ATA_LBA) { 1124 sect = (ata_bio->blkno >> 0) & 0xff; 1125 cyl = (ata_bio->blkno >> 8) & 0xffff; 1126 head = (ata_bio->blkno >> 24) & 0x0f; 1127 head |= WDSD_LBA; 1128 } else { 1129 int blkno = ata_bio->blkno; 1130 sect = blkno % drvp->lp->d_nsectors; 1131 sect++; /* Sectors begin with 1, not 0. */ 1132 blkno /= drvp->lp->d_nsectors; 1133 head = blkno % drvp->lp->d_ntracks; 1134 blkno /= drvp->lp->d_ntracks; 1135 cyl = blkno; 1136 head |= WDSD_CHS; 1137 } 1138 ata_bio->nblks = uimin(nblks, drvp->multi); 1139 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1140 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1141 if (ata_bio->nblks > 1) 1142 cmd = (ata_bio->flags & ATA_READ) ? 1143 WDCC_READMULTI : WDCC_WRITEMULTI; 1144 else 1145 cmd = (ata_bio->flags & ATA_READ) ? 1146 WDCC_READ : WDCC_WRITE; 1147 1148 /* EDMA disable, if enabled this channel. */ 1149 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1150 if (mvport->port_edmamode_curr != nodma) 1151 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1152 1153 mvsata_pmp_select(mvport, xfer->c_drive); 1154 1155 /* Do control operations specially. */ 1156 if (__predict_false(drvp->state < READY)) { 1157 /* 1158 * Actually, we want to be careful not to mess with 1159 * the control state if the device is currently busy, 1160 * but we can assume that we never get to this point 1161 * if that's the case. 1162 */ 1163 /* 1164 * If it's not a polled command, we need the kernel 1165 * thread 1166 */ 1167 if ((xfer->c_flags & C_POLL) == 0 1168 && !ata_is_thread_run(chp)) 1169 return ATASTART_TH; 1170 1171 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1172 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1173 return ATASTART_ABORT; 1174 } 1175 } 1176 1177 /* Initiate command! */ 1178 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1179 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1180 case WDCWAIT_OK: 1181 break; 1182 case WDCWAIT_TOUT: 1183 goto timeout; 1184 case WDCWAIT_THR: 1185 return ATASTART_TH; 1186 } 1187 if (ata_bio->flags & ATA_LBA48) 1188 wdccommandext(chp, 0, atacmd_to48(cmd), 1189 ata_bio->blkno, nblks, 0, WDSD_LBA); 1190 else 1191 wdccommand(chp, 0, cmd, cyl, 1192 head, sect, nblks, 1193 (drvp->lp->d_type == DKTYPE_ST506) ? 1194 drvp->lp->d_precompcyl / 4 : 0); 1195 1196 /* start timeout machinery */ 1197 if ((xfer->c_flags & C_POLL) == 0) 1198 callout_reset(&chp->c_timo_callout, 1199 mstohz(ATA_DELAY), wdctimeout, chp); 1200 } else if (ata_bio->nblks > 1) { 1201 /* The number of blocks in the last stretch may be smaller. */ 1202 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1203 if (ata_bio->nblks > nblks) { 1204 ata_bio->nblks = nblks; 1205 ata_bio->nbytes = xfer->c_bcount; 1206 } 1207 } 1208 /* If this was a write and not using DMA, push the data. */ 1209 if ((ata_bio->flags & ATA_READ) == 0) { 1210 /* 1211 * we have to busy-wait here, we can't rely on running in 1212 * thread context. 1213 */ 1214 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1215 aprint_error_dev(atac->atac_dev, 1216 "channel %d: drive %d timeout waiting for DRQ," 1217 " st=0x%02x, err=0x%02x\n", 1218 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1219 ATACH_ERR(tfd)); 1220 ata_bio->error = TIMEOUT; 1221 return ATASTART_ABORT; 1222 } 1223 if (ATACH_ST(tfd) & WDCS_ERR) { 1224 ata_bio->error = ERROR; 1225 ata_bio->r_error = ATACH_ERR(tfd); 1226 mvsata_bio_done(chp, xfer); 1227 return ATASTART_ABORT; 1228 } 1229 1230 wdc->dataout_pio(chp, drvp->drive_flags, 1231 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1232 } 1233 1234 intr: 1235 KASSERTMSG(((xfer->c_flags & C_DMA) != 0) 1236 == (mvport->port_edmamode_curr != nodma), 1237 "DMA mode mismatch: flags %x vs edmamode %d != %d", 1238 xfer->c_flags, mvport->port_edmamode_curr, nodma); 1239 1240 /* Wait for IRQ (either real or polled) */ 1241 if ((ata_bio->flags & ATA_POLL) != 0) 1242 return ATASTART_POLL; 1243 else 1244 return ATASTART_STARTED; 1245 1246 timeout: 1247 aprint_error_dev(atac->atac_dev, 1248 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1249 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1250 ata_bio->error = TIMEOUT; 1251 return ATASTART_ABORT; 1252 } 1253 1254 static void 1255 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1256 { 1257 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1258 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1259 1260 /* Wait for at last 400ns for status bit to be valid */ 1261 delay(1); 1262 if (chp->ch_flags & ATACH_DMA_WAIT) { 1263 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1264 sc->sc_enable_intr(mvport, 1 /*on*/); 1265 chp->ch_flags &= ~ATACH_DMA_WAIT; 1266 } 1267 1268 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1269 KASSERT(xfer->c_flags & C_TIMEOU); 1270 mvsata_bio_intr(chp, xfer, 0); 1271 } 1272 } 1273 1274 static int 1275 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int intr_arg) 1276 { 1277 struct atac_softc *atac = chp->ch_atac; 1278 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1279 struct ata_bio *ata_bio = &xfer->c_bio; 1280 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1281 int irq = ISSET(xfer->c_flags, (C_POLL|C_TIMEOU)) ? 0 : 1; 1282 int tfd = 0; 1283 1284 if (ISSET(xfer->c_flags, C_DMA|C_RECOVERED) && irq) { 1285 /* Invoked via mvsata_edma_handle() or recovery */ 1286 tfd = intr_arg; 1287 1288 if (tfd > 0 && ata_bio->error == NOERROR) { 1289 if (ATACH_ST(tfd) & WDCS_ERR) 1290 ata_bio->error = ERROR; 1291 if (ATACH_ST(tfd) & WDCS_BSY) 1292 ata_bio->error = TIMEOUT; 1293 ata_bio->r_error = ATACH_ERR(tfd); 1294 } 1295 } 1296 1297 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1298 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1299 xfer->c_drive)); 1300 1301 /* Cleanup EDMA if invoked from wdctimeout()/ata_timeout() */ 1302 if (ISSET(xfer->c_flags, C_TIMEOU) && ISSET(xfer->c_flags, C_DMA) 1303 && !ISSET(xfer->c_flags, C_POLL)) { 1304 mvsata_edma_rqq_remove((struct mvsata_port *)chp, xfer); 1305 } 1306 1307 ata_channel_lock(chp); 1308 1309 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1310 1311 /* 1312 * If we missed an interrupt transfer, reset and restart. 1313 * Don't try to continue transfer, we may have missed cycles. 1314 */ 1315 if (xfer->c_flags & C_TIMEOU) { 1316 ata_bio->error = TIMEOUT; 1317 ata_channel_unlock(chp); 1318 mvsata_bio_done(chp, xfer); 1319 return 1; 1320 } 1321 1322 /* Is it not a transfer, but a control operation? */ 1323 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1324 aprint_error_dev(atac->atac_dev, 1325 "channel %d: drive %d bad state %d in %s\n", 1326 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1327 panic("%s: bad state", __func__); 1328 } 1329 1330 /* Ack interrupt done by wdc_wait_for_unbusy */ 1331 if (!(xfer->c_flags & C_DMA) && 1332 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1333 == WDCWAIT_TOUT)) { 1334 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1335 ata_channel_unlock(chp); 1336 return 0; /* IRQ was not for us */ 1337 } 1338 aprint_error_dev(atac->atac_dev, 1339 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1340 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1341 xfer->c_skip); 1342 ata_bio->error = TIMEOUT; 1343 ata_channel_unlock(chp); 1344 mvsata_bio_done(chp, xfer); 1345 return 1; 1346 } 1347 1348 if (xfer->c_flags & C_DMA) { 1349 if (ata_bio->error == NOERROR) 1350 goto end; 1351 if (ata_bio->error == ERR_DMA) { 1352 ata_dmaerr(drvp, 1353 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1354 ata_channel_unlock(chp); 1355 goto err; 1356 } 1357 } 1358 1359 /* if we had an error, end */ 1360 if (ata_bio->error != NOERROR) { 1361 ata_channel_unlock(chp); 1362 err: 1363 mvsata_bio_done(chp, xfer); 1364 return 1; 1365 } 1366 1367 /* If this was a read and not using DMA, fetch the data. */ 1368 if ((ata_bio->flags & ATA_READ) != 0) { 1369 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1370 aprint_error_dev(atac->atac_dev, 1371 "channel %d: drive %d read intr before drq\n", 1372 chp->ch_channel, xfer->c_drive); 1373 ata_bio->error = TIMEOUT; 1374 ata_channel_unlock(chp); 1375 mvsata_bio_done(chp, xfer); 1376 return 1; 1377 } 1378 wdc->datain_pio(chp, drvp->drive_flags, 1379 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1380 } 1381 1382 end: 1383 ata_bio->blkno += ata_bio->nblks; 1384 ata_bio->blkdone += ata_bio->nblks; 1385 xfer->c_skip += ata_bio->nbytes; 1386 xfer->c_bcount -= ata_bio->nbytes; 1387 1388 /* See if this transfer is complete. */ 1389 if (xfer->c_bcount > 0) { 1390 if ((ata_bio->flags & ATA_POLL) == 0) { 1391 /* Start the next operation */ 1392 ata_xfer_start(xfer); 1393 } else { 1394 /* Let mvsata_bio_start do the loop */ 1395 } 1396 ata_channel_unlock(chp); 1397 } else { /* Done with this transfer */ 1398 ata_bio->error = NOERROR; 1399 ata_channel_unlock(chp); 1400 mvsata_bio_done(chp, xfer); 1401 } 1402 return 1; 1403 } 1404 1405 static void 1406 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1407 { 1408 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1409 struct atac_softc *atac = chp->ch_atac; 1410 struct ata_bio *ata_bio = &xfer->c_bio; 1411 int drive = xfer->c_drive; 1412 bool deactivate = true; 1413 1414 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1415 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1416 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1417 1418 /* EDMA restart, if enabled */ 1419 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1420 mvsata_edma_reset_qptr(mvport); 1421 mvsata_edma_enable(mvport); 1422 } 1423 1424 ata_bio->flags |= ATA_ITSDONE; 1425 switch (reason) { 1426 case KILL_GONE_INACTIVE: 1427 deactivate = false; 1428 /* FALLTHROUGH */ 1429 case KILL_GONE: 1430 ata_bio->error = ERR_NODEV; 1431 break; 1432 case KILL_RESET: 1433 ata_bio->error = ERR_RESET; 1434 break; 1435 case KILL_REQUEUE: 1436 ata_bio->error = REQUEUE; 1437 break; 1438 default: 1439 aprint_error_dev(atac->atac_dev, 1440 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1441 panic("mvsata_bio_kill_xfer"); 1442 } 1443 ata_bio->r_error = WDCE_ABRT; 1444 1445 if (deactivate) 1446 ata_deactivate_xfer(chp, xfer); 1447 1448 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1449 } 1450 1451 static void 1452 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1453 { 1454 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1455 struct ata_bio *ata_bio = &xfer->c_bio; 1456 int drive = xfer->c_drive; 1457 bool iserror = (ata_bio->error != NOERROR); 1458 1459 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1460 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1461 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1462 (u_int)xfer->c_flags)); 1463 1464 /* EDMA restart, if enabled */ 1465 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1466 mvsata_edma_reset_qptr(mvport); 1467 mvsata_edma_enable(mvport); 1468 } 1469 1470 if (ata_waitdrain_xfer_check(chp, xfer)) 1471 return; 1472 1473 /* feed back residual bcount to our caller */ 1474 ata_bio->bcount = xfer->c_bcount; 1475 1476 /* mark controller inactive and free xfer */ 1477 ata_deactivate_xfer(chp, xfer); 1478 1479 ata_bio->flags |= ATA_ITSDONE; 1480 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1481 if (!iserror) 1482 atastart(chp); 1483 } 1484 1485 static int 1486 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1487 int flags) 1488 { 1489 struct ata_channel *chp = &mvport->port_ata_channel; 1490 struct atac_softc *atac = chp->ch_atac; 1491 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1492 const char *errstring; 1493 int tfd; 1494 1495 flags |= AT_POLL; /* XXX */ 1496 1497 ata_channel_lock_owned(chp); 1498 1499 /* 1500 * disable interrupts, all commands here should be quick 1501 * enough to be able to poll, and we don't go here that often 1502 */ 1503 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1504 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1505 DELAY(10); 1506 errstring = "wait"; 1507 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1508 goto ctrltimeout; 1509 wdccommandshort(chp, 0, WDCC_RECAL); 1510 /* Wait for at least 400ns for status bit to be valid */ 1511 DELAY(1); 1512 errstring = "recal"; 1513 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1514 goto ctrltimeout; 1515 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1516 goto ctrlerror; 1517 /* Don't try to set modes if controller can't be adjusted */ 1518 if (atac->atac_set_modes == NULL) 1519 goto geometry; 1520 /* Also don't try if the drive didn't report its mode */ 1521 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1522 goto geometry; 1523 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1524 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1525 errstring = "piomode-bio"; 1526 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1527 goto ctrltimeout; 1528 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1529 goto ctrlerror; 1530 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1531 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1532 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1533 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1534 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1535 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1536 else 1537 goto geometry; 1538 errstring = "dmamode-bio"; 1539 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1540 goto ctrltimeout; 1541 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1542 goto ctrlerror; 1543 geometry: 1544 if (ata_bio->flags & ATA_LBA) 1545 goto multimode; 1546 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1547 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1548 (drvp->lp->d_type == DKTYPE_ST506) ? 1549 drvp->lp->d_precompcyl / 4 : 0); 1550 errstring = "geometry"; 1551 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1552 goto ctrltimeout; 1553 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1554 goto ctrlerror; 1555 multimode: 1556 if (drvp->multi == 1) 1557 goto ready; 1558 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1559 errstring = "setmulti"; 1560 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1561 goto ctrltimeout; 1562 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1563 goto ctrlerror; 1564 ready: 1565 drvp->state = READY; 1566 /* 1567 * The drive is usable now 1568 */ 1569 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1570 delay(10); /* some drives need a little delay here */ 1571 return 0; 1572 1573 ctrltimeout: 1574 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1575 chp->ch_channel, drive, errstring); 1576 ata_bio->error = TIMEOUT; 1577 goto ctrldone; 1578 ctrlerror: 1579 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1580 chp->ch_channel, drive, errstring); 1581 if (ATACH_ST(tfd) & WDCS_DWF) { 1582 aprint_error("drive fault\n"); 1583 ata_bio->error = ERR_DF; 1584 } else { 1585 ata_bio->r_error = ATACH_ERR(tfd); 1586 ata_bio->error = ERROR; 1587 aprint_error("error (%x)\n", ata_bio->r_error); 1588 } 1589 ctrldone: 1590 drvp->state = 0; 1591 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1592 return -1; 1593 } 1594 1595 static const struct ata_xfer_ops mvsata_wdc_cmd_xfer_ops = { 1596 .c_start = mvsata_wdc_cmd_start, 1597 .c_intr = mvsata_wdc_cmd_intr, 1598 .c_poll = mvsata_wdc_cmd_poll, 1599 .c_abort = mvsata_wdc_cmd_done, 1600 .c_kill_xfer = mvsata_wdc_cmd_kill_xfer, 1601 }; 1602 1603 static void 1604 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1605 { 1606 struct ata_channel *chp = drvp->chnl_softc; 1607 struct ata_command *ata_c = &xfer->c_ata_c; 1608 1609 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1610 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1611 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1612 " r_device=0x%02x, r_command=0x%02x\n", 1613 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1614 chp->ch_channel, 1615 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1616 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1617 1618 if (ata_c->flags & AT_POLL) 1619 xfer->c_flags |= C_POLL; 1620 if (ata_c->flags & AT_WAIT) 1621 xfer->c_flags |= C_WAIT; 1622 xfer->c_drive = drvp->drive; 1623 xfer->c_databuf = ata_c->data; 1624 xfer->c_bcount = ata_c->bcount; 1625 xfer->ops = &mvsata_wdc_cmd_xfer_ops; 1626 1627 ata_exec_xfer(chp, xfer); 1628 } 1629 1630 static int 1631 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1632 { 1633 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1634 int drive = xfer->c_drive; 1635 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1636 struct ata_command *ata_c = &xfer->c_ata_c; 1637 int tfd; 1638 1639 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1640 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1641 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1642 1643 ata_channel_lock_owned(chp); 1644 1645 /* First, EDMA disable, if enabled this channel. */ 1646 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1647 if (mvport->port_edmamode_curr != nodma) 1648 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1649 1650 mvsata_pmp_select(mvport, drive); 1651 1652 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1653 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1654 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1655 case WDCWAIT_OK: 1656 break; 1657 case WDCWAIT_TOUT: 1658 ata_c->flags |= AT_TIMEOU; 1659 return ATASTART_ABORT; 1660 case WDCWAIT_THR: 1661 return ATASTART_TH; 1662 } 1663 if (ata_c->flags & AT_POLL) 1664 /* polled command, disable interrupts */ 1665 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1666 if ((ata_c->flags & AT_LBA48) != 0) { 1667 wdccommandext(chp, 0, ata_c->r_command, 1668 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1669 ata_c->r_device & ~0x10); 1670 } else { 1671 wdccommand(chp, 0, ata_c->r_command, 1672 (ata_c->r_lba >> 8) & 0xffff, 1673 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1674 ((ata_c->r_lba >> 24) & 0x0f), 1675 ata_c->r_lba & 0xff, 1676 ata_c->r_count & 0xff, 1677 ata_c->r_features & 0xff); 1678 } 1679 1680 if ((ata_c->flags & AT_POLL) == 0) { 1681 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1682 wdctimeout, chp); 1683 return ATASTART_STARTED; 1684 } 1685 1686 return ATASTART_POLL; 1687 } 1688 1689 static void 1690 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1691 { 1692 /* 1693 * Polled command. Wait for drive ready or drq. Done in intr(). 1694 * Wait for at last 400ns for status bit to be valid. 1695 */ 1696 delay(10); /* 400ns delay */ 1697 mvsata_wdc_cmd_intr(chp, xfer, 0); 1698 } 1699 1700 static int 1701 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1702 { 1703 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1704 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1705 struct ata_command *ata_c = &xfer->c_ata_c; 1706 int bcount = ata_c->bcount; 1707 char *data = ata_c->data; 1708 int wflags; 1709 int drive_flags; 1710 int tfd; 1711 1712 ata_channel_lock(chp); 1713 1714 if (ata_c->r_command == WDCC_IDENTIFY || 1715 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1716 /* 1717 * The IDENTIFY data has been designed as an array of 1718 * u_int16_t, so we can byteswap it on the fly. 1719 * Historically it's what we have always done so keeping it 1720 * here ensure binary backward compatibility. 1721 */ 1722 drive_flags = ATA_DRIVE_NOSTREAM | 1723 chp->ch_drive[xfer->c_drive].drive_flags; 1724 else 1725 /* 1726 * Other data structure are opaque and should be transferred 1727 * as is. 1728 */ 1729 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1730 1731 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1732 /* both wait and poll, we can kpause here */ 1733 wflags = AT_WAIT | AT_POLL; 1734 else 1735 wflags = AT_POLL; 1736 1737 again: 1738 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1739 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1740 __func__, xfer->c_drive)); 1741 1742 /* 1743 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1744 * Reselect again, it doesn't hurt for others commands, and the time 1745 * penalty for the extra register write is acceptable, 1746 * wdc_exec_command() isn't called often (mostly for autoconfig) 1747 */ 1748 if ((xfer->c_flags & C_ATAPI) != 0) { 1749 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1750 } 1751 if ((ata_c->flags & AT_XFDONE) != 0) { 1752 /* 1753 * We have completed a data xfer. The drive should now be 1754 * in its initial state 1755 */ 1756 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1757 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1758 wflags, &tfd) == WDCWAIT_TOUT) { 1759 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1760 ata_channel_unlock(chp); 1761 return 0; /* IRQ was not for us */ 1762 } 1763 ata_c->flags |= AT_TIMEOU; 1764 } 1765 goto out; 1766 } 1767 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1768 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1769 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1770 ata_channel_unlock(chp); 1771 return 0; /* IRQ was not for us */ 1772 } 1773 ata_c->flags |= AT_TIMEOU; 1774 goto out; 1775 } 1776 delay(20); /* XXXXX: Delay more times. */ 1777 if (ata_c->flags & AT_READ) { 1778 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1779 ata_c->flags |= AT_TIMEOU; 1780 goto out; 1781 } 1782 wdc->datain_pio(chp, drive_flags, data, bcount); 1783 /* at this point the drive should be in its initial state */ 1784 ata_c->flags |= AT_XFDONE; 1785 /* 1786 * XXX checking the status register again here cause some 1787 * hardware to timeout. 1788 */ 1789 } else if (ata_c->flags & AT_WRITE) { 1790 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1791 ata_c->flags |= AT_TIMEOU; 1792 goto out; 1793 } 1794 wdc->dataout_pio(chp, drive_flags, data, bcount); 1795 ata_c->flags |= AT_XFDONE; 1796 if ((ata_c->flags & AT_POLL) == 0) { 1797 callout_reset(&chp->c_timo_callout, 1798 mstohz(ata_c->timeout), wdctimeout, chp); 1799 ata_channel_unlock(chp); 1800 return 1; 1801 } else 1802 goto again; 1803 } 1804 out: 1805 if (ATACH_ST(tfd) & WDCS_DWF) 1806 ata_c->flags |= AT_DF; 1807 if (ATACH_ST(tfd) & WDCS_ERR) { 1808 ata_c->flags |= AT_ERROR; 1809 ata_c->r_error = ATACH_ERR(tfd); 1810 } 1811 ata_channel_unlock(chp); 1812 mvsata_wdc_cmd_done(chp, xfer); 1813 1814 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1815 atastart(chp); 1816 1817 return 1; 1818 } 1819 1820 static void 1821 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1822 int reason) 1823 { 1824 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1825 struct ata_command *ata_c = &xfer->c_ata_c; 1826 bool deactivate = true; 1827 1828 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1829 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1830 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1831 1832 switch (reason) { 1833 case KILL_GONE_INACTIVE: 1834 deactivate = false; 1835 /* FALLTHROUGH */ 1836 case KILL_GONE: 1837 ata_c->flags |= AT_GONE; 1838 break; 1839 case KILL_RESET: 1840 ata_c->flags |= AT_RESET; 1841 break; 1842 case KILL_REQUEUE: 1843 panic("%s: not supposed to be requeued\n", __func__); 1844 break; 1845 default: 1846 aprint_error_dev(MVSATA_DEV2(mvport), 1847 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1848 panic("mvsata_cmd_kill_xfer"); 1849 } 1850 1851 mvsata_wdc_cmd_done_end(chp, xfer); 1852 1853 if (deactivate) 1854 ata_deactivate_xfer(chp, xfer); 1855 } 1856 1857 static void 1858 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1859 { 1860 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1861 struct atac_softc *atac = chp->ch_atac; 1862 struct ata_command *ata_c = &xfer->c_ata_c; 1863 1864 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1865 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1866 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1867 ata_c->flags)); 1868 1869 if (ata_waitdrain_xfer_check(chp, xfer)) 1870 return; 1871 1872 if ((ata_c->flags & AT_READREG) != 0 && 1873 device_is_active(atac->atac_dev) && 1874 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1875 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1876 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1877 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1878 ata_c->r_lba = 1879 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1880 ata_c->r_lba |= 1881 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1882 ata_c->r_lba |= 1883 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1884 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1885 if ((ata_c->flags & AT_LBA48) != 0) { 1886 if ((ata_c->flags & AT_POLL) != 0) { 1887 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1888 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1889 } else { 1890 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1891 WDCTL_HOB|WDCTL_4BIT); 1892 } 1893 ata_c->r_count |= 1894 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1895 ata_c->r_lba |= 1896 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1897 ata_c->r_lba |= 1898 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1899 ata_c->r_lba |= 1900 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1901 if ((ata_c->flags & AT_POLL) != 0) { 1902 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1903 WDCTL_4BIT|WDCTL_IDS); 1904 } else { 1905 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1906 WDCTL_4BIT); 1907 } 1908 } else { 1909 ata_c->r_lba |= 1910 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1911 } 1912 } 1913 1914 if (ata_c->flags & AT_POLL) { 1915 /* enable interrupts */ 1916 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1917 delay(10); /* some drives need a little delay here */ 1918 } 1919 1920 mvsata_wdc_cmd_done_end(chp, xfer); 1921 1922 ata_deactivate_xfer(chp, xfer); 1923 } 1924 1925 static void 1926 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1927 { 1928 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1929 struct ata_command *ata_c = &xfer->c_ata_c; 1930 1931 /* EDMA restart, if enabled */ 1932 if (mvport->port_edmamode_curr != nodma) { 1933 mvsata_edma_reset_qptr(mvport); 1934 mvsata_edma_enable(mvport); 1935 } 1936 1937 ata_c->flags |= AT_DONE; 1938 } 1939 1940 #if NATAPIBUS > 0 1941 static const struct ata_xfer_ops mvsata_atapi_xfer_ops = { 1942 .c_start = mvsata_atapi_start, 1943 .c_intr = mvsata_atapi_intr, 1944 .c_poll = mvsata_atapi_poll, 1945 .c_abort = mvsata_atapi_reset, 1946 .c_kill_xfer = mvsata_atapi_kill_xfer, 1947 }; 1948 1949 static void 1950 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 1951 scsipi_adapter_req_t req, void *arg) 1952 { 1953 struct scsipi_adapter *adapt = chan->chan_adapter; 1954 struct scsipi_periph *periph; 1955 struct scsipi_xfer *sc_xfer; 1956 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 1957 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1958 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1959 struct ata_xfer *xfer; 1960 int drive, s; 1961 1962 switch (req) { 1963 case ADAPTER_REQ_RUN_XFER: 1964 sc_xfer = arg; 1965 periph = sc_xfer->xs_periph; 1966 drive = periph->periph_target; 1967 1968 if (!device_is_active(atac->atac_dev)) { 1969 sc_xfer->error = XS_DRIVER_STUFFUP; 1970 scsipi_done(sc_xfer); 1971 return; 1972 } 1973 xfer = ata_get_xfer(chp, false); 1974 if (xfer == NULL) { 1975 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1976 scsipi_done(sc_xfer); 1977 return; 1978 } 1979 1980 if (sc_xfer->xs_control & XS_CTL_POLL) 1981 xfer->c_flags |= C_POLL; 1982 xfer->c_drive = drive; 1983 xfer->c_flags |= C_ATAPI; 1984 xfer->c_databuf = sc_xfer->data; 1985 xfer->c_bcount = sc_xfer->datalen; 1986 xfer->ops = &mvsata_atapi_xfer_ops; 1987 xfer->c_scsipi = sc_xfer; 1988 xfer->c_atapi.c_dscpoll = 0; 1989 s = splbio(); 1990 ata_exec_xfer(chp, xfer); 1991 #ifdef DIAGNOSTIC 1992 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1993 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1994 panic("mvsata_atapi_scsipi_request:" 1995 " polled command not done"); 1996 #endif 1997 splx(s); 1998 return; 1999 2000 default: 2001 /* Not supported, nothing to do. */ 2002 ; 2003 } 2004 } 2005 2006 static int 2007 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2008 { 2009 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2010 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2011 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2012 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2013 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2014 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2015 const char *errstring; 2016 int tfd; 2017 2018 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2019 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2020 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2021 xfer->c_drive, sc_xfer->xs_control)); 2022 2023 ata_channel_lock_owned(chp); 2024 2025 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2026 if (mvport->port_edmamode_curr != nodma) 2027 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2028 2029 mvsata_pmp_select(mvport, xfer->c_drive); 2030 2031 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2032 drvp->n_xfers++; 2033 2034 /* Do control operations specially. */ 2035 if (__predict_false(drvp->state < READY)) { 2036 /* If it's not a polled command, we need the kernel thread */ 2037 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 2038 && !ata_is_thread_run(chp)) 2039 return ATASTART_TH; 2040 2041 /* 2042 * disable interrupts, all commands here should be quick 2043 * enough to be able to poll, and we don't go here that often 2044 */ 2045 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2046 2047 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2048 /* Don't try to set mode if controller can't be adjusted */ 2049 if (atac->atac_set_modes == NULL) 2050 goto ready; 2051 /* Also don't try if the drive didn't report its mode */ 2052 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2053 goto ready; 2054 errstring = "unbusy"; 2055 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2056 goto timeout; 2057 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2058 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2059 errstring = "piomode-atapi"; 2060 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2061 &tfd)) 2062 goto timeout; 2063 if (ATACH_ST(tfd) & WDCS_ERR) { 2064 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2065 /* 2066 * Some ATAPI drives reject PIO settings. 2067 * Fall back to PIO mode 3 since that's the 2068 * minimum for ATAPI. 2069 */ 2070 aprint_error_dev(atac->atac_dev, 2071 "channel %d drive %d: PIO mode %d rejected," 2072 " falling back to PIO mode 3\n", 2073 chp->ch_channel, xfer->c_drive, 2074 drvp->PIO_mode); 2075 if (drvp->PIO_mode > 3) 2076 drvp->PIO_mode = 3; 2077 } else 2078 goto error; 2079 } 2080 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2081 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2082 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2083 else 2084 if (drvp->drive_flags & ATA_DRIVE_DMA) 2085 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2086 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2087 else 2088 goto ready; 2089 errstring = "dmamode-atapi"; 2090 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2091 &tfd)) 2092 goto timeout; 2093 if (ATACH_ST(tfd) & WDCS_ERR) { 2094 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2095 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2096 goto error; 2097 else { 2098 /* 2099 * The drive rejected our DMA setting. 2100 * Fall back to mode 1. 2101 */ 2102 aprint_error_dev(atac->atac_dev, 2103 "channel %d drive %d:" 2104 " DMA mode %d rejected," 2105 " falling back to DMA mode 0\n", 2106 chp->ch_channel, xfer->c_drive, 2107 drvp->DMA_mode); 2108 if (drvp->DMA_mode > 0) 2109 drvp->DMA_mode = 0; 2110 } 2111 } else 2112 goto error; 2113 } 2114 ready: 2115 drvp->state = READY; 2116 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2117 delay(10); /* some drives need a little delay here */ 2118 } 2119 /* start timeout machinery */ 2120 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2121 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 2122 wdctimeout, chp); 2123 2124 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2125 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2126 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2127 ATACH_ST(tfd)); 2128 sc_xfer->error = XS_TIMEOUT; 2129 return ATASTART_ABORT; 2130 } 2131 2132 /* 2133 * Even with WDCS_ERR, the device should accept a command packet 2134 * Limit length to what can be stuffed into the cylinder register 2135 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2136 * but not all devices do that and it's not obvious from the 2137 * ATAPI spec that that behaviour should be expected. If more 2138 * data is necessary, multiple data transfer phases will be done. 2139 */ 2140 2141 wdccommand(chp, 0, ATAPI_PKT_CMD, 2142 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2143 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2144 2145 /* 2146 * If there is no interrupt for CMD input, busy-wait for it (done in 2147 * the interrupt routine. Poll routine will exit early in this case. 2148 */ 2149 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2150 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2151 return ATASTART_POLL; 2152 else 2153 return ATASTART_STARTED; 2154 2155 timeout: 2156 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2157 chp->ch_channel, xfer->c_drive, errstring); 2158 sc_xfer->error = XS_TIMEOUT; 2159 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2160 delay(10); /* some drives need a little delay here */ 2161 return ATASTART_ABORT; 2162 2163 error: 2164 aprint_error_dev(atac->atac_dev, 2165 "channel %d drive %d: %s error (0x%x)\n", 2166 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2167 sc_xfer->error = XS_SHORTSENSE; 2168 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2169 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2170 delay(10); /* some drives need a little delay here */ 2171 return ATASTART_ABORT; 2172 } 2173 2174 static void 2175 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2176 { 2177 /* 2178 * If there is no interrupt for CMD input, busy-wait for it (done in 2179 * the interrupt routine. If it is a polled command, call the interrupt 2180 * routine until command is done. 2181 */ 2182 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2183 2184 /* Wait for at last 400ns for status bit to be valid */ 2185 DELAY(1); 2186 mvsata_atapi_intr(chp, xfer, 0); 2187 2188 if (!poll) 2189 return; 2190 2191 if (chp->ch_flags & ATACH_DMA_WAIT) { 2192 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2193 chp->ch_flags &= ~ATACH_DMA_WAIT; 2194 } 2195 2196 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2197 /* Wait for at last 400ns for status bit to be valid */ 2198 DELAY(1); 2199 mvsata_atapi_intr(chp, xfer, 0); 2200 } 2201 } 2202 2203 static int 2204 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2205 { 2206 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2207 struct atac_softc *atac = chp->ch_atac; 2208 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2209 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2210 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2211 int len, phase, ire, error, retries=0, i; 2212 int tfd; 2213 void *cmd; 2214 2215 ata_channel_lock(chp); 2216 2217 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2218 ("%s:%d:%d: mvsata_atapi_intr\n", 2219 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2220 2221 /* Is it not a transfer, but a control operation? */ 2222 if (drvp->state < READY) { 2223 aprint_error_dev(atac->atac_dev, 2224 "channel %d drive %d: bad state %d\n", 2225 chp->ch_channel, xfer->c_drive, drvp->state); 2226 panic("mvsata_atapi_intr: bad state"); 2227 } 2228 /* 2229 * If we missed an interrupt in a PIO transfer, reset and restart. 2230 * Don't try to continue transfer, we may have missed cycles. 2231 */ 2232 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2233 ata_channel_unlock(chp); 2234 sc_xfer->error = XS_TIMEOUT; 2235 mvsata_atapi_reset(chp, xfer); 2236 return 1; 2237 } 2238 2239 /* Ack interrupt done in wdc_wait_for_unbusy */ 2240 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2241 if (wdc_wait_for_unbusy(chp, 2242 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2243 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2244 ata_channel_unlock(chp); 2245 return 0; /* IRQ was not for us */ 2246 } 2247 aprint_error_dev(atac->atac_dev, 2248 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2249 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2250 if (xfer->c_flags & C_DMA) 2251 ata_dmaerr(drvp, 2252 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2253 sc_xfer->error = XS_TIMEOUT; 2254 ata_channel_unlock(chp); 2255 mvsata_atapi_reset(chp, xfer); 2256 return 1; 2257 } 2258 2259 /* 2260 * If we missed an IRQ and were using DMA, flag it as a DMA error 2261 * and reset device. 2262 */ 2263 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2264 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2265 sc_xfer->error = XS_RESET; 2266 ata_channel_unlock(chp); 2267 mvsata_atapi_reset(chp, xfer); 2268 return (1); 2269 } 2270 /* 2271 * if the request sense command was aborted, report the short sense 2272 * previously recorded, else continue normal processing 2273 */ 2274 2275 again: 2276 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2277 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2278 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2279 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2280 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2281 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2282 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2283 2284 switch (phase) { 2285 case PHASE_CMDOUT: 2286 cmd = sc_xfer->cmd; 2287 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2288 /* Init the DMA channel if necessary */ 2289 if (xfer->c_flags & C_DMA) { 2290 error = mvsata_bdma_init(mvport, xfer); 2291 if (error) { 2292 if (error == EINVAL) { 2293 /* 2294 * We can't do DMA on this transfer 2295 * for some reason. Fall back to PIO. 2296 */ 2297 xfer->c_flags &= ~C_DMA; 2298 error = 0; 2299 } else { 2300 sc_xfer->error = XS_DRIVER_STUFFUP; 2301 break; 2302 } 2303 } 2304 } 2305 2306 /* send packet command */ 2307 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2308 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2309 2310 /* Start the DMA channel if necessary */ 2311 if (xfer->c_flags & C_DMA) { 2312 mvsata_bdma_start(mvport); 2313 chp->ch_flags |= ATACH_DMA_WAIT; 2314 } 2315 ata_channel_unlock(chp); 2316 return 1; 2317 2318 case PHASE_DATAOUT: 2319 /* write data */ 2320 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2321 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2322 (xfer->c_flags & C_DMA) != 0) { 2323 aprint_error_dev(atac->atac_dev, 2324 "channel %d drive %d: bad data phase DATAOUT\n", 2325 chp->ch_channel, xfer->c_drive); 2326 if (xfer->c_flags & C_DMA) 2327 ata_dmaerr(drvp, 2328 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2329 sc_xfer->error = XS_TIMEOUT; 2330 ata_channel_unlock(chp); 2331 mvsata_atapi_reset(chp, xfer); 2332 return 1; 2333 } 2334 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2335 if (xfer->c_bcount < len) { 2336 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2337 " warning: write only %d of %d requested bytes\n", 2338 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2339 len); 2340 len = xfer->c_bcount; 2341 } 2342 2343 wdc->dataout_pio(chp, drvp->drive_flags, 2344 (char *)xfer->c_databuf + xfer->c_skip, len); 2345 2346 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 2347 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2348 2349 xfer->c_skip += len; 2350 xfer->c_bcount -= len; 2351 ata_channel_unlock(chp); 2352 return 1; 2353 2354 case PHASE_DATAIN: 2355 /* Read data */ 2356 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2357 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2358 (xfer->c_flags & C_DMA) != 0) { 2359 aprint_error_dev(atac->atac_dev, 2360 "channel %d drive %d: bad data phase DATAIN\n", 2361 chp->ch_channel, xfer->c_drive); 2362 if (xfer->c_flags & C_DMA) 2363 ata_dmaerr(drvp, 2364 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2365 ata_channel_unlock(chp); 2366 sc_xfer->error = XS_TIMEOUT; 2367 mvsata_atapi_reset(chp, xfer); 2368 return 1; 2369 } 2370 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2371 if (xfer->c_bcount < len) { 2372 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2373 " warning: reading only %d of %d bytes\n", 2374 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2375 len); 2376 len = xfer->c_bcount; 2377 } 2378 2379 wdc->datain_pio(chp, drvp->drive_flags, 2380 (char *)xfer->c_databuf + xfer->c_skip, len); 2381 2382 if (xfer->c_atapi.c_lenoff > 0) 2383 wdcbit_bucket(chp, len - xfer->c_bcount); 2384 2385 xfer->c_skip += len; 2386 xfer->c_bcount -= len; 2387 ata_channel_unlock(chp); 2388 return 1; 2389 2390 case PHASE_ABORTED: 2391 case PHASE_COMPLETED: 2392 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2393 if (xfer->c_flags & C_DMA) 2394 xfer->c_bcount -= sc_xfer->datalen; 2395 sc_xfer->resid = xfer->c_bcount; 2396 /* this will unlock channel lock too */ 2397 mvsata_atapi_phase_complete(xfer, tfd); 2398 return 1; 2399 2400 default: 2401 if (++retries<500) { 2402 DELAY(100); 2403 tfd = ATACH_ERR_ST( 2404 MVSATA_WDC_READ_1(mvport, SRB_FE), 2405 MVSATA_WDC_READ_1(mvport, SRB_CS) 2406 ); 2407 goto again; 2408 } 2409 aprint_error_dev(atac->atac_dev, 2410 "channel %d drive %d: unknown phase 0x%x\n", 2411 chp->ch_channel, xfer->c_drive, phase); 2412 if (ATACH_ST(tfd) & WDCS_ERR) { 2413 sc_xfer->error = XS_SHORTSENSE; 2414 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2415 } else { 2416 if (xfer->c_flags & C_DMA) 2417 ata_dmaerr(drvp, 2418 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2419 sc_xfer->error = XS_RESET; 2420 ata_channel_unlock(chp); 2421 mvsata_atapi_reset(chp, xfer); 2422 return (1); 2423 } 2424 } 2425 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2426 ("mvsata_atapi_intr: %s (end), error 0x%x " 2427 "sense 0x%x\n", __func__, 2428 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2429 ata_channel_unlock(chp); 2430 mvsata_atapi_done(chp, xfer); 2431 return 1; 2432 } 2433 2434 static void 2435 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2436 int reason) 2437 { 2438 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2439 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2440 bool deactivate = true; 2441 2442 /* remove this command from xfer queue */ 2443 switch (reason) { 2444 case KILL_GONE_INACTIVE: 2445 deactivate = false; 2446 /* FALLTHROUGH */ 2447 case KILL_GONE: 2448 sc_xfer->error = XS_DRIVER_STUFFUP; 2449 break; 2450 case KILL_RESET: 2451 sc_xfer->error = XS_RESET; 2452 break; 2453 case KILL_REQUEUE: 2454 sc_xfer->error = XS_REQUEUE; 2455 break; 2456 default: 2457 aprint_error_dev(MVSATA_DEV2(mvport), 2458 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2459 panic("mvsata_atapi_kill_xfer"); 2460 } 2461 2462 if (deactivate) 2463 ata_deactivate_xfer(chp, xfer); 2464 2465 ata_free_xfer(chp, xfer); 2466 scsipi_done(sc_xfer); 2467 } 2468 2469 static void 2470 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2471 { 2472 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2473 struct atac_softc *atac = chp->ch_atac; 2474 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2475 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2476 int tfd; 2477 2478 ata_channel_lock(chp); 2479 2480 mvsata_pmp_select(mvport, xfer->c_drive); 2481 2482 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2483 drvp->state = 0; 2484 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2485 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2486 chp->ch_channel, xfer->c_drive); 2487 sc_xfer->error = XS_SELTIMEOUT; 2488 } 2489 2490 ata_channel_unlock(chp); 2491 2492 mvsata_atapi_done(chp, xfer); 2493 return; 2494 } 2495 2496 static void 2497 mvsata_atapi_phase_complete(struct ata_xfer *xfer, int tfd) 2498 { 2499 struct ata_channel *chp = xfer->c_chp; 2500 struct atac_softc *atac = chp->ch_atac; 2501 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2502 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2503 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2504 2505 ata_channel_lock_owned(chp); 2506 2507 /* wait for DSC if needed */ 2508 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2509 DPRINTF(DEBUG_XFERS, 2510 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2511 device_xname(atac->atac_dev), chp->ch_channel, 2512 xfer->c_drive, xfer->c_atapi.c_dscpoll)); 2513 if (cold) 2514 panic("mvsata_atapi_phase_complete: cold"); 2515 2516 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2517 WDCWAIT_TOUT) { 2518 /* 10ms not enough, try again in 1 tick */ 2519 if (xfer->c_atapi.c_dscpoll++ > 2520 mstohz(sc_xfer->timeout)) { 2521 aprint_error_dev(atac->atac_dev, 2522 "channel %d: wait_for_dsc failed\n", 2523 chp->ch_channel); 2524 ata_channel_unlock(chp); 2525 sc_xfer->error = XS_TIMEOUT; 2526 mvsata_atapi_reset(chp, xfer); 2527 } else { 2528 callout_reset(&chp->c_timo_callout, 1, 2529 mvsata_atapi_polldsc, chp); 2530 ata_channel_unlock(chp); 2531 } 2532 return; 2533 } 2534 } 2535 2536 /* 2537 * Some drive occasionally set WDCS_ERR with 2538 * "ATA illegal length indication" in the error 2539 * register. If we read some data the sense is valid 2540 * anyway, so don't report the error. 2541 */ 2542 if (ATACH_ST(tfd) & WDCS_ERR && 2543 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2544 sc_xfer->resid == sc_xfer->datalen)) { 2545 /* save the short sense */ 2546 sc_xfer->error = XS_SHORTSENSE; 2547 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2548 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2549 /* ask scsipi to send a REQUEST_SENSE */ 2550 sc_xfer->error = XS_BUSY; 2551 sc_xfer->status = SCSI_CHECK; 2552 } else 2553 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2554 ata_dmaerr(drvp, 2555 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2556 sc_xfer->error = XS_RESET; 2557 ata_channel_unlock(chp); 2558 mvsata_atapi_reset(chp, xfer); 2559 return; 2560 } 2561 } 2562 if (xfer->c_bcount != 0) { 2563 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2564 " bcount value is %d after io\n", 2565 device_xname(atac->atac_dev), chp->ch_channel, 2566 xfer->c_drive, xfer->c_bcount)); 2567 } 2568 #ifdef DIAGNOSTIC 2569 if (xfer->c_bcount < 0) { 2570 aprint_error_dev(atac->atac_dev, 2571 "channel %d drive %d: mvsata_atapi_intr:" 2572 " warning: bcount value is %d after io\n", 2573 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2574 } 2575 #endif 2576 2577 DPRINTF(DEBUG_XFERS, 2578 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2579 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2580 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2581 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2582 ata_channel_unlock(chp); 2583 mvsata_atapi_done(chp, xfer); 2584 } 2585 2586 static void 2587 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2588 { 2589 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2590 bool iserror = (sc_xfer->error != XS_NOERROR); 2591 2592 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2593 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2594 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2595 xfer->c_drive, (u_int)xfer->c_flags)); 2596 2597 if (ata_waitdrain_xfer_check(chp, xfer)) 2598 return; 2599 2600 /* mark controller inactive and free the command */ 2601 ata_deactivate_xfer(chp, xfer); 2602 2603 ata_free_xfer(chp, xfer); 2604 2605 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2606 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2607 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2608 scsipi_done(sc_xfer); 2609 DPRINTF(DEBUG_FUNCS, 2610 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2611 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2612 chp->ch_flags)); 2613 if (!iserror) 2614 atastart(chp); 2615 } 2616 2617 static void 2618 mvsata_atapi_polldsc(void *arg) 2619 { 2620 struct ata_channel *chp = arg; 2621 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 2622 2623 KASSERT(xfer != NULL); 2624 2625 ata_channel_lock(chp); 2626 2627 /* this will unlock channel lock too */ 2628 mvsata_atapi_phase_complete(xfer, 0); 2629 } 2630 #endif /* NATAPIBUS > 0 */ 2631 2632 2633 /* 2634 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2635 * if supported queuing command by atabus? The race condition will not happen 2636 * if this is called only to the thread of atabus. 2637 */ 2638 static int 2639 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2640 { 2641 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2642 struct ata_bio *ata_bio = &xfer->c_bio; 2643 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2644 struct eprd *eprd; 2645 bus_addr_t crqb_base_addr; 2646 bus_dmamap_t data_dmamap; 2647 uint32_t reg; 2648 int erqqip, erqqop, next, rv, i; 2649 2650 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2651 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2652 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2653 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2654 2655 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2656 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2657 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2658 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2659 next = erqqip; 2660 MVSATA_EDMAQ_INC(next); 2661 if (next == erqqop) { 2662 /* queue full */ 2663 return EBUSY; 2664 } 2665 DPRINTF(DEBUG_XFERS, 2666 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2667 2668 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2669 ata_bio->flags); 2670 if (rv != 0) 2671 return rv; 2672 2673 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2674 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2675 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2676 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2677 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2678 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2679 2680 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2681 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2682 eprd->eot = htole16(0); 2683 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2684 eprd++; 2685 } 2686 (eprd - 1)->eot |= htole16(EPRD_EOT); 2687 #ifdef MVSATA_DEBUG 2688 if (mvsata_debug >= 3) 2689 mvsata_print_eprd(mvport, xfer->c_slot); 2690 #endif 2691 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2692 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2693 BUS_DMASYNC_PREWRITE); 2694 2695 /* setup EDMA Command Request Block (CRQB) Data */ 2696 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2697 #ifdef MVSATA_DEBUG 2698 if (mvsata_debug >= 3) 2699 mvsata_print_crqb(mvport, erqqip); 2700 #endif 2701 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2702 erqqip * sizeof(union mvsata_crqb), 2703 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2704 2705 MVSATA_EDMAQ_INC(erqqip); 2706 2707 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2708 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2709 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2710 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2711 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2712 2713 return 0; 2714 } 2715 2716 static int 2717 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2718 { 2719 struct ata_channel *chp = &mvport->port_ata_channel; 2720 struct crpb *crpb; 2721 struct ata_bio *ata_bio; 2722 struct ata_xfer *xfer; 2723 uint32_t reg; 2724 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2725 int st, dmaerr; 2726 2727 /* First, Sync for Request Queue buffer */ 2728 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2729 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2730 if (mvport->port_prev_erqqop != erqqop) { 2731 const int s = sizeof(union mvsata_crqb); 2732 2733 if (mvport->port_prev_erqqop < erqqop) 2734 n = erqqop - mvport->port_prev_erqqop; 2735 else { 2736 if (erqqop > 0) 2737 bus_dmamap_sync(mvport->port_dmat, 2738 mvport->port_crqb_dmamap, 0, erqqop * s, 2739 BUS_DMASYNC_POSTWRITE); 2740 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2741 } 2742 if (n > 0) 2743 bus_dmamap_sync(mvport->port_dmat, 2744 mvport->port_crqb_dmamap, 2745 mvport->port_prev_erqqop * s, n * s, 2746 BUS_DMASYNC_POSTWRITE); 2747 mvport->port_prev_erqqop = erqqop; 2748 } 2749 2750 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2751 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2752 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2753 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2754 2755 DPRINTF(DEBUG_XFERS, 2756 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2757 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2758 mvport->port, erpqip, erpqop)); 2759 2760 if (erpqop == erpqip) 2761 return 0; 2762 2763 if (erpqop < erpqip) 2764 n = erpqip - erpqop; 2765 else { 2766 if (erpqip > 0) 2767 bus_dmamap_sync(mvport->port_dmat, 2768 mvport->port_crpb_dmamap, 2769 0, erpqip * sizeof(struct crpb), 2770 BUS_DMASYNC_POSTREAD); 2771 n = MVSATA_EDMAQ_LEN - erpqop; 2772 } 2773 if (n > 0) 2774 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2775 erpqop * sizeof(struct crpb), 2776 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2777 2778 uint32_t aslots = ata_queue_active(chp); 2779 2780 prev_erpqop = erpqop; 2781 while (erpqop != erpqip) { 2782 #ifdef MVSATA_DEBUG 2783 if (mvsata_debug >= 3) 2784 mvsata_print_crpb(mvport, erpqop); 2785 #endif 2786 crpb = mvport->port_crpb + erpqop; 2787 MVSATA_EDMAQ_INC(erpqop); 2788 2789 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2790 2791 if ((aslots & __BIT(quetag)) == 0) { 2792 /* not actually executing */ 2793 continue; 2794 } 2795 2796 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2797 2798 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2799 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2800 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2801 2802 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2803 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2804 2805 ata_bio = &xfer->c_bio; 2806 ata_bio->error = NOERROR; 2807 if (dmaerr != 0) 2808 ata_bio->error = ERR_DMA; 2809 2810 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2811 2812 KASSERT(xfer->c_flags & C_DMA); 2813 mvsata_bio_intr(chp, xfer, ATACH_ERR_ST(0, st)); 2814 2815 if (xfer1 == NULL) 2816 handled++; 2817 else if (xfer == xfer1) { 2818 handled = 1; 2819 break; 2820 } 2821 } 2822 if (prev_erpqop < erpqop) 2823 n = erpqop - prev_erpqop; 2824 else { 2825 if (erpqop > 0) 2826 bus_dmamap_sync(mvport->port_dmat, 2827 mvport->port_crpb_dmamap, 0, 2828 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2829 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2830 } 2831 if (n > 0) 2832 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2833 prev_erpqop * sizeof(struct crpb), 2834 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2835 2836 reg &= ~EDMA_RESQP_ERPQP_MASK; 2837 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2838 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2839 2840 return handled; 2841 } 2842 2843 static int 2844 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2845 { 2846 int xtime; 2847 2848 for (xtime = 0; xtime < timeout * 10; xtime++) { 2849 if (mvsata_edma_handle(mvport, xfer)) 2850 return 0; 2851 DELAY(100); 2852 } 2853 2854 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2855 mvsata_edma_rqq_remove(mvport, xfer); 2856 xfer->c_flags |= C_TIMEOU; 2857 return 1; 2858 } 2859 2860 static void 2861 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2862 { 2863 struct ata_channel *chp = &mvport->port_ata_channel; 2864 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2865 bus_addr_t crqb_base_addr; 2866 int erqqip, i; 2867 2868 /* First, hardware reset, stop EDMA */ 2869 mvsata_hreset_port(mvport); 2870 2871 /* cleanup completed EDMA safely */ 2872 mvsata_edma_handle(mvport, NULL); 2873 2874 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2875 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2876 2877 uint32_t aslots = ata_queue_active(chp); 2878 2879 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2880 struct ata_xfer *rqxfer; 2881 2882 if ((aslots & __BIT(i)) == 0) 2883 continue; 2884 2885 if (i == xfer->c_slot) { 2886 /* remove xfer from EDMA request queue */ 2887 bus_dmamap_sync(mvport->port_dmat, 2888 mvport->port_eprd_dmamap, 2889 mvport->port_reqtbl[i].eprd_offset, 2890 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2891 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 2892 /* quetag freed by caller later */ 2893 continue; 2894 } 2895 2896 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 2897 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 2898 erqqip++; 2899 } 2900 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2901 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2902 BUS_DMASYNC_POSTWRITE); 2903 2904 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 2905 mvsata_edma_reset_qptr(mvport); 2906 mvsata_edma_enable(mvport); 2907 2908 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2909 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2910 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2911 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2912 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2913 } 2914 2915 #if NATAPIBUS > 0 2916 static int 2917 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 2918 { 2919 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2920 struct eprd *eprd; 2921 bus_dmamap_t data_dmamap; 2922 bus_addr_t eprd_addr; 2923 int i, rv; 2924 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2925 2926 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2927 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2928 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2929 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2930 2931 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 2932 sc_xfer->datalen, 2933 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2934 if (rv != 0) 2935 return rv; 2936 2937 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2938 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2939 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2940 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2941 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2942 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2943 2944 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2945 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2946 eprd->eot = htole16(0); 2947 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2948 eprd++; 2949 } 2950 (eprd - 1)->eot |= htole16(EPRD_EOT); 2951 #ifdef MVSATA_DEBUG 2952 if (mvsata_debug >= 3) 2953 mvsata_print_eprd(mvport, xfer->c_slot); 2954 #endif 2955 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2956 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2957 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 2958 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2959 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 2960 2961 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2962 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2963 2964 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2965 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2966 else 2967 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2968 2969 return 0; 2970 } 2971 2972 static void 2973 mvsata_bdma_start(struct mvsata_port *mvport) 2974 { 2975 2976 #ifdef MVSATA_DEBUG 2977 if (mvsata_debug >= 3) 2978 mvsata_print_eprd(mvport, 0); 2979 #endif 2980 2981 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2982 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2983 } 2984 #endif 2985 #endif 2986 2987 2988 static int 2989 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2990 { 2991 struct mvsata_softc *sc = mvhc->hc_sc; 2992 struct mvsata_port *mvport; 2993 struct ata_channel *chp; 2994 int channel, rv, i; 2995 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2996 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2997 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2998 2999 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 3000 M_ZERO | M_WAITOK); 3001 mvport->port = port; 3002 mvport->port_hc = mvhc; 3003 mvport->port_edmamode_negotiated = nodma; 3004 3005 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3006 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3007 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3008 if (rv != 0) { 3009 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3010 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3011 goto fail0; 3012 } 3013 mvport->port_iot = mvhc->hc_iot; 3014 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3015 &mvport->port_sata_sstatus); 3016 if (rv != 0) { 3017 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3018 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3019 goto fail0; 3020 } 3021 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3022 &mvport->port_sata_serror); 3023 if (rv != 0) { 3024 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3025 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3026 goto fail0; 3027 } 3028 if (sc->sc_rev == gen1) 3029 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3030 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3031 else 3032 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3033 SATA_SC, 4, &mvport->port_sata_scontrol); 3034 if (rv != 0) { 3035 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3036 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3037 goto fail0; 3038 } 3039 mvport->port_dmat = sc->sc_dmat; 3040 mvhc->hc_ports[port] = mvport; 3041 3042 channel = mvhc->hc * sc->sc_port + port; 3043 chp = &mvport->port_ata_channel; 3044 chp->ch_channel = channel; 3045 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3046 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3047 sc->sc_ata_channels[channel] = chp; 3048 3049 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3050 if (rv != 0) 3051 goto fail0; 3052 3053 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3054 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3055 if (rv != 0) { 3056 aprint_error( 3057 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3058 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3059 goto fail0; 3060 } 3061 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3062 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3063 if (rv != 0) { 3064 aprint_error( 3065 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3066 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3067 goto fail1; 3068 } 3069 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3070 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3071 if (rv != 0) { 3072 aprint_error( 3073 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3074 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3075 goto fail2; 3076 } 3077 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3078 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3079 MVSATA_MAX_SEGS, MAXPHYS, 0, BUS_DMA_NOWAIT, 3080 &mvport->port_reqtbl[i].data_dmamap); 3081 if (rv != 0) { 3082 aprint_error("%s:%d:%d:" 3083 " EDMA data map(%d) create failed: error=%d\n", 3084 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3085 rv); 3086 goto fail3; 3087 } 3088 } 3089 3090 return 0; 3091 3092 fail3: 3093 for (i--; i >= 0; i--) 3094 bus_dmamap_destroy(mvport->port_dmat, 3095 mvport->port_reqtbl[i].data_dmamap); 3096 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3097 fail2: 3098 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3099 fail1: 3100 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3101 fail0: 3102 return rv; 3103 } 3104 3105 static int 3106 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3107 { 3108 int hc, port, rv, i; 3109 3110 hc = mvport->port_hc->hc; 3111 port = mvport->port; 3112 3113 /* Create subregion for Shadow Registers Map */ 3114 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3115 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3116 if (rv != 0) { 3117 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3118 device_xname(MVSATA_DEV2(mvport)), hc, port); 3119 return rv; 3120 } 3121 wdr->cmd_iot = mvport->port_iot; 3122 3123 /* Once create subregion for each command registers */ 3124 for (i = 0; i < WDC_NREG; i++) { 3125 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3126 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3127 if (rv != 0) { 3128 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3129 device_xname(MVSATA_DEV2(mvport)), hc, port); 3130 return rv; 3131 } 3132 } 3133 /* Create subregion for Alternate Status register */ 3134 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3135 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3136 if (rv != 0) { 3137 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3138 device_xname(MVSATA_DEV2(mvport)), hc, port); 3139 return rv; 3140 } 3141 wdr->ctl_iot = mvport->port_iot; 3142 3143 wdc_init_shadow_regs(wdr); 3144 3145 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3146 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3147 if (rv != 0) { 3148 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3149 device_xname(MVSATA_DEV2(mvport)), hc, port); 3150 return rv; 3151 } 3152 wdr->sata_iot = mvport->port_iot; 3153 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3154 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3155 if (rv != 0) { 3156 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3157 device_xname(MVSATA_DEV2(mvport)), hc, port); 3158 return rv; 3159 } 3160 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3161 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3162 if (rv != 0) { 3163 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3164 device_xname(MVSATA_DEV2(mvport)), hc, port); 3165 return rv; 3166 } 3167 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3168 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3169 if (rv != 0) { 3170 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3171 device_xname(MVSATA_DEV2(mvport)), hc, port); 3172 return rv; 3173 } 3174 3175 return 0; 3176 } 3177 3178 3179 #ifndef MVSATA_WITHOUTDMA 3180 static void * 3181 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3182 bus_dmamap_t *dmamap, size_t size, int write) 3183 { 3184 bus_dma_segment_t seg; 3185 int nseg, rv; 3186 void *kva; 3187 3188 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3189 BUS_DMA_NOWAIT); 3190 if (rv != 0) { 3191 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3192 device_xname(MVSATA_DEV2(mvport)), 3193 mvport->port_hc->hc, mvport->port, rv); 3194 goto fail; 3195 } 3196 3197 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3198 if (rv != 0) { 3199 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3200 device_xname(MVSATA_DEV2(mvport)), 3201 mvport->port_hc->hc, mvport->port, rv); 3202 goto free; 3203 } 3204 3205 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3206 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3207 if (rv != 0) { 3208 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3209 device_xname(MVSATA_DEV2(mvport)), 3210 mvport->port_hc->hc, mvport->port, rv); 3211 goto unmap; 3212 } 3213 3214 if (!write) 3215 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3216 3217 return kva; 3218 3219 unmap: 3220 bus_dmamem_unmap(dmat, kva, size); 3221 free: 3222 bus_dmamem_free(dmat, &seg, nseg); 3223 fail: 3224 return NULL; 3225 } 3226 3227 /* ARGSUSED */ 3228 static void 3229 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3230 bus_dmamap_t dmamap, void *kva) 3231 { 3232 3233 bus_dmamap_unload(dmat, dmamap); 3234 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3235 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3236 } 3237 3238 static int 3239 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3240 size_t datalen, int flags) 3241 { 3242 int rv, lop, sop; 3243 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3244 3245 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3246 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3247 3248 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3249 NULL, BUS_DMA_NOWAIT | lop); 3250 if (rv) { 3251 aprint_error("%s:%d:%d: buffer load failed: error=%d\n", 3252 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3253 mvport->port, rv); 3254 return rv; 3255 } 3256 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3257 data_dmamap->dm_mapsize, sop); 3258 3259 return 0; 3260 } 3261 3262 static inline void 3263 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3264 { 3265 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3266 3267 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3268 data_dmamap->dm_mapsize, 3269 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3270 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3271 } 3272 #endif 3273 3274 static void 3275 mvsata_hreset_port(struct mvsata_port *mvport) 3276 { 3277 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3278 3279 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3280 3281 delay(25); /* allow reset propagation */ 3282 3283 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3284 3285 mvport->_fix_phy_param._fix_phy(mvport); 3286 3287 if (sc->sc_gen == gen1) 3288 delay(1000); 3289 } 3290 3291 static void 3292 mvsata_reset_port(struct mvsata_port *mvport) 3293 { 3294 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3295 3296 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3297 3298 mvsata_hreset_port(mvport); 3299 3300 if (device_is_a(parent, "pci")) 3301 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3302 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3303 else /* SoC */ 3304 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3305 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3306 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3307 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3308 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3309 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3310 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3311 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3312 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3313 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3314 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3315 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3316 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3317 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3318 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3319 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3320 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3321 } 3322 3323 static void 3324 mvsata_reset_hc(struct mvsata_hc *mvhc) 3325 { 3326 #if 0 3327 uint32_t val; 3328 #endif 3329 3330 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3331 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3332 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3333 3334 #if 0 /* XXXX needs? */ 3335 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3336 3337 /* 3338 * Keep the SS during power on and the reference clock bits (reset 3339 * sample) 3340 */ 3341 val = MVSATA_HC_READ_4(mvhc, 0x020); 3342 val &= 0x1c1c1c1c; 3343 val |= 0x03030303; 3344 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3345 #endif 3346 } 3347 3348 static uint32_t 3349 mvsata_softreset(struct mvsata_port *mvport, int flags) 3350 { 3351 struct ata_channel *chp = &mvport->port_ata_channel; 3352 uint32_t sig0 = ~0; 3353 int timeout; 3354 uint8_t st0; 3355 3356 ata_channel_lock_owned(chp); 3357 3358 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3359 delay(10); 3360 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3361 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3362 delay(10); 3363 3364 /* wait for BSY to deassert */ 3365 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3366 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3367 3368 if ((st0 & WDCS_BSY) == 0) { 3369 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3370 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3371 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3372 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3373 goto out; 3374 } 3375 ata_delay(chp, 10, "atarst", flags); 3376 } 3377 3378 aprint_error("%s:%d:%d: %s: timeout\n", 3379 device_xname(MVSATA_DEV2(mvport)), 3380 mvport->port_hc->hc, mvport->port, __func__); 3381 3382 out: 3383 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3384 return sig0; 3385 } 3386 3387 #ifndef MVSATA_WITHOUTDMA 3388 static void 3389 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3390 { 3391 const bus_addr_t crpb_addr = 3392 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3393 const uint32_t crpb_addr_mask = 3394 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3395 3396 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3397 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3398 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3399 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3400 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3401 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3402 } 3403 3404 static inline void 3405 mvsata_edma_enable(struct mvsata_port *mvport) 3406 { 3407 3408 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3409 } 3410 3411 static void 3412 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3413 { 3414 struct ata_channel *chp = &mvport->port_ata_channel; 3415 uint32_t command; 3416 int t; 3417 3418 ata_channel_lock_owned(chp); 3419 3420 /* The disable bit (eDsEDMA) is self negated. */ 3421 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3422 3423 timeout = mstohz(timeout + hztoms(1) - 1); 3424 3425 for (t = 0; ; ++t) { 3426 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3427 if (!(command & EDMA_CMD_EENEDMA)) 3428 return; 3429 if (t >= timeout) 3430 break; 3431 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3432 } 3433 3434 aprint_error("%s:%d:%d: unable to disable EDMA\n", 3435 device_xname(MVSATA_DEV2(mvport)), 3436 mvport->port_hc->hc, mvport->port); 3437 } 3438 3439 /* 3440 * Set EDMA registers according to mode. 3441 * ex. NCQ/TCQ(queued)/non queued. 3442 */ 3443 static void 3444 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3445 { 3446 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3447 uint32_t reg; 3448 3449 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3450 reg |= EDMA_CFG_RESERVED; 3451 3452 if (mode == ncq) { 3453 if (sc->sc_gen == gen1) { 3454 aprint_error_dev(MVSATA_DEV2(mvport), 3455 "GenI not support NCQ\n"); 3456 return; 3457 } else if (sc->sc_gen == gen2) 3458 reg |= EDMA_CFG_EDEVERR; 3459 reg |= EDMA_CFG_ESATANATVCMDQUE; 3460 } else if (mode == queued) { 3461 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3462 reg |= EDMA_CFG_EQUE; 3463 } else 3464 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3465 3466 if (sc->sc_gen == gen1) 3467 reg |= EDMA_CFG_ERDBSZ; 3468 else if (sc->sc_gen == gen2) 3469 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3470 else if (sc->sc_gen == gen2e) { 3471 device_t parent = device_parent(MVSATA_DEV(sc)); 3472 3473 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3474 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3475 3476 if (device_is_a(parent, "pci")) 3477 reg |= ( 3478 #if NATAPIBUS > 0 3479 EDMA_CFG_EEARLYCOMPLETIONEN | 3480 #endif 3481 EDMA_CFG_ECUTTHROUGHEN | 3482 EDMA_CFG_EWRBUFFERLEN | 3483 EDMA_CFG_ERDBSZEXT); 3484 } 3485 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3486 3487 reg = ( 3488 EDMA_IE_EIORDYERR | 3489 EDMA_IE_ETRANSINT | 3490 EDMA_IE_EDEVCON | 3491 EDMA_IE_EDEVDIS); 3492 if (sc->sc_gen != gen1) 3493 reg |= ( 3494 EDMA_IE_TRANSPROTERR | 3495 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3496 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3497 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3498 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3499 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3500 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3501 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3502 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3503 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3504 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3505 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3506 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3507 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3508 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3509 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3510 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3511 EDMA_IE_ESELFDIS); 3512 3513 if (mode == ncq) 3514 reg |= EDMA_IE_EDEVERR; 3515 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3516 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3517 reg &= ~EDMA_IE_EDEVERR; 3518 if (mode != ncq) 3519 reg |= EDMA_IE_EDEVERR; 3520 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3521 if (sc->sc_gen == gen2e) { 3522 /* 3523 * Clear FISWait4HostRdyEn[0] and [2]. 3524 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3525 * [2]: SDB FIS is received with <ERR> bit set to 1. 3526 */ 3527 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3528 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3529 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3530 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3531 } 3532 3533 mvport->port_edmamode_curr = mode; 3534 } 3535 3536 3537 /* 3538 * Generation dependent functions 3539 */ 3540 3541 static void 3542 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3543 struct ata_xfer *xfer) 3544 { 3545 struct crqb *crqb; 3546 bus_addr_t eprd_addr; 3547 daddr_t blkno; 3548 uint32_t rw; 3549 uint8_t cmd, head; 3550 int i; 3551 struct ata_bio *ata_bio = &xfer->c_bio; 3552 3553 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3554 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3555 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3556 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3557 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3558 head = WDSD_LBA; 3559 } else { 3560 head = 0; 3561 } 3562 blkno = ata_bio->blkno; 3563 if (ata_bio->flags & ATA_LBA48) 3564 cmd = atacmd_to48(cmd); 3565 else { 3566 head |= ((ata_bio->blkno >> 24) & 0xf); 3567 blkno &= 0xffffff; 3568 } 3569 crqb = &mvport->port_crqb->crqb + erqqip; 3570 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3571 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3572 crqb->ctrlflg = 3573 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3574 CRQB_CPMPORT(xfer->c_drive)); 3575 i = 0; 3576 if (mvport->port_edmamode_curr == dma) { 3577 if (ata_bio->flags & ATA_LBA48) 3578 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3579 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3580 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3581 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3582 } else { /* ncq/queued */ 3583 3584 /* 3585 * XXXX: Oops, ata command is not correct. And, atabus layer 3586 * has not been supported yet now. 3587 * Queued DMA read/write. 3588 * read/write FPDMAQueued. 3589 */ 3590 3591 if (ata_bio->flags & ATA_LBA48) 3592 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3593 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3594 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3595 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3596 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3597 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3598 } 3599 if (ata_bio->flags & ATA_LBA48) { 3600 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3601 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3602 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3603 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3604 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3605 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3606 } 3607 crqb->atacommand[i++] = 3608 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3609 crqb->atacommand[i++] = 3610 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3611 crqb->atacommand[i++] = 3612 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3613 crqb->atacommand[i++] = 3614 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3615 crqb->atacommand[i++] = htole16( 3616 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3617 CRQB_ATACOMMAND_LAST); 3618 } 3619 #endif 3620 3621 static uint32_t 3622 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3623 { 3624 struct mvsata_hc *hc = mvport->port_hc; 3625 uint32_t reg; 3626 3627 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3628 /* 3629 * [12:11] : pre 3630 * [7:5] : amps 3631 */ 3632 return reg & 0x000018e0; 3633 } 3634 3635 static void 3636 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3637 { 3638 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3639 struct mvsata_hc *mvhc = mvport->port_hc; 3640 uint32_t reg; 3641 int port = mvport->port, fix_apm_sq = 0; 3642 3643 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3644 if (sc->sc_rev == 0x01) 3645 fix_apm_sq = 1; 3646 } else { 3647 if (sc->sc_rev == 0x00) 3648 fix_apm_sq = 1; 3649 } 3650 3651 if (fix_apm_sq) { 3652 /* 3653 * Disable auto-power management 3654 * 88SX50xx FEr SATA#12 3655 */ 3656 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3657 reg |= (1 << 19); 3658 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3659 3660 /* 3661 * Fix squelch threshold 3662 * 88SX50xx FEr SATA#9 3663 */ 3664 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3665 reg &= ~0x3; 3666 reg |= 0x1; 3667 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3668 } 3669 3670 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3671 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3672 reg &= ~0x000018e0; /* pre and amps mask */ 3673 reg |= mvport->_fix_phy_param.pre_amps; 3674 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3675 } 3676 3677 static void 3678 mvsata_devconn_gen1(struct mvsata_port *mvport) 3679 { 3680 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3681 3682 /* Fix for 88SX50xx FEr SATA#2 */ 3683 mvport->_fix_phy_param._fix_phy(mvport); 3684 3685 /* If disk is connected, then enable the activity LED */ 3686 if (sc->sc_rev == 0x03) { 3687 /* XXXXX */ 3688 } 3689 } 3690 3691 static uint32_t 3692 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3693 { 3694 uint32_t reg; 3695 3696 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3697 /* 3698 * [10:8] : amps 3699 * [7:5] : pre 3700 */ 3701 return reg & 0x000007e0; 3702 } 3703 3704 static void 3705 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3706 { 3707 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3708 uint32_t reg; 3709 3710 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3711 sc->sc_gen == gen2e) { 3712 /* 3713 * Fix for 3714 * 88SX60X1 FEr SATA #23 3715 * 88SX6042/88SX7042 FEr SATA #23 3716 * 88F5182 FEr #SATA-S13 3717 * 88F5082 FEr #SATA-S13 3718 */ 3719 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3720 reg &= ~(1 << 16); 3721 reg |= (1 << 31); 3722 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3723 3724 delay(200); 3725 3726 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3727 reg &= ~((1 << 16) | (1 << 31)); 3728 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3729 3730 delay(200); 3731 } 3732 3733 /* Fix values in PHY Mode 3 Register.*/ 3734 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3735 reg &= ~0x7F900000; 3736 reg |= 0x2A800000; 3737 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3738 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3739 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3740 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3741 reg &= ~0x0000001c; 3742 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3743 3744 /* 3745 * Fix values in PHY Mode 4 Register. 3746 * 88SX60x1 FEr SATA#10 3747 * 88F5182 GL #SATA-S10 3748 * 88F5082 GL #SATA-S10 3749 */ 3750 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3751 sc->sc_gen == gen2e) { 3752 uint32_t tmp = 0; 3753 3754 /* 88SX60x1 FEr SATA #13 */ 3755 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3756 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3757 3758 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3759 reg |= (1 << 0); 3760 reg &= ~(1 << 1); 3761 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3762 if (sc->sc_gen == gen2e) { 3763 reg &= ~0x5de3fffc; 3764 reg |= (1 << 2); 3765 } 3766 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3767 3768 /* 88SX60x1 FEr SATA #13 */ 3769 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3770 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3771 } 3772 3773 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3774 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3775 reg &= ~0x000007e0; /* pre and amps mask */ 3776 reg |= mvport->_fix_phy_param.pre_amps; 3777 reg &= ~(1 << 16); 3778 if (sc->sc_gen == gen2e) { 3779 /* 3780 * according to mvSata 3.6.1, some IIE values are fixed. 3781 * some reserved fields must be written with fixed values. 3782 */ 3783 reg &= ~0xC30FF01F; 3784 reg |= 0x0000900F; 3785 } 3786 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3787 } 3788 3789 #ifndef MVSATA_WITHOUTDMA 3790 static void 3791 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3792 struct ata_xfer *xfer) 3793 { 3794 struct crqb_gen2e *crqb; 3795 bus_addr_t eprd_addr; 3796 uint32_t ctrlflg, rw; 3797 uint8_t fis[RHD_FISLEN]; 3798 3799 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3800 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3801 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3802 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3803 CRQB_CPMPORT(xfer->c_drive) | 3804 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3805 3806 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3807 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3808 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3809 crqb->ctrlflg = htole32(ctrlflg); 3810 3811 satafis_rhd_construct_bio(xfer, fis); 3812 3813 crqb->atacommand[0] = 0; 3814 crqb->atacommand[1] = 0; 3815 /* copy over the ATA command part of the fis */ 3816 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3817 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3818 } 3819 3820 #ifdef MVSATA_DEBUG 3821 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3822 do { \ 3823 int _i; \ 3824 u_char *_p = (p); \ 3825 \ 3826 printf(#type "(%d)", (n)); \ 3827 for (_i = 0; _i < (size); _i++, _p++) { \ 3828 if (_i % 16 == 0) \ 3829 printf("\n "); \ 3830 printf(" %02x", *_p); \ 3831 } \ 3832 printf("\n"); \ 3833 } while (0 /* CONSTCOND */) 3834 3835 static void 3836 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3837 { 3838 3839 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3840 n, (u_char *)(mvport->port_crqb + n)); 3841 } 3842 3843 static void 3844 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3845 { 3846 3847 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3848 n, (u_char *)(mvport->port_crpb + n)); 3849 } 3850 3851 static void 3852 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3853 { 3854 struct eprd *eprd; 3855 int i = 0; 3856 3857 eprd = mvport->port_reqtbl[n].eprd; 3858 while (1 /*CONSTCOND*/) { 3859 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3860 i, (u_char *)eprd); 3861 if (eprd->eot & EPRD_EOT) 3862 break; 3863 eprd++; 3864 i++; 3865 } 3866 } 3867 #endif 3868 #endif 3869
Indexes created Mon Sep 22 13:09:51 GMT 2025