mvsata.c revision 1.59
1 /* $NetBSD: mvsata.c,v 1.59 2021/04/24 23:36:55 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.59 2021/04/24 23:36:55 thorpej Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 /* 62 * Nice things to do: 63 * 64 * - MSI/MSI-X support - though on some models MSI actually doesn't work 65 * even when hardware claims to support it, according to FreeBSD/OpenBSD 66 * - move pci-specific code to the pci attach code 67 * - mvsata(4) use 64-bit DMA on hardware which claims to support it 68 * - e.g. AHA1430SA does not really work, crash in mvsata_intr() on boot 69 */ 70 71 #include <dev/ic/mvsatareg.h> 72 #include <dev/ic/mvsatavar.h> 73 74 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 75 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 76 77 #define MVSATA_HC_READ_4(hc, reg) \ 78 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 79 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 80 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 81 #define MVSATA_EDMA_READ_4(mvport, reg) \ 82 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 83 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 84 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 85 #define MVSATA_WDC_READ_2(mvport, reg) \ 86 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 87 SHADOW_REG_BLOCK_OFFSET + (reg)) 88 #define MVSATA_WDC_READ_1(mvport, reg) \ 89 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 90 SHADOW_REG_BLOCK_OFFSET + (reg)) 91 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 92 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 93 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 94 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 95 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 96 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 97 98 #ifdef MVSATA_DEBUG 99 100 #define DEBUG_INTR 0x01 101 #define DEBUG_XFERS 0x02 102 #define DEBUG_FUNCS 0x08 103 #define DEBUG_PROBE 0x10 104 105 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 106 int mvsata_debug = 0; 107 #else 108 #define DPRINTF(n,x) 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 113 sending a cmd */ 114 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 115 116 #define MVSATA_MAX_SEGS (MAXPHYS / PAGE_SIZE + 1) 117 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * MVSATA_MAX_SEGS) 118 119 120 static void mvsata_probe_drive(struct ata_channel *); 121 122 #ifndef MVSATA_WITHOUTDMA 123 static void mvsata_reset_channel(struct ata_channel *, int); 124 static void mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 125 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 126 static void mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 127 static int mvsata_addref(struct ata_drive_datas *); 128 static void mvsata_delref(struct ata_drive_datas *); 129 static void mvsata_killpending(struct ata_drive_datas *); 130 131 #if NATAPIBUS > 0 132 static void mvsata_atapibus_attach(struct atabus_softc *); 133 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 134 scsipi_adapter_req_t, void *); 135 static void mvsata_atapi_minphys(struct buf *); 136 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 137 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 138 #endif 139 #endif 140 141 static void mvsata_setup_channel(struct ata_channel *); 142 143 #ifndef MVSATA_WITHOUTDMA 144 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 145 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 146 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 147 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 148 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 149 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 150 int); 151 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 152 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 153 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 154 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 155 int); 156 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 157 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 158 #if NATAPIBUS > 0 159 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 160 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 161 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 162 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 163 int); 164 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 165 static void mvsata_atapi_phase_complete(struct ata_xfer *, int); 166 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 167 static void mvsata_atapi_polldsc(void *); 168 #endif 169 170 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 171 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 172 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 173 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 174 #if NATAPIBUS > 0 175 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 176 static void mvsata_bdma_start(struct mvsata_port *); 177 #endif 178 #endif 179 180 static int mvsata_nondma_handle(struct mvsata_port *); 181 182 static int mvsata_port_init(struct mvsata_hc *, int); 183 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 184 #ifndef MVSATA_WITHOUTDMA 185 static void mvsata_channel_recover(struct ata_channel *, int, uint32_t); 186 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 187 bus_dmamap_t *, size_t, int); 188 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 189 bus_dmamap_t, void *); 190 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 191 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 192 #endif 193 194 static void mvsata_hreset_port(struct mvsata_port *); 195 static void mvsata_reset_port(struct mvsata_port *); 196 static void mvsata_reset_hc(struct mvsata_hc *); 197 static uint32_t mvsata_softreset(struct mvsata_port *, int); 198 #ifndef MVSATA_WITHOUTDMA 199 static void mvsata_edma_reset_qptr(struct mvsata_port *); 200 static inline void mvsata_edma_enable(struct mvsata_port *); 201 static void mvsata_edma_disable(struct mvsata_port *, int, int); 202 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 203 204 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 205 struct ata_xfer *); 206 #endif 207 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 208 static void mvsata_fix_phy_gen1(struct mvsata_port *); 209 static void mvsata_devconn_gen1(struct mvsata_port *); 210 211 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 212 static void mvsata_fix_phy_gen2(struct mvsata_port *); 213 #ifndef MVSATA_WITHOUTDMA 214 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 215 struct ata_xfer *); 216 217 #ifdef MVSATA_DEBUG 218 static void mvsata_print_crqb(struct mvsata_port *, int); 219 static void mvsata_print_crpb(struct mvsata_port *, int); 220 static void mvsata_print_eprd(struct mvsata_port *, int); 221 #endif 222 223 static const struct ata_bustype mvsata_ata_bustype = { 224 .bustype_type = SCSIPI_BUSTYPE_ATA, 225 .ata_bio = mvsata_bio, 226 .ata_reset_drive = mvsata_reset_drive, 227 .ata_reset_channel = mvsata_reset_channel, 228 .ata_exec_command = mvsata_exec_command, 229 .ata_get_params = ata_get_params, 230 .ata_addref = mvsata_addref, 231 .ata_delref = mvsata_delref, 232 .ata_killpending = mvsata_killpending, 233 .ata_recovery = mvsata_channel_recover, 234 }; 235 236 #if NATAPIBUS > 0 237 static const struct scsipi_bustype mvsata_atapi_bustype = { 238 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 239 .bustype_cmd = atapi_scsipi_cmd, 240 .bustype_interpret_sense = atapi_interpret_sense, 241 .bustype_printaddr = atapi_print_addr, 242 .bustype_kill_pending = mvsata_atapi_kill_pending, 243 .bustype_async_event_xfer_mode = NULL, 244 }; 245 #endif /* NATAPIBUS */ 246 #endif 247 248 static void 249 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 250 { 251 uint32_t ifctl; 252 253 KASSERT(pmpport < PMP_MAX_DRIVES); 254 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 255 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 256 panic("EDMA enabled"); 257 } 258 #endif 259 260 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 261 ifctl &= ~0xf; 262 ifctl |= pmpport; 263 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 264 } 265 266 int 267 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 268 int (*mvsata_sreset)(struct mvsata_softc *), 269 int (*mvsata_misc_reset)(struct mvsata_softc *), 270 int read_pre_amps) 271 { 272 struct mvsata_hc *mvhc; 273 struct mvsata_port *mvport; 274 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 275 void (*_fix_phy)(struct mvsata_port *) = NULL; 276 #ifndef MVSATA_WITHOUTDMA 277 void (*edma_setup_crqb) 278 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 279 #endif 280 int hc, port, channel; 281 282 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 283 (product->generation == gen1) ? "I" : 284 ((product->generation == gen2) ? "II" : "IIe"), 285 product->hc, product->port); 286 287 288 switch (product->generation) { 289 case gen1: 290 mvsata_sreset = NULL; 291 read_pre_amps = 1; /* MUST */ 292 read_preamps = mvsata_read_preamps_gen1; 293 _fix_phy = mvsata_fix_phy_gen1; 294 #ifndef MVSATA_WITHOUTDMA 295 edma_setup_crqb = mvsata_edma_setup_crqb; 296 #endif 297 break; 298 299 case gen2: 300 read_preamps = mvsata_read_preamps_gen2; 301 _fix_phy = mvsata_fix_phy_gen2; 302 #ifndef MVSATA_WITHOUTDMA 303 edma_setup_crqb = mvsata_edma_setup_crqb; 304 #endif 305 break; 306 307 case gen2e: 308 read_preamps = mvsata_read_preamps_gen2; 309 _fix_phy = mvsata_fix_phy_gen2; 310 #ifndef MVSATA_WITHOUTDMA 311 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 312 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 313 #endif 314 break; 315 } 316 317 sc->sc_gen = product->generation; 318 sc->sc_hc = product->hc; 319 sc->sc_port = product->port; 320 sc->sc_flags = product->flags; 321 322 #ifdef MVSATA_WITHOUTDMA 323 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 324 #else 325 sc->sc_edma_setup_crqb = edma_setup_crqb; 326 sc->sc_wdcdev.sc_atac.atac_cap |= 327 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 328 #endif 329 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 330 #ifdef MVSATA_WITHOUTDMA 331 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 333 #else 334 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 335 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 336 #endif 337 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 338 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 339 #ifndef MVSATA_WITHOUTDMA 340 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 341 #if NATAPIBUS > 0 342 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 343 #endif 344 #endif 345 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 346 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 347 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 348 349 sc->sc_wdc_regs = 350 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 351 M_DEVBUF, M_WAITOK); 352 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 353 354 for (hc = 0; hc < sc->sc_hc; hc++) { 355 mvhc = &sc->sc_hcs[hc]; 356 mvhc->hc = hc; 357 mvhc->hc_sc = sc; 358 mvhc->hc_iot = sc->sc_iot; 359 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 360 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 361 &mvhc->hc_ioh)) { 362 aprint_error_dev(MVSATA_DEV(sc), 363 "can't subregion SATAHC %d registers\n", hc); 364 continue; 365 } 366 367 for (port = 0; port < sc->sc_port; port++) 368 if (mvsata_port_init(mvhc, port) == 0) { 369 int pre_amps; 370 371 mvport = mvhc->hc_ports[port]; 372 pre_amps = read_pre_amps ? 373 read_preamps(mvport) : 0x00000720; 374 mvport->_fix_phy_param.pre_amps = pre_amps; 375 mvport->_fix_phy_param._fix_phy = _fix_phy; 376 377 if (!mvsata_sreset) 378 mvsata_reset_port(mvport); 379 } 380 381 if (!mvsata_sreset) 382 mvsata_reset_hc(mvhc); 383 } 384 if (mvsata_sreset) 385 mvsata_sreset(sc); 386 387 if (mvsata_misc_reset) 388 mvsata_misc_reset(sc); 389 390 for (hc = 0; hc < sc->sc_hc; hc++) 391 for (port = 0; port < sc->sc_port; port++) { 392 mvport = sc->sc_hcs[hc].hc_ports[port]; 393 if (mvport == NULL) 394 continue; 395 if (mvsata_sreset) 396 mvport->_fix_phy_param._fix_phy(mvport); 397 } 398 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 399 wdcattach(sc->sc_ata_channels[channel]); 400 401 return 0; 402 } 403 404 int 405 mvsata_intr(struct mvsata_hc *mvhc) 406 { 407 struct mvsata_softc *sc = mvhc->hc_sc; 408 struct mvsata_port *mvport; 409 uint32_t cause; 410 int port, handled = 0; 411 412 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 413 414 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 415 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 416 417 if (cause & SATAHC_IC_SAINTCOAL) 418 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 419 cause &= ~SATAHC_IC_SAINTCOAL; 420 421 for (port = 0; port < sc->sc_port; port++) { 422 mvport = mvhc->hc_ports[port]; 423 424 if (cause & SATAHC_IC_DONE(port)) { 425 #ifndef MVSATA_WITHOUTDMA 426 handled = mvsata_edma_handle(mvport, NULL); 427 #endif 428 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 429 ~SATAHC_IC_DONE(port)); 430 } 431 432 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 433 (void) mvsata_nondma_handle(mvport); 434 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 435 ~SATAHC_IC_SADEVINTERRUPT(port)); 436 handled = 1; 437 } 438 } 439 440 return handled; 441 } 442 443 static int 444 mvsata_nondma_handle(struct mvsata_port *mvport) 445 { 446 struct ata_channel *chp = &mvport->port_ata_channel; 447 struct ata_xfer *xfer; 448 int ret; 449 450 /* 451 * The chip doesn't support several pending non-DMA commands, 452 * and the ata middle layer never issues several non-NCQ commands, 453 * so there must be exactly one active command at this moment. 454 */ 455 xfer = ata_queue_get_active_xfer(chp); 456 if (xfer == NULL) { 457 /* Can happen after error recovery, ignore */ 458 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 459 ("%s:%d: %s: intr without xfer\n", 460 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 461 __func__)); 462 return 0; 463 } 464 465 ret = xfer->ops->c_intr(chp, xfer, 1); 466 return (ret); 467 } 468 469 int 470 mvsata_error(struct mvsata_port *mvport) 471 { 472 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 473 uint32_t cause; 474 475 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 476 /* 477 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 478 * in EDMA_IEC. 479 */ 480 if (cause & EDMA_IE_SERRINT) { 481 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 482 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 483 } 484 if (cause & EDMA_IE_ETRANSINT) { 485 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 486 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 487 } 488 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 489 490 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 491 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 492 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 493 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 494 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 495 496 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 497 if (!cause) 498 return 0; 499 500 if (cause & EDMA_IE_EDEVDIS) { 501 aprint_normal("%s:%d:%d: device disconnect\n", 502 device_xname(MVSATA_DEV2(mvport)), 503 mvport->port_hc->hc, mvport->port); 504 } 505 if (cause & EDMA_IE_EDEVCON) { 506 if (sc->sc_gen == gen1) 507 mvsata_devconn_gen1(mvport); 508 509 DPRINTF(DEBUG_INTR, (" device connected\n")); 510 } 511 512 #ifndef MVSATA_WITHOUTDMA 513 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 514 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 515 switch (mvport->port_edmamode_curr) { 516 case dma: 517 case queued: 518 case ncq: 519 mvsata_edma_reset_qptr(mvport); 520 mvsata_edma_enable(mvport); 521 if (cause & EDMA_IE_EDEVERR) 522 break; 523 524 /* FALLTHROUGH */ 525 526 case nodma: 527 default: 528 DPRINTF(DEBUG_INTR, 529 ("%s:%d:%d: EDMA self disable happen 0x%x\n", 530 device_xname(MVSATA_DEV2(mvport)), 531 mvport->port_hc->hc, mvport->port, cause)); 532 break; 533 } 534 } 535 #endif 536 if (cause & EDMA_IE_ETRANSINT) { 537 /* hot plug the Port Multiplier */ 538 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 539 device_xname(MVSATA_DEV2(mvport)), 540 mvport->port_hc->hc, mvport->port); 541 } 542 if (cause & EDMA_IE_EDEVERR) { 543 struct ata_channel *chp = &mvport->port_ata_channel; 544 545 aprint_error("%s:%d:%d: device error, recovering\n", 546 device_xname(MVSATA_DEV2(mvport)), 547 mvport->port_hc->hc, mvport->port); 548 549 ata_channel_lock(chp); 550 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, 551 ATACH_ERR_ST(0, WDCS_ERR)); 552 ata_channel_unlock(chp); 553 } 554 555 return 1; 556 } 557 558 #ifndef MVSATA_WITHOUTDMA 559 static void 560 mvsata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 561 { 562 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 563 int drive; 564 565 ata_channel_lock_owned(chp); 566 567 if (chp->ch_ndrives > PMP_PORT_CTL) { 568 /* Get PM port number for the device in error. This device 569 * doesn't seem to have dedicated register for this, so just 570 * assume last selected port was the one. */ 571 /* XXX FIS-based switching */ 572 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 573 } else 574 drive = 0; 575 576 /* 577 * Controller doesn't need any special action. Simply execute 578 * READ LOG EXT for NCQ to unblock device processing, then continue 579 * as if nothing happened. 580 */ 581 582 ata_recovery_resume(chp, drive, tfd, AT_POLL); 583 584 /* Drive unblocked, back to normal operation */ 585 return; 586 } 587 #endif /* !MVSATA_WITHOUTDMA */ 588 589 /* 590 * ATA callback entry points 591 */ 592 593 static void 594 mvsata_probe_drive(struct ata_channel *chp) 595 { 596 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 597 uint32_t sstat, sig; 598 599 ata_channel_lock(chp); 600 601 sstat = sata_reset_interface(chp, mvport->port_iot, 602 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 603 switch (sstat) { 604 case SStatus_DET_DEV: 605 mvsata_pmp_select(mvport, PMP_PORT_CTL); 606 sig = mvsata_softreset(mvport, AT_WAIT); 607 sata_interpret_sig(chp, 0, sig); 608 break; 609 default: 610 break; 611 } 612 613 ata_channel_unlock(chp); 614 } 615 616 #ifndef MVSATA_WITHOUTDMA 617 static void 618 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 619 { 620 struct ata_channel *chp = drvp->chnl_softc; 621 struct mvsata_port *mvport = (struct mvsata_port *)chp; 622 uint32_t edma_c; 623 uint32_t sig; 624 625 ata_channel_lock_owned(chp); 626 627 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 628 629 DPRINTF(DEBUG_FUNCS, 630 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 631 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 632 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 633 634 if (edma_c & EDMA_CMD_EENEDMA) 635 mvsata_edma_disable(mvport, 10000, flags); 636 637 mvsata_pmp_select(mvport, drvp->drive); 638 639 sig = mvsata_softreset(mvport, flags); 640 641 if (sigp) 642 *sigp = sig; 643 644 if (edma_c & EDMA_CMD_EENEDMA) { 645 mvsata_edma_reset_qptr(mvport); 646 mvsata_edma_enable(mvport); 647 } 648 } 649 650 static void 651 mvsata_reset_channel(struct ata_channel *chp, int flags) 652 { 653 struct mvsata_port *mvport = (struct mvsata_port *)chp; 654 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 655 uint32_t sstat, ctrl; 656 657 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 658 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 659 660 ata_channel_lock_owned(chp); 661 662 mvsata_hreset_port(mvport); 663 sstat = sata_reset_interface(chp, mvport->port_iot, 664 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 665 666 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 667 sc->sc_gen != gen1) { 668 /* Downgrade to GenI */ 669 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 670 SControl_DET_DISABLE; 671 672 bus_space_write_4(mvport->port_iot, 673 mvport->port_sata_scontrol, 0, val); 674 675 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 676 ctrl &= ~(1 << 17); /* Disable GenII */ 677 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 678 679 mvsata_hreset_port(mvport); 680 sata_reset_interface(chp, mvport->port_iot, 681 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 682 flags); 683 } 684 685 ata_kill_active(chp, KILL_RESET, flags); 686 687 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 688 mvsata_edma_reset_qptr(mvport); 689 mvsata_edma_enable(mvport); 690 } 691 692 static int 693 mvsata_addref(struct ata_drive_datas *drvp) 694 { 695 696 return 0; 697 } 698 699 static void 700 mvsata_delref(struct ata_drive_datas *drvp) 701 { 702 703 return; 704 } 705 706 static void 707 mvsata_killpending(struct ata_drive_datas *drvp) 708 { 709 710 return; 711 } 712 713 #if NATAPIBUS > 0 714 static void 715 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 716 { 717 struct ata_channel *chp = ata_sc->sc_chan; 718 struct atac_softc *atac = chp->ch_atac; 719 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 720 struct scsipi_channel *chan = &chp->ch_atapi_channel; 721 722 /* 723 * Fill in the scsipi_adapter. 724 */ 725 adapt->adapt_dev = atac->atac_dev; 726 adapt->adapt_nchannels = atac->atac_nchannels; 727 adapt->adapt_request = mvsata_atapi_scsipi_request; 728 adapt->adapt_minphys = mvsata_atapi_minphys; 729 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 730 731 /* 732 * Fill in the scsipi_channel. 733 */ 734 memset(chan, 0, sizeof(*chan)); 735 chan->chan_adapter = adapt; 736 chan->chan_bustype = &mvsata_atapi_bustype; 737 chan->chan_channel = chp->ch_channel; 738 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 739 chan->chan_openings = 1; 740 chan->chan_max_periph = 1; 741 chan->chan_ntargets = 1; 742 chan->chan_nluns = 1; 743 744 chp->atapibus = config_found(ata_sc->sc_dev, chan, atapiprint, 745 CFARG_IATTR, "atapi", 746 CFARG_EOL); 747 } 748 749 static void 750 mvsata_atapi_minphys(struct buf *bp) 751 { 752 753 if (bp->b_bcount > MAXPHYS) 754 bp->b_bcount = MAXPHYS; 755 minphys(bp); 756 } 757 758 static void 759 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 760 { 761 struct scsipi_channel *chan = sc->sc_channel; 762 struct scsipi_periph *periph; 763 struct ataparams ids; 764 struct ataparams *id = &ids; 765 struct mvsata_softc *mvc = 766 device_private(chan->chan_adapter->adapt_dev); 767 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 768 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 769 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 770 struct scsipibus_attach_args sa; 771 char serial_number[21], model[41], firmware_revision[9]; 772 int s; 773 774 /* skip if already attached */ 775 if (scsipi_lookup_periph(chan, target, 0) != NULL) 776 return; 777 778 /* if no ATAPI device detected at attach time, skip */ 779 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 780 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 781 " drive %d not present\n", 782 device_xname(atac->atac_dev), chp->ch_channel, target)); 783 return; 784 } 785 786 /* Some ATAPI devices need a bit more time after software reset. */ 787 delay(5000); 788 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 789 #ifdef ATAPI_DEBUG_PROBE 790 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 791 device_xname(sc->sc_dev), target, 792 id->atap_config & ATAPI_CFG_CMD_MASK, 793 id->atap_config & ATAPI_CFG_DRQ_MASK); 794 #endif 795 periph = scsipi_alloc_periph(M_WAITOK); 796 periph->periph_dev = NULL; 797 periph->periph_channel = chan; 798 periph->periph_switch = &atapi_probe_periphsw; 799 periph->periph_target = target; 800 periph->periph_lun = 0; 801 periph->periph_quirks = PQUIRK_ONLYBIG; 802 803 #ifdef SCSIPI_DEBUG 804 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 805 SCSIPI_DEBUG_TARGET == target) 806 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 807 #endif 808 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 809 if (id->atap_config & ATAPI_CFG_REMOV) 810 periph->periph_flags |= PERIPH_REMOVABLE; 811 if (periph->periph_type == T_SEQUENTIAL) { 812 s = splbio(); 813 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 814 splx(s); 815 } 816 817 sa.sa_periph = periph; 818 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 819 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 820 T_REMOV : T_FIXED; 821 strnvisx(model, sizeof(model), id->atap_model, 40, 822 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 823 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 824 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 825 strnvisx(firmware_revision, sizeof(firmware_revision), 826 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 827 sa.sa_inqbuf.vendor = model; 828 sa.sa_inqbuf.product = serial_number; 829 sa.sa_inqbuf.revision = firmware_revision; 830 831 /* 832 * Determine the operating mode capabilities of the device. 833 */ 834 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 835 periph->periph_cap |= PERIPH_CAP_CMD16; 836 /* XXX This is gross. */ 837 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 838 839 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 840 841 if (drvp->drv_softc) 842 ata_probe_caps(drvp); 843 else { 844 s = splbio(); 845 drvp->drive_type = ATA_DRIVET_NONE; 846 splx(s); 847 } 848 } else { 849 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 850 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 851 device_xname(atac->atac_dev), chp->ch_channel, target)); 852 s = splbio(); 853 drvp->drive_type = ATA_DRIVET_NONE; 854 splx(s); 855 } 856 } 857 858 /* 859 * Kill off all pending xfers for a periph. 860 * 861 * Must be called at splbio(). 862 */ 863 static void 864 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 865 { 866 struct atac_softc *atac = 867 device_private(periph->periph_channel->chan_adapter->adapt_dev); 868 struct ata_channel *chp = 869 atac->atac_channels[periph->periph_channel->chan_channel]; 870 871 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 872 } 873 #endif /* NATAPIBUS > 0 */ 874 #endif /* MVSATA_WITHOUTDMA */ 875 876 877 /* 878 * mvsata_setup_channel() 879 * Setup EDMA registers and prepare/purge DMA resources. 880 * We assuming already stopped the EDMA. 881 */ 882 static void 883 mvsata_setup_channel(struct ata_channel *chp) 884 { 885 #ifndef MVSATA_WITHOUTDMA 886 struct mvsata_port *mvport = (struct mvsata_port *)chp; 887 struct ata_drive_datas *drvp; 888 int drive, s; 889 uint32_t edma_mode = nodma; 890 int i; 891 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 892 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 893 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 894 895 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 896 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 897 898 for (drive = 0; drive < chp->ch_ndrives; drive++) { 899 drvp = &chp->ch_drive[drive]; 900 901 /* If no drive, skip */ 902 if (drvp->drive_type == ATA_DRIVET_NONE) 903 continue; 904 905 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 906 /* use Ultra/DMA */ 907 s = splbio(); 908 drvp->drive_flags &= ~ATA_DRIVE_DMA; 909 splx(s); 910 } 911 912 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 913 if (drvp->drive_flags & ATA_DRIVE_NCQ) 914 edma_mode = ncq; 915 else if (drvp->drive_type == ATA_DRIVET_ATA) 916 edma_mode = dma; 917 } 918 } 919 920 DPRINTF(DEBUG_FUNCS, 921 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 922 923 if (edma_mode == nodma) { 924 no_edma: 925 if (mvport->port_crqb != NULL) 926 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 927 mvport->port_crqb_dmamap, mvport->port_crqb); 928 if (mvport->port_crpb != NULL) 929 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 930 mvport->port_crpb_dmamap, mvport->port_crpb); 931 if (mvport->port_eprd != NULL) 932 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 933 mvport->port_eprd_dmamap, mvport->port_eprd); 934 935 return; 936 } 937 938 if (mvport->port_crqb == NULL) 939 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 940 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 941 if (mvport->port_crpb == NULL) 942 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 943 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 944 if (mvport->port_eprd == NULL) { 945 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 946 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 947 1); 948 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 949 mvport->port_reqtbl[i].eprd_offset = 950 i * MVSATA_EPRD_MAX_SIZE; 951 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 952 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 953 } 954 } 955 956 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 957 mvport->port_eprd == NULL) { 958 aprint_error_dev(MVSATA_DEV2(mvport), 959 "channel %d: can't use EDMA\n", chp->ch_channel); 960 s = splbio(); 961 for (drive = 0; drive < chp->ch_ndrives; drive++) { 962 drvp = &chp->ch_drive[drive]; 963 964 /* If no drive, skip */ 965 if (drvp->drive_type == ATA_DRIVET_NONE) 966 continue; 967 968 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 969 } 970 splx(s); 971 goto no_edma; 972 } 973 974 mvsata_edma_config(mvport, edma_mode); 975 mvsata_edma_reset_qptr(mvport); 976 mvsata_edma_enable(mvport); 977 #endif 978 } 979 980 #ifndef MVSATA_WITHOUTDMA 981 static const struct ata_xfer_ops mvsata_bio_xfer_ops = { 982 .c_start = mvsata_bio_start, 983 .c_intr = mvsata_bio_intr, 984 .c_poll = mvsata_bio_poll, 985 .c_abort = mvsata_bio_done, 986 .c_kill_xfer = mvsata_bio_kill_xfer, 987 }; 988 989 static void 990 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 991 { 992 struct ata_channel *chp = drvp->chnl_softc; 993 struct atac_softc *atac = chp->ch_atac; 994 struct ata_bio *ata_bio = &xfer->c_bio; 995 996 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 997 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 998 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 999 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 1000 1001 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1002 ata_bio->flags |= ATA_POLL; 1003 if (ata_bio->flags & ATA_POLL) 1004 xfer->c_flags |= C_POLL; 1005 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1006 (ata_bio->flags & ATA_SINGLE) == 0) 1007 xfer->c_flags |= C_DMA; 1008 xfer->c_drive = drvp->drive; 1009 xfer->c_databuf = ata_bio->databuf; 1010 xfer->c_bcount = ata_bio->bcount; 1011 xfer->ops = &mvsata_bio_xfer_ops; 1012 ata_exec_xfer(chp, xfer); 1013 } 1014 1015 static int 1016 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1017 { 1018 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1019 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1020 struct atac_softc *atac = chp->ch_atac; 1021 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1022 struct ata_bio *ata_bio = &xfer->c_bio; 1023 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1024 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1025 u_int16_t cyl; 1026 u_int8_t head, sect, cmd = 0; 1027 int nblks, error, tfd; 1028 1029 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1030 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1031 1032 ata_channel_lock_owned(chp); 1033 1034 if (xfer->c_flags & C_DMA) 1035 if (drvp->n_xfers <= NXFER) 1036 drvp->n_xfers++; 1037 1038 /* 1039 * 1040 * When starting a multi-sector transfer, or doing single-sector 1041 * transfers... 1042 */ 1043 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1044 if (ata_bio->flags & ATA_SINGLE) 1045 nblks = 1; 1046 else 1047 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1048 /* Check for bad sectors and adjust transfer, if necessary. */ 1049 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1050 long blkdiff; 1051 int i; 1052 1053 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1054 i++) { 1055 blkdiff -= ata_bio->blkno; 1056 if (blkdiff < 0) 1057 continue; 1058 if (blkdiff == 0) 1059 /* Replace current block of transfer. */ 1060 ata_bio->blkno = 1061 drvp->lp->d_secperunit - 1062 drvp->lp->d_nsectors - i - 1; 1063 if (blkdiff < nblks) { 1064 /* Bad block inside transfer. */ 1065 ata_bio->flags |= ATA_SINGLE; 1066 nblks = 1; 1067 } 1068 break; 1069 } 1070 /* Transfer is okay now. */ 1071 } 1072 if (xfer->c_flags & C_DMA) { 1073 enum mvsata_edmamode dmamode; 1074 1075 ata_bio->nblks = nblks; 1076 ata_bio->nbytes = xfer->c_bcount; 1077 1078 /* switch to appropriate dma mode if necessary */ 1079 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1080 if (mvport->port_edmamode_curr != dmamode) 1081 mvsata_edma_config(mvport, dmamode); 1082 1083 if (xfer->c_flags & C_POLL) 1084 sc->sc_enable_intr(mvport, 0 /*off*/); 1085 error = mvsata_edma_enqueue(mvport, xfer); 1086 if (error) { 1087 if (error == EINVAL) { 1088 /* 1089 * We can't do DMA on this transfer 1090 * for some reason. Fall back to 1091 * PIO. 1092 */ 1093 xfer->c_flags &= ~C_DMA; 1094 error = 0; 1095 goto do_pio; 1096 } 1097 if (error == EBUSY) { 1098 aprint_error_dev(atac->atac_dev, 1099 "channel %d: EDMA Queue full\n", 1100 chp->ch_channel); 1101 /* 1102 * XXX: Perhaps, after it waits for 1103 * a while, it is necessary to call 1104 * bio_start again. 1105 */ 1106 } 1107 ata_bio->error = ERR_DMA; 1108 ata_bio->r_error = 0; 1109 return ATASTART_ABORT; 1110 } 1111 chp->ch_flags |= ATACH_DMA_WAIT; 1112 /* wait for irq */ 1113 goto intr; 1114 } /* else not DMA */ 1115 do_pio: 1116 if (ata_bio->flags & ATA_LBA48) { 1117 sect = 0; 1118 cyl = 0; 1119 head = 0; 1120 } else if (ata_bio->flags & ATA_LBA) { 1121 sect = (ata_bio->blkno >> 0) & 0xff; 1122 cyl = (ata_bio->blkno >> 8) & 0xffff; 1123 head = (ata_bio->blkno >> 24) & 0x0f; 1124 head |= WDSD_LBA; 1125 } else { 1126 int blkno = ata_bio->blkno; 1127 sect = blkno % drvp->lp->d_nsectors; 1128 sect++; /* Sectors begin with 1, not 0. */ 1129 blkno /= drvp->lp->d_nsectors; 1130 head = blkno % drvp->lp->d_ntracks; 1131 blkno /= drvp->lp->d_ntracks; 1132 cyl = blkno; 1133 head |= WDSD_CHS; 1134 } 1135 ata_bio->nblks = uimin(nblks, drvp->multi); 1136 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1137 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1138 if (ata_bio->nblks > 1) 1139 cmd = (ata_bio->flags & ATA_READ) ? 1140 WDCC_READMULTI : WDCC_WRITEMULTI; 1141 else 1142 cmd = (ata_bio->flags & ATA_READ) ? 1143 WDCC_READ : WDCC_WRITE; 1144 1145 /* EDMA disable, if enabled this channel. */ 1146 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1147 if (mvport->port_edmamode_curr != nodma) 1148 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1149 1150 mvsata_pmp_select(mvport, xfer->c_drive); 1151 1152 /* Do control operations specially. */ 1153 if (__predict_false(drvp->state < READY)) { 1154 /* 1155 * Actually, we want to be careful not to mess with 1156 * the control state if the device is currently busy, 1157 * but we can assume that we never get to this point 1158 * if that's the case. 1159 */ 1160 /* 1161 * If it's not a polled command, we need the kernel 1162 * thread 1163 */ 1164 if ((xfer->c_flags & C_POLL) == 0 1165 && !ata_is_thread_run(chp)) 1166 return ATASTART_TH; 1167 1168 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1169 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1170 return ATASTART_ABORT; 1171 } 1172 } 1173 1174 /* Initiate command! */ 1175 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1176 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1177 case WDCWAIT_OK: 1178 break; 1179 case WDCWAIT_TOUT: 1180 goto timeout; 1181 case WDCWAIT_THR: 1182 return ATASTART_TH; 1183 } 1184 if (ata_bio->flags & ATA_LBA48) 1185 wdccommandext(chp, 0, atacmd_to48(cmd), 1186 ata_bio->blkno, nblks, 0, WDSD_LBA); 1187 else 1188 wdccommand(chp, 0, cmd, cyl, 1189 head, sect, nblks, 1190 (drvp->lp->d_type == DKTYPE_ST506) ? 1191 drvp->lp->d_precompcyl / 4 : 0); 1192 } else if (ata_bio->nblks > 1) { 1193 /* The number of blocks in the last stretch may be smaller. */ 1194 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1195 if (ata_bio->nblks > nblks) { 1196 ata_bio->nblks = nblks; 1197 ata_bio->nbytes = xfer->c_bcount; 1198 } 1199 } 1200 /* If this was a write and not using DMA, push the data. */ 1201 if ((ata_bio->flags & ATA_READ) == 0) { 1202 /* 1203 * we have to busy-wait here, we can't rely on running in 1204 * thread context. 1205 */ 1206 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1207 aprint_error_dev(atac->atac_dev, 1208 "channel %d: drive %d timeout waiting for DRQ," 1209 " st=0x%02x, err=0x%02x\n", 1210 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1211 ATACH_ERR(tfd)); 1212 ata_bio->error = TIMEOUT; 1213 return ATASTART_ABORT; 1214 } 1215 if (ATACH_ST(tfd) & WDCS_ERR) { 1216 ata_bio->error = ERROR; 1217 ata_bio->r_error = ATACH_ERR(tfd); 1218 mvsata_bio_done(chp, xfer); 1219 return ATASTART_ABORT; 1220 } 1221 1222 wdc->dataout_pio(chp, drvp->drive_flags, 1223 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1224 } 1225 1226 intr: 1227 KASSERTMSG(((xfer->c_flags & C_DMA) != 0) 1228 == (mvport->port_edmamode_curr != nodma), 1229 "DMA mode mismatch: flags %x vs edmamode %d != %d", 1230 xfer->c_flags, mvport->port_edmamode_curr, nodma); 1231 1232 /* Wait for IRQ (either real or polled) */ 1233 if ((ata_bio->flags & ATA_POLL) != 0) { 1234 /* start timeout machinery */ 1235 callout_reset(&chp->c_timo_callout, 1236 mstohz(ATA_DELAY), wdctimeout, chp); 1237 return ATASTART_POLL; 1238 } else 1239 return ATASTART_STARTED; 1240 1241 timeout: 1242 aprint_error_dev(atac->atac_dev, 1243 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1244 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1245 ata_bio->error = TIMEOUT; 1246 return ATASTART_ABORT; 1247 } 1248 1249 static void 1250 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1251 { 1252 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1253 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1254 1255 /* Wait for at last 400ns for status bit to be valid */ 1256 delay(1); 1257 if (chp->ch_flags & ATACH_DMA_WAIT) { 1258 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1259 sc->sc_enable_intr(mvport, 1 /*on*/); 1260 chp->ch_flags &= ~ATACH_DMA_WAIT; 1261 } 1262 1263 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1264 KASSERT(xfer->c_flags & C_TIMEOU); 1265 mvsata_bio_intr(chp, xfer, 0); 1266 } 1267 } 1268 1269 static int 1270 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int intr_arg) 1271 { 1272 struct atac_softc *atac = chp->ch_atac; 1273 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1274 struct ata_bio *ata_bio = &xfer->c_bio; 1275 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1276 int irq = ISSET(xfer->c_flags, (C_POLL|C_TIMEOU)) ? 0 : 1; 1277 int tfd = 0; 1278 1279 if (ISSET(xfer->c_flags, C_DMA|C_RECOVERED) && irq) { 1280 /* Invoked via mvsata_edma_handle() or recovery */ 1281 tfd = intr_arg; 1282 1283 if (tfd > 0 && ata_bio->error == NOERROR) { 1284 if (ATACH_ST(tfd) & WDCS_ERR) 1285 ata_bio->error = ERROR; 1286 if (ATACH_ST(tfd) & WDCS_BSY) 1287 ata_bio->error = TIMEOUT; 1288 ata_bio->r_error = ATACH_ERR(tfd); 1289 } 1290 } 1291 1292 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1293 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1294 xfer->c_drive)); 1295 1296 /* Cleanup EDMA if invoked from wdctimeout()/ata_timeout() */ 1297 if (ISSET(xfer->c_flags, C_TIMEOU) && ISSET(xfer->c_flags, C_DMA) 1298 && !ISSET(xfer->c_flags, C_POLL)) { 1299 mvsata_edma_rqq_remove((struct mvsata_port *)chp, xfer); 1300 } 1301 1302 ata_channel_lock(chp); 1303 1304 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1305 1306 /* 1307 * If we missed an interrupt transfer, reset and restart. 1308 * Don't try to continue transfer, we may have missed cycles. 1309 */ 1310 if (xfer->c_flags & C_TIMEOU) { 1311 ata_bio->error = TIMEOUT; 1312 ata_channel_unlock(chp); 1313 mvsata_bio_done(chp, xfer); 1314 return 1; 1315 } 1316 1317 /* Is it not a transfer, but a control operation? */ 1318 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1319 aprint_error_dev(atac->atac_dev, 1320 "channel %d: drive %d bad state %d in %s\n", 1321 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1322 panic("%s: bad state", __func__); 1323 } 1324 1325 /* Ack interrupt done by wdc_wait_for_unbusy */ 1326 if (!(xfer->c_flags & C_DMA) && 1327 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1328 == WDCWAIT_TOUT)) { 1329 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1330 ata_channel_unlock(chp); 1331 return 0; /* IRQ was not for us */ 1332 } 1333 aprint_error_dev(atac->atac_dev, 1334 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1335 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1336 xfer->c_skip); 1337 ata_bio->error = TIMEOUT; 1338 ata_channel_unlock(chp); 1339 mvsata_bio_done(chp, xfer); 1340 return 1; 1341 } 1342 1343 if (xfer->c_flags & C_DMA) { 1344 if (ata_bio->error == NOERROR) 1345 goto end; 1346 if (ata_bio->error == ERR_DMA) { 1347 ata_dmaerr(drvp, 1348 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1349 ata_channel_unlock(chp); 1350 goto err; 1351 } 1352 } 1353 1354 /* if we had an error, end */ 1355 if (ata_bio->error != NOERROR) { 1356 ata_channel_unlock(chp); 1357 err: 1358 mvsata_bio_done(chp, xfer); 1359 return 1; 1360 } 1361 1362 /* If this was a read and not using DMA, fetch the data. */ 1363 if ((ata_bio->flags & ATA_READ) != 0) { 1364 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1365 aprint_error_dev(atac->atac_dev, 1366 "channel %d: drive %d read intr before drq\n", 1367 chp->ch_channel, xfer->c_drive); 1368 ata_bio->error = TIMEOUT; 1369 ata_channel_unlock(chp); 1370 mvsata_bio_done(chp, xfer); 1371 return 1; 1372 } 1373 wdc->datain_pio(chp, drvp->drive_flags, 1374 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1375 } 1376 1377 end: 1378 ata_bio->blkno += ata_bio->nblks; 1379 ata_bio->blkdone += ata_bio->nblks; 1380 xfer->c_skip += ata_bio->nbytes; 1381 xfer->c_bcount -= ata_bio->nbytes; 1382 1383 /* See if this transfer is complete. */ 1384 if (xfer->c_bcount > 0) { 1385 if ((ata_bio->flags & ATA_POLL) == 0) { 1386 /* Start the next operation */ 1387 ata_xfer_start(xfer); 1388 } else { 1389 /* Let mvsata_bio_start do the loop */ 1390 } 1391 ata_channel_unlock(chp); 1392 } else { /* Done with this transfer */ 1393 ata_bio->error = NOERROR; 1394 ata_channel_unlock(chp); 1395 mvsata_bio_done(chp, xfer); 1396 } 1397 return 1; 1398 } 1399 1400 static void 1401 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1402 { 1403 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1404 struct atac_softc *atac = chp->ch_atac; 1405 struct ata_bio *ata_bio = &xfer->c_bio; 1406 int drive = xfer->c_drive; 1407 bool deactivate = true; 1408 1409 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1410 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1411 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1412 1413 /* EDMA restart, if enabled */ 1414 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1415 mvsata_edma_reset_qptr(mvport); 1416 mvsata_edma_enable(mvport); 1417 } 1418 1419 ata_bio->flags |= ATA_ITSDONE; 1420 switch (reason) { 1421 case KILL_GONE_INACTIVE: 1422 deactivate = false; 1423 /* FALLTHROUGH */ 1424 case KILL_GONE: 1425 ata_bio->error = ERR_NODEV; 1426 break; 1427 case KILL_RESET: 1428 ata_bio->error = ERR_RESET; 1429 break; 1430 case KILL_REQUEUE: 1431 ata_bio->error = REQUEUE; 1432 break; 1433 default: 1434 aprint_error_dev(atac->atac_dev, 1435 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1436 panic("mvsata_bio_kill_xfer"); 1437 } 1438 ata_bio->r_error = WDCE_ABRT; 1439 1440 if (deactivate) 1441 ata_deactivate_xfer(chp, xfer); 1442 1443 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1444 } 1445 1446 static void 1447 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1448 { 1449 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1450 struct ata_bio *ata_bio = &xfer->c_bio; 1451 int drive = xfer->c_drive; 1452 bool iserror = (ata_bio->error != NOERROR); 1453 1454 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1455 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1456 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1457 (u_int)xfer->c_flags)); 1458 1459 /* EDMA restart, if enabled */ 1460 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1461 mvsata_edma_reset_qptr(mvport); 1462 mvsata_edma_enable(mvport); 1463 } 1464 1465 if (ata_waitdrain_xfer_check(chp, xfer)) 1466 return; 1467 1468 /* feed back residual bcount to our caller */ 1469 ata_bio->bcount = xfer->c_bcount; 1470 1471 /* mark controller inactive and free xfer */ 1472 ata_deactivate_xfer(chp, xfer); 1473 1474 ata_bio->flags |= ATA_ITSDONE; 1475 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1476 if (!iserror) 1477 atastart(chp); 1478 } 1479 1480 static int 1481 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1482 int flags) 1483 { 1484 struct ata_channel *chp = &mvport->port_ata_channel; 1485 struct atac_softc *atac = chp->ch_atac; 1486 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1487 const char *errstring; 1488 int tfd; 1489 1490 flags |= AT_POLL; /* XXX */ 1491 1492 ata_channel_lock_owned(chp); 1493 1494 /* 1495 * disable interrupts, all commands here should be quick 1496 * enough to be able to poll, and we don't go here that often 1497 */ 1498 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1499 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1500 DELAY(10); 1501 errstring = "wait"; 1502 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1503 goto ctrltimeout; 1504 wdccommandshort(chp, 0, WDCC_RECAL); 1505 /* Wait for at least 400ns for status bit to be valid */ 1506 DELAY(1); 1507 errstring = "recal"; 1508 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1509 goto ctrltimeout; 1510 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1511 goto ctrlerror; 1512 /* Don't try to set modes if controller can't be adjusted */ 1513 if (atac->atac_set_modes == NULL) 1514 goto geometry; 1515 /* Also don't try if the drive didn't report its mode */ 1516 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1517 goto geometry; 1518 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1519 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1520 errstring = "piomode-bio"; 1521 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1522 goto ctrltimeout; 1523 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1524 goto ctrlerror; 1525 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1526 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1527 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1528 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1529 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1530 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1531 else 1532 goto geometry; 1533 errstring = "dmamode-bio"; 1534 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1535 goto ctrltimeout; 1536 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1537 goto ctrlerror; 1538 geometry: 1539 if (ata_bio->flags & ATA_LBA) 1540 goto multimode; 1541 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1542 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1543 (drvp->lp->d_type == DKTYPE_ST506) ? 1544 drvp->lp->d_precompcyl / 4 : 0); 1545 errstring = "geometry"; 1546 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1547 goto ctrltimeout; 1548 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1549 goto ctrlerror; 1550 multimode: 1551 if (drvp->multi == 1) 1552 goto ready; 1553 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1554 errstring = "setmulti"; 1555 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1556 goto ctrltimeout; 1557 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1558 goto ctrlerror; 1559 ready: 1560 drvp->state = READY; 1561 /* 1562 * The drive is usable now 1563 */ 1564 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1565 delay(10); /* some drives need a little delay here */ 1566 return 0; 1567 1568 ctrltimeout: 1569 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1570 chp->ch_channel, drive, errstring); 1571 ata_bio->error = TIMEOUT; 1572 goto ctrldone; 1573 ctrlerror: 1574 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1575 chp->ch_channel, drive, errstring); 1576 if (ATACH_ST(tfd) & WDCS_DWF) { 1577 aprint_error("drive fault\n"); 1578 ata_bio->error = ERR_DF; 1579 } else { 1580 ata_bio->r_error = ATACH_ERR(tfd); 1581 ata_bio->error = ERROR; 1582 aprint_error("error (%x)\n", ata_bio->r_error); 1583 } 1584 ctrldone: 1585 drvp->state = 0; 1586 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1587 return -1; 1588 } 1589 1590 static const struct ata_xfer_ops mvsata_wdc_cmd_xfer_ops = { 1591 .c_start = mvsata_wdc_cmd_start, 1592 .c_intr = mvsata_wdc_cmd_intr, 1593 .c_poll = mvsata_wdc_cmd_poll, 1594 .c_abort = mvsata_wdc_cmd_done, 1595 .c_kill_xfer = mvsata_wdc_cmd_kill_xfer, 1596 }; 1597 1598 static void 1599 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1600 { 1601 struct ata_channel *chp = drvp->chnl_softc; 1602 struct ata_command *ata_c = &xfer->c_ata_c; 1603 1604 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1605 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1606 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1607 " r_device=0x%02x, r_command=0x%02x\n", 1608 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1609 chp->ch_channel, 1610 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1611 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1612 1613 if (ata_c->flags & AT_POLL) 1614 xfer->c_flags |= C_POLL; 1615 if (ata_c->flags & AT_WAIT) 1616 xfer->c_flags |= C_WAIT; 1617 xfer->c_drive = drvp->drive; 1618 xfer->c_databuf = ata_c->data; 1619 xfer->c_bcount = ata_c->bcount; 1620 xfer->ops = &mvsata_wdc_cmd_xfer_ops; 1621 1622 ata_exec_xfer(chp, xfer); 1623 } 1624 1625 static int 1626 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1627 { 1628 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1629 int drive = xfer->c_drive; 1630 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1631 struct ata_command *ata_c = &xfer->c_ata_c; 1632 int tfd; 1633 1634 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1635 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1636 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1637 1638 ata_channel_lock_owned(chp); 1639 1640 /* First, EDMA disable, if enabled this channel. */ 1641 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1642 if (mvport->port_edmamode_curr != nodma) 1643 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1644 1645 mvsata_pmp_select(mvport, drive); 1646 1647 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1648 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1649 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1650 case WDCWAIT_OK: 1651 break; 1652 case WDCWAIT_TOUT: 1653 ata_c->flags |= AT_TIMEOU; 1654 return ATASTART_ABORT; 1655 case WDCWAIT_THR: 1656 return ATASTART_TH; 1657 } 1658 if (ata_c->flags & AT_POLL) 1659 /* polled command, disable interrupts */ 1660 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1661 if ((ata_c->flags & AT_LBA48) != 0) { 1662 wdccommandext(chp, 0, ata_c->r_command, 1663 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1664 ata_c->r_device & ~0x10); 1665 } else { 1666 wdccommand(chp, 0, ata_c->r_command, 1667 (ata_c->r_lba >> 8) & 0xffff, 1668 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1669 ((ata_c->r_lba >> 24) & 0x0f), 1670 ata_c->r_lba & 0xff, 1671 ata_c->r_count & 0xff, 1672 ata_c->r_features & 0xff); 1673 } 1674 1675 if ((ata_c->flags & AT_POLL) == 0) { 1676 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1677 wdctimeout, chp); 1678 return ATASTART_STARTED; 1679 } 1680 1681 return ATASTART_POLL; 1682 } 1683 1684 static void 1685 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1686 { 1687 /* 1688 * Polled command. Wait for drive ready or drq. Done in intr(). 1689 * Wait for at last 400ns for status bit to be valid. 1690 */ 1691 delay(10); /* 400ns delay */ 1692 mvsata_wdc_cmd_intr(chp, xfer, 0); 1693 } 1694 1695 static int 1696 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1697 { 1698 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1699 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1700 struct ata_command *ata_c = &xfer->c_ata_c; 1701 int bcount = ata_c->bcount; 1702 char *data = ata_c->data; 1703 int wflags; 1704 int drive_flags; 1705 int tfd; 1706 1707 ata_channel_lock(chp); 1708 1709 if (ata_c->r_command == WDCC_IDENTIFY || 1710 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1711 /* 1712 * The IDENTIFY data has been designed as an array of 1713 * u_int16_t, so we can byteswap it on the fly. 1714 * Historically it's what we have always done so keeping it 1715 * here ensure binary backward compatibility. 1716 */ 1717 drive_flags = ATA_DRIVE_NOSTREAM | 1718 chp->ch_drive[xfer->c_drive].drive_flags; 1719 else 1720 /* 1721 * Other data structure are opaque and should be transferred 1722 * as is. 1723 */ 1724 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1725 1726 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1727 /* both wait and poll, we can kpause here */ 1728 wflags = AT_WAIT | AT_POLL; 1729 else 1730 wflags = AT_POLL; 1731 1732 again: 1733 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1734 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1735 __func__, xfer->c_drive)); 1736 1737 /* 1738 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1739 * Reselect again, it doesn't hurt for others commands, and the time 1740 * penalty for the extra register write is acceptable, 1741 * wdc_exec_command() isn't called often (mostly for autoconfig) 1742 */ 1743 if ((xfer->c_flags & C_ATAPI) != 0) { 1744 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1745 } 1746 if ((ata_c->flags & AT_XFDONE) != 0) { 1747 /* 1748 * We have completed a data xfer. The drive should now be 1749 * in its initial state 1750 */ 1751 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1752 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1753 wflags, &tfd) == WDCWAIT_TOUT) { 1754 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1755 ata_channel_unlock(chp); 1756 return 0; /* IRQ was not for us */ 1757 } 1758 ata_c->flags |= AT_TIMEOU; 1759 } 1760 goto out; 1761 } 1762 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1763 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1764 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1765 ata_channel_unlock(chp); 1766 return 0; /* IRQ was not for us */ 1767 } 1768 ata_c->flags |= AT_TIMEOU; 1769 goto out; 1770 } 1771 delay(20); /* XXXXX: Delay more times. */ 1772 if (ata_c->flags & AT_READ) { 1773 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1774 ata_c->flags |= AT_TIMEOU; 1775 goto out; 1776 } 1777 wdc->datain_pio(chp, drive_flags, data, bcount); 1778 /* at this point the drive should be in its initial state */ 1779 ata_c->flags |= AT_XFDONE; 1780 /* 1781 * XXX checking the status register again here cause some 1782 * hardware to timeout. 1783 */ 1784 } else if (ata_c->flags & AT_WRITE) { 1785 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1786 ata_c->flags |= AT_TIMEOU; 1787 goto out; 1788 } 1789 wdc->dataout_pio(chp, drive_flags, data, bcount); 1790 ata_c->flags |= AT_XFDONE; 1791 if ((ata_c->flags & AT_POLL) == 0) { 1792 callout_reset(&chp->c_timo_callout, 1793 mstohz(ata_c->timeout), wdctimeout, chp); 1794 ata_channel_unlock(chp); 1795 return 1; 1796 } else 1797 goto again; 1798 } 1799 out: 1800 if (ATACH_ST(tfd) & WDCS_DWF) 1801 ata_c->flags |= AT_DF; 1802 if (ATACH_ST(tfd) & WDCS_ERR) { 1803 ata_c->flags |= AT_ERROR; 1804 ata_c->r_error = ATACH_ERR(tfd); 1805 } 1806 ata_channel_unlock(chp); 1807 mvsata_wdc_cmd_done(chp, xfer); 1808 1809 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1810 atastart(chp); 1811 1812 return 1; 1813 } 1814 1815 static void 1816 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1817 int reason) 1818 { 1819 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1820 struct ata_command *ata_c = &xfer->c_ata_c; 1821 bool deactivate = true; 1822 1823 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1824 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1825 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1826 1827 switch (reason) { 1828 case KILL_GONE_INACTIVE: 1829 deactivate = false; 1830 /* FALLTHROUGH */ 1831 case KILL_GONE: 1832 ata_c->flags |= AT_GONE; 1833 break; 1834 case KILL_RESET: 1835 ata_c->flags |= AT_RESET; 1836 break; 1837 case KILL_REQUEUE: 1838 panic("%s: not supposed to be requeued\n", __func__); 1839 break; 1840 default: 1841 aprint_error_dev(MVSATA_DEV2(mvport), 1842 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1843 panic("mvsata_cmd_kill_xfer"); 1844 } 1845 1846 mvsata_wdc_cmd_done_end(chp, xfer); 1847 1848 if (deactivate) 1849 ata_deactivate_xfer(chp, xfer); 1850 } 1851 1852 static void 1853 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1854 { 1855 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1856 struct atac_softc *atac = chp->ch_atac; 1857 struct ata_command *ata_c = &xfer->c_ata_c; 1858 1859 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1860 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1861 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1862 ata_c->flags)); 1863 1864 if (ata_waitdrain_xfer_check(chp, xfer)) 1865 return; 1866 1867 if ((ata_c->flags & AT_READREG) != 0 && 1868 device_is_active(atac->atac_dev) && 1869 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1870 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1871 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1872 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1873 ata_c->r_lba = 1874 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1875 ata_c->r_lba |= 1876 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1877 ata_c->r_lba |= 1878 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1879 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1880 if ((ata_c->flags & AT_LBA48) != 0) { 1881 if ((ata_c->flags & AT_POLL) != 0) { 1882 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1883 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1884 } else { 1885 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1886 WDCTL_HOB|WDCTL_4BIT); 1887 } 1888 ata_c->r_count |= 1889 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1890 ata_c->r_lba |= 1891 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1892 ata_c->r_lba |= 1893 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1894 ata_c->r_lba |= 1895 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1896 if ((ata_c->flags & AT_POLL) != 0) { 1897 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1898 WDCTL_4BIT|WDCTL_IDS); 1899 } else { 1900 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1901 WDCTL_4BIT); 1902 } 1903 } else { 1904 ata_c->r_lba |= 1905 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1906 } 1907 } 1908 1909 if (ata_c->flags & AT_POLL) { 1910 /* enable interrupts */ 1911 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1912 delay(10); /* some drives need a little delay here */ 1913 } 1914 1915 mvsata_wdc_cmd_done_end(chp, xfer); 1916 1917 ata_deactivate_xfer(chp, xfer); 1918 } 1919 1920 static void 1921 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1922 { 1923 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1924 struct ata_command *ata_c = &xfer->c_ata_c; 1925 1926 /* EDMA restart, if enabled */ 1927 if (mvport->port_edmamode_curr != nodma) { 1928 mvsata_edma_reset_qptr(mvport); 1929 mvsata_edma_enable(mvport); 1930 } 1931 1932 ata_c->flags |= AT_DONE; 1933 } 1934 1935 #if NATAPIBUS > 0 1936 static const struct ata_xfer_ops mvsata_atapi_xfer_ops = { 1937 .c_start = mvsata_atapi_start, 1938 .c_intr = mvsata_atapi_intr, 1939 .c_poll = mvsata_atapi_poll, 1940 .c_abort = mvsata_atapi_reset, 1941 .c_kill_xfer = mvsata_atapi_kill_xfer, 1942 }; 1943 1944 static void 1945 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 1946 scsipi_adapter_req_t req, void *arg) 1947 { 1948 struct scsipi_adapter *adapt = chan->chan_adapter; 1949 struct scsipi_periph *periph; 1950 struct scsipi_xfer *sc_xfer; 1951 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 1952 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1953 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1954 struct ata_xfer *xfer; 1955 int drive, s; 1956 1957 switch (req) { 1958 case ADAPTER_REQ_RUN_XFER: 1959 sc_xfer = arg; 1960 periph = sc_xfer->xs_periph; 1961 drive = periph->periph_target; 1962 1963 if (!device_is_active(atac->atac_dev)) { 1964 sc_xfer->error = XS_DRIVER_STUFFUP; 1965 scsipi_done(sc_xfer); 1966 return; 1967 } 1968 xfer = ata_get_xfer(chp, false); 1969 if (xfer == NULL) { 1970 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1971 scsipi_done(sc_xfer); 1972 return; 1973 } 1974 1975 if (sc_xfer->xs_control & XS_CTL_POLL) 1976 xfer->c_flags |= C_POLL; 1977 xfer->c_drive = drive; 1978 xfer->c_flags |= C_ATAPI; 1979 xfer->c_databuf = sc_xfer->data; 1980 xfer->c_bcount = sc_xfer->datalen; 1981 xfer->ops = &mvsata_atapi_xfer_ops; 1982 xfer->c_scsipi = sc_xfer; 1983 xfer->c_atapi.c_dscpoll = 0; 1984 s = splbio(); 1985 ata_exec_xfer(chp, xfer); 1986 #ifdef DIAGNOSTIC 1987 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1988 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1989 panic("mvsata_atapi_scsipi_request:" 1990 " polled command not done"); 1991 #endif 1992 splx(s); 1993 return; 1994 1995 default: 1996 /* Not supported, nothing to do. */ 1997 ; 1998 } 1999 } 2000 2001 static int 2002 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2003 { 2004 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2005 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2006 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2007 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2008 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2009 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2010 const char *errstring; 2011 int tfd; 2012 2013 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2014 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2015 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2016 xfer->c_drive, sc_xfer->xs_control)); 2017 2018 ata_channel_lock_owned(chp); 2019 2020 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2021 if (mvport->port_edmamode_curr != nodma) 2022 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2023 2024 mvsata_pmp_select(mvport, xfer->c_drive); 2025 2026 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2027 drvp->n_xfers++; 2028 2029 /* Do control operations specially. */ 2030 if (__predict_false(drvp->state < READY)) { 2031 /* If it's not a polled command, we need the kernel thread */ 2032 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 2033 && !ata_is_thread_run(chp)) 2034 return ATASTART_TH; 2035 2036 /* 2037 * disable interrupts, all commands here should be quick 2038 * enough to be able to poll, and we don't go here that often 2039 */ 2040 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2041 2042 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2043 /* Don't try to set mode if controller can't be adjusted */ 2044 if (atac->atac_set_modes == NULL) 2045 goto ready; 2046 /* Also don't try if the drive didn't report its mode */ 2047 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2048 goto ready; 2049 errstring = "unbusy"; 2050 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2051 goto timeout; 2052 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2053 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2054 errstring = "piomode-atapi"; 2055 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2056 &tfd)) 2057 goto timeout; 2058 if (ATACH_ST(tfd) & WDCS_ERR) { 2059 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2060 /* 2061 * Some ATAPI drives reject PIO settings. 2062 * Fall back to PIO mode 3 since that's the 2063 * minimum for ATAPI. 2064 */ 2065 aprint_error_dev(atac->atac_dev, 2066 "channel %d drive %d: PIO mode %d rejected," 2067 " falling back to PIO mode 3\n", 2068 chp->ch_channel, xfer->c_drive, 2069 drvp->PIO_mode); 2070 if (drvp->PIO_mode > 3) 2071 drvp->PIO_mode = 3; 2072 } else 2073 goto error; 2074 } 2075 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2076 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2077 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2078 else 2079 if (drvp->drive_flags & ATA_DRIVE_DMA) 2080 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2081 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2082 else 2083 goto ready; 2084 errstring = "dmamode-atapi"; 2085 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2086 &tfd)) 2087 goto timeout; 2088 if (ATACH_ST(tfd) & WDCS_ERR) { 2089 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2090 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2091 goto error; 2092 else { 2093 /* 2094 * The drive rejected our DMA setting. 2095 * Fall back to mode 1. 2096 */ 2097 aprint_error_dev(atac->atac_dev, 2098 "channel %d drive %d:" 2099 " DMA mode %d rejected," 2100 " falling back to DMA mode 0\n", 2101 chp->ch_channel, xfer->c_drive, 2102 drvp->DMA_mode); 2103 if (drvp->DMA_mode > 0) 2104 drvp->DMA_mode = 0; 2105 } 2106 } else 2107 goto error; 2108 } 2109 ready: 2110 drvp->state = READY; 2111 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2112 delay(10); /* some drives need a little delay here */ 2113 } 2114 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2115 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2116 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2117 ATACH_ST(tfd)); 2118 sc_xfer->error = XS_TIMEOUT; 2119 return ATASTART_ABORT; 2120 } 2121 2122 /* start timeout machinery */ 2123 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2124 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 2125 wdctimeout, chp); 2126 2127 /* 2128 * Even with WDCS_ERR, the device should accept a command packet 2129 * Limit length to what can be stuffed into the cylinder register 2130 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2131 * but not all devices do that and it's not obvious from the 2132 * ATAPI spec that that behaviour should be expected. If more 2133 * data is necessary, multiple data transfer phases will be done. 2134 */ 2135 2136 wdccommand(chp, 0, ATAPI_PKT_CMD, 2137 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2138 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2139 2140 /* 2141 * If there is no interrupt for CMD input, busy-wait for it (done in 2142 * the interrupt routine. Poll routine will exit early in this case. 2143 */ 2144 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2145 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2146 return ATASTART_POLL; 2147 else 2148 return ATASTART_STARTED; 2149 2150 timeout: 2151 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2152 chp->ch_channel, xfer->c_drive, errstring); 2153 sc_xfer->error = XS_TIMEOUT; 2154 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2155 delay(10); /* some drives need a little delay here */ 2156 return ATASTART_ABORT; 2157 2158 error: 2159 aprint_error_dev(atac->atac_dev, 2160 "channel %d drive %d: %s error (0x%x)\n", 2161 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2162 sc_xfer->error = XS_SHORTSENSE; 2163 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2164 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2165 delay(10); /* some drives need a little delay here */ 2166 return ATASTART_ABORT; 2167 } 2168 2169 static void 2170 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2171 { 2172 /* 2173 * If there is no interrupt for CMD input, busy-wait for it (done in 2174 * the interrupt routine. If it is a polled command, call the interrupt 2175 * routine until command is done. 2176 */ 2177 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2178 2179 /* Wait for at last 400ns for status bit to be valid */ 2180 DELAY(1); 2181 mvsata_atapi_intr(chp, xfer, 0); 2182 2183 if (!poll) 2184 return; 2185 2186 if (chp->ch_flags & ATACH_DMA_WAIT) { 2187 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2188 chp->ch_flags &= ~ATACH_DMA_WAIT; 2189 } 2190 2191 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2192 /* Wait for at last 400ns for status bit to be valid */ 2193 DELAY(1); 2194 mvsata_atapi_intr(chp, xfer, 0); 2195 } 2196 } 2197 2198 static int 2199 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2200 { 2201 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2202 struct atac_softc *atac = chp->ch_atac; 2203 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2204 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2205 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2206 int len, phase, ire, error, retries=0, i; 2207 int tfd; 2208 void *cmd; 2209 2210 ata_channel_lock(chp); 2211 2212 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2213 ("%s:%d:%d: mvsata_atapi_intr\n", 2214 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2215 2216 /* Is it not a transfer, but a control operation? */ 2217 if (drvp->state < READY) { 2218 aprint_error_dev(atac->atac_dev, 2219 "channel %d drive %d: bad state %d\n", 2220 chp->ch_channel, xfer->c_drive, drvp->state); 2221 panic("mvsata_atapi_intr: bad state"); 2222 } 2223 /* 2224 * If we missed an interrupt in a PIO transfer, reset and restart. 2225 * Don't try to continue transfer, we may have missed cycles. 2226 */ 2227 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2228 ata_channel_unlock(chp); 2229 sc_xfer->error = XS_TIMEOUT; 2230 mvsata_atapi_reset(chp, xfer); 2231 return 1; 2232 } 2233 2234 /* Ack interrupt done in wdc_wait_for_unbusy */ 2235 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2236 if (wdc_wait_for_unbusy(chp, 2237 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2238 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2239 ata_channel_unlock(chp); 2240 return 0; /* IRQ was not for us */ 2241 } 2242 aprint_error_dev(atac->atac_dev, 2243 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2244 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2245 if (xfer->c_flags & C_DMA) 2246 ata_dmaerr(drvp, 2247 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2248 sc_xfer->error = XS_TIMEOUT; 2249 ata_channel_unlock(chp); 2250 mvsata_atapi_reset(chp, xfer); 2251 return 1; 2252 } 2253 2254 /* 2255 * If we missed an IRQ and were using DMA, flag it as a DMA error 2256 * and reset device. 2257 */ 2258 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2259 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2260 sc_xfer->error = XS_RESET; 2261 ata_channel_unlock(chp); 2262 mvsata_atapi_reset(chp, xfer); 2263 return (1); 2264 } 2265 /* 2266 * if the request sense command was aborted, report the short sense 2267 * previously recorded, else continue normal processing 2268 */ 2269 2270 again: 2271 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2272 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2273 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2274 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2275 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2276 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2277 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2278 2279 switch (phase) { 2280 case PHASE_CMDOUT: 2281 cmd = sc_xfer->cmd; 2282 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2283 /* Init the DMA channel if necessary */ 2284 if (xfer->c_flags & C_DMA) { 2285 error = mvsata_bdma_init(mvport, xfer); 2286 if (error) { 2287 if (error == EINVAL) { 2288 /* 2289 * We can't do DMA on this transfer 2290 * for some reason. Fall back to PIO. 2291 */ 2292 xfer->c_flags &= ~C_DMA; 2293 error = 0; 2294 } else { 2295 sc_xfer->error = XS_DRIVER_STUFFUP; 2296 break; 2297 } 2298 } 2299 } 2300 2301 /* send packet command */ 2302 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2303 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2304 2305 /* Start the DMA channel if necessary */ 2306 if (xfer->c_flags & C_DMA) { 2307 mvsata_bdma_start(mvport); 2308 chp->ch_flags |= ATACH_DMA_WAIT; 2309 } 2310 ata_channel_unlock(chp); 2311 return 1; 2312 2313 case PHASE_DATAOUT: 2314 /* write data */ 2315 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2316 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2317 (xfer->c_flags & C_DMA) != 0) { 2318 aprint_error_dev(atac->atac_dev, 2319 "channel %d drive %d: bad data phase DATAOUT\n", 2320 chp->ch_channel, xfer->c_drive); 2321 if (xfer->c_flags & C_DMA) 2322 ata_dmaerr(drvp, 2323 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2324 sc_xfer->error = XS_TIMEOUT; 2325 ata_channel_unlock(chp); 2326 mvsata_atapi_reset(chp, xfer); 2327 return 1; 2328 } 2329 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2330 if (xfer->c_bcount < len) { 2331 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2332 " warning: write only %d of %d requested bytes\n", 2333 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2334 len); 2335 len = xfer->c_bcount; 2336 } 2337 2338 wdc->dataout_pio(chp, drvp->drive_flags, 2339 (char *)xfer->c_databuf + xfer->c_skip, len); 2340 2341 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 2342 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2343 2344 xfer->c_skip += len; 2345 xfer->c_bcount -= len; 2346 ata_channel_unlock(chp); 2347 return 1; 2348 2349 case PHASE_DATAIN: 2350 /* Read data */ 2351 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2352 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2353 (xfer->c_flags & C_DMA) != 0) { 2354 aprint_error_dev(atac->atac_dev, 2355 "channel %d drive %d: bad data phase DATAIN\n", 2356 chp->ch_channel, xfer->c_drive); 2357 if (xfer->c_flags & C_DMA) 2358 ata_dmaerr(drvp, 2359 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2360 ata_channel_unlock(chp); 2361 sc_xfer->error = XS_TIMEOUT; 2362 mvsata_atapi_reset(chp, xfer); 2363 return 1; 2364 } 2365 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2366 if (xfer->c_bcount < len) { 2367 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2368 " warning: reading only %d of %d bytes\n", 2369 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2370 len); 2371 len = xfer->c_bcount; 2372 } 2373 2374 wdc->datain_pio(chp, drvp->drive_flags, 2375 (char *)xfer->c_databuf + xfer->c_skip, len); 2376 2377 if (xfer->c_atapi.c_lenoff > 0) 2378 wdcbit_bucket(chp, len - xfer->c_bcount); 2379 2380 xfer->c_skip += len; 2381 xfer->c_bcount -= len; 2382 ata_channel_unlock(chp); 2383 return 1; 2384 2385 case PHASE_ABORTED: 2386 case PHASE_COMPLETED: 2387 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2388 if (xfer->c_flags & C_DMA) 2389 xfer->c_bcount -= sc_xfer->datalen; 2390 sc_xfer->resid = xfer->c_bcount; 2391 /* this will unlock channel lock too */ 2392 mvsata_atapi_phase_complete(xfer, tfd); 2393 return 1; 2394 2395 default: 2396 if (++retries<500) { 2397 DELAY(100); 2398 tfd = ATACH_ERR_ST( 2399 MVSATA_WDC_READ_1(mvport, SRB_FE), 2400 MVSATA_WDC_READ_1(mvport, SRB_CS) 2401 ); 2402 goto again; 2403 } 2404 aprint_error_dev(atac->atac_dev, 2405 "channel %d drive %d: unknown phase 0x%x\n", 2406 chp->ch_channel, xfer->c_drive, phase); 2407 if (ATACH_ST(tfd) & WDCS_ERR) { 2408 sc_xfer->error = XS_SHORTSENSE; 2409 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2410 } else { 2411 if (xfer->c_flags & C_DMA) 2412 ata_dmaerr(drvp, 2413 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2414 sc_xfer->error = XS_RESET; 2415 ata_channel_unlock(chp); 2416 mvsata_atapi_reset(chp, xfer); 2417 return (1); 2418 } 2419 } 2420 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2421 ("mvsata_atapi_intr: %s (end), error 0x%x " 2422 "sense 0x%x\n", __func__, 2423 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2424 ata_channel_unlock(chp); 2425 mvsata_atapi_done(chp, xfer); 2426 return 1; 2427 } 2428 2429 static void 2430 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2431 int reason) 2432 { 2433 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2434 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2435 bool deactivate = true; 2436 2437 /* remove this command from xfer queue */ 2438 switch (reason) { 2439 case KILL_GONE_INACTIVE: 2440 deactivate = false; 2441 /* FALLTHROUGH */ 2442 case KILL_GONE: 2443 sc_xfer->error = XS_DRIVER_STUFFUP; 2444 break; 2445 case KILL_RESET: 2446 sc_xfer->error = XS_RESET; 2447 break; 2448 case KILL_REQUEUE: 2449 sc_xfer->error = XS_REQUEUE; 2450 break; 2451 default: 2452 aprint_error_dev(MVSATA_DEV2(mvport), 2453 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2454 panic("mvsata_atapi_kill_xfer"); 2455 } 2456 2457 if (deactivate) 2458 ata_deactivate_xfer(chp, xfer); 2459 2460 ata_free_xfer(chp, xfer); 2461 scsipi_done(sc_xfer); 2462 } 2463 2464 static void 2465 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2466 { 2467 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2468 struct atac_softc *atac = chp->ch_atac; 2469 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2470 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2471 int tfd; 2472 2473 ata_channel_lock(chp); 2474 2475 mvsata_pmp_select(mvport, xfer->c_drive); 2476 2477 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2478 drvp->state = 0; 2479 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2480 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2481 chp->ch_channel, xfer->c_drive); 2482 sc_xfer->error = XS_SELTIMEOUT; 2483 } 2484 2485 ata_channel_unlock(chp); 2486 2487 mvsata_atapi_done(chp, xfer); 2488 return; 2489 } 2490 2491 static void 2492 mvsata_atapi_phase_complete(struct ata_xfer *xfer, int tfd) 2493 { 2494 struct ata_channel *chp = xfer->c_chp; 2495 struct atac_softc *atac = chp->ch_atac; 2496 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2497 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2498 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2499 2500 ata_channel_lock_owned(chp); 2501 2502 /* wait for DSC if needed */ 2503 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2504 DPRINTF(DEBUG_XFERS, 2505 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2506 device_xname(atac->atac_dev), chp->ch_channel, 2507 xfer->c_drive, xfer->c_atapi.c_dscpoll)); 2508 if (cold) 2509 panic("mvsata_atapi_phase_complete: cold"); 2510 2511 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2512 WDCWAIT_TOUT) { 2513 /* 10ms not enough, try again in 1 tick */ 2514 if (xfer->c_atapi.c_dscpoll++ > 2515 mstohz(sc_xfer->timeout)) { 2516 aprint_error_dev(atac->atac_dev, 2517 "channel %d: wait_for_dsc failed\n", 2518 chp->ch_channel); 2519 ata_channel_unlock(chp); 2520 sc_xfer->error = XS_TIMEOUT; 2521 mvsata_atapi_reset(chp, xfer); 2522 } else { 2523 callout_reset(&chp->c_timo_callout, 1, 2524 mvsata_atapi_polldsc, chp); 2525 ata_channel_unlock(chp); 2526 } 2527 return; 2528 } 2529 } 2530 2531 /* 2532 * Some drive occasionally set WDCS_ERR with 2533 * "ATA illegal length indication" in the error 2534 * register. If we read some data the sense is valid 2535 * anyway, so don't report the error. 2536 */ 2537 if (ATACH_ST(tfd) & WDCS_ERR && 2538 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2539 sc_xfer->resid == sc_xfer->datalen)) { 2540 /* save the short sense */ 2541 sc_xfer->error = XS_SHORTSENSE; 2542 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2543 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2544 /* ask scsipi to send a REQUEST_SENSE */ 2545 sc_xfer->error = XS_BUSY; 2546 sc_xfer->status = SCSI_CHECK; 2547 } else 2548 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2549 ata_dmaerr(drvp, 2550 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2551 sc_xfer->error = XS_RESET; 2552 ata_channel_unlock(chp); 2553 mvsata_atapi_reset(chp, xfer); 2554 return; 2555 } 2556 } 2557 if (xfer->c_bcount != 0) { 2558 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2559 " bcount value is %d after io\n", 2560 device_xname(atac->atac_dev), chp->ch_channel, 2561 xfer->c_drive, xfer->c_bcount)); 2562 } 2563 #ifdef DIAGNOSTIC 2564 if (xfer->c_bcount < 0) { 2565 aprint_error_dev(atac->atac_dev, 2566 "channel %d drive %d: mvsata_atapi_intr:" 2567 " warning: bcount value is %d after io\n", 2568 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2569 } 2570 #endif 2571 2572 DPRINTF(DEBUG_XFERS, 2573 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2574 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2575 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2576 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2577 ata_channel_unlock(chp); 2578 mvsata_atapi_done(chp, xfer); 2579 } 2580 2581 static void 2582 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2583 { 2584 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2585 bool iserror = (sc_xfer->error != XS_NOERROR); 2586 2587 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2588 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2589 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2590 xfer->c_drive, (u_int)xfer->c_flags)); 2591 2592 if (ata_waitdrain_xfer_check(chp, xfer)) 2593 return; 2594 2595 /* mark controller inactive and free the command */ 2596 ata_deactivate_xfer(chp, xfer); 2597 2598 ata_free_xfer(chp, xfer); 2599 2600 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2601 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2602 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2603 scsipi_done(sc_xfer); 2604 DPRINTF(DEBUG_FUNCS, 2605 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2606 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2607 chp->ch_flags)); 2608 if (!iserror) 2609 atastart(chp); 2610 } 2611 2612 static void 2613 mvsata_atapi_polldsc(void *arg) 2614 { 2615 struct ata_channel *chp = arg; 2616 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 2617 2618 KASSERT(xfer != NULL); 2619 2620 ata_channel_lock(chp); 2621 2622 /* this will unlock channel lock too */ 2623 mvsata_atapi_phase_complete(xfer, 0); 2624 } 2625 #endif /* NATAPIBUS > 0 */ 2626 2627 2628 /* 2629 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2630 * if supported queuing command by atabus? The race condition will not happen 2631 * if this is called only to the thread of atabus. 2632 */ 2633 static int 2634 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2635 { 2636 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2637 struct ata_bio *ata_bio = &xfer->c_bio; 2638 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2639 struct eprd *eprd; 2640 bus_addr_t crqb_base_addr; 2641 bus_dmamap_t data_dmamap; 2642 uint32_t reg; 2643 int erqqip, erqqop, next, rv, i; 2644 2645 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2646 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2647 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2648 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2649 2650 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2651 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2652 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2653 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2654 next = erqqip; 2655 MVSATA_EDMAQ_INC(next); 2656 if (next == erqqop) { 2657 /* queue full */ 2658 return EBUSY; 2659 } 2660 DPRINTF(DEBUG_XFERS, 2661 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2662 2663 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2664 ata_bio->flags); 2665 if (rv != 0) 2666 return rv; 2667 2668 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2669 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2670 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2671 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2672 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2673 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2674 2675 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2676 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2677 eprd->eot = htole16(0); 2678 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2679 eprd++; 2680 } 2681 (eprd - 1)->eot |= htole16(EPRD_EOT); 2682 #ifdef MVSATA_DEBUG 2683 if (mvsata_debug >= 3) 2684 mvsata_print_eprd(mvport, xfer->c_slot); 2685 #endif 2686 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2687 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2688 BUS_DMASYNC_PREWRITE); 2689 2690 /* setup EDMA Command Request Block (CRQB) Data */ 2691 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2692 #ifdef MVSATA_DEBUG 2693 if (mvsata_debug >= 3) 2694 mvsata_print_crqb(mvport, erqqip); 2695 #endif 2696 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2697 erqqip * sizeof(union mvsata_crqb), 2698 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2699 2700 MVSATA_EDMAQ_INC(erqqip); 2701 2702 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2703 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2704 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2705 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2706 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2707 2708 return 0; 2709 } 2710 2711 static int 2712 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2713 { 2714 struct ata_channel *chp = &mvport->port_ata_channel; 2715 struct crpb *crpb; 2716 struct ata_bio *ata_bio; 2717 struct ata_xfer *xfer; 2718 uint32_t reg; 2719 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2720 int st, dmaerr; 2721 2722 /* First, Sync for Request Queue buffer */ 2723 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2724 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2725 if (mvport->port_prev_erqqop != erqqop) { 2726 const int s = sizeof(union mvsata_crqb); 2727 2728 if (mvport->port_prev_erqqop < erqqop) 2729 n = erqqop - mvport->port_prev_erqqop; 2730 else { 2731 if (erqqop > 0) 2732 bus_dmamap_sync(mvport->port_dmat, 2733 mvport->port_crqb_dmamap, 0, erqqop * s, 2734 BUS_DMASYNC_POSTWRITE); 2735 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2736 } 2737 if (n > 0) 2738 bus_dmamap_sync(mvport->port_dmat, 2739 mvport->port_crqb_dmamap, 2740 mvport->port_prev_erqqop * s, n * s, 2741 BUS_DMASYNC_POSTWRITE); 2742 mvport->port_prev_erqqop = erqqop; 2743 } 2744 2745 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2746 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2747 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2748 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2749 2750 DPRINTF(DEBUG_XFERS, 2751 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2752 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2753 mvport->port, erpqip, erpqop)); 2754 2755 if (erpqop == erpqip) 2756 return 0; 2757 2758 if (erpqop < erpqip) 2759 n = erpqip - erpqop; 2760 else { 2761 if (erpqip > 0) 2762 bus_dmamap_sync(mvport->port_dmat, 2763 mvport->port_crpb_dmamap, 2764 0, erpqip * sizeof(struct crpb), 2765 BUS_DMASYNC_POSTREAD); 2766 n = MVSATA_EDMAQ_LEN - erpqop; 2767 } 2768 if (n > 0) 2769 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2770 erpqop * sizeof(struct crpb), 2771 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2772 2773 uint32_t aslots = ata_queue_active(chp); 2774 2775 prev_erpqop = erpqop; 2776 while (erpqop != erpqip) { 2777 #ifdef MVSATA_DEBUG 2778 if (mvsata_debug >= 3) 2779 mvsata_print_crpb(mvport, erpqop); 2780 #endif 2781 crpb = mvport->port_crpb + erpqop; 2782 MVSATA_EDMAQ_INC(erpqop); 2783 2784 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2785 2786 if ((aslots & __BIT(quetag)) == 0) { 2787 /* not actually executing */ 2788 continue; 2789 } 2790 2791 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2792 2793 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2794 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2795 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2796 2797 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2798 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2799 2800 ata_bio = &xfer->c_bio; 2801 ata_bio->error = NOERROR; 2802 if (dmaerr != 0) 2803 ata_bio->error = ERR_DMA; 2804 2805 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2806 2807 KASSERT(xfer->c_flags & C_DMA); 2808 mvsata_bio_intr(chp, xfer, ATACH_ERR_ST(0, st)); 2809 2810 if (xfer1 == NULL) 2811 handled++; 2812 else if (xfer == xfer1) { 2813 handled = 1; 2814 break; 2815 } 2816 } 2817 if (prev_erpqop < erpqop) 2818 n = erpqop - prev_erpqop; 2819 else { 2820 if (erpqop > 0) 2821 bus_dmamap_sync(mvport->port_dmat, 2822 mvport->port_crpb_dmamap, 0, 2823 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2824 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2825 } 2826 if (n > 0) 2827 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2828 prev_erpqop * sizeof(struct crpb), 2829 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2830 2831 reg &= ~EDMA_RESQP_ERPQP_MASK; 2832 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2833 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2834 2835 return handled; 2836 } 2837 2838 static int 2839 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2840 { 2841 int xtime; 2842 2843 for (xtime = 0; xtime < timeout * 10; xtime++) { 2844 if (mvsata_edma_handle(mvport, xfer)) 2845 return 0; 2846 DELAY(100); 2847 } 2848 2849 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2850 mvsata_edma_rqq_remove(mvport, xfer); 2851 xfer->c_flags |= C_TIMEOU; 2852 return 1; 2853 } 2854 2855 static void 2856 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2857 { 2858 struct ata_channel *chp = &mvport->port_ata_channel; 2859 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2860 bus_addr_t crqb_base_addr; 2861 int erqqip, i; 2862 2863 /* First, hardware reset, stop EDMA */ 2864 mvsata_hreset_port(mvport); 2865 2866 /* cleanup completed EDMA safely */ 2867 mvsata_edma_handle(mvport, NULL); 2868 2869 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2870 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2871 2872 uint32_t aslots = ata_queue_active(chp); 2873 2874 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2875 struct ata_xfer *rqxfer; 2876 2877 if ((aslots & __BIT(i)) == 0) 2878 continue; 2879 2880 if (i == xfer->c_slot) { 2881 /* remove xfer from EDMA request queue */ 2882 bus_dmamap_sync(mvport->port_dmat, 2883 mvport->port_eprd_dmamap, 2884 mvport->port_reqtbl[i].eprd_offset, 2885 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2886 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 2887 /* quetag freed by caller later */ 2888 continue; 2889 } 2890 2891 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 2892 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 2893 erqqip++; 2894 } 2895 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2896 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2897 BUS_DMASYNC_POSTWRITE); 2898 2899 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 2900 mvsata_edma_reset_qptr(mvport); 2901 mvsata_edma_enable(mvport); 2902 2903 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2904 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2905 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2906 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2907 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2908 } 2909 2910 #if NATAPIBUS > 0 2911 static int 2912 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 2913 { 2914 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2915 struct eprd *eprd; 2916 bus_dmamap_t data_dmamap; 2917 bus_addr_t eprd_addr; 2918 int i, rv; 2919 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2920 2921 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2922 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2923 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2924 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2925 2926 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 2927 sc_xfer->datalen, 2928 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2929 if (rv != 0) 2930 return rv; 2931 2932 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2933 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2934 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2935 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2936 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2937 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2938 2939 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2940 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2941 eprd->eot = htole16(0); 2942 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2943 eprd++; 2944 } 2945 (eprd - 1)->eot |= htole16(EPRD_EOT); 2946 #ifdef MVSATA_DEBUG 2947 if (mvsata_debug >= 3) 2948 mvsata_print_eprd(mvport, xfer->c_slot); 2949 #endif 2950 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2951 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2952 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 2953 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2954 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 2955 2956 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2957 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2958 2959 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2960 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2961 else 2962 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2963 2964 return 0; 2965 } 2966 2967 static void 2968 mvsata_bdma_start(struct mvsata_port *mvport) 2969 { 2970 2971 #ifdef MVSATA_DEBUG 2972 if (mvsata_debug >= 3) 2973 mvsata_print_eprd(mvport, 0); 2974 #endif 2975 2976 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2977 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2978 } 2979 #endif 2980 #endif 2981 2982 2983 static int 2984 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2985 { 2986 struct mvsata_softc *sc = mvhc->hc_sc; 2987 struct mvsata_port *mvport; 2988 struct ata_channel *chp; 2989 int channel, rv, i; 2990 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2991 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2992 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2993 2994 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2995 M_ZERO | M_WAITOK); 2996 mvport->port = port; 2997 mvport->port_hc = mvhc; 2998 mvport->port_edmamode_negotiated = nodma; 2999 3000 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3001 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3002 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3003 if (rv != 0) { 3004 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3005 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3006 goto fail0; 3007 } 3008 mvport->port_iot = mvhc->hc_iot; 3009 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3010 &mvport->port_sata_sstatus); 3011 if (rv != 0) { 3012 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3013 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3014 goto fail0; 3015 } 3016 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3017 &mvport->port_sata_serror); 3018 if (rv != 0) { 3019 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3020 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3021 goto fail0; 3022 } 3023 if (sc->sc_rev == gen1) 3024 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3025 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3026 else 3027 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3028 SATA_SC, 4, &mvport->port_sata_scontrol); 3029 if (rv != 0) { 3030 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3031 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3032 goto fail0; 3033 } 3034 mvport->port_dmat = sc->sc_dmat; 3035 mvhc->hc_ports[port] = mvport; 3036 3037 channel = mvhc->hc * sc->sc_port + port; 3038 chp = &mvport->port_ata_channel; 3039 chp->ch_channel = channel; 3040 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3041 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3042 sc->sc_ata_channels[channel] = chp; 3043 3044 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3045 if (rv != 0) 3046 goto fail0; 3047 3048 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3049 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3050 if (rv != 0) { 3051 aprint_error( 3052 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3053 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3054 goto fail0; 3055 } 3056 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3057 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3058 if (rv != 0) { 3059 aprint_error( 3060 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3061 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3062 goto fail1; 3063 } 3064 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3065 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3066 if (rv != 0) { 3067 aprint_error( 3068 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3069 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3070 goto fail2; 3071 } 3072 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3073 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3074 MVSATA_MAX_SEGS, MAXPHYS, 0, BUS_DMA_NOWAIT, 3075 &mvport->port_reqtbl[i].data_dmamap); 3076 if (rv != 0) { 3077 aprint_error("%s:%d:%d:" 3078 " EDMA data map(%d) create failed: error=%d\n", 3079 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3080 rv); 3081 goto fail3; 3082 } 3083 } 3084 3085 return 0; 3086 3087 fail3: 3088 for (i--; i >= 0; i--) 3089 bus_dmamap_destroy(mvport->port_dmat, 3090 mvport->port_reqtbl[i].data_dmamap); 3091 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3092 fail2: 3093 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3094 fail1: 3095 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3096 fail0: 3097 return rv; 3098 } 3099 3100 static int 3101 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3102 { 3103 int hc, port, rv, i; 3104 3105 hc = mvport->port_hc->hc; 3106 port = mvport->port; 3107 3108 /* Create subregion for Shadow Registers Map */ 3109 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3110 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3111 if (rv != 0) { 3112 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3113 device_xname(MVSATA_DEV2(mvport)), hc, port); 3114 return rv; 3115 } 3116 wdr->cmd_iot = mvport->port_iot; 3117 3118 /* Once create subregion for each command registers */ 3119 for (i = 0; i < WDC_NREG; i++) { 3120 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3121 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3122 if (rv != 0) { 3123 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3124 device_xname(MVSATA_DEV2(mvport)), hc, port); 3125 return rv; 3126 } 3127 } 3128 /* Create subregion for Alternate Status register */ 3129 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3130 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3131 if (rv != 0) { 3132 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3133 device_xname(MVSATA_DEV2(mvport)), hc, port); 3134 return rv; 3135 } 3136 wdr->ctl_iot = mvport->port_iot; 3137 3138 wdc_init_shadow_regs(wdr); 3139 3140 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3141 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3142 if (rv != 0) { 3143 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3144 device_xname(MVSATA_DEV2(mvport)), hc, port); 3145 return rv; 3146 } 3147 wdr->sata_iot = mvport->port_iot; 3148 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3149 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3150 if (rv != 0) { 3151 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3152 device_xname(MVSATA_DEV2(mvport)), hc, port); 3153 return rv; 3154 } 3155 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3156 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3157 if (rv != 0) { 3158 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3159 device_xname(MVSATA_DEV2(mvport)), hc, port); 3160 return rv; 3161 } 3162 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3163 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3164 if (rv != 0) { 3165 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3166 device_xname(MVSATA_DEV2(mvport)), hc, port); 3167 return rv; 3168 } 3169 3170 return 0; 3171 } 3172 3173 3174 #ifndef MVSATA_WITHOUTDMA 3175 static void * 3176 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3177 bus_dmamap_t *dmamap, size_t size, int write) 3178 { 3179 bus_dma_segment_t seg; 3180 int nseg, rv; 3181 void *kva; 3182 3183 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3184 BUS_DMA_NOWAIT); 3185 if (rv != 0) { 3186 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3187 device_xname(MVSATA_DEV2(mvport)), 3188 mvport->port_hc->hc, mvport->port, rv); 3189 goto fail; 3190 } 3191 3192 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3193 if (rv != 0) { 3194 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3195 device_xname(MVSATA_DEV2(mvport)), 3196 mvport->port_hc->hc, mvport->port, rv); 3197 goto free; 3198 } 3199 3200 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3201 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3202 if (rv != 0) { 3203 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3204 device_xname(MVSATA_DEV2(mvport)), 3205 mvport->port_hc->hc, mvport->port, rv); 3206 goto unmap; 3207 } 3208 3209 if (!write) 3210 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3211 3212 return kva; 3213 3214 unmap: 3215 bus_dmamem_unmap(dmat, kva, size); 3216 free: 3217 bus_dmamem_free(dmat, &seg, nseg); 3218 fail: 3219 return NULL; 3220 } 3221 3222 /* ARGSUSED */ 3223 static void 3224 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3225 bus_dmamap_t dmamap, void *kva) 3226 { 3227 3228 bus_dmamap_unload(dmat, dmamap); 3229 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3230 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3231 } 3232 3233 static int 3234 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3235 size_t datalen, int flags) 3236 { 3237 int rv, lop, sop; 3238 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3239 3240 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3241 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3242 3243 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3244 NULL, BUS_DMA_NOWAIT | lop); 3245 if (rv) { 3246 aprint_error("%s:%d:%d: buffer load failed: error=%d\n", 3247 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3248 mvport->port, rv); 3249 return rv; 3250 } 3251 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3252 data_dmamap->dm_mapsize, sop); 3253 3254 return 0; 3255 } 3256 3257 static inline void 3258 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3259 { 3260 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3261 3262 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3263 data_dmamap->dm_mapsize, 3264 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3265 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3266 } 3267 #endif 3268 3269 static void 3270 mvsata_hreset_port(struct mvsata_port *mvport) 3271 { 3272 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3273 3274 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3275 3276 delay(25); /* allow reset propagation */ 3277 3278 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3279 3280 mvport->_fix_phy_param._fix_phy(mvport); 3281 3282 if (sc->sc_gen == gen1) 3283 delay(1000); 3284 } 3285 3286 static void 3287 mvsata_reset_port(struct mvsata_port *mvport) 3288 { 3289 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3290 3291 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3292 3293 mvsata_hreset_port(mvport); 3294 3295 if (device_is_a(parent, "pci")) 3296 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3297 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3298 else /* SoC */ 3299 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3300 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3301 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3302 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3303 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3304 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3305 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3306 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3307 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3308 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3309 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3310 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3311 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3312 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3313 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3314 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3315 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3316 } 3317 3318 static void 3319 mvsata_reset_hc(struct mvsata_hc *mvhc) 3320 { 3321 #if 0 3322 uint32_t val; 3323 #endif 3324 3325 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3326 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3327 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3328 3329 #if 0 /* XXXX needs? */ 3330 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3331 3332 /* 3333 * Keep the SS during power on and the reference clock bits (reset 3334 * sample) 3335 */ 3336 val = MVSATA_HC_READ_4(mvhc, 0x020); 3337 val &= 0x1c1c1c1c; 3338 val |= 0x03030303; 3339 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3340 #endif 3341 } 3342 3343 static uint32_t 3344 mvsata_softreset(struct mvsata_port *mvport, int flags) 3345 { 3346 struct ata_channel *chp = &mvport->port_ata_channel; 3347 uint32_t sig0 = ~0; 3348 int timeout; 3349 uint8_t st0; 3350 3351 ata_channel_lock_owned(chp); 3352 3353 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3354 delay(10); 3355 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3356 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3357 delay(10); 3358 3359 /* wait for BSY to deassert */ 3360 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3361 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3362 3363 if ((st0 & WDCS_BSY) == 0) { 3364 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3365 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3366 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3367 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3368 goto out; 3369 } 3370 ata_delay(chp, 10, "atarst", flags); 3371 } 3372 3373 aprint_error("%s:%d:%d: %s: timeout\n", 3374 device_xname(MVSATA_DEV2(mvport)), 3375 mvport->port_hc->hc, mvport->port, __func__); 3376 3377 out: 3378 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3379 return sig0; 3380 } 3381 3382 #ifndef MVSATA_WITHOUTDMA 3383 static void 3384 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3385 { 3386 const bus_addr_t crpb_addr = 3387 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3388 const uint32_t crpb_addr_mask = 3389 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3390 3391 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3392 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3393 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3394 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3395 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3396 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3397 } 3398 3399 static inline void 3400 mvsata_edma_enable(struct mvsata_port *mvport) 3401 { 3402 3403 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3404 } 3405 3406 static void 3407 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3408 { 3409 struct ata_channel *chp = &mvport->port_ata_channel; 3410 uint32_t command; 3411 int t; 3412 3413 ata_channel_lock_owned(chp); 3414 3415 /* The disable bit (eDsEDMA) is self negated. */ 3416 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3417 3418 timeout = mstohz(timeout + hztoms(1) - 1); 3419 3420 for (t = 0; ; ++t) { 3421 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3422 if (!(command & EDMA_CMD_EENEDMA)) 3423 return; 3424 if (t >= timeout) 3425 break; 3426 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3427 } 3428 3429 aprint_error("%s:%d:%d: unable to disable EDMA\n", 3430 device_xname(MVSATA_DEV2(mvport)), 3431 mvport->port_hc->hc, mvport->port); 3432 } 3433 3434 /* 3435 * Set EDMA registers according to mode. 3436 * ex. NCQ/TCQ(queued)/non queued. 3437 */ 3438 static void 3439 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3440 { 3441 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3442 uint32_t reg; 3443 3444 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3445 reg |= EDMA_CFG_RESERVED; 3446 3447 if (mode == ncq) { 3448 if (sc->sc_gen == gen1) { 3449 aprint_error_dev(MVSATA_DEV2(mvport), 3450 "GenI not support NCQ\n"); 3451 return; 3452 } else if (sc->sc_gen == gen2) 3453 reg |= EDMA_CFG_EDEVERR; 3454 reg |= EDMA_CFG_ESATANATVCMDQUE; 3455 } else if (mode == queued) { 3456 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3457 reg |= EDMA_CFG_EQUE; 3458 } else 3459 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3460 3461 if (sc->sc_gen == gen1) 3462 reg |= EDMA_CFG_ERDBSZ; 3463 else if (sc->sc_gen == gen2) 3464 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3465 else if (sc->sc_gen == gen2e) { 3466 device_t parent = device_parent(MVSATA_DEV(sc)); 3467 3468 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3469 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3470 3471 if (device_is_a(parent, "pci")) 3472 reg |= ( 3473 #if NATAPIBUS > 0 3474 EDMA_CFG_EEARLYCOMPLETIONEN | 3475 #endif 3476 EDMA_CFG_ECUTTHROUGHEN | 3477 EDMA_CFG_EWRBUFFERLEN | 3478 EDMA_CFG_ERDBSZEXT); 3479 } 3480 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3481 3482 reg = ( 3483 EDMA_IE_EIORDYERR | 3484 EDMA_IE_ETRANSINT | 3485 EDMA_IE_EDEVCON | 3486 EDMA_IE_EDEVDIS); 3487 if (sc->sc_gen != gen1) 3488 reg |= ( 3489 EDMA_IE_TRANSPROTERR | 3490 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3491 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3492 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3493 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3494 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3495 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3496 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3497 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3498 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3499 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3500 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3501 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3502 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3503 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3504 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3505 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3506 EDMA_IE_ESELFDIS); 3507 3508 if (mode == ncq) 3509 reg |= EDMA_IE_EDEVERR; 3510 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3511 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3512 reg &= ~EDMA_IE_EDEVERR; 3513 if (mode != ncq) 3514 reg |= EDMA_IE_EDEVERR; 3515 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3516 if (sc->sc_gen == gen2e) { 3517 /* 3518 * Clear FISWait4HostRdyEn[0] and [2]. 3519 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3520 * [2]: SDB FIS is received with <ERR> bit set to 1. 3521 */ 3522 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3523 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3524 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3525 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3526 } 3527 3528 mvport->port_edmamode_curr = mode; 3529 } 3530 3531 3532 /* 3533 * Generation dependent functions 3534 */ 3535 3536 static void 3537 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3538 struct ata_xfer *xfer) 3539 { 3540 struct crqb *crqb; 3541 bus_addr_t eprd_addr; 3542 daddr_t blkno; 3543 uint32_t rw; 3544 uint8_t cmd, head; 3545 int i; 3546 struct ata_bio *ata_bio = &xfer->c_bio; 3547 3548 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3549 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3550 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3551 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3552 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3553 head = WDSD_LBA; 3554 } else { 3555 head = 0; 3556 } 3557 blkno = ata_bio->blkno; 3558 if (ata_bio->flags & ATA_LBA48) 3559 cmd = atacmd_to48(cmd); 3560 else { 3561 head |= ((ata_bio->blkno >> 24) & 0xf); 3562 blkno &= 0xffffff; 3563 } 3564 crqb = &mvport->port_crqb->crqb + erqqip; 3565 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3566 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3567 crqb->ctrlflg = 3568 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3569 CRQB_CPMPORT(xfer->c_drive)); 3570 i = 0; 3571 if (mvport->port_edmamode_curr == dma) { 3572 if (ata_bio->flags & ATA_LBA48) 3573 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3574 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3575 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3576 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3577 } else { /* ncq/queued */ 3578 3579 /* 3580 * XXXX: Oops, ata command is not correct. And, atabus layer 3581 * has not been supported yet now. 3582 * Queued DMA read/write. 3583 * read/write FPDMAQueued. 3584 */ 3585 3586 if (ata_bio->flags & ATA_LBA48) 3587 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3588 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3589 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3590 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3591 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3592 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3593 } 3594 if (ata_bio->flags & ATA_LBA48) { 3595 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3596 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3597 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3598 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3599 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3600 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3601 } 3602 crqb->atacommand[i++] = 3603 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3604 crqb->atacommand[i++] = 3605 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3606 crqb->atacommand[i++] = 3607 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3608 crqb->atacommand[i++] = 3609 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3610 crqb->atacommand[i++] = htole16( 3611 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3612 CRQB_ATACOMMAND_LAST); 3613 } 3614 #endif 3615 3616 static uint32_t 3617 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3618 { 3619 struct mvsata_hc *hc = mvport->port_hc; 3620 uint32_t reg; 3621 3622 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3623 /* 3624 * [12:11] : pre 3625 * [7:5] : amps 3626 */ 3627 return reg & 0x000018e0; 3628 } 3629 3630 static void 3631 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3632 { 3633 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3634 struct mvsata_hc *mvhc = mvport->port_hc; 3635 uint32_t reg; 3636 int port = mvport->port, fix_apm_sq = 0; 3637 3638 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3639 if (sc->sc_rev == 0x01) 3640 fix_apm_sq = 1; 3641 } else { 3642 if (sc->sc_rev == 0x00) 3643 fix_apm_sq = 1; 3644 } 3645 3646 if (fix_apm_sq) { 3647 /* 3648 * Disable auto-power management 3649 * 88SX50xx FEr SATA#12 3650 */ 3651 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3652 reg |= (1 << 19); 3653 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3654 3655 /* 3656 * Fix squelch threshold 3657 * 88SX50xx FEr SATA#9 3658 */ 3659 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3660 reg &= ~0x3; 3661 reg |= 0x1; 3662 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3663 } 3664 3665 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3666 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3667 reg &= ~0x000018e0; /* pre and amps mask */ 3668 reg |= mvport->_fix_phy_param.pre_amps; 3669 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3670 } 3671 3672 static void 3673 mvsata_devconn_gen1(struct mvsata_port *mvport) 3674 { 3675 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3676 3677 /* Fix for 88SX50xx FEr SATA#2 */ 3678 mvport->_fix_phy_param._fix_phy(mvport); 3679 3680 /* If disk is connected, then enable the activity LED */ 3681 if (sc->sc_rev == 0x03) { 3682 /* XXXXX */ 3683 } 3684 } 3685 3686 static uint32_t 3687 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3688 { 3689 uint32_t reg; 3690 3691 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3692 /* 3693 * [10:8] : amps 3694 * [7:5] : pre 3695 */ 3696 return reg & 0x000007e0; 3697 } 3698 3699 static void 3700 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3701 { 3702 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3703 uint32_t reg; 3704 3705 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3706 sc->sc_gen == gen2e) { 3707 /* 3708 * Fix for 3709 * 88SX60X1 FEr SATA #23 3710 * 88SX6042/88SX7042 FEr SATA #23 3711 * 88F5182 FEr #SATA-S13 3712 * 88F5082 FEr #SATA-S13 3713 */ 3714 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3715 reg &= ~(1 << 16); 3716 reg |= (1 << 31); 3717 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3718 3719 delay(200); 3720 3721 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3722 reg &= ~((1 << 16) | (1 << 31)); 3723 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3724 3725 delay(200); 3726 } 3727 3728 /* Fix values in PHY Mode 3 Register.*/ 3729 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3730 reg &= ~0x7F900000; 3731 reg |= 0x2A800000; 3732 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3733 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3734 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3735 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3736 reg &= ~0x0000001c; 3737 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3738 3739 /* 3740 * Fix values in PHY Mode 4 Register. 3741 * 88SX60x1 FEr SATA#10 3742 * 88F5182 GL #SATA-S10 3743 * 88F5082 GL #SATA-S10 3744 */ 3745 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3746 sc->sc_gen == gen2e) { 3747 uint32_t tmp = 0; 3748 3749 /* 88SX60x1 FEr SATA #13 */ 3750 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3751 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3752 3753 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3754 reg |= (1 << 0); 3755 reg &= ~(1 << 1); 3756 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3757 if (sc->sc_gen == gen2e) { 3758 reg &= ~0x5de3fffc; 3759 reg |= (1 << 2); 3760 } 3761 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3762 3763 /* 88SX60x1 FEr SATA #13 */ 3764 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3765 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3766 } 3767 3768 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3769 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3770 reg &= ~0x000007e0; /* pre and amps mask */ 3771 reg |= mvport->_fix_phy_param.pre_amps; 3772 reg &= ~(1 << 16); 3773 if (sc->sc_gen == gen2e) { 3774 /* 3775 * according to mvSata 3.6.1, some IIE values are fixed. 3776 * some reserved fields must be written with fixed values. 3777 */ 3778 reg &= ~0xC30FF01F; 3779 reg |= 0x0000900F; 3780 } 3781 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3782 } 3783 3784 #ifndef MVSATA_WITHOUTDMA 3785 static void 3786 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3787 struct ata_xfer *xfer) 3788 { 3789 struct crqb_gen2e *crqb; 3790 bus_addr_t eprd_addr; 3791 uint32_t ctrlflg, rw; 3792 uint8_t fis[RHD_FISLEN]; 3793 3794 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3795 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3796 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3797 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3798 CRQB_CPMPORT(xfer->c_drive) | 3799 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3800 3801 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3802 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3803 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3804 crqb->ctrlflg = htole32(ctrlflg); 3805 3806 satafis_rhd_construct_bio(xfer, fis); 3807 3808 crqb->atacommand[0] = 0; 3809 crqb->atacommand[1] = 0; 3810 /* copy over the ATA command part of the fis */ 3811 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3812 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3813 } 3814 3815 #ifdef MVSATA_DEBUG 3816 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3817 do { \ 3818 int _i; \ 3819 u_char *_p = (p); \ 3820 \ 3821 printf(#type "(%d)", (n)); \ 3822 for (_i = 0; _i < (size); _i++, _p++) { \ 3823 if (_i % 16 == 0) \ 3824 printf("\n "); \ 3825 printf(" %02x", *_p); \ 3826 } \ 3827 printf("\n"); \ 3828 } while (0 /* CONSTCOND */) 3829 3830 static void 3831 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3832 { 3833 3834 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3835 n, (u_char *)(mvport->port_crqb + n)); 3836 } 3837 3838 static void 3839 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3840 { 3841 3842 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3843 n, (u_char *)(mvport->port_crpb + n)); 3844 } 3845 3846 static void 3847 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3848 { 3849 struct eprd *eprd; 3850 int i = 0; 3851 3852 eprd = mvport->port_reqtbl[n].eprd; 3853 while (1 /*CONSTCOND*/) { 3854 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3855 i, (u_char *)eprd); 3856 if (eprd->eot & EPRD_EOT) 3857 break; 3858 eprd++; 3859 i++; 3860 } 3861 } 3862 #endif 3863 #endif 3864
Indexes created Fri Sep 26 08:10:20 GMT 2025