mvsata.c revision 1.60
1 /* $NetBSD: mvsata.c,v 1.60 2021/08/07 16:19:12 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.60 2021/08/07 16:19:12 thorpej Exp $"); 30 31 #include "opt_mvsata.h" 32 33 #include <sys/param.h> 34 #include <sys/buf.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/disklabel.h> 39 #include <sys/errno.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 44 #include <machine/vmparam.h> 45 46 #include <dev/ata/atareg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 #include <dev/ata/satafisvar.h> 50 #include <dev/ata/satafisreg.h> 51 #include <dev/ata/satapmpreg.h> 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 55 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 56 57 #include "atapibus.h" 58 59 #include <dev/pci/pcidevs.h> /* XXX should not be here */ 60 61 /* 62 * Nice things to do: 63 * 64 * - MSI/MSI-X support - though on some models MSI actually doesn't work 65 * even when hardware claims to support it, according to FreeBSD/OpenBSD 66 * - move pci-specific code to the pci attach code 67 * - mvsata(4) use 64-bit DMA on hardware which claims to support it 68 * - e.g. AHA1430SA does not really work, crash in mvsata_intr() on boot 69 */ 70 71 #include <dev/ic/mvsatareg.h> 72 #include <dev/ic/mvsatavar.h> 73 74 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 75 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 76 77 #define MVSATA_HC_READ_4(hc, reg) \ 78 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 79 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 80 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 81 #define MVSATA_EDMA_READ_4(mvport, reg) \ 82 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 83 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 84 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 85 #define MVSATA_WDC_READ_2(mvport, reg) \ 86 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, \ 87 SHADOW_REG_BLOCK_OFFSET + (reg)) 88 #define MVSATA_WDC_READ_1(mvport, reg) \ 89 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, \ 90 SHADOW_REG_BLOCK_OFFSET + (reg)) 91 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 92 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, \ 93 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 94 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 95 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, \ 96 SHADOW_REG_BLOCK_OFFSET + (reg), (val)) 97 98 #ifdef MVSATA_DEBUG 99 100 #define DEBUG_INTR 0x01 101 #define DEBUG_XFERS 0x02 102 #define DEBUG_FUNCS 0x08 103 #define DEBUG_PROBE 0x10 104 105 #define DPRINTF(n,x) if (mvsata_debug & (n)) printf x 106 int mvsata_debug = 0; 107 #else 108 #define DPRINTF(n,x) 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 113 sending a cmd */ 114 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 115 116 #define MVSATA_MAX_SEGS (MAXPHYS / PAGE_SIZE + 1) 117 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * MVSATA_MAX_SEGS) 118 119 120 static void mvsata_probe_drive(struct ata_channel *); 121 122 #ifndef MVSATA_WITHOUTDMA 123 static void mvsata_reset_channel(struct ata_channel *, int); 124 static void mvsata_bio(struct ata_drive_datas *, struct ata_xfer *); 125 static void mvsata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 126 static void mvsata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 127 static int mvsata_addref(struct ata_drive_datas *); 128 static void mvsata_delref(struct ata_drive_datas *); 129 static void mvsata_killpending(struct ata_drive_datas *); 130 131 #if NATAPIBUS > 0 132 static void mvsata_atapibus_attach(struct atabus_softc *); 133 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 134 scsipi_adapter_req_t, void *); 135 static void mvsata_atapi_minphys(struct buf *); 136 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 137 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 138 #endif 139 #endif 140 141 static void mvsata_setup_channel(struct ata_channel *); 142 143 #ifndef MVSATA_WITHOUTDMA 144 static int mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 145 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 146 static void mvsata_bio_poll(struct ata_channel *, struct ata_xfer *); 147 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 148 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 149 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 150 int); 151 static int mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 152 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 153 static void mvsata_wdc_cmd_poll(struct ata_channel *, struct ata_xfer *); 154 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 155 int); 156 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 157 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 158 #if NATAPIBUS > 0 159 static int mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 160 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 161 static void mvsata_atapi_poll(struct ata_channel *, struct ata_xfer *); 162 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 163 int); 164 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 165 static void mvsata_atapi_phase_complete(struct ata_xfer *, int); 166 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 167 static void mvsata_atapi_polldsc(void *); 168 #endif 169 170 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_xfer *); 171 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 172 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 173 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 174 #if NATAPIBUS > 0 175 static int mvsata_bdma_init(struct mvsata_port *, struct ata_xfer *); 176 static void mvsata_bdma_start(struct mvsata_port *); 177 #endif 178 #endif 179 180 static int mvsata_nondma_handle(struct mvsata_port *); 181 182 static int mvsata_port_init(struct mvsata_hc *, int); 183 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 184 #ifndef MVSATA_WITHOUTDMA 185 static void mvsata_channel_recover(struct ata_channel *, int, uint32_t); 186 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 187 bus_dmamap_t *, size_t, int); 188 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 189 bus_dmamap_t, void *); 190 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 191 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 192 #endif 193 194 static void mvsata_hreset_port(struct mvsata_port *); 195 static void mvsata_reset_port(struct mvsata_port *); 196 static void mvsata_reset_hc(struct mvsata_hc *); 197 static uint32_t mvsata_softreset(struct mvsata_port *, int); 198 #ifndef MVSATA_WITHOUTDMA 199 static void mvsata_edma_reset_qptr(struct mvsata_port *); 200 static inline void mvsata_edma_enable(struct mvsata_port *); 201 static void mvsata_edma_disable(struct mvsata_port *, int, int); 202 static void mvsata_edma_config(struct mvsata_port *, enum mvsata_edmamode); 203 204 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, 205 struct ata_xfer *); 206 #endif 207 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 208 static void mvsata_fix_phy_gen1(struct mvsata_port *); 209 static void mvsata_devconn_gen1(struct mvsata_port *); 210 211 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 212 static void mvsata_fix_phy_gen2(struct mvsata_port *); 213 #ifndef MVSATA_WITHOUTDMA 214 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, 215 struct ata_xfer *); 216 217 #ifdef MVSATA_DEBUG 218 static void mvsata_print_crqb(struct mvsata_port *, int); 219 static void mvsata_print_crpb(struct mvsata_port *, int); 220 static void mvsata_print_eprd(struct mvsata_port *, int); 221 #endif 222 223 static const struct ata_bustype mvsata_ata_bustype = { 224 .bustype_type = SCSIPI_BUSTYPE_ATA, 225 .ata_bio = mvsata_bio, 226 .ata_reset_drive = mvsata_reset_drive, 227 .ata_reset_channel = mvsata_reset_channel, 228 .ata_exec_command = mvsata_exec_command, 229 .ata_get_params = ata_get_params, 230 .ata_addref = mvsata_addref, 231 .ata_delref = mvsata_delref, 232 .ata_killpending = mvsata_killpending, 233 .ata_recovery = mvsata_channel_recover, 234 }; 235 236 #if NATAPIBUS > 0 237 static const struct scsipi_bustype mvsata_atapi_bustype = { 238 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 239 .bustype_cmd = atapi_scsipi_cmd, 240 .bustype_interpret_sense = atapi_interpret_sense, 241 .bustype_printaddr = atapi_print_addr, 242 .bustype_kill_pending = mvsata_atapi_kill_pending, 243 .bustype_async_event_xfer_mode = NULL, 244 }; 245 #endif /* NATAPIBUS */ 246 #endif 247 248 static void 249 mvsata_pmp_select(struct mvsata_port *mvport, int pmpport) 250 { 251 uint32_t ifctl; 252 253 KASSERT(pmpport < PMP_MAX_DRIVES); 254 #if defined(DIAGNOSTIC) || defined(MVSATA_DEBUG) 255 if ((MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) != 0) { 256 panic("EDMA enabled"); 257 } 258 #endif 259 260 ifctl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL); 261 ifctl &= ~0xf; 262 ifctl |= pmpport; 263 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICTL, ifctl); 264 } 265 266 int 267 mvsata_attach(struct mvsata_softc *sc, const struct mvsata_product *product, 268 int (*mvsata_sreset)(struct mvsata_softc *), 269 int (*mvsata_misc_reset)(struct mvsata_softc *), 270 int read_pre_amps) 271 { 272 struct mvsata_hc *mvhc; 273 struct mvsata_port *mvport; 274 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 275 void (*_fix_phy)(struct mvsata_port *) = NULL; 276 #ifndef MVSATA_WITHOUTDMA 277 void (*edma_setup_crqb) 278 (struct mvsata_port *, int, struct ata_xfer *) = NULL; 279 #endif 280 int hc, port, channel; 281 282 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 283 (product->generation == gen1) ? "I" : 284 ((product->generation == gen2) ? "II" : "IIe"), 285 product->hc, product->port); 286 287 288 switch (product->generation) { 289 case gen1: 290 mvsata_sreset = NULL; 291 read_pre_amps = 1; /* MUST */ 292 read_preamps = mvsata_read_preamps_gen1; 293 _fix_phy = mvsata_fix_phy_gen1; 294 #ifndef MVSATA_WITHOUTDMA 295 edma_setup_crqb = mvsata_edma_setup_crqb; 296 #endif 297 break; 298 299 case gen2: 300 read_preamps = mvsata_read_preamps_gen2; 301 _fix_phy = mvsata_fix_phy_gen2; 302 #ifndef MVSATA_WITHOUTDMA 303 edma_setup_crqb = mvsata_edma_setup_crqb; 304 #endif 305 break; 306 307 case gen2e: 308 read_preamps = mvsata_read_preamps_gen2; 309 _fix_phy = mvsata_fix_phy_gen2; 310 #ifndef MVSATA_WITHOUTDMA 311 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 312 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NCQ; 313 #endif 314 break; 315 } 316 317 sc->sc_gen = product->generation; 318 sc->sc_hc = product->hc; 319 sc->sc_port = product->port; 320 sc->sc_flags = product->flags; 321 322 #ifdef MVSATA_WITHOUTDMA 323 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 324 #else 325 sc->sc_edma_setup_crqb = edma_setup_crqb; 326 sc->sc_wdcdev.sc_atac.atac_cap |= 327 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 328 #endif 329 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 330 #ifdef MVSATA_WITHOUTDMA 331 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 333 #else 334 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 335 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 336 #endif 337 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 338 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 339 #ifndef MVSATA_WITHOUTDMA 340 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 341 #if NATAPIBUS > 0 342 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 343 #endif 344 #endif 345 sc->sc_wdcdev.wdc_maxdrives = 1; /* SATA is always 1 drive */ 346 sc->sc_wdcdev.sc_atac.atac_probe = mvsata_probe_drive; 347 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 348 349 sc->sc_wdc_regs = 350 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 351 M_DEVBUF, M_WAITOK); 352 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 353 354 for (hc = 0; hc < sc->sc_hc; hc++) { 355 mvhc = &sc->sc_hcs[hc]; 356 mvhc->hc = hc; 357 mvhc->hc_sc = sc; 358 mvhc->hc_iot = sc->sc_iot; 359 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 360 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 361 &mvhc->hc_ioh)) { 362 aprint_error_dev(MVSATA_DEV(sc), 363 "can't subregion SATAHC %d registers\n", hc); 364 continue; 365 } 366 367 for (port = 0; port < sc->sc_port; port++) 368 if (mvsata_port_init(mvhc, port) == 0) { 369 int pre_amps; 370 371 mvport = mvhc->hc_ports[port]; 372 pre_amps = read_pre_amps ? 373 read_preamps(mvport) : 0x00000720; 374 mvport->_fix_phy_param.pre_amps = pre_amps; 375 mvport->_fix_phy_param._fix_phy = _fix_phy; 376 377 if (!mvsata_sreset) 378 mvsata_reset_port(mvport); 379 } 380 381 if (!mvsata_sreset) 382 mvsata_reset_hc(mvhc); 383 } 384 if (mvsata_sreset) 385 mvsata_sreset(sc); 386 387 if (mvsata_misc_reset) 388 mvsata_misc_reset(sc); 389 390 for (hc = 0; hc < sc->sc_hc; hc++) 391 for (port = 0; port < sc->sc_port; port++) { 392 mvport = sc->sc_hcs[hc].hc_ports[port]; 393 if (mvport == NULL) 394 continue; 395 if (mvsata_sreset) 396 mvport->_fix_phy_param._fix_phy(mvport); 397 } 398 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 399 wdcattach(sc->sc_ata_channels[channel]); 400 401 return 0; 402 } 403 404 int 405 mvsata_intr(struct mvsata_hc *mvhc) 406 { 407 struct mvsata_softc *sc = mvhc->hc_sc; 408 struct mvsata_port *mvport; 409 uint32_t cause; 410 int port, handled = 0; 411 412 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 413 414 DPRINTF(DEBUG_INTR, ("%s:%d: mvsata_intr: cause=0x%08x\n", 415 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 416 417 if (cause & SATAHC_IC_SAINTCOAL) 418 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 419 cause &= ~SATAHC_IC_SAINTCOAL; 420 421 for (port = 0; port < sc->sc_port; port++) { 422 mvport = mvhc->hc_ports[port]; 423 424 if (cause & SATAHC_IC_DONE(port)) { 425 #ifndef MVSATA_WITHOUTDMA 426 handled = mvsata_edma_handle(mvport, NULL); 427 #endif 428 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 429 ~SATAHC_IC_DONE(port)); 430 } 431 432 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 433 (void) mvsata_nondma_handle(mvport); 434 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 435 ~SATAHC_IC_SADEVINTERRUPT(port)); 436 handled = 1; 437 } 438 } 439 440 return handled; 441 } 442 443 static int 444 mvsata_nondma_handle(struct mvsata_port *mvport) 445 { 446 struct ata_channel *chp = &mvport->port_ata_channel; 447 struct ata_xfer *xfer; 448 int ret; 449 450 /* 451 * The chip doesn't support several pending non-DMA commands, 452 * and the ata middle layer never issues several non-NCQ commands, 453 * so there must be exactly one active command at this moment. 454 */ 455 xfer = ata_queue_get_active_xfer(chp); 456 if (xfer == NULL) { 457 /* Can happen after error recovery, ignore */ 458 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 459 ("%s:%d: %s: intr without xfer\n", 460 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 461 __func__)); 462 return 0; 463 } 464 465 ret = xfer->ops->c_intr(chp, xfer, 1); 466 return (ret); 467 } 468 469 int 470 mvsata_error(struct mvsata_port *mvport) 471 { 472 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 473 uint32_t cause; 474 475 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 476 /* 477 * We must ack SATA_SE and SATA_FISIC before acking coresponding bits 478 * in EDMA_IEC. 479 */ 480 if (cause & EDMA_IE_SERRINT) { 481 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, 482 MVSATA_EDMA_READ_4(mvport, SATA_SEIM)); 483 } 484 if (cause & EDMA_IE_ETRANSINT) { 485 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 486 ~MVSATA_EDMA_READ_4(mvport, SATA_FISIM)); 487 } 488 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 489 490 DPRINTF(DEBUG_INTR, ("%s:%d:%d:" 491 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 492 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 493 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 494 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 495 496 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 497 if (!cause) 498 return 0; 499 500 if (cause & EDMA_IE_EDEVDIS) { 501 aprint_normal("%s:%d:%d: device disconnect\n", 502 device_xname(MVSATA_DEV2(mvport)), 503 mvport->port_hc->hc, mvport->port); 504 } 505 if (cause & EDMA_IE_EDEVCON) { 506 if (sc->sc_gen == gen1) 507 mvsata_devconn_gen1(mvport); 508 509 DPRINTF(DEBUG_INTR, (" device connected\n")); 510 } 511 512 #ifndef MVSATA_WITHOUTDMA 513 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 514 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 515 switch (mvport->port_edmamode_curr) { 516 case dma: 517 case queued: 518 case ncq: 519 mvsata_edma_reset_qptr(mvport); 520 mvsata_edma_enable(mvport); 521 if (cause & EDMA_IE_EDEVERR) 522 break; 523 524 /* FALLTHROUGH */ 525 526 case nodma: 527 default: 528 DPRINTF(DEBUG_INTR, 529 ("%s:%d:%d: EDMA self disable happen 0x%x\n", 530 device_xname(MVSATA_DEV2(mvport)), 531 mvport->port_hc->hc, mvport->port, cause)); 532 break; 533 } 534 } 535 #endif 536 if (cause & EDMA_IE_ETRANSINT) { 537 /* hot plug the Port Multiplier */ 538 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 539 device_xname(MVSATA_DEV2(mvport)), 540 mvport->port_hc->hc, mvport->port); 541 } 542 if (cause & EDMA_IE_EDEVERR) { 543 struct ata_channel *chp = &mvport->port_ata_channel; 544 545 aprint_error("%s:%d:%d: device error, recovering\n", 546 device_xname(MVSATA_DEV2(mvport)), 547 mvport->port_hc->hc, mvport->port); 548 549 ata_channel_lock(chp); 550 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, 551 ATACH_ERR_ST(0, WDCS_ERR)); 552 ata_channel_unlock(chp); 553 } 554 555 return 1; 556 } 557 558 #ifndef MVSATA_WITHOUTDMA 559 static void 560 mvsata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 561 { 562 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 563 int drive; 564 565 ata_channel_lock_owned(chp); 566 567 if (chp->ch_ndrives > PMP_PORT_CTL) { 568 /* Get PM port number for the device in error. This device 569 * doesn't seem to have dedicated register for this, so just 570 * assume last selected port was the one. */ 571 /* XXX FIS-based switching */ 572 drive = MVSATA_EDMA_READ_4(mvport, SATA_SATAICTL) & 0xf; 573 } else 574 drive = 0; 575 576 /* 577 * Controller doesn't need any special action. Simply execute 578 * READ LOG EXT for NCQ to unblock device processing, then continue 579 * as if nothing happened. 580 */ 581 582 ata_recovery_resume(chp, drive, tfd, AT_POLL); 583 584 /* Drive unblocked, back to normal operation */ 585 return; 586 } 587 #endif /* !MVSATA_WITHOUTDMA */ 588 589 /* 590 * ATA callback entry points 591 */ 592 593 static void 594 mvsata_probe_drive(struct ata_channel *chp) 595 { 596 struct mvsata_port * const mvport = (struct mvsata_port *)chp; 597 uint32_t sstat, sig; 598 599 ata_channel_lock(chp); 600 601 sstat = sata_reset_interface(chp, mvport->port_iot, 602 mvport->port_sata_scontrol, mvport->port_sata_sstatus, AT_WAIT); 603 switch (sstat) { 604 case SStatus_DET_DEV: 605 mvsata_pmp_select(mvport, PMP_PORT_CTL); 606 sig = mvsata_softreset(mvport, AT_WAIT); 607 sata_interpret_sig(chp, 0, sig); 608 break; 609 default: 610 break; 611 } 612 613 ata_channel_unlock(chp); 614 } 615 616 #ifndef MVSATA_WITHOUTDMA 617 static void 618 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 619 { 620 struct ata_channel *chp = drvp->chnl_softc; 621 struct mvsata_port *mvport = (struct mvsata_port *)chp; 622 uint32_t edma_c; 623 uint32_t sig; 624 625 ata_channel_lock_owned(chp); 626 627 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 628 629 DPRINTF(DEBUG_FUNCS, 630 ("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 631 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 632 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 633 634 if (edma_c & EDMA_CMD_EENEDMA) 635 mvsata_edma_disable(mvport, 10000, flags); 636 637 mvsata_pmp_select(mvport, drvp->drive); 638 639 sig = mvsata_softreset(mvport, flags); 640 641 if (sigp) 642 *sigp = sig; 643 644 if (edma_c & EDMA_CMD_EENEDMA) { 645 mvsata_edma_reset_qptr(mvport); 646 mvsata_edma_enable(mvport); 647 } 648 } 649 650 static void 651 mvsata_reset_channel(struct ata_channel *chp, int flags) 652 { 653 struct mvsata_port *mvport = (struct mvsata_port *)chp; 654 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 655 uint32_t sstat, ctrl; 656 657 DPRINTF(DEBUG_FUNCS, ("%s: mvsata_reset_channel: channel=%d\n", 658 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 659 660 ata_channel_lock_owned(chp); 661 662 mvsata_hreset_port(mvport); 663 sstat = sata_reset_interface(chp, mvport->port_iot, 664 mvport->port_sata_scontrol, mvport->port_sata_sstatus, flags); 665 666 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 667 sc->sc_gen != gen1) { 668 /* Downgrade to GenI */ 669 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 670 SControl_DET_DISABLE; 671 672 bus_space_write_4(mvport->port_iot, 673 mvport->port_sata_scontrol, 0, val); 674 675 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 676 ctrl &= ~(1 << 17); /* Disable GenII */ 677 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 678 679 mvsata_hreset_port(mvport); 680 sata_reset_interface(chp, mvport->port_iot, 681 mvport->port_sata_scontrol, mvport->port_sata_sstatus, 682 flags); 683 } 684 685 ata_kill_active(chp, KILL_RESET, flags); 686 687 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 688 mvsata_edma_reset_qptr(mvport); 689 mvsata_edma_enable(mvport); 690 } 691 692 static int 693 mvsata_addref(struct ata_drive_datas *drvp) 694 { 695 696 return 0; 697 } 698 699 static void 700 mvsata_delref(struct ata_drive_datas *drvp) 701 { 702 703 return; 704 } 705 706 static void 707 mvsata_killpending(struct ata_drive_datas *drvp) 708 { 709 710 return; 711 } 712 713 #if NATAPIBUS > 0 714 static void 715 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 716 { 717 struct ata_channel *chp = ata_sc->sc_chan; 718 struct atac_softc *atac = chp->ch_atac; 719 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 720 struct scsipi_channel *chan = &chp->ch_atapi_channel; 721 722 /* 723 * Fill in the scsipi_adapter. 724 */ 725 adapt->adapt_dev = atac->atac_dev; 726 adapt->adapt_nchannels = atac->atac_nchannels; 727 adapt->adapt_request = mvsata_atapi_scsipi_request; 728 adapt->adapt_minphys = mvsata_atapi_minphys; 729 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 730 731 /* 732 * Fill in the scsipi_channel. 733 */ 734 memset(chan, 0, sizeof(*chan)); 735 chan->chan_adapter = adapt; 736 chan->chan_bustype = &mvsata_atapi_bustype; 737 chan->chan_channel = chp->ch_channel; 738 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 739 chan->chan_openings = 1; 740 chan->chan_max_periph = 1; 741 chan->chan_ntargets = 1; 742 chan->chan_nluns = 1; 743 744 chp->atapibus = config_found(ata_sc->sc_dev, chan, atapiprint, 745 CFARGS(.iattr = "atapi")); 746 } 747 748 static void 749 mvsata_atapi_minphys(struct buf *bp) 750 { 751 752 if (bp->b_bcount > MAXPHYS) 753 bp->b_bcount = MAXPHYS; 754 minphys(bp); 755 } 756 757 static void 758 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 759 { 760 struct scsipi_channel *chan = sc->sc_channel; 761 struct scsipi_periph *periph; 762 struct ataparams ids; 763 struct ataparams *id = &ids; 764 struct mvsata_softc *mvc = 765 device_private(chan->chan_adapter->adapt_dev); 766 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 767 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 768 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 769 struct scsipibus_attach_args sa; 770 char serial_number[21], model[41], firmware_revision[9]; 771 int s; 772 773 /* skip if already attached */ 774 if (scsipi_lookup_periph(chan, target, 0) != NULL) 775 return; 776 777 /* if no ATAPI device detected at attach time, skip */ 778 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 779 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 780 " drive %d not present\n", 781 device_xname(atac->atac_dev), chp->ch_channel, target)); 782 return; 783 } 784 785 /* Some ATAPI devices need a bit more time after software reset. */ 786 delay(5000); 787 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 788 #ifdef ATAPI_DEBUG_PROBE 789 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 790 device_xname(sc->sc_dev), target, 791 id->atap_config & ATAPI_CFG_CMD_MASK, 792 id->atap_config & ATAPI_CFG_DRQ_MASK); 793 #endif 794 periph = scsipi_alloc_periph(M_WAITOK); 795 periph->periph_dev = NULL; 796 periph->periph_channel = chan; 797 periph->periph_switch = &atapi_probe_periphsw; 798 periph->periph_target = target; 799 periph->periph_lun = 0; 800 periph->periph_quirks = PQUIRK_ONLYBIG; 801 802 #ifdef SCSIPI_DEBUG 803 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 804 SCSIPI_DEBUG_TARGET == target) 805 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 806 #endif 807 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 808 if (id->atap_config & ATAPI_CFG_REMOV) 809 periph->periph_flags |= PERIPH_REMOVABLE; 810 if (periph->periph_type == T_SEQUENTIAL) { 811 s = splbio(); 812 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 813 splx(s); 814 } 815 816 sa.sa_periph = periph; 817 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 818 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 819 T_REMOV : T_FIXED; 820 strnvisx(model, sizeof(model), id->atap_model, 40, 821 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 822 strnvisx(serial_number, sizeof(serial_number), id->atap_serial, 823 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 824 strnvisx(firmware_revision, sizeof(firmware_revision), 825 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 826 sa.sa_inqbuf.vendor = model; 827 sa.sa_inqbuf.product = serial_number; 828 sa.sa_inqbuf.revision = firmware_revision; 829 830 /* 831 * Determine the operating mode capabilities of the device. 832 */ 833 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 834 periph->periph_cap |= PERIPH_CAP_CMD16; 835 /* XXX This is gross. */ 836 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 837 838 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 839 840 if (drvp->drv_softc) 841 ata_probe_caps(drvp); 842 else { 843 s = splbio(); 844 drvp->drive_type = ATA_DRIVET_NONE; 845 splx(s); 846 } 847 } else { 848 DPRINTF(DEBUG_PROBE, ("%s:%d: mvsata_atapi_probe_device:" 849 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error\n", 850 device_xname(atac->atac_dev), chp->ch_channel, target)); 851 s = splbio(); 852 drvp->drive_type = ATA_DRIVET_NONE; 853 splx(s); 854 } 855 } 856 857 /* 858 * Kill off all pending xfers for a periph. 859 * 860 * Must be called at splbio(). 861 */ 862 static void 863 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 864 { 865 struct atac_softc *atac = 866 device_private(periph->periph_channel->chan_adapter->adapt_dev); 867 struct ata_channel *chp = 868 atac->atac_channels[periph->periph_channel->chan_channel]; 869 870 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 871 } 872 #endif /* NATAPIBUS > 0 */ 873 #endif /* MVSATA_WITHOUTDMA */ 874 875 876 /* 877 * mvsata_setup_channel() 878 * Setup EDMA registers and prepare/purge DMA resources. 879 * We assuming already stopped the EDMA. 880 */ 881 static void 882 mvsata_setup_channel(struct ata_channel *chp) 883 { 884 #ifndef MVSATA_WITHOUTDMA 885 struct mvsata_port *mvport = (struct mvsata_port *)chp; 886 struct ata_drive_datas *drvp; 887 int drive, s; 888 uint32_t edma_mode = nodma; 889 int i; 890 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 891 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 892 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 893 894 DPRINTF(DEBUG_FUNCS, ("%s:%d: mvsata_setup_channel: ", 895 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 896 897 for (drive = 0; drive < chp->ch_ndrives; drive++) { 898 drvp = &chp->ch_drive[drive]; 899 900 /* If no drive, skip */ 901 if (drvp->drive_type == ATA_DRIVET_NONE) 902 continue; 903 904 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 905 /* use Ultra/DMA */ 906 s = splbio(); 907 drvp->drive_flags &= ~ATA_DRIVE_DMA; 908 splx(s); 909 } 910 911 if (drvp->drive_flags & (ATA_DRIVE_UDMA | ATA_DRIVE_DMA)) { 912 if (drvp->drive_flags & ATA_DRIVE_NCQ) 913 edma_mode = ncq; 914 else if (drvp->drive_type == ATA_DRIVET_ATA) 915 edma_mode = dma; 916 } 917 } 918 919 DPRINTF(DEBUG_FUNCS, 920 ("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 921 922 if (edma_mode == nodma) { 923 no_edma: 924 if (mvport->port_crqb != NULL) 925 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 926 mvport->port_crqb_dmamap, mvport->port_crqb); 927 if (mvport->port_crpb != NULL) 928 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 929 mvport->port_crpb_dmamap, mvport->port_crpb); 930 if (mvport->port_eprd != NULL) 931 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 932 mvport->port_eprd_dmamap, mvport->port_eprd); 933 934 return; 935 } 936 937 if (mvport->port_crqb == NULL) 938 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 939 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 940 if (mvport->port_crpb == NULL) 941 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 942 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 943 if (mvport->port_eprd == NULL) { 944 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 945 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 946 1); 947 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 948 mvport->port_reqtbl[i].eprd_offset = 949 i * MVSATA_EPRD_MAX_SIZE; 950 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 951 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 952 } 953 } 954 955 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 956 mvport->port_eprd == NULL) { 957 aprint_error_dev(MVSATA_DEV2(mvport), 958 "channel %d: can't use EDMA\n", chp->ch_channel); 959 s = splbio(); 960 for (drive = 0; drive < chp->ch_ndrives; drive++) { 961 drvp = &chp->ch_drive[drive]; 962 963 /* If no drive, skip */ 964 if (drvp->drive_type == ATA_DRIVET_NONE) 965 continue; 966 967 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 968 } 969 splx(s); 970 goto no_edma; 971 } 972 973 mvsata_edma_config(mvport, edma_mode); 974 mvsata_edma_reset_qptr(mvport); 975 mvsata_edma_enable(mvport); 976 #endif 977 } 978 979 #ifndef MVSATA_WITHOUTDMA 980 static const struct ata_xfer_ops mvsata_bio_xfer_ops = { 981 .c_start = mvsata_bio_start, 982 .c_intr = mvsata_bio_intr, 983 .c_poll = mvsata_bio_poll, 984 .c_abort = mvsata_bio_done, 985 .c_kill_xfer = mvsata_bio_kill_xfer, 986 }; 987 988 static void 989 mvsata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 990 { 991 struct ata_channel *chp = drvp->chnl_softc; 992 struct atac_softc *atac = chp->ch_atac; 993 struct ata_bio *ata_bio = &xfer->c_bio; 994 995 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 996 ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 997 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 998 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 999 1000 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1001 ata_bio->flags |= ATA_POLL; 1002 if (ata_bio->flags & ATA_POLL) 1003 xfer->c_flags |= C_POLL; 1004 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 1005 (ata_bio->flags & ATA_SINGLE) == 0) 1006 xfer->c_flags |= C_DMA; 1007 xfer->c_drive = drvp->drive; 1008 xfer->c_databuf = ata_bio->databuf; 1009 xfer->c_bcount = ata_bio->bcount; 1010 xfer->ops = &mvsata_bio_xfer_ops; 1011 ata_exec_xfer(chp, xfer); 1012 } 1013 1014 static int 1015 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1016 { 1017 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1018 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1019 struct atac_softc *atac = chp->ch_atac; 1020 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1021 struct ata_bio *ata_bio = &xfer->c_bio; 1022 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1023 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1024 u_int16_t cyl; 1025 u_int8_t head, sect, cmd = 0; 1026 int nblks, error, tfd; 1027 1028 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: mvsata_bio_start: drive=%d\n", 1029 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1030 1031 ata_channel_lock_owned(chp); 1032 1033 if (xfer->c_flags & C_DMA) 1034 if (drvp->n_xfers <= NXFER) 1035 drvp->n_xfers++; 1036 1037 /* 1038 * 1039 * When starting a multi-sector transfer, or doing single-sector 1040 * transfers... 1041 */ 1042 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1043 if (ata_bio->flags & ATA_SINGLE) 1044 nblks = 1; 1045 else 1046 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1047 /* Check for bad sectors and adjust transfer, if necessary. */ 1048 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 1049 long blkdiff; 1050 int i; 1051 1052 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 1053 i++) { 1054 blkdiff -= ata_bio->blkno; 1055 if (blkdiff < 0) 1056 continue; 1057 if (blkdiff == 0) 1058 /* Replace current block of transfer. */ 1059 ata_bio->blkno = 1060 drvp->lp->d_secperunit - 1061 drvp->lp->d_nsectors - i - 1; 1062 if (blkdiff < nblks) { 1063 /* Bad block inside transfer. */ 1064 ata_bio->flags |= ATA_SINGLE; 1065 nblks = 1; 1066 } 1067 break; 1068 } 1069 /* Transfer is okay now. */ 1070 } 1071 if (xfer->c_flags & C_DMA) { 1072 enum mvsata_edmamode dmamode; 1073 1074 ata_bio->nblks = nblks; 1075 ata_bio->nbytes = xfer->c_bcount; 1076 1077 /* switch to appropriate dma mode if necessary */ 1078 dmamode = (xfer->c_flags & C_NCQ) ? ncq : dma; 1079 if (mvport->port_edmamode_curr != dmamode) 1080 mvsata_edma_config(mvport, dmamode); 1081 1082 if (xfer->c_flags & C_POLL) 1083 sc->sc_enable_intr(mvport, 0 /*off*/); 1084 error = mvsata_edma_enqueue(mvport, xfer); 1085 if (error) { 1086 if (error == EINVAL) { 1087 /* 1088 * We can't do DMA on this transfer 1089 * for some reason. Fall back to 1090 * PIO. 1091 */ 1092 xfer->c_flags &= ~C_DMA; 1093 error = 0; 1094 goto do_pio; 1095 } 1096 if (error == EBUSY) { 1097 aprint_error_dev(atac->atac_dev, 1098 "channel %d: EDMA Queue full\n", 1099 chp->ch_channel); 1100 /* 1101 * XXX: Perhaps, after it waits for 1102 * a while, it is necessary to call 1103 * bio_start again. 1104 */ 1105 } 1106 ata_bio->error = ERR_DMA; 1107 ata_bio->r_error = 0; 1108 return ATASTART_ABORT; 1109 } 1110 chp->ch_flags |= ATACH_DMA_WAIT; 1111 /* wait for irq */ 1112 goto intr; 1113 } /* else not DMA */ 1114 do_pio: 1115 if (ata_bio->flags & ATA_LBA48) { 1116 sect = 0; 1117 cyl = 0; 1118 head = 0; 1119 } else if (ata_bio->flags & ATA_LBA) { 1120 sect = (ata_bio->blkno >> 0) & 0xff; 1121 cyl = (ata_bio->blkno >> 8) & 0xffff; 1122 head = (ata_bio->blkno >> 24) & 0x0f; 1123 head |= WDSD_LBA; 1124 } else { 1125 int blkno = ata_bio->blkno; 1126 sect = blkno % drvp->lp->d_nsectors; 1127 sect++; /* Sectors begin with 1, not 0. */ 1128 blkno /= drvp->lp->d_nsectors; 1129 head = blkno % drvp->lp->d_ntracks; 1130 blkno /= drvp->lp->d_ntracks; 1131 cyl = blkno; 1132 head |= WDSD_CHS; 1133 } 1134 ata_bio->nblks = uimin(nblks, drvp->multi); 1135 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 1136 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1137 if (ata_bio->nblks > 1) 1138 cmd = (ata_bio->flags & ATA_READ) ? 1139 WDCC_READMULTI : WDCC_WRITEMULTI; 1140 else 1141 cmd = (ata_bio->flags & ATA_READ) ? 1142 WDCC_READ : WDCC_WRITE; 1143 1144 /* EDMA disable, if enabled this channel. */ 1145 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1146 if (mvport->port_edmamode_curr != nodma) 1147 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1148 1149 mvsata_pmp_select(mvport, xfer->c_drive); 1150 1151 /* Do control operations specially. */ 1152 if (__predict_false(drvp->state < READY)) { 1153 /* 1154 * Actually, we want to be careful not to mess with 1155 * the control state if the device is currently busy, 1156 * but we can assume that we never get to this point 1157 * if that's the case. 1158 */ 1159 /* 1160 * If it's not a polled command, we need the kernel 1161 * thread 1162 */ 1163 if ((xfer->c_flags & C_POLL) == 0 1164 && !ata_is_thread_run(chp)) 1165 return ATASTART_TH; 1166 1167 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1168 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1169 return ATASTART_ABORT; 1170 } 1171 } 1172 1173 /* Initiate command! */ 1174 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1175 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 1176 case WDCWAIT_OK: 1177 break; 1178 case WDCWAIT_TOUT: 1179 goto timeout; 1180 case WDCWAIT_THR: 1181 return ATASTART_TH; 1182 } 1183 if (ata_bio->flags & ATA_LBA48) 1184 wdccommandext(chp, 0, atacmd_to48(cmd), 1185 ata_bio->blkno, nblks, 0, WDSD_LBA); 1186 else 1187 wdccommand(chp, 0, cmd, cyl, 1188 head, sect, nblks, 1189 (drvp->lp->d_type == DKTYPE_ST506) ? 1190 drvp->lp->d_precompcyl / 4 : 0); 1191 } else if (ata_bio->nblks > 1) { 1192 /* The number of blocks in the last stretch may be smaller. */ 1193 nblks = xfer->c_bcount / drvp->lp->d_secsize; 1194 if (ata_bio->nblks > nblks) { 1195 ata_bio->nblks = nblks; 1196 ata_bio->nbytes = xfer->c_bcount; 1197 } 1198 } 1199 /* If this was a write and not using DMA, push the data. */ 1200 if ((ata_bio->flags & ATA_READ) == 0) { 1201 /* 1202 * we have to busy-wait here, we can't rely on running in 1203 * thread context. 1204 */ 1205 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 1206 aprint_error_dev(atac->atac_dev, 1207 "channel %d: drive %d timeout waiting for DRQ," 1208 " st=0x%02x, err=0x%02x\n", 1209 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), 1210 ATACH_ERR(tfd)); 1211 ata_bio->error = TIMEOUT; 1212 return ATASTART_ABORT; 1213 } 1214 if (ATACH_ST(tfd) & WDCS_ERR) { 1215 ata_bio->error = ERROR; 1216 ata_bio->r_error = ATACH_ERR(tfd); 1217 mvsata_bio_done(chp, xfer); 1218 return ATASTART_ABORT; 1219 } 1220 1221 wdc->dataout_pio(chp, drvp->drive_flags, 1222 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1223 } 1224 1225 intr: 1226 KASSERTMSG(((xfer->c_flags & C_DMA) != 0) 1227 == (mvport->port_edmamode_curr != nodma), 1228 "DMA mode mismatch: flags %x vs edmamode %d != %d", 1229 xfer->c_flags, mvport->port_edmamode_curr, nodma); 1230 1231 /* Wait for IRQ (either real or polled) */ 1232 if ((ata_bio->flags & ATA_POLL) != 0) { 1233 /* start timeout machinery */ 1234 callout_reset(&chp->c_timo_callout, 1235 mstohz(ATA_DELAY), wdctimeout, chp); 1236 return ATASTART_POLL; 1237 } else 1238 return ATASTART_STARTED; 1239 1240 timeout: 1241 aprint_error_dev(atac->atac_dev, 1242 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1243 chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd)); 1244 ata_bio->error = TIMEOUT; 1245 return ATASTART_ABORT; 1246 } 1247 1248 static void 1249 mvsata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1250 { 1251 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1252 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1253 1254 /* Wait for at last 400ns for status bit to be valid */ 1255 delay(1); 1256 if (chp->ch_flags & ATACH_DMA_WAIT) { 1257 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1258 sc->sc_enable_intr(mvport, 1 /*on*/); 1259 chp->ch_flags &= ~ATACH_DMA_WAIT; 1260 } 1261 1262 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1263 KASSERT(xfer->c_flags & C_TIMEOU); 1264 mvsata_bio_intr(chp, xfer, 0); 1265 } 1266 } 1267 1268 static int 1269 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int intr_arg) 1270 { 1271 struct atac_softc *atac = chp->ch_atac; 1272 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1273 struct ata_bio *ata_bio = &xfer->c_bio; 1274 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1275 int irq = ISSET(xfer->c_flags, (C_POLL|C_TIMEOU)) ? 0 : 1; 1276 int tfd = 0; 1277 1278 if (ISSET(xfer->c_flags, C_DMA|C_RECOVERED) && irq) { 1279 /* Invoked via mvsata_edma_handle() or recovery */ 1280 tfd = intr_arg; 1281 1282 if (tfd > 0 && ata_bio->error == NOERROR) { 1283 if (ATACH_ST(tfd) & WDCS_ERR) 1284 ata_bio->error = ERROR; 1285 if (ATACH_ST(tfd) & WDCS_BSY) 1286 ata_bio->error = TIMEOUT; 1287 ata_bio->r_error = ATACH_ERR(tfd); 1288 } 1289 } 1290 1291 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1292 device_xname(atac->atac_dev), chp->ch_channel, __func__, 1293 xfer->c_drive)); 1294 1295 /* Cleanup EDMA if invoked from wdctimeout()/ata_timeout() */ 1296 if (ISSET(xfer->c_flags, C_TIMEOU) && ISSET(xfer->c_flags, C_DMA) 1297 && !ISSET(xfer->c_flags, C_POLL)) { 1298 mvsata_edma_rqq_remove((struct mvsata_port *)chp, xfer); 1299 } 1300 1301 ata_channel_lock(chp); 1302 1303 chp->ch_flags &= ~(ATACH_DMA_WAIT); 1304 1305 /* 1306 * If we missed an interrupt transfer, reset and restart. 1307 * Don't try to continue transfer, we may have missed cycles. 1308 */ 1309 if (xfer->c_flags & C_TIMEOU) { 1310 ata_bio->error = TIMEOUT; 1311 ata_channel_unlock(chp); 1312 mvsata_bio_done(chp, xfer); 1313 return 1; 1314 } 1315 1316 /* Is it not a transfer, but a control operation? */ 1317 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1318 aprint_error_dev(atac->atac_dev, 1319 "channel %d: drive %d bad state %d in %s\n", 1320 chp->ch_channel, xfer->c_drive, drvp->state, __func__); 1321 panic("%s: bad state", __func__); 1322 } 1323 1324 /* Ack interrupt done by wdc_wait_for_unbusy */ 1325 if (!(xfer->c_flags & C_DMA) && 1326 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) 1327 == WDCWAIT_TOUT)) { 1328 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1329 ata_channel_unlock(chp); 1330 return 0; /* IRQ was not for us */ 1331 } 1332 aprint_error_dev(atac->atac_dev, 1333 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1334 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1335 xfer->c_skip); 1336 ata_bio->error = TIMEOUT; 1337 ata_channel_unlock(chp); 1338 mvsata_bio_done(chp, xfer); 1339 return 1; 1340 } 1341 1342 if (xfer->c_flags & C_DMA) { 1343 if (ata_bio->error == NOERROR) 1344 goto end; 1345 if (ata_bio->error == ERR_DMA) { 1346 ata_dmaerr(drvp, 1347 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1348 ata_channel_unlock(chp); 1349 goto err; 1350 } 1351 } 1352 1353 /* if we had an error, end */ 1354 if (ata_bio->error != NOERROR) { 1355 ata_channel_unlock(chp); 1356 err: 1357 mvsata_bio_done(chp, xfer); 1358 return 1; 1359 } 1360 1361 /* If this was a read and not using DMA, fetch the data. */ 1362 if ((ata_bio->flags & ATA_READ) != 0) { 1363 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 1364 aprint_error_dev(atac->atac_dev, 1365 "channel %d: drive %d read intr before drq\n", 1366 chp->ch_channel, xfer->c_drive); 1367 ata_bio->error = TIMEOUT; 1368 ata_channel_unlock(chp); 1369 mvsata_bio_done(chp, xfer); 1370 return 1; 1371 } 1372 wdc->datain_pio(chp, drvp->drive_flags, 1373 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1374 } 1375 1376 end: 1377 ata_bio->blkno += ata_bio->nblks; 1378 ata_bio->blkdone += ata_bio->nblks; 1379 xfer->c_skip += ata_bio->nbytes; 1380 xfer->c_bcount -= ata_bio->nbytes; 1381 1382 /* See if this transfer is complete. */ 1383 if (xfer->c_bcount > 0) { 1384 if ((ata_bio->flags & ATA_POLL) == 0) { 1385 /* Start the next operation */ 1386 ata_xfer_start(xfer); 1387 } else { 1388 /* Let mvsata_bio_start do the loop */ 1389 } 1390 ata_channel_unlock(chp); 1391 } else { /* Done with this transfer */ 1392 ata_bio->error = NOERROR; 1393 ata_channel_unlock(chp); 1394 mvsata_bio_done(chp, xfer); 1395 } 1396 return 1; 1397 } 1398 1399 static void 1400 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1401 { 1402 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1403 struct atac_softc *atac = chp->ch_atac; 1404 struct ata_bio *ata_bio = &xfer->c_bio; 1405 int drive = xfer->c_drive; 1406 bool deactivate = true; 1407 1408 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1409 ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1410 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1411 1412 /* EDMA restart, if enabled */ 1413 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1414 mvsata_edma_reset_qptr(mvport); 1415 mvsata_edma_enable(mvport); 1416 } 1417 1418 ata_bio->flags |= ATA_ITSDONE; 1419 switch (reason) { 1420 case KILL_GONE_INACTIVE: 1421 deactivate = false; 1422 /* FALLTHROUGH */ 1423 case KILL_GONE: 1424 ata_bio->error = ERR_NODEV; 1425 break; 1426 case KILL_RESET: 1427 ata_bio->error = ERR_RESET; 1428 break; 1429 case KILL_REQUEUE: 1430 ata_bio->error = REQUEUE; 1431 break; 1432 default: 1433 aprint_error_dev(atac->atac_dev, 1434 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1435 panic("mvsata_bio_kill_xfer"); 1436 } 1437 ata_bio->r_error = WDCE_ABRT; 1438 1439 if (deactivate) 1440 ata_deactivate_xfer(chp, xfer); 1441 1442 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1443 } 1444 1445 static void 1446 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1447 { 1448 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1449 struct ata_bio *ata_bio = &xfer->c_bio; 1450 int drive = xfer->c_drive; 1451 bool iserror = (ata_bio->error != NOERROR); 1452 1453 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1454 ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1455 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1456 (u_int)xfer->c_flags)); 1457 1458 /* EDMA restart, if enabled */ 1459 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode_curr != nodma) { 1460 mvsata_edma_reset_qptr(mvport); 1461 mvsata_edma_enable(mvport); 1462 } 1463 1464 if (ata_waitdrain_xfer_check(chp, xfer)) 1465 return; 1466 1467 /* feed back residual bcount to our caller */ 1468 ata_bio->bcount = xfer->c_bcount; 1469 1470 /* mark controller inactive and free xfer */ 1471 ata_deactivate_xfer(chp, xfer); 1472 1473 ata_bio->flags |= ATA_ITSDONE; 1474 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1475 if (!iserror) 1476 atastart(chp); 1477 } 1478 1479 static int 1480 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1481 int flags) 1482 { 1483 struct ata_channel *chp = &mvport->port_ata_channel; 1484 struct atac_softc *atac = chp->ch_atac; 1485 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1486 const char *errstring; 1487 int tfd; 1488 1489 flags |= AT_POLL; /* XXX */ 1490 1491 ata_channel_lock_owned(chp); 1492 1493 /* 1494 * disable interrupts, all commands here should be quick 1495 * enough to be able to poll, and we don't go here that often 1496 */ 1497 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1498 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1499 DELAY(10); 1500 errstring = "wait"; 1501 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1502 goto ctrltimeout; 1503 wdccommandshort(chp, 0, WDCC_RECAL); 1504 /* Wait for at least 400ns for status bit to be valid */ 1505 DELAY(1); 1506 errstring = "recal"; 1507 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1508 goto ctrltimeout; 1509 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1510 goto ctrlerror; 1511 /* Don't try to set modes if controller can't be adjusted */ 1512 if (atac->atac_set_modes == NULL) 1513 goto geometry; 1514 /* Also don't try if the drive didn't report its mode */ 1515 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 1516 goto geometry; 1517 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1518 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1519 errstring = "piomode-bio"; 1520 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1521 goto ctrltimeout; 1522 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1523 goto ctrlerror; 1524 if (drvp->drive_flags & ATA_DRIVE_UDMA) 1525 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1526 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1527 else if (drvp->drive_flags & ATA_DRIVE_DMA) 1528 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 1529 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1530 else 1531 goto geometry; 1532 errstring = "dmamode-bio"; 1533 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1534 goto ctrltimeout; 1535 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1536 goto ctrlerror; 1537 geometry: 1538 if (ata_bio->flags & ATA_LBA) 1539 goto multimode; 1540 wdccommand(chp, 0, WDCC_IDP, drvp->lp->d_ncylinders, 1541 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 1542 (drvp->lp->d_type == DKTYPE_ST506) ? 1543 drvp->lp->d_precompcyl / 4 : 0); 1544 errstring = "geometry"; 1545 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1546 goto ctrltimeout; 1547 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1548 goto ctrlerror; 1549 multimode: 1550 if (drvp->multi == 1) 1551 goto ready; 1552 wdccommand(chp, 0, WDCC_SETMULTI, 0, 0, 0, drvp->multi, 0); 1553 errstring = "setmulti"; 1554 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags, &tfd)) 1555 goto ctrltimeout; 1556 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 1557 goto ctrlerror; 1558 ready: 1559 drvp->state = READY; 1560 /* 1561 * The drive is usable now 1562 */ 1563 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1564 delay(10); /* some drives need a little delay here */ 1565 return 0; 1566 1567 ctrltimeout: 1568 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1569 chp->ch_channel, drive, errstring); 1570 ata_bio->error = TIMEOUT; 1571 goto ctrldone; 1572 ctrlerror: 1573 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1574 chp->ch_channel, drive, errstring); 1575 if (ATACH_ST(tfd) & WDCS_DWF) { 1576 aprint_error("drive fault\n"); 1577 ata_bio->error = ERR_DF; 1578 } else { 1579 ata_bio->r_error = ATACH_ERR(tfd); 1580 ata_bio->error = ERROR; 1581 aprint_error("error (%x)\n", ata_bio->r_error); 1582 } 1583 ctrldone: 1584 drvp->state = 0; 1585 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1586 return -1; 1587 } 1588 1589 static const struct ata_xfer_ops mvsata_wdc_cmd_xfer_ops = { 1590 .c_start = mvsata_wdc_cmd_start, 1591 .c_intr = mvsata_wdc_cmd_intr, 1592 .c_poll = mvsata_wdc_cmd_poll, 1593 .c_abort = mvsata_wdc_cmd_done, 1594 .c_kill_xfer = mvsata_wdc_cmd_kill_xfer, 1595 }; 1596 1597 static void 1598 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1599 { 1600 struct ata_channel *chp = drvp->chnl_softc; 1601 struct ata_command *ata_c = &xfer->c_ata_c; 1602 1603 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1604 ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 1605 " r_lba=0x%012"PRIx64", r_count=0x%04x, r_features=0x%04x," 1606 " r_device=0x%02x, r_command=0x%02x\n", 1607 device_xname(MVSATA_DEV2((struct mvsata_port *)chp)), 1608 chp->ch_channel, 1609 drvp->drive, ata_c->bcount, ata_c->r_lba, ata_c->r_count, 1610 ata_c->r_features, ata_c->r_device, ata_c->r_command)); 1611 1612 if (ata_c->flags & AT_POLL) 1613 xfer->c_flags |= C_POLL; 1614 if (ata_c->flags & AT_WAIT) 1615 xfer->c_flags |= C_WAIT; 1616 xfer->c_drive = drvp->drive; 1617 xfer->c_databuf = ata_c->data; 1618 xfer->c_bcount = ata_c->bcount; 1619 xfer->ops = &mvsata_wdc_cmd_xfer_ops; 1620 1621 ata_exec_xfer(chp, xfer); 1622 } 1623 1624 static int 1625 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1626 { 1627 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1628 int drive = xfer->c_drive; 1629 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1630 struct ata_command *ata_c = &xfer->c_ata_c; 1631 int tfd; 1632 1633 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1634 ("%s:%d: mvsata_cmd_start: drive=%d\n", 1635 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1636 1637 ata_channel_lock_owned(chp); 1638 1639 /* First, EDMA disable, if enabled this channel. */ 1640 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 1641 if (mvport->port_edmamode_curr != nodma) 1642 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1643 1644 mvsata_pmp_select(mvport, drive); 1645 1646 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1647 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1648 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1649 case WDCWAIT_OK: 1650 break; 1651 case WDCWAIT_TOUT: 1652 ata_c->flags |= AT_TIMEOU; 1653 return ATASTART_ABORT; 1654 case WDCWAIT_THR: 1655 return ATASTART_TH; 1656 } 1657 if (ata_c->flags & AT_POLL) 1658 /* polled command, disable interrupts */ 1659 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1660 if ((ata_c->flags & AT_LBA48) != 0) { 1661 wdccommandext(chp, 0, ata_c->r_command, 1662 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1663 ata_c->r_device & ~0x10); 1664 } else { 1665 wdccommand(chp, 0, ata_c->r_command, 1666 (ata_c->r_lba >> 8) & 0xffff, 1667 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1668 ((ata_c->r_lba >> 24) & 0x0f), 1669 ata_c->r_lba & 0xff, 1670 ata_c->r_count & 0xff, 1671 ata_c->r_features & 0xff); 1672 } 1673 1674 if ((ata_c->flags & AT_POLL) == 0) { 1675 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1676 wdctimeout, chp); 1677 return ATASTART_STARTED; 1678 } 1679 1680 return ATASTART_POLL; 1681 } 1682 1683 static void 1684 mvsata_wdc_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1685 { 1686 /* 1687 * Polled command. Wait for drive ready or drq. Done in intr(). 1688 * Wait for at last 400ns for status bit to be valid. 1689 */ 1690 delay(10); /* 400ns delay */ 1691 mvsata_wdc_cmd_intr(chp, xfer, 0); 1692 } 1693 1694 static int 1695 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1696 { 1697 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1698 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1699 struct ata_command *ata_c = &xfer->c_ata_c; 1700 int bcount = ata_c->bcount; 1701 char *data = ata_c->data; 1702 int wflags; 1703 int drive_flags; 1704 int tfd; 1705 1706 ata_channel_lock(chp); 1707 1708 if (ata_c->r_command == WDCC_IDENTIFY || 1709 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1710 /* 1711 * The IDENTIFY data has been designed as an array of 1712 * u_int16_t, so we can byteswap it on the fly. 1713 * Historically it's what we have always done so keeping it 1714 * here ensure binary backward compatibility. 1715 */ 1716 drive_flags = ATA_DRIVE_NOSTREAM | 1717 chp->ch_drive[xfer->c_drive].drive_flags; 1718 else 1719 /* 1720 * Other data structure are opaque and should be transferred 1721 * as is. 1722 */ 1723 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1724 1725 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1726 /* both wait and poll, we can kpause here */ 1727 wflags = AT_WAIT | AT_POLL; 1728 else 1729 wflags = AT_POLL; 1730 1731 again: 1732 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d: %s: drive=%d\n", 1733 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 1734 __func__, xfer->c_drive)); 1735 1736 /* 1737 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1738 * Reselect again, it doesn't hurt for others commands, and the time 1739 * penalty for the extra register write is acceptable, 1740 * wdc_exec_command() isn't called often (mostly for autoconfig) 1741 */ 1742 if ((xfer->c_flags & C_ATAPI) != 0) { 1743 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1744 } 1745 if ((ata_c->flags & AT_XFDONE) != 0) { 1746 /* 1747 * We have completed a data xfer. The drive should now be 1748 * in its initial state 1749 */ 1750 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1751 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1752 wflags, &tfd) == WDCWAIT_TOUT) { 1753 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1754 ata_channel_unlock(chp); 1755 return 0; /* IRQ was not for us */ 1756 } 1757 ata_c->flags |= AT_TIMEOU; 1758 } 1759 goto out; 1760 } 1761 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1762 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1763 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1764 ata_channel_unlock(chp); 1765 return 0; /* IRQ was not for us */ 1766 } 1767 ata_c->flags |= AT_TIMEOU; 1768 goto out; 1769 } 1770 delay(20); /* XXXXX: Delay more times. */ 1771 if (ata_c->flags & AT_READ) { 1772 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1773 ata_c->flags |= AT_TIMEOU; 1774 goto out; 1775 } 1776 wdc->datain_pio(chp, drive_flags, data, bcount); 1777 /* at this point the drive should be in its initial state */ 1778 ata_c->flags |= AT_XFDONE; 1779 /* 1780 * XXX checking the status register again here cause some 1781 * hardware to timeout. 1782 */ 1783 } else if (ata_c->flags & AT_WRITE) { 1784 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1785 ata_c->flags |= AT_TIMEOU; 1786 goto out; 1787 } 1788 wdc->dataout_pio(chp, drive_flags, data, bcount); 1789 ata_c->flags |= AT_XFDONE; 1790 if ((ata_c->flags & AT_POLL) == 0) { 1791 callout_reset(&chp->c_timo_callout, 1792 mstohz(ata_c->timeout), wdctimeout, chp); 1793 ata_channel_unlock(chp); 1794 return 1; 1795 } else 1796 goto again; 1797 } 1798 out: 1799 if (ATACH_ST(tfd) & WDCS_DWF) 1800 ata_c->flags |= AT_DF; 1801 if (ATACH_ST(tfd) & WDCS_ERR) { 1802 ata_c->flags |= AT_ERROR; 1803 ata_c->r_error = ATACH_ERR(tfd); 1804 } 1805 ata_channel_unlock(chp); 1806 mvsata_wdc_cmd_done(chp, xfer); 1807 1808 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1809 atastart(chp); 1810 1811 return 1; 1812 } 1813 1814 static void 1815 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1816 int reason) 1817 { 1818 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1819 struct ata_command *ata_c = &xfer->c_ata_c; 1820 bool deactivate = true; 1821 1822 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1823 ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1824 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1825 1826 switch (reason) { 1827 case KILL_GONE_INACTIVE: 1828 deactivate = false; 1829 /* FALLTHROUGH */ 1830 case KILL_GONE: 1831 ata_c->flags |= AT_GONE; 1832 break; 1833 case KILL_RESET: 1834 ata_c->flags |= AT_RESET; 1835 break; 1836 case KILL_REQUEUE: 1837 panic("%s: not supposed to be requeued\n", __func__); 1838 break; 1839 default: 1840 aprint_error_dev(MVSATA_DEV2(mvport), 1841 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1842 panic("mvsata_cmd_kill_xfer"); 1843 } 1844 1845 mvsata_wdc_cmd_done_end(chp, xfer); 1846 1847 if (deactivate) 1848 ata_deactivate_xfer(chp, xfer); 1849 } 1850 1851 static void 1852 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1853 { 1854 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1855 struct atac_softc *atac = chp->ch_atac; 1856 struct ata_command *ata_c = &xfer->c_ata_c; 1857 1858 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 1859 ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1860 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1861 ata_c->flags)); 1862 1863 if (ata_waitdrain_xfer_check(chp, xfer)) 1864 return; 1865 1866 if ((ata_c->flags & AT_READREG) != 0 && 1867 device_is_active(atac->atac_dev) && 1868 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1869 ata_c->r_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 1870 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1871 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1872 ata_c->r_lba = 1873 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 0; 1874 ata_c->r_lba |= 1875 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1876 ata_c->r_lba |= 1877 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 16; 1878 ata_c->r_device = MVSATA_WDC_READ_1(mvport, SRB_H); 1879 if ((ata_c->flags & AT_LBA48) != 0) { 1880 if ((ata_c->flags & AT_POLL) != 0) { 1881 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1882 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1883 } else { 1884 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1885 WDCTL_HOB|WDCTL_4BIT); 1886 } 1887 ata_c->r_count |= 1888 MVSATA_WDC_READ_1(mvport, SRB_SC) << 8; 1889 ata_c->r_lba |= 1890 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 24; 1891 ata_c->r_lba |= 1892 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 32; 1893 ata_c->r_lba |= 1894 (uint64_t)MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 40; 1895 if ((ata_c->flags & AT_POLL) != 0) { 1896 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1897 WDCTL_4BIT|WDCTL_IDS); 1898 } else { 1899 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, 1900 WDCTL_4BIT); 1901 } 1902 } else { 1903 ata_c->r_lba |= 1904 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1905 } 1906 } 1907 1908 if (ata_c->flags & AT_POLL) { 1909 /* enable interrupts */ 1910 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1911 delay(10); /* some drives need a little delay here */ 1912 } 1913 1914 mvsata_wdc_cmd_done_end(chp, xfer); 1915 1916 ata_deactivate_xfer(chp, xfer); 1917 } 1918 1919 static void 1920 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1921 { 1922 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1923 struct ata_command *ata_c = &xfer->c_ata_c; 1924 1925 /* EDMA restart, if enabled */ 1926 if (mvport->port_edmamode_curr != nodma) { 1927 mvsata_edma_reset_qptr(mvport); 1928 mvsata_edma_enable(mvport); 1929 } 1930 1931 ata_c->flags |= AT_DONE; 1932 } 1933 1934 #if NATAPIBUS > 0 1935 static const struct ata_xfer_ops mvsata_atapi_xfer_ops = { 1936 .c_start = mvsata_atapi_start, 1937 .c_intr = mvsata_atapi_intr, 1938 .c_poll = mvsata_atapi_poll, 1939 .c_abort = mvsata_atapi_reset, 1940 .c_kill_xfer = mvsata_atapi_kill_xfer, 1941 }; 1942 1943 static void 1944 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 1945 scsipi_adapter_req_t req, void *arg) 1946 { 1947 struct scsipi_adapter *adapt = chan->chan_adapter; 1948 struct scsipi_periph *periph; 1949 struct scsipi_xfer *sc_xfer; 1950 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 1951 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1952 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1953 struct ata_xfer *xfer; 1954 int drive, s; 1955 1956 switch (req) { 1957 case ADAPTER_REQ_RUN_XFER: 1958 sc_xfer = arg; 1959 periph = sc_xfer->xs_periph; 1960 drive = periph->periph_target; 1961 1962 if (!device_is_active(atac->atac_dev)) { 1963 sc_xfer->error = XS_DRIVER_STUFFUP; 1964 scsipi_done(sc_xfer); 1965 return; 1966 } 1967 xfer = ata_get_xfer(chp, false); 1968 if (xfer == NULL) { 1969 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1970 scsipi_done(sc_xfer); 1971 return; 1972 } 1973 1974 if (sc_xfer->xs_control & XS_CTL_POLL) 1975 xfer->c_flags |= C_POLL; 1976 xfer->c_drive = drive; 1977 xfer->c_flags |= C_ATAPI; 1978 xfer->c_databuf = sc_xfer->data; 1979 xfer->c_bcount = sc_xfer->datalen; 1980 xfer->ops = &mvsata_atapi_xfer_ops; 1981 xfer->c_scsipi = sc_xfer; 1982 xfer->c_atapi.c_dscpoll = 0; 1983 s = splbio(); 1984 ata_exec_xfer(chp, xfer); 1985 #ifdef DIAGNOSTIC 1986 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1987 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1988 panic("mvsata_atapi_scsipi_request:" 1989 " polled command not done"); 1990 #endif 1991 splx(s); 1992 return; 1993 1994 default: 1995 /* Not supported, nothing to do. */ 1996 ; 1997 } 1998 } 1999 2000 static int 2001 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 2002 { 2003 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 2004 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2005 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 2006 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2007 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2008 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 2009 const char *errstring; 2010 int tfd; 2011 2012 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2013 ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 2014 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2015 xfer->c_drive, sc_xfer->xs_control)); 2016 2017 ata_channel_lock_owned(chp); 2018 2019 KASSERT((chp->ch_flags & ATACH_NCQ) == 0); 2020 if (mvport->port_edmamode_curr != nodma) 2021 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 2022 2023 mvsata_pmp_select(mvport, xfer->c_drive); 2024 2025 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 2026 drvp->n_xfers++; 2027 2028 /* Do control operations specially. */ 2029 if (__predict_false(drvp->state < READY)) { 2030 /* If it's not a polled command, we need the kernel thread */ 2031 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 2032 && !ata_is_thread_run(chp)) 2033 return ATASTART_TH; 2034 2035 /* 2036 * disable interrupts, all commands here should be quick 2037 * enough to be able to poll, and we don't go here that often 2038 */ 2039 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 2040 2041 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2042 /* Don't try to set mode if controller can't be adjusted */ 2043 if (atac->atac_set_modes == NULL) 2044 goto ready; 2045 /* Also don't try if the drive didn't report its mode */ 2046 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 2047 goto ready; 2048 errstring = "unbusy"; 2049 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 2050 goto timeout; 2051 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2052 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 2053 errstring = "piomode-atapi"; 2054 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2055 &tfd)) 2056 goto timeout; 2057 if (ATACH_ST(tfd) & WDCS_ERR) { 2058 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2059 /* 2060 * Some ATAPI drives reject PIO settings. 2061 * Fall back to PIO mode 3 since that's the 2062 * minimum for ATAPI. 2063 */ 2064 aprint_error_dev(atac->atac_dev, 2065 "channel %d drive %d: PIO mode %d rejected," 2066 " falling back to PIO mode 3\n", 2067 chp->ch_channel, xfer->c_drive, 2068 drvp->PIO_mode); 2069 if (drvp->PIO_mode > 3) 2070 drvp->PIO_mode = 3; 2071 } else 2072 goto error; 2073 } 2074 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2075 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2076 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 2077 else 2078 if (drvp->drive_flags & ATA_DRIVE_DMA) 2079 wdccommand(chp, 0, SET_FEATURES, 0, 0, 0, 2080 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 2081 else 2082 goto ready; 2083 errstring = "dmamode-atapi"; 2084 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 2085 &tfd)) 2086 goto timeout; 2087 if (ATACH_ST(tfd) & WDCS_ERR) { 2088 if (ATACH_ERR(tfd) == WDCE_ABRT) { 2089 if (drvp->drive_flags & ATA_DRIVE_UDMA) 2090 goto error; 2091 else { 2092 /* 2093 * The drive rejected our DMA setting. 2094 * Fall back to mode 1. 2095 */ 2096 aprint_error_dev(atac->atac_dev, 2097 "channel %d drive %d:" 2098 " DMA mode %d rejected," 2099 " falling back to DMA mode 0\n", 2100 chp->ch_channel, xfer->c_drive, 2101 drvp->DMA_mode); 2102 if (drvp->DMA_mode > 0) 2103 drvp->DMA_mode = 0; 2104 } 2105 } else 2106 goto error; 2107 } 2108 ready: 2109 drvp->state = READY; 2110 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2111 delay(10); /* some drives need a little delay here */ 2112 } 2113 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2114 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd) != 0) { 2115 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 2116 ATACH_ST(tfd)); 2117 sc_xfer->error = XS_TIMEOUT; 2118 return ATASTART_ABORT; 2119 } 2120 2121 /* start timeout machinery */ 2122 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2123 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 2124 wdctimeout, chp); 2125 2126 /* 2127 * Even with WDCS_ERR, the device should accept a command packet 2128 * Limit length to what can be stuffed into the cylinder register 2129 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 2130 * but not all devices do that and it's not obvious from the 2131 * ATAPI spec that that behaviour should be expected. If more 2132 * data is necessary, multiple data transfer phases will be done. 2133 */ 2134 2135 wdccommand(chp, 0, ATAPI_PKT_CMD, 2136 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 2137 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 2138 2139 /* 2140 * If there is no interrupt for CMD input, busy-wait for it (done in 2141 * the interrupt routine. Poll routine will exit early in this case. 2142 */ 2143 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 2144 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 2145 return ATASTART_POLL; 2146 else 2147 return ATASTART_STARTED; 2148 2149 timeout: 2150 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 2151 chp->ch_channel, xfer->c_drive, errstring); 2152 sc_xfer->error = XS_TIMEOUT; 2153 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2154 delay(10); /* some drives need a little delay here */ 2155 return ATASTART_ABORT; 2156 2157 error: 2158 aprint_error_dev(atac->atac_dev, 2159 "channel %d drive %d: %s error (0x%x)\n", 2160 chp->ch_channel, xfer->c_drive, errstring, ATACH_ERR(tfd)); 2161 sc_xfer->error = XS_SHORTSENSE; 2162 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2163 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 2164 delay(10); /* some drives need a little delay here */ 2165 return ATASTART_ABORT; 2166 } 2167 2168 static void 2169 mvsata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 2170 { 2171 /* 2172 * If there is no interrupt for CMD input, busy-wait for it (done in 2173 * the interrupt routine. If it is a polled command, call the interrupt 2174 * routine until command is done. 2175 */ 2176 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 2177 2178 /* Wait for at last 400ns for status bit to be valid */ 2179 DELAY(1); 2180 mvsata_atapi_intr(chp, xfer, 0); 2181 2182 if (!poll) 2183 return; 2184 2185 if (chp->ch_flags & ATACH_DMA_WAIT) { 2186 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 2187 chp->ch_flags &= ~ATACH_DMA_WAIT; 2188 } 2189 2190 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 2191 /* Wait for at last 400ns for status bit to be valid */ 2192 DELAY(1); 2193 mvsata_atapi_intr(chp, xfer, 0); 2194 } 2195 } 2196 2197 static int 2198 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 2199 { 2200 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2201 struct atac_softc *atac = chp->ch_atac; 2202 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2203 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2204 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2205 int len, phase, ire, error, retries=0, i; 2206 int tfd; 2207 void *cmd; 2208 2209 ata_channel_lock(chp); 2210 2211 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2212 ("%s:%d:%d: mvsata_atapi_intr\n", 2213 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 2214 2215 /* Is it not a transfer, but a control operation? */ 2216 if (drvp->state < READY) { 2217 aprint_error_dev(atac->atac_dev, 2218 "channel %d drive %d: bad state %d\n", 2219 chp->ch_channel, xfer->c_drive, drvp->state); 2220 panic("mvsata_atapi_intr: bad state"); 2221 } 2222 /* 2223 * If we missed an interrupt in a PIO transfer, reset and restart. 2224 * Don't try to continue transfer, we may have missed cycles. 2225 */ 2226 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 2227 ata_channel_unlock(chp); 2228 sc_xfer->error = XS_TIMEOUT; 2229 mvsata_atapi_reset(chp, xfer); 2230 return 1; 2231 } 2232 2233 /* Ack interrupt done in wdc_wait_for_unbusy */ 2234 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 2235 if (wdc_wait_for_unbusy(chp, 2236 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 2237 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 2238 ata_channel_unlock(chp); 2239 return 0; /* IRQ was not for us */ 2240 } 2241 aprint_error_dev(atac->atac_dev, 2242 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 2243 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 2244 if (xfer->c_flags & C_DMA) 2245 ata_dmaerr(drvp, 2246 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2247 sc_xfer->error = XS_TIMEOUT; 2248 ata_channel_unlock(chp); 2249 mvsata_atapi_reset(chp, xfer); 2250 return 1; 2251 } 2252 2253 /* 2254 * If we missed an IRQ and were using DMA, flag it as a DMA error 2255 * and reset device. 2256 */ 2257 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 2258 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2259 sc_xfer->error = XS_RESET; 2260 ata_channel_unlock(chp); 2261 mvsata_atapi_reset(chp, xfer); 2262 return (1); 2263 } 2264 /* 2265 * if the request sense command was aborted, report the short sense 2266 * previously recorded, else continue normal processing 2267 */ 2268 2269 again: 2270 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2271 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2272 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2273 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 2274 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ( 2275 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2276 xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire)); 2277 2278 switch (phase) { 2279 case PHASE_CMDOUT: 2280 cmd = sc_xfer->cmd; 2281 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("PHASE_CMDOUT\n")); 2282 /* Init the DMA channel if necessary */ 2283 if (xfer->c_flags & C_DMA) { 2284 error = mvsata_bdma_init(mvport, xfer); 2285 if (error) { 2286 if (error == EINVAL) { 2287 /* 2288 * We can't do DMA on this transfer 2289 * for some reason. Fall back to PIO. 2290 */ 2291 xfer->c_flags &= ~C_DMA; 2292 error = 0; 2293 } else { 2294 sc_xfer->error = XS_DRIVER_STUFFUP; 2295 break; 2296 } 2297 } 2298 } 2299 2300 /* send packet command */ 2301 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2302 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2303 2304 /* Start the DMA channel if necessary */ 2305 if (xfer->c_flags & C_DMA) { 2306 mvsata_bdma_start(mvport); 2307 chp->ch_flags |= ATACH_DMA_WAIT; 2308 } 2309 ata_channel_unlock(chp); 2310 return 1; 2311 2312 case PHASE_DATAOUT: 2313 /* write data */ 2314 DPRINTF(DEBUG_XFERS, ("PHASE_DATAOUT\n")); 2315 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2316 (xfer->c_flags & C_DMA) != 0) { 2317 aprint_error_dev(atac->atac_dev, 2318 "channel %d drive %d: bad data phase DATAOUT\n", 2319 chp->ch_channel, xfer->c_drive); 2320 if (xfer->c_flags & C_DMA) 2321 ata_dmaerr(drvp, 2322 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2323 sc_xfer->error = XS_TIMEOUT; 2324 ata_channel_unlock(chp); 2325 mvsata_atapi_reset(chp, xfer); 2326 return 1; 2327 } 2328 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2329 if (xfer->c_bcount < len) { 2330 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2331 " warning: write only %d of %d requested bytes\n", 2332 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2333 len); 2334 len = xfer->c_bcount; 2335 } 2336 2337 wdc->dataout_pio(chp, drvp->drive_flags, 2338 (char *)xfer->c_databuf + xfer->c_skip, len); 2339 2340 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 2341 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2342 2343 xfer->c_skip += len; 2344 xfer->c_bcount -= len; 2345 ata_channel_unlock(chp); 2346 return 1; 2347 2348 case PHASE_DATAIN: 2349 /* Read data */ 2350 DPRINTF(DEBUG_XFERS, ("PHASE_DATAIN\n")); 2351 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2352 (xfer->c_flags & C_DMA) != 0) { 2353 aprint_error_dev(atac->atac_dev, 2354 "channel %d drive %d: bad data phase DATAIN\n", 2355 chp->ch_channel, xfer->c_drive); 2356 if (xfer->c_flags & C_DMA) 2357 ata_dmaerr(drvp, 2358 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2359 ata_channel_unlock(chp); 2360 sc_xfer->error = XS_TIMEOUT; 2361 mvsata_atapi_reset(chp, xfer); 2362 return 1; 2363 } 2364 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 2365 if (xfer->c_bcount < len) { 2366 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2367 " warning: reading only %d of %d bytes\n", 2368 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2369 len); 2370 len = xfer->c_bcount; 2371 } 2372 2373 wdc->datain_pio(chp, drvp->drive_flags, 2374 (char *)xfer->c_databuf + xfer->c_skip, len); 2375 2376 if (xfer->c_atapi.c_lenoff > 0) 2377 wdcbit_bucket(chp, len - xfer->c_bcount); 2378 2379 xfer->c_skip += len; 2380 xfer->c_bcount -= len; 2381 ata_channel_unlock(chp); 2382 return 1; 2383 2384 case PHASE_ABORTED: 2385 case PHASE_COMPLETED: 2386 DPRINTF(DEBUG_XFERS, ("PHASE_COMPLETED\n")); 2387 if (xfer->c_flags & C_DMA) 2388 xfer->c_bcount -= sc_xfer->datalen; 2389 sc_xfer->resid = xfer->c_bcount; 2390 /* this will unlock channel lock too */ 2391 mvsata_atapi_phase_complete(xfer, tfd); 2392 return 1; 2393 2394 default: 2395 if (++retries<500) { 2396 DELAY(100); 2397 tfd = ATACH_ERR_ST( 2398 MVSATA_WDC_READ_1(mvport, SRB_FE), 2399 MVSATA_WDC_READ_1(mvport, SRB_CS) 2400 ); 2401 goto again; 2402 } 2403 aprint_error_dev(atac->atac_dev, 2404 "channel %d drive %d: unknown phase 0x%x\n", 2405 chp->ch_channel, xfer->c_drive, phase); 2406 if (ATACH_ST(tfd) & WDCS_ERR) { 2407 sc_xfer->error = XS_SHORTSENSE; 2408 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2409 } else { 2410 if (xfer->c_flags & C_DMA) 2411 ata_dmaerr(drvp, 2412 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2413 sc_xfer->error = XS_RESET; 2414 ata_channel_unlock(chp); 2415 mvsata_atapi_reset(chp, xfer); 2416 return (1); 2417 } 2418 } 2419 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2420 ("mvsata_atapi_intr: %s (end), error 0x%x " 2421 "sense 0x%x\n", __func__, 2422 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2423 ata_channel_unlock(chp); 2424 mvsata_atapi_done(chp, xfer); 2425 return 1; 2426 } 2427 2428 static void 2429 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2430 int reason) 2431 { 2432 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2433 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2434 bool deactivate = true; 2435 2436 /* remove this command from xfer queue */ 2437 switch (reason) { 2438 case KILL_GONE_INACTIVE: 2439 deactivate = false; 2440 /* FALLTHROUGH */ 2441 case KILL_GONE: 2442 sc_xfer->error = XS_DRIVER_STUFFUP; 2443 break; 2444 case KILL_RESET: 2445 sc_xfer->error = XS_RESET; 2446 break; 2447 case KILL_REQUEUE: 2448 sc_xfer->error = XS_REQUEUE; 2449 break; 2450 default: 2451 aprint_error_dev(MVSATA_DEV2(mvport), 2452 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2453 panic("mvsata_atapi_kill_xfer"); 2454 } 2455 2456 if (deactivate) 2457 ata_deactivate_xfer(chp, xfer); 2458 2459 ata_free_xfer(chp, xfer); 2460 scsipi_done(sc_xfer); 2461 } 2462 2463 static void 2464 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2465 { 2466 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2467 struct atac_softc *atac = chp->ch_atac; 2468 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2469 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2470 int tfd; 2471 2472 ata_channel_lock(chp); 2473 2474 mvsata_pmp_select(mvport, xfer->c_drive); 2475 2476 wdccommandshort(chp, 0, ATAPI_SOFT_RESET); 2477 drvp->state = 0; 2478 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 2479 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2480 chp->ch_channel, xfer->c_drive); 2481 sc_xfer->error = XS_SELTIMEOUT; 2482 } 2483 2484 ata_channel_unlock(chp); 2485 2486 mvsata_atapi_done(chp, xfer); 2487 return; 2488 } 2489 2490 static void 2491 mvsata_atapi_phase_complete(struct ata_xfer *xfer, int tfd) 2492 { 2493 struct ata_channel *chp = xfer->c_chp; 2494 struct atac_softc *atac = chp->ch_atac; 2495 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2496 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2497 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2498 2499 ata_channel_lock_owned(chp); 2500 2501 /* wait for DSC if needed */ 2502 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 2503 DPRINTF(DEBUG_XFERS, 2504 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2505 device_xname(atac->atac_dev), chp->ch_channel, 2506 xfer->c_drive, xfer->c_atapi.c_dscpoll)); 2507 if (cold) 2508 panic("mvsata_atapi_phase_complete: cold"); 2509 2510 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL, &tfd) == 2511 WDCWAIT_TOUT) { 2512 /* 10ms not enough, try again in 1 tick */ 2513 if (xfer->c_atapi.c_dscpoll++ > 2514 mstohz(sc_xfer->timeout)) { 2515 aprint_error_dev(atac->atac_dev, 2516 "channel %d: wait_for_dsc failed\n", 2517 chp->ch_channel); 2518 ata_channel_unlock(chp); 2519 sc_xfer->error = XS_TIMEOUT; 2520 mvsata_atapi_reset(chp, xfer); 2521 } else { 2522 callout_reset(&chp->c_timo_callout, 1, 2523 mvsata_atapi_polldsc, chp); 2524 ata_channel_unlock(chp); 2525 } 2526 return; 2527 } 2528 } 2529 2530 /* 2531 * Some drive occasionally set WDCS_ERR with 2532 * "ATA illegal length indication" in the error 2533 * register. If we read some data the sense is valid 2534 * anyway, so don't report the error. 2535 */ 2536 if (ATACH_ST(tfd) & WDCS_ERR && 2537 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2538 sc_xfer->resid == sc_xfer->datalen)) { 2539 /* save the short sense */ 2540 sc_xfer->error = XS_SHORTSENSE; 2541 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 2542 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2543 /* ask scsipi to send a REQUEST_SENSE */ 2544 sc_xfer->error = XS_BUSY; 2545 sc_xfer->status = SCSI_CHECK; 2546 } else 2547 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2548 ata_dmaerr(drvp, 2549 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2550 sc_xfer->error = XS_RESET; 2551 ata_channel_unlock(chp); 2552 mvsata_atapi_reset(chp, xfer); 2553 return; 2554 } 2555 } 2556 if (xfer->c_bcount != 0) { 2557 DPRINTF(DEBUG_XFERS, ("%s:%d:%d: mvsata_atapi_intr:" 2558 " bcount value is %d after io\n", 2559 device_xname(atac->atac_dev), chp->ch_channel, 2560 xfer->c_drive, xfer->c_bcount)); 2561 } 2562 #ifdef DIAGNOSTIC 2563 if (xfer->c_bcount < 0) { 2564 aprint_error_dev(atac->atac_dev, 2565 "channel %d drive %d: mvsata_atapi_intr:" 2566 " warning: bcount value is %d after io\n", 2567 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2568 } 2569 #endif 2570 2571 DPRINTF(DEBUG_XFERS, 2572 ("%s:%d:%d: mvsata_atapi_phase_complete:" 2573 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2574 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2575 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2576 ata_channel_unlock(chp); 2577 mvsata_atapi_done(chp, xfer); 2578 } 2579 2580 static void 2581 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2582 { 2583 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2584 bool iserror = (sc_xfer->error != XS_NOERROR); 2585 2586 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2587 ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2588 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2589 xfer->c_drive, (u_int)xfer->c_flags)); 2590 2591 if (ata_waitdrain_xfer_check(chp, xfer)) 2592 return; 2593 2594 /* mark controller inactive and free the command */ 2595 ata_deactivate_xfer(chp, xfer); 2596 2597 ata_free_xfer(chp, xfer); 2598 2599 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2600 ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2601 device_xname(chp->ch_atac->atac_dev), chp->ch_channel)); 2602 scsipi_done(sc_xfer); 2603 DPRINTF(DEBUG_FUNCS, 2604 ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2605 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 2606 chp->ch_flags)); 2607 if (!iserror) 2608 atastart(chp); 2609 } 2610 2611 static void 2612 mvsata_atapi_polldsc(void *arg) 2613 { 2614 struct ata_channel *chp = arg; 2615 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 2616 2617 KASSERT(xfer != NULL); 2618 2619 ata_channel_lock(chp); 2620 2621 /* this will unlock channel lock too */ 2622 mvsata_atapi_phase_complete(xfer, 0); 2623 } 2624 #endif /* NATAPIBUS > 0 */ 2625 2626 2627 /* 2628 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2629 * if supported queuing command by atabus? The race condition will not happen 2630 * if this is called only to the thread of atabus. 2631 */ 2632 static int 2633 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_xfer *xfer) 2634 { 2635 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2636 struct ata_bio *ata_bio = &xfer->c_bio; 2637 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2638 struct eprd *eprd; 2639 bus_addr_t crqb_base_addr; 2640 bus_dmamap_t data_dmamap; 2641 uint32_t reg; 2642 int erqqip, erqqop, next, rv, i; 2643 2644 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, ("%s:%d:%d: mvsata_edma_enqueue:" 2645 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2646 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2647 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2648 2649 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2650 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2651 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2652 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2653 next = erqqip; 2654 MVSATA_EDMAQ_INC(next); 2655 if (next == erqqop) { 2656 /* queue full */ 2657 return EBUSY; 2658 } 2659 DPRINTF(DEBUG_XFERS, 2660 (" erqqip=%d, quetag=%d\n", erqqip, xfer->c_slot)); 2661 2662 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, ata_bio->nbytes, 2663 ata_bio->flags); 2664 if (rv != 0) 2665 return rv; 2666 2667 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2668 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2669 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2670 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2671 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2672 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2673 2674 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2675 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2676 eprd->eot = htole16(0); 2677 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2678 eprd++; 2679 } 2680 (eprd - 1)->eot |= htole16(EPRD_EOT); 2681 #ifdef MVSATA_DEBUG 2682 if (mvsata_debug >= 3) 2683 mvsata_print_eprd(mvport, xfer->c_slot); 2684 #endif 2685 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2686 mvport->port_reqtbl[xfer->c_slot].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2687 BUS_DMASYNC_PREWRITE); 2688 2689 /* setup EDMA Command Request Block (CRQB) Data */ 2690 sc->sc_edma_setup_crqb(mvport, erqqip, xfer); 2691 #ifdef MVSATA_DEBUG 2692 if (mvsata_debug >= 3) 2693 mvsata_print_crqb(mvport, erqqip); 2694 #endif 2695 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2696 erqqip * sizeof(union mvsata_crqb), 2697 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2698 2699 MVSATA_EDMAQ_INC(erqqip); 2700 2701 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2702 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2703 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2704 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2705 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2706 2707 return 0; 2708 } 2709 2710 static int 2711 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2712 { 2713 struct ata_channel *chp = &mvport->port_ata_channel; 2714 struct crpb *crpb; 2715 struct ata_bio *ata_bio; 2716 struct ata_xfer *xfer; 2717 uint32_t reg; 2718 int erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2719 int st, dmaerr; 2720 2721 /* First, Sync for Request Queue buffer */ 2722 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2723 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2724 if (mvport->port_prev_erqqop != erqqop) { 2725 const int s = sizeof(union mvsata_crqb); 2726 2727 if (mvport->port_prev_erqqop < erqqop) 2728 n = erqqop - mvport->port_prev_erqqop; 2729 else { 2730 if (erqqop > 0) 2731 bus_dmamap_sync(mvport->port_dmat, 2732 mvport->port_crqb_dmamap, 0, erqqop * s, 2733 BUS_DMASYNC_POSTWRITE); 2734 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2735 } 2736 if (n > 0) 2737 bus_dmamap_sync(mvport->port_dmat, 2738 mvport->port_crqb_dmamap, 2739 mvport->port_prev_erqqop * s, n * s, 2740 BUS_DMASYNC_POSTWRITE); 2741 mvport->port_prev_erqqop = erqqop; 2742 } 2743 2744 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2745 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2746 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2747 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2748 2749 DPRINTF(DEBUG_XFERS, 2750 ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2751 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2752 mvport->port, erpqip, erpqop)); 2753 2754 if (erpqop == erpqip) 2755 return 0; 2756 2757 if (erpqop < erpqip) 2758 n = erpqip - erpqop; 2759 else { 2760 if (erpqip > 0) 2761 bus_dmamap_sync(mvport->port_dmat, 2762 mvport->port_crpb_dmamap, 2763 0, erpqip * sizeof(struct crpb), 2764 BUS_DMASYNC_POSTREAD); 2765 n = MVSATA_EDMAQ_LEN - erpqop; 2766 } 2767 if (n > 0) 2768 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2769 erpqop * sizeof(struct crpb), 2770 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2771 2772 uint32_t aslots = ata_queue_active(chp); 2773 2774 prev_erpqop = erpqop; 2775 while (erpqop != erpqip) { 2776 #ifdef MVSATA_DEBUG 2777 if (mvsata_debug >= 3) 2778 mvsata_print_crpb(mvport, erpqop); 2779 #endif 2780 crpb = mvport->port_crpb + erpqop; 2781 MVSATA_EDMAQ_INC(erpqop); 2782 2783 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2784 2785 if ((aslots & __BIT(quetag)) == 0) { 2786 /* not actually executing */ 2787 continue; 2788 } 2789 2790 xfer = ata_queue_hwslot_to_xfer(chp, quetag); 2791 2792 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2793 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2794 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2795 2796 st = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2797 dmaerr = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2798 2799 ata_bio = &xfer->c_bio; 2800 ata_bio->error = NOERROR; 2801 if (dmaerr != 0) 2802 ata_bio->error = ERR_DMA; 2803 2804 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2805 2806 KASSERT(xfer->c_flags & C_DMA); 2807 mvsata_bio_intr(chp, xfer, ATACH_ERR_ST(0, st)); 2808 2809 if (xfer1 == NULL) 2810 handled++; 2811 else if (xfer == xfer1) { 2812 handled = 1; 2813 break; 2814 } 2815 } 2816 if (prev_erpqop < erpqop) 2817 n = erpqop - prev_erpqop; 2818 else { 2819 if (erpqop > 0) 2820 bus_dmamap_sync(mvport->port_dmat, 2821 mvport->port_crpb_dmamap, 0, 2822 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2823 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2824 } 2825 if (n > 0) 2826 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2827 prev_erpqop * sizeof(struct crpb), 2828 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2829 2830 reg &= ~EDMA_RESQP_ERPQP_MASK; 2831 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2832 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2833 2834 return handled; 2835 } 2836 2837 static int 2838 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2839 { 2840 int xtime; 2841 2842 for (xtime = 0; xtime < timeout * 10; xtime++) { 2843 if (mvsata_edma_handle(mvport, xfer)) 2844 return 0; 2845 DELAY(100); 2846 } 2847 2848 DPRINTF(DEBUG_FUNCS, ("%s: timeout: %p\n", __func__, xfer)); 2849 mvsata_edma_rqq_remove(mvport, xfer); 2850 xfer->c_flags |= C_TIMEOU; 2851 return 1; 2852 } 2853 2854 static void 2855 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2856 { 2857 struct ata_channel *chp = &mvport->port_ata_channel; 2858 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2859 bus_addr_t crqb_base_addr; 2860 int erqqip, i; 2861 2862 /* First, hardware reset, stop EDMA */ 2863 mvsata_hreset_port(mvport); 2864 2865 /* cleanup completed EDMA safely */ 2866 mvsata_edma_handle(mvport, NULL); 2867 2868 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2869 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2870 2871 uint32_t aslots = ata_queue_active(chp); 2872 2873 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2874 struct ata_xfer *rqxfer; 2875 2876 if ((aslots & __BIT(i)) == 0) 2877 continue; 2878 2879 if (i == xfer->c_slot) { 2880 /* remove xfer from EDMA request queue */ 2881 bus_dmamap_sync(mvport->port_dmat, 2882 mvport->port_eprd_dmamap, 2883 mvport->port_reqtbl[i].eprd_offset, 2884 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2885 mvsata_dma_bufunload(mvport, i, xfer->c_bio.flags); 2886 /* quetag freed by caller later */ 2887 continue; 2888 } 2889 2890 rqxfer = ata_queue_hwslot_to_xfer(chp, i); 2891 sc->sc_edma_setup_crqb(mvport, erqqip, rqxfer); 2892 erqqip++; 2893 } 2894 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2895 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2896 BUS_DMASYNC_POSTWRITE); 2897 2898 mvsata_edma_config(mvport, mvport->port_edmamode_curr); 2899 mvsata_edma_reset_qptr(mvport); 2900 mvsata_edma_enable(mvport); 2901 2902 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2903 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2904 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2905 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2906 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2907 } 2908 2909 #if NATAPIBUS > 0 2910 static int 2911 mvsata_bdma_init(struct mvsata_port *mvport, struct ata_xfer *xfer) 2912 { 2913 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 2914 struct eprd *eprd; 2915 bus_dmamap_t data_dmamap; 2916 bus_addr_t eprd_addr; 2917 int i, rv; 2918 void *databuf = (uint8_t *)xfer->c_databuf + xfer->c_skip; 2919 2920 DPRINTF(DEBUG_FUNCS|DEBUG_XFERS, 2921 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2922 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2923 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2924 2925 rv = mvsata_dma_bufload(mvport, xfer->c_slot, databuf, 2926 sc_xfer->datalen, 2927 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2928 if (rv != 0) 2929 return rv; 2930 2931 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2932 data_dmamap = mvport->port_reqtbl[xfer->c_slot].data_dmamap; 2933 eprd = mvport->port_reqtbl[xfer->c_slot].eprd; 2934 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2935 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2936 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2937 2938 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2939 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2940 eprd->eot = htole16(0); 2941 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2942 eprd++; 2943 } 2944 (eprd - 1)->eot |= htole16(EPRD_EOT); 2945 #ifdef MVSATA_DEBUG 2946 if (mvsata_debug >= 3) 2947 mvsata_print_eprd(mvport, xfer->c_slot); 2948 #endif 2949 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2950 mvport->port_reqtbl[xfer->c_slot].eprd_offset, 2951 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_PREWRITE); 2952 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2953 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 2954 2955 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2956 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2957 2958 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2959 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2960 else 2961 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2962 2963 return 0; 2964 } 2965 2966 static void 2967 mvsata_bdma_start(struct mvsata_port *mvport) 2968 { 2969 2970 #ifdef MVSATA_DEBUG 2971 if (mvsata_debug >= 3) 2972 mvsata_print_eprd(mvport, 0); 2973 #endif 2974 2975 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2976 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2977 } 2978 #endif 2979 #endif 2980 2981 2982 static int 2983 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2984 { 2985 struct mvsata_softc *sc = mvhc->hc_sc; 2986 struct mvsata_port *mvport; 2987 struct ata_channel *chp; 2988 int channel, rv, i; 2989 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2990 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2991 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2992 2993 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2994 M_ZERO | M_WAITOK); 2995 mvport->port = port; 2996 mvport->port_hc = mvhc; 2997 mvport->port_edmamode_negotiated = nodma; 2998 2999 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3000 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 3001 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 3002 if (rv != 0) { 3003 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 3004 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3005 goto fail0; 3006 } 3007 mvport->port_iot = mvhc->hc_iot; 3008 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 3009 &mvport->port_sata_sstatus); 3010 if (rv != 0) { 3011 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 3012 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3013 goto fail0; 3014 } 3015 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 3016 &mvport->port_sata_serror); 3017 if (rv != 0) { 3018 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 3019 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3020 goto fail0; 3021 } 3022 if (sc->sc_rev == gen1) 3023 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 3024 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 3025 else 3026 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3027 SATA_SC, 4, &mvport->port_sata_scontrol); 3028 if (rv != 0) { 3029 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 3030 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 3031 goto fail0; 3032 } 3033 mvport->port_dmat = sc->sc_dmat; 3034 mvhc->hc_ports[port] = mvport; 3035 3036 channel = mvhc->hc * sc->sc_port + port; 3037 chp = &mvport->port_ata_channel; 3038 chp->ch_channel = channel; 3039 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 3040 chp->ch_queue = ata_queue_alloc(MVSATA_EDMAQ_LEN); 3041 sc->sc_ata_channels[channel] = chp; 3042 3043 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 3044 if (rv != 0) 3045 goto fail0; 3046 3047 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 3048 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 3049 if (rv != 0) { 3050 aprint_error( 3051 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 3052 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3053 goto fail0; 3054 } 3055 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 3056 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 3057 if (rv != 0) { 3058 aprint_error( 3059 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 3060 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3061 goto fail1; 3062 } 3063 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 3064 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 3065 if (rv != 0) { 3066 aprint_error( 3067 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 3068 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 3069 goto fail2; 3070 } 3071 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 3072 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 3073 MVSATA_MAX_SEGS, MAXPHYS, 0, BUS_DMA_NOWAIT, 3074 &mvport->port_reqtbl[i].data_dmamap); 3075 if (rv != 0) { 3076 aprint_error("%s:%d:%d:" 3077 " EDMA data map(%d) create failed: error=%d\n", 3078 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 3079 rv); 3080 goto fail3; 3081 } 3082 } 3083 3084 return 0; 3085 3086 fail3: 3087 for (i--; i >= 0; i--) 3088 bus_dmamap_destroy(mvport->port_dmat, 3089 mvport->port_reqtbl[i].data_dmamap); 3090 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 3091 fail2: 3092 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 3093 fail1: 3094 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 3095 fail0: 3096 return rv; 3097 } 3098 3099 static int 3100 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 3101 { 3102 int hc, port, rv, i; 3103 3104 hc = mvport->port_hc->hc; 3105 port = mvport->port; 3106 3107 /* Create subregion for Shadow Registers Map */ 3108 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3109 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 3110 if (rv != 0) { 3111 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 3112 device_xname(MVSATA_DEV2(mvport)), hc, port); 3113 return rv; 3114 } 3115 wdr->cmd_iot = mvport->port_iot; 3116 3117 /* Once create subregion for each command registers */ 3118 for (i = 0; i < WDC_NREG; i++) { 3119 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3120 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 3121 if (rv != 0) { 3122 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3123 device_xname(MVSATA_DEV2(mvport)), hc, port); 3124 return rv; 3125 } 3126 } 3127 /* Create subregion for Alternate Status register */ 3128 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 3129 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 3130 if (rv != 0) { 3131 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 3132 device_xname(MVSATA_DEV2(mvport)), hc, port); 3133 return rv; 3134 } 3135 wdr->ctl_iot = mvport->port_iot; 3136 3137 wdc_init_shadow_regs(wdr); 3138 3139 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3140 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 3141 if (rv != 0) { 3142 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 3143 device_xname(MVSATA_DEV2(mvport)), hc, port); 3144 return rv; 3145 } 3146 wdr->sata_iot = mvport->port_iot; 3147 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3148 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 3149 if (rv != 0) { 3150 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 3151 device_xname(MVSATA_DEV2(mvport)), hc, port); 3152 return rv; 3153 } 3154 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3155 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 3156 if (rv != 0) { 3157 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 3158 device_xname(MVSATA_DEV2(mvport)), hc, port); 3159 return rv; 3160 } 3161 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 3162 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 3163 if (rv != 0) { 3164 aprint_error("%s:%d:%d: couldn't subregion SError\n", 3165 device_xname(MVSATA_DEV2(mvport)), hc, port); 3166 return rv; 3167 } 3168 3169 return 0; 3170 } 3171 3172 3173 #ifndef MVSATA_WITHOUTDMA 3174 static void * 3175 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3176 bus_dmamap_t *dmamap, size_t size, int write) 3177 { 3178 bus_dma_segment_t seg; 3179 int nseg, rv; 3180 void *kva; 3181 3182 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 3183 BUS_DMA_NOWAIT); 3184 if (rv != 0) { 3185 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 3186 device_xname(MVSATA_DEV2(mvport)), 3187 mvport->port_hc->hc, mvport->port, rv); 3188 goto fail; 3189 } 3190 3191 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 3192 if (rv != 0) { 3193 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 3194 device_xname(MVSATA_DEV2(mvport)), 3195 mvport->port_hc->hc, mvport->port, rv); 3196 goto free; 3197 } 3198 3199 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 3200 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 3201 if (rv != 0) { 3202 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 3203 device_xname(MVSATA_DEV2(mvport)), 3204 mvport->port_hc->hc, mvport->port, rv); 3205 goto unmap; 3206 } 3207 3208 if (!write) 3209 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 3210 3211 return kva; 3212 3213 unmap: 3214 bus_dmamem_unmap(dmat, kva, size); 3215 free: 3216 bus_dmamem_free(dmat, &seg, nseg); 3217 fail: 3218 return NULL; 3219 } 3220 3221 /* ARGSUSED */ 3222 static void 3223 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 3224 bus_dmamap_t dmamap, void *kva) 3225 { 3226 3227 bus_dmamap_unload(dmat, dmamap); 3228 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3229 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3230 } 3231 3232 static int 3233 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3234 size_t datalen, int flags) 3235 { 3236 int rv, lop, sop; 3237 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3238 3239 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3240 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3241 3242 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3243 NULL, BUS_DMA_NOWAIT | lop); 3244 if (rv) { 3245 aprint_error("%s:%d:%d: buffer load failed: error=%d\n", 3246 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3247 mvport->port, rv); 3248 return rv; 3249 } 3250 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3251 data_dmamap->dm_mapsize, sop); 3252 3253 return 0; 3254 } 3255 3256 static inline void 3257 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3258 { 3259 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3260 3261 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3262 data_dmamap->dm_mapsize, 3263 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3264 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3265 } 3266 #endif 3267 3268 static void 3269 mvsata_hreset_port(struct mvsata_port *mvport) 3270 { 3271 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3272 3273 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3274 3275 delay(25); /* allow reset propagation */ 3276 3277 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3278 3279 mvport->_fix_phy_param._fix_phy(mvport); 3280 3281 if (sc->sc_gen == gen1) 3282 delay(1000); 3283 } 3284 3285 static void 3286 mvsata_reset_port(struct mvsata_port *mvport) 3287 { 3288 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3289 3290 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3291 3292 mvsata_hreset_port(mvport); 3293 3294 if (device_is_a(parent, "pci")) 3295 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3296 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3297 else /* SoC */ 3298 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3299 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3300 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3301 MVSATA_EDMA_WRITE_4(mvport, SATA_SEIM, 0x019c0000); 3302 MVSATA_EDMA_WRITE_4(mvport, SATA_SE, ~0); 3303 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3304 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3305 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3306 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3307 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3308 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3309 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3310 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3311 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3312 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3313 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3314 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3315 } 3316 3317 static void 3318 mvsata_reset_hc(struct mvsata_hc *mvhc) 3319 { 3320 #if 0 3321 uint32_t val; 3322 #endif 3323 3324 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3325 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3326 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3327 3328 #if 0 /* XXXX needs? */ 3329 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3330 3331 /* 3332 * Keep the SS during power on and the reference clock bits (reset 3333 * sample) 3334 */ 3335 val = MVSATA_HC_READ_4(mvhc, 0x020); 3336 val &= 0x1c1c1c1c; 3337 val |= 0x03030303; 3338 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3339 #endif 3340 } 3341 3342 static uint32_t 3343 mvsata_softreset(struct mvsata_port *mvport, int flags) 3344 { 3345 struct ata_channel *chp = &mvport->port_ata_channel; 3346 uint32_t sig0 = ~0; 3347 int timeout; 3348 uint8_t st0; 3349 3350 ata_channel_lock_owned(chp); 3351 3352 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 3353 delay(10); 3354 (void) MVSATA_WDC_READ_1(mvport, SRB_FE); 3355 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS | WDCTL_4BIT); 3356 delay(10); 3357 3358 /* wait for BSY to deassert */ 3359 for (timeout = 0; timeout < WDC_RESET_WAIT / 10; timeout++) { 3360 st0 = MVSATA_WDC_READ_1(mvport, SRB_CS); 3361 3362 if ((st0 & WDCS_BSY) == 0) { 3363 sig0 = MVSATA_WDC_READ_1(mvport, SRB_SC) << 0; 3364 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAL) << 8; 3365 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 16; 3366 sig0 |= MVSATA_WDC_READ_1(mvport, SRB_LBAH) << 24; 3367 goto out; 3368 } 3369 ata_delay(chp, 10, "atarst", flags); 3370 } 3371 3372 aprint_error("%s:%d:%d: %s: timeout\n", 3373 device_xname(MVSATA_DEV2(mvport)), 3374 mvport->port_hc->hc, mvport->port, __func__); 3375 3376 out: 3377 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 3378 return sig0; 3379 } 3380 3381 #ifndef MVSATA_WITHOUTDMA 3382 static void 3383 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3384 { 3385 const bus_addr_t crpb_addr = 3386 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3387 const uint32_t crpb_addr_mask = 3388 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3389 3390 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3391 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3392 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3393 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3394 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3395 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3396 } 3397 3398 static inline void 3399 mvsata_edma_enable(struct mvsata_port *mvport) 3400 { 3401 3402 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3403 } 3404 3405 static void 3406 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int wflags) 3407 { 3408 struct ata_channel *chp = &mvport->port_ata_channel; 3409 uint32_t command; 3410 int t; 3411 3412 ata_channel_lock_owned(chp); 3413 3414 /* The disable bit (eDsEDMA) is self negated. */ 3415 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3416 3417 timeout = mstohz(timeout + hztoms(1) - 1); 3418 3419 for (t = 0; ; ++t) { 3420 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3421 if (!(command & EDMA_CMD_EENEDMA)) 3422 return; 3423 if (t >= timeout) 3424 break; 3425 ata_delay(chp, hztoms(1), "mvsata_edma2", wflags); 3426 } 3427 3428 aprint_error("%s:%d:%d: unable to disable EDMA\n", 3429 device_xname(MVSATA_DEV2(mvport)), 3430 mvport->port_hc->hc, mvport->port); 3431 } 3432 3433 /* 3434 * Set EDMA registers according to mode. 3435 * ex. NCQ/TCQ(queued)/non queued. 3436 */ 3437 static void 3438 mvsata_edma_config(struct mvsata_port *mvport, enum mvsata_edmamode mode) 3439 { 3440 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3441 uint32_t reg; 3442 3443 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3444 reg |= EDMA_CFG_RESERVED; 3445 3446 if (mode == ncq) { 3447 if (sc->sc_gen == gen1) { 3448 aprint_error_dev(MVSATA_DEV2(mvport), 3449 "GenI not support NCQ\n"); 3450 return; 3451 } else if (sc->sc_gen == gen2) 3452 reg |= EDMA_CFG_EDEVERR; 3453 reg |= EDMA_CFG_ESATANATVCMDQUE; 3454 } else if (mode == queued) { 3455 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3456 reg |= EDMA_CFG_EQUE; 3457 } else 3458 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3459 3460 if (sc->sc_gen == gen1) 3461 reg |= EDMA_CFG_ERDBSZ; 3462 else if (sc->sc_gen == gen2) 3463 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3464 else if (sc->sc_gen == gen2e) { 3465 device_t parent = device_parent(MVSATA_DEV(sc)); 3466 3467 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3468 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3469 3470 if (device_is_a(parent, "pci")) 3471 reg |= ( 3472 #if NATAPIBUS > 0 3473 EDMA_CFG_EEARLYCOMPLETIONEN | 3474 #endif 3475 EDMA_CFG_ECUTTHROUGHEN | 3476 EDMA_CFG_EWRBUFFERLEN | 3477 EDMA_CFG_ERDBSZEXT); 3478 } 3479 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3480 3481 reg = ( 3482 EDMA_IE_EIORDYERR | 3483 EDMA_IE_ETRANSINT | 3484 EDMA_IE_EDEVCON | 3485 EDMA_IE_EDEVDIS); 3486 if (sc->sc_gen != gen1) 3487 reg |= ( 3488 EDMA_IE_TRANSPROTERR | 3489 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3490 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3491 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3492 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3493 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3494 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3495 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3496 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3497 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3498 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3499 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3500 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3501 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3502 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3503 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3504 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3505 EDMA_IE_ESELFDIS); 3506 3507 if (mode == ncq) 3508 reg |= EDMA_IE_EDEVERR; 3509 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3510 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3511 reg &= ~EDMA_IE_EDEVERR; 3512 if (mode != ncq) 3513 reg |= EDMA_IE_EDEVERR; 3514 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3515 if (sc->sc_gen == gen2e) { 3516 /* 3517 * Clear FISWait4HostRdyEn[0] and [2]. 3518 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3519 * [2]: SDB FIS is received with <ERR> bit set to 1. 3520 */ 3521 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3522 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3523 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3524 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3525 } 3526 3527 mvport->port_edmamode_curr = mode; 3528 } 3529 3530 3531 /* 3532 * Generation dependent functions 3533 */ 3534 3535 static void 3536 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, 3537 struct ata_xfer *xfer) 3538 { 3539 struct crqb *crqb; 3540 bus_addr_t eprd_addr; 3541 daddr_t blkno; 3542 uint32_t rw; 3543 uint8_t cmd, head; 3544 int i; 3545 struct ata_bio *ata_bio = &xfer->c_bio; 3546 3547 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3548 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3549 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3550 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3551 if (ata_bio->flags & (ATA_LBA|ATA_LBA48)) { 3552 head = WDSD_LBA; 3553 } else { 3554 head = 0; 3555 } 3556 blkno = ata_bio->blkno; 3557 if (ata_bio->flags & ATA_LBA48) 3558 cmd = atacmd_to48(cmd); 3559 else { 3560 head |= ((ata_bio->blkno >> 24) & 0xf); 3561 blkno &= 0xffffff; 3562 } 3563 crqb = &mvport->port_crqb->crqb + erqqip; 3564 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3565 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3566 crqb->ctrlflg = 3567 htole16(rw | CRQB_CHOSTQUETAG(xfer->c_slot) | 3568 CRQB_CPMPORT(xfer->c_drive)); 3569 i = 0; 3570 if (mvport->port_edmamode_curr == dma) { 3571 if (ata_bio->flags & ATA_LBA48) 3572 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3573 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3574 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3575 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3576 } else { /* ncq/queued */ 3577 3578 /* 3579 * XXXX: Oops, ata command is not correct. And, atabus layer 3580 * has not been supported yet now. 3581 * Queued DMA read/write. 3582 * read/write FPDMAQueued. 3583 */ 3584 3585 if (ata_bio->flags & ATA_LBA48) 3586 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3587 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3588 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3589 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3590 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3591 CRQB_ATACOMMAND_SECTORCOUNT, xfer->c_slot << 3)); 3592 } 3593 if (ata_bio->flags & ATA_LBA48) { 3594 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3595 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3596 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3597 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3598 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3599 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3600 } 3601 crqb->atacommand[i++] = 3602 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3603 crqb->atacommand[i++] = 3604 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3605 crqb->atacommand[i++] = 3606 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3607 crqb->atacommand[i++] = 3608 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3609 crqb->atacommand[i++] = htole16( 3610 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3611 CRQB_ATACOMMAND_LAST); 3612 } 3613 #endif 3614 3615 static uint32_t 3616 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3617 { 3618 struct mvsata_hc *hc = mvport->port_hc; 3619 uint32_t reg; 3620 3621 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3622 /* 3623 * [12:11] : pre 3624 * [7:5] : amps 3625 */ 3626 return reg & 0x000018e0; 3627 } 3628 3629 static void 3630 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3631 { 3632 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3633 struct mvsata_hc *mvhc = mvport->port_hc; 3634 uint32_t reg; 3635 int port = mvport->port, fix_apm_sq = 0; 3636 3637 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3638 if (sc->sc_rev == 0x01) 3639 fix_apm_sq = 1; 3640 } else { 3641 if (sc->sc_rev == 0x00) 3642 fix_apm_sq = 1; 3643 } 3644 3645 if (fix_apm_sq) { 3646 /* 3647 * Disable auto-power management 3648 * 88SX50xx FEr SATA#12 3649 */ 3650 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3651 reg |= (1 << 19); 3652 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3653 3654 /* 3655 * Fix squelch threshold 3656 * 88SX50xx FEr SATA#9 3657 */ 3658 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3659 reg &= ~0x3; 3660 reg |= 0x1; 3661 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3662 } 3663 3664 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3665 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3666 reg &= ~0x000018e0; /* pre and amps mask */ 3667 reg |= mvport->_fix_phy_param.pre_amps; 3668 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3669 } 3670 3671 static void 3672 mvsata_devconn_gen1(struct mvsata_port *mvport) 3673 { 3674 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3675 3676 /* Fix for 88SX50xx FEr SATA#2 */ 3677 mvport->_fix_phy_param._fix_phy(mvport); 3678 3679 /* If disk is connected, then enable the activity LED */ 3680 if (sc->sc_rev == 0x03) { 3681 /* XXXXX */ 3682 } 3683 } 3684 3685 static uint32_t 3686 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3687 { 3688 uint32_t reg; 3689 3690 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3691 /* 3692 * [10:8] : amps 3693 * [7:5] : pre 3694 */ 3695 return reg & 0x000007e0; 3696 } 3697 3698 static void 3699 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3700 { 3701 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3702 uint32_t reg; 3703 3704 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3705 sc->sc_gen == gen2e) { 3706 /* 3707 * Fix for 3708 * 88SX60X1 FEr SATA #23 3709 * 88SX6042/88SX7042 FEr SATA #23 3710 * 88F5182 FEr #SATA-S13 3711 * 88F5082 FEr #SATA-S13 3712 */ 3713 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3714 reg &= ~(1 << 16); 3715 reg |= (1 << 31); 3716 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3717 3718 delay(200); 3719 3720 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3721 reg &= ~((1 << 16) | (1 << 31)); 3722 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3723 3724 delay(200); 3725 } 3726 3727 /* Fix values in PHY Mode 3 Register.*/ 3728 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3729 reg &= ~0x7F900000; 3730 reg |= 0x2A800000; 3731 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3732 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3733 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3734 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3735 reg &= ~0x0000001c; 3736 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3737 3738 /* 3739 * Fix values in PHY Mode 4 Register. 3740 * 88SX60x1 FEr SATA#10 3741 * 88F5182 GL #SATA-S10 3742 * 88F5082 GL #SATA-S10 3743 */ 3744 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3745 sc->sc_gen == gen2e) { 3746 uint32_t tmp = 0; 3747 3748 /* 88SX60x1 FEr SATA #13 */ 3749 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3750 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3751 3752 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3753 reg |= (1 << 0); 3754 reg &= ~(1 << 1); 3755 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3756 if (sc->sc_gen == gen2e) { 3757 reg &= ~0x5de3fffc; 3758 reg |= (1 << 2); 3759 } 3760 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3761 3762 /* 88SX60x1 FEr SATA #13 */ 3763 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3764 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3765 } 3766 3767 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3768 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3769 reg &= ~0x000007e0; /* pre and amps mask */ 3770 reg |= mvport->_fix_phy_param.pre_amps; 3771 reg &= ~(1 << 16); 3772 if (sc->sc_gen == gen2e) { 3773 /* 3774 * according to mvSata 3.6.1, some IIE values are fixed. 3775 * some reserved fields must be written with fixed values. 3776 */ 3777 reg &= ~0xC30FF01F; 3778 reg |= 0x0000900F; 3779 } 3780 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3781 } 3782 3783 #ifndef MVSATA_WITHOUTDMA 3784 static void 3785 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, 3786 struct ata_xfer *xfer) 3787 { 3788 struct crqb_gen2e *crqb; 3789 bus_addr_t eprd_addr; 3790 uint32_t ctrlflg, rw; 3791 uint8_t fis[RHD_FISLEN]; 3792 3793 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3794 mvport->port_reqtbl[xfer->c_slot].eprd_offset; 3795 rw = (xfer->c_bio.flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3796 ctrlflg = (rw | CRQB_CDEVICEQUETAG(xfer->c_slot) | 3797 CRQB_CPMPORT(xfer->c_drive) | 3798 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(xfer->c_slot)); 3799 3800 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3801 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3802 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3803 crqb->ctrlflg = htole32(ctrlflg); 3804 3805 satafis_rhd_construct_bio(xfer, fis); 3806 3807 crqb->atacommand[0] = 0; 3808 crqb->atacommand[1] = 0; 3809 /* copy over the ATA command part of the fis */ 3810 memcpy(&crqb->atacommand[2], &fis[rhd_command], 3811 MIN(sizeof(crqb->atacommand) - 2, RHD_FISLEN - rhd_command)); 3812 } 3813 3814 #ifdef MVSATA_DEBUG 3815 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3816 do { \ 3817 int _i; \ 3818 u_char *_p = (p); \ 3819 \ 3820 printf(#type "(%d)", (n)); \ 3821 for (_i = 0; _i < (size); _i++, _p++) { \ 3822 if (_i % 16 == 0) \ 3823 printf("\n "); \ 3824 printf(" %02x", *_p); \ 3825 } \ 3826 printf("\n"); \ 3827 } while (0 /* CONSTCOND */) 3828 3829 static void 3830 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3831 { 3832 3833 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3834 n, (u_char *)(mvport->port_crqb + n)); 3835 } 3836 3837 static void 3838 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3839 { 3840 3841 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3842 n, (u_char *)(mvport->port_crpb + n)); 3843 } 3844 3845 static void 3846 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3847 { 3848 struct eprd *eprd; 3849 int i = 0; 3850 3851 eprd = mvport->port_reqtbl[n].eprd; 3852 while (1 /*CONSTCOND*/) { 3853 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3854 i, (u_char *)eprd); 3855 if (eprd->eot & EPRD_EOT) 3856 break; 3857 eprd++; 3858 i++; 3859 } 3860 } 3861 #endif 3862 #endif 3863
Indexes created Mon Sep 22 13:09:51 GMT 2025