mvsata.c revision 1.9
1 /* $NetBSD: mvsata.c,v 1.9 2011/08/14 16:50:49 jakllsch Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata.c,v 1.9 2011/08/14 16:50:49 jakllsch Exp $"); 30 31 #include "opt_mvsata.h" 32 33 /* ATAPI implementation not finished. Also don't work shadow registers? */ 34 //#include "atapibus.h" 35 36 #include <sys/param.h> 37 #if NATAPIBUS > 0 38 #include <sys/buf.h> 39 #endif 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/disklabel.h> 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 49 #include <machine/vmparam.h> 50 51 #include <dev/ata/atareg.h> 52 #include <dev/ata/atavar.h> 53 #include <dev/ic/wdcvar.h> 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 57 #if NATAPIBUS > 0 58 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 59 #endif 60 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ic/mvsatareg.h> 64 #include <dev/ic/mvsatavar.h> 65 66 67 #define MVSATA_DEV(sc) ((sc)->sc_wdcdev.sc_atac.atac_dev) 68 #define MVSATA_DEV2(mvport) ((mvport)->port_ata_channel.ch_atac->atac_dev) 69 70 #define MVSATA_HC_READ_4(hc, reg) \ 71 bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg)) 72 #define MVSATA_HC_WRITE_4(hc, reg, val) \ 73 bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val)) 74 #define MVSATA_EDMA_READ_4(mvport, reg) \ 75 bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg)) 76 #define MVSATA_EDMA_WRITE_4(mvport, reg, val) \ 77 bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 78 #define MVSATA_WDC_READ_2(mvport, reg) \ 79 bus_space_read_2((mvport)->port_iot, (mvport)->port_ioh, (reg)) 80 #define MVSATA_WDC_READ_1(mvport, reg) \ 81 bus_space_read_1((mvport)->port_iot, (mvport)->port_ioh, (reg)) 82 #define MVSATA_WDC_WRITE_2(mvport, reg, val) \ 83 bus_space_write_2((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 84 #define MVSATA_WDC_WRITE_1(mvport, reg, val) \ 85 bus_space_write_1((mvport)->port_iot, (mvport)->port_ioh, (reg), (val)) 86 87 #ifdef MVSATA_DEBUG 88 #define DPRINTF(x) if (mvsata_debug) printf x 89 #define DPRINTFN(n,x) if (mvsata_debug >= (n)) printf x 90 int mvsata_debug = 3; 91 #else 92 #define DPRINTF(x) 93 #define DPRINTFN(n,x) 94 #endif 95 96 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 97 #define ATAPI_DELAY 10 /* 10 ms, this is used only before 98 sending a cmd */ 99 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATURE cmds */ 100 101 #define MVSATA_EPRD_MAX_SIZE (sizeof(struct eprd) * (MAXPHYS / PAGE_SIZE)) 102 103 104 #ifndef MVSATA_WITHOUTDMA 105 static int mvsata_bio(struct ata_drive_datas *, struct ata_bio *); 106 static void mvsata_reset_drive(struct ata_drive_datas *, int); 107 static void mvsata_reset_channel(struct ata_channel *, int); 108 static int mvsata_exec_command(struct ata_drive_datas *, struct ata_command *); 109 static int mvsata_addref(struct ata_drive_datas *); 110 static void mvsata_delref(struct ata_drive_datas *); 111 static void mvsata_killpending(struct ata_drive_datas *); 112 113 #if NATAPIBUS > 0 114 static void mvsata_atapibus_attach(struct atabus_softc *); 115 static void mvsata_atapi_scsipi_request(struct scsipi_channel *, 116 scsipi_adapter_req_t, void *); 117 static void mvsata_atapi_minphys(struct buf *); 118 static void mvsata_atapi_probe_device(struct atapibus_softc *, int); 119 static void mvsata_atapi_kill_pending(struct scsipi_periph *); 120 #endif 121 #endif 122 123 static void mvsata_setup_channel(struct ata_channel *); 124 125 #ifndef MVSATA_WITHOUTDMA 126 static void mvsata_bio_start(struct ata_channel *, struct ata_xfer *); 127 static int mvsata_bio_intr(struct ata_channel *, struct ata_xfer *, int); 128 static void mvsata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 129 static void mvsata_bio_done(struct ata_channel *, struct ata_xfer *); 130 static int mvsata_bio_ready(struct mvsata_port *, struct ata_bio *, int, 131 int); 132 static void mvsata_wdc_cmd_start(struct ata_channel *, struct ata_xfer *); 133 static int mvsata_wdc_cmd_intr(struct ata_channel *, struct ata_xfer *, int); 134 static void mvsata_wdc_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, 135 int); 136 static void mvsata_wdc_cmd_done(struct ata_channel *, struct ata_xfer *); 137 static void mvsata_wdc_cmd_done_end(struct ata_channel *, struct ata_xfer *); 138 #if NATAPIBUS > 0 139 static void mvsata_atapi_start(struct ata_channel *, struct ata_xfer *); 140 static int mvsata_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 141 static void mvsata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, 142 int); 143 static void mvsata_atapi_reset(struct ata_channel *, struct ata_xfer *); 144 static void mvsata_atapi_phase_complete(struct ata_xfer *); 145 static void mvsata_atapi_done(struct ata_channel *, struct ata_xfer *); 146 static void mvsata_atapi_polldsc(void *); 147 #endif 148 149 static int mvsata_edma_enqueue(struct mvsata_port *, struct ata_bio *, void *); 150 static int mvsata_edma_handle(struct mvsata_port *, struct ata_xfer *); 151 static int mvsata_edma_wait(struct mvsata_port *, struct ata_xfer *, int); 152 static void mvsata_edma_timeout(void *); 153 static void mvsata_edma_rqq_remove(struct mvsata_port *, struct ata_xfer *); 154 #if NATAPIBUS > 0 155 static int mvsata_bdma_init(struct mvsata_port *, struct scsipi_xfer *, void *); 156 static void mvsata_bdma_start(struct mvsata_port *); 157 #endif 158 #endif 159 160 static int mvsata_port_init(struct mvsata_hc *, int); 161 static int mvsata_wdc_reg_init(struct mvsata_port *, struct wdc_regs *); 162 #ifndef MVSATA_WITHOUTDMA 163 static inline void mvsata_quetag_init(struct mvsata_port *); 164 static inline int mvsata_quetag_get(struct mvsata_port *); 165 static inline void mvsata_quetag_put(struct mvsata_port *, int); 166 static void *mvsata_edma_resource_prepare(struct mvsata_port *, bus_dma_tag_t, 167 bus_dmamap_t *, size_t, int); 168 static void mvsata_edma_resource_purge(struct mvsata_port *, bus_dma_tag_t, 169 bus_dmamap_t, void *); 170 static int mvsata_dma_bufload(struct mvsata_port *, int, void *, size_t, int); 171 static inline void mvsata_dma_bufunload(struct mvsata_port *, int, int); 172 #endif 173 174 static void mvsata_hreset_port(struct mvsata_port *); 175 static void mvsata_reset_port(struct mvsata_port *); 176 static void mvsata_reset_hc(struct mvsata_hc *); 177 #ifndef MVSATA_WITHOUTDMA 178 static void mvsata_softreset(struct mvsata_port *, int); 179 static void mvsata_edma_reset_qptr(struct mvsata_port *); 180 static inline void mvsata_edma_enable(struct mvsata_port *); 181 static int mvsata_edma_disable(struct mvsata_port *, int, int); 182 static void mvsata_edma_config(struct mvsata_port *, int); 183 184 static void mvsata_edma_setup_crqb(struct mvsata_port *, int, int, 185 struct ata_bio *); 186 #endif 187 static uint32_t mvsata_read_preamps_gen1(struct mvsata_port *); 188 static void mvsata_fix_phy_gen1(struct mvsata_port *); 189 static void mvsata_devconn_gen1(struct mvsata_port *); 190 191 static uint32_t mvsata_read_preamps_gen2(struct mvsata_port *); 192 static void mvsata_fix_phy_gen2(struct mvsata_port *); 193 #ifndef MVSATA_WITHOUTDMA 194 static void mvsata_edma_setup_crqb_gen2e(struct mvsata_port *, int, int, 195 struct ata_bio *); 196 197 #ifdef MVSATA_DEBUG 198 static void mvsata_print_crqb(struct mvsata_port *, int); 199 static void mvsata_print_crpb(struct mvsata_port *, int); 200 static void mvsata_print_eprd(struct mvsata_port *, int); 201 #endif 202 203 204 struct ata_bustype mvsata_ata_bustype = { 205 SCSIPI_BUSTYPE_ATA, 206 mvsata_bio, 207 mvsata_reset_drive, 208 mvsata_reset_channel, 209 mvsata_exec_command, 210 ata_get_params, 211 mvsata_addref, 212 mvsata_delref, 213 mvsata_killpending 214 }; 215 216 #if NATAPIBUS > 0 217 static const struct scsipi_bustype mvsata_atapi_bustype = { 218 SCSIPI_BUSTYPE_ATAPI, 219 atapi_scsipi_cmd, 220 atapi_interpret_sense, 221 atapi_print_addr, 222 mvsata_atapi_kill_pending, 223 }; 224 #endif /* NATAPIBUS */ 225 #endif 226 227 228 int 229 mvsata_attach(struct mvsata_softc *sc, struct mvsata_product *product, 230 int (*mvsata_sreset)(struct mvsata_softc *), 231 int (*mvsata_misc_reset)(struct mvsata_softc *), 232 int read_pre_amps) 233 { 234 struct mvsata_hc *mvhc; 235 struct mvsata_port *mvport; 236 uint32_t (*read_preamps)(struct mvsata_port *) = NULL; 237 void (*_fix_phy)(struct mvsata_port *) = NULL; 238 #ifndef MVSATA_WITHOUTDMA 239 void (*edma_setup_crqb) 240 (struct mvsata_port *, int, int, struct ata_bio *) = NULL; 241 #endif 242 int hc, port, channel; 243 244 aprint_normal_dev(MVSATA_DEV(sc), "Gen%s, %dhc, %dport/hc\n", 245 (product->generation == gen1) ? "I" : 246 ((product->generation == gen2) ? "II" : "IIe"), 247 product->hc, product->port); 248 249 250 switch (product->generation) { 251 case gen1: 252 mvsata_sreset = NULL; 253 read_pre_amps = 1; /* MUST */ 254 read_preamps = mvsata_read_preamps_gen1; 255 _fix_phy = mvsata_fix_phy_gen1; 256 #ifndef MVSATA_WITHOUTDMA 257 edma_setup_crqb = mvsata_edma_setup_crqb; 258 #endif 259 break; 260 261 case gen2: 262 read_preamps = mvsata_read_preamps_gen2; 263 _fix_phy = mvsata_fix_phy_gen2; 264 #ifndef MVSATA_WITHOUTDMA 265 edma_setup_crqb = mvsata_edma_setup_crqb; 266 #endif 267 break; 268 269 case gen2e: 270 read_preamps = mvsata_read_preamps_gen2; 271 _fix_phy = mvsata_fix_phy_gen2; 272 #ifndef MVSATA_WITHOUTDMA 273 edma_setup_crqb = mvsata_edma_setup_crqb_gen2e; 274 #endif 275 break; 276 } 277 278 sc->sc_gen = product->generation; 279 sc->sc_hc = product->hc; 280 sc->sc_port = product->port; 281 sc->sc_flags = product->flags; 282 283 #ifdef MVSATA_WITHOUTDMA 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 285 #else 286 sc->sc_edma_setup_crqb = edma_setup_crqb; 287 sc->sc_wdcdev.sc_atac.atac_cap |= 288 (ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA); 289 #endif 290 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 291 #ifdef MVSATA_WITHOUTDMA 292 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 293 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 294 #else 295 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 297 #endif 298 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_ata_channels; 299 sc->sc_wdcdev.sc_atac.atac_nchannels = sc->sc_hc * sc->sc_port; 300 #ifndef MVSATA_WITHOUTDMA 301 sc->sc_wdcdev.sc_atac.atac_bustype_ata = &mvsata_ata_bustype; 302 #if NATAPIBUS > 0 303 sc->sc_wdcdev.sc_atac.atac_atapibus_attach = mvsata_atapibus_attach; 304 #endif 305 #endif 306 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 307 sc->sc_wdcdev.sc_atac.atac_set_modes = mvsata_setup_channel; 308 309 sc->sc_wdc_regs = 310 malloc(sizeof(struct wdc_regs) * product->hc * product->port, 311 M_DEVBUF, M_NOWAIT); 312 if (sc->sc_wdc_regs == NULL) { 313 aprint_error_dev(MVSATA_DEV(sc), 314 "can't allocate wdc regs memory\n"); 315 return ENOMEM; 316 } 317 sc->sc_wdcdev.regs = sc->sc_wdc_regs; 318 319 for (hc = 0; hc < sc->sc_hc; hc++) { 320 mvhc = &sc->sc_hcs[hc]; 321 mvhc->hc = hc; 322 mvhc->hc_sc = sc; 323 mvhc->hc_iot = sc->sc_iot; 324 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 325 hc * SATAHC_REGISTER_SIZE, SATAHC_REGISTER_SIZE, 326 &mvhc->hc_ioh)) { 327 aprint_error_dev(MVSATA_DEV(sc), 328 "can't subregion SATAHC %d registers\n", hc); 329 continue; 330 } 331 332 for (port = 0; port < sc->sc_port; port++) 333 if (mvsata_port_init(mvhc, port) == 0) { 334 int pre_amps; 335 336 mvport = mvhc->hc_ports[port]; 337 pre_amps = read_pre_amps ? 338 read_preamps(mvport) : 0x00000720; 339 mvport->_fix_phy_param.pre_amps = pre_amps; 340 mvport->_fix_phy_param._fix_phy = _fix_phy; 341 342 if (!mvsata_sreset) 343 mvsata_reset_port(mvport); 344 } 345 346 if (!mvsata_sreset) 347 mvsata_reset_hc(mvhc); 348 } 349 if (mvsata_sreset) 350 mvsata_sreset(sc); 351 352 if (mvsata_misc_reset) 353 mvsata_misc_reset(sc); 354 355 for (hc = 0; hc < sc->sc_hc; hc++) 356 for (port = 0; port < sc->sc_port; port++) { 357 mvport = sc->sc_hcs[hc].hc_ports[port]; 358 if (mvport == NULL) 359 continue; 360 if (mvsata_sreset) 361 mvport->_fix_phy_param._fix_phy(mvport); 362 } 363 for (channel = 0; channel < sc->sc_hc * sc->sc_port; channel++) 364 wdcattach(sc->sc_ata_channels[channel]); 365 366 return 0; 367 } 368 369 int 370 mvsata_intr(struct mvsata_hc *mvhc) 371 { 372 struct mvsata_softc *sc = mvhc->hc_sc; 373 struct mvsata_port *mvport; 374 uint32_t cause; 375 int port, handled = 0; 376 377 cause = MVSATA_HC_READ_4(mvhc, SATAHC_IC); 378 379 DPRINTFN(3, ("%s:%d: mvsata_intr: cause=0x%08x\n", 380 device_xname(MVSATA_DEV(sc)), mvhc->hc, cause)); 381 382 if (cause & SATAHC_IC_SAINTCOAL) 383 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, ~SATAHC_IC_SAINTCOAL); 384 cause &= ~SATAHC_IC_SAINTCOAL; 385 for (port = 0; port < sc->sc_port; port++) { 386 mvport = mvhc->hc_ports[port]; 387 388 if (cause & SATAHC_IC_DONE(port)) { 389 #ifndef MVSATA_WITHOUTDMA 390 handled = mvsata_edma_handle(mvport, NULL); 391 #endif 392 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 393 ~SATAHC_IC_DONE(port)); 394 } 395 396 if (cause & SATAHC_IC_SADEVINTERRUPT(port)) { 397 wdcintr(&mvport->port_ata_channel); 398 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 399 ~SATAHC_IC_SADEVINTERRUPT(port)); 400 handled = 1; 401 } 402 } 403 404 return handled; 405 } 406 407 int 408 mvsata_error(struct mvsata_port *mvport) 409 { 410 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 411 uint32_t cause; 412 int handled = 0; 413 414 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 415 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 416 417 DPRINTFN(3, ("%s:%d:%d:" 418 " mvsata_error: cause=0x%08x, mask=0x%08x, status=0x%08x\n", 419 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 420 mvport->port, cause, MVSATA_EDMA_READ_4(mvport, EDMA_IEM), 421 MVSATA_EDMA_READ_4(mvport, EDMA_S))); 422 423 cause &= MVSATA_EDMA_READ_4(mvport, EDMA_IEM); 424 if (!cause) 425 return 0; 426 427 /* If PM connected, connect/disconnect interrupts storm could happen */ 428 if (MVSATA_EDMA_READ_4(mvport, EDMA_IEC) & 429 (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) 430 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 431 delay(20 * 1000); 432 cause = MVSATA_EDMA_READ_4(mvport, EDMA_IEC); 433 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, ~cause); 434 } 435 436 if (cause & EDMA_IE_EDEVDIS) 437 aprint_normal("%s:%d:%d: device disconnect\n", 438 device_xname(MVSATA_DEV2(mvport)), 439 mvport->port_hc->hc, mvport->port); 440 if (cause & EDMA_IE_EDEVCON) { 441 if (sc->sc_gen == gen1) 442 mvsata_devconn_gen1(mvport); 443 444 DPRINTFN(3, (" device connected\n")); 445 handled = 1; 446 } 447 #ifndef MVSATA_WITHOUTDMA 448 if ((sc->sc_gen == gen1 && cause & EDMA_IE_ETRANSINT) || 449 (sc->sc_gen != gen1 && cause & EDMA_IE_ESELFDIS)) { 450 switch (mvport->port_edmamode) { 451 case dma: 452 case queued: 453 case ncq: 454 mvsata_edma_reset_qptr(mvport); 455 mvsata_edma_enable(mvport); 456 if (cause & EDMA_IE_EDEVERR) 457 break; 458 459 /* FALLTHROUGH */ 460 461 case nodma: 462 default: 463 aprint_error( 464 "%s:%d:%d: EDMA self disable happen 0x%x\n", 465 device_xname(MVSATA_DEV2(mvport)), 466 mvport->port_hc->hc, mvport->port, cause); 467 break; 468 } 469 handled = 1; 470 } 471 #endif 472 if (cause & EDMA_IE_ETRANSINT) { 473 /* hot plug the Port Multiplier */ 474 aprint_normal("%s:%d:%d: detect Port Multiplier?\n", 475 device_xname(MVSATA_DEV2(mvport)), 476 mvport->port_hc->hc, mvport->port); 477 } 478 479 return handled; 480 } 481 482 483 /* 484 * ATA callback entry points 485 */ 486 487 #ifndef MVSATA_WITHOUTDMA 488 static int 489 mvsata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 490 { 491 struct ata_channel *chp = drvp->chnl_softc; 492 struct atac_softc *atac = chp->ch_atac; 493 struct ata_xfer *xfer; 494 495 DPRINTFN(1, ("%s:%d: mvsata_bio: drive=%d, blkno=%" PRId64 496 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel, 497 drvp->drive, ata_bio->blkno, ata_bio->bcount)); 498 499 xfer = ata_get_xfer(ATAXF_NOSLEEP); 500 if (xfer == NULL) 501 return ATACMD_TRY_AGAIN; 502 if (atac->atac_cap & ATAC_CAP_NOIRQ) 503 ata_bio->flags |= ATA_POLL; 504 if (ata_bio->flags & ATA_POLL) 505 xfer->c_flags |= C_POLL; 506 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 507 (ata_bio->flags & ATA_SINGLE) == 0) 508 xfer->c_flags |= C_DMA; 509 xfer->c_drive = drvp->drive; 510 xfer->c_cmd = ata_bio; 511 xfer->c_databuf = ata_bio->databuf; 512 xfer->c_bcount = ata_bio->bcount; 513 xfer->c_start = mvsata_bio_start; 514 xfer->c_intr = mvsata_bio_intr; 515 xfer->c_kill_xfer = mvsata_bio_kill_xfer; 516 ata_exec_xfer(chp, xfer); 517 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 518 } 519 520 static void 521 mvsata_reset_drive(struct ata_drive_datas *drvp, int flags) 522 { 523 struct ata_channel *chp = drvp->chnl_softc; 524 struct mvsata_port *mvport = (struct mvsata_port *)chp; 525 uint32_t edma_c; 526 527 edma_c = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 528 529 DPRINTF(("%s:%d: mvsata_reset_drive: drive=%d (EDMA %sactive)\n", 530 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive, 531 (edma_c & EDMA_CMD_EENEDMA) ? "" : "not ")); 532 533 if (edma_c & EDMA_CMD_EENEDMA) 534 mvsata_edma_disable(mvport, 10000, flags & AT_WAIT); 535 536 mvsata_softreset(mvport, flags & AT_WAIT); 537 538 if (edma_c & EDMA_CMD_EENEDMA) { 539 mvsata_edma_reset_qptr(mvport); 540 mvsata_edma_enable(mvport); 541 } 542 return; 543 } 544 545 static void 546 mvsata_reset_channel(struct ata_channel *chp, int flags) 547 { 548 struct mvsata_port *mvport = (struct mvsata_port *)chp; 549 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 550 struct ata_xfer *xfer; 551 uint32_t sstat, ctrl; 552 int i; 553 554 DPRINTF(("%s: mvsata_reset_channel: channel=%d\n", 555 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 556 557 mvsata_hreset_port(mvport); 558 sstat = sata_reset_interface(chp, mvport->port_iot, 559 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 560 561 if (flags & AT_WAIT && sstat == SStatus_DET_DEV_NE && 562 sc->sc_gen != gen1) { 563 /* Downgrade to GenI */ 564 const uint32_t val = SControl_IPM_NONE | SControl_SPD_ANY | 565 SControl_DET_DISABLE; 566 567 MVSATA_EDMA_WRITE_4(mvport, mvport->port_sata_scontrol, val); 568 569 ctrl = MVSATA_EDMA_READ_4(mvport, SATA_SATAICFG); 570 ctrl &= ~(1 << 17); /* Disable GenII */ 571 MVSATA_EDMA_WRITE_4(mvport, SATA_SATAICFG, ctrl); 572 573 mvsata_hreset_port(mvport); 574 sata_reset_interface(chp, mvport->port_iot, 575 mvport->port_sata_scontrol, mvport->port_sata_sstatus); 576 } 577 578 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 579 xfer = mvport->port_reqtbl[i].xfer; 580 if (xfer == NULL) 581 continue; 582 chp->ch_queue->active_xfer = xfer; 583 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 584 } 585 586 mvsata_edma_config(mvport, mvport->port_edmamode); 587 mvsata_edma_reset_qptr(mvport); 588 mvsata_edma_enable(mvport); 589 return; 590 } 591 592 593 static int 594 mvsata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 595 { 596 struct ata_channel *chp = drvp->chnl_softc; 597 #ifdef MVSATA_DEBUG 598 struct mvsata_port *mvport = (struct mvsata_port *)chp; 599 #endif 600 struct ata_xfer *xfer; 601 int rv, s; 602 603 DPRINTFN(1, ("%s:%d: mvsata_exec_command: drive=%d, bcount=%d," 604 " r_command=0x%x, r_head=0x%x, r_cyl=0x%x, r_sector=0x%x," 605 " r_count=0x%x, r_features=0x%x\n", 606 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, 607 drvp->drive, ata_c->bcount, ata_c->r_command, ata_c->r_head, 608 ata_c->r_cyl, ata_c->r_sector, ata_c->r_count, ata_c->r_features)); 609 610 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 611 ATAXF_NOSLEEP); 612 if (xfer == NULL) 613 return ATACMD_TRY_AGAIN; 614 if (ata_c->flags & AT_POLL) 615 xfer->c_flags |= C_POLL; 616 if (ata_c->flags & AT_WAIT) 617 xfer->c_flags |= C_WAIT; 618 xfer->c_drive = drvp->drive; 619 xfer->c_databuf = ata_c->data; 620 xfer->c_bcount = ata_c->bcount; 621 xfer->c_cmd = ata_c; 622 xfer->c_start = mvsata_wdc_cmd_start; 623 xfer->c_intr = mvsata_wdc_cmd_intr; 624 xfer->c_kill_xfer = mvsata_wdc_cmd_kill_xfer; 625 s = splbio(); 626 ata_exec_xfer(chp, xfer); 627 #ifdef DIAGNOSTIC 628 if ((ata_c->flags & AT_POLL) != 0 && 629 (ata_c->flags & AT_DONE) == 0) 630 panic("mvsata_exec_command: polled command not done"); 631 #endif 632 if (ata_c->flags & AT_DONE) 633 rv = ATACMD_COMPLETE; 634 else { 635 if (ata_c->flags & AT_WAIT) { 636 while ((ata_c->flags & AT_DONE) == 0) 637 tsleep(ata_c, PRIBIO, "mvsatacmd", 0); 638 rv = ATACMD_COMPLETE; 639 } else 640 rv = ATACMD_QUEUED; 641 } 642 splx(s); 643 return rv; 644 } 645 646 static int 647 mvsata_addref(struct ata_drive_datas *drvp) 648 { 649 650 return 0; 651 } 652 653 static void 654 mvsata_delref(struct ata_drive_datas *drvp) 655 { 656 657 return; 658 } 659 660 static void 661 mvsata_killpending(struct ata_drive_datas *drvp) 662 { 663 664 return; 665 } 666 667 #if NATAPIBUS > 0 668 static void 669 mvsata_atapibus_attach(struct atabus_softc *ata_sc) 670 { 671 struct ata_channel *chp = ata_sc->sc_chan; 672 struct atac_softc *atac = chp->ch_atac; 673 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 674 struct scsipi_channel *chan = &chp->ch_atapi_channel; 675 676 /* 677 * Fill in the scsipi_adapter. 678 */ 679 adapt->adapt_dev = atac->atac_dev; 680 adapt->adapt_nchannels = atac->atac_nchannels; 681 adapt->adapt_request = mvsata_atapi_scsipi_request; 682 adapt->adapt_minphys = mvsata_atapi_minphys; 683 atac->atac_atapi_adapter.atapi_probe_device = mvsata_atapi_probe_device; 684 685 /* 686 * Fill in the scsipi_channel. 687 */ 688 memset(chan, 0, sizeof(*chan)); 689 chan->chan_adapter = adapt; 690 chan->chan_bustype = &mvsata_atapi_bustype; 691 chan->chan_channel = chp->ch_channel; 692 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 693 chan->chan_openings = 1; 694 chan->chan_max_periph = 1; 695 chan->chan_ntargets = 1; 696 chan->chan_nluns = 1; 697 698 chp->atapibus = 699 config_found_ia(ata_sc->sc_dev, "atapi", chan, atapiprint); 700 } 701 702 static void 703 mvsata_atapi_scsipi_request(struct scsipi_channel *chan, 704 scsipi_adapter_req_t req, void *arg) 705 { 706 struct scsipi_adapter *adapt = chan->chan_adapter; 707 struct scsipi_periph *periph; 708 struct scsipi_xfer *sc_xfer; 709 struct mvsata_softc *sc = device_private(adapt->adapt_dev); 710 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 711 struct ata_xfer *xfer; 712 int channel = chan->chan_channel; 713 int drive, s; 714 715 switch (req) { 716 case ADAPTER_REQ_RUN_XFER: 717 sc_xfer = arg; 718 periph = sc_xfer->xs_periph; 719 drive = periph->periph_target; 720 721 if (!device_is_active(atac->atac_dev)) { 722 sc_xfer->error = XS_DRIVER_STUFFUP; 723 scsipi_done(sc_xfer); 724 return; 725 } 726 xfer = ata_get_xfer(ATAXF_NOSLEEP); 727 if (xfer == NULL) { 728 sc_xfer->error = XS_RESOURCE_SHORTAGE; 729 scsipi_done(sc_xfer); 730 return; 731 } 732 733 if (sc_xfer->xs_control & XS_CTL_POLL) 734 xfer->c_flags |= C_POLL; 735 xfer->c_drive = drive; 736 xfer->c_flags |= C_ATAPI; 737 xfer->c_cmd = sc_xfer; 738 xfer->c_databuf = sc_xfer->data; 739 xfer->c_bcount = sc_xfer->datalen; 740 xfer->c_start = mvsata_atapi_start; 741 xfer->c_intr = mvsata_atapi_intr; 742 xfer->c_kill_xfer = mvsata_atapi_kill_xfer; 743 xfer->c_dscpoll = 0; 744 s = splbio(); 745 ata_exec_xfer(atac->atac_channels[channel], xfer); 746 #ifdef DIAGNOSTIC 747 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 748 (sc_xfer->xs_status & XS_STS_DONE) == 0) 749 panic("mvsata_atapi_scsipi_request:" 750 " polled command not done"); 751 #endif 752 splx(s); 753 return; 754 755 default: 756 /* Not supported, nothing to do. */ 757 ; 758 } 759 } 760 761 static void 762 mvsata_atapi_minphys(struct buf *bp) 763 { 764 765 if (bp->b_bcount > MAXPHYS) 766 bp->b_bcount = MAXPHYS; 767 minphys(bp); 768 } 769 770 static void 771 mvsata_atapi_probe_device(struct atapibus_softc *sc, int target) 772 { 773 struct scsipi_channel *chan = sc->sc_channel; 774 struct scsipi_periph *periph; 775 struct ataparams ids; 776 struct ataparams *id = &ids; 777 struct mvsata_softc *mvc = 778 device_private(chan->chan_adapter->adapt_dev); 779 struct atac_softc *atac = &mvc->sc_wdcdev.sc_atac; 780 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 781 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 782 struct scsipibus_attach_args sa; 783 char serial_number[21], model[41], firmware_revision[9]; 784 int s; 785 786 /* skip if already attached */ 787 if (scsipi_lookup_periph(chan, target, 0) != NULL) 788 return; 789 790 /* if no ATAPI device detected at attach time, skip */ 791 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 792 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 793 " drive %d not present\n", 794 device_xname(atac->atac_dev), chp->ch_channel, target)); 795 return; 796 } 797 798 /* Some ATAPI devices need a bit more time after software reset. */ 799 delay(5000); 800 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 801 #ifdef ATAPI_DEBUG_PROBE 802 log(LOG_DEBUG, "%s:%d: drive %d: cmdsz 0x%x drqtype 0x%x\n", 803 device_xname(atac->atac_dev), chp->ch_channel, target, 804 id->atap_config & ATAPI_CFG_CMD_MASK, 805 id->atap_config & ATAPI_CFG_DRQ_MASK); 806 #endif 807 periph = scsipi_alloc_periph(M_NOWAIT); 808 if (periph == NULL) { 809 aprint_error_dev(atac->atac_dev, 810 "unable to allocate periph" 811 " for channel %d drive %d\n", 812 chp->ch_channel, target); 813 return; 814 } 815 periph->periph_dev = NULL; 816 periph->periph_channel = chan; 817 periph->periph_switch = &atapi_probe_periphsw; 818 periph->periph_target = target; 819 periph->periph_lun = 0; 820 periph->periph_quirks = PQUIRK_ONLYBIG; 821 822 #ifdef SCSIPI_DEBUG 823 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 824 SCSIPI_DEBUG_TARGET == target) 825 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 826 #endif 827 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 828 if (id->atap_config & ATAPI_CFG_REMOV) 829 periph->periph_flags |= PERIPH_REMOVABLE; 830 if (periph->periph_type == T_SEQUENTIAL) { 831 s = splbio(); 832 drvp->drive_flags |= DRIVE_ATAPIST; 833 splx(s); 834 } 835 836 sa.sa_periph = periph; 837 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 838 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 839 T_REMOV : T_FIXED; 840 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 841 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 20); 842 scsipi_strvis((u_char *)firmware_revision, 8, id->atap_revision, 843 8); 844 sa.sa_inqbuf.vendor = model; 845 sa.sa_inqbuf.product = serial_number; 846 sa.sa_inqbuf.revision = firmware_revision; 847 848 /* 849 * Determine the operating mode capabilities of the device. 850 */ 851 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 852 periph->periph_cap |= PERIPH_CAP_CMD16; 853 /* XXX This is gross. */ 854 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 855 856 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 857 858 if (drvp->drv_softc) 859 ata_probe_caps(drvp); 860 else { 861 s = splbio(); 862 drvp->drive_flags &= ~DRIVE_ATAPI; 863 splx(s); 864 } 865 } else { 866 DPRINTF(("%s:%d: mvsata_atapi_probe_device:" 867 " ATAPI_IDENTIFY_DEVICE failed for drive %d: error 0x%x\n", 868 device_xname(atac->atac_dev), chp->ch_channel, target, 869 chp->ch_error)); 870 s = splbio(); 871 drvp->drive_flags &= ~DRIVE_ATAPI; 872 splx(s); 873 } 874 } 875 876 /* 877 * Kill off all pending xfers for a periph. 878 * 879 * Must be called at splbio(). 880 */ 881 static void 882 mvsata_atapi_kill_pending(struct scsipi_periph *periph) 883 { 884 struct atac_softc *atac = 885 device_private(periph->periph_channel->chan_adapter->adapt_dev); 886 struct ata_channel *chp = 887 atac->atac_channels[periph->periph_channel->chan_channel]; 888 889 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 890 } 891 #endif /* NATAPIBUS > 0 */ 892 #endif /* MVSATA_WITHOUTDMA */ 893 894 895 /* 896 * mvsata_setup_channel() 897 * Setup EDMA registers and prepare/purge DMA resources. 898 * We assuming already stopped the EDMA. 899 */ 900 static void 901 mvsata_setup_channel(struct ata_channel *chp) 902 { 903 #if !defined(MVSATA_WITHOUTDMA) || defined(MVSATA_DEBUG) 904 struct mvsata_port *mvport = (struct mvsata_port *)chp; 905 #endif 906 struct ata_drive_datas *drvp; 907 uint32_t edma_mode; 908 int drive, s; 909 #ifndef MVSATA_WITHOUTDMA 910 int i; 911 const int crqb_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 912 const int crpb_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 913 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 914 #endif 915 916 DPRINTF(("%s:%d: mvsata_setup_channel: ", 917 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel)); 918 919 edma_mode = nodma; 920 for (drive = 0; drive < chp->ch_ndrive; drive++) { 921 drvp = &chp->ch_drive[drive]; 922 923 /* If no drive, skip */ 924 if (!(drvp->drive_flags & DRIVE)) 925 continue; 926 927 if (drvp->drive_flags & DRIVE_UDMA) { 928 /* use Ultra/DMA */ 929 s = splbio(); 930 drvp->drive_flags &= ~DRIVE_DMA; 931 splx(s); 932 } 933 934 if (drvp->drive_flags & (DRIVE_UDMA | DRIVE_DMA)) 935 if (drvp->drive_flags & DRIVE_ATA) 936 edma_mode = dma; 937 } 938 939 DPRINTF(("EDMA %sactive mode\n", (edma_mode == nodma) ? "not " : "")); 940 941 #ifndef MVSATA_WITHOUTDMA 942 if (edma_mode == nodma) { 943 no_edma: 944 if (mvport->port_crqb != NULL) 945 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 946 mvport->port_crqb_dmamap, mvport->port_crqb); 947 if (mvport->port_crpb != NULL) 948 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 949 mvport->port_crpb_dmamap, mvport->port_crpb); 950 if (mvport->port_eprd != NULL) 951 mvsata_edma_resource_purge(mvport, mvport->port_dmat, 952 mvport->port_eprd_dmamap, mvport->port_eprd); 953 954 return; 955 } 956 957 if (mvport->port_crqb == NULL) 958 mvport->port_crqb = mvsata_edma_resource_prepare(mvport, 959 mvport->port_dmat, &mvport->port_crqb_dmamap, crqb_size, 1); 960 if (mvport->port_crpb == NULL) 961 mvport->port_crpb = mvsata_edma_resource_prepare(mvport, 962 mvport->port_dmat, &mvport->port_crpb_dmamap, crpb_size, 0); 963 if (mvport->port_eprd == NULL) { 964 mvport->port_eprd = mvsata_edma_resource_prepare(mvport, 965 mvport->port_dmat, &mvport->port_eprd_dmamap, eprd_buf_size, 966 1); 967 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 968 mvport->port_reqtbl[i].eprd_offset = 969 i * MVSATA_EPRD_MAX_SIZE; 970 mvport->port_reqtbl[i].eprd = mvport->port_eprd + 971 i * MVSATA_EPRD_MAX_SIZE / sizeof(struct eprd); 972 } 973 } 974 975 if (mvport->port_crqb == NULL || mvport->port_crpb == NULL || 976 mvport->port_eprd == NULL) { 977 aprint_error_dev(MVSATA_DEV2(mvport), 978 "channel %d: can't use EDMA\n", chp->ch_channel); 979 s = splbio(); 980 for (drive = 0; drive < chp->ch_ndrive; drive++) { 981 drvp = &chp->ch_drive[drive]; 982 983 /* If no drive, skip */ 984 if (!(drvp->drive_flags & DRIVE)) 985 continue; 986 987 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 988 } 989 splx(s); 990 goto no_edma; 991 } 992 993 mvsata_edma_config(mvport, edma_mode); 994 mvsata_edma_reset_qptr(mvport); 995 mvsata_edma_enable(mvport); 996 #endif 997 } 998 999 #ifndef MVSATA_WITHOUTDMA 1000 static void 1001 mvsata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1002 { 1003 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1004 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 1005 struct atac_softc *atac = chp->ch_atac; 1006 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1007 struct ata_bio *ata_bio = xfer->c_cmd; 1008 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1009 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1010 u_int16_t cyl; 1011 u_int8_t head, sect, cmd = 0; 1012 int nblks, error; 1013 1014 DPRINTFN(2, ("%s:%d: mvsata_bio_start: drive=%d\n", 1015 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1016 1017 if (xfer->c_flags & C_DMA) 1018 if (drvp->n_xfers <= NXFER) 1019 drvp->n_xfers++; 1020 1021 again: 1022 /* 1023 * 1024 * When starting a multi-sector transfer, or doing single-sector 1025 * transfers... 1026 */ 1027 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 1028 if (ata_bio->flags & ATA_SINGLE) 1029 nblks = 1; 1030 else 1031 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1032 /* Check for bad sectors and adjust transfer, if necessary. */ 1033 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 1034 long blkdiff; 1035 int i; 1036 1037 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 1038 i++) { 1039 blkdiff -= ata_bio->blkno; 1040 if (blkdiff < 0) 1041 continue; 1042 if (blkdiff == 0) 1043 /* Replace current block of transfer. */ 1044 ata_bio->blkno = 1045 ata_bio->lp->d_secperunit - 1046 ata_bio->lp->d_nsectors - i - 1; 1047 if (blkdiff < nblks) { 1048 /* Bad block inside transfer. */ 1049 ata_bio->flags |= ATA_SINGLE; 1050 nblks = 1; 1051 } 1052 break; 1053 } 1054 /* Transfer is okay now. */ 1055 } 1056 if (xfer->c_flags & C_DMA) { 1057 ata_bio->nblks = nblks; 1058 ata_bio->nbytes = xfer->c_bcount; 1059 1060 if (xfer->c_flags & C_POLL) 1061 sc->sc_enable_intr(mvport, 0 /*off*/); 1062 error = mvsata_edma_enqueue(mvport, ata_bio, 1063 (char *)xfer->c_databuf + xfer->c_skip); 1064 if (error) { 1065 if (error == EINVAL) { 1066 /* 1067 * We can't do DMA on this transfer 1068 * for some reason. Fall back to 1069 * PIO. 1070 */ 1071 xfer->c_flags &= ~C_DMA; 1072 error = 0; 1073 goto do_pio; 1074 } 1075 if (error == EBUSY) { 1076 aprint_error_dev(atac->atac_dev, 1077 "channel %d: EDMA Queue full\n", 1078 chp->ch_channel); 1079 /* 1080 * XXXX: Perhaps, after it waits for 1081 * a while, it is necessary to call 1082 * bio_start again. 1083 */ 1084 } 1085 ata_bio->error = ERR_DMA; 1086 ata_bio->r_error = 0; 1087 mvsata_bio_done(chp, xfer); 1088 return; 1089 } 1090 chp->ch_flags |= ATACH_DMA_WAIT; 1091 /* start timeout machinery */ 1092 if ((xfer->c_flags & C_POLL) == 0) 1093 callout_reset(&chp->ch_callout, 1094 ATA_DELAY / 1000 * hz, 1095 mvsata_edma_timeout, xfer); 1096 /* wait for irq */ 1097 goto intr; 1098 } /* else not DMA */ 1099 do_pio: 1100 if (ata_bio->flags & ATA_LBA48) { 1101 sect = 0; 1102 cyl = 0; 1103 head = 0; 1104 } else if (ata_bio->flags & ATA_LBA) { 1105 sect = (ata_bio->blkno >> 0) & 0xff; 1106 cyl = (ata_bio->blkno >> 8) & 0xffff; 1107 head = (ata_bio->blkno >> 24) & 0x0f; 1108 head |= WDSD_LBA; 1109 } else { 1110 int blkno = ata_bio->blkno; 1111 sect = blkno % ata_bio->lp->d_nsectors; 1112 sect++; /* Sectors begin with 1, not 0. */ 1113 blkno /= ata_bio->lp->d_nsectors; 1114 head = blkno % ata_bio->lp->d_ntracks; 1115 blkno /= ata_bio->lp->d_ntracks; 1116 cyl = blkno; 1117 head |= WDSD_CHS; 1118 } 1119 ata_bio->nblks = min(nblks, ata_bio->multi); 1120 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 1121 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 1122 if (ata_bio->nblks > 1) 1123 cmd = (ata_bio->flags & ATA_READ) ? 1124 WDCC_READMULTI : WDCC_WRITEMULTI; 1125 else 1126 cmd = (ata_bio->flags & ATA_READ) ? 1127 WDCC_READ : WDCC_WRITE; 1128 1129 /* EDMA disable, if enabled this channel. */ 1130 if (mvport->port_edmamode != nodma) 1131 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1132 1133 /* Do control operations specially. */ 1134 if (__predict_false(drvp->state < READY)) { 1135 /* 1136 * Actually, we want to be careful not to mess with 1137 * the control state if the device is currently busy, 1138 * but we can assume that we never get to this point 1139 * if that's the case. 1140 */ 1141 /* 1142 * If it's not a polled command, we need the kernel 1143 * thread 1144 */ 1145 if ((xfer->c_flags & C_POLL) == 0 && cpu_intr_p()) { 1146 chp->ch_queue->queue_freeze++; 1147 wakeup(&chp->ch_thread); 1148 return; 1149 } 1150 if (mvsata_bio_ready(mvport, ata_bio, xfer->c_drive, 1151 (xfer->c_flags & C_POLL) ? AT_POLL : 0) != 0) { 1152 mvsata_bio_done(chp, xfer); 1153 return; 1154 } 1155 } 1156 1157 /* Initiate command! */ 1158 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1159 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 1160 case WDCWAIT_OK: 1161 break; 1162 case WDCWAIT_TOUT: 1163 goto timeout; 1164 case WDCWAIT_THR: 1165 return; 1166 } 1167 if (ata_bio->flags & ATA_LBA48) 1168 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 1169 (u_int64_t)ata_bio->blkno, nblks); 1170 else 1171 wdccommand(chp, xfer->c_drive, cmd, cyl, 1172 head, sect, nblks, 1173 (ata_bio->lp->d_type == DTYPE_ST506) ? 1174 ata_bio->lp->d_precompcyl / 4 : 0); 1175 1176 /* start timeout machinery */ 1177 if ((xfer->c_flags & C_POLL) == 0) 1178 callout_reset(&chp->ch_callout, 1179 ATA_DELAY / 1000 * hz, wdctimeout, chp); 1180 } else if (ata_bio->nblks > 1) { 1181 /* The number of blocks in the last stretch may be smaller. */ 1182 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 1183 if (ata_bio->nblks > nblks) { 1184 ata_bio->nblks = nblks; 1185 ata_bio->nbytes = xfer->c_bcount; 1186 } 1187 } 1188 /* If this was a write and not using DMA, push the data. */ 1189 if ((ata_bio->flags & ATA_READ) == 0) { 1190 /* 1191 * we have to busy-wait here, we can't rely on running in 1192 * thread context. 1193 */ 1194 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 1195 aprint_error_dev(atac->atac_dev, 1196 "channel %d: drive %d timeout waiting for DRQ," 1197 " st=0x%02x, err=0x%02x\n", 1198 chp->ch_channel, xfer->c_drive, chp->ch_status, 1199 chp->ch_error); 1200 ata_bio->error = TIMEOUT; 1201 mvsata_bio_done(chp, xfer); 1202 return; 1203 } 1204 if (chp->ch_status & WDCS_ERR) { 1205 ata_bio->error = ERROR; 1206 ata_bio->r_error = chp->ch_error; 1207 mvsata_bio_done(chp, xfer); 1208 return; 1209 } 1210 1211 wdc->dataout_pio(chp, drvp->drive_flags, 1212 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1213 } 1214 1215 intr: 1216 /* Wait for IRQ (either real or polled) */ 1217 if ((ata_bio->flags & ATA_POLL) == 0) { 1218 chp->ch_flags |= ATACH_IRQ_WAIT; 1219 1220 #if 1 /* XXXXX: Marvell SATA and mvsata(4) can accept next xfer. */ 1221 chp->ch_queue->active_xfer = NULL; 1222 #endif 1223 } else { 1224 /* Wait for at last 400ns for status bit to be valid */ 1225 delay(1); 1226 if (chp->ch_flags & ATACH_DMA_WAIT) { 1227 mvsata_edma_wait(mvport, xfer, ATA_DELAY); 1228 sc->sc_enable_intr(mvport, 1 /*on*/); 1229 chp->ch_flags &= ~ATACH_DMA_WAIT; 1230 } 1231 mvsata_bio_intr(chp, xfer, 0); 1232 if ((ata_bio->flags & ATA_ITSDONE) == 0) 1233 goto again; 1234 } 1235 return; 1236 1237 timeout: 1238 aprint_error_dev(atac->atac_dev, 1239 "channel %d: drive %d not ready, st=0x%02x, err=0x%02x\n", 1240 chp->ch_channel, xfer->c_drive, chp->ch_status, chp->ch_error); 1241 ata_bio->error = TIMEOUT; 1242 mvsata_bio_done(chp, xfer); 1243 return; 1244 } 1245 1246 static int 1247 mvsata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1248 { 1249 struct atac_softc *atac = chp->ch_atac; 1250 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1251 struct ata_bio *ata_bio = xfer->c_cmd; 1252 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1253 1254 DPRINTFN(2, ("%s:%d: mvsata_bio_intr: drive=%d\n", 1255 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1256 1257 /* Is it not a transfer, but a control operation? */ 1258 if (!(xfer->c_flags & C_DMA) && drvp->state < READY) { 1259 aprint_error_dev(atac->atac_dev, 1260 "channel %d: drive %d bad state %d in mvsata_bio_intr\n", 1261 chp->ch_channel, xfer->c_drive, drvp->state); 1262 panic("mvsata_bio_intr: bad state"); 1263 } 1264 1265 /* 1266 * if we missed an interrupt transfer, reset and restart. 1267 * Don't try to continue transfer, we may have missed cycles. 1268 */ 1269 if (xfer->c_flags & C_TIMEOU) { 1270 ata_bio->error = TIMEOUT; 1271 mvsata_bio_done(chp, xfer); 1272 return 1; 1273 } 1274 1275 /* Ack interrupt done by wdc_wait_for_unbusy */ 1276 if (!(xfer->c_flags & C_DMA) && 1277 (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) 1278 == WDCWAIT_TOUT)) { 1279 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1280 return 0; /* IRQ was not for us */ 1281 aprint_error_dev(atac->atac_dev, 1282 "channel %d: drive %d timeout, c_bcount=%d, c_skip%d\n", 1283 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 1284 xfer->c_skip); 1285 ata_bio->error = TIMEOUT; 1286 mvsata_bio_done(chp, xfer); 1287 return 1; 1288 } 1289 1290 if (xfer->c_flags & C_DMA) { 1291 if (ata_bio->error == NOERROR) 1292 goto end; 1293 if (ata_bio->error == ERR_DMA) 1294 ata_dmaerr(drvp, 1295 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1296 } 1297 1298 /* if we had an error, end */ 1299 if (ata_bio->error != NOERROR) { 1300 mvsata_bio_done(chp, xfer); 1301 return 1; 1302 } 1303 1304 /* If this was a read and not using DMA, fetch the data. */ 1305 if ((ata_bio->flags & ATA_READ) != 0) { 1306 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 1307 aprint_error_dev(atac->atac_dev, 1308 "channel %d: drive %d read intr before drq\n", 1309 chp->ch_channel, xfer->c_drive); 1310 ata_bio->error = TIMEOUT; 1311 mvsata_bio_done(chp, xfer); 1312 return 1; 1313 } 1314 wdc->datain_pio(chp, drvp->drive_flags, 1315 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 1316 } 1317 1318 end: 1319 ata_bio->blkno += ata_bio->nblks; 1320 ata_bio->blkdone += ata_bio->nblks; 1321 xfer->c_skip += ata_bio->nbytes; 1322 xfer->c_bcount -= ata_bio->nbytes; 1323 /* See if this transfer is complete. */ 1324 if (xfer->c_bcount > 0) { 1325 if ((ata_bio->flags & ATA_POLL) == 0) 1326 /* Start the next operation */ 1327 mvsata_bio_start(chp, xfer); 1328 else 1329 /* Let mvsata_bio_start do the loop */ 1330 return 1; 1331 } else { /* Done with this transfer */ 1332 ata_bio->error = NOERROR; 1333 mvsata_bio_done(chp, xfer); 1334 } 1335 return 1; 1336 } 1337 1338 static void 1339 mvsata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1340 { 1341 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1342 struct atac_softc *atac = chp->ch_atac; 1343 struct ata_bio *ata_bio = xfer->c_cmd; 1344 int drive = xfer->c_drive; 1345 1346 DPRINTFN(2, ("%s:%d: mvsata_bio_kill_xfer: drive=%d\n", 1347 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1348 1349 /* EDMA restart, if enabled */ 1350 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1351 mvsata_edma_reset_qptr(mvport); 1352 mvsata_edma_enable(mvport); 1353 } 1354 1355 ata_free_xfer(chp, xfer); 1356 1357 ata_bio->flags |= ATA_ITSDONE; 1358 switch (reason) { 1359 case KILL_GONE: 1360 ata_bio->error = ERR_NODEV; 1361 break; 1362 case KILL_RESET: 1363 ata_bio->error = ERR_RESET; 1364 break; 1365 default: 1366 aprint_error_dev(atac->atac_dev, 1367 "mvsata_bio_kill_xfer: unknown reason %d\n", reason); 1368 panic("mvsata_bio_kill_xfer"); 1369 } 1370 ata_bio->r_error = WDCE_ABRT; 1371 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1372 } 1373 1374 static void 1375 mvsata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 1376 { 1377 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1378 struct ata_bio *ata_bio = xfer->c_cmd; 1379 int drive = xfer->c_drive; 1380 1381 DPRINTFN(2, ("%s:%d: mvsata_bio_done: drive=%d, flags=0x%x\n", 1382 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive, 1383 (u_int)xfer->c_flags)); 1384 1385 callout_stop(&chp->ch_callout); 1386 1387 /* EDMA restart, if enabled */ 1388 if (!(xfer->c_flags & C_DMA) && mvport->port_edmamode != nodma) { 1389 mvsata_edma_reset_qptr(mvport); 1390 mvsata_edma_enable(mvport); 1391 } 1392 1393 /* feed back residual bcount to our caller */ 1394 ata_bio->bcount = xfer->c_bcount; 1395 1396 /* mark controller inactive and free xfer */ 1397 chp->ch_queue->active_xfer = NULL; 1398 ata_free_xfer(chp, xfer); 1399 1400 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1401 ata_bio->error = ERR_NODEV; 1402 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1403 wakeup(&chp->ch_queue->active_xfer); 1404 } 1405 ata_bio->flags |= ATA_ITSDONE; 1406 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1407 atastart(chp); 1408 } 1409 1410 static int 1411 mvsata_bio_ready(struct mvsata_port *mvport, struct ata_bio *ata_bio, int drive, 1412 int flags) 1413 { 1414 struct ata_channel *chp = &mvport->port_ata_channel; 1415 struct atac_softc *atac = chp->ch_atac; 1416 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 1417 const char *errstring; 1418 1419 /* 1420 * disable interrupts, all commands here should be quick 1421 * enough to be able to poll, and we don't go here that often 1422 */ 1423 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1424 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1425 DELAY(10); 1426 errstring = "wait"; 1427 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1428 goto ctrltimeout; 1429 wdccommandshort(chp, drive, WDCC_RECAL); 1430 /* Wait for at last 400ns for status bit to be valid */ 1431 DELAY(1); 1432 errstring = "recal"; 1433 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1434 goto ctrltimeout; 1435 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1436 goto ctrlerror; 1437 /* Don't try to set modes if controller can't be adjusted */ 1438 if (atac->atac_set_modes == NULL) 1439 goto geometry; 1440 /* Also don't try if the drive didn't report its mode */ 1441 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1442 goto geometry; 1443 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1444 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1445 errstring = "piomode"; 1446 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1447 goto ctrltimeout; 1448 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1449 goto ctrlerror; 1450 if (drvp->drive_flags & DRIVE_UDMA) 1451 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1452 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1453 else if (drvp->drive_flags & DRIVE_DMA) 1454 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1455 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1456 else 1457 goto geometry; 1458 errstring = "dmamode"; 1459 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1460 goto ctrltimeout; 1461 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1462 goto ctrlerror; 1463 geometry: 1464 if (ata_bio->flags & ATA_LBA) 1465 goto multimode; 1466 wdccommand(chp, drive, WDCC_IDP, ata_bio->lp->d_ncylinders, 1467 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 1468 (ata_bio->lp->d_type == DTYPE_ST506) ? 1469 ata_bio->lp->d_precompcyl / 4 : 0); 1470 errstring = "geometry"; 1471 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1472 goto ctrltimeout; 1473 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1474 goto ctrlerror; 1475 multimode: 1476 if (ata_bio->multi == 1) 1477 goto ready; 1478 wdccommand(chp, drive, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0); 1479 errstring = "setmulti"; 1480 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, flags)) 1481 goto ctrltimeout; 1482 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 1483 goto ctrlerror; 1484 ready: 1485 drvp->state = READY; 1486 /* 1487 * The drive is usable now 1488 */ 1489 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1490 delay(10); /* some drives need a little delay here */ 1491 return 0; 1492 1493 ctrltimeout: 1494 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s timed out\n", 1495 chp->ch_channel, drive, errstring); 1496 ata_bio->error = TIMEOUT; 1497 goto ctrldone; 1498 ctrlerror: 1499 aprint_error_dev(atac->atac_dev, "channel %d: drive %d %s ", 1500 chp->ch_channel, drive, errstring); 1501 if (chp->ch_status & WDCS_DWF) { 1502 aprint_error("drive fault\n"); 1503 ata_bio->error = ERR_DF; 1504 } else { 1505 aprint_error("error (%x)\n", chp->ch_error); 1506 ata_bio->r_error = chp->ch_error; 1507 ata_bio->error = ERROR; 1508 } 1509 ctrldone: 1510 drvp->state = 0; 1511 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1512 return -1; 1513 } 1514 1515 static void 1516 mvsata_wdc_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1517 { 1518 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1519 int drive = xfer->c_drive; 1520 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1521 struct ata_command *ata_c = xfer->c_cmd; 1522 1523 DPRINTFN(1, ("%s:%d: mvsata_cmd_start: drive=%d\n", 1524 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drive)); 1525 1526 /* First, EDMA disable, if enabled this channel. */ 1527 if (mvport->port_edmamode != nodma) 1528 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1529 1530 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1531 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1532 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1533 case WDCWAIT_OK: 1534 break; 1535 case WDCWAIT_TOUT: 1536 ata_c->flags |= AT_TIMEOU; 1537 mvsata_wdc_cmd_done(chp, xfer); 1538 return; 1539 case WDCWAIT_THR: 1540 return; 1541 } 1542 if (ata_c->flags & AT_POLL) 1543 /* polled command, disable interrupts */ 1544 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1545 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1546 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1547 1548 if ((ata_c->flags & AT_POLL) == 0) { 1549 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1550 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1551 wdctimeout, chp); 1552 return; 1553 } 1554 /* 1555 * Polled command. Wait for drive ready or drq. Done in intr(). 1556 * Wait for at last 400ns for status bit to be valid. 1557 */ 1558 delay(10); /* 400ns delay */ 1559 mvsata_wdc_cmd_intr(chp, xfer, 0); 1560 } 1561 1562 static int 1563 mvsata_wdc_cmd_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1564 { 1565 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1566 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1567 struct ata_command *ata_c = xfer->c_cmd; 1568 int bcount = ata_c->bcount; 1569 char *data = ata_c->data; 1570 int wflags; 1571 int drive_flags; 1572 1573 if (ata_c->r_command == WDCC_IDENTIFY || 1574 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) 1575 /* 1576 * The IDENTIFY data has been designed as an array of 1577 * u_int16_t, so we can byteswap it on the fly. 1578 * Historically it's what we have always done so keeping it 1579 * here ensure binary backward compatibility. 1580 */ 1581 drive_flags = DRIVE_NOSTREAM | 1582 chp->ch_drive[xfer->c_drive].drive_flags; 1583 else 1584 /* 1585 * Other data structure are opaque and should be transfered 1586 * as is. 1587 */ 1588 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1589 1590 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) 1591 /* both wait and poll, we can tsleep here */ 1592 wflags = AT_WAIT | AT_POLL; 1593 else 1594 wflags = AT_POLL; 1595 1596 again: 1597 DPRINTFN(1, ("%s:%d: mvsata_cmd_intr: drive=%d\n", 1598 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1599 1600 /* 1601 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1602 * Reselect again, it doesn't hurt for others commands, and the time 1603 * penalty for the extra regiter write is acceptable, 1604 * wdc_exec_command() isn't called often (mosly for autoconfig) 1605 */ 1606 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1607 if ((ata_c->flags & AT_XFDONE) != 0) { 1608 /* 1609 * We have completed a data xfer. The drive should now be 1610 * in its initial state 1611 */ 1612 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1613 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1614 wflags) == WDCWAIT_TOUT) { 1615 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1616 return 0; /* IRQ was not for us */ 1617 ata_c->flags |= AT_TIMEOU; 1618 } 1619 goto out; 1620 } 1621 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1622 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1623 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1624 return 0; /* IRQ was not for us */ 1625 ata_c->flags |= AT_TIMEOU; 1626 goto out; 1627 } 1628 if (ata_c->flags & AT_READ) { 1629 if ((chp->ch_status & WDCS_DRQ) == 0) { 1630 ata_c->flags |= AT_TIMEOU; 1631 goto out; 1632 } 1633 wdc->datain_pio(chp, drive_flags, data, bcount); 1634 /* at this point the drive should be in its initial state */ 1635 ata_c->flags |= AT_XFDONE; 1636 /* 1637 * XXX checking the status register again here cause some 1638 * hardware to timeout. 1639 */ 1640 } else if (ata_c->flags & AT_WRITE) { 1641 if ((chp->ch_status & WDCS_DRQ) == 0) { 1642 ata_c->flags |= AT_TIMEOU; 1643 goto out; 1644 } 1645 wdc->dataout_pio(chp, drive_flags, data, bcount); 1646 ata_c->flags |= AT_XFDONE; 1647 if ((ata_c->flags & AT_POLL) == 0) { 1648 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for intr */ 1649 callout_reset(&chp->ch_callout, 1650 mstohz(ata_c->timeout), wdctimeout, chp); 1651 return 1; 1652 } else 1653 goto again; 1654 } 1655 out: 1656 mvsata_wdc_cmd_done(chp, xfer); 1657 return 1; 1658 } 1659 1660 static void 1661 mvsata_wdc_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1662 int reason) 1663 { 1664 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1665 struct ata_command *ata_c = xfer->c_cmd; 1666 1667 DPRINTFN(1, ("%s:%d: mvsata_cmd_kill_xfer: drive=%d\n", 1668 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, xfer->c_drive)); 1669 1670 switch (reason) { 1671 case KILL_GONE: 1672 ata_c->flags |= AT_GONE; 1673 break; 1674 case KILL_RESET: 1675 ata_c->flags |= AT_RESET; 1676 break; 1677 default: 1678 aprint_error_dev(MVSATA_DEV2(mvport), 1679 "mvsata_cmd_kill_xfer: unknown reason %d\n", reason); 1680 panic("mvsata_cmd_kill_xfer"); 1681 } 1682 mvsata_wdc_cmd_done_end(chp, xfer); 1683 } 1684 1685 static void 1686 mvsata_wdc_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1687 { 1688 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1689 struct atac_softc *atac = chp->ch_atac; 1690 struct ata_command *ata_c = xfer->c_cmd; 1691 1692 DPRINTFN(1, ("%s:%d: mvsata_cmd_done: drive=%d, flags=0x%x\n", 1693 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1694 ata_c->flags)); 1695 1696 if (chp->ch_status & WDCS_DWF) 1697 ata_c->flags |= AT_DF; 1698 if (chp->ch_status & WDCS_ERR) { 1699 ata_c->flags |= AT_ERROR; 1700 ata_c->r_error = chp->ch_error; 1701 } 1702 if ((ata_c->flags & AT_READREG) != 0 && 1703 device_is_active(atac->atac_dev) && 1704 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1705 ata_c->r_head = MVSATA_WDC_READ_1(mvport, SRB_H); 1706 ata_c->r_count = MVSATA_WDC_READ_1(mvport, SRB_SC); 1707 ata_c->r_sector = MVSATA_WDC_READ_1(mvport, SRB_LBAL); 1708 ata_c->r_cyl = MVSATA_WDC_READ_1(mvport, SRB_LBAM) << 8; 1709 ata_c->r_cyl |= MVSATA_WDC_READ_1(mvport, SRB_LBAH); 1710 ata_c->r_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 1711 ata_c->r_features = ata_c->r_error; 1712 } 1713 callout_stop(&chp->ch_callout); 1714 chp->ch_queue->active_xfer = NULL; 1715 if (ata_c->flags & AT_POLL) { 1716 /* enable interrupts */ 1717 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1718 delay(10); /* some drives need a little delay here */ 1719 } 1720 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1721 mvsata_wdc_cmd_kill_xfer(chp, xfer, KILL_GONE); 1722 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1723 wakeup(&chp->ch_queue->active_xfer); 1724 } else 1725 mvsata_wdc_cmd_done_end(chp, xfer); 1726 } 1727 1728 static void 1729 mvsata_wdc_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1730 { 1731 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1732 struct ata_command *ata_c = xfer->c_cmd; 1733 1734 /* EDMA restart, if enabled */ 1735 if (mvport->port_edmamode != nodma) { 1736 mvsata_edma_reset_qptr(mvport); 1737 mvsata_edma_enable(mvport); 1738 } 1739 1740 ata_c->flags |= AT_DONE; 1741 ata_free_xfer(chp, xfer); 1742 if (ata_c->flags & AT_WAIT) 1743 wakeup(ata_c); 1744 else if (ata_c->callback) 1745 ata_c->callback(ata_c->callback_arg); 1746 atastart(chp); 1747 1748 return; 1749 } 1750 1751 #if NATAPIBUS > 0 1752 static void 1753 mvsata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1754 { 1755 struct mvsata_softc *sc = (struct mvsata_softc *)chp->ch_atac; 1756 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1757 struct atac_softc *atac = &sc->sc_wdcdev.sc_atac; 1758 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1759 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1760 const int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1761 const char *errstring; 1762 1763 DPRINTFN(2, ("%s:%d:%d: mvsata_atapi_start: scsi flags 0x%x\n", 1764 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1765 xfer->c_drive, sc_xfer->xs_control)); 1766 1767 if (mvport->port_edmamode != nodma) 1768 mvsata_edma_disable(mvport, 10 /* ms */, wait_flags); 1769 1770 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 1771 drvp->n_xfers++; 1772 1773 /* Do control operations specially. */ 1774 if (__predict_false(drvp->state < READY)) { 1775 /* If it's not a polled command, we need the kernel thread */ 1776 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 && cpu_intr_p()) { 1777 chp->ch_queue->queue_freeze++; 1778 wakeup(&chp->ch_thread); 1779 return; 1780 } 1781 /* 1782 * disable interrupts, all commands here should be quick 1783 * enough to be able to poll, and we don't go here that often 1784 */ 1785 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT | WDCTL_IDS); 1786 1787 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1788 /* Don't try to set mode if controller can't be adjusted */ 1789 if (atac->atac_set_modes == NULL) 1790 goto ready; 1791 /* Also don't try if the drive didn't report its mode */ 1792 if ((drvp->drive_flags & DRIVE_MODE) == 0) 1793 goto ready; 1794 errstring = "unbusy"; 1795 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) 1796 goto timeout; 1797 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1798 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 1799 errstring = "piomode"; 1800 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1801 goto timeout; 1802 if (chp->ch_status & WDCS_ERR) { 1803 if (chp->ch_error == WDCE_ABRT) { 1804 /* 1805 * Some ATAPI drives reject PIO settings. 1806 * Fall back to PIO mode 3 since that's the 1807 * minimum for ATAPI. 1808 */ 1809 aprint_error_dev(atac->atac_dev, 1810 "channel %d drive %d: PIO mode %d rejected," 1811 " falling back to PIO mode 3\n", 1812 chp->ch_channel, xfer->c_drive, 1813 drvp->PIO_mode); 1814 if (drvp->PIO_mode > 3) 1815 drvp->PIO_mode = 3; 1816 } else 1817 goto error; 1818 } 1819 if (drvp->drive_flags & DRIVE_UDMA) 1820 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1821 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 1822 else 1823 if (drvp->drive_flags & DRIVE_DMA) 1824 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 1825 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 1826 else 1827 goto ready; 1828 errstring = "dmamode"; 1829 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags)) 1830 goto timeout; 1831 if (chp->ch_status & WDCS_ERR) { 1832 if (chp->ch_error == WDCE_ABRT) { 1833 if (drvp->drive_flags & DRIVE_UDMA) 1834 goto error; 1835 else { 1836 /* 1837 * The drive rejected our DMA setting. 1838 * Fall back to mode 1. 1839 */ 1840 aprint_error_dev(atac->atac_dev, 1841 "channel %d drive %d:" 1842 " DMA mode %d rejected," 1843 " falling back to DMA mode 0\n", 1844 chp->ch_channel, xfer->c_drive, 1845 drvp->DMA_mode); 1846 if (drvp->DMA_mode > 0) 1847 drvp->DMA_mode = 0; 1848 } 1849 } else 1850 goto error; 1851 } 1852 ready: 1853 drvp->state = READY; 1854 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1855 delay(10); /* some drives need a little delay here */ 1856 } 1857 /* start timeout machinery */ 1858 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 1859 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1860 wdctimeout, chp); 1861 1862 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1863 switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags) < 0) { 1864 case WDCWAIT_OK: 1865 break; 1866 case WDCWAIT_TOUT: 1867 aprint_error_dev(atac->atac_dev, "not ready, st = %02x\n", 1868 chp->ch_status); 1869 sc_xfer->error = XS_TIMEOUT; 1870 mvsata_atapi_reset(chp, xfer); 1871 return; 1872 case WDCWAIT_THR: 1873 return; 1874 } 1875 1876 /* 1877 * Even with WDCS_ERR, the device should accept a command packet 1878 * Limit length to what can be stuffed into the cylinder register 1879 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 1880 * but not all devices do that and it's not obvious from the 1881 * ATAPI spec that that behaviour should be expected. If more 1882 * data is necessary, multiple data transfer phases will be done. 1883 */ 1884 1885 wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD, 1886 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 0, 0, 0, 1887 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1888 1889 /* 1890 * If there is no interrupt for CMD input, busy-wait for it (done in 1891 * the interrupt routine. If it is a polled command, call the interrupt 1892 * routine until command is done. 1893 */ 1894 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 1895 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) { 1896 /* Wait for at last 400ns for status bit to be valid */ 1897 DELAY(1); 1898 mvsata_atapi_intr(chp, xfer, 0); 1899 } else 1900 chp->ch_flags |= ATACH_IRQ_WAIT; 1901 if (sc_xfer->xs_control & XS_CTL_POLL) { 1902 if (chp->ch_flags & ATACH_DMA_WAIT) { 1903 wdc_dmawait(chp, xfer, sc_xfer->timeout); 1904 chp->ch_flags &= ~ATACH_DMA_WAIT; 1905 } 1906 while ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1907 /* Wait for at last 400ns for status bit to be valid */ 1908 DELAY(1); 1909 mvsata_atapi_intr(chp, xfer, 0); 1910 } 1911 } 1912 return; 1913 1914 timeout: 1915 aprint_error_dev(atac->atac_dev, "channel %d drive %d: %s timed out\n", 1916 chp->ch_channel, xfer->c_drive, errstring); 1917 sc_xfer->error = XS_TIMEOUT; 1918 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1919 delay(10); /* some drives need a little delay here */ 1920 mvsata_atapi_reset(chp, xfer); 1921 return; 1922 1923 error: 1924 aprint_error_dev(atac->atac_dev, 1925 "channel %d drive %d: %s error (0x%x)\n", 1926 chp->ch_channel, xfer->c_drive, errstring, chp->ch_error); 1927 sc_xfer->error = XS_SHORTSENSE; 1928 sc_xfer->sense.atapi_sense = chp->ch_error; 1929 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_4BIT); 1930 delay(10); /* some drives need a little delay here */ 1931 mvsata_atapi_reset(chp, xfer); 1932 return; 1933 } 1934 1935 static int 1936 mvsata_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1937 { 1938 struct mvsata_port *mvport = (struct mvsata_port *)chp; 1939 struct atac_softc *atac = chp->ch_atac; 1940 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1941 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1942 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1943 int len, phase, ire, error, retries=0, i; 1944 void *cmd; 1945 1946 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr\n", 1947 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive)); 1948 1949 /* Is it not a transfer, but a control operation? */ 1950 if (drvp->state < READY) { 1951 aprint_error_dev(atac->atac_dev, 1952 "channel %d drive %d: bad state %d\n", 1953 chp->ch_channel, xfer->c_drive, drvp->state); 1954 panic("mvsata_atapi_intr: bad state"); 1955 } 1956 /* 1957 * If we missed an interrupt in a PIO transfer, reset and restart. 1958 * Don't try to continue transfer, we may have missed cycles. 1959 */ 1960 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 1961 sc_xfer->error = XS_TIMEOUT; 1962 mvsata_atapi_reset(chp, xfer); 1963 return 1; 1964 } 1965 1966 /* Ack interrupt done in wdc_wait_for_unbusy */ 1967 MVSATA_WDC_WRITE_1(mvport, SRB_H, WDSD_IBM); 1968 if (wdc_wait_for_unbusy(chp, 1969 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL) == WDCWAIT_TOUT) { 1970 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1971 return 0; /* IRQ was not for us */ 1972 aprint_error_dev(atac->atac_dev, 1973 "channel %d: device timeout, c_bcount=%d, c_skip=%d\n", 1974 chp->ch_channel, xfer->c_bcount, xfer->c_skip); 1975 if (xfer->c_flags & C_DMA) 1976 ata_dmaerr(drvp, 1977 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1978 sc_xfer->error = XS_TIMEOUT; 1979 mvsata_atapi_reset(chp, xfer); 1980 return 1; 1981 } 1982 1983 /* 1984 * If we missed an IRQ and were using DMA, flag it as a DMA error 1985 * and reset device. 1986 */ 1987 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 1988 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1989 sc_xfer->error = XS_RESET; 1990 mvsata_atapi_reset(chp, xfer); 1991 return (1); 1992 } 1993 /* 1994 * if the request sense command was aborted, report the short sense 1995 * previously recorded, else continue normal processing 1996 */ 1997 1998 again: 1999 len = MVSATA_WDC_READ_1(mvport, SRB_LBAM) + 2000 256 * MVSATA_WDC_READ_1(mvport, SRB_LBAH); 2001 ire = MVSATA_WDC_READ_1(mvport, SRB_SC); 2002 phase = (ire & (WDCI_CMD | WDCI_IN)) | (chp->ch_status & WDCS_DRQ); 2003 DPRINTF(( 2004 "mvsata_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x ire 0x%x :", 2005 xfer->c_bcount, len, chp->ch_status, chp->ch_error, ire)); 2006 2007 switch (phase) { 2008 case PHASE_CMDOUT: 2009 cmd = sc_xfer->cmd; 2010 DPRINTF(("PHASE_CMDOUT\n")); 2011 /* Init the DMA channel if necessary */ 2012 if (xfer->c_flags & C_DMA) { 2013 error = mvsata_bdma_init(mvport, sc_xfer, 2014 (char *)xfer->c_databuf + xfer->c_skip); 2015 if (error) { 2016 if (error == EINVAL) { 2017 /* 2018 * We can't do DMA on this transfer 2019 * for some reason. Fall back to PIO. 2020 */ 2021 xfer->c_flags &= ~C_DMA; 2022 error = 0; 2023 } else { 2024 sc_xfer->error = XS_DRIVER_STUFFUP; 2025 break; 2026 } 2027 } 2028 } 2029 2030 /* send packet command */ 2031 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 2032 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 2033 2034 /* Start the DMA channel if necessary */ 2035 if (xfer->c_flags & C_DMA) { 2036 mvsata_bdma_start(mvport); 2037 chp->ch_flags |= ATACH_DMA_WAIT; 2038 } 2039 2040 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2041 chp->ch_flags |= ATACH_IRQ_WAIT; 2042 return 1; 2043 2044 case PHASE_DATAOUT: 2045 /* write data */ 2046 DPRINTF(("PHASE_DATAOUT\n")); 2047 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 2048 (xfer->c_flags & C_DMA) != 0) { 2049 aprint_error_dev(atac->atac_dev, 2050 "channel %d drive %d: bad data phase DATAOUT\n", 2051 chp->ch_channel, xfer->c_drive); 2052 if (xfer->c_flags & C_DMA) 2053 ata_dmaerr(drvp, 2054 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2055 sc_xfer->error = XS_TIMEOUT; 2056 mvsata_atapi_reset(chp, xfer); 2057 return 1; 2058 } 2059 xfer->c_lenoff = len - xfer->c_bcount; 2060 if (xfer->c_bcount < len) { 2061 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2062 " warning: write only %d of %d requested bytes\n", 2063 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2064 len); 2065 len = xfer->c_bcount; 2066 } 2067 2068 wdc->dataout_pio(chp, drvp->drive_flags, 2069 (char *)xfer->c_databuf + xfer->c_skip, len); 2070 2071 for (i = xfer->c_lenoff; i > 0; i -= 2) 2072 MVSATA_WDC_WRITE_2(mvport, SRB_PIOD, 0); 2073 2074 xfer->c_skip += len; 2075 xfer->c_bcount -= len; 2076 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2077 chp->ch_flags |= ATACH_IRQ_WAIT; 2078 return 1; 2079 2080 case PHASE_DATAIN: 2081 /* Read data */ 2082 DPRINTF(("PHASE_DATAIN\n")); 2083 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 2084 (xfer->c_flags & C_DMA) != 0) { 2085 aprint_error_dev(atac->atac_dev, 2086 "channel %d drive %d: bad data phase DATAIN\n", 2087 chp->ch_channel, xfer->c_drive); 2088 if (xfer->c_flags & C_DMA) 2089 ata_dmaerr(drvp, 2090 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2091 sc_xfer->error = XS_TIMEOUT; 2092 mvsata_atapi_reset(chp, xfer); 2093 return 1; 2094 } 2095 xfer->c_lenoff = len - xfer->c_bcount; 2096 if (xfer->c_bcount < len) { 2097 aprint_error_dev(atac->atac_dev, "channel %d drive %d:" 2098 " warning: reading only %d of %d bytes\n", 2099 chp->ch_channel, xfer->c_drive, xfer->c_bcount, 2100 len); 2101 len = xfer->c_bcount; 2102 } 2103 2104 wdc->datain_pio(chp, drvp->drive_flags, 2105 (char *)xfer->c_databuf + xfer->c_skip, len); 2106 2107 if (xfer->c_lenoff > 0) 2108 wdcbit_bucket(chp, len - xfer->c_bcount); 2109 2110 xfer->c_skip += len; 2111 xfer->c_bcount -= len; 2112 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 2113 chp->ch_flags |= ATACH_IRQ_WAIT; 2114 return 1; 2115 2116 case PHASE_ABORTED: 2117 case PHASE_COMPLETED: 2118 DPRINTF(("PHASE_COMPLETED\n")); 2119 if (xfer->c_flags & C_DMA) 2120 xfer->c_bcount -= sc_xfer->datalen; 2121 sc_xfer->resid = xfer->c_bcount; 2122 mvsata_atapi_phase_complete(xfer); 2123 return 1; 2124 2125 default: 2126 if (++retries<500) { 2127 DELAY(100); 2128 chp->ch_status = MVSATA_WDC_READ_1(mvport, SRB_CS); 2129 chp->ch_error = MVSATA_WDC_READ_1(mvport, SRB_FE); 2130 goto again; 2131 } 2132 aprint_error_dev(atac->atac_dev, 2133 "channel %d drive %d: unknown phase 0x%x\n", 2134 chp->ch_channel, xfer->c_drive, phase); 2135 if (chp->ch_status & WDCS_ERR) { 2136 sc_xfer->error = XS_SHORTSENSE; 2137 sc_xfer->sense.atapi_sense = chp->ch_error; 2138 } else { 2139 if (xfer->c_flags & C_DMA) 2140 ata_dmaerr(drvp, 2141 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2142 sc_xfer->error = XS_RESET; 2143 mvsata_atapi_reset(chp, xfer); 2144 return (1); 2145 } 2146 } 2147 DPRINTF(("mvsata_atapi_intr: mvsata_atapi_done() (end), error 0x%x " 2148 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense)); 2149 mvsata_atapi_done(chp, xfer); 2150 return 1; 2151 } 2152 2153 static void 2154 mvsata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 2155 int reason) 2156 { 2157 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2158 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2159 2160 /* remove this command from xfer queue */ 2161 switch (reason) { 2162 case KILL_GONE: 2163 sc_xfer->error = XS_DRIVER_STUFFUP; 2164 break; 2165 2166 case KILL_RESET: 2167 sc_xfer->error = XS_RESET; 2168 break; 2169 2170 default: 2171 aprint_error_dev(MVSATA_DEV2(mvport), 2172 "mvsata_atapi_kill_xfer: unknown reason %d\n", reason); 2173 panic("mvsata_atapi_kill_xfer"); 2174 } 2175 ata_free_xfer(chp, xfer); 2176 scsipi_done(sc_xfer); 2177 } 2178 2179 static void 2180 mvsata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 2181 { 2182 struct atac_softc *atac = chp->ch_atac; 2183 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2184 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2185 2186 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 2187 drvp->state = 0; 2188 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL) != 0) { 2189 printf("%s:%d:%d: reset failed\n", device_xname(atac->atac_dev), 2190 chp->ch_channel, xfer->c_drive); 2191 sc_xfer->error = XS_SELTIMEOUT; 2192 } 2193 mvsata_atapi_done(chp, xfer); 2194 return; 2195 } 2196 2197 static void 2198 mvsata_atapi_phase_complete(struct ata_xfer *xfer) 2199 { 2200 struct ata_channel *chp = xfer->c_chp; 2201 struct atac_softc *atac = chp->ch_atac; 2202 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 2203 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2204 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 2205 2206 /* wait for DSC if needed */ 2207 if (drvp->drive_flags & DRIVE_ATAPIST) { 2208 DPRINTFN(1, 2209 ("%s:%d:%d: mvsata_atapi_phase_complete: polldsc %d\n", 2210 device_xname(atac->atac_dev), chp->ch_channel, 2211 xfer->c_drive, xfer->c_dscpoll)); 2212 if (cold) 2213 panic("mvsata_atapi_phase_complete: cold"); 2214 2215 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, AT_POLL) == 2216 WDCWAIT_TOUT) { 2217 /* 10ms not enough, try again in 1 tick */ 2218 if (xfer->c_dscpoll++ > mstohz(sc_xfer->timeout)) { 2219 aprint_error_dev(atac->atac_dev, 2220 "channel %d: wait_for_dsc failed\n", 2221 chp->ch_channel); 2222 sc_xfer->error = XS_TIMEOUT; 2223 mvsata_atapi_reset(chp, xfer); 2224 return; 2225 } else 2226 callout_reset(&chp->ch_callout, 1, 2227 mvsata_atapi_polldsc, xfer); 2228 return; 2229 } 2230 } 2231 2232 /* 2233 * Some drive occasionally set WDCS_ERR with 2234 * "ATA illegal length indication" in the error 2235 * register. If we read some data the sense is valid 2236 * anyway, so don't report the error. 2237 */ 2238 if (chp->ch_status & WDCS_ERR && 2239 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 2240 sc_xfer->resid == sc_xfer->datalen)) { 2241 /* save the short sense */ 2242 sc_xfer->error = XS_SHORTSENSE; 2243 sc_xfer->sense.atapi_sense = chp->ch_error; 2244 if ((sc_xfer->xs_periph->periph_quirks & PQUIRK_NOSENSE) == 0) { 2245 /* ask scsipi to send a REQUEST_SENSE */ 2246 sc_xfer->error = XS_BUSY; 2247 sc_xfer->status = SCSI_CHECK; 2248 } else 2249 if (wdc->dma_status & (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 2250 ata_dmaerr(drvp, 2251 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 2252 sc_xfer->error = XS_RESET; 2253 mvsata_atapi_reset(chp, xfer); 2254 return; 2255 } 2256 } 2257 if (xfer->c_bcount != 0) 2258 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_intr:" 2259 " bcount value is %d after io\n", 2260 device_xname(atac->atac_dev), chp->ch_channel, 2261 xfer->c_drive, xfer->c_bcount)); 2262 #ifdef DIAGNOSTIC 2263 if (xfer->c_bcount < 0) 2264 aprint_error_dev(atac->atac_dev, 2265 "channel %d drive %d: mvsata_atapi_intr:" 2266 " warning: bcount value is %d after io\n", 2267 chp->ch_channel, xfer->c_drive, xfer->c_bcount); 2268 #endif 2269 2270 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_phase_complete:" 2271 " mvsata_atapi_done(), error 0x%x sense 0x%x\n", 2272 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2273 sc_xfer->error, sc_xfer->sense.atapi_sense)); 2274 mvsata_atapi_done(chp, xfer); 2275 } 2276 2277 static void 2278 mvsata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 2279 { 2280 struct atac_softc *atac = chp->ch_atac; 2281 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 2282 int drive = xfer->c_drive; 2283 2284 DPRINTFN(1, ("%s:%d:%d: mvsata_atapi_done: flags 0x%x\n", 2285 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 2286 (u_int)xfer->c_flags)); 2287 callout_stop(&chp->ch_callout); 2288 /* mark controller inactive and free the command */ 2289 chp->ch_queue->active_xfer = NULL; 2290 ata_free_xfer(chp, xfer); 2291 2292 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 2293 sc_xfer->error = XS_DRIVER_STUFFUP; 2294 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 2295 wakeup(&chp->ch_queue->active_xfer); 2296 } 2297 2298 DPRINTFN(1, ("%s:%d: mvsata_atapi_done: scsipi_done\n", 2299 device_xname(atac->atac_dev), chp->ch_channel)); 2300 scsipi_done(sc_xfer); 2301 DPRINTFN(1, ("%s:%d: atastart from wdc_atapi_done, flags 0x%x\n", 2302 device_xname(atac->atac_dev), chp->ch_channel, chp->ch_flags)); 2303 atastart(chp); 2304 } 2305 2306 static void 2307 mvsata_atapi_polldsc(void *arg) 2308 { 2309 2310 mvsata_atapi_phase_complete(arg); 2311 } 2312 #endif /* NATAPIBUS > 0 */ 2313 2314 2315 /* 2316 * XXXX: Shall we need lock for race condition in mvsata_edma_enqueue{,_gen2}(), 2317 * if supported queuing command by atabus? The race condition will not happen 2318 * if this is called only to the thread of atabus. 2319 */ 2320 static int 2321 mvsata_edma_enqueue(struct mvsata_port *mvport, struct ata_bio *ata_bio, 2322 void *databuf) 2323 { 2324 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2325 struct ata_channel *chp = &mvport->port_ata_channel; 2326 struct eprd *eprd; 2327 bus_addr_t crqb_base_addr; 2328 bus_dmamap_t data_dmamap; 2329 uint32_t reg; 2330 int quetag, erqqip, erqqop, next, rv, i; 2331 2332 DPRINTFN(2, ("%s:%d:%d: mvsata_edma_enqueue:" 2333 " blkno=0x%" PRIx64 ", nbytes=%d, flags=0x%x\n", 2334 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2335 mvport->port, ata_bio->blkno, ata_bio->nbytes, ata_bio->flags)); 2336 2337 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2338 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2339 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP); 2340 erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2341 next = erqqip; 2342 MVSATA_EDMAQ_INC(next); 2343 if (next == erqqop) 2344 /* queue full */ 2345 return EBUSY; 2346 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2347 /* tag nothing */ 2348 return EBUSY; 2349 DPRINTFN(2, (" erqqip=%d, quetag=%d\n", erqqip, quetag)); 2350 2351 rv = mvsata_dma_bufload(mvport, quetag, databuf, ata_bio->nbytes, 2352 ata_bio->flags); 2353 if (rv != 0) 2354 return rv; 2355 2356 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2357 2358 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2359 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2360 eprd = mvport->port_reqtbl[quetag].eprd; 2361 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2362 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2363 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2364 2365 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2366 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2367 eprd->eot = htole16(0); 2368 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2369 eprd++; 2370 } 2371 (eprd - 1)->eot |= htole16(EPRD_EOT); 2372 #ifdef MVSATA_DEBUG 2373 if (mvsata_debug >= 3) 2374 mvsata_print_eprd(mvport, quetag); 2375 #endif 2376 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2377 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2378 BUS_DMASYNC_PREWRITE); 2379 2380 /* setup EDMA Command Request Block (CRQB) Data */ 2381 sc->sc_edma_setup_crqb(mvport, erqqip, quetag, ata_bio); 2382 #ifdef MVSATA_DEBUG 2383 if (mvsata_debug >= 3) 2384 mvsata_print_crqb(mvport, erqqip); 2385 #endif 2386 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 2387 erqqip * sizeof(union mvsata_crqb), 2388 sizeof(union mvsata_crqb), BUS_DMASYNC_PREWRITE); 2389 2390 MVSATA_EDMAQ_INC(erqqip); 2391 2392 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2393 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2394 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2395 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2396 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2397 2398 return 0; 2399 } 2400 2401 static int 2402 mvsata_edma_handle(struct mvsata_port *mvport, struct ata_xfer *xfer1) 2403 { 2404 struct ata_channel *chp = &mvport->port_ata_channel; 2405 struct crpb *crpb; 2406 struct ata_bio *ata_bio; 2407 struct ata_xfer *xfer; 2408 uint32_t reg; 2409 int erqqip, erqqop, erpqip, erpqop, prev_erpqop, quetag, handled = 0, n; 2410 2411 /* First, Sync for Request Queue buffer */ 2412 reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP); 2413 erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2414 if (mvport->port_prev_erqqop != erqqop) { 2415 const int s = sizeof(union mvsata_crqb); 2416 2417 if (mvport->port_prev_erqqop < erqqop) 2418 n = erqqop - mvport->port_prev_erqqop; 2419 else { 2420 if (erqqop > 0) 2421 bus_dmamap_sync(mvport->port_dmat, 2422 mvport->port_crqb_dmamap, 0, erqqop * s, 2423 BUS_DMASYNC_POSTWRITE); 2424 n = MVSATA_EDMAQ_LEN - mvport->port_prev_erqqop; 2425 } 2426 if (n > 0) 2427 bus_dmamap_sync(mvport->port_dmat, 2428 mvport->port_crqb_dmamap, 2429 mvport->port_prev_erqqop * s, n * s, 2430 BUS_DMASYNC_POSTWRITE); 2431 mvport->port_prev_erqqop = erqqop; 2432 } 2433 2434 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP); 2435 erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2436 reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP); 2437 erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT; 2438 2439 DPRINTFN(3, ("%s:%d:%d: mvsata_edma_handle: erpqip=%d, erpqop=%d\n", 2440 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2441 mvport->port, erpqip, erpqop)); 2442 2443 if (erpqop == erpqip) 2444 return 0; 2445 2446 if (erpqop < erpqip) 2447 n = erpqip - erpqop; 2448 else { 2449 if (erpqip > 0) 2450 bus_dmamap_sync(mvport->port_dmat, 2451 mvport->port_crpb_dmamap, 2452 0, erpqip * sizeof(struct crpb), 2453 BUS_DMASYNC_POSTREAD); 2454 n = MVSATA_EDMAQ_LEN - erpqop; 2455 } 2456 if (n > 0) 2457 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2458 erpqop * sizeof(struct crpb), 2459 n * sizeof(struct crpb), BUS_DMASYNC_POSTREAD); 2460 2461 prev_erpqop = erpqop; 2462 while (erpqop != erpqip) { 2463 #ifdef MVSATA_DEBUG 2464 if (mvsata_debug >= 3) 2465 mvsata_print_crpb(mvport, erpqop); 2466 #endif 2467 crpb = mvport->port_crpb + erpqop; 2468 quetag = CRPB_CHOSTQUETAG(le16toh(crpb->id)); 2469 xfer = chp->ch_queue->active_xfer = 2470 mvport->port_reqtbl[quetag].xfer; 2471 #ifdef DIAGNOSTIC 2472 if (xfer == NULL) 2473 panic("unknwon response received: %s:%d:%d: tag 0x%x\n", 2474 device_xname(MVSATA_DEV2(mvport)), 2475 mvport->port_hc->hc, mvport->port, quetag); 2476 #endif 2477 2478 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2479 mvport->port_reqtbl[quetag].eprd_offset, 2480 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2481 2482 chp->ch_status = CRPB_CDEVSTS(le16toh(crpb->rspflg)); 2483 chp->ch_error = CRPB_CEDMASTS(le16toh(crpb->rspflg)); 2484 ata_bio = xfer->c_cmd; 2485 ata_bio->error = NOERROR; 2486 ata_bio->r_error = 0; 2487 if (chp->ch_status & WDCS_ERR) 2488 ata_bio->error = ERROR; 2489 if (chp->ch_status & WDCS_BSY) 2490 ata_bio->error = TIMEOUT; 2491 if (chp->ch_error) 2492 ata_bio->error = ERR_DMA; 2493 2494 mvsata_dma_bufunload(mvport, quetag, ata_bio->flags); 2495 mvport->port_reqtbl[quetag].xfer = NULL; 2496 mvsata_quetag_put(mvport, quetag); 2497 MVSATA_EDMAQ_INC(erpqop); 2498 2499 #if 1 /* XXXX: flags clears here, because necessary the atabus layer. */ 2500 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2501 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2502 if (erpqop == erqqip) 2503 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2504 #endif 2505 mvsata_bio_intr(chp, xfer, 1); 2506 if (xfer1 == NULL) 2507 handled++; 2508 else if (xfer == xfer1) { 2509 handled = 1; 2510 break; 2511 } 2512 } 2513 if (prev_erpqop < erpqop) 2514 n = erpqop - prev_erpqop; 2515 else { 2516 if (erpqop > 0) 2517 bus_dmamap_sync(mvport->port_dmat, 2518 mvport->port_crpb_dmamap, 0, 2519 erpqop * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2520 n = MVSATA_EDMAQ_LEN - prev_erpqop; 2521 } 2522 if (n > 0) 2523 bus_dmamap_sync(mvport->port_dmat, mvport->port_crpb_dmamap, 2524 prev_erpqop * sizeof(struct crpb), 2525 n * sizeof(struct crpb), BUS_DMASYNC_PREREAD); 2526 2527 reg &= ~EDMA_RESQP_ERPQP_MASK; 2528 reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT); 2529 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg); 2530 2531 #if 0 /* already cleared ago? */ 2532 erqqip = (MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP) & 2533 EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT; 2534 if (erpqop == erqqip) 2535 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_IRQ_WAIT); 2536 #endif 2537 2538 return handled; 2539 } 2540 2541 static int 2542 mvsata_edma_wait(struct mvsata_port *mvport, struct ata_xfer *xfer, int timeout) 2543 { 2544 struct ata_bio *ata_bio = xfer->c_cmd; 2545 int xtime; 2546 2547 for (xtime = 0; xtime < timeout / 10; xtime++) { 2548 if (mvsata_edma_handle(mvport, xfer)) 2549 return 0; 2550 if (ata_bio->flags & ATA_NOSLEEP) 2551 delay(10000); 2552 else 2553 tsleep(&xfer, PRIBIO, "mvsataipl", mstohz(10)); 2554 } 2555 2556 DPRINTF(("mvsata_edma_wait: timeout: %p\n", xfer)); 2557 mvsata_edma_rqq_remove(mvport, xfer); 2558 xfer->c_flags |= C_TIMEOU; 2559 return 1; 2560 } 2561 2562 static void 2563 mvsata_edma_timeout(void *arg) 2564 { 2565 struct ata_xfer *xfer = (struct ata_xfer *)arg; 2566 struct ata_channel *chp = xfer->c_chp; 2567 struct mvsata_port *mvport = (struct mvsata_port *)chp; 2568 int s; 2569 2570 s = splbio(); 2571 DPRINTF(("mvsata_edma_timeout: %p\n", xfer)); 2572 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 2573 mvsata_edma_rqq_remove(mvport, xfer); 2574 xfer->c_flags |= C_TIMEOU; 2575 mvsata_bio_intr(chp, xfer, 1); 2576 } 2577 splx(s); 2578 } 2579 2580 static void 2581 mvsata_edma_rqq_remove(struct mvsata_port *mvport, struct ata_xfer *xfer) 2582 { 2583 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2584 struct ata_bio *ata_bio; 2585 bus_addr_t crqb_base_addr; 2586 int erqqip, i; 2587 2588 /* First, hardware reset, stop EDMA */ 2589 mvsata_hreset_port(mvport); 2590 2591 /* cleanup completed EDMA safely */ 2592 mvsata_edma_handle(mvport, NULL); 2593 2594 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2595 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, BUS_DMASYNC_PREWRITE); 2596 for (i = 0, erqqip = 0; i < MVSATA_EDMAQ_LEN; i++) { 2597 if (mvport->port_reqtbl[i].xfer == NULL) 2598 continue; 2599 2600 ata_bio = mvport->port_reqtbl[i].xfer->c_cmd; 2601 if (mvport->port_reqtbl[i].xfer == xfer) { 2602 /* remove xfer from EDMA request queue */ 2603 bus_dmamap_sync(mvport->port_dmat, 2604 mvport->port_eprd_dmamap, 2605 mvport->port_reqtbl[i].eprd_offset, 2606 MVSATA_EPRD_MAX_SIZE, BUS_DMASYNC_POSTWRITE); 2607 mvsata_dma_bufunload(mvport, i, ata_bio->flags); 2608 mvport->port_reqtbl[i].xfer = NULL; 2609 mvsata_quetag_put(mvport, i); 2610 continue; 2611 } 2612 2613 sc->sc_edma_setup_crqb(mvport, erqqip, i, ata_bio); 2614 erqqip++; 2615 } 2616 bus_dmamap_sync(mvport->port_dmat, mvport->port_crqb_dmamap, 0, 2617 sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN, 2618 BUS_DMASYNC_POSTWRITE); 2619 2620 mvsata_edma_config(mvport, mvport->port_edmamode); 2621 mvsata_edma_reset_qptr(mvport); 2622 mvsata_edma_enable(mvport); 2623 2624 crqb_base_addr = mvport->port_crqb_dmamap->dm_segs[0].ds_addr & 2625 (EDMA_REQQP_ERQQBAP_MASK | EDMA_REQQP_ERQQBA_MASK); 2626 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, (crqb_base_addr >> 16) >> 16); 2627 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 2628 crqb_base_addr | (erqqip << EDMA_REQQP_ERQQP_SHIFT)); 2629 } 2630 2631 #if NATAPIBUS > 0 2632 static int 2633 mvsata_bdma_init(struct mvsata_port *mvport, struct scsipi_xfer *sc_xfer, 2634 void *databuf) 2635 { 2636 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 2637 struct eprd *eprd; 2638 bus_dmamap_t data_dmamap; 2639 bus_addr_t eprd_addr; 2640 int quetag, rv; 2641 2642 DPRINTFN(2, 2643 ("%s:%d:%d: mvsata_bdma_init: datalen=%d, xs_control=0x%x\n", 2644 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 2645 mvport->port, sc_xfer->datalen, sc_xfer->xs_control)); 2646 2647 if ((quetag = mvsata_quetag_get(mvport)) == -1) 2648 /* tag nothing */ 2649 return EBUSY; 2650 DPRINTFN(2, (" quetag=%d\n", quetag)); 2651 2652 rv = mvsata_dma_bufload(mvport, quetag, databuf, sc_xfer->datalen, 2653 sc_xfer->xs_control & XS_CTL_DATA_IN ? ATA_READ : 0); 2654 if (rv != 0) 2655 return rv; 2656 2657 mvport->port_reqtbl[quetag].xfer = chp->ch_queue->active_xfer; 2658 2659 /* setup EDMA Physical Region Descriptors (ePRD) Table Data */ 2660 data_dmamap = mvport->port_reqtbl[quetag].data_dmamap; 2661 eprd = mvport->port_reqtbl[quetag].eprd; 2662 for (i = 0; i < data_dmamap->dm_nsegs; i++) { 2663 bus_addr_t ds_addr = data_dmamap->dm_segs[i].ds_addr; 2664 bus_size_t ds_len = data_dmamap->dm_segs[i].ds_len; 2665 2666 eprd->prdbal = htole32(ds_addr & EPRD_PRDBAL_MASK); 2667 eprd->bytecount = htole32(EPRD_BYTECOUNT(ds_len)); 2668 eprd->eot = htole16(0); 2669 eprd->prdbah = htole32((ds_addr >> 16) >> 16); 2670 eprd++; 2671 } 2672 (eprd - 1)->eot |= htole16(EPRD_EOT); 2673 #ifdef MVSATA_DEBUG 2674 if (mvsata_debug >= 3) 2675 mvsata_print_eprd(mvport, quetag); 2676 #endif 2677 bus_dmamap_sync(mvport->port_dmat, mvport->port_eprd_dmamap, 2678 mvport->port_reqtbl[quetag].eprd_offset, MVSATA_EPRD_MAX_SIZE, 2679 BUS_DMASYNC_PREWRITE); 2680 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 2681 mvport->port_reqtbl[quetag].eprd_offset; 2682 2683 MVSATA_EDMA_WRITE_4(mvport, DMA_DTLBA, eprd_addr & DMA_DTLBA_MASK); 2684 MVSATA_EDMA_WRITE_4(mvport, DMA_DTHBA, (eprd_addr >> 16) >> 16); 2685 2686 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 2687 MVSATA_EDMA_WRITE_4(mvport, DMA_C, DMA_C_READ); 2688 else 2689 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 0); 2690 2691 return 0; 2692 } 2693 2694 static void 2695 mvsata_bdma_start(struct mvsata_port *mvport) 2696 { 2697 2698 #ifdef MVSATA_DEBUG 2699 if (mvsata_debug >= 3) 2700 mvsata_print_eprd(mvport, 0); 2701 #endif 2702 2703 MVSATA_EDMA_WRITE_4(mvport, DMA_C, 2704 MVSATA_EDMA_READ_4(mvport, DMA_C) | DMA_C_START); 2705 } 2706 #endif 2707 #endif 2708 2709 2710 static int 2711 mvsata_port_init(struct mvsata_hc *mvhc, int port) 2712 { 2713 struct mvsata_softc *sc = mvhc->hc_sc; 2714 struct mvsata_port *mvport; 2715 struct ata_channel *chp; 2716 int channel, rv, i; 2717 const int crqbq_size = sizeof(union mvsata_crqb) * MVSATA_EDMAQ_LEN; 2718 const int crpbq_size = sizeof(struct crpb) * MVSATA_EDMAQ_LEN; 2719 const int eprd_buf_size = MVSATA_EPRD_MAX_SIZE * MVSATA_EDMAQ_LEN; 2720 2721 mvport = malloc(sizeof(struct mvsata_port), M_DEVBUF, 2722 M_ZERO | M_NOWAIT); 2723 if (mvport == NULL) { 2724 aprint_error("%s:%d: can't allocate memory for port %d\n", 2725 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2726 return ENOMEM; 2727 } 2728 2729 mvport->port = port; 2730 mvport->port_hc = mvhc; 2731 mvport->port_edmamode = nodma; 2732 2733 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2734 EDMA_REGISTERS_OFFSET + port * EDMA_REGISTERS_SIZE, 2735 EDMA_REGISTERS_SIZE, &mvport->port_ioh); 2736 if (rv != 0) { 2737 aprint_error("%s:%d: can't subregion EDMA %d registers\n", 2738 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2739 goto fail0; 2740 } 2741 mvport->port_iot = mvhc->hc_iot; 2742 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SS, 4, 2743 &mvport->port_sata_sstatus); 2744 if (rv != 0) { 2745 aprint_error("%s:%d:%d: couldn't subregion sstatus regs\n", 2746 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2747 goto fail0; 2748 } 2749 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, SATA_SE, 4, 2750 &mvport->port_sata_serror); 2751 if (rv != 0) { 2752 aprint_error("%s:%d:%d: couldn't subregion serror regs\n", 2753 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2754 goto fail0; 2755 } 2756 if (sc->sc_rev == gen1) 2757 rv = bus_space_subregion(mvhc->hc_iot, mvhc->hc_ioh, 2758 SATAHC_I_R02(port), 4, &mvport->port_sata_scontrol); 2759 else 2760 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2761 SATA_SC, 4, &mvport->port_sata_scontrol); 2762 if (rv != 0) { 2763 aprint_error("%s:%d:%d: couldn't subregion scontrol regs\n", 2764 device_xname(MVSATA_DEV(sc)), mvhc->hc, port); 2765 goto fail0; 2766 } 2767 mvport->port_dmat = sc->sc_dmat; 2768 #ifndef MVSATA_WITHOUTDMA 2769 mvsata_quetag_init(mvport); 2770 #endif 2771 mvhc->hc_ports[port] = mvport; 2772 2773 channel = mvhc->hc * sc->sc_port + port; 2774 chp = &mvport->port_ata_channel; 2775 chp->ch_channel = channel; 2776 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 2777 chp->ch_ndrive = 1; /* SATA is always 1 drive */ 2778 chp->ch_queue = &mvport->port_ata_queue; 2779 sc->sc_ata_channels[channel] = chp; 2780 2781 rv = mvsata_wdc_reg_init(mvport, sc->sc_wdcdev.regs + channel); 2782 if (rv != 0) 2783 goto fail0; 2784 2785 rv = bus_dmamap_create(mvport->port_dmat, crqbq_size, 1, crqbq_size, 0, 2786 BUS_DMA_NOWAIT, &mvport->port_crqb_dmamap); 2787 if (rv != 0) { 2788 aprint_error( 2789 "%s:%d:%d: EDMA CRQB map create failed: error=%d\n", 2790 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2791 goto fail0; 2792 } 2793 rv = bus_dmamap_create(mvport->port_dmat, crpbq_size, 1, crpbq_size, 0, 2794 BUS_DMA_NOWAIT, &mvport->port_crpb_dmamap); 2795 if (rv != 0) { 2796 aprint_error( 2797 "%s:%d:%d: EDMA CRPB map create failed: error=%d\n", 2798 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2799 goto fail1; 2800 } 2801 rv = bus_dmamap_create(mvport->port_dmat, eprd_buf_size, 1, 2802 eprd_buf_size, 0, BUS_DMA_NOWAIT, &mvport->port_eprd_dmamap); 2803 if (rv != 0) { 2804 aprint_error( 2805 "%s:%d:%d: EDMA ePRD buffer map create failed: error=%d\n", 2806 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, rv); 2807 goto fail2; 2808 } 2809 for (i = 0; i < MVSATA_EDMAQ_LEN; i++) { 2810 rv = bus_dmamap_create(mvport->port_dmat, MAXPHYS, 2811 MAXPHYS / PAGE_SIZE, MAXPHYS, 0, BUS_DMA_NOWAIT, 2812 &mvport->port_reqtbl[i].data_dmamap); 2813 if (rv != 0) { 2814 aprint_error("%s:%d:%d:" 2815 " EDMA data map(%d) create failed: error=%d\n", 2816 device_xname(MVSATA_DEV(sc)), mvhc->hc, port, i, 2817 rv); 2818 goto fail3; 2819 } 2820 } 2821 2822 return 0; 2823 2824 fail3: 2825 for (i--; i >= 0; i--) 2826 bus_dmamap_destroy(mvport->port_dmat, 2827 mvport->port_reqtbl[i].data_dmamap); 2828 bus_dmamap_destroy(mvport->port_dmat, mvport->port_eprd_dmamap); 2829 fail2: 2830 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crpb_dmamap); 2831 fail1: 2832 bus_dmamap_destroy(mvport->port_dmat, mvport->port_crqb_dmamap); 2833 fail0: 2834 return rv; 2835 } 2836 2837 static int 2838 mvsata_wdc_reg_init(struct mvsata_port *mvport, struct wdc_regs *wdr) 2839 { 2840 int hc, port, rv, i; 2841 2842 hc = mvport->port_hc->hc; 2843 port = mvport->port; 2844 2845 /* Create subregion for Shadow Registers Map */ 2846 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2847 SHADOW_REG_BLOCK_OFFSET, SHADOW_REG_BLOCK_SIZE, &wdr->cmd_baseioh); 2848 if (rv != 0) { 2849 aprint_error("%s:%d:%d: couldn't subregion shadow block regs\n", 2850 device_xname(MVSATA_DEV2(mvport)), hc, port); 2851 return rv; 2852 } 2853 wdr->cmd_iot = mvport->port_iot; 2854 2855 /* Once create subregion for each command registers */ 2856 for (i = 0; i < WDC_NREG; i++) { 2857 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2858 i * 4, sizeof(uint32_t), &wdr->cmd_iohs[i]); 2859 if (rv != 0) { 2860 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2861 device_xname(MVSATA_DEV2(mvport)), hc, port); 2862 return rv; 2863 } 2864 } 2865 /* Create subregion for Alternate Status register */ 2866 rv = bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 2867 i * 4, sizeof(uint32_t), &wdr->ctl_ioh); 2868 if (rv != 0) { 2869 aprint_error("%s:%d:%d: couldn't subregion cmd regs\n", 2870 device_xname(MVSATA_DEV2(mvport)), hc, port); 2871 return rv; 2872 } 2873 wdr->ctl_iot = mvport->port_iot; 2874 2875 wdc_init_shadow_regs(&mvport->port_ata_channel); 2876 2877 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2878 SATA_SS, sizeof(uint32_t) * 3, &wdr->sata_baseioh); 2879 if (rv != 0) { 2880 aprint_error("%s:%d:%d: couldn't subregion SATA regs\n", 2881 device_xname(MVSATA_DEV2(mvport)), hc, port); 2882 return rv; 2883 } 2884 wdr->sata_iot = mvport->port_iot; 2885 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2886 SATA_SC, sizeof(uint32_t), &wdr->sata_control); 2887 if (rv != 0) { 2888 aprint_error("%s:%d:%d: couldn't subregion SControl\n", 2889 device_xname(MVSATA_DEV2(mvport)), hc, port); 2890 return rv; 2891 } 2892 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2893 SATA_SS, sizeof(uint32_t), &wdr->sata_status); 2894 if (rv != 0) { 2895 aprint_error("%s:%d:%d: couldn't subregion SStatus\n", 2896 device_xname(MVSATA_DEV2(mvport)), hc, port); 2897 return rv; 2898 } 2899 rv = bus_space_subregion(mvport->port_iot, mvport->port_ioh, 2900 SATA_SE, sizeof(uint32_t), &wdr->sata_error); 2901 if (rv != 0) { 2902 aprint_error("%s:%d:%d: couldn't subregion SError\n", 2903 device_xname(MVSATA_DEV2(mvport)), hc, port); 2904 return rv; 2905 } 2906 2907 return 0; 2908 } 2909 2910 2911 #ifndef MVSATA_WITHOUTDMA 2912 /* 2913 * There are functions to determine Host Queue Tag. 2914 * XXXX: We hope to rotate Tag to facilitate debugging. 2915 */ 2916 2917 static inline void 2918 mvsata_quetag_init(struct mvsata_port *mvport) 2919 { 2920 2921 mvport->port_quetagidx = 0; 2922 } 2923 2924 static inline int 2925 mvsata_quetag_get(struct mvsata_port *mvport) 2926 { 2927 int begin = mvport->port_quetagidx; 2928 2929 do { 2930 if (mvport->port_reqtbl[mvport->port_quetagidx].xfer == NULL) { 2931 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2932 return mvport->port_quetagidx; 2933 } 2934 MVSATA_EDMAQ_INC(mvport->port_quetagidx); 2935 } while (mvport->port_quetagidx != begin); 2936 2937 return -1; 2938 } 2939 2940 static inline void 2941 mvsata_quetag_put(struct mvsata_port *mvport, int quetag) 2942 { 2943 2944 /* nothing */ 2945 } 2946 2947 static void * 2948 mvsata_edma_resource_prepare(struct mvsata_port *mvport, bus_dma_tag_t dmat, 2949 bus_dmamap_t *dmamap, size_t size, int write) 2950 { 2951 bus_dma_segment_t seg; 2952 int nseg, rv; 2953 void *kva; 2954 2955 rv = bus_dmamem_alloc(dmat, size, PAGE_SIZE, 0, &seg, 1, &nseg, 2956 BUS_DMA_NOWAIT); 2957 if (rv != 0) { 2958 aprint_error("%s:%d:%d: DMA memory alloc failed: error=%d\n", 2959 device_xname(MVSATA_DEV2(mvport)), 2960 mvport->port_hc->hc, mvport->port, rv); 2961 goto fail; 2962 } 2963 2964 rv = bus_dmamem_map(dmat, &seg, nseg, size, &kva, BUS_DMA_NOWAIT); 2965 if (rv != 0) { 2966 aprint_error("%s:%d:%d: DMA memory map failed: error=%d\n", 2967 device_xname(MVSATA_DEV2(mvport)), 2968 mvport->port_hc->hc, mvport->port, rv); 2969 goto free; 2970 } 2971 2972 rv = bus_dmamap_load(dmat, *dmamap, kva, size, NULL, 2973 BUS_DMA_NOWAIT | (write ? BUS_DMA_WRITE : BUS_DMA_READ)); 2974 if (rv != 0) { 2975 aprint_error("%s:%d:%d: DMA map load failed: error=%d\n", 2976 device_xname(MVSATA_DEV2(mvport)), 2977 mvport->port_hc->hc, mvport->port, rv); 2978 goto unmap; 2979 } 2980 2981 if (!write) 2982 bus_dmamap_sync(dmat, *dmamap, 0, size, BUS_DMASYNC_PREREAD); 2983 2984 return kva; 2985 2986 unmap: 2987 bus_dmamem_unmap(dmat, kva, size); 2988 free: 2989 bus_dmamem_free(dmat, &seg, nseg); 2990 fail: 2991 return NULL; 2992 } 2993 2994 /* ARGSUSED */ 2995 static void 2996 mvsata_edma_resource_purge(struct mvsata_port *mvport, bus_dma_tag_t dmat, 2997 bus_dmamap_t dmamap, void *kva) 2998 { 2999 3000 bus_dmamap_unload(dmat, dmamap); 3001 bus_dmamem_unmap(dmat, kva, dmamap->dm_mapsize); 3002 bus_dmamem_free(dmat, dmamap->dm_segs, dmamap->dm_nsegs); 3003 } 3004 3005 static int 3006 mvsata_dma_bufload(struct mvsata_port *mvport, int index, void *databuf, 3007 size_t datalen, int flags) 3008 { 3009 int rv, lop, sop; 3010 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3011 3012 lop = (flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE; 3013 sop = (flags & ATA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE; 3014 3015 rv = bus_dmamap_load(mvport->port_dmat, data_dmamap, databuf, datalen, 3016 NULL, BUS_DMA_NOWAIT | lop); 3017 if (rv) { 3018 aprint_error("%s:%d:%d: buffer load failed: error=%d", 3019 device_xname(MVSATA_DEV2(mvport)), mvport->port_hc->hc, 3020 mvport->port, rv); 3021 return rv; 3022 } 3023 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3024 data_dmamap->dm_mapsize, sop); 3025 3026 return 0; 3027 } 3028 3029 static inline void 3030 mvsata_dma_bufunload(struct mvsata_port *mvport, int index, int flags) 3031 { 3032 bus_dmamap_t data_dmamap = mvport->port_reqtbl[index].data_dmamap; 3033 3034 bus_dmamap_sync(mvport->port_dmat, data_dmamap, 0, 3035 data_dmamap->dm_mapsize, 3036 (flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3037 bus_dmamap_unload(mvport->port_dmat, data_dmamap); 3038 } 3039 #endif 3040 3041 static void 3042 mvsata_hreset_port(struct mvsata_port *mvport) 3043 { 3044 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3045 3046 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EATARST); 3047 3048 delay(25); /* allow reset propagation */ 3049 3050 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3051 3052 mvport->_fix_phy_param._fix_phy(mvport); 3053 3054 if (sc->sc_gen == gen1) 3055 delay(1000); 3056 } 3057 3058 static void 3059 mvsata_reset_port(struct mvsata_port *mvport) 3060 { 3061 device_t parent = device_parent(MVSATA_DEV2(mvport)); 3062 3063 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3064 3065 mvsata_hreset_port(mvport); 3066 3067 if (device_is_a(parent, "pci")) 3068 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3069 EDMA_CFG_RESERVED | EDMA_CFG_ERDBSZ); 3070 else /* SoC */ 3071 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, 3072 EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2); 3073 MVSATA_EDMA_WRITE_4(mvport, EDMA_T, 0); 3074 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEC, 0); 3075 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, 0); 3076 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3077 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3078 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3079 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, 0); 3080 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3081 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, 0); 3082 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, 0); 3083 MVSATA_EDMA_WRITE_4(mvport, EDMA_TC, 0); 3084 MVSATA_EDMA_WRITE_4(mvport, EDMA_IORT, 0xbc); 3085 3086 MVSATA_EDMA_WRITE_4(mvport, SATA_FISIC, 0); 3087 } 3088 3089 static void 3090 mvsata_reset_hc(struct mvsata_hc *mvhc) 3091 { 3092 #if 0 3093 uint32_t val; 3094 #endif 3095 3096 MVSATA_HC_WRITE_4(mvhc, SATAHC_ICT, 0); 3097 MVSATA_HC_WRITE_4(mvhc, SATAHC_ITT, 0); 3098 MVSATA_HC_WRITE_4(mvhc, SATAHC_IC, 0); 3099 3100 #if 0 /* XXXX needs? */ 3101 MVSATA_HC_WRITE_4(mvhc, 0x01c, 0); 3102 3103 /* 3104 * Keep the SS during power on and the reference clock bits (reset 3105 * sample) 3106 */ 3107 val = MVSATA_HC_READ_4(mvhc, 0x020); 3108 val &= 0x1c1c1c1c; 3109 val |= 0x03030303; 3110 MVSATA_HC_READ_4(mvhc, 0x020, 0); 3111 #endif 3112 } 3113 3114 #ifndef MVSATA_WITHOUTDMA 3115 static void 3116 mvsata_softreset(struct mvsata_port *mvport, int waitok) 3117 { 3118 uint32_t stat; 3119 int i; 3120 3121 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_RST | WDCTL_IDS); 3122 delay(10); 3123 MVSATA_WDC_WRITE_1(mvport, SRB_CAS, WDCTL_IDS); 3124 delay(2000); 3125 3126 if (waitok) { 3127 /* wait maximum 31sec */ 3128 for (i = 31000; i > 0; i--) { 3129 stat = MVSATA_WDC_READ_1(mvport, SRB_CS); 3130 if (!(stat & WDCS_BSY)) 3131 break; 3132 delay(1000); 3133 } 3134 if (i == 0) 3135 aprint_error("%s:%d:%d: soft reset failed\n", 3136 device_xname(MVSATA_DEV2(mvport)), 3137 mvport->port_hc->hc, mvport->port); 3138 } 3139 } 3140 3141 static void 3142 mvsata_edma_reset_qptr(struct mvsata_port *mvport) 3143 { 3144 const bus_addr_t crpb_addr = 3145 mvport->port_crpb_dmamap->dm_segs[0].ds_addr; 3146 const uint32_t crpb_addr_mask = 3147 EDMA_RESQP_ERPQBAP_MASK | EDMA_RESQP_ERPQBA_MASK; 3148 3149 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQBAH, 0); 3150 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQIP, 0); 3151 MVSATA_EDMA_WRITE_4(mvport, EDMA_REQQOP, 0); 3152 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQBAH, (crpb_addr >> 16) >> 16); 3153 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQIP, 0); 3154 MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, (crpb_addr & crpb_addr_mask)); 3155 } 3156 3157 static inline void 3158 mvsata_edma_enable(struct mvsata_port *mvport) 3159 { 3160 3161 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EENEDMA); 3162 } 3163 3164 static int 3165 mvsata_edma_disable(struct mvsata_port *mvport, int timeout, int waitok) 3166 { 3167 uint32_t status, command; 3168 int ms; 3169 3170 if (MVSATA_EDMA_READ_4(mvport, EDMA_CMD) & EDMA_CMD_EENEDMA) { 3171 for (ms = 0; ms < timeout; ms++) { 3172 status = MVSATA_EDMA_READ_4(mvport, EDMA_S); 3173 if (status & EDMA_S_EDMAIDLE) 3174 break; 3175 if (waitok) 3176 tsleep(&waitok, PRIBIO, "mvsata_edma1", 3177 mstohz(1)); 3178 else 3179 delay(1000); 3180 } 3181 if (ms == timeout) 3182 return EBUSY; 3183 3184 /* The diable bit (eDsEDMA) is self negated. */ 3185 MVSATA_EDMA_WRITE_4(mvport, EDMA_CMD, EDMA_CMD_EDSEDMA); 3186 3187 for ( ; ms < timeout; ms++) { 3188 command = MVSATA_EDMA_READ_4(mvport, EDMA_CMD); 3189 if (!(command & EDMA_CMD_EENEDMA)) 3190 break; 3191 if (waitok) 3192 tsleep(&waitok, PRIBIO, "mvsata_edma2", 3193 mstohz(1)); 3194 else 3195 delay(1000); 3196 } 3197 if (ms == timeout) { 3198 aprint_error("%s:%d:%d: unable to stop EDMA\n", 3199 device_xname(MVSATA_DEV2(mvport)), 3200 mvport->port_hc->hc, mvport->port); 3201 return EBUSY; 3202 } 3203 } 3204 return 0; 3205 } 3206 3207 /* 3208 * Set EDMA registers according to mode. 3209 * ex. NCQ/TCQ(queued)/non queued. 3210 */ 3211 static void 3212 mvsata_edma_config(struct mvsata_port *mvport, int mode) 3213 { 3214 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3215 uint32_t reg; 3216 3217 reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG); 3218 reg |= EDMA_CFG_RESERVED; 3219 3220 if (mode == ncq) { 3221 if (sc->sc_gen == gen1) { 3222 aprint_error_dev(MVSATA_DEV2(mvport), 3223 "GenI not support NCQ\n"); 3224 return; 3225 } else if (sc->sc_gen == gen2) 3226 reg |= EDMA_CFG_EDEVERR; 3227 reg |= EDMA_CFG_ESATANATVCMDQUE; 3228 } else if (mode == queued) { 3229 reg &= ~EDMA_CFG_ESATANATVCMDQUE; 3230 reg |= EDMA_CFG_EQUE; 3231 } else 3232 reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE); 3233 3234 if (sc->sc_gen == gen1) 3235 reg |= EDMA_CFG_ERDBSZ; 3236 else if (sc->sc_gen == gen2) 3237 reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN); 3238 else if (sc->sc_gen == gen2e) { 3239 device_t parent = device_parent(MVSATA_DEV(sc)); 3240 3241 reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN); 3242 reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN); 3243 3244 if (device_is_a(parent, "pci")) 3245 reg |= ( 3246 #if NATAPIBUS > 0 3247 EDMA_CFG_EEARLYCOMPLETIONEN | 3248 #endif 3249 EDMA_CFG_ECUTTHROUGHEN | 3250 EDMA_CFG_EWRBUFFERLEN | 3251 EDMA_CFG_ERDBSZEXT); 3252 } 3253 MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg); 3254 3255 reg = ( 3256 EDMA_IE_EIORDYERR | 3257 EDMA_IE_ETRANSINT | 3258 EDMA_IE_EDEVCON | 3259 EDMA_IE_EDEVDIS); 3260 if (sc->sc_gen != gen1) 3261 reg |= ( 3262 EDMA_IE_TRANSPROTERR | 3263 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKTXERR_FISTXABORTED) | 3264 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3265 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3266 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3267 EDMA_IE_LINKDATATXERR(EDMA_IE_LINKXERR_SATACRC) | 3268 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3269 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3270 EDMA_IE_LINKCTLTXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3271 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3272 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3273 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3274 EDMA_IE_LINKDATARXERR(EDMA_IE_LINKXERR_SATACRC) | 3275 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_OTHERERRORS) | 3276 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_LINKLAYERRESET) | 3277 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_INTERNALFIFO) | 3278 EDMA_IE_LINKCTLRXERR(EDMA_IE_LINKXERR_SATACRC) | 3279 EDMA_IE_ESELFDIS); 3280 3281 if (mode == ncq) 3282 reg |= EDMA_IE_EDEVERR; 3283 MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg); 3284 reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC); 3285 reg &= ~EDMA_IE_EDEVERR; 3286 if (mode != ncq) 3287 reg |= EDMA_IE_EDEVERR; 3288 MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg); 3289 if (sc->sc_gen == gen2e) { 3290 /* 3291 * Clear FISWait4HostRdyEn[0] and [2]. 3292 * [0]: Device to Host FIS with <ERR> or <DF> bit set to 1. 3293 * [2]: SDB FIS is received with <ERR> bit set to 1. 3294 */ 3295 reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC); 3296 reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 | 3297 SATA_FISC_FISWAIT4HOSTRDYEN_B2); 3298 MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg); 3299 } 3300 3301 mvport->port_edmamode = mode; 3302 } 3303 3304 3305 /* 3306 * Generation dependent functions 3307 */ 3308 3309 static void 3310 mvsata_edma_setup_crqb(struct mvsata_port *mvport, int erqqip, int quetag, 3311 struct ata_bio *ata_bio) 3312 { 3313 struct crqb *crqb; 3314 bus_addr_t eprd_addr; 3315 daddr_t blkno; 3316 uint32_t rw; 3317 uint8_t cmd, head; 3318 int i; 3319 const int drive = 3320 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3321 3322 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3323 mvport->port_reqtbl[quetag].eprd_offset; 3324 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3325 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3326 head = WDSD_LBA; 3327 blkno = ata_bio->blkno; 3328 if (ata_bio->flags & ATA_LBA48) 3329 cmd = atacmd_to48(cmd); 3330 else { 3331 head |= ((ata_bio->blkno >> 24) & 0xf); 3332 blkno &= 0xffffff; 3333 } 3334 crqb = &mvport->port_crqb->crqb + erqqip; 3335 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3336 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3337 crqb->ctrlflg = 3338 htole16(rw | CRQB_CHOSTQUETAG(quetag) | CRQB_CPMPORT(drive)); 3339 i = 0; 3340 if (mvport->port_edmamode == dma) { 3341 if (ata_bio->flags & ATA_LBA48) 3342 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3343 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks >> 8)); 3344 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3345 CRQB_ATACOMMAND_SECTORCOUNT, ata_bio->nblks)); 3346 } else { /* ncq/queued */ 3347 3348 /* 3349 * XXXX: Oops, ata command is not correct. And, atabus layer 3350 * has not been supported yet now. 3351 * Queued DMA read/write. 3352 * read/write FPDMAQueued. 3353 */ 3354 3355 if (ata_bio->flags & ATA_LBA48) 3356 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3357 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks >> 8)); 3358 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3359 CRQB_ATACOMMAND_FEATURES, ata_bio->nblks)); 3360 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3361 CRQB_ATACOMMAND_SECTORCOUNT, quetag << 3)); 3362 } 3363 if (ata_bio->flags & ATA_LBA48) { 3364 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3365 CRQB_ATACOMMAND_LBALOW, blkno >> 24)); 3366 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3367 CRQB_ATACOMMAND_LBAMID, blkno >> 32)); 3368 crqb->atacommand[i++] = htole16(CRQB_ATACOMMAND( 3369 CRQB_ATACOMMAND_LBAHIGH, blkno >> 40)); 3370 } 3371 crqb->atacommand[i++] = 3372 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBALOW, blkno)); 3373 crqb->atacommand[i++] = 3374 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAMID, blkno >> 8)); 3375 crqb->atacommand[i++] = 3376 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_LBAHIGH, blkno >> 16)); 3377 crqb->atacommand[i++] = 3378 htole16(CRQB_ATACOMMAND(CRQB_ATACOMMAND_DEVICE, head)); 3379 crqb->atacommand[i++] = htole16( 3380 CRQB_ATACOMMAND(CRQB_ATACOMMAND_COMMAND, cmd) | 3381 CRQB_ATACOMMAND_LAST); 3382 } 3383 #endif 3384 3385 static uint32_t 3386 mvsata_read_preamps_gen1(struct mvsata_port *mvport) 3387 { 3388 struct mvsata_hc *hc = mvport->port_hc; 3389 uint32_t reg; 3390 3391 reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port)); 3392 /* 3393 * [12:11] : pre 3394 * [7:5] : amps 3395 */ 3396 return reg & 0x000018e0; 3397 } 3398 3399 static void 3400 mvsata_fix_phy_gen1(struct mvsata_port *mvport) 3401 { 3402 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3403 struct mvsata_hc *mvhc = mvport->port_hc; 3404 uint32_t reg; 3405 int port = mvport->port, fix_apm_sq = 0; 3406 3407 if (sc->sc_model == PCI_PRODUCT_MARVELL_88SX5080) { 3408 if (sc->sc_rev == 0x01) 3409 fix_apm_sq = 1; 3410 } else { 3411 if (sc->sc_rev == 0x00) 3412 fix_apm_sq = 1; 3413 } 3414 3415 if (fix_apm_sq) { 3416 /* 3417 * Disable auto-power management 3418 * 88SX50xx FEr SATA#12 3419 */ 3420 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port)); 3421 reg |= (1 << 19); 3422 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg); 3423 3424 /* 3425 * Fix squelch threshold 3426 * 88SX50xx FEr SATA#9 3427 */ 3428 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port)); 3429 reg &= ~0x3; 3430 reg |= 0x1; 3431 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg); 3432 } 3433 3434 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3435 reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port)); 3436 reg &= ~0x000018e0; /* pre and amps mask */ 3437 reg |= mvport->_fix_phy_param.pre_amps; 3438 MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg); 3439 } 3440 3441 static void 3442 mvsata_devconn_gen1(struct mvsata_port *mvport) 3443 { 3444 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3445 3446 /* Fix for 88SX50xx FEr SATA#2 */ 3447 mvport->_fix_phy_param._fix_phy(mvport); 3448 3449 /* If disk is connected, then enable the activity LED */ 3450 if (sc->sc_rev == 0x03) { 3451 /* XXXXX */ 3452 } 3453 } 3454 3455 static uint32_t 3456 mvsata_read_preamps_gen2(struct mvsata_port *mvport) 3457 { 3458 uint32_t reg; 3459 3460 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3461 /* 3462 * [10:8] : amps 3463 * [7:5] : pre 3464 */ 3465 return reg & 0x000007e0; 3466 } 3467 3468 static void 3469 mvsata_fix_phy_gen2(struct mvsata_port *mvport) 3470 { 3471 struct mvsata_softc *sc = device_private(MVSATA_DEV2(mvport)); 3472 uint32_t reg; 3473 3474 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3475 sc->sc_gen == gen2e) { 3476 /* 3477 * Fix for 3478 * 88SX60X1 FEr SATA #23 3479 * 88SX6042/88SX7042 FEr SATA #23 3480 * 88F5182 FEr #SATA-S13 3481 * 88F5082 FEr #SATA-S13 3482 */ 3483 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3484 reg &= ~(1 << 16); 3485 reg |= (1 << 31); 3486 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3487 3488 delay(200); 3489 3490 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3491 reg &= ~((1 << 16) | (1 << 31)); 3492 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3493 3494 delay(200); 3495 } 3496 3497 /* Fix values in PHY Mode 3 Register.*/ 3498 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3499 reg &= ~0x7F900000; 3500 reg |= 0x2A800000; 3501 /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ 3502 if (sc->sc_model == PCI_PRODUCT_MARVELL_88F5082 || 3503 sc->sc_model == PCI_PRODUCT_MARVELL_88F5182 || 3504 sc->sc_model == PCI_PRODUCT_MARVELL_88F6082) 3505 reg &= ~0x0000001c; 3506 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg); 3507 3508 /* 3509 * Fix values in PHY Mode 4 Register. 3510 * 88SX60x1 FEr SATA#10 3511 * 88F5182 GL #SATA-S10 3512 * 88F5082 GL #SATA-S10 3513 */ 3514 if ((sc->sc_gen == gen2 && sc->sc_rev == 0x07) || 3515 sc->sc_gen == gen2e) { 3516 uint32_t tmp = 0; 3517 3518 /* 88SX60x1 FEr SATA #13 */ 3519 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3520 tmp = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3); 3521 3522 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4); 3523 reg |= (1 << 0); 3524 reg &= ~(1 << 1); 3525 /* PHY Mode 4 Register of Gen IIE has some restriction */ 3526 if (sc->sc_gen == gen2e) { 3527 reg &= ~0x5de3fffc; 3528 reg |= (1 << 2); 3529 } 3530 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg); 3531 3532 /* 88SX60x1 FEr SATA #13 */ 3533 if (sc->sc_gen == 2 && sc->sc_rev == 0x07) 3534 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, tmp); 3535 } 3536 3537 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3538 reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2); 3539 reg &= ~0x000007e0; /* pre and amps mask */ 3540 reg |= mvport->_fix_phy_param.pre_amps; 3541 reg &= ~(1 << 16); 3542 if (sc->sc_gen == gen2e) { 3543 /* 3544 * according to mvSata 3.6.1, some IIE values are fixed. 3545 * some reserved fields must be written with fixed values. 3546 */ 3547 reg &= ~0xC30FF01F; 3548 reg |= 0x0000900F; 3549 } 3550 MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg); 3551 } 3552 3553 #ifndef MVSATA_WITHOUTDMA 3554 static void 3555 mvsata_edma_setup_crqb_gen2e(struct mvsata_port *mvport, int erqqip, int quetag, 3556 struct ata_bio *ata_bio) 3557 { 3558 struct crqb_gen2e *crqb; 3559 bus_addr_t eprd_addr; 3560 daddr_t blkno; 3561 uint32_t ctrlflg, rw; 3562 uint8_t cmd, head; 3563 const int drive = 3564 mvport->port_ata_channel.ch_queue->active_xfer->c_drive; 3565 3566 eprd_addr = mvport->port_eprd_dmamap->dm_segs[0].ds_addr + 3567 mvport->port_reqtbl[quetag].eprd_offset; 3568 rw = (ata_bio->flags & ATA_READ) ? CRQB_CDIR_READ : CRQB_CDIR_WRITE; 3569 ctrlflg = (rw | CRQB_CDEVICEQUETAG(quetag) | CRQB_CPMPORT(drive) | 3570 CRQB_CPRDMODE_EPRD | CRQB_CHOSTQUETAG_GEN2(quetag)); 3571 cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 3572 head = WDSD_LBA; 3573 blkno = ata_bio->blkno; 3574 if (ata_bio->flags & ATA_LBA48) 3575 cmd = atacmd_to48(cmd); 3576 else { 3577 head |= ((ata_bio->blkno >> 24) & 0xf); 3578 blkno &= 0xffffff; 3579 } 3580 crqb = &mvport->port_crqb->crqb_gen2e + erqqip; 3581 crqb->cprdbl = htole32(eprd_addr & CRQB_CRQBL_EPRD_MASK); 3582 crqb->cprdbh = htole32((eprd_addr >> 16) >> 16); 3583 crqb->ctrlflg = htole32(ctrlflg); 3584 if (mvport->port_edmamode == dma) { 3585 crqb->atacommand[0] = htole32(cmd << 16); 3586 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3587 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff)); 3588 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3589 } else { /* ncq/queued */ 3590 3591 /* 3592 * XXXX: Oops, ata command is not correct. And, atabus layer 3593 * has not been supported yet now. 3594 * Queued DMA read/write. 3595 * read/write FPDMAQueued. 3596 */ 3597 3598 crqb->atacommand[0] = htole32( 3599 (cmd << 16) | ((ata_bio->nblks & 0xff) << 24)); 3600 crqb->atacommand[1] = htole32((blkno & 0xffffff) | head << 24); 3601 crqb->atacommand[2] = htole32(((blkno >> 24) & 0xffffff) | 3602 ((ata_bio->nblks >> 8) & 0xff)); 3603 crqb->atacommand[3] = htole32(ata_bio->nblks & 0xffff); 3604 crqb->atacommand[3] = htole32(quetag << 3); 3605 } 3606 } 3607 3608 3609 #ifdef MVSATA_DEBUG 3610 #define MVSATA_DEBUG_PRINT(type, size, n, p) \ 3611 do { \ 3612 int _i; \ 3613 u_char *_p = (p); \ 3614 \ 3615 printf(#type "(%d)", (n)); \ 3616 for (_i = 0; _i < (size); _i++, _p++) { \ 3617 if (_i % 16 == 0) \ 3618 printf("\n "); \ 3619 printf(" %02x", *_p); \ 3620 } \ 3621 printf("\n"); \ 3622 } while (0 /* CONSTCOND */) 3623 3624 static void 3625 mvsata_print_crqb(struct mvsata_port *mvport, int n) 3626 { 3627 3628 MVSATA_DEBUG_PRINT(crqb, sizeof(union mvsata_crqb), 3629 n, (u_char *)(mvport->port_crqb + n)); 3630 } 3631 3632 static void 3633 mvsata_print_crpb(struct mvsata_port *mvport, int n) 3634 { 3635 3636 MVSATA_DEBUG_PRINT(crpb, sizeof(struct crpb), 3637 n, (u_char *)(mvport->port_crpb + n)); 3638 } 3639 3640 static void 3641 mvsata_print_eprd(struct mvsata_port *mvport, int n) 3642 { 3643 struct eprd *eprd; 3644 int i = 0; 3645 3646 eprd = mvport->port_reqtbl[n].eprd; 3647 while (1 /*CONSTCOND*/) { 3648 MVSATA_DEBUG_PRINT(eprd, sizeof(struct eprd), 3649 i, (u_char *)eprd); 3650 if (eprd->eot & EPRD_EOT) 3651 break; 3652 eprd++; 3653 i++; 3654 } 3655 } 3656 #endif 3657 #endif 3658
Indexes created Mon Sep 22 21:09:42 GMT 2025