mx98905.c revision 1.11.6.2 1 1.11.6.1 mjf /* $NetBSD: mx98905.c,v 1.11.6.2 2008/06/02 13:23:25 mjf Exp $ */
2 1.1 bjh21
3 1.1 bjh21 /*-
4 1.1 bjh21 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5 1.1 bjh21 * All rights reserved.
6 1.1 bjh21 *
7 1.1 bjh21 * This code is derived from software contributed to The NetBSD Foundation
8 1.1 bjh21 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.1 bjh21 * NASA Ames Research Center.
10 1.1 bjh21 *
11 1.1 bjh21 * Redistribution and use in source and binary forms, with or without
12 1.1 bjh21 * modification, are permitted provided that the following conditions
13 1.1 bjh21 * are met:
14 1.1 bjh21 * 1. Redistributions of source code must retain the above copyright
15 1.1 bjh21 * notice, this list of conditions and the following disclaimer.
16 1.1 bjh21 * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 bjh21 * notice, this list of conditions and the following disclaimer in the
18 1.1 bjh21 * documentation and/or other materials provided with the distribution.
19 1.1 bjh21 *
20 1.1 bjh21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 1.1 bjh21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 1.1 bjh21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 1.1 bjh21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 1.1 bjh21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 1.1 bjh21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 1.1 bjh21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 1.1 bjh21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 1.1 bjh21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 1.1 bjh21 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 1.1 bjh21 * POSSIBILITY OF SUCH DAMAGE.
31 1.1 bjh21 */
32 1.1 bjh21
33 1.1 bjh21 /*
34 1.1 bjh21 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
35 1.1 bjh21 * adapters.
36 1.1 bjh21 *
37 1.1 bjh21 * Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved.
38 1.1 bjh21 *
39 1.1 bjh21 * Copyright (C) 1993, David Greenman. This software may be used, modified,
40 1.1 bjh21 * copied, distributed, and sold, in both source and binary form provided that
41 1.1 bjh21 * the above copyright and these terms are retained. Under no circumstances is
42 1.1 bjh21 * the author responsible for the proper functioning of this software, nor does
43 1.1 bjh21 * the author assume any responsibility for damages incurred with its use.
44 1.1 bjh21 */
45 1.1 bjh21
46 1.1 bjh21 /*
47 1.1 bjh21 * Special routines for the Macronix MX 98905. For use with the "ne" driver.
48 1.1 bjh21 */
49 1.1 bjh21
50 1.1 bjh21 /*
51 1.5 keihan * <URL:http://mail-index.NetBSD.org/port-arm32/1996/06/23/0005.html>:
52 1.1 bjh21 * There are 2 types of etherh card. One uses the macronics chipset MX98905
53 1.4 wiz * and that chipset has a bug in it, in that it the MSB remote DMA
54 1.1 bjh21 * register does not work. There is a workaround for this which
55 1.1 bjh21 * should be around soon. In fact, I think only the buffer ram test
56 1.4 wiz * ever transfers more than 256 bytes across the DMA channel, so diabling
57 1.1 bjh21 * it will make the mx stuff work.
58 1.1 bjh21 */
59 1.1 bjh21
60 1.1 bjh21 #include <sys/param.h>
61 1.1 bjh21
62 1.11.6.1 mjf __KERNEL_RCSID(0, "$NetBSD: mx98905.c,v 1.11.6.2 2008/06/02 13:23:25 mjf Exp $");
63 1.1 bjh21
64 1.1 bjh21 #include <sys/device.h>
65 1.1 bjh21 #include <sys/mbuf.h>
66 1.1 bjh21 #include <sys/socket.h>
67 1.1 bjh21 #include <sys/syslog.h>
68 1.1 bjh21 #include <sys/systm.h>
69 1.1 bjh21
70 1.1 bjh21 #include <net/if.h>
71 1.1 bjh21 #include <net/if_ether.h>
72 1.1 bjh21 #include <net/if_media.h>
73 1.1 bjh21
74 1.10 ad #include <sys/bus.h>
75 1.1 bjh21
76 1.1 bjh21 #include <dev/ic/dp8390reg.h>
77 1.1 bjh21 #include <dev/ic/dp8390var.h>
78 1.1 bjh21 #include <dev/ic/ne2000reg.h>
79 1.1 bjh21 #include <dev/ic/ne2000var.h>
80 1.1 bjh21 #include <dev/ic/mx98905var.h>
81 1.1 bjh21
82 1.1 bjh21 #ifndef __BUS_SPACE_HAS_STREAM_METHODS
83 1.1 bjh21 #define bus_space_write_stream_2 bus_space_write_2
84 1.1 bjh21 #define bus_space_write_multi_stream_2 bus_space_write_multi_2
85 1.1 bjh21 #define bus_space_read_multi_stream_2 bus_space_read_multi_2
86 1.1 bjh21 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */
87 1.2 bjh21
88 1.8 perry static inline void mx98905_write_setup(struct dp8390_softc *, int, int);
89 1.8 perry static inline void mx98905_write_wait(struct dp8390_softc *);
90 1.1 bjh21
91 1.1 bjh21 void
92 1.1 bjh21 mx98905_attach(struct dp8390_softc *sc)
93 1.1 bjh21 {
94 1.1 bjh21
95 1.1 bjh21 sc->ring_copy = mx98905_ring_copy;
96 1.1 bjh21 sc->write_mbuf = mx98905_write_mbuf;
97 1.1 bjh21 sc->read_hdr = mx98905_read_hdr;
98 1.1 bjh21 }
99 1.1 bjh21
100 1.8 perry static inline void
101 1.1 bjh21 mx98905_write_setup(sc, len, buf)
102 1.1 bjh21 struct dp8390_softc *sc;
103 1.1 bjh21 int len, buf;
104 1.1 bjh21 {
105 1.1 bjh21 bus_space_tag_t nict = sc->sc_regt;
106 1.1 bjh21 bus_space_handle_t nich = sc->sc_regh;
107 1.1 bjh21
108 1.1 bjh21 /* Select page 0 registers. */
109 1.1 bjh21 NIC_BARRIER(nict, nich);
110 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_CR,
111 1.1 bjh21 ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
112 1.1 bjh21 NIC_BARRIER(nict, nich);
113 1.1 bjh21
114 1.1 bjh21 /* Reset remote DMA complete flag. */
115 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_ISR, ED_ISR_RDC);
116 1.1 bjh21 NIC_BARRIER(nict, nich);
117 1.1 bjh21
118 1.1 bjh21 /* Set up DMA byte count. */
119 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RBCR0, len);
120 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RBCR1, len >> 8);
121 1.1 bjh21
122 1.1 bjh21 /* Set up destination address in NIC mem. */
123 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RSAR0, buf);
124 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RSAR1, buf >> 8);
125 1.1 bjh21
126 1.1 bjh21 /* Set remote DMA write. */
127 1.1 bjh21 NIC_BARRIER(nict, nich);
128 1.1 bjh21 bus_space_write_1(nict, nich,
129 1.1 bjh21 ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
130 1.1 bjh21 NIC_BARRIER(nict, nich);
131 1.1 bjh21 }
132 1.1 bjh21
133 1.1 bjh21
134 1.8 perry static inline void
135 1.1 bjh21 mx98905_write_wait(sc)
136 1.1 bjh21 struct dp8390_softc *sc;
137 1.1 bjh21 {
138 1.1 bjh21 int maxwait = 100; /* about 120us */
139 1.1 bjh21 bus_space_tag_t nict = sc->sc_regt;
140 1.1 bjh21 bus_space_handle_t nich = sc->sc_regh;
141 1.1 bjh21
142 1.1 bjh21 /*
143 1.1 bjh21 * Wait for remote DMA to complete. This is necessary because on the
144 1.1 bjh21 * transmit side, data is handled internally by the NIC in bursts, and
145 1.1 bjh21 * we can't start another remote DMA until this one completes. Not
146 1.1 bjh21 * waiting causes really bad things to happen - like the NIC wedging
147 1.1 bjh21 * the bus.
148 1.1 bjh21 */
149 1.1 bjh21 while (((bus_space_read_1(nict, nich, ED_P0_ISR) & ED_ISR_RDC) !=
150 1.1 bjh21 ED_ISR_RDC) && --maxwait) {
151 1.1 bjh21 bus_space_read_1(nict, nich, ED_P0_CRDA1);
152 1.1 bjh21 bus_space_read_1(nict, nich, ED_P0_CRDA0);
153 1.1 bjh21 NIC_BARRIER(nict, nich);
154 1.1 bjh21 DELAY(1);
155 1.1 bjh21 }
156 1.1 bjh21
157 1.1 bjh21 if (maxwait == 0) {
158 1.1 bjh21 log(LOG_WARNING,
159 1.1 bjh21 "%s: remote transmit DMA failed to complete\n",
160 1.11.6.1 mjf device_xname(sc->sc_dev));
161 1.1 bjh21 dp8390_reset(sc);
162 1.1 bjh21 }
163 1.1 bjh21 }
164 1.1 bjh21
165 1.1 bjh21 /*
166 1.1 bjh21 * Write an mbuf chain to the destination NIC memory address using programmed
167 1.1 bjh21 * I/O.
168 1.1 bjh21 */
169 1.1 bjh21 int
170 1.1 bjh21 mx98905_write_mbuf(sc, m, buf)
171 1.1 bjh21 struct dp8390_softc *sc;
172 1.1 bjh21 struct mbuf *m;
173 1.1 bjh21 int buf;
174 1.1 bjh21 {
175 1.1 bjh21 struct ne2000_softc *nsc = (struct ne2000_softc *)sc;
176 1.1 bjh21 bus_space_tag_t nict = sc->sc_regt;
177 1.1 bjh21 bus_space_handle_t nich = sc->sc_regh;
178 1.1 bjh21 bus_space_tag_t asict = nsc->sc_asict;
179 1.1 bjh21 bus_space_handle_t asich = nsc->sc_asich;
180 1.1 bjh21 int savelen, dmalen, resid, len;
181 1.1 bjh21 u_int8_t *data, savebyte[2];
182 1.1 bjh21 int l, leftover;
183 1.1 bjh21 #ifdef DIAGNOSTIC
184 1.1 bjh21 u_int8_t *lim;
185 1.1 bjh21 #endif
186 1.3 bouyer int i;
187 1.1 bjh21
188 1.1 bjh21 resid = savelen = m->m_pkthdr.len;
189 1.1 bjh21
190 1.1 bjh21 dmalen = min(resid, 254);
191 1.1 bjh21
192 1.1 bjh21 mx98905_write_setup(sc, dmalen, buf);
193 1.1 bjh21
194 1.1 bjh21 buf += dmalen;
195 1.1 bjh21 resid -= dmalen;
196 1.1 bjh21
197 1.1 bjh21 /*
198 1.1 bjh21 * Transfer the mbuf chain to the NIC memory. NE2000 cards
199 1.1 bjh21 * require that data be transferred as words, and only words,
200 1.1 bjh21 * so that case requires some extra code to patch over odd-length
201 1.1 bjh21 * mbufs.
202 1.1 bjh21 */
203 1.1 bjh21 /* NE2000s are a bit trickier. */
204 1.1 bjh21 /* Start out with no leftover data. */
205 1.1 bjh21 leftover = 0;
206 1.1 bjh21 savebyte[0] = savebyte[1] = 0;
207 1.1 bjh21
208 1.1 bjh21 for (; m != 0; m = m->m_next) {
209 1.1 bjh21 l = m->m_len;
210 1.1 bjh21 if (l == 0)
211 1.1 bjh21 continue;
212 1.1 bjh21 data = mtod(m, u_int8_t *);
213 1.1 bjh21 #ifdef DIAGNOSTIC
214 1.1 bjh21 lim = data + l;
215 1.1 bjh21 #endif
216 1.1 bjh21 while (l > 0) {
217 1.1 bjh21 if (leftover) {
218 1.1 bjh21 /*
219 1.1 bjh21 * Data left over (from mbuf or
220 1.1 bjh21 * realignment). Buffer the next
221 1.1 bjh21 * byte, and write it and the leftover
222 1.1 bjh21 * data out.
223 1.1 bjh21 */
224 1.1 bjh21 savebyte[1] = *data++;
225 1.1 bjh21 l--;
226 1.1 bjh21 bus_space_write_stream_2(asict, asich,
227 1.1 bjh21 NE2000_ASIC_DATA, *(u_int16_t *)savebyte);
228 1.1 bjh21 dmalen -= 2;
229 1.1 bjh21 leftover = 0;
230 1.1 bjh21 } else if (BUS_SPACE_ALIGNED_POINTER(data,
231 1.1 bjh21 u_int16_t) == 0) {
232 1.1 bjh21 /* Unaligned data; buffer the next byte. */
233 1.1 bjh21 savebyte[0] = *data++;
234 1.1 bjh21 l--;
235 1.1 bjh21 leftover = 1;
236 1.1 bjh21 } else {
237 1.1 bjh21 /*
238 1.1 bjh21 * Aligned data; output contiguous
239 1.1 bjh21 * words as much as we can, then
240 1.1 bjh21 * buffer the remaining byte, if any.
241 1.1 bjh21 */
242 1.1 bjh21 len = min(l, dmalen);
243 1.1 bjh21 leftover = len & 1;
244 1.1 bjh21 len &= ~1;
245 1.1 bjh21 bus_space_write_multi_stream_2(asict,
246 1.1 bjh21 asich, NE2000_ASIC_DATA,
247 1.1 bjh21 (u_int16_t *)data, len >> 1);
248 1.1 bjh21 dmalen -= len;
249 1.1 bjh21 data += len;
250 1.1 bjh21 if (leftover)
251 1.1 bjh21 savebyte[0] = *data++;
252 1.1 bjh21 l -= len + leftover;
253 1.1 bjh21 }
254 1.1 bjh21 if (dmalen == 0 && resid > 0) {
255 1.1 bjh21 mx98905_write_wait(sc);
256 1.1 bjh21 dmalen = min(resid, 254);
257 1.1 bjh21
258 1.1 bjh21 mx98905_write_setup(sc, dmalen, buf);
259 1.1 bjh21
260 1.1 bjh21 buf += dmalen;
261 1.1 bjh21 resid -= dmalen;
262 1.1 bjh21 }
263 1.1 bjh21 }
264 1.1 bjh21 if (l < 0)
265 1.1 bjh21 panic("mx98905_write_mbuf: negative len");
266 1.1 bjh21 #ifdef DIAGNOSTIC
267 1.1 bjh21 if (data != lim)
268 1.1 bjh21 panic("mx98905_write_mbuf: data != lim");
269 1.1 bjh21 #endif
270 1.1 bjh21 }
271 1.1 bjh21 if (leftover) {
272 1.1 bjh21 savebyte[1] = 0;
273 1.1 bjh21 bus_space_write_stream_2(asict, asich, NE2000_ASIC_DATA,
274 1.1 bjh21 *(u_int16_t *)savebyte);
275 1.3 bouyer }
276 1.3 bouyer if (savelen < ETHER_MIN_LEN - ETHER_CRC_LEN) {
277 1.3 bouyer for(i = 0; i < (ETHER_MIN_LEN - ETHER_CRC_LEN - savelen) >> 1;
278 1.3 bouyer i++)
279 1.3 bouyer bus_space_write_stream_2(asict, asich,
280 1.3 bouyer NE2000_ASIC_DATA, 0);
281 1.3 bouyer savelen = ETHER_MIN_LEN - ETHER_CRC_LEN;
282 1.1 bjh21 }
283 1.1 bjh21 NIC_BARRIER(nict, nich);
284 1.1 bjh21
285 1.1 bjh21 mx98905_write_wait(sc);
286 1.1 bjh21
287 1.1 bjh21 return (savelen);
288 1.1 bjh21 }
289 1.1 bjh21
290 1.1 bjh21 /*
291 1.1 bjh21 * Given a source and destination address, copy 'amout' of a packet from
292 1.1 bjh21 * the ring buffer into a linear destination buffer. Takes into account
293 1.1 bjh21 * ring-wrap.
294 1.1 bjh21 */
295 1.1 bjh21 int
296 1.11 matt mx98905_ring_copy(sc, src, vdst, amount)
297 1.1 bjh21 struct dp8390_softc *sc;
298 1.1 bjh21 int src;
299 1.11 matt void *vdst;
300 1.1 bjh21 u_short amount;
301 1.1 bjh21 {
302 1.1 bjh21 struct ne2000_softc *nsc = (struct ne2000_softc *)sc;
303 1.11 matt uint8_t *dst = vdst;
304 1.1 bjh21 bus_space_tag_t nict = sc->sc_regt;
305 1.1 bjh21 bus_space_handle_t nich = sc->sc_regh;
306 1.1 bjh21 bus_space_tag_t asict = nsc->sc_asict;
307 1.1 bjh21 bus_space_handle_t asich = nsc->sc_asich;
308 1.1 bjh21 u_short tmp_amount;
309 1.6 he int useword = nsc->sc_useword;
310 1.1 bjh21
311 1.1 bjh21 /* Does copy wrap to lower addr in ring buffer? */
312 1.1 bjh21 if (src + amount > sc->mem_end) {
313 1.1 bjh21 tmp_amount = sc->mem_end - src;
314 1.1 bjh21
315 1.1 bjh21 /* Copy amount up to end of NIC memory. */
316 1.1 bjh21 mx98905_readmem(nict, nich, asict, asich, src,
317 1.1 bjh21 (u_int8_t *)dst, tmp_amount, useword);
318 1.1 bjh21
319 1.1 bjh21 amount -= tmp_amount;
320 1.1 bjh21 src = sc->mem_ring;
321 1.1 bjh21 dst += tmp_amount;
322 1.1 bjh21 }
323 1.1 bjh21
324 1.11 matt mx98905_readmem(nict, nich, asict, asich, src, dst, amount, useword);
325 1.1 bjh21
326 1.1 bjh21 return (src + amount);
327 1.1 bjh21 }
328 1.1 bjh21
329 1.1 bjh21 void
330 1.1 bjh21 mx98905_read_hdr(sc, buf, hdr)
331 1.1 bjh21 struct dp8390_softc *sc;
332 1.1 bjh21 int buf;
333 1.1 bjh21 struct dp8390_ring *hdr;
334 1.1 bjh21 {
335 1.1 bjh21 struct ne2000_softc *nsc = (struct ne2000_softc *)sc;
336 1.1 bjh21
337 1.1 bjh21 mx98905_readmem(sc->sc_regt, sc->sc_regh, nsc->sc_asict, nsc->sc_asich,
338 1.1 bjh21 buf, (u_int8_t *)hdr, sizeof(struct dp8390_ring),
339 1.6 he nsc->sc_useword);
340 1.1 bjh21 #if BYTE_ORDER == BIG_ENDIAN
341 1.1 bjh21 hdr->count = bswap16(hdr->count);
342 1.1 bjh21 #endif
343 1.1 bjh21 }
344 1.1 bjh21
345 1.8 perry static inline void
346 1.1 bjh21 mx98905_read_setup(bus_space_tag_t nict, bus_space_handle_t nich,
347 1.1 bjh21 int len, int buf)
348 1.1 bjh21 {
349 1.1 bjh21
350 1.1 bjh21 /* Select page 0 registers. */
351 1.1 bjh21 NIC_BARRIER(nict, nich);
352 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_CR,
353 1.1 bjh21 ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
354 1.1 bjh21 NIC_BARRIER(nict, nich);
355 1.1 bjh21
356 1.1 bjh21 /* Set up DMA byte count. */
357 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RBCR0, len);
358 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RBCR1, len >> 8);
359 1.1 bjh21
360 1.1 bjh21 /* Set up source address in NIC mem. */
361 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RSAR0, buf);
362 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_RSAR1, buf >> 8);
363 1.1 bjh21
364 1.1 bjh21 NIC_BARRIER(nict, nich);
365 1.1 bjh21 bus_space_write_1(nict, nich, ED_P0_CR,
366 1.1 bjh21 ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA);
367 1.1 bjh21
368 1.1 bjh21 bus_space_barrier(nict, nich, 0, NE2000_NPORTS,
369 1.1 bjh21 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
370 1.1 bjh21 }
371 1.1 bjh21
372 1.1 bjh21 /*
373 1.1 bjh21 * Given a NIC memory source address and a host memory destination address,
374 1.1 bjh21 * copy 'amount' from NIC to host using programmed i/o. The 'amount' is
375 1.1 bjh21 * rounded up to a word - ok as long as mbufs are word sized.
376 1.1 bjh21 */
377 1.1 bjh21 void
378 1.1 bjh21 mx98905_readmem(nict, nich, asict, asich, src, dst, amount, useword)
379 1.1 bjh21 bus_space_tag_t nict;
380 1.1 bjh21 bus_space_handle_t nich;
381 1.1 bjh21 bus_space_tag_t asict;
382 1.1 bjh21 bus_space_handle_t asich;
383 1.1 bjh21 int src;
384 1.1 bjh21 u_int8_t *dst;
385 1.1 bjh21 size_t amount;
386 1.1 bjh21 int useword;
387 1.1 bjh21 {
388 1.1 bjh21 int len, resid;
389 1.1 bjh21
390 1.1 bjh21 resid = amount;
391 1.1 bjh21 /* Round up to a word. */
392 1.1 bjh21 if (resid & 1)
393 1.1 bjh21 ++resid;
394 1.1 bjh21
395 1.1 bjh21 while (resid > 0) {
396 1.1 bjh21 len = min(resid, 254);
397 1.1 bjh21 mx98905_read_setup(nict, nich, len, src);
398 1.1 bjh21 if (useword)
399 1.1 bjh21 bus_space_read_multi_stream_2(asict, asich,
400 1.1 bjh21 NE2000_ASIC_DATA, (u_int16_t *)dst, len >> 1);
401 1.1 bjh21 else
402 1.1 bjh21 bus_space_read_multi_1(asict, asich, NE2000_ASIC_DATA,
403 1.1 bjh21 dst, len);
404 1.1 bjh21 resid -= len;
405 1.1 bjh21 src += len;
406 1.1 bjh21 dst += len;
407 1.1 bjh21 }
408 1.1 bjh21 }
409