Home | History | Annotate | Line # | Download | only in ic
ncr5380reg.h revision 1.1 
      1 /*	$NetBSD: ncr5380reg.h,v 1.1 1995/07/08 21:30:43 pk Exp $	*/
      2 
      3 /*
      4  * Mach Operating System
      5  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
      6  * All Rights Reserved.
      7  *
      8  * Permission to use, copy, modify and distribute this software and its
      9  * documentation is hereby granted, provided that both the copyright
     10  * notice and this permission notice appear in all copies of the
     11  * software, derivative works or modified versions, and any portions
     12  * thereof, and that both notices appear in supporting documentation.
     13  *
     14  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
     15  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
     16  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     17  *
     18  * Carnegie Mellon requests users of this software to return to
     19  *
     20  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     21  *  School of Computer Science
     22  *  Carnegie Mellon University
     23  *  Pittsburgh PA 15213-3890
     24  *
     25  * any improvements or extensions that they make and grant Carnegie the
     26  * rights to redistribute these changes.
     27  */
     28 /*
     29  * HISTORY (mach3)
     30  * Revision 2.3  91/08/24  12:25:10  af
     31  * 	Moved padding of regmap in impl file.
     32  * 	[91/08/02  04:22:39  af]
     33  *
     34  * Revision 2.2  91/06/19  16:28:35  rvb
     35  * 	From the NCR data sheets
     36  * 	"NCR 5380 Family, SCSI Protocol Controller Data Manual"
     37  * 	NCR Microelectronics Division, Colorado Spring, 6/98 T01891L
     38  * 	[91/04/21            af]
     39  *
     40  */
     41 
     42 /*
     43  *	File: scsi_5380.h
     44  * 	Author: Alessandro Forin, Carnegie Mellon University
     45  *	Date:	5/91
     46  *
     47  *	Defines for the NCR 5380 (SCSI chip), aka Am5380
     48  */
     49 
     50 /*
     51  * Register map
     52  */
     53 typedef struct {
     54 	volatile unsigned char	sci_data;	/* r:  Current data */
     55 #define			sci_odata sci_data	/* w:  Out data */
     56 	volatile unsigned char	sci_icmd;	/* rw: Initiator command */
     57 	volatile unsigned char	sci_mode;	/* rw: Mode */
     58 	volatile unsigned char	sci_tcmd;	/* rw: Target command */
     59 	volatile unsigned char	sci_bus_csr;	/* r:  Bus Status */
     60 #define			sci_sel_enb sci_bus_csr	/* w:  Select enable */
     61 	volatile unsigned char	sci_csr;	/* r:  Status */
     62 #define			sci_dma_send sci_csr	/* w:  Start dma send data */
     63 	volatile unsigned char	sci_idata;	/* r:  Input data */
     64 #define			sci_trecv sci_idata	/* w:  Start dma receive, target */
     65 	volatile unsigned char	sci_iack;	/* r:  Interrupt Acknowledge  */
     66 #define			sci_irecv sci_iack	/* w:  Start dma receive, initiator */
     67 } sci_regmap_t;
     68 
     69 
     70 /*
     71  * Initiator command register
     72  */
     73 #define SCI_ICMD_DATA		0x01		/* rw: Assert data bus   */
     74 #define SCI_ICMD_ATN		0x02		/* rw: Assert ATN signal */
     75 #define SCI_ICMD_SEL		0x04		/* rw: Assert SEL signal */
     76 #define SCI_ICMD_BSY		0x08		/* rw: Assert BSY signal */
     77 #define SCI_ICMD_ACK		0x10		/* rw: Assert ACK signal */
     78 #define SCI_ICMD_LST		0x20		/* r:  Lost arbitration */
     79 #define SCI_ICMD_DIFF	SCI_ICMD_LST		/* w:  Differential cable */
     80 #define SCI_ICMD_AIP		0x40		/* r:  Arbitration in progress */
     81 #define SCI_ICMD_TEST	SCI_ICMD_AIP		/* w:  Test mode */
     82 #define SCI_ICMD_RST		0x80		/* rw: Assert RST signal */
     83 
     84 
     85 /*
     86  * Mode register
     87  */
     88 #define SCI_MODE_ARB		0x01		/* rw: Start arbitration */
     89 #define SCI_MODE_DMA		0x02		/* rw: Enable DMA xfers */
     90 #define SCI_MODE_MONBSY		0x04		/* rw: Monitor BSY signal */
     91 #define SCI_MODE_DMA_IE		0x08		/* rw: Enable DMA complete interrupt */
     92 #define SCI_MODE_PERR_IE	0x10		/* rw: Interrupt on parity errors */
     93 #define SCI_MODE_PAR_CHK	0x20		/* rw: Check parity */
     94 #define SCI_MODE_TARGET		0x40		/* rw: Target mode (Initiator if 0) */
     95 #define SCI_MODE_BLOCKDMA	0x80		/* rw: Block-mode DMA handshake (MBZ) */
     96 
     97 
     98 /*
     99  * Target command register
    100  */
    101 #define SCI_TCMD_IO		0x01		/* rw: Assert I/O signal */
    102 #define SCI_TCMD_CD		0x02		/* rw: Assert C/D signal */
    103 #define SCI_TCMD_MSG		0x04		/* rw: Assert MSG signal */
    104 #define SCI_TCMD_PHASE_MASK	0x07		/* r:  Mask for current bus phase */
    105 #define SCI_TCMD_REQ		0x08		/* rw: Assert REQ signal */
    106 #define	SCI_TCMD_LAST_SENT	0x80		/* ro: Last byte was xferred
    107 						 *     (not on 5380/1) */
    108 
    109 #define	SCI_PHASE(x)		((x)&0x7)
    110 
    111 /*
    112  * Current (SCSI) Bus status
    113  */
    114 #define SCI_BUS_DBP		0x01		/* r:  Data Bus parity */
    115 #define SCI_BUS_SEL		0x02		/* r:  SEL signal */
    116 #define SCI_BUS_IO		0x04		/* r:  I/O signal */
    117 #define SCI_BUS_CD		0x08		/* r:  C/D signal */
    118 #define SCI_BUS_MSG		0x10		/* r:  MSG signal */
    119 #define SCI_BUS_REQ		0x20		/* r:  REQ signal */
    120 #define SCI_BUS_BSY		0x40		/* r:  BSY signal */
    121 #define SCI_BUS_RST		0x80		/* r:  RST signal */
    122 
    123 #define	SCI_CUR_PHASE(x)	SCI_PHASE((x)>>2)
    124 
    125 /*
    126  * Bus and Status register
    127  */
    128 #define SCI_CSR_ACK		0x01		/* r:  ACK signal */
    129 #define SCI_CSR_ATN		0x02		/* r:  ATN signal */
    130 #define SCI_CSR_DISC		0x04		/* r:  Disconnected (BSY==0) */
    131 #define SCI_CSR_PHASE_MATCH	0x08		/* r:  Bus and SCI_TCMD match */
    132 #define SCI_CSR_INT		0x10		/* r:  Interrupt request */
    133 #define SCI_CSR_PERR		0x20		/* r:  Parity error */
    134 #define SCI_CSR_DREQ		0x40		/* r:  DMA request */
    135 #define SCI_CSR_DONE		0x80		/* r:  DMA count is zero */
    136