ncr53c9x.c revision 1.16
1 /* $NetBSD: ncr53c9x.c,v 1.16 1997/07/30 12:01:53 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 90 #include <dev/ic/ncr53c9xreg.h> 91 #include <dev/ic/ncr53c9xvar.h> 92 93 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 94 95 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 96 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 97 struct ncr53c9x_ecb *)); 98 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 99 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 100 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 101 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 102 struct scsi_xfer *, int)); 103 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 104 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 105 struct ncr53c9x_ecb *)); 106 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 107 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 108 /*static*/ void ncr53c9x_timeout __P((void *arg)); 109 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 110 struct ncr53c9x_ecb *)); 111 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 112 struct ncr53c9x_ecb *)); 113 114 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 115 struct ncr53c9x_ecb *)); 116 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 117 struct ncr53c9x_ecb *, int)); 118 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 119 120 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 121 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 122 struct ncr53c9x_tinfo *)); 123 124 /* 125 * Names for the NCR53c9x variants, correspnding to the variant tags 126 * in ncr53c9xvar.h. 127 */ 128 const char *ncr53c9x_variant_names[] = { 129 "ESP100", 130 "ESP100A", 131 "ESP200", 132 "NCR53C94", 133 "NCR53C96", 134 "ESP406", 135 "FAS408", 136 }; 137 138 /* 139 * Attach this instance, and then all the sub-devices 140 */ 141 void 142 ncr53c9x_attach(sc, adapter, dev) 143 struct ncr53c9x_softc *sc; 144 struct scsi_adapter *adapter; 145 struct scsi_device *dev; 146 { 147 148 /* 149 * Note, the front-end has set us up to print the chip variation. 150 */ 151 152 if (sc->sc_rev >= NCR_VARIANT_MAX) { 153 printf("\n%s: unknown variant %d, devices not attached\n", 154 sc->sc_dev.dv_xname, sc->sc_rev); 155 return; 156 } 157 158 printf(": %s, %dMHz, SCSI ID %d\n", 159 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 160 161 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 162 163 /* The value *must not* be == 1. Make it 2 */ 164 if (sc->sc_ccf == 1) 165 sc->sc_ccf = 2; 166 167 /* 168 * The recommended timeout is 250ms. This register is loaded 169 * with a value calculated as follows, from the docs: 170 * 171 * (timout period) x (CLK frequency) 172 * reg = ------------------------------------- 173 * 8192 x (Clock Conversion Factor) 174 * 175 * Since CCF has a linear relation to CLK, this generally computes 176 * to the constant of 153. 177 */ 178 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 179 180 /* CCF register only has 3 bits; 0 is actually 8 */ 181 sc->sc_ccf &= 7; 182 183 /* Reset state & bus */ 184 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 185 sc->sc_state = 0; 186 ncr53c9x_init(sc, 1); 187 188 /* 189 * fill in the prototype scsi_link. 190 */ 191 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 192 sc->sc_link.adapter_softc = sc; 193 sc->sc_link.adapter_target = sc->sc_id; 194 sc->sc_link.adapter = adapter; 195 sc->sc_link.device = dev; 196 sc->sc_link.openings = 2; 197 sc->sc_link.max_target = 7; 198 199 /* 200 * Now try to attach all the sub-devices 201 */ 202 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 203 204 /* 205 * Enable interupts from the SCSI core 206 */ 207 if ((sc->sc_rev == NCR_VARIANT_ESP406) || 208 (sc->sc_rev == NCR_VARIANT_FAS408)) { 209 NCR_PIOREGS(sc); 210 NCR_WRITE_REG(sc, NCR_CFG5, NCRCFG5_SINT | 211 NCR_READ_REG(sc, NCR_CFG5)); 212 NCR_SCSIREGS(sc); 213 } 214 } 215 216 /* 217 * This is the generic esp reset function. It does not reset the SCSI bus, 218 * only this controllers, but kills any on-going commands, and also stops 219 * and resets the DMA. 220 * 221 * After reset, registers are loaded with the defaults from the attach 222 * routine above. 223 */ 224 void 225 ncr53c9x_reset(sc) 226 struct ncr53c9x_softc *sc; 227 { 228 229 /* reset DMA first */ 230 NCRDMA_RESET(sc); 231 232 /* reset SCSI chip */ 233 NCRCMD(sc, NCRCMD_RSTCHIP); 234 NCRCMD(sc, NCRCMD_NOP); 235 DELAY(500); 236 237 /* do these backwards, and fall through */ 238 switch (sc->sc_rev) { 239 case NCR_VARIANT_ESP406: 240 case NCR_VARIANT_FAS408: 241 NCR_SCSIREGS(sc); 242 case NCR_VARIANT_NCR53C94: 243 case NCR_VARIANT_NCR53C96: 244 case NCR_VARIANT_ESP200: 245 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 246 case NCR_VARIANT_ESP100A: 247 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 248 case NCR_VARIANT_ESP100: 249 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 250 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 251 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 252 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 253 break; 254 default: 255 printf("%s: unknown revision code, assuming ESP100\n", 256 sc->sc_dev.dv_xname); 257 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 258 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 259 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 260 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 261 } 262 } 263 264 /* 265 * Reset the SCSI bus, but not the chip 266 */ 267 void 268 ncr53c9x_scsi_reset(sc) 269 struct ncr53c9x_softc *sc; 270 { 271 272 (*sc->sc_glue->gl_dma_stop)(sc); 273 274 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 275 NCRCMD(sc, NCRCMD_RSTSCSI); 276 } 277 278 /* 279 * Initialize esp state machine 280 */ 281 void 282 ncr53c9x_init(sc, doreset) 283 struct ncr53c9x_softc *sc; 284 int doreset; 285 { 286 struct ncr53c9x_ecb *ecb; 287 int r; 288 289 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 290 291 if (sc->sc_state == 0) { 292 /* First time through; initialize. */ 293 TAILQ_INIT(&sc->ready_list); 294 TAILQ_INIT(&sc->nexus_list); 295 TAILQ_INIT(&sc->free_list); 296 sc->sc_nexus = NULL; 297 ecb = sc->sc_ecb; 298 bzero(ecb, sizeof(sc->sc_ecb)); 299 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 300 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 301 ecb++; 302 } 303 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 304 } else { 305 /* Cancel any active commands. */ 306 sc->sc_state = NCR_CLEANING; 307 if ((ecb = sc->sc_nexus) != NULL) { 308 ecb->xs->error = XS_TIMEOUT; 309 ncr53c9x_done(sc, ecb); 310 } 311 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 312 ecb->xs->error = XS_TIMEOUT; 313 ncr53c9x_done(sc, ecb); 314 } 315 } 316 317 /* 318 * reset the chip to a known state 319 */ 320 ncr53c9x_reset(sc); 321 322 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 323 for (r = 0; r < 8; r++) { 324 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 325 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 326 327 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8)))) 328 ? T_NEGOTIATE : 0) | 329 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) | 330 T_NEED_TO_RESET; 331 ti->period = sc->sc_minsync; 332 ti->offset = 0; 333 } 334 335 if (doreset) { 336 sc->sc_state = NCR_SBR; 337 NCRCMD(sc, NCRCMD_RSTSCSI); 338 } else { 339 sc->sc_state = NCR_IDLE; 340 ncr53c9x_sched(sc); 341 } 342 } 343 344 /* 345 * Read the NCR registers, and save their contents for later use. 346 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 347 * NCR_INTR - so make sure it is the last read. 348 * 349 * I think that (from reading the docs) most bits in these registers 350 * only make sense when he DMA CSR has an interrupt showing. Call only 351 * if an interrupt is pending. 352 */ 353 void 354 ncr53c9x_readregs(sc) 355 struct ncr53c9x_softc *sc; 356 { 357 358 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 359 /* Only the stepo bits are of interest */ 360 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 361 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 362 363 if (sc->sc_glue->gl_clear_latched_intr != NULL) 364 (*sc->sc_glue->gl_clear_latched_intr)(sc); 365 366 /* 367 * Determine the SCSI bus phase, return either a real SCSI bus phase 368 * or some pseudo phase we use to detect certain exceptions. 369 */ 370 371 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 372 ? /* Disconnected */ BUSFREE_PHASE 373 : sc->sc_espstat & NCRSTAT_PHASE; 374 375 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 376 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 377 } 378 379 /* 380 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 381 */ 382 static inline int 383 ncr53c9x_stp2cpb(sc, period) 384 struct ncr53c9x_softc *sc; 385 int period; 386 { 387 int v; 388 v = (sc->sc_freq * period) / 250; 389 if (ncr53c9x_cpb2stp(sc, v) < period) 390 /* Correct round-down error */ 391 v++; 392 return v; 393 } 394 395 static inline void 396 ncr53c9x_setsync(sc, ti) 397 struct ncr53c9x_softc *sc; 398 struct ncr53c9x_tinfo *ti; 399 { 400 401 if (ti->flags & T_SYNCMODE) { 402 NCR_WRITE_REG(sc, NCR_SYNCOFF, ti->offset); 403 NCR_WRITE_REG(sc, NCR_SYNCTP, 404 ncr53c9x_stp2cpb(sc, ti->period)); 405 } else { 406 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 407 NCR_WRITE_REG(sc, NCR_SYNCTP, 0); 408 } 409 } 410 411 int ncr53c9x_dmaselect = 0; 412 /* 413 * Send a command to a target, set the driver state to NCR_SELECTING 414 * and let the caller take care of the rest. 415 * 416 * Keeping this as a function allows me to say that this may be done 417 * by DMA instead of programmed I/O soon. 418 */ 419 void 420 ncr53c9x_select(sc, ecb) 421 struct ncr53c9x_softc *sc; 422 struct ncr53c9x_ecb *ecb; 423 { 424 struct scsi_link *sc_link = ecb->xs->sc_link; 425 int target = sc_link->target; 426 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 427 u_char *cmd; 428 int clen; 429 430 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 431 sc_link->target, sc_link->lun, ecb->cmd.cmd.opcode)); 432 433 /* new state NCR_SELECTING */ 434 sc->sc_state = NCR_SELECTING; 435 436 /* 437 * Schedule the timeout now, the first time we will go away 438 * expecting to come back due to an interrupt, because it is 439 * always possible that the interrupt may never happen. 440 */ 441 if ((ecb->xs->flags & SCSI_POLL) == 0) 442 timeout(ncr53c9x_timeout, ecb, 443 (ecb->timeout * hz) / 1000); 444 445 NCRCMD(sc, NCRCMD_FLUSH); 446 447 /* 448 * The docs say the target register is never reset, and I 449 * can't think of a better place to set it 450 */ 451 NCR_WRITE_REG(sc, NCR_SELID, target); 452 ncr53c9x_setsync(sc, ti); 453 454 if (ncr53c9x_dmaselect && (ti->flags & T_NEGOTIATE) == 0) { 455 size_t dmacl; 456 ecb->cmd.id = 457 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1); 458 459 /* setup DMA transfer for command */ 460 clen = ecb->clen + 1; 461 sc->sc_cmdlen = clen; 462 sc->sc_cmdp = (caddr_t)&ecb->cmd; 463 dmacl = clen; 464 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmacl); 465 /* Program the SCSI counter */ 466 NCR_WRITE_REG(sc, NCR_TCL, clen); 467 NCR_WRITE_REG(sc, NCR_TCM, clen >> 8); 468 if (sc->sc_cfg2 & NCRCFG2_FE) { 469 NCR_WRITE_REG(sc, NCR_TCH, clen >> 16); 470 } 471 472 /* And get the targets attention */ 473 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 474 NCRDMA_GO(sc); 475 return; 476 } 477 /* 478 * Who am I. This is where we tell the target that we are 479 * happy for it to disconnect etc. 480 */ 481 NCR_WRITE_REG(sc, NCR_FIFO, 482 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 483 484 if (ti->flags & T_NEGOTIATE) { 485 /* Arbitrate, select and stop after IDENTIFY message */ 486 NCRCMD(sc, NCRCMD_SELATNS); 487 return; 488 } 489 490 /* Now the command into the FIFO */ 491 cmd = (u_char *)&ecb->cmd.cmd; 492 clen = ecb->clen; 493 while (clen--) 494 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 495 496 /* And get the targets attention */ 497 NCRCMD(sc, NCRCMD_SELATN); 498 } 499 500 void 501 ncr53c9x_free_ecb(sc, ecb, flags) 502 struct ncr53c9x_softc *sc; 503 struct ncr53c9x_ecb *ecb; 504 int flags; 505 { 506 int s; 507 508 s = splbio(); 509 510 ecb->flags = 0; 511 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 512 513 /* 514 * If there were none, wake anybody waiting for one to come free, 515 * starting with queued entries. 516 */ 517 if (ecb->chain.tqe_next == 0) 518 wakeup(&sc->free_list); 519 520 splx(s); 521 } 522 523 struct ncr53c9x_ecb * 524 ncr53c9x_get_ecb(sc, flags) 525 struct ncr53c9x_softc *sc; 526 int flags; 527 { 528 struct ncr53c9x_ecb *ecb; 529 int s; 530 531 s = splbio(); 532 533 while ((ecb = sc->free_list.tqh_first) == NULL && 534 (flags & SCSI_NOSLEEP) == 0) 535 tsleep(&sc->free_list, PRIBIO, "especb", 0); 536 if (ecb) { 537 TAILQ_REMOVE(&sc->free_list, ecb, chain); 538 ecb->flags |= ECB_ALLOC; 539 } 540 541 splx(s); 542 return ecb; 543 } 544 545 /* 546 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 547 */ 548 549 /* 550 * Start a SCSI-command 551 * This function is called by the higher level SCSI-driver to queue/run 552 * SCSI-commands. 553 */ 554 int 555 ncr53c9x_scsi_cmd(xs) 556 struct scsi_xfer *xs; 557 { 558 struct scsi_link *sc_link = xs->sc_link; 559 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 560 struct ncr53c9x_ecb *ecb; 561 int s, flags; 562 563 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 564 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 565 sc_link->target)); 566 567 flags = xs->flags; 568 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) 569 return TRY_AGAIN_LATER; 570 571 /* Initialize ecb */ 572 ecb->xs = xs; 573 ecb->timeout = xs->timeout; 574 575 if (flags & SCSI_RESET) { 576 ecb->flags |= ECB_RESET; 577 ecb->clen = 0; 578 ecb->dleft = 0; 579 } else { 580 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 581 ecb->clen = xs->cmdlen; 582 ecb->daddr = xs->data; 583 ecb->dleft = xs->datalen; 584 } 585 ecb->stat = 0; 586 587 s = splbio(); 588 589 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 590 if (sc->sc_state == NCR_IDLE) 591 ncr53c9x_sched(sc); 592 593 splx(s); 594 595 if ((flags & SCSI_POLL) == 0) 596 return SUCCESSFULLY_QUEUED; 597 598 /* Not allowed to use interrupts, use polling instead */ 599 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 600 ncr53c9x_timeout(ecb); 601 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 602 ncr53c9x_timeout(ecb); 603 } 604 return COMPLETE; 605 } 606 607 /* 608 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 609 */ 610 int 611 ncr53c9x_poll(sc, xs, count) 612 struct ncr53c9x_softc *sc; 613 struct scsi_xfer *xs; 614 int count; 615 { 616 617 NCR_TRACE(("[ncr53c9x_poll] ")); 618 while (count) { 619 if (NCRDMA_ISINTR(sc)) { 620 ncr53c9x_intr(sc); 621 } 622 #if alternatively 623 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 624 ncr53c9x_intr(sc); 625 #endif 626 if ((xs->flags & ITSDONE) != 0) 627 return 0; 628 if (sc->sc_state == NCR_IDLE) { 629 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 630 ncr53c9x_sched(sc); 631 } 632 DELAY(1000); 633 count--; 634 } 635 return 1; 636 } 637 638 639 /* 640 * LOW LEVEL SCSI UTILITIES 641 */ 642 643 /* 644 * Schedule a scsi operation. This has now been pulled out of the interrupt 645 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 646 * This may save us an unecessary interrupt just to get things going. 647 * Should only be called when state == NCR_IDLE and at bio pl. 648 */ 649 void 650 ncr53c9x_sched(sc) 651 struct ncr53c9x_softc *sc; 652 { 653 struct ncr53c9x_ecb *ecb; 654 struct scsi_link *sc_link; 655 struct ncr53c9x_tinfo *ti; 656 657 NCR_TRACE(("[ncr53c9x_sched] ")); 658 if (sc->sc_state != NCR_IDLE) 659 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 660 661 /* 662 * Find first ecb in ready queue that is for a target/lunit 663 * combinations that is not busy. 664 */ 665 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 666 sc_link = ecb->xs->sc_link; 667 ti = &sc->sc_tinfo[sc_link->target]; 668 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 669 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 670 sc->sc_nexus = ecb; 671 ncr53c9x_select(sc, ecb); 672 break; 673 } else 674 NCR_MISC(("%d:%d busy\n", 675 sc_link->target, sc_link->lun)); 676 } 677 } 678 679 void 680 ncr53c9x_sense(sc, ecb) 681 struct ncr53c9x_softc *sc; 682 struct ncr53c9x_ecb *ecb; 683 { 684 struct scsi_xfer *xs = ecb->xs; 685 struct scsi_link *sc_link = xs->sc_link; 686 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 687 struct scsi_sense *ss = (void *)&ecb->cmd.cmd; 688 689 NCR_MISC(("requesting sense ")); 690 /* Next, setup a request sense command block */ 691 bzero(ss, sizeof(*ss)); 692 ss->opcode = REQUEST_SENSE; 693 ss->byte2 = sc_link->lun << 5; 694 ss->length = sizeof(struct scsi_sense_data); 695 ecb->clen = sizeof(*ss); 696 ecb->daddr = (char *)&xs->sense; 697 ecb->dleft = sizeof(struct scsi_sense_data); 698 ecb->flags |= ECB_SENSE; 699 ecb->timeout = NCR_SENSE_TIMEOUT; 700 ti->senses++; 701 if (ecb->flags & ECB_NEXUS) 702 ti->lubusy &= ~(1 << sc_link->lun); 703 if (ecb == sc->sc_nexus) { 704 ncr53c9x_select(sc, ecb); 705 } else { 706 ncr53c9x_dequeue(sc, ecb); 707 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 708 if (sc->sc_state == NCR_IDLE) 709 ncr53c9x_sched(sc); 710 } 711 } 712 713 /* 714 * POST PROCESSING OF SCSI_CMD (usually current) 715 */ 716 void 717 ncr53c9x_done(sc, ecb) 718 struct ncr53c9x_softc *sc; 719 struct ncr53c9x_ecb *ecb; 720 { 721 struct scsi_xfer *xs = ecb->xs; 722 struct scsi_link *sc_link = xs->sc_link; 723 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 724 725 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 726 727 untimeout(ncr53c9x_timeout, ecb); 728 729 /* 730 * Now, if we've come here with no error code, i.e. we've kept the 731 * initial XS_NOERROR, and the status code signals that we should 732 * check sense, we'll need to set up a request sense cmd block and 733 * push the command back into the ready queue *before* any other 734 * commands for this target/lunit, else we lose the sense info. 735 * We don't support chk sense conditions for the request sense cmd. 736 */ 737 if (xs->error == XS_NOERROR) { 738 xs->status = ecb->stat; 739 if ((ecb->flags & ECB_ABORT) != 0) { 740 xs->error = XS_TIMEOUT; 741 } else if ((ecb->flags & ECB_SENSE) != 0) { 742 xs->error = XS_SENSE; 743 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 744 /* First, save the return values */ 745 xs->resid = ecb->dleft; 746 ncr53c9x_sense(sc, ecb); 747 return; 748 } else { 749 xs->resid = ecb->dleft; 750 } 751 } 752 753 xs->flags |= ITSDONE; 754 755 #ifdef NCR53C9X_DEBUG 756 if (ncr53c9x_debug & NCR_SHOWMISC) { 757 if (xs->resid != 0) 758 printf("resid=%d ", xs->resid); 759 if (xs->error == XS_SENSE) 760 printf("sense=0x%02x\n", xs->sense.error_code); 761 else 762 printf("error=%d\n", xs->error); 763 } 764 #endif 765 766 /* 767 * Remove the ECB from whatever queue it's on. 768 */ 769 if (ecb->flags & ECB_NEXUS) 770 ti->lubusy &= ~(1 << sc_link->lun); 771 if (ecb == sc->sc_nexus) { 772 sc->sc_nexus = NULL; 773 if (sc->sc_state != NCR_CLEANING) { 774 sc->sc_state = NCR_IDLE; 775 ncr53c9x_sched(sc); 776 } 777 } else 778 ncr53c9x_dequeue(sc, ecb); 779 780 ncr53c9x_free_ecb(sc, ecb, xs->flags); 781 ti->cmds++; 782 scsi_done(xs); 783 } 784 785 void 786 ncr53c9x_dequeue(sc, ecb) 787 struct ncr53c9x_softc *sc; 788 struct ncr53c9x_ecb *ecb; 789 { 790 791 if (ecb->flags & ECB_NEXUS) { 792 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 793 } else { 794 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 795 } 796 } 797 798 /* 799 * INTERRUPT/PROTOCOL ENGINE 800 */ 801 802 /* 803 * Schedule an outgoing message by prioritizing it, and asserting 804 * attention on the bus. We can only do this when we are the initiator 805 * else there will be an illegal command interrupt. 806 */ 807 #define ncr53c9x_sched_msgout(m) \ 808 do { \ 809 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 810 NCRCMD(sc, NCRCMD_SETATN); \ 811 sc->sc_flags |= NCR_ATN; \ 812 sc->sc_msgpriq |= (m); \ 813 } while (0) 814 815 int 816 ncr53c9x_reselect(sc, message) 817 struct ncr53c9x_softc *sc; 818 int message; 819 { 820 u_char selid, target, lun; 821 struct ncr53c9x_ecb *ecb; 822 struct scsi_link *sc_link; 823 struct ncr53c9x_tinfo *ti; 824 825 /* 826 * The SCSI chip made a snapshot of the data bus while the reselection 827 * was being negotiated. This enables us to determine which target did 828 * the reselect. 829 */ 830 selid = sc->sc_selid & ~(1 << sc->sc_id); 831 if (selid & (selid - 1)) { 832 printf("%s: reselect with invalid selid %02x;" 833 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 834 goto reset; 835 } 836 837 /* 838 * Search wait queue for disconnected cmd 839 * The list should be short, so I haven't bothered with 840 * any more sophisticated structures than a simple 841 * singly linked list. 842 */ 843 target = ffs(selid) - 1; 844 lun = message & 0x07; 845 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 846 ecb = ecb->chain.tqe_next) { 847 sc_link = ecb->xs->sc_link; 848 if (sc_link->target == target && sc_link->lun == lun) 849 break; 850 } 851 if (ecb == NULL) { 852 printf("%s: reselect from target %d lun %d with no nexus;" 853 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 854 goto abort; 855 } 856 857 /* Make this nexus active again. */ 858 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 859 sc->sc_state = NCR_CONNECTED; 860 sc->sc_nexus = ecb; 861 ti = &sc->sc_tinfo[target]; 862 ti->lubusy |= (1 << lun); 863 ncr53c9x_setsync(sc, ti); 864 865 if (ecb->flags & ECB_RESET) 866 ncr53c9x_sched_msgout(SEND_DEV_RESET); 867 else if (ecb->flags & ECB_ABORT) 868 ncr53c9x_sched_msgout(SEND_ABORT); 869 870 /* Do an implicit RESTORE POINTERS. */ 871 sc->sc_dp = ecb->daddr; 872 sc->sc_dleft = ecb->dleft; 873 874 return (0); 875 876 reset: 877 ncr53c9x_sched_msgout(SEND_DEV_RESET); 878 return (1); 879 880 abort: 881 ncr53c9x_sched_msgout(SEND_ABORT); 882 return (1); 883 } 884 885 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 886 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 887 #define ISEXTMSG(m) ((m) == 1) 888 889 /* 890 * Get an incoming message as initiator. 891 * 892 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 893 * byte in the FIFO 894 */ 895 void 896 ncr53c9x_msgin(sc) 897 register struct ncr53c9x_softc *sc; 898 { 899 register int v; 900 901 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 902 903 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 904 printf("%s: msgin: no msg byte available\n", 905 sc->sc_dev.dv_xname); 906 return; 907 } 908 909 /* 910 * Prepare for a new message. A message should (according 911 * to the SCSI standard) be transmitted in one single 912 * MESSAGE_IN_PHASE. If we have been in some other phase, 913 * then this is a new message. 914 */ 915 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 916 sc->sc_flags &= ~NCR_DROP_MSGI; 917 sc->sc_imlen = 0; 918 } 919 920 v = NCR_READ_REG(sc, NCR_FIFO); 921 NCR_MISC(("<msgbyte:0x%02x>", v)); 922 923 #if 0 924 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 925 /* 926 * Which target is reselecting us? (The ID bit really) 927 */ 928 sc->sc_selid = v; 929 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 930 return; 931 } 932 #endif 933 934 sc->sc_imess[sc->sc_imlen] = v; 935 936 /* 937 * If we're going to reject the message, don't bother storing 938 * the incoming bytes. But still, we need to ACK them. 939 */ 940 941 if ((sc->sc_flags & NCR_DROP_MSGI)) { 942 NCRCMD(sc, NCRCMD_MSGOK); 943 printf("<dropping msg byte %x>", 944 sc->sc_imess[sc->sc_imlen]); 945 return; 946 } 947 948 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 949 ncr53c9x_sched_msgout(SEND_REJECT); 950 sc->sc_flags |= NCR_DROP_MSGI; 951 } else { 952 sc->sc_imlen++; 953 /* 954 * This testing is suboptimal, but most 955 * messages will be of the one byte variety, so 956 * it should not effect performance 957 * significantly. 958 */ 959 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 960 goto gotit; 961 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 962 goto gotit; 963 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 964 sc->sc_imlen == sc->sc_imess[1] + 2) 965 goto gotit; 966 } 967 /* Ack what we have so far */ 968 NCRCMD(sc, NCRCMD_MSGOK); 969 return; 970 971 gotit: 972 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 973 /* 974 * Now we should have a complete message (1 byte, 2 byte 975 * and moderately long extended messages). We only handle 976 * extended messages which total length is shorter than 977 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 978 */ 979 switch (sc->sc_state) { 980 struct ncr53c9x_ecb *ecb; 981 struct ncr53c9x_tinfo *ti; 982 983 case NCR_CONNECTED: 984 ecb = sc->sc_nexus; 985 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 986 987 switch (sc->sc_imess[0]) { 988 case MSG_CMDCOMPLETE: 989 NCR_MSGS(("cmdcomplete ")); 990 if (sc->sc_dleft < 0) { 991 struct scsi_link *sc_link = ecb->xs->sc_link; 992 printf("%s: %ld extra bytes from %d:%d\n", 993 sc->sc_dev.dv_xname, -(long)sc->sc_dleft, 994 sc_link->target, sc_link->lun); 995 sc->sc_dleft = 0; 996 } 997 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 998 ? 0 999 : sc->sc_dleft; 1000 if ((ecb->flags & ECB_SENSE) == 0) 1001 ecb->xs->resid = ecb->dleft; 1002 sc->sc_state = NCR_CMDCOMPLETE; 1003 break; 1004 1005 case MSG_MESSAGE_REJECT: 1006 if (ncr53c9x_debug & NCR_SHOWMSGS) 1007 printf("%s: our msg rejected by target\n", 1008 sc->sc_dev.dv_xname); 1009 switch (sc->sc_msgout) { 1010 case SEND_SDTR: 1011 sc->sc_flags &= ~NCR_SYNCHNEGO; 1012 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1013 ncr53c9x_setsync(sc, ti); 1014 break; 1015 case SEND_INIT_DET_ERR: 1016 goto abort; 1017 } 1018 break; 1019 1020 case MSG_NOOP: 1021 NCR_MSGS(("noop ")); 1022 break; 1023 1024 case MSG_DISCONNECT: 1025 NCR_MSGS(("disconnect ")); 1026 ti->dconns++; 1027 sc->sc_state = NCR_DISCONNECT; 1028 1029 /* 1030 * Mark the fact that all bytes have moved. The 1031 * target may not bother to do a SAVE POINTERS 1032 * at this stage. This flag will set the residual 1033 * count to zero on MSG COMPLETE. 1034 */ 1035 if (sc->sc_dleft == 0) 1036 ecb->flags |= ECB_TENTATIVE_DONE; 1037 1038 break; 1039 1040 case MSG_SAVEDATAPOINTER: 1041 NCR_MSGS(("save datapointer ")); 1042 ecb->daddr = sc->sc_dp; 1043 ecb->dleft = sc->sc_dleft; 1044 break; 1045 1046 case MSG_RESTOREPOINTERS: 1047 NCR_MSGS(("restore datapointer ")); 1048 sc->sc_dp = ecb->daddr; 1049 sc->sc_dleft = ecb->dleft; 1050 break; 1051 1052 case MSG_EXTENDED: 1053 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1054 switch (sc->sc_imess[2]) { 1055 case MSG_EXT_SDTR: 1056 NCR_MSGS(("SDTR period %d, offset %d ", 1057 sc->sc_imess[3], sc->sc_imess[4])); 1058 if (sc->sc_imess[1] != 3) 1059 goto reject; 1060 ti->period = sc->sc_imess[3]; 1061 ti->offset = sc->sc_imess[4]; 1062 ti->flags &= ~T_NEGOTIATE; 1063 if (sc->sc_minsync == 0 || 1064 ti->offset == 0 || 1065 ti->period > 124) { 1066 printf("%s:%d: async\n", "esp", 1067 ecb->xs->sc_link->target); 1068 if ((sc->sc_flags&NCR_SYNCHNEGO) 1069 == 0) { 1070 /* 1071 * target initiated negotiation 1072 */ 1073 ti->offset = 0; 1074 ti->flags &= ~T_SYNCMODE; 1075 ncr53c9x_sched_msgout( 1076 SEND_SDTR); 1077 } else { 1078 /* we are async */ 1079 ti->flags &= ~T_SYNCMODE; 1080 } 1081 } else { 1082 int r = 250/ti->period; 1083 int s = (100*250)/ti->period - 100*r; 1084 int p; 1085 1086 p = ncr53c9x_stp2cpb(sc, ti->period); 1087 ti->period = ncr53c9x_cpb2stp(sc, p); 1088 #ifdef NCR53C9X_DEBUG 1089 sc_print_addr(ecb->xs->sc_link); 1090 printf("max sync rate %d.%02dMb/s\n", 1091 r, s); 1092 #endif 1093 if ((sc->sc_flags&NCR_SYNCHNEGO) 1094 == 0) { 1095 /* 1096 * target initiated negotiation 1097 */ 1098 if (ti->period < 1099 sc->sc_minsync) 1100 ti->period = 1101 sc->sc_minsync; 1102 if (ti->offset > 15) 1103 ti->offset = 15; 1104 ti->flags &= ~T_SYNCMODE; 1105 ncr53c9x_sched_msgout( 1106 SEND_SDTR); 1107 } else { 1108 /* we are sync */ 1109 ti->flags |= T_SYNCMODE; 1110 } 1111 } 1112 sc->sc_flags &= ~NCR_SYNCHNEGO; 1113 ncr53c9x_setsync(sc, ti); 1114 break; 1115 1116 default: 1117 printf("%s: unrecognized MESSAGE EXTENDED;" 1118 " sending REJECT\n", sc->sc_dev.dv_xname); 1119 goto reject; 1120 } 1121 break; 1122 1123 default: 1124 NCR_MSGS(("ident ")); 1125 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1126 sc->sc_dev.dv_xname); 1127 reject: 1128 ncr53c9x_sched_msgout(SEND_REJECT); 1129 break; 1130 } 1131 break; 1132 1133 case NCR_RESELECTED: 1134 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1135 printf("%s: reselect without IDENTIFY;" 1136 " sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1137 goto reset; 1138 } 1139 1140 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1141 break; 1142 1143 default: 1144 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1145 sc->sc_dev.dv_xname); 1146 reset: 1147 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1148 break; 1149 1150 abort: 1151 ncr53c9x_sched_msgout(SEND_ABORT); 1152 break; 1153 } 1154 1155 /* Ack last message byte */ 1156 NCRCMD(sc, NCRCMD_MSGOK); 1157 1158 /* Done, reset message pointer. */ 1159 sc->sc_flags &= ~NCR_DROP_MSGI; 1160 sc->sc_imlen = 0; 1161 } 1162 1163 1164 /* 1165 * Send the highest priority, scheduled message 1166 */ 1167 void 1168 ncr53c9x_msgout(sc) 1169 register struct ncr53c9x_softc *sc; 1170 { 1171 struct ncr53c9x_tinfo *ti; 1172 struct ncr53c9x_ecb *ecb; 1173 size_t size; 1174 1175 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1176 sc->sc_msgpriq, sc->sc_prevphase)); 1177 1178 if (sc->sc_flags & NCR_ATN) { 1179 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1180 new: 1181 NCRCMD(sc, NCRCMD_FLUSH); 1182 DELAY(1); 1183 sc->sc_msgoutq = 0; 1184 sc->sc_omlen = 0; 1185 } 1186 } else { 1187 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1188 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1189 goto new; 1190 } else { 1191 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1192 sc->sc_dev.dv_xname, __LINE__); 1193 } 1194 } 1195 1196 if (sc->sc_omlen == 0) { 1197 /* Pick up highest priority message */ 1198 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1199 sc->sc_msgoutq |= sc->sc_msgout; 1200 sc->sc_msgpriq &= ~sc->sc_msgout; 1201 sc->sc_omlen = 1; /* "Default" message len */ 1202 switch (sc->sc_msgout) { 1203 case SEND_SDTR: 1204 ecb = sc->sc_nexus; 1205 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1206 sc->sc_omess[0] = MSG_EXTENDED; 1207 sc->sc_omess[1] = 3; 1208 sc->sc_omess[2] = MSG_EXT_SDTR; 1209 sc->sc_omess[3] = ti->period; 1210 sc->sc_omess[4] = ti->offset; 1211 sc->sc_omlen = 5; 1212 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1213 ti->flags |= T_SYNCMODE; 1214 ncr53c9x_setsync(sc, ti); 1215 } 1216 break; 1217 case SEND_IDENTIFY: 1218 if (sc->sc_state != NCR_CONNECTED) { 1219 printf("%s at line %d: no nexus\n", 1220 sc->sc_dev.dv_xname, __LINE__); 1221 } 1222 ecb = sc->sc_nexus; 1223 sc->sc_omess[0] = 1224 MSG_IDENTIFY(ecb->xs->sc_link->lun, 0); 1225 break; 1226 case SEND_DEV_RESET: 1227 sc->sc_flags |= NCR_ABORTING; 1228 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1229 ecb = sc->sc_nexus; 1230 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1231 ti->flags &= ~T_SYNCMODE; 1232 ti->flags |= T_NEGOTIATE; 1233 break; 1234 case SEND_PARITY_ERROR: 1235 sc->sc_omess[0] = MSG_PARITY_ERROR; 1236 break; 1237 case SEND_ABORT: 1238 sc->sc_flags |= NCR_ABORTING; 1239 sc->sc_omess[0] = MSG_ABORT; 1240 break; 1241 case SEND_INIT_DET_ERR: 1242 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1243 break; 1244 case SEND_REJECT: 1245 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1246 break; 1247 default: 1248 NCRCMD(sc, NCRCMD_RSTATN); 1249 sc->sc_flags &= ~NCR_ATN; 1250 sc->sc_omess[0] = MSG_NOOP; 1251 break; 1252 } 1253 sc->sc_omp = sc->sc_omess; 1254 } 1255 1256 #if 1 1257 /* (re)send the message */ 1258 size = min(sc->sc_omlen, sc->sc_maxxfer); 1259 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1260 /* Program the SCSI counter */ 1261 NCR_WRITE_REG(sc, NCR_TCL, size); 1262 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1263 if (sc->sc_cfg2 & NCRCFG2_FE) { 1264 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1265 } 1266 /* load the count in */ 1267 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1268 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1269 NCRDMA_GO(sc); 1270 #else 1271 { int i; 1272 for (i = 0; i < sc->sc_omlen; i++) 1273 NCR_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1274 NCRCMD(sc, NCRCMD_TRANS); 1275 sc->sc_omlen = 0; 1276 } 1277 #endif 1278 } 1279 1280 /* 1281 * This is the most critical part of the driver, and has to know 1282 * how to deal with *all* error conditions and phases from the SCSI 1283 * bus. If there are no errors and the DMA was active, then call the 1284 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1285 * and we can return from here without further processing. 1286 * 1287 * Most of this needs verifying. 1288 */ 1289 int 1290 ncr53c9x_intr(sc) 1291 register struct ncr53c9x_softc *sc; 1292 { 1293 register struct ncr53c9x_ecb *ecb; 1294 register struct scsi_link *sc_link; 1295 struct ncr53c9x_tinfo *ti; 1296 int loop; 1297 size_t size; 1298 int nfifo; 1299 1300 NCR_TRACE(("[ncr53c9x_intr] ")); 1301 1302 /* 1303 * I have made some (maybe seriously flawed) assumptions here, 1304 * but basic testing (uncomment the printf() below), show that 1305 * certainly something happens when this loop is here. 1306 * 1307 * The idea is that many of the SCSI operations take very little 1308 * time, and going away and getting interrupted is too high an 1309 * overhead to pay. For example, selecting, sending a message 1310 * and command and then doing some work can be done in one "pass". 1311 * 1312 * The DELAY is not variable because I do not understand that the 1313 * DELAY loop should be fixed-time regardless of CPU speed, but 1314 * I am *assuming* that the faster SCSI processors get things done 1315 * quicker (sending a command byte etc), and so there is no 1316 * need to be too slow. 1317 * 1318 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1319 * at 40Mhz. This needs testing. 1320 */ 1321 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1322 /* a feeling of deja-vu */ 1323 if (!NCRDMA_ISINTR(sc)) 1324 return (loop != 0); 1325 #if 0 1326 if (loop) 1327 printf("*"); 1328 #endif 1329 1330 /* and what do the registers say... */ 1331 ncr53c9x_readregs(sc); 1332 1333 sc->sc_intrcnt.ev_count++; 1334 1335 /* 1336 * At the moment, only a SCSI Bus Reset or Illegal 1337 * Command are classed as errors. A disconnect is a 1338 * valid condition, and we let the code check is the 1339 * "NCR_BUSFREE_OK" flag was set before declaring it 1340 * and error. 1341 * 1342 * Also, the status register tells us about "Gross 1343 * Errors" and "Parity errors". Only the Gross Error 1344 * is really bad, and the parity errors are dealt 1345 * with later 1346 * 1347 * TODO 1348 * If there are too many parity error, go to slow 1349 * cable mode ? 1350 */ 1351 1352 /* SCSI Reset */ 1353 if (sc->sc_espintr & NCRINTR_SBR) { 1354 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1355 NCRCMD(sc, NCRCMD_FLUSH); 1356 DELAY(1); 1357 } 1358 if (sc->sc_state != NCR_SBR) { 1359 printf("%s: SCSI bus reset\n", 1360 sc->sc_dev.dv_xname); 1361 ncr53c9x_init(sc, 0); /* Restart everything */ 1362 return 1; 1363 } 1364 #if 0 1365 /*XXX*/ printf("<expected bus reset: " 1366 "[intr %x, stat %x, step %d]>\n", 1367 sc->sc_espintr, sc->sc_espstat, 1368 sc->sc_espstep); 1369 #endif 1370 if (sc->sc_nexus) 1371 panic("%s: nexus in reset state", 1372 sc->sc_dev.dv_xname); 1373 goto sched; 1374 } 1375 1376 ecb = sc->sc_nexus; 1377 1378 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1379 if (sc->sc_espintr & NCRINTR_ERR || 1380 sc->sc_espstat & NCRSTAT_GE) { 1381 1382 if (sc->sc_espstat & NCRSTAT_GE) { 1383 /* no target ? */ 1384 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1385 NCRCMD(sc, NCRCMD_FLUSH); 1386 DELAY(1); 1387 } 1388 if (sc->sc_state == NCR_CONNECTED || 1389 sc->sc_state == NCR_SELECTING) { 1390 ecb->xs->error = XS_TIMEOUT; 1391 ncr53c9x_done(sc, ecb); 1392 } 1393 return 1; 1394 } 1395 1396 if (sc->sc_espintr & NCRINTR_ILL) { 1397 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1398 printf("%s: ILL: ESP100 work-around activated\n", sc->sc_dev.dv_xname); 1399 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1400 continue; 1401 } 1402 /* illegal command, out of sync ? */ 1403 printf("%s: illegal command: 0x%x " 1404 "(state %d, phase %x, prevphase %x)\n", 1405 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1406 sc->sc_state, sc->sc_phase, 1407 sc->sc_prevphase); 1408 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1409 NCRCMD(sc, NCRCMD_FLUSH); 1410 DELAY(1); 1411 } 1412 ncr53c9x_init(sc, 1); /* Restart everything */ 1413 return 1; 1414 } 1415 } 1416 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1417 1418 /* 1419 * Call if DMA is active. 1420 * 1421 * If DMA_INTR returns true, then maybe go 'round the loop 1422 * again in case there is no more DMA queued, but a phase 1423 * change is expected. 1424 */ 1425 if (NCRDMA_ISACTIVE(sc)) { 1426 int r = NCRDMA_INTR(sc); 1427 if (r == -1) { 1428 printf("%s: DMA error; resetting\n", 1429 sc->sc_dev.dv_xname); 1430 ncr53c9x_init(sc, 1); 1431 } 1432 /* If DMA active here, then go back to work... */ 1433 if (NCRDMA_ISACTIVE(sc)) 1434 return 1; 1435 1436 /* 1437 * Note that this can happen during normal operation 1438 * if we are reselected while using DMA to select 1439 * a target. If this is the case, don't issue the 1440 * warning. 1441 */ 1442 if (sc->sc_dleft == 0 && 1443 (sc->sc_espstat & NCRSTAT_TC) == 0 && 1444 sc->sc_state != NCR_SELECTING) 1445 printf("%s: !TC [intr %x, stat %x, step %d]" 1446 " prevphase %x, resid %x\n", 1447 sc->sc_dev.dv_xname, 1448 sc->sc_espintr, 1449 sc->sc_espstat, 1450 sc->sc_espstep, 1451 sc->sc_prevphase, 1452 ecb?ecb->dleft:-1); 1453 } 1454 1455 #if 0 /* Unreliable on some NCR revisions? */ 1456 if ((sc->sc_espstat & NCRSTAT_INT) == 0) { 1457 printf("%s: spurious interrupt\n", 1458 sc->sc_dev.dv_xname); 1459 return 1; 1460 } 1461 #endif 1462 1463 /* 1464 * check for less serious errors 1465 */ 1466 if (sc->sc_espstat & NCRSTAT_PE) { 1467 printf("%s: SCSI bus parity error\n", 1468 sc->sc_dev.dv_xname); 1469 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1470 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1471 else 1472 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1473 } 1474 1475 if (sc->sc_espintr & NCRINTR_DIS) { 1476 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1477 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1478 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1479 NCRCMD(sc, NCRCMD_FLUSH); 1480 DELAY(1); 1481 } 1482 /* 1483 * This command must (apparently) be issued within 1484 * 250mS of a disconnect. So here you are... 1485 */ 1486 NCRCMD(sc, NCRCMD_ENSEL); 1487 switch (sc->sc_state) { 1488 case NCR_RESELECTED: 1489 goto sched; 1490 1491 case NCR_SELECTING: 1492 ecb->xs->error = XS_SELTIMEOUT; 1493 goto finish; 1494 1495 case NCR_CONNECTED: 1496 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1497 #ifdef NCR53C9X_DEBUG 1498 if (ecb) 1499 sc_print_addr(ecb->xs->sc_link); 1500 printf("sync nego not completed!\n"); 1501 #endif 1502 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1503 sc->sc_flags &= ~NCR_SYNCHNEGO; 1504 ti->flags &= 1505 ~(T_NEGOTIATE | T_SYNCMODE); 1506 } 1507 1508 /* it may be OK to disconnect */ 1509 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1510 /* 1511 * Section 5.1.1 of the SCSI 2 spec 1512 * suggests issuing a REQUEST SENSE 1513 * following an unexpected disconnect. 1514 * Some devices go into a contingent 1515 * allegiance condition when 1516 * disconnecting, and this is necessary 1517 * to clean up their state. 1518 */ 1519 printf("%s: unexpected disconnect; ", 1520 sc->sc_dev.dv_xname); 1521 if (ecb->flags & ECB_SENSE) { 1522 printf("resetting\n"); 1523 goto reset; 1524 } 1525 printf("sending REQUEST SENSE\n"); 1526 untimeout(ncr53c9x_timeout, ecb); 1527 ncr53c9x_sense(sc, ecb); 1528 goto out; 1529 } 1530 1531 ecb->xs->error = XS_TIMEOUT; 1532 goto finish; 1533 1534 case NCR_DISCONNECT: 1535 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1536 sc->sc_nexus = NULL; 1537 goto sched; 1538 1539 case NCR_CMDCOMPLETE: 1540 goto finish; 1541 } 1542 } 1543 1544 switch (sc->sc_state) { 1545 1546 case NCR_SBR: 1547 printf("%s: waiting for SCSI Bus Reset to happen\n", 1548 sc->sc_dev.dv_xname); 1549 return 1; 1550 1551 case NCR_RESELECTED: 1552 /* 1553 * we must be continuing a message ? 1554 */ 1555 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1556 printf("%s: target didn't identify\n", 1557 sc->sc_dev.dv_xname); 1558 ncr53c9x_init(sc, 1); 1559 return 1; 1560 } 1561 printf("<<RESELECT CONT'd>>"); 1562 #if XXXX 1563 ncr53c9x_msgin(sc); 1564 if (sc->sc_state != NCR_CONNECTED) { 1565 /* IDENTIFY fail?! */ 1566 printf("%s: identify failed\n", 1567 sc->sc_dev.dv_xname); 1568 ncr53c9x_init(sc, 1); 1569 return 1; 1570 } 1571 #endif 1572 break; 1573 1574 case NCR_IDLE: 1575 if (sc->sc_flags & NCR_ICCS) printf("[[esp: BUMMER]]"); 1576 case NCR_SELECTING: 1577 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1578 sc->sc_flags = 0; 1579 ecb = sc->sc_nexus; 1580 1581 if (sc->sc_espintr & NCRINTR_RESEL) { 1582 /* 1583 * If we're trying to select a 1584 * target ourselves, push our command 1585 * back into the ready list. 1586 */ 1587 if (sc->sc_state == NCR_SELECTING) { 1588 NCR_MISC(("backoff selector ")); 1589 untimeout(ncr53c9x_timeout, ecb); 1590 sc_link = ecb->xs->sc_link; 1591 ti = &sc->sc_tinfo[sc_link->target]; 1592 TAILQ_INSERT_HEAD(&sc->ready_list, 1593 ecb, chain); 1594 ecb = sc->sc_nexus = NULL; 1595 } 1596 sc->sc_state = NCR_RESELECTED; 1597 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1598 /* 1599 * Things are seriously fucked up. 1600 * Pull the brakes, i.e. reset 1601 */ 1602 printf("%s: target didn't identify\n", 1603 sc->sc_dev.dv_xname); 1604 ncr53c9x_init(sc, 1); 1605 return 1; 1606 } 1607 /* 1608 * The C90 only inhibits FIFO writes until 1609 * reselection is complete, instead of 1610 * waiting until the interrupt status register 1611 * has been read. So, if the reselect happens 1612 * while we were entering a command bytes (for 1613 * another target) some of those bytes can 1614 * appear in the FIFO here, after the 1615 * interrupt is taken. 1616 */ 1617 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1618 if (nfifo < 2 || 1619 (nfifo > 2 && 1620 sc->sc_rev != NCR_VARIANT_ESP100)) { 1621 printf("%s: RESELECT: " 1622 "%d bytes in FIFO! " 1623 "[intr %x, stat %x, step %d, prevphase %x]\n", 1624 sc->sc_dev.dv_xname, 1625 nfifo, 1626 sc->sc_espintr, 1627 sc->sc_espstat, 1628 sc->sc_espstep, 1629 sc->sc_prevphase); 1630 ncr53c9x_init(sc, 1); 1631 return 1; 1632 } 1633 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1634 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1635 1636 /* Handle identify message */ 1637 ncr53c9x_msgin(sc); 1638 if (nfifo != 2) { 1639 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1640 NCRCMD(sc, NCRCMD_FLUSH); 1641 } 1642 1643 if (sc->sc_state != NCR_CONNECTED) { 1644 /* IDENTIFY fail?! */ 1645 printf("%s: identify failed\n", 1646 sc->sc_dev.dv_xname); 1647 ncr53c9x_init(sc, 1); 1648 return 1; 1649 } 1650 continue; /* ie. next phase expected soon */ 1651 } 1652 1653 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1654 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1655 ecb = sc->sc_nexus; 1656 if (!ecb) 1657 panic("esp: not nexus at sc->sc_nexus"); 1658 1659 sc_link = ecb->xs->sc_link; 1660 ti = &sc->sc_tinfo[sc_link->target]; 1661 1662 switch (sc->sc_espstep) { 1663 case 0: 1664 printf("%s: select timeout/no " 1665 "disconnect\n", 1666 sc->sc_dev.dv_xname); 1667 ecb->xs->error = XS_SELTIMEOUT; 1668 goto finish; 1669 case 1: 1670 if ((ti->flags & T_NEGOTIATE) == 0) { 1671 printf("%s: step 1 & !NEG\n", 1672 sc->sc_dev.dv_xname); 1673 goto reset; 1674 } 1675 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1676 printf("%s: !MSGOUT\n", 1677 sc->sc_dev.dv_xname); 1678 goto reset; 1679 } 1680 /* Start negotiating */ 1681 ti->period = sc->sc_minsync; 1682 ti->offset = 15; 1683 sc->sc_flags |= NCR_SYNCHNEGO; 1684 ncr53c9x_sched_msgout(SEND_SDTR); 1685 break; 1686 case 3: 1687 /* 1688 * Grr, this is supposed to mean 1689 * "target left command phase 1690 * prematurely". It seems to happen 1691 * regularly when sync mode is on. 1692 * Look at FIFO to see if command 1693 * went out. 1694 * (Timing problems?) 1695 */ 1696 if (ncr53c9x_dmaselect) { 1697 if (sc->sc_cmdlen == 0) 1698 /* Hope for the best.. */ 1699 break; 1700 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1701 & NCRFIFO_FF) == 0) { 1702 /* Hope for the best.. */ 1703 break; 1704 } 1705 printf("(%s:%d:%d): selection failed;" 1706 " %d left in FIFO " 1707 "[intr %x, stat %x, step %d]\n", 1708 sc->sc_dev.dv_xname, 1709 sc_link->target, 1710 sc_link->lun, 1711 NCR_READ_REG(sc, NCR_FFLAG) 1712 & NCRFIFO_FF, 1713 sc->sc_espintr, sc->sc_espstat, 1714 sc->sc_espstep); 1715 NCRCMD(sc, NCRCMD_FLUSH); 1716 ncr53c9x_sched_msgout(SEND_ABORT); 1717 return 1; 1718 case 2: 1719 /* Select stuck at Command Phase */ 1720 NCRCMD(sc, NCRCMD_FLUSH); 1721 case 4: 1722 if (ncr53c9x_dmaselect && 1723 sc->sc_cmdlen != 0) 1724 printf("(%s:%d:%d): select; " 1725 "%d left in DMA buffer\n", 1726 sc->sc_dev.dv_xname, 1727 sc_link->target, 1728 sc_link->lun, 1729 sc->sc_cmdlen); 1730 /* So far, everything went fine */ 1731 break; 1732 } 1733 #if 0 1734 if (ecb->xs->flags & SCSI_RESET) 1735 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1736 else if (ti->flags & T_NEGOTIATE) 1737 ncr53c9x_sched_msgout( 1738 SEND_IDENTIFY | SEND_SDTR); 1739 else 1740 ncr53c9x_sched_msgout(SEND_IDENTIFY); 1741 #endif 1742 1743 ecb->flags |= ECB_NEXUS; 1744 ti->lubusy |= (1 << sc_link->lun); 1745 1746 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1747 /* Do an implicit RESTORE POINTERS. */ 1748 sc->sc_dp = ecb->daddr; 1749 sc->sc_dleft = ecb->dleft; 1750 sc->sc_state = NCR_CONNECTED; 1751 break; 1752 } else { 1753 printf("%s: unexpected status after select" 1754 ": [intr %x, stat %x, step %x]\n", 1755 sc->sc_dev.dv_xname, 1756 sc->sc_espintr, sc->sc_espstat, 1757 sc->sc_espstep); 1758 NCRCMD(sc, NCRCMD_FLUSH); 1759 DELAY(1); 1760 goto reset; 1761 } 1762 if (sc->sc_state == NCR_IDLE) { 1763 printf("%s: stray interrupt\n", 1764 sc->sc_dev.dv_xname); 1765 return 0; 1766 } 1767 break; 1768 1769 case NCR_CONNECTED: 1770 if (sc->sc_flags & NCR_ICCS) { 1771 u_char msg; 1772 1773 sc->sc_flags &= ~NCR_ICCS; 1774 1775 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1776 printf("%s: ICCS: " 1777 ": [intr %x, stat %x, step %x]\n", 1778 sc->sc_dev.dv_xname, 1779 sc->sc_espintr, sc->sc_espstat, 1780 sc->sc_espstep); 1781 } 1782 if ((NCR_READ_REG(sc, NCR_FFLAG) 1783 & NCRFIFO_FF) != 2) { 1784 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1785 & NCRFIFO_FF) - 2; 1786 while (i--) 1787 (void) NCR_READ_REG(sc, 1788 NCR_FIFO); 1789 } 1790 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1791 msg = NCR_READ_REG(sc, NCR_FIFO); 1792 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1793 if (msg == MSG_CMDCOMPLETE) { 1794 ecb->dleft = 1795 (ecb->flags & ECB_TENTATIVE_DONE) 1796 ? 0 1797 : sc->sc_dleft; 1798 if ((ecb->flags & ECB_SENSE) == 0) 1799 ecb->xs->resid = ecb->dleft; 1800 sc->sc_state = NCR_CMDCOMPLETE; 1801 } else 1802 printf("%s: STATUS_PHASE: msg %d\n", 1803 sc->sc_dev.dv_xname, msg); 1804 NCRCMD(sc, NCRCMD_MSGOK); 1805 continue; /* ie. wait for disconnect */ 1806 } 1807 break; 1808 default: 1809 panic("%s: invalid state: %d", 1810 sc->sc_dev.dv_xname, 1811 sc->sc_state); 1812 } 1813 1814 /* 1815 * Driver is now in state NCR_CONNECTED, i.e. we 1816 * have a current command working the SCSI bus. 1817 */ 1818 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1819 panic("esp no nexus"); 1820 } 1821 1822 switch (sc->sc_phase) { 1823 case MESSAGE_OUT_PHASE: 1824 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1825 ncr53c9x_msgout(sc); 1826 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1827 break; 1828 case MESSAGE_IN_PHASE: 1829 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1830 if (sc->sc_espintr & NCRINTR_BS) { 1831 NCRCMD(sc, NCRCMD_FLUSH); 1832 sc->sc_flags |= NCR_WAITI; 1833 NCRCMD(sc, NCRCMD_TRANS); 1834 } else if (sc->sc_espintr & NCRINTR_FC) { 1835 if ((sc->sc_flags & NCR_WAITI) == 0) { 1836 printf("%s: MSGIN: unexpected FC bit: " 1837 "[intr %x, stat %x, step %x]\n", 1838 sc->sc_dev.dv_xname, 1839 sc->sc_espintr, sc->sc_espstat, 1840 sc->sc_espstep); 1841 } 1842 sc->sc_flags &= ~NCR_WAITI; 1843 ncr53c9x_msgin(sc); 1844 } else { 1845 printf("%s: MSGIN: weird bits: " 1846 "[intr %x, stat %x, step %x]\n", 1847 sc->sc_dev.dv_xname, 1848 sc->sc_espintr, sc->sc_espstat, 1849 sc->sc_espstep); 1850 } 1851 sc->sc_prevphase = MESSAGE_IN_PHASE; 1852 break; 1853 case COMMAND_PHASE: 1854 /* 1855 * Send the command block. Normally we don't see this 1856 * phase because the SEL_ATN command takes care of 1857 * all this. However, we end up here if either the 1858 * target or we wanted exchange some more messages 1859 * first (e.g. to start negotiations). 1860 */ 1861 1862 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 1863 ecb->cmd.cmd.opcode, ecb->clen)); 1864 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1865 NCRCMD(sc, NCRCMD_FLUSH); 1866 DELAY(1); 1867 } 1868 if (ncr53c9x_dmaselect) { 1869 size_t size; 1870 /* setup DMA transfer for command */ 1871 size = ecb->clen; 1872 sc->sc_cmdlen = size; 1873 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 1874 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 1875 0, &size); 1876 /* Program the SCSI counter */ 1877 NCR_WRITE_REG(sc, NCR_TCL, size); 1878 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1879 if (sc->sc_cfg2 & NCRCFG2_FE) { 1880 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1881 } 1882 1883 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 1884 NCRDMA_GO(sc); 1885 } else { 1886 u_char *cmd = (u_char *)&ecb->cmd.cmd; 1887 int i; 1888 /* Now the command into the FIFO */ 1889 for (i = 0; i < ecb->clen; i++) 1890 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 1891 NCRCMD(sc, NCRCMD_TRANS); 1892 } 1893 sc->sc_prevphase = COMMAND_PHASE; 1894 break; 1895 case DATA_OUT_PHASE: 1896 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 1897 NCRCMD(sc, NCRCMD_FLUSH); 1898 size = min(sc->sc_dleft, sc->sc_maxxfer); 1899 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1900 0, &size); 1901 sc->sc_prevphase = DATA_OUT_PHASE; 1902 goto setup_xfer; 1903 case DATA_IN_PHASE: 1904 NCR_PHASE(("DATA_IN_PHASE ")); 1905 if (sc->sc_rev == NCR_VARIANT_ESP100) 1906 NCRCMD(sc, NCRCMD_FLUSH); 1907 size = min(sc->sc_dleft, sc->sc_maxxfer); 1908 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1909 1, &size); 1910 sc->sc_prevphase = DATA_IN_PHASE; 1911 setup_xfer: 1912 /* Target returned to data phase: wipe "done" memory */ 1913 ecb->flags &= ~ECB_TENTATIVE_DONE; 1914 1915 /* Program the SCSI counter */ 1916 NCR_WRITE_REG(sc, NCR_TCL, size); 1917 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1918 if (sc->sc_cfg2 & NCRCFG2_FE) { 1919 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1920 } 1921 /* load the count in */ 1922 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1923 1924 /* 1925 * Note that if `size' is 0, we've already transceived 1926 * all the bytes we want but we're still in DATA PHASE. 1927 * Apparently, the device needs padding. Also, a 1928 * transfer size of 0 means "maximum" to the chip 1929 * DMA logic. 1930 */ 1931 NCRCMD(sc, 1932 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 1933 NCRDMA_GO(sc); 1934 return 1; 1935 case STATUS_PHASE: 1936 NCR_PHASE(("STATUS_PHASE ")); 1937 sc->sc_flags |= NCR_ICCS; 1938 NCRCMD(sc, NCRCMD_ICCS); 1939 sc->sc_prevphase = STATUS_PHASE; 1940 break; 1941 case INVALID_PHASE: 1942 break; 1943 default: 1944 printf("%s: unexpected bus phase; resetting\n", 1945 sc->sc_dev.dv_xname); 1946 goto reset; 1947 } 1948 } 1949 panic("esp: should not get here.."); 1950 1951 reset: 1952 ncr53c9x_init(sc, 1); 1953 return 1; 1954 1955 finish: 1956 ncr53c9x_done(sc, ecb); 1957 goto out; 1958 1959 sched: 1960 sc->sc_state = NCR_IDLE; 1961 ncr53c9x_sched(sc); 1962 goto out; 1963 1964 out: 1965 return 1; 1966 } 1967 1968 void 1969 ncr53c9x_abort(sc, ecb) 1970 struct ncr53c9x_softc *sc; 1971 struct ncr53c9x_ecb *ecb; 1972 { 1973 1974 /* 2 secs for the abort */ 1975 ecb->timeout = NCR_ABORT_TIMEOUT; 1976 ecb->flags |= ECB_ABORT; 1977 1978 if (ecb == sc->sc_nexus) { 1979 /* 1980 * If we're still selecting, the message will be scheduled 1981 * after selection is complete. 1982 */ 1983 if (sc->sc_state == NCR_CONNECTED) 1984 ncr53c9x_sched_msgout(SEND_ABORT); 1985 1986 /* 1987 * Reschedule timeout. First, cancel a queued timeout (if any) 1988 * in case someone decides to call ncr53c9x_abort() from 1989 * elsewhere. 1990 */ 1991 untimeout(ncr53c9x_timeout, ecb); 1992 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 1993 } else { 1994 ncr53c9x_dequeue(sc, ecb); 1995 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1996 if (sc->sc_state == NCR_IDLE) 1997 ncr53c9x_sched(sc); 1998 } 1999 } 2000 2001 void 2002 ncr53c9x_timeout(arg) 2003 void *arg; 2004 { 2005 struct ncr53c9x_ecb *ecb = arg; 2006 struct scsi_xfer *xs = ecb->xs; 2007 struct scsi_link *sc_link = xs->sc_link; 2008 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 2009 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 2010 int s; 2011 2012 sc_print_addr(sc_link); 2013 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2014 "<state %d, nexus %p, phase(c %x, p %x), resid %lx, " 2015 "msg(q %x,o %x) %s>", 2016 sc->sc_dev.dv_xname, 2017 ecb, ecb->flags, ecb->dleft, ecb->stat, 2018 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2019 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2020 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2021 #if NCR53C9X_DEBUG > 1 2022 printf("TRACE: %s.", ecb->trace); 2023 #endif 2024 2025 s = splbio(); 2026 2027 if (ecb->flags & ECB_ABORT) { 2028 /* abort timed out */ 2029 printf(" AGAIN\n"); 2030 2031 ncr53c9x_init(sc, 1); 2032 } else { 2033 /* abort the operation that has timed out */ 2034 printf("\n"); 2035 xs->error = XS_TIMEOUT; 2036 ncr53c9x_abort(sc, ecb); 2037 2038 /* Disable sync mode if stuck in a data phase */ 2039 if (ecb == sc->sc_nexus && 2040 (ti->flags & T_SYNCMODE) != 0 && 2041 (sc->sc_phase & (MSGI|CDI)) == 0) { 2042 sc_print_addr(sc_link); 2043 printf("sync negotiation disabled\n"); 2044 sc->sc_cfflags |= (1<<(sc_link->target+8)); 2045 } 2046 } 2047 2048 splx(s); 2049 } 2050
Indexes created Sun Sep 28 16:09:52 GMT 2025