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ncr53c9x.c revision 1.23
      1 /*	$NetBSD: ncr53c9x.c,v 1.23 1998/01/31 23:37:51 pk Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996 Charles M. Hannum.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Charles M. Hannum.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Copyright (c) 1994 Peter Galbavy
     34  * Copyright (c) 1995 Paul Kranenburg
     35  * All rights reserved.
     36  *
     37  * Redistribution and use in source and binary forms, with or without
     38  * modification, are permitted provided that the following conditions
     39  * are met:
     40  * 1. Redistributions of source code must retain the above copyright
     41  *    notice, this list of conditions and the following disclaimer.
     42  * 2. Redistributions in binary form must reproduce the above copyright
     43  *    notice, this list of conditions and the following disclaimer in the
     44  *    documentation and/or other materials provided with the distribution.
     45  * 3. All advertising materials mentioning features or use of this software
     46  *    must display the following acknowledgement:
     47  *	This product includes software developed by Peter Galbavy
     48  * 4. The name of the author may not be used to endorse or promote products
     49  *    derived from this software without specific prior written permission.
     50  *
     51  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     52  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     53  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     54  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     55  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     56  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     57  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     58  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     59  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     60  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     61  * POSSIBILITY OF SUCH DAMAGE.
     62  */
     63 
     64 /*
     65  * Based on aic6360 by Jarle Greipsland
     66  *
     67  * Acknowledgements: Many of the algorithms used in this driver are
     68  * inspired by the work of Julian Elischer (julian (at) tfs.com) and
     69  * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu).  Thanks a million!
     70  */
     71 
     72 #include <sys/types.h>
     73 #include <sys/param.h>
     74 #include <sys/systm.h>
     75 #include <sys/kernel.h>
     76 #include <sys/errno.h>
     77 #include <sys/ioctl.h>
     78 #include <sys/device.h>
     79 #include <sys/buf.h>
     80 #include <sys/proc.h>
     81 #include <sys/user.h>
     82 #include <sys/queue.h>
     83 
     84 #include <dev/scsipi/scsi_all.h>
     85 #include <dev/scsipi/scsipi_all.h>
     86 #include <dev/scsipi/scsiconf.h>
     87 #include <dev/scsipi/scsi_message.h>
     88 
     89 #include <machine/cpu.h>
     90 
     91 #include <dev/ic/ncr53c9xreg.h>
     92 #include <dev/ic/ncr53c9xvar.h>
     93 
     94 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/
     95 
     96 /*static*/ void	ncr53c9x_readregs	__P((struct ncr53c9x_softc *));
     97 /*static*/ void	ncr53c9x_select		__P((struct ncr53c9x_softc *,
     98 					    struct ncr53c9x_ecb *));
     99 /*static*/ int ncr53c9x_reselect	__P((struct ncr53c9x_softc *, int));
    100 /*static*/ void	ncr53c9x_scsi_reset	__P((struct ncr53c9x_softc *));
    101 /*static*/ void	ncr53c9x_init		__P((struct ncr53c9x_softc *, int));
    102 /*static*/ int	ncr53c9x_poll		__P((struct ncr53c9x_softc *,
    103 					    struct scsipi_xfer *, int));
    104 /*static*/ void	ncr53c9x_sched		__P((struct ncr53c9x_softc *));
    105 /*static*/ void	ncr53c9x_done		__P((struct ncr53c9x_softc *,
    106 					    struct ncr53c9x_ecb *));
    107 /*static*/ void	ncr53c9x_msgin		__P((struct ncr53c9x_softc *));
    108 /*static*/ void	ncr53c9x_msgout		__P((struct ncr53c9x_softc *));
    109 /*static*/ void	ncr53c9x_timeout	__P((void *arg));
    110 /*static*/ void	ncr53c9x_abort		__P((struct ncr53c9x_softc *,
    111 					    struct ncr53c9x_ecb *));
    112 /*static*/ void ncr53c9x_dequeue	__P((struct ncr53c9x_softc *,
    113 					    struct ncr53c9x_ecb *));
    114 
    115 void ncr53c9x_sense			__P((struct ncr53c9x_softc *,
    116 					    struct ncr53c9x_ecb *));
    117 void ncr53c9x_free_ecb			__P((struct ncr53c9x_softc *,
    118 					    struct ncr53c9x_ecb *, int));
    119 struct ncr53c9x_ecb *ncr53c9x_get_ecb	__P((struct ncr53c9x_softc *, int));
    120 
    121 static inline int ncr53c9x_stp2cpb	__P((struct ncr53c9x_softc *, int));
    122 static inline void ncr53c9x_setsync	__P((struct ncr53c9x_softc *,
    123 					    struct ncr53c9x_tinfo *));
    124 
    125 /*
    126  * Names for the NCR53c9x variants, correspnding to the variant tags
    127  * in ncr53c9xvar.h.
    128  */
    129 const char *ncr53c9x_variant_names[] = {
    130 	"ESP100",
    131 	"ESP100A",
    132 	"ESP200",
    133 	"NCR53C94",
    134 	"NCR53C96",
    135 	"ESP406",
    136 	"FAS408",
    137 	"FAS216",
    138 };
    139 
    140 /*
    141  * Attach this instance, and then all the sub-devices
    142  */
    143 void
    144 ncr53c9x_attach(sc, adapter, dev)
    145 	struct ncr53c9x_softc *sc;
    146 	struct scsipi_adapter *adapter;
    147 	struct scsipi_device *dev;
    148 {
    149 
    150 	/*
    151 	 * Note, the front-end has set us up to print the chip variation.
    152 	 */
    153 
    154 	if (sc->sc_rev >= NCR_VARIANT_MAX) {
    155 		printf("\n%s: unknown variant %d, devices not attached\n",
    156 		    sc->sc_dev.dv_xname, sc->sc_rev);
    157 		return;
    158 	}
    159 
    160 	printf(": %s, %dMHz, SCSI ID %d\n",
    161 	    ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id);
    162 
    163 	sc->sc_ccf = FREQTOCCF(sc->sc_freq);
    164 
    165 	/* The value *must not* be == 1. Make it 2 */
    166 	if (sc->sc_ccf == 1)
    167 		sc->sc_ccf = 2;
    168 
    169 	/*
    170 	 * The recommended timeout is 250ms. This register is loaded
    171 	 * with a value calculated as follows, from the docs:
    172 	 *
    173 	 *		(timout period) x (CLK frequency)
    174 	 *	reg = -------------------------------------
    175 	 *		 8192 x (Clock Conversion Factor)
    176 	 *
    177 	 * Since CCF has a linear relation to CLK, this generally computes
    178 	 * to the constant of 153.
    179 	 */
    180 	sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf);
    181 
    182 	/* CCF register only has 3 bits; 0 is actually 8 */
    183 	sc->sc_ccf &= 7;
    184 
    185 	/* Reset state & bus */
    186 	sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags;
    187 	sc->sc_state = 0;
    188 	ncr53c9x_init(sc, 1);
    189 
    190 	/*
    191 	 * fill in the prototype scsipi_link.
    192 	 */
    193 	sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
    194 	sc->sc_link.adapter_softc = sc;
    195 	sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id;
    196 	sc->sc_link.adapter = adapter;
    197 	sc->sc_link.device = dev;
    198 	sc->sc_link.openings = 2;
    199 	sc->sc_link.scsipi_scsi.max_target = 7;
    200 	sc->sc_link.type = BUS_SCSI;
    201 
    202 	/*
    203 	 * Now try to attach all the sub-devices
    204 	 */
    205 	config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
    206 
    207 	/*
    208 	 * Enable interupts from the SCSI core
    209 	 */
    210 	if ((sc->sc_rev == NCR_VARIANT_ESP406) ||
    211 	    (sc->sc_rev == NCR_VARIANT_FAS408)) {
    212 		NCR_PIOREGS(sc);
    213 		NCR_WRITE_REG(sc, NCR_CFG5, NCRCFG5_SINT |
    214 		    NCR_READ_REG(sc, NCR_CFG5));
    215 		NCR_SCSIREGS(sc);
    216 	}
    217 }
    218 
    219 /*
    220  * This is the generic esp reset function. It does not reset the SCSI bus,
    221  * only this controllers, but kills any on-going commands, and also stops
    222  * and resets the DMA.
    223  *
    224  * After reset, registers are loaded with the defaults from the attach
    225  * routine above.
    226  */
    227 void
    228 ncr53c9x_reset(sc)
    229 	struct ncr53c9x_softc *sc;
    230 {
    231 
    232 	/* reset DMA first */
    233 	NCRDMA_RESET(sc);
    234 
    235 	/* reset SCSI chip */
    236 	NCRCMD(sc, NCRCMD_RSTCHIP);
    237 	NCRCMD(sc, NCRCMD_NOP);
    238 	DELAY(500);
    239 
    240 	/* do these backwards, and fall through */
    241 	switch (sc->sc_rev) {
    242 	case NCR_VARIANT_ESP406:
    243 	case NCR_VARIANT_FAS408:
    244 		NCR_SCSIREGS(sc);
    245 	case NCR_VARIANT_FAS216:
    246 	case NCR_VARIANT_NCR53C94:
    247 	case NCR_VARIANT_NCR53C96:
    248 	case NCR_VARIANT_ESP200:
    249 		NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
    250 	case NCR_VARIANT_ESP100A:
    251 		NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
    252 	case NCR_VARIANT_ESP100:
    253 		NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
    254 		NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
    255 		NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
    256 		NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
    257 		break;
    258 	default:
    259 		printf("%s: unknown revision code, assuming ESP100\n",
    260 		    sc->sc_dev.dv_xname);
    261 		NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
    262 		NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
    263 		NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
    264 		NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
    265 	}
    266 }
    267 
    268 /*
    269  * Reset the SCSI bus, but not the chip
    270  */
    271 void
    272 ncr53c9x_scsi_reset(sc)
    273 	struct ncr53c9x_softc *sc;
    274 {
    275 
    276 	(*sc->sc_glue->gl_dma_stop)(sc);
    277 
    278 	printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname);
    279 	NCRCMD(sc, NCRCMD_RSTSCSI);
    280 }
    281 
    282 /*
    283  * Initialize esp state machine
    284  */
    285 void
    286 ncr53c9x_init(sc, doreset)
    287 	struct ncr53c9x_softc *sc;
    288 	int doreset;
    289 {
    290 	struct ncr53c9x_ecb *ecb;
    291 	int r;
    292 
    293 	NCR_TRACE(("[NCR_INIT(%d)] ", doreset));
    294 
    295 	if (sc->sc_state == 0) {
    296 		/* First time through; initialize. */
    297 		TAILQ_INIT(&sc->ready_list);
    298 		TAILQ_INIT(&sc->nexus_list);
    299 		TAILQ_INIT(&sc->free_list);
    300 		sc->sc_nexus = NULL;
    301 		ecb = sc->sc_ecb;
    302 		bzero(ecb, sizeof(sc->sc_ecb));
    303 		for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) {
    304 			TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain);
    305 			ecb++;
    306 		}
    307 		bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo));
    308 	} else {
    309 		/* Cancel any active commands. */
    310 		sc->sc_state = NCR_CLEANING;
    311 		if ((ecb = sc->sc_nexus) != NULL) {
    312 			ecb->xs->error = XS_TIMEOUT;
    313 			ncr53c9x_done(sc, ecb);
    314 		}
    315 		while ((ecb = sc->nexus_list.tqh_first) != NULL) {
    316 			ecb->xs->error = XS_TIMEOUT;
    317 			ncr53c9x_done(sc, ecb);
    318 		}
    319 	}
    320 
    321 	/*
    322 	 * reset the chip to a known state
    323 	 */
    324 	ncr53c9x_reset(sc);
    325 
    326 	sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
    327 	for (r = 0; r < 8; r++) {
    328 		struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r];
    329 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */
    330 
    331 		ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8))))
    332 				? T_NEGOTIATE : 0) |
    333 				((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) |
    334 				T_NEED_TO_RESET;
    335 		ti->period = sc->sc_minsync;
    336 		ti->offset = 0;
    337 	}
    338 
    339 	if (doreset) {
    340 		sc->sc_state = NCR_SBR;
    341 		NCRCMD(sc, NCRCMD_RSTSCSI);
    342 	} else {
    343 		sc->sc_state = NCR_IDLE;
    344 		ncr53c9x_sched(sc);
    345 	}
    346 }
    347 
    348 /*
    349  * Read the NCR registers, and save their contents for later use.
    350  * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading
    351  * NCR_INTR - so make sure it is the last read.
    352  *
    353  * I think that (from reading the docs) most bits in these registers
    354  * only make sense when he DMA CSR has an interrupt showing. Call only
    355  * if an interrupt is pending.
    356  */
    357 void
    358 ncr53c9x_readregs(sc)
    359 	struct ncr53c9x_softc *sc;
    360 {
    361 
    362 	sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT);
    363 	/* Only the stepo bits are of interest */
    364 	sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK;
    365 	sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR);
    366 
    367 	if (sc->sc_glue->gl_clear_latched_intr != NULL)
    368 		(*sc->sc_glue->gl_clear_latched_intr)(sc);
    369 
    370 	/*
    371 	 * Determine the SCSI bus phase, return either a real SCSI bus phase
    372 	 * or some pseudo phase we use to detect certain exceptions.
    373 	 */
    374 
    375 	sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS)
    376 			? /* Disconnected */ BUSFREE_PHASE
    377 			: sc->sc_espstat & NCRSTAT_PHASE;
    378 
    379 	NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ",
    380 		sc->sc_espintr, sc->sc_espstat, sc->sc_espstep));
    381 }
    382 
    383 /*
    384  * Convert Synchronous Transfer Period to chip register Clock Per Byte value.
    385  */
    386 static inline int
    387 ncr53c9x_stp2cpb(sc, period)
    388 	struct ncr53c9x_softc *sc;
    389 	int period;
    390 {
    391 	int v;
    392 	v = (sc->sc_freq * period) / 250;
    393 	if (ncr53c9x_cpb2stp(sc, v) < period)
    394 		/* Correct round-down error */
    395 		v++;
    396 	return v;
    397 }
    398 
    399 static inline void
    400 ncr53c9x_setsync(sc, ti)
    401 	struct ncr53c9x_softc *sc;
    402 	struct ncr53c9x_tinfo *ti;
    403 {
    404 
    405 	if (ti->flags & T_SYNCMODE) {
    406 		NCR_WRITE_REG(sc, NCR_SYNCOFF, ti->offset);
    407 		NCR_WRITE_REG(sc, NCR_SYNCTP,
    408 		    ncr53c9x_stp2cpb(sc, ti->period));
    409 	} else {
    410 		NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
    411 		NCR_WRITE_REG(sc, NCR_SYNCTP, 0);
    412 	}
    413 }
    414 
    415 int ncr53c9x_dmaselect = 0;
    416 /*
    417  * Send a command to a target, set the driver state to NCR_SELECTING
    418  * and let the caller take care of the rest.
    419  *
    420  * Keeping this as a function allows me to say that this may be done
    421  * by DMA instead of programmed I/O soon.
    422  */
    423 void
    424 ncr53c9x_select(sc, ecb)
    425 	struct ncr53c9x_softc *sc;
    426 	struct ncr53c9x_ecb *ecb;
    427 {
    428 	struct scsipi_link *sc_link = ecb->xs->sc_link;
    429 	int target = sc_link->scsipi_scsi.target;
    430 	int lun = sc_link->scsipi_scsi.lun;
    431 	struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target];
    432 	int tiflags = ti->flags;
    433 	u_char *cmd;
    434 	int clen;
    435 
    436 	NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ",
    437 		   target, lun, ecb->cmd.cmd.opcode));
    438 
    439 	sc->sc_state = NCR_SELECTING;
    440 
    441 	/*
    442 	 * Schedule the timeout now, the first time we will go away
    443 	 * expecting to come back due to an interrupt, because it is
    444 	 * always possible that the interrupt may never happen.
    445 	 */
    446 	if ((ecb->xs->flags & SCSI_POLL) == 0)
    447 		timeout(ncr53c9x_timeout, ecb,
    448 		    (ecb->timeout * hz) / 1000);
    449 
    450 	/*
    451 	 * The docs say the target register is never reset, and I
    452 	 * can't think of a better place to set it
    453 	 */
    454 	NCR_WRITE_REG(sc, NCR_SELID, target);
    455 	ncr53c9x_setsync(sc, ti);
    456 
    457 	if (ncr53c9x_dmaselect && (tiflags & T_NEGOTIATE) == 0) {
    458 		size_t dmasize;
    459 
    460 		ecb->cmd.id =
    461 		    MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1);
    462 
    463 
    464 		/* setup DMA transfer for command */
    465 		dmasize = clen = ecb->clen + 1;
    466 		sc->sc_cmdlen = clen;
    467 		sc->sc_cmdp = (caddr_t)&ecb->cmd;
    468 		NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize);
    469 
    470 		/* Program the SCSI counter */
    471 		NCR_WRITE_REG(sc, NCR_TCL, dmasize);
    472 		NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8);
    473 		if (sc->sc_cfg2 & NCRCFG2_FE) {
    474 			NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16);
    475 		}
    476 
    477 		/* load the count in */
    478 		NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
    479 
    480 		/* And get the targets attention */
    481 		NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA);
    482 		NCRDMA_GO(sc);
    483 		return;
    484 	}
    485 
    486 	/*
    487 	 * Who am I. This is where we tell the target that we are
    488 	 * happy for it to disconnect etc.
    489 	 */
    490 	NCR_WRITE_REG(sc, NCR_FIFO,
    491 		      MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1));
    492 
    493 	if (ti->flags & T_NEGOTIATE) {
    494 		/* Arbitrate, select and stop after IDENTIFY message */
    495 		NCRCMD(sc, NCRCMD_SELATNS);
    496 		return;
    497 	}
    498 
    499 	/* Now the command into the FIFO */
    500 	cmd = (u_char *)&ecb->cmd.cmd;
    501 	clen = ecb->clen;
    502 	while (clen--)
    503 		NCR_WRITE_REG(sc, NCR_FIFO, *cmd++);
    504 
    505 	/* And get the targets attention */
    506 	NCRCMD(sc, NCRCMD_SELATN);
    507 }
    508 
    509 void
    510 ncr53c9x_free_ecb(sc, ecb, flags)
    511 	struct ncr53c9x_softc *sc;
    512 	struct ncr53c9x_ecb *ecb;
    513 	int flags;
    514 {
    515 	int s;
    516 
    517 	s = splbio();
    518 
    519 	ecb->flags = 0;
    520 	TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain);
    521 
    522 	/*
    523 	 * If there were none, wake anybody waiting for one to come free,
    524 	 * starting with queued entries.
    525 	 */
    526 	if (ecb->chain.tqe_next == 0)
    527 		wakeup(&sc->free_list);
    528 
    529 	splx(s);
    530 }
    531 
    532 struct ncr53c9x_ecb *
    533 ncr53c9x_get_ecb(sc, flags)
    534 	struct ncr53c9x_softc *sc;
    535 	int flags;
    536 {
    537 	struct ncr53c9x_ecb *ecb;
    538 	int s;
    539 
    540 	s = splbio();
    541 
    542 	while ((ecb = sc->free_list.tqh_first) == NULL &&
    543 	       (flags & SCSI_NOSLEEP) == 0)
    544 		tsleep(&sc->free_list, PRIBIO, "especb", 0);
    545 	if (ecb) {
    546 		TAILQ_REMOVE(&sc->free_list, ecb, chain);
    547 		ecb->flags |= ECB_ALLOC;
    548 	}
    549 
    550 	splx(s);
    551 	return ecb;
    552 }
    553 
    554 /*
    555  * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
    556  */
    557 
    558 /*
    559  * Start a SCSI-command
    560  * This function is called by the higher level SCSI-driver to queue/run
    561  * SCSI-commands.
    562  */
    563 int
    564 ncr53c9x_scsi_cmd(xs)
    565 	struct scsipi_xfer *xs;
    566 {
    567 	struct scsipi_link *sc_link = xs->sc_link;
    568 	struct ncr53c9x_softc *sc = sc_link->adapter_softc;
    569 	struct ncr53c9x_ecb *ecb;
    570 	int s, flags;
    571 
    572 	NCR_TRACE(("[ncr53c9x_scsi_cmd] "));
    573 	NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen,
    574 	    sc_link->scsipi_scsi.target));
    575 
    576 	flags = xs->flags;
    577 	if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL)
    578 		return TRY_AGAIN_LATER;
    579 
    580 	/* Initialize ecb */
    581 	ecb->xs = xs;
    582 	ecb->timeout = xs->timeout;
    583 
    584 	if (flags & SCSI_RESET) {
    585 		ecb->flags |= ECB_RESET;
    586 		ecb->clen = 0;
    587 		ecb->dleft = 0;
    588 	} else {
    589 		bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen);
    590 		ecb->clen = xs->cmdlen;
    591 		ecb->daddr = xs->data;
    592 		ecb->dleft = xs->datalen;
    593 	}
    594 	ecb->stat = 0;
    595 
    596 	s = splbio();
    597 
    598 	TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain);
    599 	if (sc->sc_state == NCR_IDLE)
    600 		ncr53c9x_sched(sc);
    601 
    602 	splx(s);
    603 
    604 	if ((flags & SCSI_POLL) == 0)
    605 		return SUCCESSFULLY_QUEUED;
    606 
    607 	/* Not allowed to use interrupts, use polling instead */
    608 	if (ncr53c9x_poll(sc, xs, ecb->timeout)) {
    609 		ncr53c9x_timeout(ecb);
    610 		if (ncr53c9x_poll(sc, xs, ecb->timeout))
    611 			ncr53c9x_timeout(ecb);
    612 	}
    613 	return COMPLETE;
    614 }
    615 
    616 /*
    617  * Used when interrupt driven I/O isn't allowed, e.g. during boot.
    618  */
    619 int
    620 ncr53c9x_poll(sc, xs, count)
    621 	struct ncr53c9x_softc *sc;
    622 	struct scsipi_xfer *xs;
    623 	int count;
    624 {
    625 
    626 	NCR_TRACE(("[ncr53c9x_poll] "));
    627 	while (count) {
    628 		if (NCRDMA_ISINTR(sc)) {
    629 			ncr53c9x_intr(sc);
    630 		}
    631 #if alternatively
    632 		if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT)
    633 			ncr53c9x_intr(sc);
    634 #endif
    635 		if ((xs->flags & ITSDONE) != 0)
    636 			return 0;
    637 		if (sc->sc_state == NCR_IDLE) {
    638 			NCR_TRACE(("[ncr53c9x_poll: rescheduling] "));
    639 			ncr53c9x_sched(sc);
    640 		}
    641 		DELAY(1000);
    642 		count--;
    643 	}
    644 	return 1;
    645 }
    646 
    647 
    648 /*
    649  * LOW LEVEL SCSI UTILITIES
    650  */
    651 
    652 /*
    653  * Schedule a scsi operation.  This has now been pulled out of the interrupt
    654  * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done.
    655  * This may save us an unecessary interrupt just to get things going.
    656  * Should only be called when state == NCR_IDLE and at bio pl.
    657  */
    658 void
    659 ncr53c9x_sched(sc)
    660 	struct ncr53c9x_softc *sc;
    661 {
    662 	struct ncr53c9x_ecb *ecb;
    663 	struct scsipi_link *sc_link;
    664 	struct ncr53c9x_tinfo *ti;
    665 
    666 	NCR_TRACE(("[ncr53c9x_sched] "));
    667 	if (sc->sc_state != NCR_IDLE)
    668 		panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state);
    669 
    670 	/*
    671 	 * Find first ecb in ready queue that is for a target/lunit
    672 	 * combinations that is not busy.
    673 	 */
    674 	for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) {
    675 		sc_link = ecb->xs->sc_link;
    676 		ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
    677 		if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) {
    678 			TAILQ_REMOVE(&sc->ready_list, ecb, chain);
    679 			sc->sc_nexus = ecb;
    680 			ncr53c9x_select(sc, ecb);
    681 			break;
    682 		} else
    683 			NCR_MISC(("%d:%d busy\n",
    684 				  sc_link->scsipi_scsi.target,
    685 				  sc_link->scsipi_scsi.lun));
    686 	}
    687 }
    688 
    689 void
    690 ncr53c9x_sense(sc, ecb)
    691 	struct ncr53c9x_softc *sc;
    692 	struct ncr53c9x_ecb *ecb;
    693 {
    694 	struct scsipi_xfer *xs = ecb->xs;
    695 	struct scsipi_link *sc_link = xs->sc_link;
    696 	struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
    697 	struct scsipi_sense *ss = (void *)&ecb->cmd.cmd;
    698 
    699 	NCR_MISC(("requesting sense "));
    700 	/* Next, setup a request sense command block */
    701 	bzero(ss, sizeof(*ss));
    702 	ss->opcode = REQUEST_SENSE;
    703 	ss->byte2 = sc_link->scsipi_scsi.lun << 5;
    704 	ss->length = sizeof(struct scsipi_sense_data);
    705 	ecb->clen = sizeof(*ss);
    706 	ecb->daddr = (char *)&xs->sense.scsi_sense;
    707 	ecb->dleft = sizeof(struct scsipi_sense_data);
    708 	ecb->flags |= ECB_SENSE;
    709 	ecb->timeout = NCR_SENSE_TIMEOUT;
    710 	ti->senses++;
    711 	if (ecb->flags & ECB_NEXUS)
    712 		ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun);
    713 	if (ecb == sc->sc_nexus) {
    714 		ecb->flags &= ~ECB_NEXUS;
    715 		ncr53c9x_select(sc, ecb);
    716 	} else {
    717 		ncr53c9x_dequeue(sc, ecb);
    718 		TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
    719 		if (sc->sc_state == NCR_IDLE)
    720 			ncr53c9x_sched(sc);
    721 	}
    722 }
    723 
    724 /*
    725  * POST PROCESSING OF SCSI_CMD (usually current)
    726  */
    727 void
    728 ncr53c9x_done(sc, ecb)
    729 	struct ncr53c9x_softc *sc;
    730 	struct ncr53c9x_ecb *ecb;
    731 {
    732 	struct scsipi_xfer *xs = ecb->xs;
    733 	struct scsipi_link *sc_link = xs->sc_link;
    734 	struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
    735 
    736 	NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error));
    737 
    738 	untimeout(ncr53c9x_timeout, ecb);
    739 
    740 	/*
    741 	 * Now, if we've come here with no error code, i.e. we've kept the
    742 	 * initial XS_NOERROR, and the status code signals that we should
    743 	 * check sense, we'll need to set up a request sense cmd block and
    744 	 * push the command back into the ready queue *before* any other
    745 	 * commands for this target/lunit, else we lose the sense info.
    746 	 * We don't support chk sense conditions for the request sense cmd.
    747 	 */
    748 	if (xs->error == XS_NOERROR) {
    749 		xs->status = ecb->stat;
    750 		if ((ecb->flags & ECB_ABORT) != 0) {
    751 			xs->error = XS_TIMEOUT;
    752 		} else if ((ecb->flags & ECB_SENSE) != 0) {
    753 			xs->error = XS_SENSE;
    754 		} else if ((ecb->stat & ST_MASK) == SCSI_CHECK) {
    755 			/* First, save the return values */
    756 			xs->resid = ecb->dleft;
    757 			ncr53c9x_sense(sc, ecb);
    758 			return;
    759 		} else {
    760 			xs->resid = ecb->dleft;
    761 		}
    762 	}
    763 
    764 	xs->flags |= ITSDONE;
    765 
    766 #ifdef NCR53C9X_DEBUG
    767 	if (ncr53c9x_debug & NCR_SHOWMISC) {
    768 		if (xs->resid != 0)
    769 			printf("resid=%d ", xs->resid);
    770 		if (xs->error == XS_SENSE)
    771 			printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code);
    772 		else
    773 			printf("error=%d\n", xs->error);
    774 	}
    775 #endif
    776 
    777 	/*
    778 	 * Remove the ECB from whatever queue it's on.
    779 	 */
    780 	if (ecb->flags & ECB_NEXUS)
    781 		ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun);
    782 	if (ecb == sc->sc_nexus) {
    783 		sc->sc_nexus = NULL;
    784 		if (sc->sc_state != NCR_CLEANING) {
    785 			sc->sc_state = NCR_IDLE;
    786 			ncr53c9x_sched(sc);
    787 		}
    788 	} else
    789 		ncr53c9x_dequeue(sc, ecb);
    790 
    791 	ncr53c9x_free_ecb(sc, ecb, xs->flags);
    792 	ti->cmds++;
    793 	scsipi_done(xs);
    794 }
    795 
    796 void
    797 ncr53c9x_dequeue(sc, ecb)
    798 	struct ncr53c9x_softc *sc;
    799 	struct ncr53c9x_ecb *ecb;
    800 {
    801 
    802 	if (ecb->flags & ECB_NEXUS) {
    803 		TAILQ_REMOVE(&sc->nexus_list, ecb, chain);
    804 		ecb->flags &= ~ECB_NEXUS;
    805 	} else {
    806 		TAILQ_REMOVE(&sc->ready_list, ecb, chain);
    807 	}
    808 }
    809 
    810 /*
    811  * INTERRUPT/PROTOCOL ENGINE
    812  */
    813 
    814 /*
    815  * Schedule an outgoing message by prioritizing it, and asserting
    816  * attention on the bus. We can only do this when we are the initiator
    817  * else there will be an illegal command interrupt.
    818  */
    819 #define ncr53c9x_sched_msgout(m) \
    820 	do {							\
    821 		NCR_MISC(("ncr53c9x_sched_msgout %d ", m));	\
    822 		NCRCMD(sc, NCRCMD_SETATN);			\
    823 		sc->sc_flags |= NCR_ATN;			\
    824 		sc->sc_msgpriq |= (m);				\
    825 	} while (0)
    826 
    827 int
    828 ncr53c9x_reselect(sc, message)
    829 	struct ncr53c9x_softc *sc;
    830 	int message;
    831 {
    832 	u_char selid, target, lun;
    833 	struct ncr53c9x_ecb *ecb;
    834 	struct scsipi_link *sc_link;
    835 	struct ncr53c9x_tinfo *ti;
    836 
    837 	/*
    838 	 * The SCSI chip made a snapshot of the data bus while the reselection
    839 	 * was being negotiated.  This enables us to determine which target did
    840 	 * the reselect.
    841 	 */
    842 	selid = sc->sc_selid & ~(1 << sc->sc_id);
    843 	if (selid & (selid - 1)) {
    844 		printf("%s: reselect with invalid selid %02x;"
    845 		    " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid);
    846 		goto reset;
    847 	}
    848 
    849 	/*
    850 	 * Search wait queue for disconnected cmd
    851 	 * The list should be short, so I haven't bothered with
    852 	 * any more sophisticated structures than a simple
    853 	 * singly linked list.
    854 	 */
    855 	target = ffs(selid) - 1;
    856 	lun = message & 0x07;
    857 	for (ecb = sc->nexus_list.tqh_first; ecb != NULL;
    858 	     ecb = ecb->chain.tqe_next) {
    859 		sc_link = ecb->xs->sc_link;
    860 		if (sc_link->scsipi_scsi.target == target &&
    861 		    sc_link->scsipi_scsi.lun == lun)
    862 			break;
    863 	}
    864 	if (ecb == NULL) {
    865 		printf("%s: reselect from target %d lun %d with no nexus;"
    866 		    " sending ABORT\n", sc->sc_dev.dv_xname, target, lun);
    867 		goto abort;
    868 	}
    869 
    870 	/* Make this nexus active again. */
    871 	TAILQ_REMOVE(&sc->nexus_list, ecb, chain);
    872 	sc->sc_state = NCR_CONNECTED;
    873 	sc->sc_nexus = ecb;
    874 	ti = &sc->sc_tinfo[target];
    875 #ifdef NCR53C9X_DEBUG
    876 	if ((ti->lubusy & (1 << lun)) == 0) {
    877 		printf("%s: reselect: target %d, lun %d: should be busy\n",
    878 			sc->sc_dev.dv_xname, target, lun);
    879 		ti->lubusy |= (1 << lun);
    880 	}
    881 #endif
    882 	ncr53c9x_setsync(sc, ti);
    883 
    884 	if (ecb->flags & ECB_RESET)
    885 		ncr53c9x_sched_msgout(SEND_DEV_RESET);
    886 	else if (ecb->flags & ECB_ABORT)
    887 		ncr53c9x_sched_msgout(SEND_ABORT);
    888 
    889 	/* Do an implicit RESTORE POINTERS. */
    890 	sc->sc_dp = ecb->daddr;
    891 	sc->sc_dleft = ecb->dleft;
    892 
    893 	return (0);
    894 
    895 reset:
    896 	ncr53c9x_sched_msgout(SEND_DEV_RESET);
    897 	return (1);
    898 
    899 abort:
    900 	ncr53c9x_sched_msgout(SEND_ABORT);
    901 	return (1);
    902 }
    903 
    904 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80)
    905 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20)
    906 #define ISEXTMSG(m) ((m) == 1)
    907 
    908 /*
    909  * Get an incoming message as initiator.
    910  *
    911  * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a
    912  * byte in the FIFO
    913  */
    914 void
    915 ncr53c9x_msgin(sc)
    916 	register struct ncr53c9x_softc *sc;
    917 {
    918 	register int v;
    919 
    920 	NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen));
    921 
    922 	if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) {
    923 		printf("%s: msgin: no msg byte available\n",
    924 			sc->sc_dev.dv_xname);
    925 		return;
    926 	}
    927 
    928 	/*
    929 	 * Prepare for a new message.  A message should (according
    930 	 * to the SCSI standard) be transmitted in one single
    931 	 * MESSAGE_IN_PHASE. If we have been in some other phase,
    932 	 * then this is a new message.
    933 	 */
    934 	if (sc->sc_prevphase != MESSAGE_IN_PHASE) {
    935 		sc->sc_flags &= ~NCR_DROP_MSGI;
    936 		sc->sc_imlen = 0;
    937 	}
    938 
    939 	v = NCR_READ_REG(sc, NCR_FIFO);
    940 	NCR_MISC(("<msgbyte:0x%02x>", v));
    941 
    942 #if 0
    943 	if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) {
    944 		/*
    945 		 * Which target is reselecting us? (The ID bit really)
    946 		 */
    947 		sc->sc_selid = v;
    948 		NCR_MISC(("selid=0x%2x ", sc->sc_selid));
    949 		return;
    950 	}
    951 #endif
    952 
    953 	sc->sc_imess[sc->sc_imlen] = v;
    954 
    955 	/*
    956 	 * If we're going to reject the message, don't bother storing
    957 	 * the incoming bytes.  But still, we need to ACK them.
    958 	 */
    959 
    960 	if ((sc->sc_flags & NCR_DROP_MSGI)) {
    961 		NCRCMD(sc, NCRCMD_MSGOK);
    962 		printf("<dropping msg byte %x>",
    963 			sc->sc_imess[sc->sc_imlen]);
    964 		return;
    965 	}
    966 
    967 	if (sc->sc_imlen >= NCR_MAX_MSG_LEN) {
    968 		ncr53c9x_sched_msgout(SEND_REJECT);
    969 		sc->sc_flags |= NCR_DROP_MSGI;
    970 	} else {
    971 		sc->sc_imlen++;
    972 		/*
    973 		 * This testing is suboptimal, but most
    974 		 * messages will be of the one byte variety, so
    975 		 * it should not effect performance
    976 		 * significantly.
    977 		 */
    978 		if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0]))
    979 			goto gotit;
    980 		if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0]))
    981 			goto gotit;
    982 		if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) &&
    983 		    sc->sc_imlen == sc->sc_imess[1] + 2)
    984 			goto gotit;
    985 	}
    986 	/* Ack what we have so far */
    987 	NCRCMD(sc, NCRCMD_MSGOK);
    988 	return;
    989 
    990 gotit:
    991 	NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0]));
    992 	/*
    993 	 * Now we should have a complete message (1 byte, 2 byte
    994 	 * and moderately long extended messages).  We only handle
    995 	 * extended messages which total length is shorter than
    996 	 * NCR_MAX_MSG_LEN.  Longer messages will be amputated.
    997 	 */
    998 	switch (sc->sc_state) {
    999 		struct ncr53c9x_ecb *ecb;
   1000 		struct ncr53c9x_tinfo *ti;
   1001 
   1002 	case NCR_CONNECTED:
   1003 		ecb = sc->sc_nexus;
   1004 		ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
   1005 
   1006 		switch (sc->sc_imess[0]) {
   1007 		case MSG_CMDCOMPLETE:
   1008 			NCR_MSGS(("cmdcomplete "));
   1009 			if (sc->sc_dleft < 0) {
   1010 				struct scsipi_link *sc_link = ecb->xs->sc_link;
   1011 				printf("%s: %ld extra bytes from %d:%d\n",
   1012 				    sc->sc_dev.dv_xname, -(long)sc->sc_dleft,
   1013 				    sc_link->scsipi_scsi.target, sc_link->scsipi_scsi.lun);
   1014 				sc->sc_dleft = 0;
   1015 			}
   1016 			ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE)
   1017 				? 0
   1018 				: sc->sc_dleft;
   1019 			if ((ecb->flags & ECB_SENSE) == 0)
   1020 				ecb->xs->resid = ecb->dleft;
   1021 			sc->sc_state = NCR_CMDCOMPLETE;
   1022 			break;
   1023 
   1024 		case MSG_MESSAGE_REJECT:
   1025 			NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout));
   1026 			switch (sc->sc_msgout) {
   1027 			case SEND_SDTR:
   1028 				sc->sc_flags &= ~NCR_SYNCHNEGO;
   1029 				ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE);
   1030 				ncr53c9x_setsync(sc, ti);
   1031 				break;
   1032 			case SEND_INIT_DET_ERR:
   1033 				goto abort;
   1034 			}
   1035 			break;
   1036 
   1037 		case MSG_NOOP:
   1038 			NCR_MSGS(("noop "));
   1039 			break;
   1040 
   1041 		case MSG_DISCONNECT:
   1042 			NCR_MSGS(("disconnect "));
   1043 			ti->dconns++;
   1044 			sc->sc_state = NCR_DISCONNECT;
   1045 
   1046 			/*
   1047 			 * Mark the fact that all bytes have moved. The
   1048 			 * target may not bother to do a SAVE POINTERS
   1049 			 * at this stage. This flag will set the residual
   1050 			 * count to zero on MSG COMPLETE.
   1051 			 */
   1052 			if (sc->sc_dleft == 0)
   1053 				ecb->flags |= ECB_TENTATIVE_DONE;
   1054 
   1055 			break;
   1056 
   1057 		case MSG_SAVEDATAPOINTER:
   1058 			NCR_MSGS(("save datapointer "));
   1059 			ecb->daddr = sc->sc_dp;
   1060 			ecb->dleft = sc->sc_dleft;
   1061 			break;
   1062 
   1063 		case MSG_RESTOREPOINTERS:
   1064 			NCR_MSGS(("restore datapointer "));
   1065 			sc->sc_dp = ecb->daddr;
   1066 			sc->sc_dleft = ecb->dleft;
   1067 			break;
   1068 
   1069 		case MSG_EXTENDED:
   1070 			NCR_MSGS(("extended(%x) ", sc->sc_imess[2]));
   1071 			switch (sc->sc_imess[2]) {
   1072 			case MSG_EXT_SDTR:
   1073 				NCR_MSGS(("SDTR period %d, offset %d ",
   1074 					sc->sc_imess[3], sc->sc_imess[4]));
   1075 				if (sc->sc_imess[1] != 3)
   1076 					goto reject;
   1077 				ti->period = sc->sc_imess[3];
   1078 				ti->offset = sc->sc_imess[4];
   1079 				ti->flags &= ~T_NEGOTIATE;
   1080 				if (sc->sc_minsync == 0 ||
   1081 				    ti->offset == 0 ||
   1082 				    ti->period > 124) {
   1083 					printf("%s:%d: async\n", "esp",
   1084 						ecb->xs->sc_link->scsipi_scsi.target);
   1085 					if ((sc->sc_flags&NCR_SYNCHNEGO)
   1086 					    == 0) {
   1087 						/*
   1088 						 * target initiated negotiation
   1089 						 */
   1090 						ti->offset = 0;
   1091 						ti->flags &= ~T_SYNCMODE;
   1092 						ncr53c9x_sched_msgout(
   1093 						    SEND_SDTR);
   1094 					} else {
   1095 						/* we are async */
   1096 						ti->flags &= ~T_SYNCMODE;
   1097 					}
   1098 				} else {
   1099 					int r = 250/ti->period;
   1100 					int s = (100*250)/ti->period - 100*r;
   1101 					int p;
   1102 
   1103 					p = ncr53c9x_stp2cpb(sc, ti->period);
   1104 					ti->period = ncr53c9x_cpb2stp(sc, p);
   1105 #ifdef NCR53C9X_DEBUG
   1106 					scsi_print_addr(ecb->xs->sc_link);
   1107 					printf("max sync rate %d.%02dMb/s\n",
   1108 						r, s);
   1109 #endif
   1110 					if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) {
   1111 						/*
   1112 						 * target initiated negotiation
   1113 						 */
   1114 						if (ti->period <
   1115 						    sc->sc_minsync)
   1116 							ti->period =
   1117 							    sc->sc_minsync;
   1118 						if (ti->offset > 15)
   1119 							ti->offset = 15;
   1120 						ti->flags &= ~T_SYNCMODE;
   1121 						ncr53c9x_sched_msgout(
   1122 						    SEND_SDTR);
   1123 					} else {
   1124 						/* we are sync */
   1125 						ti->flags |= T_SYNCMODE;
   1126 					}
   1127 				}
   1128 				sc->sc_flags &= ~NCR_SYNCHNEGO;
   1129 				ncr53c9x_setsync(sc, ti);
   1130 				break;
   1131 
   1132 			default:
   1133 				printf("%s: unrecognized MESSAGE EXTENDED;"
   1134 				    " sending REJECT\n", sc->sc_dev.dv_xname);
   1135 				goto reject;
   1136 			}
   1137 			break;
   1138 
   1139 		default:
   1140 			NCR_MSGS(("ident "));
   1141 			printf("%s: unrecognized MESSAGE; sending REJECT\n",
   1142 			    sc->sc_dev.dv_xname);
   1143 		reject:
   1144 			ncr53c9x_sched_msgout(SEND_REJECT);
   1145 			break;
   1146 		}
   1147 		break;
   1148 
   1149 	case NCR_RESELECTED:
   1150 		if (!MSG_ISIDENTIFY(sc->sc_imess[0])) {
   1151 			printf("%s: reselect without IDENTIFY;"
   1152 			    " sending DEVICE RESET\n", sc->sc_dev.dv_xname);
   1153 			goto reset;
   1154 		}
   1155 
   1156 		(void) ncr53c9x_reselect(sc, sc->sc_imess[0]);
   1157 		break;
   1158 
   1159 	default:
   1160 		printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n",
   1161 		    sc->sc_dev.dv_xname);
   1162 	reset:
   1163 		ncr53c9x_sched_msgout(SEND_DEV_RESET);
   1164 		break;
   1165 
   1166 	abort:
   1167 		ncr53c9x_sched_msgout(SEND_ABORT);
   1168 		break;
   1169 	}
   1170 
   1171 	/* Ack last message byte */
   1172 	NCRCMD(sc, NCRCMD_MSGOK);
   1173 
   1174 	/* Done, reset message pointer. */
   1175 	sc->sc_flags &= ~NCR_DROP_MSGI;
   1176 	sc->sc_imlen = 0;
   1177 }
   1178 
   1179 
   1180 /*
   1181  * Send the highest priority, scheduled message
   1182  */
   1183 void
   1184 ncr53c9x_msgout(sc)
   1185 	register struct ncr53c9x_softc *sc;
   1186 {
   1187 	struct ncr53c9x_tinfo *ti;
   1188 	struct ncr53c9x_ecb *ecb;
   1189 	size_t size;
   1190 
   1191 	NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]",
   1192 	    sc->sc_msgpriq, sc->sc_prevphase));
   1193 
   1194 	/*
   1195 	 * XXX - the NCR_ATN flag is not in sync with the actual ATN
   1196 	 *	 condition on the SCSI bus. The 53c9x chip
   1197 	 *	 automatically turns off ATN before sending the
   1198 	 *	 message byte.  (see also the comment below in the
   1199 	 *	 default case when picking out a message to send)
   1200 	 */
   1201 	if (sc->sc_flags & NCR_ATN) {
   1202 		if (sc->sc_prevphase != MESSAGE_OUT_PHASE) {
   1203 		new:
   1204 			NCRCMD(sc, NCRCMD_FLUSH);
   1205 			DELAY(1);
   1206 			sc->sc_msgoutq = 0;
   1207 			sc->sc_omlen = 0;
   1208 		}
   1209 	} else {
   1210 		if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
   1211 			ncr53c9x_sched_msgout(sc->sc_msgoutq);
   1212 			goto new;
   1213 		} else {
   1214 			printf("%s at line %d: unexpected MESSAGE OUT phase\n",
   1215 			    sc->sc_dev.dv_xname, __LINE__);
   1216 		}
   1217 	}
   1218 
   1219 	if (sc->sc_omlen == 0) {
   1220 		/* Pick up highest priority message */
   1221 		sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq;
   1222 		sc->sc_msgoutq |= sc->sc_msgout;
   1223 		sc->sc_msgpriq &= ~sc->sc_msgout;
   1224 		sc->sc_omlen = 1;		/* "Default" message len */
   1225 		switch (sc->sc_msgout) {
   1226 		case SEND_SDTR:
   1227 			ecb = sc->sc_nexus;
   1228 			ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
   1229 			sc->sc_omess[0] = MSG_EXTENDED;
   1230 			sc->sc_omess[1] = 3;
   1231 			sc->sc_omess[2] = MSG_EXT_SDTR;
   1232 			sc->sc_omess[3] = ti->period;
   1233 			sc->sc_omess[4] = ti->offset;
   1234 			sc->sc_omlen = 5;
   1235 			if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) {
   1236 				ti->flags |= T_SYNCMODE;
   1237 				ncr53c9x_setsync(sc, ti);
   1238 			}
   1239 			break;
   1240 		case SEND_IDENTIFY:
   1241 			if (sc->sc_state != NCR_CONNECTED) {
   1242 				printf("%s at line %d: no nexus\n",
   1243 				    sc->sc_dev.dv_xname, __LINE__);
   1244 			}
   1245 			ecb = sc->sc_nexus;
   1246 			sc->sc_omess[0] =
   1247 			    MSG_IDENTIFY(ecb->xs->sc_link->scsipi_scsi.lun, 0);
   1248 			break;
   1249 		case SEND_DEV_RESET:
   1250 			sc->sc_flags |= NCR_ABORTING;
   1251 			sc->sc_omess[0] = MSG_BUS_DEV_RESET;
   1252 			ecb = sc->sc_nexus;
   1253 			ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
   1254 			ti->flags &= ~T_SYNCMODE;
   1255 			ti->flags |= T_NEGOTIATE;
   1256 			break;
   1257 		case SEND_PARITY_ERROR:
   1258 			sc->sc_omess[0] = MSG_PARITY_ERROR;
   1259 			break;
   1260 		case SEND_ABORT:
   1261 			sc->sc_flags |= NCR_ABORTING;
   1262 			sc->sc_omess[0] = MSG_ABORT;
   1263 			break;
   1264 		case SEND_INIT_DET_ERR:
   1265 			sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
   1266 			break;
   1267 		case SEND_REJECT:
   1268 			sc->sc_omess[0] = MSG_MESSAGE_REJECT;
   1269 			break;
   1270 		default:
   1271 			/*
   1272 			 * We normally do not get here, since the chip
   1273 			 * automatically turns off ATN before the last
   1274 			 * byte of a message is sent to the target.
   1275 			 * However, if the target rejects our (multi-byte)
   1276 			 * message early by switching to MSG IN phase
   1277 			 * ATN remains on, so the target may return to
   1278 			 * MSG OUT phase. If there are no scheduled messages
   1279 			 * left we send a NO-OP.
   1280 			 *
   1281 			 * XXX - Note that this leaves no useful purpose for
   1282 			 * the NCR_ATN flag.
   1283 			 */
   1284 			sc->sc_flags &= ~NCR_ATN;
   1285 			sc->sc_omess[0] = MSG_NOOP;
   1286 			break;
   1287 		}
   1288 		sc->sc_omp = sc->sc_omess;
   1289 	}
   1290 
   1291 	/* (re)send the message */
   1292 	size = min(sc->sc_omlen, sc->sc_maxxfer);
   1293 	NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size);
   1294 	/* Program the SCSI counter */
   1295 	NCR_WRITE_REG(sc, NCR_TCL, size);
   1296 	NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
   1297 	if (sc->sc_cfg2 & NCRCFG2_FE) {
   1298 		NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
   1299 	}
   1300 	/* Load the count in and start the message-out transfer */
   1301 	NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
   1302 	NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA);
   1303 	NCRDMA_GO(sc);
   1304 }
   1305 
   1306 /*
   1307  * This is the most critical part of the driver, and has to know
   1308  * how to deal with *all* error conditions and phases from the SCSI
   1309  * bus. If there are no errors and the DMA was active, then call the
   1310  * DMA pseudo-interrupt handler. If this returns 1, then that was it
   1311  * and we can return from here without further processing.
   1312  *
   1313  * Most of this needs verifying.
   1314  */
   1315 int
   1316 ncr53c9x_intr(sc)
   1317 	register struct ncr53c9x_softc *sc;
   1318 {
   1319 	register struct ncr53c9x_ecb *ecb;
   1320 	register struct scsipi_link *sc_link;
   1321 	struct ncr53c9x_tinfo *ti;
   1322 	int loop;
   1323 	size_t size;
   1324 	int nfifo;
   1325 
   1326 	NCR_TRACE(("[ncr53c9x_intr] "));
   1327 
   1328 	/*
   1329 	 * I have made some (maybe seriously flawed) assumptions here,
   1330 	 * but basic testing (uncomment the printf() below), show that
   1331 	 * certainly something happens when this loop is here.
   1332 	 *
   1333 	 * The idea is that many of the SCSI operations take very little
   1334 	 * time, and going away and getting interrupted is too high an
   1335 	 * overhead to pay. For example, selecting, sending a message
   1336 	 * and command and then doing some work can be done in one "pass".
   1337 	 *
   1338 	 * The DELAY is not variable because I do not understand that the
   1339 	 * DELAY loop should be fixed-time regardless of CPU speed, but
   1340 	 * I am *assuming* that the faster SCSI processors get things done
   1341 	 * quicker (sending a command byte etc), and so there is no
   1342 	 * need to be too slow.
   1343 	 *
   1344 	 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1
   1345 	 * at 40Mhz. This needs testing.
   1346 	 */
   1347 	for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) {
   1348 		/* a feeling of deja-vu */
   1349 		if (!NCRDMA_ISINTR(sc))
   1350 			return (loop != 0);
   1351 #if 0
   1352 		if (loop)
   1353 			printf("*");
   1354 #endif
   1355 
   1356 		/* and what do the registers say... */
   1357 		ncr53c9x_readregs(sc);
   1358 
   1359 		sc->sc_intrcnt.ev_count++;
   1360 
   1361 		/*
   1362 		 * At the moment, only a SCSI Bus Reset or Illegal
   1363 		 * Command are classed as errors. A disconnect is a
   1364 		 * valid condition, and we let the code check is the
   1365 		 * "NCR_BUSFREE_OK" flag was set before declaring it
   1366 		 * and error.
   1367 		 *
   1368 		 * Also, the status register tells us about "Gross
   1369 		 * Errors" and "Parity errors". Only the Gross Error
   1370 		 * is really bad, and the parity errors are dealt
   1371 		 * with later
   1372 		 *
   1373 		 * TODO
   1374 		 *	If there are too many parity error, go to slow
   1375 		 *	cable mode ?
   1376 		 */
   1377 
   1378 		/* SCSI Reset */
   1379 		if (sc->sc_espintr & NCRINTR_SBR) {
   1380 			if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
   1381 				NCRCMD(sc, NCRCMD_FLUSH);
   1382 				DELAY(1);
   1383 			}
   1384 			if (sc->sc_state != NCR_SBR) {
   1385 				printf("%s: SCSI bus reset\n",
   1386 					sc->sc_dev.dv_xname);
   1387 				ncr53c9x_init(sc, 0); /* Restart everything */
   1388 				return 1;
   1389 			}
   1390 #if 0
   1391 	/*XXX*/		printf("<expected bus reset: "
   1392 				"[intr %x, stat %x, step %d]>\n",
   1393 				sc->sc_espintr, sc->sc_espstat,
   1394 				sc->sc_espstep);
   1395 #endif
   1396 			if (sc->sc_nexus)
   1397 				panic("%s: nexus in reset state",
   1398 				      sc->sc_dev.dv_xname);
   1399 			goto sched;
   1400 		}
   1401 
   1402 		ecb = sc->sc_nexus;
   1403 
   1404 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL)
   1405 		if (sc->sc_espintr & NCRINTR_ERR ||
   1406 		    sc->sc_espstat & NCRSTAT_GE) {
   1407 
   1408 			if (sc->sc_espstat & NCRSTAT_GE) {
   1409 				/* no target ? */
   1410 				if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
   1411 					NCRCMD(sc, NCRCMD_FLUSH);
   1412 					DELAY(1);
   1413 				}
   1414 				if (sc->sc_state == NCR_CONNECTED ||
   1415 				    sc->sc_state == NCR_SELECTING) {
   1416 					ecb->xs->error = XS_TIMEOUT;
   1417 					ncr53c9x_done(sc, ecb);
   1418 				}
   1419 				return 1;
   1420 			}
   1421 
   1422 			if (sc->sc_espintr & NCRINTR_ILL) {
   1423 				if (sc->sc_flags & NCR_EXPECT_ILLCMD) {
   1424 					/*
   1425 					 * Eat away "Illegal command" interrupt
   1426 					 * on a ESP100 caused by a re-selection
   1427 					 * while we were trying to select
   1428 					 * another target.
   1429 					 */
   1430 #ifdef DEBUG
   1431 					printf("%s: ESP100 work-around activated\n",
   1432 						sc->sc_dev.dv_xname);
   1433 #endif
   1434 					sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
   1435 					continue;
   1436 				}
   1437 				/* illegal command, out of sync ? */
   1438 				printf("%s: illegal command: 0x%x "
   1439 				    "(state %d, phase %x, prevphase %x)\n",
   1440 					sc->sc_dev.dv_xname, sc->sc_lastcmd,
   1441 					sc->sc_state, sc->sc_phase,
   1442 					sc->sc_prevphase);
   1443 				if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
   1444 					NCRCMD(sc, NCRCMD_FLUSH);
   1445 					DELAY(1);
   1446 				}
   1447 				ncr53c9x_init(sc, 1); /* Restart everything */
   1448 				return 1;
   1449 			}
   1450 		}
   1451 		sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
   1452 
   1453 		/*
   1454 		 * Call if DMA is active.
   1455 		 *
   1456 		 * If DMA_INTR returns true, then maybe go 'round the loop
   1457 		 * again in case there is no more DMA queued, but a phase
   1458 		 * change is expected.
   1459 		 */
   1460 		if (NCRDMA_ISACTIVE(sc)) {
   1461 			int r = NCRDMA_INTR(sc);
   1462 			if (r == -1) {
   1463 				printf("%s: DMA error; resetting\n",
   1464 					sc->sc_dev.dv_xname);
   1465 				ncr53c9x_init(sc, 1);
   1466 			}
   1467 			/* If DMA active here, then go back to work... */
   1468 			if (NCRDMA_ISACTIVE(sc))
   1469 				return 1;
   1470 
   1471 			if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
   1472 				/*
   1473 				 * DMA not completed.  If we can not find a
   1474 				 * acceptable explanation, print a diagnostic.
   1475 				 */
   1476 				if (sc->sc_state == NCR_SELECTING)
   1477 					/*
   1478 					 * This can happen if we are reselected
   1479 					 * while using DMA to select a target.
   1480 					 */
   1481 					/*void*/;
   1482 				else if (sc->sc_prevphase == MESSAGE_OUT_PHASE){
   1483 					/*
   1484 					 * Our (multi-byte) message (eg SDTR)
   1485 					 * was interrupted by the target to
   1486 					 * send a MSG REJECT.
   1487 					 * Print diagnostic if current phase
   1488 					 * is not MESSAGE IN.
   1489 					 */
   1490 					if (sc->sc_phase != MESSAGE_IN_PHASE)
   1491 					    printf("%s: !TC on MSG OUT"
   1492 					       " [intr %x, stat %x, step %d]"
   1493 					       " prevphase %x, resid %x\n",
   1494 						sc->sc_dev.dv_xname,
   1495 						sc->sc_espintr,
   1496 						sc->sc_espstat,
   1497 						sc->sc_espstep,
   1498 						sc->sc_prevphase,
   1499 						sc->sc_omlen);
   1500 				} else if (sc->sc_dleft == 0) {
   1501 					/*
   1502 					 * The DMA operation was started for
   1503 					 * a DATA transfer. Print a diagnostic
   1504 					 * if the DMA counter and TC bit
   1505 					 * appear to be out of sync.
   1506 					 */
   1507 					printf("%s: !TC on DATA XFER"
   1508 					       " [intr %x, stat %x, step %d]"
   1509 					       " prevphase %x, resid %x\n",
   1510 						sc->sc_dev.dv_xname,
   1511 						sc->sc_espintr,
   1512 						sc->sc_espstat,
   1513 						sc->sc_espstep,
   1514 						sc->sc_prevphase,
   1515 						ecb?ecb->dleft:-1);
   1516 				}
   1517 			}
   1518 		}
   1519 
   1520 #if 0	/* Unreliable on some NCR revisions? */
   1521 		if ((sc->sc_espstat & NCRSTAT_INT) == 0) {
   1522 			printf("%s: spurious interrupt\n",
   1523 			    sc->sc_dev.dv_xname);
   1524 			return 1;
   1525 		}
   1526 #endif
   1527 
   1528 		/*
   1529 		 * check for less serious errors
   1530 		 */
   1531 		if (sc->sc_espstat & NCRSTAT_PE) {
   1532 			printf("%s: SCSI bus parity error\n",
   1533 				sc->sc_dev.dv_xname);
   1534 			if (sc->sc_prevphase == MESSAGE_IN_PHASE)
   1535 				ncr53c9x_sched_msgout(SEND_PARITY_ERROR);
   1536 			else
   1537 				ncr53c9x_sched_msgout(SEND_INIT_DET_ERR);
   1538 		}
   1539 
   1540 		if (sc->sc_espintr & NCRINTR_DIS) {
   1541 			NCR_MISC(("<DISC [intr %x, stat %x, step %d]>",
   1542 				sc->sc_espintr,sc->sc_espstat,sc->sc_espstep));
   1543 			if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
   1544 				NCRCMD(sc, NCRCMD_FLUSH);
   1545 				DELAY(1);
   1546 			}
   1547 			/*
   1548 			 * This command must (apparently) be issued within
   1549 			 * 250mS of a disconnect. So here you are...
   1550 			 */
   1551 			NCRCMD(sc, NCRCMD_ENSEL);
   1552 
   1553 			switch (sc->sc_state) {
   1554 			case NCR_RESELECTED:
   1555 				goto sched;
   1556 
   1557 			case NCR_SELECTING:
   1558 				ecb->xs->error = XS_SELTIMEOUT;
   1559 				goto finish;
   1560 
   1561 			case NCR_CONNECTED:
   1562 				if ((sc->sc_flags & NCR_SYNCHNEGO)) {
   1563 #ifdef NCR53C9X_DEBUG
   1564 					if (ecb)
   1565 						scsi_print_addr(ecb->xs->sc_link);
   1566 					printf("sync nego not completed!\n");
   1567 #endif
   1568 					ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
   1569 					sc->sc_flags &= ~NCR_SYNCHNEGO;
   1570 					ti->flags &=
   1571 					    ~(T_NEGOTIATE | T_SYNCMODE);
   1572 				}
   1573 
   1574 				/* it may be OK to disconnect */
   1575 				if ((sc->sc_flags & NCR_ABORTING) == 0) {
   1576 					/*
   1577 					 * Section 5.1.1 of the SCSI 2 spec
   1578 					 * suggests issuing a REQUEST SENSE
   1579 					 * following an unexpected disconnect.
   1580 					 * Some devices go into a contingent
   1581 					 * allegiance condition when
   1582 					 * disconnecting, and this is necessary
   1583 					 * to clean up their state.
   1584 					 */
   1585 					printf("%s: unexpected disconnect; ",
   1586 					    sc->sc_dev.dv_xname);
   1587 					if (ecb->flags & ECB_SENSE) {
   1588 						printf("resetting\n");
   1589 						goto reset;
   1590 					}
   1591 					printf("sending REQUEST SENSE\n");
   1592 					untimeout(ncr53c9x_timeout, ecb);
   1593 					ncr53c9x_sense(sc, ecb);
   1594 					goto out;
   1595 				}
   1596 
   1597 				ecb->xs->error = XS_TIMEOUT;
   1598 				goto finish;
   1599 
   1600 			case NCR_DISCONNECT:
   1601 				TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain);
   1602 				sc->sc_nexus = NULL;
   1603 				goto sched;
   1604 
   1605 			case NCR_CMDCOMPLETE:
   1606 				goto finish;
   1607 			}
   1608 		}
   1609 
   1610 		switch (sc->sc_state) {
   1611 
   1612 		case NCR_SBR:
   1613 			printf("%s: waiting for SCSI Bus Reset to happen\n",
   1614 				sc->sc_dev.dv_xname);
   1615 			return 1;
   1616 
   1617 		case NCR_RESELECTED:
   1618 			/*
   1619 			 * we must be continuing a message ?
   1620 			 */
   1621 			if (sc->sc_phase != MESSAGE_IN_PHASE) {
   1622 				printf("%s: target didn't identify\n",
   1623 					sc->sc_dev.dv_xname);
   1624 				ncr53c9x_init(sc, 1);
   1625 				return 1;
   1626 			}
   1627 printf("<<RESELECT CONT'd>>");
   1628 #if XXXX
   1629 			ncr53c9x_msgin(sc);
   1630 			if (sc->sc_state != NCR_CONNECTED) {
   1631 				/* IDENTIFY fail?! */
   1632 				printf("%s: identify failed\n",
   1633 					sc->sc_dev.dv_xname);
   1634 				ncr53c9x_init(sc, 1);
   1635 				return 1;
   1636 			}
   1637 #endif
   1638 			break;
   1639 
   1640 		case NCR_IDLE:
   1641 		case NCR_SELECTING:
   1642 			sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
   1643 			sc->sc_flags = 0;
   1644 			ecb = sc->sc_nexus;
   1645 			if (ecb != NULL && (ecb->flags & ECB_NEXUS)) {
   1646 				scsi_print_addr(ecb->xs->sc_link);
   1647 				printf("ECB_NEXUS while in state %x\n",
   1648 					sc->sc_state);
   1649 			}
   1650 
   1651 			if (sc->sc_espintr & NCRINTR_RESEL) {
   1652 				/*
   1653 				 * If we're trying to select a
   1654 				 * target ourselves, push our command
   1655 				 * back into the ready list.
   1656 				 */
   1657 				if (sc->sc_state == NCR_SELECTING) {
   1658 					NCR_MISC(("backoff selector "));
   1659 					untimeout(ncr53c9x_timeout, ecb);
   1660 					sc_link = ecb->xs->sc_link;
   1661 					ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
   1662 					TAILQ_INSERT_HEAD(&sc->ready_list,
   1663 					    ecb, chain);
   1664 					ecb = sc->sc_nexus = NULL;
   1665 				}
   1666 				sc->sc_state = NCR_RESELECTED;
   1667 				if (sc->sc_phase != MESSAGE_IN_PHASE) {
   1668 					/*
   1669 					 * Things are seriously fucked up.
   1670 					 * Pull the brakes, i.e. reset
   1671 					 */
   1672 					printf("%s: target didn't identify\n",
   1673 						sc->sc_dev.dv_xname);
   1674 					ncr53c9x_init(sc, 1);
   1675 					return 1;
   1676 				}
   1677 				/*
   1678 				 * The C90 only inhibits FIFO writes until
   1679 				 * reselection is complete, instead of
   1680 				 * waiting until the interrupt status register
   1681 				 * has been read. So, if the reselect happens
   1682 				 * while we were entering a command bytes (for
   1683 				 * another target) some of those bytes can
   1684 				 * appear in the FIFO here, after the
   1685 				 * interrupt is taken.
   1686 				 */
   1687 				nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF;
   1688 				if (nfifo < 2 ||
   1689 				    (nfifo > 2 &&
   1690 				     sc->sc_rev != NCR_VARIANT_ESP100)) {
   1691 					printf("%s: RESELECT: "
   1692 					    "%d bytes in FIFO! "
   1693 					    "[intr %x, stat %x, step %d, prevphase %x]\n",
   1694 						sc->sc_dev.dv_xname,
   1695 						nfifo,
   1696 						sc->sc_espintr,
   1697 						sc->sc_espstat,
   1698 						sc->sc_espstep,
   1699 						sc->sc_prevphase);
   1700 					ncr53c9x_init(sc, 1);
   1701 					return 1;
   1702 				}
   1703 				sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO);
   1704 				NCR_MISC(("selid=0x%2x ", sc->sc_selid));
   1705 
   1706 				/* Handle identify message */
   1707 				ncr53c9x_msgin(sc);
   1708 				if (nfifo != 2) {
   1709 					/*
   1710 					 * Note: this should not happen
   1711 					 * with `dmaselect' on.
   1712 					 */
   1713 					sc->sc_flags |= NCR_EXPECT_ILLCMD;
   1714 					NCRCMD(sc, NCRCMD_FLUSH);
   1715 				} else if (ncr53c9x_dmaselect &&
   1716 					   sc->sc_rev == NCR_VARIANT_ESP100) {
   1717 					sc->sc_flags |= NCR_EXPECT_ILLCMD;
   1718 				}
   1719 
   1720 				if (sc->sc_state != NCR_CONNECTED) {
   1721 					/* IDENTIFY fail?! */
   1722 					printf("%s: identify failed\n",
   1723 						sc->sc_dev.dv_xname);
   1724 					ncr53c9x_init(sc, 1);
   1725 					return 1;
   1726 				}
   1727 				continue; /* ie. next phase expected soon */
   1728 			}
   1729 
   1730 #define	NCRINTR_DONE	(NCRINTR_FC|NCRINTR_BS)
   1731 			if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) {
   1732 				ecb = sc->sc_nexus;
   1733 				if (!ecb)
   1734 					panic("esp: not nexus at sc->sc_nexus");
   1735 
   1736 				sc_link = ecb->xs->sc_link;
   1737 				ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
   1738 
   1739 				switch (sc->sc_espstep) {
   1740 				case 0:
   1741 					/*
   1742 					 * The target did not respond with a
   1743 					 * message out phase - probably an old
   1744 					 * device that doesn't recognize ATN.
   1745 					 * Clear ATN and just continue, the
   1746 					 * target should be in the command
   1747 					 * phase.
   1748 					 * XXXX check for command phase?
   1749 					 */
   1750 					NCRCMD(sc, NCRCMD_RSTATN);
   1751 					break;
   1752 				case 1:
   1753 					if ((ti->flags & T_NEGOTIATE) == 0) {
   1754 						printf("%s: step 1 & !NEG\n",
   1755 							sc->sc_dev.dv_xname);
   1756 						goto reset;
   1757 					}
   1758 					if (sc->sc_phase != MESSAGE_OUT_PHASE) {
   1759 						printf("%s: !MSGOUT\n",
   1760 							sc->sc_dev.dv_xname);
   1761 						goto reset;
   1762 					}
   1763 					/* Start negotiating */
   1764 					ti->period = sc->sc_minsync;
   1765 					ti->offset = 15;
   1766 					sc->sc_flags |= NCR_SYNCHNEGO;
   1767 					ncr53c9x_sched_msgout(SEND_SDTR);
   1768 					break;
   1769 				case 3:
   1770 					/*
   1771 					 * Grr, this is supposed to mean
   1772 					 * "target left command phase
   1773 					 *  prematurely". It seems to happen
   1774 					 * regularly when sync mode is on.
   1775 					 * Look at FIFO to see if command
   1776 					 * went out.
   1777 					 * (Timing problems?)
   1778 					 */
   1779 					if (ncr53c9x_dmaselect) {
   1780 					    if (sc->sc_cmdlen == 0)
   1781 						/* Hope for the best.. */
   1782 						break;
   1783 					} else if ((NCR_READ_REG(sc, NCR_FFLAG)
   1784 					    & NCRFIFO_FF) == 0) {
   1785 						/* Hope for the best.. */
   1786 						break;
   1787 					}
   1788 					printf("(%s:%d:%d): selection failed;"
   1789 						" %d left in FIFO "
   1790 						"[intr %x, stat %x, step %d]\n",
   1791 						sc->sc_dev.dv_xname,
   1792 						sc_link->scsipi_scsi.target,
   1793 						sc_link->scsipi_scsi.lun,
   1794 						NCR_READ_REG(sc, NCR_FFLAG)
   1795 						 & NCRFIFO_FF,
   1796 						sc->sc_espintr, sc->sc_espstat,
   1797 						sc->sc_espstep);
   1798 					NCRCMD(sc, NCRCMD_FLUSH);
   1799 					ncr53c9x_sched_msgout(SEND_ABORT);
   1800 					return 1;
   1801 				case 2:
   1802 					/* Select stuck at Command Phase */
   1803 					NCRCMD(sc, NCRCMD_FLUSH);
   1804 				case 4:
   1805 					if (ncr53c9x_dmaselect &&
   1806 					    sc->sc_cmdlen != 0)
   1807 						printf("(%s:%d:%d): select; "
   1808 						       "%d left in DMA buffer "
   1809 						"[intr %x, stat %x, step %d]\n",
   1810 							sc->sc_dev.dv_xname,
   1811 							sc_link->scsipi_scsi.target,
   1812 							sc_link->scsipi_scsi.lun,
   1813 							sc->sc_cmdlen,
   1814 							sc->sc_espintr,
   1815 							sc->sc_espstat,
   1816 							sc->sc_espstep);
   1817 					/* So far, everything went fine */
   1818 					break;
   1819 				}
   1820 #if 0
   1821 				if (ecb->xs->flags & SCSI_RESET)
   1822 					ncr53c9x_sched_msgout(SEND_DEV_RESET);
   1823 				else if (ti->flags & T_NEGOTIATE)
   1824 					ncr53c9x_sched_msgout(
   1825 					    SEND_IDENTIFY | SEND_SDTR);
   1826 				else
   1827 					ncr53c9x_sched_msgout(SEND_IDENTIFY);
   1828 #endif
   1829 
   1830 				ecb->flags |= ECB_NEXUS;
   1831 				ti->lubusy |= (1 << sc_link->scsipi_scsi.lun);
   1832 
   1833 				sc->sc_prevphase = INVALID_PHASE; /* ?? */
   1834 				/* Do an implicit RESTORE POINTERS. */
   1835 				sc->sc_dp = ecb->daddr;
   1836 				sc->sc_dleft = ecb->dleft;
   1837 				sc->sc_state = NCR_CONNECTED;
   1838 				break;
   1839 			} else {
   1840 				printf("%s: unexpected status after select"
   1841 					": [intr %x, stat %x, step %x]\n",
   1842 					sc->sc_dev.dv_xname,
   1843 					sc->sc_espintr, sc->sc_espstat,
   1844 					sc->sc_espstep);
   1845 				NCRCMD(sc, NCRCMD_FLUSH);
   1846 				DELAY(1);
   1847 				goto reset;
   1848 			}
   1849 			if (sc->sc_state == NCR_IDLE) {
   1850 				printf("%s: stray interrupt\n",
   1851 				    sc->sc_dev.dv_xname);
   1852 					return 0;
   1853 			}
   1854 			break;
   1855 
   1856 		case NCR_CONNECTED:
   1857 			if (sc->sc_flags & NCR_ICCS) {
   1858 				u_char msg;
   1859 
   1860 				sc->sc_flags &= ~NCR_ICCS;
   1861 
   1862 				if (!(sc->sc_espintr & NCRINTR_DONE)) {
   1863 					printf("%s: ICCS: "
   1864 					      ": [intr %x, stat %x, step %x]\n",
   1865 						sc->sc_dev.dv_xname,
   1866 						sc->sc_espintr, sc->sc_espstat,
   1867 						sc->sc_espstep);
   1868 				}
   1869 				if ((NCR_READ_REG(sc, NCR_FFLAG)
   1870 				    & NCRFIFO_FF) != 2) {
   1871 					int i = (NCR_READ_REG(sc, NCR_FFLAG)
   1872 					    & NCRFIFO_FF) - 2;
   1873 					while (i--)
   1874 						(void) NCR_READ_REG(sc,
   1875 								    NCR_FIFO);
   1876 				}
   1877 				ecb->stat = NCR_READ_REG(sc, NCR_FIFO);
   1878 				msg = NCR_READ_REG(sc, NCR_FIFO);
   1879 				NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg));
   1880 				if (msg == MSG_CMDCOMPLETE) {
   1881 					ecb->dleft =
   1882 					  (ecb->flags & ECB_TENTATIVE_DONE)
   1883 						? 0
   1884 						: sc->sc_dleft;
   1885 					if ((ecb->flags & ECB_SENSE) == 0)
   1886 						ecb->xs->resid = ecb->dleft;
   1887 					sc->sc_state = NCR_CMDCOMPLETE;
   1888 				} else
   1889 					printf("%s: STATUS_PHASE: msg %d\n",
   1890 						sc->sc_dev.dv_xname, msg);
   1891 				NCRCMD(sc, NCRCMD_MSGOK);
   1892 				continue; /* ie. wait for disconnect */
   1893 			}
   1894 			break;
   1895 		default:
   1896 			panic("%s: invalid state: %d",
   1897 			      sc->sc_dev.dv_xname,
   1898 			      sc->sc_state);
   1899 		}
   1900 
   1901 		/*
   1902 		 * Driver is now in state NCR_CONNECTED, i.e. we
   1903 		 * have a current command working the SCSI bus.
   1904 		 */
   1905 		if (sc->sc_state != NCR_CONNECTED || ecb == NULL) {
   1906 			panic("esp no nexus");
   1907 		}
   1908 
   1909 		switch (sc->sc_phase) {
   1910 		case MESSAGE_OUT_PHASE:
   1911 			NCR_PHASE(("MESSAGE_OUT_PHASE "));
   1912 			ncr53c9x_msgout(sc);
   1913 			sc->sc_prevphase = MESSAGE_OUT_PHASE;
   1914 			break;
   1915 		case MESSAGE_IN_PHASE:
   1916 			NCR_PHASE(("MESSAGE_IN_PHASE "));
   1917 			if (sc->sc_espintr & NCRINTR_BS) {
   1918 				NCRCMD(sc, NCRCMD_FLUSH);
   1919 				sc->sc_flags |= NCR_WAITI;
   1920 				NCRCMD(sc, NCRCMD_TRANS);
   1921 			} else if (sc->sc_espintr & NCRINTR_FC) {
   1922 				if ((sc->sc_flags & NCR_WAITI) == 0) {
   1923 					printf("%s: MSGIN: unexpected FC bit: "
   1924 						"[intr %x, stat %x, step %x]\n",
   1925 					sc->sc_dev.dv_xname,
   1926 					sc->sc_espintr, sc->sc_espstat,
   1927 					sc->sc_espstep);
   1928 				}
   1929 				sc->sc_flags &= ~NCR_WAITI;
   1930 				ncr53c9x_msgin(sc);
   1931 			} else {
   1932 				printf("%s: MSGIN: weird bits: "
   1933 					"[intr %x, stat %x, step %x]\n",
   1934 					sc->sc_dev.dv_xname,
   1935 					sc->sc_espintr, sc->sc_espstat,
   1936 					sc->sc_espstep);
   1937 			}
   1938 			sc->sc_prevphase = MESSAGE_IN_PHASE;
   1939 			break;
   1940 		case COMMAND_PHASE:
   1941 			/*
   1942 			 * Send the command block. Normally we don't see this
   1943 			 * phase because the SEL_ATN command takes care of
   1944 			 * all this. However, we end up here if either the
   1945 			 * target or we wanted to exchange some more messages
   1946 			 * first (e.g. to start negotiations).
   1947 			 */
   1948 
   1949 			NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ",
   1950 				ecb->cmd.cmd.opcode, ecb->clen));
   1951 			if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
   1952 				NCRCMD(sc, NCRCMD_FLUSH);
   1953 				DELAY(1);
   1954 			}
   1955 			if (ncr53c9x_dmaselect) {
   1956 				size_t size;
   1957 				/* setup DMA transfer for command */
   1958 				size = ecb->clen;
   1959 				sc->sc_cmdlen = size;
   1960 				sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd;
   1961 				NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen,
   1962 					     0, &size);
   1963 				/* Program the SCSI counter */
   1964 				NCR_WRITE_REG(sc, NCR_TCL, size);
   1965 				NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
   1966 				if (sc->sc_cfg2 & NCRCFG2_FE) {
   1967 					NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
   1968 				}
   1969 
   1970 				/* load the count in */
   1971 				NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
   1972 
   1973 				/* start the command transfer */
   1974 				NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
   1975 				NCRDMA_GO(sc);
   1976 			} else {
   1977 				u_char *cmd = (u_char *)&ecb->cmd.cmd;
   1978 				int i;
   1979 				/* Now the command into the FIFO */
   1980 				for (i = 0; i < ecb->clen; i++)
   1981 					NCR_WRITE_REG(sc, NCR_FIFO, *cmd++);
   1982 				NCRCMD(sc, NCRCMD_TRANS);
   1983 			}
   1984 			sc->sc_prevphase = COMMAND_PHASE;
   1985 			break;
   1986 		case DATA_OUT_PHASE:
   1987 			NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft));
   1988 			NCRCMD(sc, NCRCMD_FLUSH);
   1989 			size = min(sc->sc_dleft, sc->sc_maxxfer);
   1990 			NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft,
   1991 				  0, &size);
   1992 			sc->sc_prevphase = DATA_OUT_PHASE;
   1993 			goto setup_xfer;
   1994 		case DATA_IN_PHASE:
   1995 			NCR_PHASE(("DATA_IN_PHASE "));
   1996 			if (sc->sc_rev == NCR_VARIANT_ESP100)
   1997 				NCRCMD(sc, NCRCMD_FLUSH);
   1998 			size = min(sc->sc_dleft, sc->sc_maxxfer);
   1999 			NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft,
   2000 				  1, &size);
   2001 			sc->sc_prevphase = DATA_IN_PHASE;
   2002 		setup_xfer:
   2003 			/* Target returned to data phase: wipe "done" memory */
   2004 			ecb->flags &= ~ECB_TENTATIVE_DONE;
   2005 
   2006 			/* Program the SCSI counter */
   2007 			NCR_WRITE_REG(sc, NCR_TCL, size);
   2008 			NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
   2009 			if (sc->sc_cfg2 & NCRCFG2_FE) {
   2010 				NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
   2011 			}
   2012 			/* load the count in */
   2013 			NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
   2014 
   2015 			/*
   2016 			 * Note that if `size' is 0, we've already transceived
   2017 			 * all the bytes we want but we're still in DATA PHASE.
   2018 			 * Apparently, the device needs padding. Also, a
   2019 			 * transfer size of 0 means "maximum" to the chip
   2020 			 * DMA logic.
   2021 			 */
   2022 			NCRCMD(sc,
   2023 			       (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA);
   2024 			NCRDMA_GO(sc);
   2025 			return 1;
   2026 		case STATUS_PHASE:
   2027 			NCR_PHASE(("STATUS_PHASE "));
   2028 			sc->sc_flags |= NCR_ICCS;
   2029 			NCRCMD(sc, NCRCMD_ICCS);
   2030 			sc->sc_prevphase = STATUS_PHASE;
   2031 			break;
   2032 		case INVALID_PHASE:
   2033 			break;
   2034 		default:
   2035 			printf("%s: unexpected bus phase; resetting\n",
   2036 			    sc->sc_dev.dv_xname);
   2037 			goto reset;
   2038 		}
   2039 	}
   2040 	panic("esp: should not get here..");
   2041 
   2042 reset:
   2043 	ncr53c9x_init(sc, 1);
   2044 	return 1;
   2045 
   2046 finish:
   2047 	ncr53c9x_done(sc, ecb);
   2048 	goto out;
   2049 
   2050 sched:
   2051 	sc->sc_state = NCR_IDLE;
   2052 	ncr53c9x_sched(sc);
   2053 	goto out;
   2054 
   2055 out:
   2056 	return 1;
   2057 }
   2058 
   2059 void
   2060 ncr53c9x_abort(sc, ecb)
   2061 	struct ncr53c9x_softc *sc;
   2062 	struct ncr53c9x_ecb *ecb;
   2063 {
   2064 
   2065 	/* 2 secs for the abort */
   2066 	ecb->timeout = NCR_ABORT_TIMEOUT;
   2067 	ecb->flags |= ECB_ABORT;
   2068 
   2069 	if (ecb == sc->sc_nexus) {
   2070 		/*
   2071 		 * If we're still selecting, the message will be scheduled
   2072 		 * after selection is complete.
   2073 		 */
   2074 		if (sc->sc_state == NCR_CONNECTED)
   2075 			ncr53c9x_sched_msgout(SEND_ABORT);
   2076 
   2077 		/*
   2078 		 * Reschedule timeout. First, cancel a queued timeout (if any)
   2079 		 * in case someone decides to call ncr53c9x_abort() from
   2080 		 * elsewhere.
   2081 		 */
   2082 		untimeout(ncr53c9x_timeout, ecb);
   2083 		timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000);
   2084 	} else {
   2085 		/* The command should be on the nexus list */
   2086 		if ((ecb->flags & ECB_NEXUS) == 0) {
   2087 			scsi_print_addr(ecb->xs->sc_link);
   2088 			printf("ncr53c9x_abort: not NEXUS\n");
   2089 			ncr53c9x_init(sc, 1);
   2090 		}
   2091 		/*
   2092 		 * Just leave the command on the nexus list.
   2093 		 * XXX - what choice do we have but to reset the SCSI
   2094 		 *	 eventually?
   2095 		 */
   2096 		if (sc->sc_state == NCR_IDLE)
   2097 			ncr53c9x_sched(sc);
   2098 	}
   2099 }
   2100 
   2101 void
   2102 ncr53c9x_timeout(arg)
   2103 	void *arg;
   2104 {
   2105 	struct ncr53c9x_ecb *ecb = arg;
   2106 	struct scsipi_xfer *xs = ecb->xs;
   2107 	struct scsipi_link *sc_link = xs->sc_link;
   2108 	struct ncr53c9x_softc *sc = sc_link->adapter_softc;
   2109 	struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
   2110 	int s;
   2111 
   2112 	scsi_print_addr(sc_link);
   2113 	printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], "
   2114 	       "<state %d, nexus %p, phase(l %x, c %x, p %x), resid %lx, "
   2115 	       "msg(q %x,o %x) %s>",
   2116 		sc->sc_dev.dv_xname,
   2117 		ecb, ecb->flags, ecb->dleft, ecb->stat,
   2118 		sc->sc_state, sc->sc_nexus,
   2119 		NCR_READ_REG(sc, NCR_STAT),
   2120 		sc->sc_phase, sc->sc_prevphase,
   2121 		(long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout,
   2122 		NCRDMA_ISACTIVE(sc) ? "DMA active" : "");
   2123 #if NCR53C9X_DEBUG > 1
   2124 	printf("TRACE: %s.", ecb->trace);
   2125 #endif
   2126 
   2127 	s = splbio();
   2128 
   2129 	if (ecb->flags & ECB_ABORT) {
   2130 		/* abort timed out */
   2131 		printf(" AGAIN\n");
   2132 
   2133 		ncr53c9x_init(sc, 1);
   2134 	} else {
   2135 		/* abort the operation that has timed out */
   2136 		printf("\n");
   2137 		xs->error = XS_TIMEOUT;
   2138 		ncr53c9x_abort(sc, ecb);
   2139 
   2140 		/* Disable sync mode if stuck in a data phase */
   2141 		if (ecb == sc->sc_nexus &&
   2142 		    (ti->flags & T_SYNCMODE) != 0 &&
   2143 		    (sc->sc_phase & (MSGI|CDI)) == 0) {
   2144 			scsi_print_addr(sc_link);
   2145 			printf("sync negotiation disabled\n");
   2146 			sc->sc_cfflags |= (1<<(sc_link->scsipi_scsi.target+8));
   2147 		}
   2148 	}
   2149 
   2150 	splx(s);
   2151 }
   2152