ncr53c9x.c revision 1.36
1 /* $NetBSD: ncr53c9x.c,v 1.36 1999/09/30 23:04:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1994 Peter Galbavy 41 * Copyright (c) 1995 Paul Kranenburg 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/malloc.h> 88 #include <sys/proc.h> 89 #include <sys/user.h> 90 #include <sys/queue.h> 91 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsiconf.h> 95 #include <dev/scsipi/scsi_message.h> 96 97 #include <machine/cpu.h> 98 99 #include <dev/ic/ncr53c9xreg.h> 100 #include <dev/ic/ncr53c9xvar.h> 101 102 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 103 104 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 105 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 106 struct ncr53c9x_ecb *)); 107 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 108 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 109 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 110 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 111 struct scsipi_xfer *, int)); 112 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 113 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 114 struct ncr53c9x_ecb *)); 115 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 116 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 117 /*static*/ void ncr53c9x_timeout __P((void *arg)); 118 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 119 struct ncr53c9x_ecb *)); 120 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 121 struct ncr53c9x_ecb *)); 122 123 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 124 struct ncr53c9x_ecb *)); 125 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 126 struct ncr53c9x_ecb *, int)); 127 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 128 129 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 130 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 131 struct ncr53c9x_tinfo *)); 132 133 /* 134 * Names for the NCR53c9x variants, correspnding to the variant tags 135 * in ncr53c9xvar.h. 136 */ 137 const char *ncr53c9x_variant_names[] = { 138 "ESP100", 139 "ESP100A", 140 "ESP200", 141 "NCR53C94", 142 "NCR53C96", 143 "ESP406", 144 "FAS408", 145 "FAS216", 146 "AM53C974", 147 }; 148 149 /* 150 * Attach this instance, and then all the sub-devices 151 */ 152 void 153 ncr53c9x_attach(sc, dev) 154 struct ncr53c9x_softc *sc; 155 struct scsipi_device *dev; 156 { 157 158 /* 159 * Allocate SCSI message buffers. 160 * Front-ends can override allocation to avoid alignment 161 * handling in the DMA engines. Note that that ncr53c9x_msgout() 162 * can request a 1 byte DMA transfer. 163 */ 164 if (sc->sc_omess == NULL) 165 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 166 167 if (sc->sc_imess == NULL) 168 sc->sc_imess = malloc(NCR_MAX_MSG_LEN+1, M_DEVBUF, M_NOWAIT); 169 170 if (sc->sc_omess == NULL || sc->sc_imess == NULL) { 171 printf("out of memory\n"); 172 return; 173 } 174 175 /* 176 * Note, the front-end has set us up to print the chip variation. 177 */ 178 if (sc->sc_rev >= NCR_VARIANT_MAX) { 179 printf("\n%s: unknown variant %d, devices not attached\n", 180 sc->sc_dev.dv_xname, sc->sc_rev); 181 return; 182 } 183 184 printf(": %s, %dMHz, SCSI ID %d\n", 185 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 186 187 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 188 189 /* The value *must not* be == 1. Make it 2 */ 190 if (sc->sc_ccf == 1) 191 sc->sc_ccf = 2; 192 193 /* 194 * The recommended timeout is 250ms. This register is loaded 195 * with a value calculated as follows, from the docs: 196 * 197 * (timout period) x (CLK frequency) 198 * reg = ------------------------------------- 199 * 8192 x (Clock Conversion Factor) 200 * 201 * Since CCF has a linear relation to CLK, this generally computes 202 * to the constant of 153. 203 */ 204 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 205 206 /* CCF register only has 3 bits; 0 is actually 8 */ 207 sc->sc_ccf &= 7; 208 209 /* Reset state & bus */ 210 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 211 sc->sc_state = 0; 212 ncr53c9x_init(sc, 1); 213 214 /* 215 * fill in the prototype scsipi_link. 216 */ 217 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 218 sc->sc_link.adapter_softc = sc; 219 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 220 sc->sc_link.adapter = &sc->sc_adapter; 221 sc->sc_link.device = dev; 222 sc->sc_link.openings = 2; 223 sc->sc_link.scsipi_scsi.max_target = 7; 224 sc->sc_link.scsipi_scsi.max_lun = 7; 225 sc->sc_link.type = BUS_SCSI; 226 227 /* 228 * Now try to attach all the sub-devices 229 */ 230 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 231 232 /* 233 * Enable interupts from the SCSI core 234 */ 235 if ((sc->sc_rev == NCR_VARIANT_ESP406) || 236 (sc->sc_rev == NCR_VARIANT_FAS408)) { 237 NCR_PIOREGS(sc); 238 NCR_WRITE_REG(sc, NCR_CFG5, NCRCFG5_SINT | 239 NCR_READ_REG(sc, NCR_CFG5)); 240 NCR_SCSIREGS(sc); 241 } 242 243 } 244 245 /* 246 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus, 247 * only this controller, but kills any on-going commands, and also stops 248 * and resets the DMA. 249 * 250 * After reset, registers are loaded with the defaults from the attach 251 * routine above. 252 */ 253 void 254 ncr53c9x_reset(sc) 255 struct ncr53c9x_softc *sc; 256 { 257 258 /* reset DMA first */ 259 NCRDMA_RESET(sc); 260 261 /* reset SCSI chip */ 262 NCRCMD(sc, NCRCMD_RSTCHIP); 263 NCRCMD(sc, NCRCMD_NOP); 264 DELAY(500); 265 266 /* do these backwards, and fall through */ 267 switch (sc->sc_rev) { 268 case NCR_VARIANT_ESP406: 269 case NCR_VARIANT_FAS408: 270 NCR_SCSIREGS(sc); 271 case NCR_VARIANT_AM53C974: 272 case NCR_VARIANT_FAS216: 273 case NCR_VARIANT_NCR53C94: 274 case NCR_VARIANT_NCR53C96: 275 case NCR_VARIANT_ESP200: 276 sc->sc_features |= NCR_F_HASCFG3; 277 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 278 case NCR_VARIANT_ESP100A: 279 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 280 case NCR_VARIANT_ESP100: 281 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 282 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 283 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 284 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 285 break; 286 default: 287 printf("%s: unknown revision code, assuming ESP100\n", 288 sc->sc_dev.dv_xname); 289 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 290 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 291 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 292 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 293 } 294 295 if (sc->sc_rev == NCR_VARIANT_AM53C974) 296 NCR_WRITE_REG(sc, NCR_AMDCFG4, 297 NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE); 298 } 299 300 /* 301 * Reset the SCSI bus, but not the chip 302 */ 303 void 304 ncr53c9x_scsi_reset(sc) 305 struct ncr53c9x_softc *sc; 306 { 307 308 (*sc->sc_glue->gl_dma_stop)(sc); 309 310 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 311 NCRCMD(sc, NCRCMD_RSTSCSI); 312 } 313 314 /* 315 * Initialize ncr53c9x state machine 316 */ 317 void 318 ncr53c9x_init(sc, doreset) 319 struct ncr53c9x_softc *sc; 320 int doreset; 321 { 322 struct ncr53c9x_ecb *ecb; 323 int r; 324 325 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 326 327 if (sc->sc_state == 0) { 328 /* First time through; initialize. */ 329 TAILQ_INIT(&sc->ready_list); 330 TAILQ_INIT(&sc->nexus_list); 331 TAILQ_INIT(&sc->free_list); 332 sc->sc_nexus = NULL; 333 ecb = sc->sc_ecb; 334 bzero(ecb, sizeof(sc->sc_ecb)); 335 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 336 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 337 ecb++; 338 } 339 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 340 } else { 341 /* Cancel any active commands. */ 342 sc->sc_state = NCR_CLEANING; 343 if ((ecb = sc->sc_nexus) != NULL) { 344 ecb->xs->error = XS_TIMEOUT; 345 ncr53c9x_done(sc, ecb); 346 } 347 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 348 ecb->xs->error = XS_TIMEOUT; 349 ncr53c9x_done(sc, ecb); 350 } 351 } 352 353 /* 354 * reset the chip to a known state 355 */ 356 ncr53c9x_reset(sc); 357 358 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 359 for (r = 0; r < 8; r++) { 360 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 361 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 362 363 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8)))) 364 ? T_NEGOTIATE : 0) | 365 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) | 366 T_NEED_TO_RESET; 367 ti->period = sc->sc_minsync; 368 ti->offset = 0; 369 } 370 371 if (doreset) { 372 sc->sc_state = NCR_SBR; 373 NCRCMD(sc, NCRCMD_RSTSCSI); 374 } else { 375 sc->sc_state = NCR_IDLE; 376 ncr53c9x_sched(sc); 377 } 378 } 379 380 /* 381 * Read the NCR registers, and save their contents for later use. 382 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 383 * NCR_INTR - so make sure it is the last read. 384 * 385 * I think that (from reading the docs) most bits in these registers 386 * only make sense when he DMA CSR has an interrupt showing. Call only 387 * if an interrupt is pending. 388 */ 389 __inline__ void 390 ncr53c9x_readregs(sc) 391 struct ncr53c9x_softc *sc; 392 { 393 394 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 395 /* Only the stepo bits are of interest */ 396 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 397 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 398 399 if (sc->sc_glue->gl_clear_latched_intr != NULL) 400 (*sc->sc_glue->gl_clear_latched_intr)(sc); 401 402 /* 403 * Determine the SCSI bus phase, return either a real SCSI bus phase 404 * or some pseudo phase we use to detect certain exceptions. 405 */ 406 407 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 408 ? /* Disconnected */ BUSFREE_PHASE 409 : sc->sc_espstat & NCRSTAT_PHASE; 410 411 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 412 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 413 } 414 415 /* 416 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 417 */ 418 static inline int 419 ncr53c9x_stp2cpb(sc, period) 420 struct ncr53c9x_softc *sc; 421 int period; 422 { 423 int v; 424 v = (sc->sc_freq * period) / 250; 425 if (ncr53c9x_cpb2stp(sc, v) < period) 426 /* Correct round-down error */ 427 v++; 428 return (v); 429 } 430 431 static inline void 432 ncr53c9x_setsync(sc, ti) 433 struct ncr53c9x_softc *sc; 434 struct ncr53c9x_tinfo *ti; 435 { 436 u_char syncoff, synctp, cfg3 = sc->sc_cfg3; 437 438 if (ti->flags & T_SYNCMODE) { 439 syncoff = ti->offset; 440 synctp = ncr53c9x_stp2cpb(sc, ti->period); 441 if (sc->sc_features & NCR_F_FASTSCSI) { 442 /* 443 * If the period is 200ns or less (ti->period <= 50), 444 * put the chip in Fast SCSI mode. 445 */ 446 if (ti->period <= 50) 447 /* 448 * There are (at least) 4 variations of the 449 * configuration 3 register. The drive attach 450 * routine sets the appropriate bit to put the 451 * chip into Fast SCSI mode so that it doesn't 452 * have to be figured out here each time. 453 */ 454 cfg3 |= sc->sc_cfg3_fscsi; 455 } 456 457 /* 458 * Am53c974 requires different SYNCTP values when the 459 * FSCSI bit is off. 460 */ 461 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 462 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 463 synctp--; 464 } else { 465 syncoff = 0; 466 synctp = 0; 467 } 468 469 if (sc->sc_features & NCR_F_HASCFG3) 470 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 471 472 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 473 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 474 } 475 476 int ncr53c9x_dmaselect = 0; 477 /* 478 * Send a command to a target, set the driver state to NCR_SELECTING 479 * and let the caller take care of the rest. 480 * 481 * Keeping this as a function allows me to say that this may be done 482 * by DMA instead of programmed I/O soon. 483 */ 484 void 485 ncr53c9x_select(sc, ecb) 486 struct ncr53c9x_softc *sc; 487 struct ncr53c9x_ecb *ecb; 488 { 489 struct scsipi_link *sc_link = ecb->xs->sc_link; 490 int target = sc_link->scsipi_scsi.target; 491 int lun = sc_link->scsipi_scsi.lun; 492 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 493 int tiflags = ti->flags; 494 u_char *cmd; 495 int clen; 496 497 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 498 target, lun, ecb->cmd.cmd.opcode)); 499 500 sc->sc_state = NCR_SELECTING; 501 502 /* 503 * Schedule the timeout now, the first time we will go away 504 * expecting to come back due to an interrupt, because it is 505 * always possible that the interrupt may never happen. 506 */ 507 if ((ecb->xs->xs_control & XS_CTL_POLL) == 0) 508 timeout(ncr53c9x_timeout, ecb, 509 (ecb->timeout * hz) / 1000); 510 511 /* 512 * The docs say the target register is never reset, and I 513 * can't think of a better place to set it 514 */ 515 NCR_WRITE_REG(sc, NCR_SELID, target); 516 ncr53c9x_setsync(sc, ti); 517 518 if (ncr53c9x_dmaselect && (tiflags & T_NEGOTIATE) == 0) { 519 size_t dmasize; 520 521 ecb->cmd.id = 522 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1); 523 524 525 /* setup DMA transfer for command */ 526 dmasize = clen = ecb->clen + 1; 527 sc->sc_cmdlen = clen; 528 sc->sc_cmdp = (caddr_t)&ecb->cmd; 529 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 530 531 /* Program the SCSI counter */ 532 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 533 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 534 if (sc->sc_cfg2 & NCRCFG2_FE) { 535 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 536 } 537 538 /* load the count in */ 539 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 540 541 /* And get the targets attention */ 542 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 543 NCRDMA_GO(sc); 544 return; 545 } 546 547 /* 548 * Who am I. This is where we tell the target that we are 549 * happy for it to disconnect etc. 550 */ 551 NCR_WRITE_REG(sc, NCR_FIFO, 552 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1)); 553 554 if (ti->flags & T_NEGOTIATE) { 555 /* Arbitrate, select and stop after IDENTIFY message */ 556 NCRCMD(sc, NCRCMD_SELATNS); 557 return; 558 } 559 560 /* Now the command into the FIFO */ 561 cmd = (u_char *)&ecb->cmd.cmd; 562 clen = ecb->clen; 563 while (clen--) 564 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 565 566 /* And get the targets attention */ 567 NCRCMD(sc, NCRCMD_SELATN); 568 } 569 570 void 571 ncr53c9x_free_ecb(sc, ecb, flags) 572 struct ncr53c9x_softc *sc; 573 struct ncr53c9x_ecb *ecb; 574 int flags; 575 { 576 int s; 577 578 s = splbio(); 579 580 ecb->flags = 0; 581 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 582 583 /* 584 * If there were none, wake anybody waiting for one to come free, 585 * starting with queued entries. 586 */ 587 if (ecb->chain.tqe_next == 0) 588 wakeup(&sc->free_list); 589 590 splx(s); 591 } 592 593 struct ncr53c9x_ecb * 594 ncr53c9x_get_ecb(sc, flags) 595 struct ncr53c9x_softc *sc; 596 int flags; 597 { 598 struct ncr53c9x_ecb *ecb; 599 int s; 600 601 s = splbio(); 602 603 while ((ecb = sc->free_list.tqh_first) == NULL && 604 (flags & XS_CTL_NOSLEEP) == 0) 605 tsleep(&sc->free_list, PRIBIO, "especb", 0); 606 if (ecb) { 607 TAILQ_REMOVE(&sc->free_list, ecb, chain); 608 ecb->flags |= ECB_ALLOC; 609 } 610 611 splx(s); 612 return (ecb); 613 } 614 615 /* 616 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 617 */ 618 619 /* 620 * Start a SCSI-command 621 * This function is called by the higher level SCSI-driver to queue/run 622 * SCSI-commands. 623 */ 624 int 625 ncr53c9x_scsi_cmd(xs) 626 struct scsipi_xfer *xs; 627 { 628 struct scsipi_link *sc_link = xs->sc_link; 629 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 630 struct ncr53c9x_ecb *ecb; 631 int s, flags; 632 633 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 634 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 635 sc_link->scsipi_scsi.target)); 636 637 flags = xs->xs_control; 638 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) 639 return (TRY_AGAIN_LATER); 640 641 /* Initialize ecb */ 642 ecb->xs = xs; 643 ecb->timeout = xs->timeout; 644 645 if (flags & XS_CTL_RESET) { 646 ecb->flags |= ECB_RESET; 647 ecb->clen = 0; 648 ecb->dleft = 0; 649 } else { 650 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 651 ecb->clen = xs->cmdlen; 652 ecb->daddr = xs->data; 653 ecb->dleft = xs->datalen; 654 } 655 ecb->stat = 0; 656 657 s = splbio(); 658 659 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 660 if (sc->sc_state == NCR_IDLE) 661 ncr53c9x_sched(sc); 662 663 splx(s); 664 665 if ((flags & XS_CTL_POLL) == 0) 666 return (SUCCESSFULLY_QUEUED); 667 668 /* Not allowed to use interrupts, use polling instead */ 669 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 670 ncr53c9x_timeout(ecb); 671 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 672 ncr53c9x_timeout(ecb); 673 } 674 return (COMPLETE); 675 } 676 677 /* 678 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 679 */ 680 int 681 ncr53c9x_poll(sc, xs, count) 682 struct ncr53c9x_softc *sc; 683 struct scsipi_xfer *xs; 684 int count; 685 { 686 687 NCR_TRACE(("[ncr53c9x_poll] ")); 688 while (count) { 689 if (NCRDMA_ISINTR(sc)) { 690 ncr53c9x_intr(sc); 691 } 692 #if alternatively 693 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 694 ncr53c9x_intr(sc); 695 #endif 696 if ((xs->xs_status & XS_STS_DONE) != 0) 697 return (0); 698 if (sc->sc_state == NCR_IDLE) { 699 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 700 ncr53c9x_sched(sc); 701 } 702 DELAY(1000); 703 count--; 704 } 705 return (1); 706 } 707 708 709 /* 710 * LOW LEVEL SCSI UTILITIES 711 */ 712 713 /* 714 * Schedule a scsi operation. This has now been pulled out of the interrupt 715 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 716 * This may save us an unecessary interrupt just to get things going. 717 * Should only be called when state == NCR_IDLE and at bio pl. 718 */ 719 void 720 ncr53c9x_sched(sc) 721 struct ncr53c9x_softc *sc; 722 { 723 struct ncr53c9x_ecb *ecb; 724 struct scsipi_link *sc_link; 725 struct ncr53c9x_tinfo *ti; 726 727 NCR_TRACE(("[ncr53c9x_sched] ")); 728 if (sc->sc_state != NCR_IDLE) 729 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 730 731 /* 732 * Find first ecb in ready queue that is for a target/lunit 733 * combinations that is not busy. 734 */ 735 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 736 sc_link = ecb->xs->sc_link; 737 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 738 if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) { 739 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 740 sc->sc_nexus = ecb; 741 ncr53c9x_select(sc, ecb); 742 break; 743 } else 744 NCR_MISC(("%d:%d busy\n", 745 sc_link->scsipi_scsi.target, 746 sc_link->scsipi_scsi.lun)); 747 } 748 } 749 750 void 751 ncr53c9x_sense(sc, ecb) 752 struct ncr53c9x_softc *sc; 753 struct ncr53c9x_ecb *ecb; 754 { 755 struct scsipi_xfer *xs = ecb->xs; 756 struct scsipi_link *sc_link = xs->sc_link; 757 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 758 struct scsipi_sense *ss = (void *)&ecb->cmd.cmd; 759 760 NCR_MISC(("requesting sense ")); 761 /* Next, setup a request sense command block */ 762 bzero(ss, sizeof(*ss)); 763 ss->opcode = REQUEST_SENSE; 764 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 765 ss->length = sizeof(struct scsipi_sense_data); 766 ecb->clen = sizeof(*ss); 767 ecb->daddr = (char *)&xs->sense.scsi_sense; 768 ecb->dleft = sizeof(struct scsipi_sense_data); 769 ecb->flags |= ECB_SENSE; 770 ecb->timeout = NCR_SENSE_TIMEOUT; 771 ti->senses++; 772 if (ecb->flags & ECB_NEXUS) 773 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 774 if (ecb == sc->sc_nexus) { 775 ecb->flags &= ~ECB_NEXUS; 776 ncr53c9x_select(sc, ecb); 777 } else { 778 ncr53c9x_dequeue(sc, ecb); 779 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 780 if (sc->sc_state == NCR_IDLE) 781 ncr53c9x_sched(sc); 782 } 783 } 784 785 /* 786 * POST PROCESSING OF SCSI_CMD (usually current) 787 */ 788 void 789 ncr53c9x_done(sc, ecb) 790 struct ncr53c9x_softc *sc; 791 struct ncr53c9x_ecb *ecb; 792 { 793 struct scsipi_xfer *xs = ecb->xs; 794 struct scsipi_link *sc_link = xs->sc_link; 795 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 796 797 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 798 799 untimeout(ncr53c9x_timeout, ecb); 800 801 /* 802 * Now, if we've come here with no error code, i.e. we've kept the 803 * initial XS_NOERROR, and the status code signals that we should 804 * check sense, we'll need to set up a request sense cmd block and 805 * push the command back into the ready queue *before* any other 806 * commands for this target/lunit, else we lose the sense info. 807 * We don't support chk sense conditions for the request sense cmd. 808 */ 809 if (xs->error == XS_NOERROR) { 810 xs->status = ecb->stat; 811 if ((ecb->flags & ECB_ABORT) != 0) { 812 xs->error = XS_TIMEOUT; 813 } else if ((ecb->flags & ECB_SENSE) != 0) { 814 xs->error = XS_SENSE; 815 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 816 /* First, save the return values */ 817 xs->resid = ecb->dleft; 818 ncr53c9x_sense(sc, ecb); 819 return; 820 } else { 821 xs->resid = ecb->dleft; 822 } 823 } 824 825 xs->xs_status |= XS_STS_DONE; 826 827 #ifdef NCR53C9X_DEBUG 828 if (ncr53c9x_debug & NCR_SHOWMISC) { 829 if (xs->resid != 0) 830 printf("resid=%d ", xs->resid); 831 if (xs->error == XS_SENSE) 832 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 833 else 834 printf("error=%d\n", xs->error); 835 } 836 #endif 837 838 /* 839 * Remove the ECB from whatever queue it's on. 840 */ 841 if (ecb->flags & ECB_NEXUS) 842 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 843 if (ecb == sc->sc_nexus) { 844 sc->sc_nexus = NULL; 845 if (sc->sc_state != NCR_CLEANING) { 846 sc->sc_state = NCR_IDLE; 847 ncr53c9x_sched(sc); 848 } 849 } else 850 ncr53c9x_dequeue(sc, ecb); 851 852 ncr53c9x_free_ecb(sc, ecb, xs->xs_control); 853 ti->cmds++; 854 scsipi_done(xs); 855 } 856 857 void 858 ncr53c9x_dequeue(sc, ecb) 859 struct ncr53c9x_softc *sc; 860 struct ncr53c9x_ecb *ecb; 861 { 862 863 if (ecb->flags & ECB_NEXUS) { 864 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 865 ecb->flags &= ~ECB_NEXUS; 866 } else { 867 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 868 } 869 } 870 871 /* 872 * INTERRUPT/PROTOCOL ENGINE 873 */ 874 875 /* 876 * Schedule an outgoing message by prioritizing it, and asserting 877 * attention on the bus. We can only do this when we are the initiator 878 * else there will be an illegal command interrupt. 879 */ 880 #define ncr53c9x_sched_msgout(m) \ 881 do { \ 882 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 883 NCRCMD(sc, NCRCMD_SETATN); \ 884 sc->sc_flags |= NCR_ATN; \ 885 sc->sc_msgpriq |= (m); \ 886 } while (0) 887 888 int 889 ncr53c9x_reselect(sc, message) 890 struct ncr53c9x_softc *sc; 891 int message; 892 { 893 u_char selid, target, lun; 894 struct ncr53c9x_ecb *ecb; 895 struct scsipi_link *sc_link; 896 struct ncr53c9x_tinfo *ti; 897 898 /* 899 * The SCSI chip made a snapshot of the data bus while the reselection 900 * was being negotiated. This enables us to determine which target did 901 * the reselect. 902 */ 903 selid = sc->sc_selid & ~(1 << sc->sc_id); 904 if (selid & (selid - 1)) { 905 printf("%s: reselect with invalid selid %02x;" 906 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 907 goto reset; 908 } 909 910 /* 911 * Search wait queue for disconnected cmd 912 * The list should be short, so I haven't bothered with 913 * any more sophisticated structures than a simple 914 * singly linked list. 915 */ 916 target = ffs(selid) - 1; 917 lun = message & 0x07; 918 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 919 ecb = ecb->chain.tqe_next) { 920 sc_link = ecb->xs->sc_link; 921 if (sc_link->scsipi_scsi.target == target && 922 sc_link->scsipi_scsi.lun == lun) 923 break; 924 } 925 if (ecb == NULL) { 926 printf("%s: reselect from target %d lun %d with no nexus;" 927 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 928 goto abort; 929 } 930 931 /* Make this nexus active again. */ 932 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 933 sc->sc_state = NCR_CONNECTED; 934 sc->sc_nexus = ecb; 935 ti = &sc->sc_tinfo[target]; 936 #ifdef NCR53C9X_DEBUG 937 if ((ti->lubusy & (1 << lun)) == 0) { 938 printf("%s: reselect: target %d, lun %d: should be busy\n", 939 sc->sc_dev.dv_xname, target, lun); 940 ti->lubusy |= (1 << lun); 941 } 942 #endif 943 ncr53c9x_setsync(sc, ti); 944 945 if (ecb->flags & ECB_RESET) 946 ncr53c9x_sched_msgout(SEND_DEV_RESET); 947 else if (ecb->flags & ECB_ABORT) 948 ncr53c9x_sched_msgout(SEND_ABORT); 949 950 /* Do an implicit RESTORE POINTERS. */ 951 sc->sc_dp = ecb->daddr; 952 sc->sc_dleft = ecb->dleft; 953 954 return (0); 955 956 reset: 957 ncr53c9x_sched_msgout(SEND_DEV_RESET); 958 return (1); 959 960 abort: 961 ncr53c9x_sched_msgout(SEND_ABORT); 962 return (1); 963 } 964 965 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 966 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 967 #define ISEXTMSG(m) ((m) == 1) 968 969 /* 970 * Get an incoming message as initiator. 971 * 972 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 973 * byte in the FIFO 974 */ 975 void 976 ncr53c9x_msgin(sc) 977 register struct ncr53c9x_softc *sc; 978 { 979 register int v; 980 981 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 982 983 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 984 printf("%s: msgin: no msg byte available\n", 985 sc->sc_dev.dv_xname); 986 return; 987 } 988 989 /* 990 * Prepare for a new message. A message should (according 991 * to the SCSI standard) be transmitted in one single 992 * MESSAGE_IN_PHASE. If we have been in some other phase, 993 * then this is a new message. 994 */ 995 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 996 sc->sc_flags &= ~NCR_DROP_MSGI; 997 sc->sc_imlen = 0; 998 } 999 1000 v = NCR_READ_REG(sc, NCR_FIFO); 1001 NCR_MISC(("<msgbyte:0x%02x>", v)); 1002 1003 #if 0 1004 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 1005 /* 1006 * Which target is reselecting us? (The ID bit really) 1007 */ 1008 sc->sc_selid = v; 1009 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1010 return; 1011 } 1012 #endif 1013 1014 sc->sc_imess[sc->sc_imlen] = v; 1015 1016 /* 1017 * If we're going to reject the message, don't bother storing 1018 * the incoming bytes. But still, we need to ACK them. 1019 */ 1020 1021 if ((sc->sc_flags & NCR_DROP_MSGI)) { 1022 NCRCMD(sc, NCRCMD_MSGOK); 1023 printf("<dropping msg byte %x>", 1024 sc->sc_imess[sc->sc_imlen]); 1025 return; 1026 } 1027 1028 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1029 ncr53c9x_sched_msgout(SEND_REJECT); 1030 sc->sc_flags |= NCR_DROP_MSGI; 1031 } else { 1032 sc->sc_imlen++; 1033 /* 1034 * This testing is suboptimal, but most 1035 * messages will be of the one byte variety, so 1036 * it should not effect performance 1037 * significantly. 1038 */ 1039 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1040 goto gotit; 1041 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1042 goto gotit; 1043 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1044 sc->sc_imlen == sc->sc_imess[1] + 2) 1045 goto gotit; 1046 } 1047 /* Ack what we have so far */ 1048 NCRCMD(sc, NCRCMD_MSGOK); 1049 return; 1050 1051 gotit: 1052 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1053 /* 1054 * Now we should have a complete message (1 byte, 2 byte 1055 * and moderately long extended messages). We only handle 1056 * extended messages which total length is shorter than 1057 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1058 */ 1059 switch (sc->sc_state) { 1060 struct ncr53c9x_ecb *ecb; 1061 struct ncr53c9x_tinfo *ti; 1062 1063 case NCR_CONNECTED: 1064 ecb = sc->sc_nexus; 1065 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1066 1067 switch (sc->sc_imess[0]) { 1068 case MSG_CMDCOMPLETE: 1069 NCR_MSGS(("cmdcomplete ")); 1070 if (sc->sc_dleft < 0) { 1071 scsi_print_addr(ecb->xs->sc_link); 1072 printf("got %ld extra bytes\n", 1073 -(long)sc->sc_dleft); 1074 sc->sc_dleft = 0; 1075 } 1076 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1077 ? 0 1078 : sc->sc_dleft; 1079 if ((ecb->flags & ECB_SENSE) == 0) 1080 ecb->xs->resid = ecb->dleft; 1081 sc->sc_state = NCR_CMDCOMPLETE; 1082 break; 1083 1084 case MSG_MESSAGE_REJECT: 1085 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1086 switch (sc->sc_msgout) { 1087 case SEND_SDTR: 1088 sc->sc_flags &= ~NCR_SYNCHNEGO; 1089 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1090 ncr53c9x_setsync(sc, ti); 1091 break; 1092 case SEND_INIT_DET_ERR: 1093 goto abort; 1094 } 1095 break; 1096 1097 case MSG_NOOP: 1098 NCR_MSGS(("noop ")); 1099 break; 1100 1101 case MSG_DISCONNECT: 1102 NCR_MSGS(("disconnect ")); 1103 ti->dconns++; 1104 sc->sc_state = NCR_DISCONNECT; 1105 1106 /* 1107 * Mark the fact that all bytes have moved. The 1108 * target may not bother to do a SAVE POINTERS 1109 * at this stage. This flag will set the residual 1110 * count to zero on MSG COMPLETE. 1111 */ 1112 if (sc->sc_dleft == 0) 1113 ecb->flags |= ECB_TENTATIVE_DONE; 1114 1115 break; 1116 1117 case MSG_SAVEDATAPOINTER: 1118 NCR_MSGS(("save datapointer ")); 1119 ecb->daddr = sc->sc_dp; 1120 ecb->dleft = sc->sc_dleft; 1121 break; 1122 1123 case MSG_RESTOREPOINTERS: 1124 NCR_MSGS(("restore datapointer ")); 1125 sc->sc_dp = ecb->daddr; 1126 sc->sc_dleft = ecb->dleft; 1127 break; 1128 1129 case MSG_EXTENDED: 1130 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1131 switch (sc->sc_imess[2]) { 1132 case MSG_EXT_SDTR: 1133 NCR_MSGS(("SDTR period %d, offset %d ", 1134 sc->sc_imess[3], sc->sc_imess[4])); 1135 if (sc->sc_imess[1] != 3) 1136 goto reject; 1137 ti->period = sc->sc_imess[3]; 1138 ti->offset = sc->sc_imess[4]; 1139 ti->flags &= ~T_NEGOTIATE; 1140 if (sc->sc_minsync == 0 || 1141 ti->offset == 0 || 1142 ti->period > 124) { 1143 #ifdef NCR53C9X_DEBUG 1144 scsi_print_addr(ecb->xs->sc_link); 1145 printf("async mode\n"); 1146 #endif 1147 if ((sc->sc_flags&NCR_SYNCHNEGO) 1148 == 0) { 1149 /* 1150 * target initiated negotiation 1151 */ 1152 ti->offset = 0; 1153 ti->flags &= ~T_SYNCMODE; 1154 ncr53c9x_sched_msgout( 1155 SEND_SDTR); 1156 } else { 1157 /* we are async */ 1158 ti->flags &= ~T_SYNCMODE; 1159 } 1160 } else { 1161 int r = 250/ti->period; 1162 int s = (100*250)/ti->period - 100*r; 1163 int p; 1164 1165 p = ncr53c9x_stp2cpb(sc, ti->period); 1166 ti->period = ncr53c9x_cpb2stp(sc, p); 1167 #ifdef NCR53C9X_DEBUG 1168 scsi_print_addr(ecb->xs->sc_link); 1169 printf("max sync rate %d.%02dMb/s\n", 1170 r, s); 1171 #endif 1172 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) { 1173 /* 1174 * target initiated negotiation 1175 */ 1176 if (ti->period < 1177 sc->sc_minsync) 1178 ti->period = 1179 sc->sc_minsync; 1180 if (ti->offset > 15) 1181 ti->offset = 15; 1182 ti->flags &= ~T_SYNCMODE; 1183 ncr53c9x_sched_msgout( 1184 SEND_SDTR); 1185 } else { 1186 /* we are sync */ 1187 ti->flags |= T_SYNCMODE; 1188 } 1189 } 1190 sc->sc_flags &= ~NCR_SYNCHNEGO; 1191 ncr53c9x_setsync(sc, ti); 1192 break; 1193 1194 default: 1195 scsi_print_addr(ecb->xs->sc_link); 1196 printf("unrecognized MESSAGE EXTENDED;" 1197 " sending REJECT\n"); 1198 goto reject; 1199 } 1200 break; 1201 1202 default: 1203 NCR_MSGS(("ident ")); 1204 scsi_print_addr(ecb->xs->sc_link); 1205 printf("unrecognized MESSAGE; sending REJECT\n"); 1206 reject: 1207 ncr53c9x_sched_msgout(SEND_REJECT); 1208 break; 1209 } 1210 break; 1211 1212 case NCR_RESELECTED: 1213 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1214 printf("%s: reselect without IDENTIFY;" 1215 " sending DEVICE RESET\n", 1216 sc->sc_dev.dv_xname); 1217 goto reset; 1218 } 1219 1220 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1221 break; 1222 1223 default: 1224 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1225 sc->sc_dev.dv_xname); 1226 reset: 1227 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1228 break; 1229 1230 abort: 1231 ncr53c9x_sched_msgout(SEND_ABORT); 1232 break; 1233 } 1234 1235 /* Ack last message byte */ 1236 NCRCMD(sc, NCRCMD_MSGOK); 1237 1238 /* Done, reset message pointer. */ 1239 sc->sc_flags &= ~NCR_DROP_MSGI; 1240 sc->sc_imlen = 0; 1241 } 1242 1243 1244 /* 1245 * Send the highest priority, scheduled message 1246 */ 1247 void 1248 ncr53c9x_msgout(sc) 1249 register struct ncr53c9x_softc *sc; 1250 { 1251 struct ncr53c9x_tinfo *ti; 1252 struct ncr53c9x_ecb *ecb; 1253 size_t size; 1254 1255 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1256 sc->sc_msgpriq, sc->sc_prevphase)); 1257 1258 /* 1259 * XXX - the NCR_ATN flag is not in sync with the actual ATN 1260 * condition on the SCSI bus. The 53c9x chip 1261 * automatically turns off ATN before sending the 1262 * message byte. (see also the comment below in the 1263 * default case when picking out a message to send) 1264 */ 1265 if (sc->sc_flags & NCR_ATN) { 1266 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1267 new: 1268 NCRCMD(sc, NCRCMD_FLUSH); 1269 DELAY(1); 1270 sc->sc_msgoutq = 0; 1271 sc->sc_omlen = 0; 1272 } 1273 } else { 1274 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1275 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1276 goto new; 1277 } else { 1278 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1279 sc->sc_dev.dv_xname, __LINE__); 1280 } 1281 } 1282 1283 if (sc->sc_omlen == 0) { 1284 /* Pick up highest priority message */ 1285 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1286 sc->sc_msgoutq |= sc->sc_msgout; 1287 sc->sc_msgpriq &= ~sc->sc_msgout; 1288 sc->sc_omlen = 1; /* "Default" message len */ 1289 switch (sc->sc_msgout) { 1290 case SEND_SDTR: 1291 ecb = sc->sc_nexus; 1292 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1293 sc->sc_omess[0] = MSG_EXTENDED; 1294 sc->sc_omess[1] = 3; 1295 sc->sc_omess[2] = MSG_EXT_SDTR; 1296 sc->sc_omess[3] = ti->period; 1297 sc->sc_omess[4] = ti->offset; 1298 sc->sc_omlen = 5; 1299 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1300 ti->flags |= T_SYNCMODE; 1301 ncr53c9x_setsync(sc, ti); 1302 } 1303 break; 1304 case SEND_IDENTIFY: 1305 if (sc->sc_state != NCR_CONNECTED) { 1306 printf("%s at line %d: no nexus\n", 1307 sc->sc_dev.dv_xname, __LINE__); 1308 } 1309 ecb = sc->sc_nexus; 1310 sc->sc_omess[0] = 1311 MSG_IDENTIFY(ecb->xs->sc_link->scsipi_scsi.lun, 0); 1312 break; 1313 case SEND_DEV_RESET: 1314 sc->sc_flags |= NCR_ABORTING; 1315 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1316 ecb = sc->sc_nexus; 1317 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1318 ti->flags &= ~T_SYNCMODE; 1319 ti->flags |= T_NEGOTIATE; 1320 break; 1321 case SEND_PARITY_ERROR: 1322 sc->sc_omess[0] = MSG_PARITY_ERROR; 1323 break; 1324 case SEND_ABORT: 1325 sc->sc_flags |= NCR_ABORTING; 1326 sc->sc_omess[0] = MSG_ABORT; 1327 break; 1328 case SEND_INIT_DET_ERR: 1329 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1330 break; 1331 case SEND_REJECT: 1332 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1333 break; 1334 default: 1335 /* 1336 * We normally do not get here, since the chip 1337 * automatically turns off ATN before the last 1338 * byte of a message is sent to the target. 1339 * However, if the target rejects our (multi-byte) 1340 * message early by switching to MSG IN phase 1341 * ATN remains on, so the target may return to 1342 * MSG OUT phase. If there are no scheduled messages 1343 * left we send a NO-OP. 1344 * 1345 * XXX - Note that this leaves no useful purpose for 1346 * the NCR_ATN flag. 1347 */ 1348 sc->sc_flags &= ~NCR_ATN; 1349 sc->sc_omess[0] = MSG_NOOP; 1350 break; 1351 } 1352 sc->sc_omp = sc->sc_omess; 1353 } 1354 1355 /* (re)send the message */ 1356 size = min(sc->sc_omlen, sc->sc_maxxfer); 1357 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1358 /* Program the SCSI counter */ 1359 NCR_WRITE_REG(sc, NCR_TCL, size); 1360 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1361 if (sc->sc_cfg2 & NCRCFG2_FE) { 1362 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1363 } 1364 /* Load the count in and start the message-out transfer */ 1365 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1366 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1367 NCRDMA_GO(sc); 1368 } 1369 1370 /* 1371 * This is the most critical part of the driver, and has to know 1372 * how to deal with *all* error conditions and phases from the SCSI 1373 * bus. If there are no errors and the DMA was active, then call the 1374 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1375 * and we can return from here without further processing. 1376 * 1377 * Most of this needs verifying. 1378 */ 1379 int sdebug = 0; 1380 int 1381 ncr53c9x_intr(sc) 1382 register struct ncr53c9x_softc *sc; 1383 { 1384 register struct ncr53c9x_ecb *ecb; 1385 register struct scsipi_link *sc_link; 1386 struct ncr53c9x_tinfo *ti; 1387 size_t size; 1388 int nfifo; 1389 1390 NCR_TRACE(("[ncr53c9x_intr] ")); 1391 1392 if (!NCRDMA_ISINTR(sc)) 1393 return (0); 1394 1395 again: 1396 /* and what do the registers say... */ 1397 ncr53c9x_readregs(sc); 1398 1399 sc->sc_intrcnt.ev_count++; 1400 1401 /* 1402 * At the moment, only a SCSI Bus Reset or Illegal 1403 * Command are classed as errors. A disconnect is a 1404 * valid condition, and we let the code check is the 1405 * "NCR_BUSFREE_OK" flag was set before declaring it 1406 * and error. 1407 * 1408 * Also, the status register tells us about "Gross 1409 * Errors" and "Parity errors". Only the Gross Error 1410 * is really bad, and the parity errors are dealt 1411 * with later 1412 * 1413 * TODO 1414 * If there are too many parity error, go to slow 1415 * cable mode ? 1416 */ 1417 1418 /* SCSI Reset */ 1419 if (sc->sc_espintr & NCRINTR_SBR) { 1420 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1421 NCRCMD(sc, NCRCMD_FLUSH); 1422 DELAY(1); 1423 } 1424 if (sc->sc_state != NCR_SBR) { 1425 printf("%s: SCSI bus reset\n", 1426 sc->sc_dev.dv_xname); 1427 ncr53c9x_init(sc, 0); /* Restart everything */ 1428 return (1); 1429 } 1430 #if 0 1431 /*XXX*/ printf("<expected bus reset: " 1432 "[intr %x, stat %x, step %d]>\n", 1433 sc->sc_espintr, sc->sc_espstat, 1434 sc->sc_espstep); 1435 #endif 1436 if (sc->sc_nexus) 1437 panic("%s: nexus in reset state", 1438 sc->sc_dev.dv_xname); 1439 goto sched; 1440 } 1441 1442 ecb = sc->sc_nexus; 1443 1444 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1445 if (sc->sc_espintr & NCRINTR_ERR || 1446 sc->sc_espstat & NCRSTAT_GE) { 1447 1448 if (sc->sc_espstat & NCRSTAT_GE) { 1449 /* Gross Error; no target ? */ 1450 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1451 NCRCMD(sc, NCRCMD_FLUSH); 1452 DELAY(1); 1453 } 1454 if (sc->sc_state == NCR_CONNECTED || 1455 sc->sc_state == NCR_SELECTING) { 1456 ecb->xs->error = XS_TIMEOUT; 1457 ncr53c9x_done(sc, ecb); 1458 } 1459 return (1); 1460 } 1461 1462 if (sc->sc_espintr & NCRINTR_ILL) { 1463 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1464 /* 1465 * Eat away "Illegal command" interrupt 1466 * on a ESP100 caused by a re-selection 1467 * while we were trying to select 1468 * another target. 1469 */ 1470 #ifdef DEBUG 1471 printf("%s: ESP100 work-around activated\n", 1472 sc->sc_dev.dv_xname); 1473 #endif 1474 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1475 return (1); 1476 } 1477 /* illegal command, out of sync ? */ 1478 printf("%s: illegal command: 0x%x " 1479 "(state %d, phase %x, prevphase %x)\n", 1480 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1481 sc->sc_state, sc->sc_phase, 1482 sc->sc_prevphase); 1483 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1484 NCRCMD(sc, NCRCMD_FLUSH); 1485 DELAY(1); 1486 } 1487 ncr53c9x_init(sc, 1); /* Restart everything */ 1488 return (1); 1489 } 1490 } 1491 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1492 1493 /* 1494 * Call if DMA is active. 1495 * 1496 * If DMA_INTR returns true, then maybe go 'round the loop 1497 * again in case there is no more DMA queued, but a phase 1498 * change is expected. 1499 */ 1500 if (NCRDMA_ISACTIVE(sc)) { 1501 int r = NCRDMA_INTR(sc); 1502 if (r == -1) { 1503 printf("%s: DMA error; resetting\n", 1504 sc->sc_dev.dv_xname); 1505 ncr53c9x_init(sc, 1); 1506 } 1507 /* If DMA active here, then go back to work... */ 1508 if (NCRDMA_ISACTIVE(sc)) 1509 return (1); 1510 1511 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 1512 /* 1513 * DMA not completed. If we can not find a 1514 * acceptable explanation, print a diagnostic. 1515 */ 1516 if (sc->sc_state == NCR_SELECTING) 1517 /* 1518 * This can happen if we are reselected 1519 * while using DMA to select a target. 1520 */ 1521 /*void*/; 1522 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1523 /* 1524 * Our (multi-byte) message (eg SDTR) was 1525 * interrupted by the target to send 1526 * a MSG REJECT. 1527 * Print diagnostic if current phase 1528 * is not MESSAGE IN. 1529 */ 1530 if (sc->sc_phase != MESSAGE_IN_PHASE) 1531 printf("%s: !TC on MSG OUT" 1532 " [intr %x, stat %x, step %d]" 1533 " prevphase %x, resid %lx\n", 1534 sc->sc_dev.dv_xname, 1535 sc->sc_espintr, 1536 sc->sc_espstat, 1537 sc->sc_espstep, 1538 sc->sc_prevphase, 1539 (u_long)sc->sc_omlen); 1540 } else if (sc->sc_dleft == 0) { 1541 /* 1542 * The DMA operation was started for 1543 * a DATA transfer. Print a diagnostic 1544 * if the DMA counter and TC bit 1545 * appear to be out of sync. 1546 */ 1547 printf("%s: !TC on DATA XFER" 1548 " [intr %x, stat %x, step %d]" 1549 " prevphase %x, resid %x\n", 1550 sc->sc_dev.dv_xname, 1551 sc->sc_espintr, 1552 sc->sc_espstat, 1553 sc->sc_espstep, 1554 sc->sc_prevphase, 1555 ecb?ecb->dleft:-1); 1556 } 1557 } 1558 } 1559 1560 /* 1561 * Check for less serious errors. 1562 */ 1563 if (sc->sc_espstat & NCRSTAT_PE) { 1564 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1565 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1566 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1567 else 1568 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1569 } 1570 1571 if (sc->sc_espintr & NCRINTR_DIS) { 1572 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1573 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1574 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1575 NCRCMD(sc, NCRCMD_FLUSH); 1576 DELAY(1); 1577 } 1578 /* 1579 * This command must (apparently) be issued within 1580 * 250mS of a disconnect. So here you are... 1581 */ 1582 NCRCMD(sc, NCRCMD_ENSEL); 1583 1584 switch (sc->sc_state) { 1585 case NCR_RESELECTED: 1586 goto sched; 1587 1588 case NCR_SELECTING: 1589 ecb->xs->error = XS_SELTIMEOUT; 1590 goto finish; 1591 1592 case NCR_CONNECTED: 1593 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1594 #ifdef NCR53C9X_DEBUG 1595 if (ecb) 1596 scsi_print_addr(ecb->xs->sc_link); 1597 printf("sync nego not completed!\n"); 1598 #endif 1599 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1600 sc->sc_flags &= ~NCR_SYNCHNEGO; 1601 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1602 } 1603 1604 /* it may be OK to disconnect */ 1605 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1606 /* 1607 * Section 5.1.1 of the SCSI 2 spec 1608 * suggests issuing a REQUEST SENSE 1609 * following an unexpected disconnect. 1610 * Some devices go into a contingent 1611 * allegiance condition when 1612 * disconnecting, and this is necessary 1613 * to clean up their state. 1614 */ 1615 printf("%s: unexpected disconnect; ", 1616 sc->sc_dev.dv_xname); 1617 if (ecb->flags & ECB_SENSE) { 1618 printf("resetting\n"); 1619 goto reset; 1620 } 1621 printf("sending REQUEST SENSE\n"); 1622 untimeout(ncr53c9x_timeout, ecb); 1623 ncr53c9x_sense(sc, ecb); 1624 goto out; 1625 } 1626 1627 ecb->xs->error = XS_TIMEOUT; 1628 goto finish; 1629 1630 case NCR_DISCONNECT: 1631 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1632 sc->sc_nexus = NULL; 1633 goto sched; 1634 1635 case NCR_CMDCOMPLETE: 1636 goto finish; 1637 } 1638 } 1639 1640 switch (sc->sc_state) { 1641 1642 case NCR_SBR: 1643 printf("%s: waiting for SCSI Bus Reset to happen\n", 1644 sc->sc_dev.dv_xname); 1645 return (1); 1646 1647 case NCR_RESELECTED: 1648 /* 1649 * we must be continuing a message ? 1650 */ 1651 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1652 printf("%s: target didn't identify\n", 1653 sc->sc_dev.dv_xname); 1654 ncr53c9x_init(sc, 1); 1655 return (1); 1656 } 1657 printf("<<RESELECT CONT'd>>"); 1658 #if XXXX 1659 ncr53c9x_msgin(sc); 1660 if (sc->sc_state != NCR_CONNECTED) { 1661 /* IDENTIFY fail?! */ 1662 printf("%s: identify failed\n", 1663 sc->sc_dev.dv_xname); 1664 ncr53c9x_init(sc, 1); 1665 return (1); 1666 } 1667 #endif 1668 break; 1669 1670 case NCR_IDLE: 1671 case NCR_SELECTING: 1672 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1673 sc->sc_flags = 0; 1674 ecb = sc->sc_nexus; 1675 if (ecb != NULL && (ecb->flags & ECB_NEXUS)) { 1676 scsi_print_addr(ecb->xs->sc_link); 1677 printf("ECB_NEXUS while in state %x\n", sc->sc_state); 1678 } 1679 1680 if (sc->sc_espintr & NCRINTR_RESEL) { 1681 /* 1682 * If we're trying to select a 1683 * target ourselves, push our command 1684 * back into the ready list. 1685 */ 1686 if (sc->sc_state == NCR_SELECTING) { 1687 NCR_MISC(("backoff selector ")); 1688 untimeout(ncr53c9x_timeout, ecb); 1689 sc_link = ecb->xs->sc_link; 1690 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1691 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1692 ecb = sc->sc_nexus = NULL; 1693 } 1694 sc->sc_state = NCR_RESELECTED; 1695 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1696 /* 1697 * Things are seriously fucked up. 1698 * Pull the brakes, i.e. reset 1699 */ 1700 printf("%s: target didn't identify\n", 1701 sc->sc_dev.dv_xname); 1702 ncr53c9x_init(sc, 1); 1703 return (1); 1704 } 1705 /* 1706 * The C90 only inhibits FIFO writes until 1707 * reselection is complete, instead of 1708 * waiting until the interrupt status register 1709 * has been read. So, if the reselect happens 1710 * while we were entering a command bytes (for 1711 * another target) some of those bytes can 1712 * appear in the FIFO here, after the 1713 * interrupt is taken. 1714 */ 1715 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1716 if (nfifo < 2 || 1717 (nfifo > 2 && 1718 sc->sc_rev != NCR_VARIANT_ESP100)) { 1719 printf("%s: RESELECT: %d bytes in FIFO! " 1720 "[intr %x, stat %x, step %d, prevphase %x]\n", 1721 sc->sc_dev.dv_xname, 1722 nfifo, 1723 sc->sc_espintr, 1724 sc->sc_espstat, 1725 sc->sc_espstep, 1726 sc->sc_prevphase); 1727 ncr53c9x_init(sc, 1); 1728 return (1); 1729 } 1730 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1731 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1732 1733 /* Handle identify message */ 1734 ncr53c9x_msgin(sc); 1735 if (nfifo != 2) { 1736 /* 1737 * Note: this should not happen 1738 * with `dmaselect' on. 1739 */ 1740 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1741 NCRCMD(sc, NCRCMD_FLUSH); 1742 } else if (ncr53c9x_dmaselect && 1743 sc->sc_rev == NCR_VARIANT_ESP100) { 1744 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1745 } 1746 1747 if (sc->sc_state != NCR_CONNECTED) { 1748 /* IDENTIFY fail?! */ 1749 printf("%s: identify failed\n", 1750 sc->sc_dev.dv_xname); 1751 ncr53c9x_init(sc, 1); 1752 return (1); 1753 } 1754 goto shortcut; /* ie. next phase expected soon */ 1755 } 1756 1757 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1758 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1759 /* 1760 * Arbitration won; examine the `step' register 1761 * to determine how far the selection could progress. 1762 */ 1763 ecb = sc->sc_nexus; 1764 if (!ecb) 1765 panic("ncr53c9x: no nexus"); 1766 1767 sc_link = ecb->xs->sc_link; 1768 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1769 1770 switch (sc->sc_espstep) { 1771 case 0: 1772 /* 1773 * The target did not respond with a 1774 * message out phase - probably an old 1775 * device that doesn't recognize ATN. 1776 * Clear ATN and just continue, the 1777 * target should be in the command 1778 * phase. 1779 * XXXX check for command phase? 1780 */ 1781 NCRCMD(sc, NCRCMD_RSTATN); 1782 break; 1783 case 1: 1784 if ((ti->flags & T_NEGOTIATE) == 0) { 1785 printf("%s: step 1 & !NEG\n", 1786 sc->sc_dev.dv_xname); 1787 goto reset; 1788 } 1789 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1790 printf("%s: !MSGOUT\n", 1791 sc->sc_dev.dv_xname); 1792 goto reset; 1793 } 1794 /* Start negotiating */ 1795 ti->period = sc->sc_minsync; 1796 ti->offset = 15; 1797 sc->sc_flags |= NCR_SYNCHNEGO; 1798 ncr53c9x_sched_msgout(SEND_SDTR); 1799 break; 1800 case 3: 1801 /* 1802 * Grr, this is supposed to mean 1803 * "target left command phase prematurely". 1804 * It seems to happen regularly when 1805 * sync mode is on. 1806 * Look at FIFO to see if command went out. 1807 * (Timing problems?) 1808 */ 1809 if (ncr53c9x_dmaselect) { 1810 if (sc->sc_cmdlen == 0) 1811 /* Hope for the best.. */ 1812 break; 1813 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1814 & NCRFIFO_FF) == 0) { 1815 /* Hope for the best.. */ 1816 break; 1817 } 1818 printf("(%s:%d:%d): selection failed;" 1819 " %d left in FIFO " 1820 "[intr %x, stat %x, step %d]\n", 1821 sc->sc_dev.dv_xname, 1822 sc_link->scsipi_scsi.target, 1823 sc_link->scsipi_scsi.lun, 1824 NCR_READ_REG(sc, NCR_FFLAG) 1825 & NCRFIFO_FF, 1826 sc->sc_espintr, sc->sc_espstat, 1827 sc->sc_espstep); 1828 NCRCMD(sc, NCRCMD_FLUSH); 1829 ncr53c9x_sched_msgout(SEND_ABORT); 1830 return (1); 1831 case 2: 1832 /* Select stuck at Command Phase */ 1833 NCRCMD(sc, NCRCMD_FLUSH); 1834 case 4: 1835 if (ncr53c9x_dmaselect && 1836 sc->sc_cmdlen != 0) 1837 printf("(%s:%d:%d): select; " 1838 "%lu left in DMA buffer " 1839 "[intr %x, stat %x, step %d]\n", 1840 sc->sc_dev.dv_xname, 1841 sc_link->scsipi_scsi.target, 1842 sc_link->scsipi_scsi.lun, 1843 (u_long)sc->sc_cmdlen, 1844 sc->sc_espintr, 1845 sc->sc_espstat, 1846 sc->sc_espstep); 1847 /* So far, everything went fine */ 1848 break; 1849 } 1850 1851 ecb->flags |= ECB_NEXUS; 1852 ti->lubusy |= (1 << sc_link->scsipi_scsi.lun); 1853 1854 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1855 /* Do an implicit RESTORE POINTERS. */ 1856 sc->sc_dp = ecb->daddr; 1857 sc->sc_dleft = ecb->dleft; 1858 sc->sc_state = NCR_CONNECTED; 1859 break; 1860 1861 } else { 1862 1863 printf("%s: unexpected status after select" 1864 ": [intr %x, stat %x, step %x]\n", 1865 sc->sc_dev.dv_xname, 1866 sc->sc_espintr, sc->sc_espstat, 1867 sc->sc_espstep); 1868 NCRCMD(sc, NCRCMD_FLUSH); 1869 DELAY(1); 1870 goto reset; 1871 } 1872 if (sc->sc_state == NCR_IDLE) { 1873 printf("%s: stray interrupt\n", 1874 sc->sc_dev.dv_xname); 1875 return (0); 1876 } 1877 break; 1878 1879 case NCR_CONNECTED: 1880 if (sc->sc_flags & NCR_ICCS) { 1881 /* "Initiate Command Complete Steps" in progress */ 1882 u_char msg; 1883 1884 sc->sc_flags &= ~NCR_ICCS; 1885 1886 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1887 printf("%s: ICCS: " 1888 ": [intr %x, stat %x, step %x]\n", 1889 sc->sc_dev.dv_xname, 1890 sc->sc_espintr, sc->sc_espstat, 1891 sc->sc_espstep); 1892 } 1893 if ((NCR_READ_REG(sc, NCR_FFLAG) 1894 & NCRFIFO_FF) != 2) { 1895 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1896 & NCRFIFO_FF) - 2; 1897 while (i--) 1898 (void) NCR_READ_REG(sc, NCR_FIFO); 1899 } 1900 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1901 msg = NCR_READ_REG(sc, NCR_FIFO); 1902 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1903 if (msg == MSG_CMDCOMPLETE) { 1904 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1905 ? 0 1906 : sc->sc_dleft; 1907 if ((ecb->flags & ECB_SENSE) == 0) 1908 ecb->xs->resid = ecb->dleft; 1909 sc->sc_state = NCR_CMDCOMPLETE; 1910 } else 1911 printf("%s: STATUS_PHASE: msg %d\n", 1912 sc->sc_dev.dv_xname, msg); 1913 NCRCMD(sc, NCRCMD_MSGOK); 1914 goto shortcut; /* ie. wait for disconnect */ 1915 } 1916 break; 1917 default: 1918 panic("%s: invalid state: %d", 1919 sc->sc_dev.dv_xname, 1920 sc->sc_state); 1921 } 1922 1923 /* 1924 * Driver is now in state NCR_CONNECTED, i.e. we 1925 * have a current command working the SCSI bus. 1926 */ 1927 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1928 panic("ncr53c9x: no nexus"); 1929 } 1930 1931 switch (sc->sc_phase) { 1932 case MESSAGE_OUT_PHASE: 1933 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1934 ncr53c9x_msgout(sc); 1935 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1936 break; 1937 case MESSAGE_IN_PHASE: 1938 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1939 sc->sc_prevphase = MESSAGE_IN_PHASE; 1940 if (sc->sc_espintr & NCRINTR_BS) { 1941 NCRCMD(sc, NCRCMD_FLUSH); 1942 sc->sc_flags |= NCR_WAITI; 1943 NCRCMD(sc, NCRCMD_TRANS); 1944 } else if (sc->sc_espintr & NCRINTR_FC) { 1945 if ((sc->sc_flags & NCR_WAITI) == 0) { 1946 printf("%s: MSGIN: unexpected FC bit: " 1947 "[intr %x, stat %x, step %x]\n", 1948 sc->sc_dev.dv_xname, 1949 sc->sc_espintr, sc->sc_espstat, 1950 sc->sc_espstep); 1951 } 1952 sc->sc_flags &= ~NCR_WAITI; 1953 ncr53c9x_msgin(sc); 1954 } else { 1955 printf("%s: MSGIN: weird bits: " 1956 "[intr %x, stat %x, step %x]\n", 1957 sc->sc_dev.dv_xname, 1958 sc->sc_espintr, sc->sc_espstat, 1959 sc->sc_espstep); 1960 } 1961 goto shortcut; /* i.e. expect data to be ready */ 1962 break; 1963 case COMMAND_PHASE: 1964 /* 1965 * Send the command block. Normally we don't see this 1966 * phase because the SEL_ATN command takes care of 1967 * all this. However, we end up here if either the 1968 * target or we wanted to exchange some more messages 1969 * first (e.g. to start negotiations). 1970 */ 1971 1972 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 1973 ecb->cmd.cmd.opcode, ecb->clen)); 1974 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1975 NCRCMD(sc, NCRCMD_FLUSH); 1976 DELAY(1); 1977 } 1978 if (ncr53c9x_dmaselect) { 1979 size_t size; 1980 /* setup DMA transfer for command */ 1981 size = ecb->clen; 1982 sc->sc_cmdlen = size; 1983 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 1984 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 1985 0, &size); 1986 /* Program the SCSI counter */ 1987 NCR_WRITE_REG(sc, NCR_TCL, size); 1988 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1989 if (sc->sc_cfg2 & NCRCFG2_FE) { 1990 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1991 } 1992 1993 /* load the count in */ 1994 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1995 1996 /* start the command transfer */ 1997 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 1998 NCRDMA_GO(sc); 1999 } else { 2000 u_char *cmd = (u_char *)&ecb->cmd.cmd; 2001 int i; 2002 /* Now the command into the FIFO */ 2003 for (i = 0; i < ecb->clen; i++) 2004 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 2005 NCRCMD(sc, NCRCMD_TRANS); 2006 } 2007 sc->sc_prevphase = COMMAND_PHASE; 2008 break; 2009 case DATA_OUT_PHASE: 2010 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 2011 NCRCMD(sc, NCRCMD_FLUSH); 2012 size = min(sc->sc_dleft, sc->sc_maxxfer); 2013 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2014 0, &size); 2015 sc->sc_prevphase = DATA_OUT_PHASE; 2016 goto setup_xfer; 2017 case DATA_IN_PHASE: 2018 NCR_PHASE(("DATA_IN_PHASE ")); 2019 if (sc->sc_rev == NCR_VARIANT_ESP100) 2020 NCRCMD(sc, NCRCMD_FLUSH); 2021 size = min(sc->sc_dleft, sc->sc_maxxfer); 2022 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2023 1, &size); 2024 sc->sc_prevphase = DATA_IN_PHASE; 2025 setup_xfer: 2026 /* Target returned to data phase: wipe "done" memory */ 2027 ecb->flags &= ~ECB_TENTATIVE_DONE; 2028 2029 /* Program the SCSI counter */ 2030 NCR_WRITE_REG(sc, NCR_TCL, size); 2031 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2032 if (sc->sc_cfg2 & NCRCFG2_FE) { 2033 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2034 } 2035 /* load the count in */ 2036 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2037 2038 /* 2039 * Note that if `size' is 0, we've already transceived 2040 * all the bytes we want but we're still in DATA PHASE. 2041 * Apparently, the device needs padding. Also, a 2042 * transfer size of 0 means "maximum" to the chip 2043 * DMA logic. 2044 */ 2045 NCRCMD(sc, 2046 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 2047 NCRDMA_GO(sc); 2048 return (1); 2049 case STATUS_PHASE: 2050 NCR_PHASE(("STATUS_PHASE ")); 2051 sc->sc_flags |= NCR_ICCS; 2052 NCRCMD(sc, NCRCMD_ICCS); 2053 sc->sc_prevphase = STATUS_PHASE; 2054 goto shortcut; /* i.e. expect status results soon */ 2055 break; 2056 case INVALID_PHASE: 2057 break; 2058 default: 2059 printf("%s: unexpected bus phase; resetting\n", 2060 sc->sc_dev.dv_xname); 2061 goto reset; 2062 } 2063 2064 out: 2065 return (1); 2066 2067 reset: 2068 ncr53c9x_init(sc, 1); 2069 goto out; 2070 2071 finish: 2072 ncr53c9x_done(sc, ecb); 2073 goto out; 2074 2075 sched: 2076 sc->sc_state = NCR_IDLE; 2077 ncr53c9x_sched(sc); 2078 goto out; 2079 2080 shortcut: 2081 /* 2082 * The idea is that many of the SCSI operations take very little 2083 * time, and going away and getting interrupted is too high an 2084 * overhead to pay. For example, selecting, sending a message 2085 * and command and then doing some work can be done in one "pass". 2086 * 2087 * The delay is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 2088 * at 40Mhz. This needs testing. 2089 */ 2090 DELAY(50/sc->sc_freq); 2091 if (NCRDMA_ISINTR(sc)) 2092 goto again; 2093 goto out; 2094 } 2095 2096 void 2097 ncr53c9x_abort(sc, ecb) 2098 struct ncr53c9x_softc *sc; 2099 struct ncr53c9x_ecb *ecb; 2100 { 2101 2102 /* 2 secs for the abort */ 2103 ecb->timeout = NCR_ABORT_TIMEOUT; 2104 ecb->flags |= ECB_ABORT; 2105 2106 if (ecb == sc->sc_nexus) { 2107 /* 2108 * If we're still selecting, the message will be scheduled 2109 * after selection is complete. 2110 */ 2111 if (sc->sc_state == NCR_CONNECTED) 2112 ncr53c9x_sched_msgout(SEND_ABORT); 2113 2114 /* 2115 * Reschedule timeout. First, cancel a queued timeout (if any) 2116 * in case someone decides to call ncr53c9x_abort() from 2117 * elsewhere. 2118 */ 2119 untimeout(ncr53c9x_timeout, ecb); 2120 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 2121 } else { 2122 /* The command should be on the nexus list */ 2123 if ((ecb->flags & ECB_NEXUS) == 0) { 2124 scsi_print_addr(ecb->xs->sc_link); 2125 printf("ncr53c9x_abort: not NEXUS\n"); 2126 ncr53c9x_init(sc, 1); 2127 } 2128 /* 2129 * Just leave the command on the nexus list. 2130 * XXX - what choice do we have but to reset the SCSI 2131 * eventually? 2132 */ 2133 if (sc->sc_state == NCR_IDLE) 2134 ncr53c9x_sched(sc); 2135 } 2136 } 2137 2138 void 2139 ncr53c9x_timeout(arg) 2140 void *arg; 2141 { 2142 struct ncr53c9x_ecb *ecb = arg; 2143 struct scsipi_xfer *xs = ecb->xs; 2144 struct scsipi_link *sc_link = xs->sc_link; 2145 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 2146 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 2147 int s; 2148 2149 scsi_print_addr(sc_link); 2150 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2151 "<state %d, nexus %p, phase(l %x, c %x, p %x), resid %lx, " 2152 "msg(q %x,o %x) %s>", 2153 sc->sc_dev.dv_xname, 2154 ecb, ecb->flags, ecb->dleft, ecb->stat, 2155 sc->sc_state, sc->sc_nexus, 2156 NCR_READ_REG(sc, NCR_STAT), 2157 sc->sc_phase, sc->sc_prevphase, 2158 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2159 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2160 #if NCR53C9X_DEBUG > 1 2161 printf("TRACE: %s.", ecb->trace); 2162 #endif 2163 2164 s = splbio(); 2165 2166 if (ecb->flags & ECB_ABORT) { 2167 /* abort timed out */ 2168 printf(" AGAIN\n"); 2169 2170 ncr53c9x_init(sc, 1); 2171 } else { 2172 /* abort the operation that has timed out */ 2173 printf("\n"); 2174 xs->error = XS_TIMEOUT; 2175 ncr53c9x_abort(sc, ecb); 2176 2177 /* Disable sync mode if stuck in a data phase */ 2178 if (ecb == sc->sc_nexus && 2179 (ti->flags & T_SYNCMODE) != 0 && 2180 (sc->sc_phase & (MSGI|CDI)) == 0) { 2181 scsi_print_addr(sc_link); 2182 printf("sync negotiation disabled\n"); 2183 sc->sc_cfflags |= (1<<(sc_link->scsipi_scsi.target+8)); 2184 } 2185 } 2186 2187 splx(s); 2188 } 2189
Indexes created Mon Sep 29 21:09:56 GMT 2025