ncr53c9x.c revision 1.36.2.1
1 /* $NetBSD: ncr53c9x.c,v 1.36.2.1 1999/10/19 17:47:40 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1994 Peter Galbavy 41 * Copyright (c) 1995 Paul Kranenburg 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/malloc.h> 88 #include <sys/proc.h> 89 #include <sys/user.h> 90 #include <sys/queue.h> 91 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsiconf.h> 95 #include <dev/scsipi/scsi_message.h> 96 97 #include <machine/cpu.h> 98 99 #include <dev/ic/ncr53c9xreg.h> 100 #include <dev/ic/ncr53c9xvar.h> 101 102 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 103 104 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 105 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 106 struct ncr53c9x_ecb *)); 107 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 108 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 109 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 110 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 111 struct scsipi_xfer *, int)); 112 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 113 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 114 struct ncr53c9x_ecb *)); 115 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 116 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 117 /*static*/ void ncr53c9x_timeout __P((void *arg)); 118 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 119 struct ncr53c9x_ecb *)); 120 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 121 struct ncr53c9x_ecb *)); 122 123 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 124 struct ncr53c9x_ecb *)); 125 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 126 struct ncr53c9x_ecb *, int)); 127 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 128 129 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 130 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 131 struct ncr53c9x_tinfo *)); 132 133 /* 134 * Names for the NCR53c9x variants, correspnding to the variant tags 135 * in ncr53c9xvar.h. 136 */ 137 const char *ncr53c9x_variant_names[] = { 138 "ESP100", 139 "ESP100A", 140 "ESP200", 141 "NCR53C94", 142 "NCR53C96", 143 "ESP406", 144 "FAS408", 145 "FAS216", 146 "AM53C974", 147 }; 148 149 /* 150 * Attach this instance, and then all the sub-devices 151 */ 152 void 153 ncr53c9x_attach(sc) 154 struct ncr53c9x_softc *sc; 155 { 156 struct scsipi_adapter *adapt = &sc->sc_adapter; 157 struct scsipi_channel *chan = &sc->sc_channel; 158 159 /* 160 * Allocate SCSI message buffers. 161 * Front-ends can override allocation to avoid alignment 162 * handling in the DMA engines. Note that that ncr53c9x_msgout() 163 * can request a 1 byte DMA transfer. 164 */ 165 if (sc->sc_omess == NULL) 166 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 167 168 if (sc->sc_imess == NULL) 169 sc->sc_imess = malloc(NCR_MAX_MSG_LEN+1, M_DEVBUF, M_NOWAIT); 170 171 if (sc->sc_omess == NULL || sc->sc_imess == NULL) { 172 printf("out of memory\n"); 173 return; 174 } 175 176 /* 177 * Note, the front-end has set us up to print the chip variation. 178 */ 179 if (sc->sc_rev >= NCR_VARIANT_MAX) { 180 printf("\n%s: unknown variant %d, devices not attached\n", 181 sc->sc_dev.dv_xname, sc->sc_rev); 182 return; 183 } 184 185 printf(": %s, %dMHz, SCSI ID %d\n", 186 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 187 188 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 189 190 /* The value *must not* be == 1. Make it 2 */ 191 if (sc->sc_ccf == 1) 192 sc->sc_ccf = 2; 193 194 /* 195 * The recommended timeout is 250ms. This register is loaded 196 * with a value calculated as follows, from the docs: 197 * 198 * (timout period) x (CLK frequency) 199 * reg = ------------------------------------- 200 * 8192 x (Clock Conversion Factor) 201 * 202 * Since CCF has a linear relation to CLK, this generally computes 203 * to the constant of 153. 204 */ 205 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 206 207 /* CCF register only has 3 bits; 0 is actually 8 */ 208 sc->sc_ccf &= 7; 209 210 /* Reset state & bus */ 211 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 212 sc->sc_state = 0; 213 ncr53c9x_init(sc, 1); 214 215 /* 216 * Fill in the scsipi_adapter. 217 */ 218 adapt->adapt_dev = &sc->sc_dev; 219 adapt->adapt_nchannels = 1; 220 adapt->adapt_openings = 8; 221 adapt->adapt_max_periph = 1; 222 /* adapt_request initialized by front-end */ 223 /* adapt_minphys initialized by front-end */ 224 225 /* 226 * Fill in the scsipi_channel. 227 */ 228 memset(chan, 0, sizeof(*chan)); 229 chan->chan_adapter = adapt; 230 chan->chan_bustype = &scsi_bustype; 231 chan->chan_channel = 0; 232 chan->chan_ntargets = 8; 233 chan->chan_nluns = 8; 234 chan->chan_id = sc->sc_id; 235 236 /* 237 * Enable interupts from the SCSI core 238 */ 239 if ((sc->sc_rev == NCR_VARIANT_ESP406) || 240 (sc->sc_rev == NCR_VARIANT_FAS408)) { 241 NCR_PIOREGS(sc); 242 NCR_WRITE_REG(sc, NCR_CFG5, NCRCFG5_SINT | 243 NCR_READ_REG(sc, NCR_CFG5)); 244 NCR_SCSIREGS(sc); 245 } 246 247 /* 248 * Now try to attach all the sub-devices. 249 */ 250 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 251 } 252 253 /* 254 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus, 255 * only this controller, but kills any on-going commands, and also stops 256 * and resets the DMA. 257 * 258 * After reset, registers are loaded with the defaults from the attach 259 * routine above. 260 */ 261 void 262 ncr53c9x_reset(sc) 263 struct ncr53c9x_softc *sc; 264 { 265 266 /* reset DMA first */ 267 NCRDMA_RESET(sc); 268 269 /* reset SCSI chip */ 270 NCRCMD(sc, NCRCMD_RSTCHIP); 271 NCRCMD(sc, NCRCMD_NOP); 272 DELAY(500); 273 274 /* do these backwards, and fall through */ 275 switch (sc->sc_rev) { 276 case NCR_VARIANT_ESP406: 277 case NCR_VARIANT_FAS408: 278 NCR_SCSIREGS(sc); 279 case NCR_VARIANT_AM53C974: 280 case NCR_VARIANT_FAS216: 281 case NCR_VARIANT_NCR53C94: 282 case NCR_VARIANT_NCR53C96: 283 case NCR_VARIANT_ESP200: 284 sc->sc_features |= NCR_F_HASCFG3; 285 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 286 case NCR_VARIANT_ESP100A: 287 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 288 case NCR_VARIANT_ESP100: 289 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 290 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 291 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 292 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 293 break; 294 default: 295 printf("%s: unknown revision code, assuming ESP100\n", 296 sc->sc_dev.dv_xname); 297 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 298 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 299 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 300 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 301 } 302 303 if (sc->sc_rev == NCR_VARIANT_AM53C974) 304 NCR_WRITE_REG(sc, NCR_AMDCFG4, 305 NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE); 306 } 307 308 /* 309 * Reset the SCSI bus, but not the chip 310 */ 311 void 312 ncr53c9x_scsi_reset(sc) 313 struct ncr53c9x_softc *sc; 314 { 315 316 (*sc->sc_glue->gl_dma_stop)(sc); 317 318 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 319 NCRCMD(sc, NCRCMD_RSTSCSI); 320 } 321 322 /* 323 * Initialize ncr53c9x state machine 324 */ 325 void 326 ncr53c9x_init(sc, doreset) 327 struct ncr53c9x_softc *sc; 328 int doreset; 329 { 330 struct ncr53c9x_ecb *ecb; 331 int r; 332 333 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 334 335 if (sc->sc_state == 0) { 336 /* First time through; initialize. */ 337 TAILQ_INIT(&sc->ready_list); 338 TAILQ_INIT(&sc->nexus_list); 339 TAILQ_INIT(&sc->free_list); 340 sc->sc_nexus = NULL; 341 ecb = sc->sc_ecb; 342 bzero(ecb, sizeof(sc->sc_ecb)); 343 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 344 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 345 ecb++; 346 } 347 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 348 } else { 349 /* Cancel any active commands. */ 350 sc->sc_state = NCR_CLEANING; 351 if ((ecb = sc->sc_nexus) != NULL) { 352 ecb->xs->error = XS_TIMEOUT; 353 ncr53c9x_done(sc, ecb); 354 } 355 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 356 ecb->xs->error = XS_TIMEOUT; 357 ncr53c9x_done(sc, ecb); 358 } 359 } 360 361 /* 362 * reset the chip to a known state 363 */ 364 ncr53c9x_reset(sc); 365 366 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 367 for (r = 0; r < 8; r++) { 368 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 369 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 370 371 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8)))) 372 ? T_NEGOTIATE : 0) | 373 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) | 374 T_NEED_TO_RESET; 375 ti->period = sc->sc_minsync; 376 ti->offset = 0; 377 } 378 379 if (doreset) { 380 sc->sc_state = NCR_SBR; 381 NCRCMD(sc, NCRCMD_RSTSCSI); 382 } else { 383 sc->sc_state = NCR_IDLE; 384 ncr53c9x_sched(sc); 385 } 386 } 387 388 /* 389 * Read the NCR registers, and save their contents for later use. 390 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 391 * NCR_INTR - so make sure it is the last read. 392 * 393 * I think that (from reading the docs) most bits in these registers 394 * only make sense when he DMA CSR has an interrupt showing. Call only 395 * if an interrupt is pending. 396 */ 397 __inline__ void 398 ncr53c9x_readregs(sc) 399 struct ncr53c9x_softc *sc; 400 { 401 402 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 403 /* Only the stepo bits are of interest */ 404 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 405 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 406 407 if (sc->sc_glue->gl_clear_latched_intr != NULL) 408 (*sc->sc_glue->gl_clear_latched_intr)(sc); 409 410 /* 411 * Determine the SCSI bus phase, return either a real SCSI bus phase 412 * or some pseudo phase we use to detect certain exceptions. 413 */ 414 415 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 416 ? /* Disconnected */ BUSFREE_PHASE 417 : sc->sc_espstat & NCRSTAT_PHASE; 418 419 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 420 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 421 } 422 423 /* 424 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 425 */ 426 static inline int 427 ncr53c9x_stp2cpb(sc, period) 428 struct ncr53c9x_softc *sc; 429 int period; 430 { 431 int v; 432 v = (sc->sc_freq * period) / 250; 433 if (ncr53c9x_cpb2stp(sc, v) < period) 434 /* Correct round-down error */ 435 v++; 436 return (v); 437 } 438 439 static inline void 440 ncr53c9x_setsync(sc, ti) 441 struct ncr53c9x_softc *sc; 442 struct ncr53c9x_tinfo *ti; 443 { 444 u_char syncoff, synctp, cfg3 = sc->sc_cfg3; 445 446 if (ti->flags & T_SYNCMODE) { 447 syncoff = ti->offset; 448 synctp = ncr53c9x_stp2cpb(sc, ti->period); 449 if (sc->sc_features & NCR_F_FASTSCSI) { 450 /* 451 * If the period is 200ns or less (ti->period <= 50), 452 * put the chip in Fast SCSI mode. 453 */ 454 if (ti->period <= 50) 455 /* 456 * There are (at least) 4 variations of the 457 * configuration 3 register. The drive attach 458 * routine sets the appropriate bit to put the 459 * chip into Fast SCSI mode so that it doesn't 460 * have to be figured out here each time. 461 */ 462 cfg3 |= sc->sc_cfg3_fscsi; 463 } 464 465 /* 466 * Am53c974 requires different SYNCTP values when the 467 * FSCSI bit is off. 468 */ 469 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 470 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 471 synctp--; 472 } else { 473 syncoff = 0; 474 synctp = 0; 475 } 476 477 if (sc->sc_features & NCR_F_HASCFG3) 478 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 479 480 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 481 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 482 } 483 484 int ncr53c9x_dmaselect = 0; 485 /* 486 * Send a command to a target, set the driver state to NCR_SELECTING 487 * and let the caller take care of the rest. 488 * 489 * Keeping this as a function allows me to say that this may be done 490 * by DMA instead of programmed I/O soon. 491 */ 492 void 493 ncr53c9x_select(sc, ecb) 494 struct ncr53c9x_softc *sc; 495 struct ncr53c9x_ecb *ecb; 496 { 497 struct scsipi_periph *periph = ecb->xs->xs_periph; 498 int target = periph->periph_target; 499 int lun = periph->periph_lun; 500 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 501 int tiflags = ti->flags; 502 u_char *cmd; 503 int clen; 504 505 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 506 target, lun, ecb->cmd.cmd.opcode)); 507 508 sc->sc_state = NCR_SELECTING; 509 510 /* 511 * Schedule the timeout now, the first time we will go away 512 * expecting to come back due to an interrupt, because it is 513 * always possible that the interrupt may never happen. 514 */ 515 if ((ecb->xs->xs_control & XS_CTL_POLL) == 0) 516 timeout(ncr53c9x_timeout, ecb, 517 (ecb->timeout * hz) / 1000); 518 519 /* 520 * The docs say the target register is never reset, and I 521 * can't think of a better place to set it 522 */ 523 NCR_WRITE_REG(sc, NCR_SELID, target); 524 ncr53c9x_setsync(sc, ti); 525 526 if (ncr53c9x_dmaselect && (tiflags & T_NEGOTIATE) == 0) { 527 size_t dmasize; 528 529 ecb->cmd.id = 530 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1); 531 532 533 /* setup DMA transfer for command */ 534 dmasize = clen = ecb->clen + 1; 535 sc->sc_cmdlen = clen; 536 sc->sc_cmdp = (caddr_t)&ecb->cmd; 537 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 538 539 /* Program the SCSI counter */ 540 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 541 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 542 if (sc->sc_cfg2 & NCRCFG2_FE) { 543 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 544 } 545 546 /* load the count in */ 547 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 548 549 /* And get the targets attention */ 550 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 551 NCRDMA_GO(sc); 552 return; 553 } 554 555 /* 556 * Who am I. This is where we tell the target that we are 557 * happy for it to disconnect etc. 558 */ 559 NCR_WRITE_REG(sc, NCR_FIFO, 560 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1)); 561 562 if (ti->flags & T_NEGOTIATE) { 563 /* Arbitrate, select and stop after IDENTIFY message */ 564 NCRCMD(sc, NCRCMD_SELATNS); 565 return; 566 } 567 568 /* Now the command into the FIFO */ 569 cmd = (u_char *)&ecb->cmd.cmd; 570 clen = ecb->clen; 571 while (clen--) 572 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 573 574 /* And get the targets attention */ 575 NCRCMD(sc, NCRCMD_SELATN); 576 } 577 578 void 579 ncr53c9x_free_ecb(sc, ecb, flags) 580 struct ncr53c9x_softc *sc; 581 struct ncr53c9x_ecb *ecb; 582 int flags; 583 { 584 int s; 585 586 s = splbio(); 587 588 ecb->flags = 0; 589 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 590 591 /* 592 * If there were none, wake anybody waiting for one to come free, 593 * starting with queued entries. 594 */ 595 if (ecb->chain.tqe_next == 0) 596 wakeup(&sc->free_list); 597 598 splx(s); 599 } 600 601 struct ncr53c9x_ecb * 602 ncr53c9x_get_ecb(sc, flags) 603 struct ncr53c9x_softc *sc; 604 int flags; 605 { 606 struct ncr53c9x_ecb *ecb; 607 int s; 608 609 s = splbio(); 610 611 while ((ecb = sc->free_list.tqh_first) == NULL && 612 (flags & XS_CTL_NOSLEEP) == 0) 613 tsleep(&sc->free_list, PRIBIO, "especb", 0); 614 if (ecb) { 615 TAILQ_REMOVE(&sc->free_list, ecb, chain); 616 ecb->flags |= ECB_ALLOC; 617 } 618 619 splx(s); 620 return (ecb); 621 } 622 623 /* 624 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 625 */ 626 627 /* 628 * Start a SCSI-command 629 * This function is called by the higher level SCSI-driver to queue/run 630 * SCSI-commands. 631 */ 632 void 633 ncr53c9x_scsipi_request(chan, req, arg) 634 struct scsipi_channel *chan; 635 scsipi_adapter_req_t req; 636 void *arg; 637 { 638 struct scsipi_xfer *xs; 639 struct scsipi_periph *periph; 640 struct ncr53c9x_softc *sc = (void *)chan->chan_adapter->adapt_dev; 641 struct ncr53c9x_ecb *ecb; 642 int s, flags; 643 644 NCR_TRACE(("[ncr53c9x_scsipi_request] ")); 645 646 switch (req) { 647 case ADAPTER_REQ_RUN_XFER: 648 xs = arg; 649 periph = xs->xs_periph; 650 flags = xs->xs_control; 651 652 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 653 periph->periph_target)); 654 655 /* Get an ECB to use. */ 656 ecb = ncr53c9x_get_ecb(sc, flags); 657 #ifdef DIAGNOSTIC 658 /* 659 * This should never happen as we track resources 660 * in the mid-layer. 661 */ 662 if (ecb == NULL) { 663 scsipi_printaddr(periph); 664 printf("unable to allocate ecb\n"); 665 panic("ncr53c9x_scsipi_request"); 666 } 667 #endif 668 669 /* Initialize ecb */ 670 ecb->xs = xs; 671 ecb->timeout = xs->timeout; 672 673 if (flags & XS_CTL_RESET) { 674 ecb->flags |= ECB_RESET; 675 ecb->clen = 0; 676 ecb->dleft = 0; 677 } else { 678 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 679 ecb->clen = xs->cmdlen; 680 ecb->daddr = xs->data; 681 ecb->dleft = xs->datalen; 682 } 683 ecb->stat = 0; 684 685 s = splbio(); 686 687 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 688 if (sc->sc_state == NCR_IDLE) 689 ncr53c9x_sched(sc); 690 691 splx(s); 692 693 if ((flags & XS_CTL_POLL) == 0) 694 return; 695 696 /* Not allowed to use interrupts, use polling instead */ 697 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 698 ncr53c9x_timeout(ecb); 699 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 700 ncr53c9x_timeout(ecb); 701 } 702 return; 703 704 case ADAPTER_REQ_GROW_RESOURCES: 705 /* XXX Not supported. */ 706 return; 707 708 case ADAPTER_REQ_SET_XFER_MODE: 709 { 710 struct ncr53c9x_tinfo *ti; 711 periph = arg; 712 ti = &sc->sc_tinfo[periph->periph_target]; 713 if ((periph->periph_cap & PERIPH_CAP_SYNC) != 0 && 714 sc->sc_minsync != 0 && 715 (sc->sc_cfflags & 716 (1 << (periph->periph_target + 8))) == 0) { 717 ti->flags |= T_NEGOTIATE; 718 ti->period = sc->sc_minsync; 719 ti->offset = 0; 720 } 721 return; 722 } 723 724 case ADAPTER_REQ_GET_XFER_MODE: 725 { 726 struct ncr53c9x_tinfo *ti; 727 periph = arg; 728 ti = &sc->sc_tinfo[periph->periph_target]; 729 730 periph->periph_mode = 0; 731 periph->periph_period = 0; 732 periph->periph_offset = 0; 733 734 if (ti->flags & T_SYNCMODE) { 735 periph->periph_mode |= PERIPH_CAP_SYNC; 736 periph->periph_period = ti->period; 737 periph->periph_offset = ti->offset; 738 } 739 periph->periph_flags |= PERIPH_MODE_VALID; 740 return; 741 } 742 } 743 } 744 745 /* 746 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 747 */ 748 int 749 ncr53c9x_poll(sc, xs, count) 750 struct ncr53c9x_softc *sc; 751 struct scsipi_xfer *xs; 752 int count; 753 { 754 755 NCR_TRACE(("[ncr53c9x_poll] ")); 756 while (count) { 757 if (NCRDMA_ISINTR(sc)) { 758 ncr53c9x_intr(sc); 759 } 760 #if alternatively 761 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 762 ncr53c9x_intr(sc); 763 #endif 764 if ((xs->xs_status & XS_STS_DONE) != 0) 765 return (0); 766 if (sc->sc_state == NCR_IDLE) { 767 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 768 ncr53c9x_sched(sc); 769 } 770 DELAY(1000); 771 count--; 772 } 773 return (1); 774 } 775 776 777 /* 778 * LOW LEVEL SCSI UTILITIES 779 */ 780 781 /* 782 * Schedule a scsi operation. This has now been pulled out of the interrupt 783 * handler so that we may call it from ncr53c9x_scsipi_request and 784 * ncr53c9x_done. This may save us an unecessary interrupt just to get 785 * things going. Should only be called when state == NCR_IDLE and at bio pl. 786 */ 787 void 788 ncr53c9x_sched(sc) 789 struct ncr53c9x_softc *sc; 790 { 791 struct ncr53c9x_ecb *ecb; 792 struct scsipi_periph *periph; 793 struct ncr53c9x_tinfo *ti; 794 795 NCR_TRACE(("[ncr53c9x_sched] ")); 796 if (sc->sc_state != NCR_IDLE) 797 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 798 799 /* 800 * Find first ecb in ready queue that is for a target/lunit 801 * combinations that is not busy. 802 */ 803 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 804 periph = ecb->xs->xs_periph; 805 ti = &sc->sc_tinfo[periph->periph_target]; 806 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 807 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 808 sc->sc_nexus = ecb; 809 ncr53c9x_select(sc, ecb); 810 break; 811 } else 812 NCR_MISC(("%d:%d busy\n", 813 periph->periph_target, 814 periph->periph_lun)); 815 } 816 } 817 818 void 819 ncr53c9x_sense(sc, ecb) 820 struct ncr53c9x_softc *sc; 821 struct ncr53c9x_ecb *ecb; 822 { 823 struct scsipi_xfer *xs = ecb->xs; 824 struct scsipi_periph *periph = xs->xs_periph; 825 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 826 struct scsipi_sense *ss = (void *)&ecb->cmd.cmd; 827 828 NCR_MISC(("requesting sense ")); 829 /* Next, setup a request sense command block */ 830 bzero(ss, sizeof(*ss)); 831 ss->opcode = REQUEST_SENSE; 832 ss->byte2 = periph->periph_lun << 5; 833 ss->length = sizeof(struct scsipi_sense_data); 834 ecb->clen = sizeof(*ss); 835 ecb->daddr = (char *)&xs->sense.scsi_sense; 836 ecb->dleft = sizeof(struct scsipi_sense_data); 837 ecb->flags |= ECB_SENSE; 838 ecb->timeout = NCR_SENSE_TIMEOUT; 839 ti->senses++; 840 if (ecb->flags & ECB_NEXUS) 841 ti->lubusy &= ~(1 << periph->periph_lun); 842 if (ecb == sc->sc_nexus) { 843 ecb->flags &= ~ECB_NEXUS; 844 ncr53c9x_select(sc, ecb); 845 } else { 846 ncr53c9x_dequeue(sc, ecb); 847 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 848 if (sc->sc_state == NCR_IDLE) 849 ncr53c9x_sched(sc); 850 } 851 } 852 853 /* 854 * POST PROCESSING OF SCSI_CMD (usually current) 855 */ 856 void 857 ncr53c9x_done(sc, ecb) 858 struct ncr53c9x_softc *sc; 859 struct ncr53c9x_ecb *ecb; 860 { 861 struct scsipi_xfer *xs = ecb->xs; 862 struct scsipi_periph *periph = xs->xs_periph; 863 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 864 865 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 866 867 untimeout(ncr53c9x_timeout, ecb); 868 869 /* 870 * Now, if we've come here with no error code, i.e. we've kept the 871 * initial XS_NOERROR, and the status code signals that we should 872 * check sense, we'll need to set up a request sense cmd block and 873 * push the command back into the ready queue *before* any other 874 * commands for this target/lunit, else we lose the sense info. 875 * We don't support chk sense conditions for the request sense cmd. 876 */ 877 if (xs->error == XS_NOERROR) { 878 xs->status = ecb->stat; 879 if ((ecb->flags & ECB_ABORT) != 0) { 880 xs->error = XS_TIMEOUT; 881 } else if ((ecb->flags & ECB_SENSE) != 0) { 882 xs->error = XS_SENSE; 883 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 884 /* First, save the return values */ 885 xs->resid = ecb->dleft; 886 ncr53c9x_sense(sc, ecb); 887 return; 888 } else { 889 xs->resid = ecb->dleft; 890 } 891 } 892 893 #ifdef NCR53C9X_DEBUG 894 if (ncr53c9x_debug & NCR_SHOWMISC) { 895 if (xs->resid != 0) 896 printf("resid=%d ", xs->resid); 897 if (xs->error == XS_SENSE) 898 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 899 else 900 printf("error=%d\n", xs->error); 901 } 902 #endif 903 904 /* 905 * Remove the ECB from whatever queue it's on. 906 */ 907 if (ecb->flags & ECB_NEXUS) 908 ti->lubusy &= ~(1 << periph->periph_lun); 909 if (ecb == sc->sc_nexus) { 910 sc->sc_nexus = NULL; 911 if (sc->sc_state != NCR_CLEANING) { 912 sc->sc_state = NCR_IDLE; 913 ncr53c9x_sched(sc); 914 } 915 } else 916 ncr53c9x_dequeue(sc, ecb); 917 918 ncr53c9x_free_ecb(sc, ecb, xs->xs_control); 919 ti->cmds++; 920 scsipi_done(xs); 921 } 922 923 void 924 ncr53c9x_dequeue(sc, ecb) 925 struct ncr53c9x_softc *sc; 926 struct ncr53c9x_ecb *ecb; 927 { 928 929 if (ecb->flags & ECB_NEXUS) { 930 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 931 ecb->flags &= ~ECB_NEXUS; 932 } else { 933 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 934 } 935 } 936 937 /* 938 * INTERRUPT/PROTOCOL ENGINE 939 */ 940 941 /* 942 * Schedule an outgoing message by prioritizing it, and asserting 943 * attention on the bus. We can only do this when we are the initiator 944 * else there will be an illegal command interrupt. 945 */ 946 #define ncr53c9x_sched_msgout(m) \ 947 do { \ 948 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 949 NCRCMD(sc, NCRCMD_SETATN); \ 950 sc->sc_flags |= NCR_ATN; \ 951 sc->sc_msgpriq |= (m); \ 952 } while (0) 953 954 int 955 ncr53c9x_reselect(sc, message) 956 struct ncr53c9x_softc *sc; 957 int message; 958 { 959 u_char selid, target, lun; 960 struct ncr53c9x_ecb *ecb; 961 struct scsipi_periph *periph; 962 struct ncr53c9x_tinfo *ti; 963 964 /* 965 * The SCSI chip made a snapshot of the data bus while the reselection 966 * was being negotiated. This enables us to determine which target did 967 * the reselect. 968 */ 969 selid = sc->sc_selid & ~(1 << sc->sc_id); 970 if (selid & (selid - 1)) { 971 printf("%s: reselect with invalid selid %02x;" 972 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 973 goto reset; 974 } 975 976 /* 977 * Search wait queue for disconnected cmd 978 * The list should be short, so I haven't bothered with 979 * any more sophisticated structures than a simple 980 * singly linked list. 981 */ 982 target = ffs(selid) - 1; 983 lun = message & 0x07; 984 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 985 ecb = ecb->chain.tqe_next) { 986 periph = ecb->xs->xs_periph; 987 if (periph->periph_target == target && 988 periph->periph_lun == lun) 989 break; 990 } 991 if (ecb == NULL) { 992 printf("%s: reselect from target %d lun %d with no nexus;" 993 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 994 goto abort; 995 } 996 997 /* Make this nexus active again. */ 998 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 999 sc->sc_state = NCR_CONNECTED; 1000 sc->sc_nexus = ecb; 1001 ti = &sc->sc_tinfo[target]; 1002 #ifdef NCR53C9X_DEBUG 1003 if ((ti->lubusy & (1 << lun)) == 0) { 1004 printf("%s: reselect: target %d, lun %d: should be busy\n", 1005 sc->sc_dev.dv_xname, target, lun); 1006 ti->lubusy |= (1 << lun); 1007 } 1008 #endif 1009 ncr53c9x_setsync(sc, ti); 1010 1011 if (ecb->flags & ECB_RESET) 1012 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1013 else if (ecb->flags & ECB_ABORT) 1014 ncr53c9x_sched_msgout(SEND_ABORT); 1015 1016 /* Do an implicit RESTORE POINTERS. */ 1017 sc->sc_dp = ecb->daddr; 1018 sc->sc_dleft = ecb->dleft; 1019 1020 return (0); 1021 1022 reset: 1023 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1024 return (1); 1025 1026 abort: 1027 ncr53c9x_sched_msgout(SEND_ABORT); 1028 return (1); 1029 } 1030 1031 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1032 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1033 #define ISEXTMSG(m) ((m) == 1) 1034 1035 /* 1036 * Get an incoming message as initiator. 1037 * 1038 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1039 * byte in the FIFO 1040 */ 1041 void 1042 ncr53c9x_msgin(sc) 1043 register struct ncr53c9x_softc *sc; 1044 { 1045 register int v; 1046 1047 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1048 1049 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 1050 printf("%s: msgin: no msg byte available\n", 1051 sc->sc_dev.dv_xname); 1052 return; 1053 } 1054 1055 /* 1056 * Prepare for a new message. A message should (according 1057 * to the SCSI standard) be transmitted in one single 1058 * MESSAGE_IN_PHASE. If we have been in some other phase, 1059 * then this is a new message. 1060 */ 1061 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1062 sc->sc_flags &= ~NCR_DROP_MSGI; 1063 sc->sc_imlen = 0; 1064 } 1065 1066 v = NCR_READ_REG(sc, NCR_FIFO); 1067 NCR_MISC(("<msgbyte:0x%02x>", v)); 1068 1069 #if 0 1070 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 1071 /* 1072 * Which target is reselecting us? (The ID bit really) 1073 */ 1074 sc->sc_selid = v; 1075 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1076 return; 1077 } 1078 #endif 1079 1080 sc->sc_imess[sc->sc_imlen] = v; 1081 1082 /* 1083 * If we're going to reject the message, don't bother storing 1084 * the incoming bytes. But still, we need to ACK them. 1085 */ 1086 1087 if ((sc->sc_flags & NCR_DROP_MSGI)) { 1088 NCRCMD(sc, NCRCMD_MSGOK); 1089 printf("<dropping msg byte %x>", 1090 sc->sc_imess[sc->sc_imlen]); 1091 return; 1092 } 1093 1094 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1095 ncr53c9x_sched_msgout(SEND_REJECT); 1096 sc->sc_flags |= NCR_DROP_MSGI; 1097 } else { 1098 sc->sc_imlen++; 1099 /* 1100 * This testing is suboptimal, but most 1101 * messages will be of the one byte variety, so 1102 * it should not effect performance 1103 * significantly. 1104 */ 1105 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1106 goto gotit; 1107 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1108 goto gotit; 1109 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1110 sc->sc_imlen == sc->sc_imess[1] + 2) 1111 goto gotit; 1112 } 1113 /* Ack what we have so far */ 1114 NCRCMD(sc, NCRCMD_MSGOK); 1115 return; 1116 1117 gotit: 1118 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1119 /* 1120 * Now we should have a complete message (1 byte, 2 byte 1121 * and moderately long extended messages). We only handle 1122 * extended messages which total length is shorter than 1123 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1124 */ 1125 switch (sc->sc_state) { 1126 struct ncr53c9x_ecb *ecb; 1127 struct ncr53c9x_tinfo *ti; 1128 1129 case NCR_CONNECTED: 1130 ecb = sc->sc_nexus; 1131 ti = &sc->sc_tinfo[ecb->xs->xs_periph->periph_target]; 1132 1133 switch (sc->sc_imess[0]) { 1134 case MSG_CMDCOMPLETE: 1135 NCR_MSGS(("cmdcomplete ")); 1136 if (sc->sc_dleft < 0) { 1137 scsipi_printaddr(ecb->xs->xs_periph); 1138 printf("got %ld extra bytes\n", 1139 -(long)sc->sc_dleft); 1140 sc->sc_dleft = 0; 1141 } 1142 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1143 ? 0 1144 : sc->sc_dleft; 1145 if ((ecb->flags & ECB_SENSE) == 0) 1146 ecb->xs->resid = ecb->dleft; 1147 sc->sc_state = NCR_CMDCOMPLETE; 1148 break; 1149 1150 case MSG_MESSAGE_REJECT: 1151 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1152 switch (sc->sc_msgout) { 1153 case SEND_SDTR: 1154 sc->sc_flags &= ~NCR_SYNCHNEGO; 1155 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1156 ncr53c9x_setsync(sc, ti); 1157 break; 1158 case SEND_INIT_DET_ERR: 1159 goto abort; 1160 } 1161 break; 1162 1163 case MSG_NOOP: 1164 NCR_MSGS(("noop ")); 1165 break; 1166 1167 case MSG_DISCONNECT: 1168 NCR_MSGS(("disconnect ")); 1169 ti->dconns++; 1170 sc->sc_state = NCR_DISCONNECT; 1171 1172 /* 1173 * Mark the fact that all bytes have moved. The 1174 * target may not bother to do a SAVE POINTERS 1175 * at this stage. This flag will set the residual 1176 * count to zero on MSG COMPLETE. 1177 */ 1178 if (sc->sc_dleft == 0) 1179 ecb->flags |= ECB_TENTATIVE_DONE; 1180 1181 break; 1182 1183 case MSG_SAVEDATAPOINTER: 1184 NCR_MSGS(("save datapointer ")); 1185 ecb->daddr = sc->sc_dp; 1186 ecb->dleft = sc->sc_dleft; 1187 break; 1188 1189 case MSG_RESTOREPOINTERS: 1190 NCR_MSGS(("restore datapointer ")); 1191 sc->sc_dp = ecb->daddr; 1192 sc->sc_dleft = ecb->dleft; 1193 break; 1194 1195 case MSG_EXTENDED: 1196 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1197 switch (sc->sc_imess[2]) { 1198 case MSG_EXT_SDTR: 1199 NCR_MSGS(("SDTR period %d, offset %d ", 1200 sc->sc_imess[3], sc->sc_imess[4])); 1201 if (sc->sc_imess[1] != 3) 1202 goto reject; 1203 ti->period = sc->sc_imess[3]; 1204 ti->offset = sc->sc_imess[4]; 1205 ti->flags &= ~T_NEGOTIATE; 1206 if (sc->sc_minsync == 0 || 1207 ti->offset == 0 || 1208 ti->period > 124) { 1209 #if 0 1210 #ifdef NCR53C9X_DEBUG 1211 scsipi_printaddr(ecb->xs->xs_periph); 1212 printf("async mode\n"); 1213 #endif 1214 #endif 1215 if ((sc->sc_flags&NCR_SYNCHNEGO) 1216 == 0) { 1217 /* 1218 * target initiated negotiation 1219 */ 1220 ti->offset = 0; 1221 ti->flags &= ~T_SYNCMODE; 1222 ncr53c9x_sched_msgout( 1223 SEND_SDTR); 1224 } else { 1225 /* we are async */ 1226 ti->flags &= ~T_SYNCMODE; 1227 } 1228 } else { 1229 #if 0 1230 int r = 250/ti->period; 1231 int s = (100*250)/ti->period - 100*r; 1232 #endif 1233 int p; 1234 1235 p = ncr53c9x_stp2cpb(sc, ti->period); 1236 ti->period = ncr53c9x_cpb2stp(sc, p); 1237 #if 0 1238 #ifdef NCR53C9X_DEBUG 1239 scsipi_printaddr(ecb->xs->xs_periph); 1240 printf("max sync rate %d.%02dMb/s\n", 1241 r, s); 1242 #endif 1243 #endif 1244 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) { 1245 /* 1246 * target initiated negotiation 1247 */ 1248 if (ti->period < 1249 sc->sc_minsync) 1250 ti->period = 1251 sc->sc_minsync; 1252 if (ti->offset > 15) 1253 ti->offset = 15; 1254 ti->flags &= ~T_SYNCMODE; 1255 ncr53c9x_sched_msgout( 1256 SEND_SDTR); 1257 } else { 1258 /* we are sync */ 1259 ti->flags |= T_SYNCMODE; 1260 } 1261 } 1262 sc->sc_flags &= ~NCR_SYNCHNEGO; 1263 ncr53c9x_setsync(sc, ti); 1264 break; 1265 1266 default: 1267 scsipi_printaddr(ecb->xs->xs_periph); 1268 printf("unrecognized MESSAGE EXTENDED;" 1269 " sending REJECT\n"); 1270 goto reject; 1271 } 1272 break; 1273 1274 default: 1275 NCR_MSGS(("ident ")); 1276 scsipi_printaddr(ecb->xs->xs_periph); 1277 printf("unrecognized MESSAGE; sending REJECT\n"); 1278 reject: 1279 ncr53c9x_sched_msgout(SEND_REJECT); 1280 break; 1281 } 1282 break; 1283 1284 case NCR_RESELECTED: 1285 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1286 printf("%s: reselect without IDENTIFY;" 1287 " sending DEVICE RESET\n", 1288 sc->sc_dev.dv_xname); 1289 goto reset; 1290 } 1291 1292 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1293 break; 1294 1295 default: 1296 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1297 sc->sc_dev.dv_xname); 1298 reset: 1299 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1300 break; 1301 1302 abort: 1303 ncr53c9x_sched_msgout(SEND_ABORT); 1304 break; 1305 } 1306 1307 /* Ack last message byte */ 1308 NCRCMD(sc, NCRCMD_MSGOK); 1309 1310 /* Done, reset message pointer. */ 1311 sc->sc_flags &= ~NCR_DROP_MSGI; 1312 sc->sc_imlen = 0; 1313 } 1314 1315 1316 /* 1317 * Send the highest priority, scheduled message 1318 */ 1319 void 1320 ncr53c9x_msgout(sc) 1321 register struct ncr53c9x_softc *sc; 1322 { 1323 struct ncr53c9x_tinfo *ti; 1324 struct ncr53c9x_ecb *ecb; 1325 size_t size; 1326 1327 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1328 sc->sc_msgpriq, sc->sc_prevphase)); 1329 1330 /* 1331 * XXX - the NCR_ATN flag is not in sync with the actual ATN 1332 * condition on the SCSI bus. The 53c9x chip 1333 * automatically turns off ATN before sending the 1334 * message byte. (see also the comment below in the 1335 * default case when picking out a message to send) 1336 */ 1337 if (sc->sc_flags & NCR_ATN) { 1338 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1339 new: 1340 NCRCMD(sc, NCRCMD_FLUSH); 1341 DELAY(1); 1342 sc->sc_msgoutq = 0; 1343 sc->sc_omlen = 0; 1344 } 1345 } else { 1346 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1347 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1348 goto new; 1349 } else { 1350 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1351 sc->sc_dev.dv_xname, __LINE__); 1352 } 1353 } 1354 1355 if (sc->sc_omlen == 0) { 1356 /* Pick up highest priority message */ 1357 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1358 sc->sc_msgoutq |= sc->sc_msgout; 1359 sc->sc_msgpriq &= ~sc->sc_msgout; 1360 sc->sc_omlen = 1; /* "Default" message len */ 1361 switch (sc->sc_msgout) { 1362 case SEND_SDTR: 1363 ecb = sc->sc_nexus; 1364 ti = &sc->sc_tinfo[ecb->xs->xs_periph->periph_target]; 1365 sc->sc_omess[0] = MSG_EXTENDED; 1366 sc->sc_omess[1] = 3; 1367 sc->sc_omess[2] = MSG_EXT_SDTR; 1368 sc->sc_omess[3] = ti->period; 1369 sc->sc_omess[4] = ti->offset; 1370 sc->sc_omlen = 5; 1371 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1372 ti->flags |= T_SYNCMODE; 1373 ncr53c9x_setsync(sc, ti); 1374 } 1375 break; 1376 case SEND_IDENTIFY: 1377 if (sc->sc_state != NCR_CONNECTED) { 1378 printf("%s at line %d: no nexus\n", 1379 sc->sc_dev.dv_xname, __LINE__); 1380 } 1381 ecb = sc->sc_nexus; 1382 sc->sc_omess[0] = 1383 MSG_IDENTIFY(ecb->xs->xs_periph->periph_lun, 0); 1384 break; 1385 case SEND_DEV_RESET: 1386 sc->sc_flags |= NCR_ABORTING; 1387 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1388 ecb = sc->sc_nexus; 1389 ti = &sc->sc_tinfo[ecb->xs->xs_periph->periph_target]; 1390 ti->flags &= ~T_SYNCMODE; 1391 ti->flags |= T_NEGOTIATE; 1392 break; 1393 case SEND_PARITY_ERROR: 1394 sc->sc_omess[0] = MSG_PARITY_ERROR; 1395 break; 1396 case SEND_ABORT: 1397 sc->sc_flags |= NCR_ABORTING; 1398 sc->sc_omess[0] = MSG_ABORT; 1399 break; 1400 case SEND_INIT_DET_ERR: 1401 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1402 break; 1403 case SEND_REJECT: 1404 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1405 break; 1406 default: 1407 /* 1408 * We normally do not get here, since the chip 1409 * automatically turns off ATN before the last 1410 * byte of a message is sent to the target. 1411 * However, if the target rejects our (multi-byte) 1412 * message early by switching to MSG IN phase 1413 * ATN remains on, so the target may return to 1414 * MSG OUT phase. If there are no scheduled messages 1415 * left we send a NO-OP. 1416 * 1417 * XXX - Note that this leaves no useful purpose for 1418 * the NCR_ATN flag. 1419 */ 1420 sc->sc_flags &= ~NCR_ATN; 1421 sc->sc_omess[0] = MSG_NOOP; 1422 break; 1423 } 1424 sc->sc_omp = sc->sc_omess; 1425 } 1426 1427 /* (re)send the message */ 1428 size = min(sc->sc_omlen, sc->sc_maxxfer); 1429 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1430 /* Program the SCSI counter */ 1431 NCR_WRITE_REG(sc, NCR_TCL, size); 1432 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1433 if (sc->sc_cfg2 & NCRCFG2_FE) { 1434 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1435 } 1436 /* Load the count in and start the message-out transfer */ 1437 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1438 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1439 NCRDMA_GO(sc); 1440 } 1441 1442 /* 1443 * This is the most critical part of the driver, and has to know 1444 * how to deal with *all* error conditions and phases from the SCSI 1445 * bus. If there are no errors and the DMA was active, then call the 1446 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1447 * and we can return from here without further processing. 1448 * 1449 * Most of this needs verifying. 1450 */ 1451 int sdebug = 0; 1452 int 1453 ncr53c9x_intr(sc) 1454 register struct ncr53c9x_softc *sc; 1455 { 1456 register struct ncr53c9x_ecb *ecb; 1457 register struct scsipi_periph *periph; 1458 struct ncr53c9x_tinfo *ti; 1459 size_t size; 1460 int nfifo; 1461 1462 NCR_TRACE(("[ncr53c9x_intr] ")); 1463 1464 if (!NCRDMA_ISINTR(sc)) 1465 return (0); 1466 1467 again: 1468 /* and what do the registers say... */ 1469 ncr53c9x_readregs(sc); 1470 1471 sc->sc_intrcnt.ev_count++; 1472 1473 /* 1474 * At the moment, only a SCSI Bus Reset or Illegal 1475 * Command are classed as errors. A disconnect is a 1476 * valid condition, and we let the code check is the 1477 * "NCR_BUSFREE_OK" flag was set before declaring it 1478 * and error. 1479 * 1480 * Also, the status register tells us about "Gross 1481 * Errors" and "Parity errors". Only the Gross Error 1482 * is really bad, and the parity errors are dealt 1483 * with later 1484 * 1485 * TODO 1486 * If there are too many parity error, go to slow 1487 * cable mode ? 1488 */ 1489 1490 /* SCSI Reset */ 1491 if (sc->sc_espintr & NCRINTR_SBR) { 1492 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1493 NCRCMD(sc, NCRCMD_FLUSH); 1494 DELAY(1); 1495 } 1496 if (sc->sc_state != NCR_SBR) { 1497 printf("%s: SCSI bus reset\n", 1498 sc->sc_dev.dv_xname); 1499 ncr53c9x_init(sc, 0); /* Restart everything */ 1500 return (1); 1501 } 1502 #if 0 1503 /*XXX*/ printf("<expected bus reset: " 1504 "[intr %x, stat %x, step %d]>\n", 1505 sc->sc_espintr, sc->sc_espstat, 1506 sc->sc_espstep); 1507 #endif 1508 if (sc->sc_nexus) 1509 panic("%s: nexus in reset state", 1510 sc->sc_dev.dv_xname); 1511 goto sched; 1512 } 1513 1514 ecb = sc->sc_nexus; 1515 1516 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1517 if (sc->sc_espintr & NCRINTR_ERR || 1518 sc->sc_espstat & NCRSTAT_GE) { 1519 1520 if (sc->sc_espstat & NCRSTAT_GE) { 1521 /* Gross Error; no target ? */ 1522 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1523 NCRCMD(sc, NCRCMD_FLUSH); 1524 DELAY(1); 1525 } 1526 if (sc->sc_state == NCR_CONNECTED || 1527 sc->sc_state == NCR_SELECTING) { 1528 ecb->xs->error = XS_TIMEOUT; 1529 ncr53c9x_done(sc, ecb); 1530 } 1531 return (1); 1532 } 1533 1534 if (sc->sc_espintr & NCRINTR_ILL) { 1535 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1536 /* 1537 * Eat away "Illegal command" interrupt 1538 * on a ESP100 caused by a re-selection 1539 * while we were trying to select 1540 * another target. 1541 */ 1542 #ifdef DEBUG 1543 printf("%s: ESP100 work-around activated\n", 1544 sc->sc_dev.dv_xname); 1545 #endif 1546 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1547 return (1); 1548 } 1549 /* illegal command, out of sync ? */ 1550 printf("%s: illegal command: 0x%x " 1551 "(state %d, phase %x, prevphase %x)\n", 1552 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1553 sc->sc_state, sc->sc_phase, 1554 sc->sc_prevphase); 1555 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1556 NCRCMD(sc, NCRCMD_FLUSH); 1557 DELAY(1); 1558 } 1559 ncr53c9x_init(sc, 1); /* Restart everything */ 1560 return (1); 1561 } 1562 } 1563 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1564 1565 /* 1566 * Call if DMA is active. 1567 * 1568 * If DMA_INTR returns true, then maybe go 'round the loop 1569 * again in case there is no more DMA queued, but a phase 1570 * change is expected. 1571 */ 1572 if (NCRDMA_ISACTIVE(sc)) { 1573 int r = NCRDMA_INTR(sc); 1574 if (r == -1) { 1575 printf("%s: DMA error; resetting\n", 1576 sc->sc_dev.dv_xname); 1577 ncr53c9x_init(sc, 1); 1578 } 1579 /* If DMA active here, then go back to work... */ 1580 if (NCRDMA_ISACTIVE(sc)) 1581 return (1); 1582 1583 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 1584 /* 1585 * DMA not completed. If we can not find a 1586 * acceptable explanation, print a diagnostic. 1587 */ 1588 if (sc->sc_state == NCR_SELECTING) 1589 /* 1590 * This can happen if we are reselected 1591 * while using DMA to select a target. 1592 */ 1593 /*void*/; 1594 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1595 /* 1596 * Our (multi-byte) message (eg SDTR) was 1597 * interrupted by the target to send 1598 * a MSG REJECT. 1599 * Print diagnostic if current phase 1600 * is not MESSAGE IN. 1601 */ 1602 if (sc->sc_phase != MESSAGE_IN_PHASE) 1603 printf("%s: !TC on MSG OUT" 1604 " [intr %x, stat %x, step %d]" 1605 " prevphase %x, resid %lx\n", 1606 sc->sc_dev.dv_xname, 1607 sc->sc_espintr, 1608 sc->sc_espstat, 1609 sc->sc_espstep, 1610 sc->sc_prevphase, 1611 (u_long)sc->sc_omlen); 1612 } else if (sc->sc_dleft == 0) { 1613 /* 1614 * The DMA operation was started for 1615 * a DATA transfer. Print a diagnostic 1616 * if the DMA counter and TC bit 1617 * appear to be out of sync. 1618 */ 1619 printf("%s: !TC on DATA XFER" 1620 " [intr %x, stat %x, step %d]" 1621 " prevphase %x, resid %x\n", 1622 sc->sc_dev.dv_xname, 1623 sc->sc_espintr, 1624 sc->sc_espstat, 1625 sc->sc_espstep, 1626 sc->sc_prevphase, 1627 ecb?ecb->dleft:-1); 1628 } 1629 } 1630 } 1631 1632 /* 1633 * Check for less serious errors. 1634 */ 1635 if (sc->sc_espstat & NCRSTAT_PE) { 1636 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1637 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1638 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1639 else 1640 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1641 } 1642 1643 if (sc->sc_espintr & NCRINTR_DIS) { 1644 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1645 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1646 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1647 NCRCMD(sc, NCRCMD_FLUSH); 1648 DELAY(1); 1649 } 1650 /* 1651 * This command must (apparently) be issued within 1652 * 250mS of a disconnect. So here you are... 1653 */ 1654 NCRCMD(sc, NCRCMD_ENSEL); 1655 1656 switch (sc->sc_state) { 1657 case NCR_RESELECTED: 1658 goto sched; 1659 1660 case NCR_SELECTING: 1661 ecb->xs->error = XS_SELTIMEOUT; 1662 goto finish; 1663 1664 case NCR_CONNECTED: 1665 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1666 #ifdef NCR53C9X_DEBUG 1667 if (ecb) 1668 scsipi_printaddr(ecb->xs->xs_periph); 1669 printf("sync nego not completed!\n"); 1670 #endif 1671 ti = &sc->sc_tinfo[ecb->xs->xs_periph->periph_target]; 1672 sc->sc_flags &= ~NCR_SYNCHNEGO; 1673 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1674 } 1675 1676 /* it may be OK to disconnect */ 1677 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1678 /* 1679 * Section 5.1.1 of the SCSI 2 spec 1680 * suggests issuing a REQUEST SENSE 1681 * following an unexpected disconnect. 1682 * Some devices go into a contingent 1683 * allegiance condition when 1684 * disconnecting, and this is necessary 1685 * to clean up their state. 1686 */ 1687 printf("%s: unexpected disconnect; ", 1688 sc->sc_dev.dv_xname); 1689 if (ecb->flags & ECB_SENSE) { 1690 printf("resetting\n"); 1691 goto reset; 1692 } 1693 printf("sending REQUEST SENSE\n"); 1694 untimeout(ncr53c9x_timeout, ecb); 1695 ncr53c9x_sense(sc, ecb); 1696 goto out; 1697 } 1698 1699 ecb->xs->error = XS_TIMEOUT; 1700 goto finish; 1701 1702 case NCR_DISCONNECT: 1703 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1704 sc->sc_nexus = NULL; 1705 goto sched; 1706 1707 case NCR_CMDCOMPLETE: 1708 goto finish; 1709 } 1710 } 1711 1712 switch (sc->sc_state) { 1713 1714 case NCR_SBR: 1715 printf("%s: waiting for SCSI Bus Reset to happen\n", 1716 sc->sc_dev.dv_xname); 1717 return (1); 1718 1719 case NCR_RESELECTED: 1720 /* 1721 * we must be continuing a message ? 1722 */ 1723 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1724 printf("%s: target didn't identify\n", 1725 sc->sc_dev.dv_xname); 1726 ncr53c9x_init(sc, 1); 1727 return (1); 1728 } 1729 printf("<<RESELECT CONT'd>>"); 1730 #if XXXX 1731 ncr53c9x_msgin(sc); 1732 if (sc->sc_state != NCR_CONNECTED) { 1733 /* IDENTIFY fail?! */ 1734 printf("%s: identify failed\n", 1735 sc->sc_dev.dv_xname); 1736 ncr53c9x_init(sc, 1); 1737 return (1); 1738 } 1739 #endif 1740 break; 1741 1742 case NCR_IDLE: 1743 case NCR_SELECTING: 1744 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1745 sc->sc_flags = 0; 1746 ecb = sc->sc_nexus; 1747 if (ecb != NULL && (ecb->flags & ECB_NEXUS)) { 1748 scsipi_printaddr(ecb->xs->xs_periph); 1749 printf("ECB_NEXUS while in state %x\n", sc->sc_state); 1750 } 1751 1752 if (sc->sc_espintr & NCRINTR_RESEL) { 1753 /* 1754 * If we're trying to select a 1755 * target ourselves, push our command 1756 * back into the ready list. 1757 */ 1758 if (sc->sc_state == NCR_SELECTING) { 1759 NCR_MISC(("backoff selector ")); 1760 untimeout(ncr53c9x_timeout, ecb); 1761 periph = ecb->xs->xs_periph; 1762 ti = &sc->sc_tinfo[periph->periph_target]; 1763 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1764 ecb = sc->sc_nexus = NULL; 1765 } 1766 sc->sc_state = NCR_RESELECTED; 1767 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1768 /* 1769 * Things are seriously fucked up. 1770 * Pull the brakes, i.e. reset 1771 */ 1772 printf("%s: target didn't identify\n", 1773 sc->sc_dev.dv_xname); 1774 ncr53c9x_init(sc, 1); 1775 return (1); 1776 } 1777 /* 1778 * The C90 only inhibits FIFO writes until 1779 * reselection is complete, instead of 1780 * waiting until the interrupt status register 1781 * has been read. So, if the reselect happens 1782 * while we were entering a command bytes (for 1783 * another target) some of those bytes can 1784 * appear in the FIFO here, after the 1785 * interrupt is taken. 1786 */ 1787 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1788 if (nfifo < 2 || 1789 (nfifo > 2 && 1790 sc->sc_rev != NCR_VARIANT_ESP100)) { 1791 printf("%s: RESELECT: %d bytes in FIFO! " 1792 "[intr %x, stat %x, step %d, prevphase %x]\n", 1793 sc->sc_dev.dv_xname, 1794 nfifo, 1795 sc->sc_espintr, 1796 sc->sc_espstat, 1797 sc->sc_espstep, 1798 sc->sc_prevphase); 1799 ncr53c9x_init(sc, 1); 1800 return (1); 1801 } 1802 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1803 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1804 1805 /* Handle identify message */ 1806 ncr53c9x_msgin(sc); 1807 if (nfifo != 2) { 1808 /* 1809 * Note: this should not happen 1810 * with `dmaselect' on. 1811 */ 1812 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1813 NCRCMD(sc, NCRCMD_FLUSH); 1814 } else if (ncr53c9x_dmaselect && 1815 sc->sc_rev == NCR_VARIANT_ESP100) { 1816 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1817 } 1818 1819 if (sc->sc_state != NCR_CONNECTED) { 1820 /* IDENTIFY fail?! */ 1821 printf("%s: identify failed\n", 1822 sc->sc_dev.dv_xname); 1823 ncr53c9x_init(sc, 1); 1824 return (1); 1825 } 1826 goto shortcut; /* ie. next phase expected soon */ 1827 } 1828 1829 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1830 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1831 /* 1832 * Arbitration won; examine the `step' register 1833 * to determine how far the selection could progress. 1834 */ 1835 ecb = sc->sc_nexus; 1836 if (!ecb) 1837 panic("ncr53c9x: no nexus"); 1838 1839 periph = ecb->xs->xs_periph; 1840 ti = &sc->sc_tinfo[periph->periph_target]; 1841 1842 switch (sc->sc_espstep) { 1843 case 0: 1844 /* 1845 * The target did not respond with a 1846 * message out phase - probably an old 1847 * device that doesn't recognize ATN. 1848 * Clear ATN and just continue, the 1849 * target should be in the command 1850 * phase. 1851 * XXXX check for command phase? 1852 */ 1853 NCRCMD(sc, NCRCMD_RSTATN); 1854 break; 1855 case 1: 1856 if ((ti->flags & T_NEGOTIATE) == 0) { 1857 printf("%s: step 1 & !NEG\n", 1858 sc->sc_dev.dv_xname); 1859 goto reset; 1860 } 1861 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1862 printf("%s: !MSGOUT\n", 1863 sc->sc_dev.dv_xname); 1864 goto reset; 1865 } 1866 /* Start negotiating */ 1867 ti->period = sc->sc_minsync; 1868 ti->offset = 15; 1869 sc->sc_flags |= NCR_SYNCHNEGO; 1870 ncr53c9x_sched_msgout(SEND_SDTR); 1871 break; 1872 case 3: 1873 /* 1874 * Grr, this is supposed to mean 1875 * "target left command phase prematurely". 1876 * It seems to happen regularly when 1877 * sync mode is on. 1878 * Look at FIFO to see if command went out. 1879 * (Timing problems?) 1880 */ 1881 if (ncr53c9x_dmaselect) { 1882 if (sc->sc_cmdlen == 0) 1883 /* Hope for the best.. */ 1884 break; 1885 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1886 & NCRFIFO_FF) == 0) { 1887 /* Hope for the best.. */ 1888 break; 1889 } 1890 printf("(%s:%d:%d): selection failed;" 1891 " %d left in FIFO " 1892 "[intr %x, stat %x, step %d]\n", 1893 sc->sc_dev.dv_xname, 1894 periph->periph_target, 1895 periph->periph_lun, 1896 NCR_READ_REG(sc, NCR_FFLAG) 1897 & NCRFIFO_FF, 1898 sc->sc_espintr, sc->sc_espstat, 1899 sc->sc_espstep); 1900 NCRCMD(sc, NCRCMD_FLUSH); 1901 ncr53c9x_sched_msgout(SEND_ABORT); 1902 return (1); 1903 case 2: 1904 /* Select stuck at Command Phase */ 1905 NCRCMD(sc, NCRCMD_FLUSH); 1906 case 4: 1907 if (ncr53c9x_dmaselect && 1908 sc->sc_cmdlen != 0) 1909 printf("(%s:%d:%d): select; " 1910 "%lu left in DMA buffer " 1911 "[intr %x, stat %x, step %d]\n", 1912 sc->sc_dev.dv_xname, 1913 periph->periph_target, 1914 periph->periph_lun, 1915 (u_long)sc->sc_cmdlen, 1916 sc->sc_espintr, 1917 sc->sc_espstat, 1918 sc->sc_espstep); 1919 /* So far, everything went fine */ 1920 break; 1921 } 1922 1923 ecb->flags |= ECB_NEXUS; 1924 ti->lubusy |= (1 << periph->periph_lun); 1925 1926 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1927 /* Do an implicit RESTORE POINTERS. */ 1928 sc->sc_dp = ecb->daddr; 1929 sc->sc_dleft = ecb->dleft; 1930 sc->sc_state = NCR_CONNECTED; 1931 break; 1932 1933 } else { 1934 1935 printf("%s: unexpected status after select" 1936 ": [intr %x, stat %x, step %x]\n", 1937 sc->sc_dev.dv_xname, 1938 sc->sc_espintr, sc->sc_espstat, 1939 sc->sc_espstep); 1940 NCRCMD(sc, NCRCMD_FLUSH); 1941 DELAY(1); 1942 goto reset; 1943 } 1944 if (sc->sc_state == NCR_IDLE) { 1945 printf("%s: stray interrupt\n", 1946 sc->sc_dev.dv_xname); 1947 return (0); 1948 } 1949 break; 1950 1951 case NCR_CONNECTED: 1952 if (sc->sc_flags & NCR_ICCS) { 1953 /* "Initiate Command Complete Steps" in progress */ 1954 u_char msg; 1955 1956 sc->sc_flags &= ~NCR_ICCS; 1957 1958 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1959 printf("%s: ICCS: " 1960 ": [intr %x, stat %x, step %x]\n", 1961 sc->sc_dev.dv_xname, 1962 sc->sc_espintr, sc->sc_espstat, 1963 sc->sc_espstep); 1964 } 1965 if ((NCR_READ_REG(sc, NCR_FFLAG) 1966 & NCRFIFO_FF) != 2) { 1967 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1968 & NCRFIFO_FF) - 2; 1969 while (i--) 1970 (void) NCR_READ_REG(sc, NCR_FIFO); 1971 } 1972 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1973 msg = NCR_READ_REG(sc, NCR_FIFO); 1974 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1975 if (msg == MSG_CMDCOMPLETE) { 1976 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1977 ? 0 1978 : sc->sc_dleft; 1979 if ((ecb->flags & ECB_SENSE) == 0) 1980 ecb->xs->resid = ecb->dleft; 1981 sc->sc_state = NCR_CMDCOMPLETE; 1982 } else 1983 printf("%s: STATUS_PHASE: msg %d\n", 1984 sc->sc_dev.dv_xname, msg); 1985 NCRCMD(sc, NCRCMD_MSGOK); 1986 goto shortcut; /* ie. wait for disconnect */ 1987 } 1988 break; 1989 default: 1990 panic("%s: invalid state: %d", 1991 sc->sc_dev.dv_xname, 1992 sc->sc_state); 1993 } 1994 1995 /* 1996 * Driver is now in state NCR_CONNECTED, i.e. we 1997 * have a current command working the SCSI bus. 1998 */ 1999 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 2000 panic("ncr53c9x: no nexus"); 2001 } 2002 2003 switch (sc->sc_phase) { 2004 case MESSAGE_OUT_PHASE: 2005 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 2006 ncr53c9x_msgout(sc); 2007 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2008 break; 2009 case MESSAGE_IN_PHASE: 2010 NCR_PHASE(("MESSAGE_IN_PHASE ")); 2011 sc->sc_prevphase = MESSAGE_IN_PHASE; 2012 if (sc->sc_espintr & NCRINTR_BS) { 2013 NCRCMD(sc, NCRCMD_FLUSH); 2014 sc->sc_flags |= NCR_WAITI; 2015 NCRCMD(sc, NCRCMD_TRANS); 2016 } else if (sc->sc_espintr & NCRINTR_FC) { 2017 if ((sc->sc_flags & NCR_WAITI) == 0) { 2018 printf("%s: MSGIN: unexpected FC bit: " 2019 "[intr %x, stat %x, step %x]\n", 2020 sc->sc_dev.dv_xname, 2021 sc->sc_espintr, sc->sc_espstat, 2022 sc->sc_espstep); 2023 } 2024 sc->sc_flags &= ~NCR_WAITI; 2025 ncr53c9x_msgin(sc); 2026 } else { 2027 printf("%s: MSGIN: weird bits: " 2028 "[intr %x, stat %x, step %x]\n", 2029 sc->sc_dev.dv_xname, 2030 sc->sc_espintr, sc->sc_espstat, 2031 sc->sc_espstep); 2032 } 2033 goto shortcut; /* i.e. expect data to be ready */ 2034 break; 2035 case COMMAND_PHASE: 2036 /* 2037 * Send the command block. Normally we don't see this 2038 * phase because the SEL_ATN command takes care of 2039 * all this. However, we end up here if either the 2040 * target or we wanted to exchange some more messages 2041 * first (e.g. to start negotiations). 2042 */ 2043 2044 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2045 ecb->cmd.cmd.opcode, ecb->clen)); 2046 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2047 NCRCMD(sc, NCRCMD_FLUSH); 2048 DELAY(1); 2049 } 2050 if (ncr53c9x_dmaselect) { 2051 size_t size; 2052 /* setup DMA transfer for command */ 2053 size = ecb->clen; 2054 sc->sc_cmdlen = size; 2055 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2056 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2057 0, &size); 2058 /* Program the SCSI counter */ 2059 NCR_WRITE_REG(sc, NCR_TCL, size); 2060 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2061 if (sc->sc_cfg2 & NCRCFG2_FE) { 2062 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2063 } 2064 2065 /* load the count in */ 2066 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2067 2068 /* start the command transfer */ 2069 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2070 NCRDMA_GO(sc); 2071 } else { 2072 u_char *cmd = (u_char *)&ecb->cmd.cmd; 2073 int i; 2074 /* Now the command into the FIFO */ 2075 for (i = 0; i < ecb->clen; i++) 2076 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 2077 NCRCMD(sc, NCRCMD_TRANS); 2078 } 2079 sc->sc_prevphase = COMMAND_PHASE; 2080 break; 2081 case DATA_OUT_PHASE: 2082 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 2083 NCRCMD(sc, NCRCMD_FLUSH); 2084 size = min(sc->sc_dleft, sc->sc_maxxfer); 2085 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2086 0, &size); 2087 sc->sc_prevphase = DATA_OUT_PHASE; 2088 goto setup_xfer; 2089 case DATA_IN_PHASE: 2090 NCR_PHASE(("DATA_IN_PHASE ")); 2091 if (sc->sc_rev == NCR_VARIANT_ESP100) 2092 NCRCMD(sc, NCRCMD_FLUSH); 2093 size = min(sc->sc_dleft, sc->sc_maxxfer); 2094 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2095 1, &size); 2096 sc->sc_prevphase = DATA_IN_PHASE; 2097 setup_xfer: 2098 /* Target returned to data phase: wipe "done" memory */ 2099 ecb->flags &= ~ECB_TENTATIVE_DONE; 2100 2101 /* Program the SCSI counter */ 2102 NCR_WRITE_REG(sc, NCR_TCL, size); 2103 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2104 if (sc->sc_cfg2 & NCRCFG2_FE) { 2105 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2106 } 2107 /* load the count in */ 2108 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2109 2110 /* 2111 * Note that if `size' is 0, we've already transceived 2112 * all the bytes we want but we're still in DATA PHASE. 2113 * Apparently, the device needs padding. Also, a 2114 * transfer size of 0 means "maximum" to the chip 2115 * DMA logic. 2116 */ 2117 NCRCMD(sc, 2118 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 2119 NCRDMA_GO(sc); 2120 return (1); 2121 case STATUS_PHASE: 2122 NCR_PHASE(("STATUS_PHASE ")); 2123 sc->sc_flags |= NCR_ICCS; 2124 NCRCMD(sc, NCRCMD_ICCS); 2125 sc->sc_prevphase = STATUS_PHASE; 2126 goto shortcut; /* i.e. expect status results soon */ 2127 break; 2128 case INVALID_PHASE: 2129 break; 2130 default: 2131 printf("%s: unexpected bus phase; resetting\n", 2132 sc->sc_dev.dv_xname); 2133 goto reset; 2134 } 2135 2136 out: 2137 return (1); 2138 2139 reset: 2140 ncr53c9x_init(sc, 1); 2141 goto out; 2142 2143 finish: 2144 ncr53c9x_done(sc, ecb); 2145 goto out; 2146 2147 sched: 2148 sc->sc_state = NCR_IDLE; 2149 ncr53c9x_sched(sc); 2150 goto out; 2151 2152 shortcut: 2153 /* 2154 * The idea is that many of the SCSI operations take very little 2155 * time, and going away and getting interrupted is too high an 2156 * overhead to pay. For example, selecting, sending a message 2157 * and command and then doing some work can be done in one "pass". 2158 * 2159 * The delay is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 2160 * at 40Mhz. This needs testing. 2161 */ 2162 DELAY(50/sc->sc_freq); 2163 if (NCRDMA_ISINTR(sc)) 2164 goto again; 2165 goto out; 2166 } 2167 2168 void 2169 ncr53c9x_abort(sc, ecb) 2170 struct ncr53c9x_softc *sc; 2171 struct ncr53c9x_ecb *ecb; 2172 { 2173 2174 /* 2 secs for the abort */ 2175 ecb->timeout = NCR_ABORT_TIMEOUT; 2176 ecb->flags |= ECB_ABORT; 2177 2178 if (ecb == sc->sc_nexus) { 2179 /* 2180 * If we're still selecting, the message will be scheduled 2181 * after selection is complete. 2182 */ 2183 if (sc->sc_state == NCR_CONNECTED) 2184 ncr53c9x_sched_msgout(SEND_ABORT); 2185 2186 /* 2187 * Reschedule timeout. First, cancel a queued timeout (if any) 2188 * in case someone decides to call ncr53c9x_abort() from 2189 * elsewhere. 2190 */ 2191 untimeout(ncr53c9x_timeout, ecb); 2192 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 2193 } else { 2194 /* The command should be on the nexus list */ 2195 if ((ecb->flags & ECB_NEXUS) == 0) { 2196 scsipi_printaddr(ecb->xs->xs_periph); 2197 printf("ncr53c9x_abort: not NEXUS\n"); 2198 ncr53c9x_init(sc, 1); 2199 } 2200 /* 2201 * Just leave the command on the nexus list. 2202 * XXX - what choice do we have but to reset the SCSI 2203 * eventually? 2204 */ 2205 if (sc->sc_state == NCR_IDLE) 2206 ncr53c9x_sched(sc); 2207 } 2208 } 2209 2210 void 2211 ncr53c9x_timeout(arg) 2212 void *arg; 2213 { 2214 struct ncr53c9x_ecb *ecb = arg; 2215 struct scsipi_xfer *xs = ecb->xs; 2216 struct scsipi_periph *periph = xs->xs_periph; 2217 struct ncr53c9x_softc *sc = 2218 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2219 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 2220 int s; 2221 2222 scsipi_printaddr(periph); 2223 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2224 "<state %d, nexus %p, phase(l %x, c %x, p %x), resid %lx, " 2225 "msg(q %x,o %x) %s>", 2226 sc->sc_dev.dv_xname, 2227 ecb, ecb->flags, ecb->dleft, ecb->stat, 2228 sc->sc_state, sc->sc_nexus, 2229 NCR_READ_REG(sc, NCR_STAT), 2230 sc->sc_phase, sc->sc_prevphase, 2231 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2232 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2233 #if NCR53C9X_DEBUG > 1 2234 printf("TRACE: %s.", ecb->trace); 2235 #endif 2236 2237 s = splbio(); 2238 2239 if (ecb->flags & ECB_ABORT) { 2240 /* abort timed out */ 2241 printf(" AGAIN\n"); 2242 2243 ncr53c9x_init(sc, 1); 2244 } else { 2245 /* abort the operation that has timed out */ 2246 printf("\n"); 2247 xs->error = XS_TIMEOUT; 2248 ncr53c9x_abort(sc, ecb); 2249 2250 /* Disable sync mode if stuck in a data phase */ 2251 if (ecb == sc->sc_nexus && 2252 (ti->flags & T_SYNCMODE) != 0 && 2253 (sc->sc_phase & (MSGI|CDI)) == 0) { 2254 /* XXX ASYNC CALLBACK! */ 2255 scsipi_printaddr(periph); 2256 printf("sync negotiation disabled\n"); 2257 sc->sc_cfflags |= (1<<(periph->periph_target+8)); 2258 } 2259 } 2260 2261 splx(s); 2262 } 2263
Indexes created Thu Oct 23 22:10:10 GMT 2025