ncr53c9x.c revision 1.41
1 /* $NetBSD: ncr53c9x.c,v 1.41 2000/03/09 23:19:26 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1994 Peter Galbavy 41 * Copyright (c) 1995 Paul Kranenburg 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/malloc.h> 88 #include <sys/proc.h> 89 #include <sys/user.h> 90 #include <sys/queue.h> 91 92 #include <dev/scsipi/scsi_all.h> 93 #include <dev/scsipi/scsipi_all.h> 94 #include <dev/scsipi/scsiconf.h> 95 #include <dev/scsipi/scsi_message.h> 96 97 #include <machine/cpu.h> 98 99 #include <dev/ic/ncr53c9xreg.h> 100 #include <dev/ic/ncr53c9xvar.h> 101 102 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 103 104 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 105 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 106 struct ncr53c9x_ecb *)); 107 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 108 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 109 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 110 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 111 struct scsipi_xfer *, int)); 112 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 113 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 114 struct ncr53c9x_ecb *)); 115 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 116 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 117 /*static*/ void ncr53c9x_timeout __P((void *arg)); 118 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 119 struct ncr53c9x_ecb *)); 120 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 121 struct ncr53c9x_ecb *)); 122 123 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 124 struct ncr53c9x_ecb *)); 125 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 126 struct ncr53c9x_ecb *, int)); 127 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 128 129 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 130 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 131 struct ncr53c9x_tinfo *)); 132 133 /* 134 * Names for the NCR53c9x variants, correspnding to the variant tags 135 * in ncr53c9xvar.h. 136 */ 137 const char *ncr53c9x_variant_names[] = { 138 "ESP100", 139 "ESP100A", 140 "ESP200", 141 "NCR53C94", 142 "NCR53C96", 143 "ESP406", 144 "FAS408", 145 "FAS216", 146 "AM53C974", 147 }; 148 149 /* 150 * Attach this instance, and then all the sub-devices 151 */ 152 void 153 ncr53c9x_attach(sc, dev) 154 struct ncr53c9x_softc *sc; 155 struct scsipi_device *dev; 156 { 157 158 /* 159 * Allocate SCSI message buffers. 160 * Front-ends can override allocation to avoid alignment 161 * handling in the DMA engines. Note that that ncr53c9x_msgout() 162 * can request a 1 byte DMA transfer. 163 */ 164 if (sc->sc_omess == NULL) 165 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 166 167 if (sc->sc_imess == NULL) 168 sc->sc_imess = malloc(NCR_MAX_MSG_LEN+1, M_DEVBUF, M_NOWAIT); 169 170 if (sc->sc_omess == NULL || sc->sc_imess == NULL) { 171 printf("out of memory\n"); 172 return; 173 } 174 175 /* 176 * Note, the front-end has set us up to print the chip variation. 177 */ 178 if (sc->sc_rev >= NCR_VARIANT_MAX) { 179 printf("\n%s: unknown variant %d, devices not attached\n", 180 sc->sc_dev.dv_xname, sc->sc_rev); 181 return; 182 } 183 184 printf(": %s, %dMHz, SCSI ID %d\n", 185 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 186 187 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 188 189 /* The value *must not* be == 1. Make it 2 */ 190 if (sc->sc_ccf == 1) 191 sc->sc_ccf = 2; 192 193 /* 194 * The recommended timeout is 250ms. This register is loaded 195 * with a value calculated as follows, from the docs: 196 * 197 * (timout period) x (CLK frequency) 198 * reg = ------------------------------------- 199 * 8192 x (Clock Conversion Factor) 200 * 201 * Since CCF has a linear relation to CLK, this generally computes 202 * to the constant of 153. 203 */ 204 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 205 206 /* CCF register only has 3 bits; 0 is actually 8 */ 207 sc->sc_ccf &= 7; 208 209 /* Reset state & bus */ 210 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 211 sc->sc_state = 0; 212 ncr53c9x_init(sc, 1); 213 214 /* 215 * fill in the prototype scsipi_link. 216 */ 217 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 218 sc->sc_link.adapter_softc = sc; 219 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 220 sc->sc_link.adapter = &sc->sc_adapter; 221 sc->sc_link.device = dev; 222 sc->sc_link.openings = 2; 223 sc->sc_link.scsipi_scsi.max_target = 7; 224 sc->sc_link.scsipi_scsi.max_lun = 7; 225 sc->sc_link.type = BUS_SCSI; 226 227 /* 228 * Now try to attach all the sub-devices 229 */ 230 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 231 232 /* 233 * Enable interupts from the SCSI core 234 */ 235 if ((sc->sc_rev == NCR_VARIANT_ESP406) || 236 (sc->sc_rev == NCR_VARIANT_FAS408)) { 237 NCR_PIOREGS(sc); 238 NCR_WRITE_REG(sc, NCR_CFG5, NCRCFG5_SINT | 239 NCR_READ_REG(sc, NCR_CFG5)); 240 NCR_SCSIREGS(sc); 241 } 242 243 } 244 245 /* 246 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus, 247 * only this controller, but kills any on-going commands, and also stops 248 * and resets the DMA. 249 * 250 * After reset, registers are loaded with the defaults from the attach 251 * routine above. 252 */ 253 void 254 ncr53c9x_reset(sc) 255 struct ncr53c9x_softc *sc; 256 { 257 258 /* reset DMA first */ 259 NCRDMA_RESET(sc); 260 261 /* reset SCSI chip */ 262 NCRCMD(sc, NCRCMD_RSTCHIP); 263 NCRCMD(sc, NCRCMD_NOP); 264 DELAY(500); 265 266 /* do these backwards, and fall through */ 267 switch (sc->sc_rev) { 268 case NCR_VARIANT_ESP406: 269 case NCR_VARIANT_FAS408: 270 NCR_SCSIREGS(sc); 271 case NCR_VARIANT_AM53C974: 272 case NCR_VARIANT_FAS216: 273 case NCR_VARIANT_NCR53C94: 274 case NCR_VARIANT_NCR53C96: 275 case NCR_VARIANT_ESP200: 276 sc->sc_features |= NCR_F_HASCFG3; 277 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 278 case NCR_VARIANT_ESP100A: 279 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 280 case NCR_VARIANT_ESP100: 281 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 282 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 283 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 284 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 285 break; 286 default: 287 printf("%s: unknown revision code, assuming ESP100\n", 288 sc->sc_dev.dv_xname); 289 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 290 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 291 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 292 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 293 } 294 295 if (sc->sc_rev == NCR_VARIANT_AM53C974) 296 NCR_WRITE_REG(sc, NCR_AMDCFG4, 297 NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE); 298 } 299 300 /* 301 * Reset the SCSI bus, but not the chip 302 */ 303 void 304 ncr53c9x_scsi_reset(sc) 305 struct ncr53c9x_softc *sc; 306 { 307 308 (*sc->sc_glue->gl_dma_stop)(sc); 309 310 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 311 NCRCMD(sc, NCRCMD_RSTSCSI); 312 } 313 314 /* 315 * Initialize ncr53c9x state machine 316 */ 317 void 318 ncr53c9x_init(sc, doreset) 319 struct ncr53c9x_softc *sc; 320 int doreset; 321 { 322 struct ncr53c9x_ecb *ecb; 323 int r; 324 325 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 326 327 if (sc->sc_state == 0) { 328 /* First time through; initialize. */ 329 TAILQ_INIT(&sc->ready_list); 330 TAILQ_INIT(&sc->nexus_list); 331 TAILQ_INIT(&sc->free_list); 332 sc->sc_nexus = NULL; 333 ecb = sc->sc_ecb; 334 bzero(ecb, sizeof(sc->sc_ecb)); 335 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 336 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 337 ecb++; 338 } 339 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 340 } else { 341 /* Cancel any active commands. */ 342 sc->sc_state = NCR_CLEANING; 343 if ((ecb = sc->sc_nexus) != NULL) { 344 ecb->xs->error = XS_TIMEOUT; 345 ncr53c9x_done(sc, ecb); 346 } 347 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 348 ecb->xs->error = XS_TIMEOUT; 349 ncr53c9x_done(sc, ecb); 350 } 351 } 352 353 /* 354 * reset the chip to a known state 355 */ 356 ncr53c9x_reset(sc); 357 358 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 359 for (r = 0; r < 8; r++) { 360 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 361 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 362 363 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8)))) 364 ? T_NEGOTIATE : 0) | 365 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) | 366 T_NEED_TO_RESET; 367 ti->period = sc->sc_minsync; 368 ti->offset = 0; 369 } 370 371 if (doreset) { 372 sc->sc_state = NCR_SBR; 373 NCRCMD(sc, NCRCMD_RSTSCSI); 374 } else { 375 sc->sc_state = NCR_IDLE; 376 ncr53c9x_sched(sc); 377 } 378 } 379 380 /* 381 * Read the NCR registers, and save their contents for later use. 382 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 383 * NCR_INTR - so make sure it is the last read. 384 * 385 * I think that (from reading the docs) most bits in these registers 386 * only make sense when he DMA CSR has an interrupt showing. Call only 387 * if an interrupt is pending. 388 */ 389 __inline__ void 390 ncr53c9x_readregs(sc) 391 struct ncr53c9x_softc *sc; 392 { 393 394 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 395 /* Only the stepo bits are of interest */ 396 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 397 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 398 399 if (sc->sc_glue->gl_clear_latched_intr != NULL) 400 (*sc->sc_glue->gl_clear_latched_intr)(sc); 401 402 /* 403 * Determine the SCSI bus phase, return either a real SCSI bus phase 404 * or some pseudo phase we use to detect certain exceptions. 405 */ 406 407 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 408 ? /* Disconnected */ BUSFREE_PHASE 409 : sc->sc_espstat & NCRSTAT_PHASE; 410 411 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 412 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 413 } 414 415 /* 416 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 417 */ 418 static inline int 419 ncr53c9x_stp2cpb(sc, period) 420 struct ncr53c9x_softc *sc; 421 int period; 422 { 423 int v; 424 v = (sc->sc_freq * period) / 250; 425 if (ncr53c9x_cpb2stp(sc, v) < period) 426 /* Correct round-down error */ 427 v++; 428 return (v); 429 } 430 431 static inline void 432 ncr53c9x_setsync(sc, ti) 433 struct ncr53c9x_softc *sc; 434 struct ncr53c9x_tinfo *ti; 435 { 436 u_char syncoff, synctp, cfg3 = sc->sc_cfg3; 437 438 if (ti->flags & T_SYNCMODE) { 439 syncoff = ti->offset; 440 synctp = ncr53c9x_stp2cpb(sc, ti->period); 441 if (sc->sc_features & NCR_F_FASTSCSI) { 442 /* 443 * If the period is 200ns or less (ti->period <= 50), 444 * put the chip in Fast SCSI mode. 445 */ 446 if (ti->period <= 50) 447 /* 448 * There are (at least) 4 variations of the 449 * configuration 3 register. The drive attach 450 * routine sets the appropriate bit to put the 451 * chip into Fast SCSI mode so that it doesn't 452 * have to be figured out here each time. 453 */ 454 cfg3 |= sc->sc_cfg3_fscsi; 455 } 456 457 /* 458 * Am53c974 requires different SYNCTP values when the 459 * FSCSI bit is off. 460 */ 461 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 462 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 463 synctp--; 464 } else { 465 syncoff = 0; 466 synctp = 0; 467 } 468 469 if (sc->sc_features & NCR_F_HASCFG3) 470 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 471 472 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 473 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 474 } 475 476 int ncr53c9x_dmaselect = 0; 477 /* 478 * Send a command to a target, set the driver state to NCR_SELECTING 479 * and let the caller take care of the rest. 480 * 481 * Keeping this as a function allows me to say that this may be done 482 * by DMA instead of programmed I/O soon. 483 */ 484 void 485 ncr53c9x_select(sc, ecb) 486 struct ncr53c9x_softc *sc; 487 struct ncr53c9x_ecb *ecb; 488 { 489 struct scsipi_link *sc_link = ecb->xs->sc_link; 490 int target = sc_link->scsipi_scsi.target; 491 int lun = sc_link->scsipi_scsi.lun; 492 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 493 int tiflags = ti->flags; 494 u_char *cmd; 495 int clen; 496 size_t dmasize; 497 498 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 499 target, lun, ecb->cmd.cmd.opcode)); 500 501 sc->sc_state = NCR_SELECTING; 502 503 /* 504 * Schedule the timeout now, the first time we will go away 505 * expecting to come back due to an interrupt, because it is 506 * always possible that the interrupt may never happen. 507 */ 508 if ((ecb->xs->xs_control & XS_CTL_POLL) == 0) 509 timeout(ncr53c9x_timeout, ecb, 510 (ecb->timeout * hz) / 1000); 511 512 /* 513 * The docs say the target register is never reset, and I 514 * can't think of a better place to set it 515 */ 516 NCR_WRITE_REG(sc, NCR_SELID, target); 517 ncr53c9x_setsync(sc, ti); 518 519 if (ecb->flags & ECB_SENSE) { 520 /* 521 * For REQUEST SENSE, we should not send an IDENTIFY or 522 * otherwise mangle the target. There should be no MESSAGE IN 523 * phase. 524 */ 525 if (ncr53c9x_dmaselect) { 526 /* setup DMA transfer for command */ 527 dmasize = clen = ecb->clen; 528 sc->sc_cmdlen = clen; 529 sc->sc_cmdp = (caddr_t)&ecb->cmd + 1; 530 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 531 532 /* Program the SCSI counter */ 533 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 534 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 535 if (sc->sc_cfg2 & NCRCFG2_FE) { 536 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 537 } 538 539 /* load the count in */ 540 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 541 542 /* And get the targets attention */ 543 NCRCMD(sc, NCRCMD_SELNATN | NCRCMD_DMA); 544 NCRDMA_GO(sc); 545 } else { 546 /* Now the command into the FIFO */ 547 cmd = (u_char *)&ecb->cmd.cmd; 548 clen = ecb->clen; 549 while (clen--) 550 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 551 552 NCRCMD(sc, NCRCMD_SELNATN); 553 } 554 return; 555 } 556 557 if (ncr53c9x_dmaselect && (tiflags & T_NEGOTIATE) == 0) { 558 ecb->cmd.id = 559 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1); 560 561 /* setup DMA transfer for command */ 562 dmasize = clen = ecb->clen + 1; 563 sc->sc_cmdlen = clen; 564 sc->sc_cmdp = (caddr_t)&ecb->cmd; 565 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 566 567 /* Program the SCSI counter */ 568 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 569 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 570 if (sc->sc_cfg2 & NCRCFG2_FE) { 571 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 572 } 573 574 /* load the count in */ 575 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 576 577 /* And get the targets attention */ 578 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 579 NCRDMA_GO(sc); 580 return; 581 } 582 583 /* 584 * Who am I. This is where we tell the target that we are 585 * happy for it to disconnect etc. 586 */ 587 NCR_WRITE_REG(sc, NCR_FIFO, 588 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1)); 589 590 if (ti->flags & T_NEGOTIATE) { 591 /* Arbitrate, select and stop after IDENTIFY message */ 592 NCRCMD(sc, NCRCMD_SELATNS); 593 return; 594 } 595 596 /* Now the command into the FIFO */ 597 cmd = (u_char *)&ecb->cmd.cmd; 598 clen = ecb->clen; 599 while (clen--) 600 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 601 602 /* And get the targets attention */ 603 NCRCMD(sc, NCRCMD_SELATN); 604 } 605 606 void 607 ncr53c9x_free_ecb(sc, ecb, flags) 608 struct ncr53c9x_softc *sc; 609 struct ncr53c9x_ecb *ecb; 610 int flags; 611 { 612 int s; 613 614 s = splbio(); 615 616 ecb->flags = 0; 617 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 618 619 /* 620 * If there were none, wake anybody waiting for one to come free, 621 * starting with queued entries. 622 */ 623 if (ecb->chain.tqe_next == 0) 624 wakeup(&sc->free_list); 625 626 splx(s); 627 } 628 629 struct ncr53c9x_ecb * 630 ncr53c9x_get_ecb(sc, flags) 631 struct ncr53c9x_softc *sc; 632 int flags; 633 { 634 struct ncr53c9x_ecb *ecb; 635 int s; 636 637 s = splbio(); 638 639 while ((ecb = sc->free_list.tqh_first) == NULL && 640 (flags & XS_CTL_NOSLEEP) == 0) 641 tsleep(&sc->free_list, PRIBIO, "especb", 0); 642 if (ecb) { 643 TAILQ_REMOVE(&sc->free_list, ecb, chain); 644 ecb->flags |= ECB_ALLOC; 645 } 646 647 splx(s); 648 return (ecb); 649 } 650 651 /* 652 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 653 */ 654 655 /* 656 * Start a SCSI-command 657 * This function is called by the higher level SCSI-driver to queue/run 658 * SCSI-commands. 659 */ 660 int 661 ncr53c9x_scsi_cmd(xs) 662 struct scsipi_xfer *xs; 663 { 664 struct scsipi_link *sc_link = xs->sc_link; 665 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 666 struct ncr53c9x_ecb *ecb; 667 int s, flags; 668 669 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 670 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 671 sc_link->scsipi_scsi.target)); 672 673 flags = xs->xs_control; 674 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) 675 return (TRY_AGAIN_LATER); 676 677 /* Initialize ecb */ 678 ecb->xs = xs; 679 ecb->timeout = xs->timeout; 680 681 if (flags & XS_CTL_RESET) { 682 ecb->flags |= ECB_RESET; 683 ecb->clen = 0; 684 ecb->dleft = 0; 685 } else { 686 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 687 ecb->clen = xs->cmdlen; 688 ecb->daddr = xs->data; 689 ecb->dleft = xs->datalen; 690 } 691 ecb->stat = 0; 692 693 s = splbio(); 694 695 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 696 if (sc->sc_state == NCR_IDLE) 697 ncr53c9x_sched(sc); 698 699 splx(s); 700 701 if ((flags & XS_CTL_POLL) == 0) 702 return (SUCCESSFULLY_QUEUED); 703 704 /* Not allowed to use interrupts, use polling instead */ 705 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 706 ncr53c9x_timeout(ecb); 707 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 708 ncr53c9x_timeout(ecb); 709 } 710 return (COMPLETE); 711 } 712 713 /* 714 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 715 */ 716 int 717 ncr53c9x_poll(sc, xs, count) 718 struct ncr53c9x_softc *sc; 719 struct scsipi_xfer *xs; 720 int count; 721 { 722 723 NCR_TRACE(("[ncr53c9x_poll] ")); 724 while (count) { 725 if (NCRDMA_ISINTR(sc)) { 726 ncr53c9x_intr(sc); 727 } 728 #if alternatively 729 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 730 ncr53c9x_intr(sc); 731 #endif 732 if ((xs->xs_status & XS_STS_DONE) != 0) 733 return (0); 734 if (sc->sc_state == NCR_IDLE) { 735 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 736 ncr53c9x_sched(sc); 737 } 738 DELAY(1000); 739 count--; 740 } 741 return (1); 742 } 743 744 745 /* 746 * LOW LEVEL SCSI UTILITIES 747 */ 748 749 /* 750 * Schedule a scsi operation. This has now been pulled out of the interrupt 751 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 752 * This may save us an unecessary interrupt just to get things going. 753 * Should only be called when state == NCR_IDLE and at bio pl. 754 */ 755 void 756 ncr53c9x_sched(sc) 757 struct ncr53c9x_softc *sc; 758 { 759 struct ncr53c9x_ecb *ecb; 760 struct scsipi_link *sc_link; 761 struct ncr53c9x_tinfo *ti; 762 763 NCR_TRACE(("[ncr53c9x_sched] ")); 764 if (sc->sc_state != NCR_IDLE) 765 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 766 767 /* 768 * Find first ecb in ready queue that is for a target/lunit 769 * combinations that is not busy. 770 */ 771 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 772 sc_link = ecb->xs->sc_link; 773 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 774 if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) { 775 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 776 sc->sc_nexus = ecb; 777 ncr53c9x_select(sc, ecb); 778 break; 779 } else 780 NCR_MISC(("%d:%d busy\n", 781 sc_link->scsipi_scsi.target, 782 sc_link->scsipi_scsi.lun)); 783 } 784 } 785 786 void 787 ncr53c9x_sense(sc, ecb) 788 struct ncr53c9x_softc *sc; 789 struct ncr53c9x_ecb *ecb; 790 { 791 struct scsipi_xfer *xs = ecb->xs; 792 struct scsipi_link *sc_link = xs->sc_link; 793 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 794 struct scsipi_sense *ss = (void *)&ecb->cmd.cmd; 795 796 NCR_MISC(("requesting sense ")); 797 /* Next, setup a request sense command block */ 798 bzero(ss, sizeof(*ss)); 799 ss->opcode = REQUEST_SENSE; 800 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 801 ss->length = sizeof(struct scsipi_sense_data); 802 ecb->clen = sizeof(*ss); 803 ecb->daddr = (char *)&xs->sense.scsi_sense; 804 ecb->dleft = sizeof(struct scsipi_sense_data); 805 ecb->flags |= ECB_SENSE; 806 ecb->timeout = NCR_SENSE_TIMEOUT; 807 ti->senses++; 808 if (ecb->flags & ECB_NEXUS) 809 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 810 if (ecb == sc->sc_nexus) { 811 ecb->flags &= ~ECB_NEXUS; 812 ncr53c9x_select(sc, ecb); 813 } else { 814 ncr53c9x_dequeue(sc, ecb); 815 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 816 if (sc->sc_state == NCR_IDLE) 817 ncr53c9x_sched(sc); 818 } 819 } 820 821 /* 822 * POST PROCESSING OF SCSI_CMD (usually current) 823 */ 824 void 825 ncr53c9x_done(sc, ecb) 826 struct ncr53c9x_softc *sc; 827 struct ncr53c9x_ecb *ecb; 828 { 829 struct scsipi_xfer *xs = ecb->xs; 830 struct scsipi_link *sc_link = xs->sc_link; 831 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 832 833 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 834 835 untimeout(ncr53c9x_timeout, ecb); 836 837 /* 838 * Now, if we've come here with no error code, i.e. we've kept the 839 * initial XS_NOERROR, and the status code signals that we should 840 * check sense, we'll need to set up a request sense cmd block and 841 * push the command back into the ready queue *before* any other 842 * commands for this target/lunit, else we lose the sense info. 843 * We don't support chk sense conditions for the request sense cmd. 844 */ 845 if (xs->error == XS_NOERROR) { 846 xs->status = ecb->stat; 847 if ((ecb->flags & ECB_ABORT) != 0) { 848 xs->error = XS_TIMEOUT; 849 } else if ((ecb->flags & ECB_SENSE) != 0) { 850 xs->error = XS_SENSE; 851 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 852 /* First, save the return values */ 853 xs->resid = ecb->dleft; 854 ncr53c9x_sense(sc, ecb); 855 return; 856 } else { 857 xs->resid = ecb->dleft; 858 } 859 } 860 861 xs->xs_status |= XS_STS_DONE; 862 863 #ifdef NCR53C9X_DEBUG 864 if (ncr53c9x_debug & NCR_SHOWMISC) { 865 if (xs->resid != 0) 866 printf("resid=%d ", xs->resid); 867 if (xs->error == XS_SENSE) 868 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 869 else 870 printf("error=%d\n", xs->error); 871 } 872 #endif 873 874 /* 875 * Remove the ECB from whatever queue it's on. 876 */ 877 if (ecb->flags & ECB_NEXUS) 878 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 879 if (ecb == sc->sc_nexus) { 880 sc->sc_nexus = NULL; 881 if (sc->sc_state != NCR_CLEANING) { 882 sc->sc_state = NCR_IDLE; 883 ncr53c9x_sched(sc); 884 } 885 } else 886 ncr53c9x_dequeue(sc, ecb); 887 888 ncr53c9x_free_ecb(sc, ecb, xs->xs_control); 889 ti->cmds++; 890 scsipi_done(xs); 891 } 892 893 void 894 ncr53c9x_dequeue(sc, ecb) 895 struct ncr53c9x_softc *sc; 896 struct ncr53c9x_ecb *ecb; 897 { 898 899 if (ecb->flags & ECB_NEXUS) { 900 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 901 ecb->flags &= ~ECB_NEXUS; 902 } else { 903 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 904 } 905 } 906 907 /* 908 * INTERRUPT/PROTOCOL ENGINE 909 */ 910 911 /* 912 * Schedule an outgoing message by prioritizing it, and asserting 913 * attention on the bus. We can only do this when we are the initiator 914 * else there will be an illegal command interrupt. 915 */ 916 #define ncr53c9x_sched_msgout(m) \ 917 do { \ 918 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 919 NCRCMD(sc, NCRCMD_SETATN); \ 920 sc->sc_flags |= NCR_ATN; \ 921 sc->sc_msgpriq |= (m); \ 922 } while (0) 923 924 int 925 ncr53c9x_reselect(sc, message) 926 struct ncr53c9x_softc *sc; 927 int message; 928 { 929 u_char selid, target, lun; 930 struct ncr53c9x_ecb *ecb; 931 struct scsipi_link *sc_link; 932 struct ncr53c9x_tinfo *ti; 933 934 /* 935 * The SCSI chip made a snapshot of the data bus while the reselection 936 * was being negotiated. This enables us to determine which target did 937 * the reselect. 938 */ 939 selid = sc->sc_selid & ~(1 << sc->sc_id); 940 if (selid & (selid - 1)) { 941 printf("%s: reselect with invalid selid %02x;" 942 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 943 goto reset; 944 } 945 946 /* 947 * Search wait queue for disconnected cmd 948 * The list should be short, so I haven't bothered with 949 * any more sophisticated structures than a simple 950 * singly linked list. 951 */ 952 target = ffs(selid) - 1; 953 lun = message & 0x07; 954 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 955 ecb = ecb->chain.tqe_next) { 956 sc_link = ecb->xs->sc_link; 957 if (sc_link->scsipi_scsi.target == target && 958 sc_link->scsipi_scsi.lun == lun) 959 break; 960 } 961 if (ecb == NULL) { 962 printf("%s: reselect from target %d lun %d with no nexus;" 963 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 964 goto abort; 965 } 966 967 /* Make this nexus active again. */ 968 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 969 sc->sc_state = NCR_CONNECTED; 970 sc->sc_nexus = ecb; 971 ti = &sc->sc_tinfo[target]; 972 #ifdef NCR53C9X_DEBUG 973 if ((ti->lubusy & (1 << lun)) == 0) { 974 printf("%s: reselect: target %d, lun %d: should be busy\n", 975 sc->sc_dev.dv_xname, target, lun); 976 ti->lubusy |= (1 << lun); 977 } 978 #endif 979 ncr53c9x_setsync(sc, ti); 980 981 if (ecb->flags & ECB_RESET) 982 ncr53c9x_sched_msgout(SEND_DEV_RESET); 983 else if (ecb->flags & ECB_ABORT) 984 ncr53c9x_sched_msgout(SEND_ABORT); 985 986 /* Do an implicit RESTORE POINTERS. */ 987 sc->sc_dp = ecb->daddr; 988 sc->sc_dleft = ecb->dleft; 989 990 return (0); 991 992 reset: 993 ncr53c9x_sched_msgout(SEND_DEV_RESET); 994 return (1); 995 996 abort: 997 ncr53c9x_sched_msgout(SEND_ABORT); 998 return (1); 999 } 1000 1001 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1002 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1003 #define ISEXTMSG(m) ((m) == 1) 1004 1005 /* 1006 * Get an incoming message as initiator. 1007 * 1008 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1009 * byte in the FIFO 1010 */ 1011 void 1012 ncr53c9x_msgin(sc) 1013 register struct ncr53c9x_softc *sc; 1014 { 1015 register int v; 1016 1017 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1018 1019 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 1020 printf("%s: msgin: no msg byte available\n", 1021 sc->sc_dev.dv_xname); 1022 return; 1023 } 1024 1025 /* 1026 * Prepare for a new message. A message should (according 1027 * to the SCSI standard) be transmitted in one single 1028 * MESSAGE_IN_PHASE. If we have been in some other phase, 1029 * then this is a new message. 1030 */ 1031 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1032 sc->sc_flags &= ~NCR_DROP_MSGI; 1033 sc->sc_imlen = 0; 1034 } 1035 1036 v = NCR_READ_REG(sc, NCR_FIFO); 1037 NCR_MISC(("<msgbyte:0x%02x>", v)); 1038 1039 #if 0 1040 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 1041 /* 1042 * Which target is reselecting us? (The ID bit really) 1043 */ 1044 sc->sc_selid = v; 1045 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1046 return; 1047 } 1048 #endif 1049 1050 sc->sc_imess[sc->sc_imlen] = v; 1051 1052 /* 1053 * If we're going to reject the message, don't bother storing 1054 * the incoming bytes. But still, we need to ACK them. 1055 */ 1056 1057 if ((sc->sc_flags & NCR_DROP_MSGI)) { 1058 NCRCMD(sc, NCRCMD_MSGOK); 1059 printf("<dropping msg byte %x>", 1060 sc->sc_imess[sc->sc_imlen]); 1061 return; 1062 } 1063 1064 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1065 ncr53c9x_sched_msgout(SEND_REJECT); 1066 sc->sc_flags |= NCR_DROP_MSGI; 1067 } else { 1068 sc->sc_imlen++; 1069 /* 1070 * This testing is suboptimal, but most 1071 * messages will be of the one byte variety, so 1072 * it should not effect performance 1073 * significantly. 1074 */ 1075 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1076 goto gotit; 1077 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1078 goto gotit; 1079 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1080 sc->sc_imlen == sc->sc_imess[1] + 2) 1081 goto gotit; 1082 } 1083 /* Ack what we have so far */ 1084 NCRCMD(sc, NCRCMD_MSGOK); 1085 return; 1086 1087 gotit: 1088 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1089 /* 1090 * Now we should have a complete message (1 byte, 2 byte 1091 * and moderately long extended messages). We only handle 1092 * extended messages which total length is shorter than 1093 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1094 */ 1095 switch (sc->sc_state) { 1096 struct ncr53c9x_ecb *ecb; 1097 struct ncr53c9x_tinfo *ti; 1098 1099 case NCR_CONNECTED: 1100 ecb = sc->sc_nexus; 1101 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1102 1103 switch (sc->sc_imess[0]) { 1104 case MSG_CMDCOMPLETE: 1105 NCR_MSGS(("cmdcomplete ")); 1106 if (sc->sc_dleft < 0) { 1107 scsi_print_addr(ecb->xs->sc_link); 1108 printf("got %ld extra bytes\n", 1109 -(long)sc->sc_dleft); 1110 sc->sc_dleft = 0; 1111 } 1112 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1113 ? 0 1114 : sc->sc_dleft; 1115 if ((ecb->flags & ECB_SENSE) == 0) 1116 ecb->xs->resid = ecb->dleft; 1117 sc->sc_state = NCR_CMDCOMPLETE; 1118 break; 1119 1120 case MSG_MESSAGE_REJECT: 1121 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1122 switch (sc->sc_msgout) { 1123 case SEND_SDTR: 1124 sc->sc_flags &= ~NCR_SYNCHNEGO; 1125 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1126 ncr53c9x_setsync(sc, ti); 1127 break; 1128 case SEND_INIT_DET_ERR: 1129 goto abort; 1130 } 1131 break; 1132 1133 case MSG_NOOP: 1134 NCR_MSGS(("noop ")); 1135 break; 1136 1137 case MSG_DISCONNECT: 1138 NCR_MSGS(("disconnect ")); 1139 ti->dconns++; 1140 sc->sc_state = NCR_DISCONNECT; 1141 1142 /* 1143 * Mark the fact that all bytes have moved. The 1144 * target may not bother to do a SAVE POINTERS 1145 * at this stage. This flag will set the residual 1146 * count to zero on MSG COMPLETE. 1147 */ 1148 if (sc->sc_dleft == 0) 1149 ecb->flags |= ECB_TENTATIVE_DONE; 1150 1151 break; 1152 1153 case MSG_SAVEDATAPOINTER: 1154 NCR_MSGS(("save datapointer ")); 1155 ecb->daddr = sc->sc_dp; 1156 ecb->dleft = sc->sc_dleft; 1157 break; 1158 1159 case MSG_RESTOREPOINTERS: 1160 NCR_MSGS(("restore datapointer ")); 1161 sc->sc_dp = ecb->daddr; 1162 sc->sc_dleft = ecb->dleft; 1163 break; 1164 1165 case MSG_EXTENDED: 1166 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1167 switch (sc->sc_imess[2]) { 1168 case MSG_EXT_SDTR: 1169 NCR_MSGS(("SDTR period %d, offset %d ", 1170 sc->sc_imess[3], sc->sc_imess[4])); 1171 if (sc->sc_imess[1] != 3) 1172 goto reject; 1173 ti->period = sc->sc_imess[3]; 1174 ti->offset = sc->sc_imess[4]; 1175 ti->flags &= ~T_NEGOTIATE; 1176 if (sc->sc_minsync == 0 || 1177 ti->offset == 0 || 1178 ti->period > 124) { 1179 #ifdef NCR53C9X_DEBUG 1180 scsi_print_addr(ecb->xs->sc_link); 1181 printf("async mode\n"); 1182 #endif 1183 if ((sc->sc_flags&NCR_SYNCHNEGO) 1184 == 0) { 1185 /* 1186 * target initiated negotiation 1187 */ 1188 ti->offset = 0; 1189 ti->flags &= ~T_SYNCMODE; 1190 ncr53c9x_sched_msgout( 1191 SEND_SDTR); 1192 } else { 1193 /* we are async */ 1194 ti->flags &= ~T_SYNCMODE; 1195 } 1196 } else { 1197 int r = 250/ti->period; 1198 int s = (100*250)/ti->period - 100*r; 1199 int p; 1200 1201 p = ncr53c9x_stp2cpb(sc, ti->period); 1202 ti->period = ncr53c9x_cpb2stp(sc, p); 1203 #ifdef NCR53C9X_DEBUG 1204 scsi_print_addr(ecb->xs->sc_link); 1205 printf("max sync rate %d.%02dMB/s\n", 1206 r, s); 1207 #endif 1208 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) { 1209 /* 1210 * target initiated negotiation 1211 */ 1212 if (ti->period < 1213 sc->sc_minsync) 1214 ti->period = 1215 sc->sc_minsync; 1216 if (ti->offset > 15) 1217 ti->offset = 15; 1218 ti->flags &= ~T_SYNCMODE; 1219 ncr53c9x_sched_msgout( 1220 SEND_SDTR); 1221 } else { 1222 /* we are sync */ 1223 ti->flags |= T_SYNCMODE; 1224 } 1225 } 1226 sc->sc_flags &= ~NCR_SYNCHNEGO; 1227 ncr53c9x_setsync(sc, ti); 1228 break; 1229 1230 default: 1231 scsi_print_addr(ecb->xs->sc_link); 1232 printf("unrecognized MESSAGE EXTENDED;" 1233 " sending REJECT\n"); 1234 goto reject; 1235 } 1236 break; 1237 1238 default: 1239 NCR_MSGS(("ident ")); 1240 scsi_print_addr(ecb->xs->sc_link); 1241 printf("unrecognized MESSAGE; sending REJECT\n"); 1242 reject: 1243 ncr53c9x_sched_msgout(SEND_REJECT); 1244 break; 1245 } 1246 break; 1247 1248 case NCR_RESELECTED: 1249 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1250 printf("%s: reselect without IDENTIFY;" 1251 " sending DEVICE RESET\n", 1252 sc->sc_dev.dv_xname); 1253 goto reset; 1254 } 1255 1256 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1257 break; 1258 1259 default: 1260 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1261 sc->sc_dev.dv_xname); 1262 reset: 1263 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1264 break; 1265 1266 abort: 1267 ncr53c9x_sched_msgout(SEND_ABORT); 1268 break; 1269 } 1270 1271 /* Ack last message byte */ 1272 NCRCMD(sc, NCRCMD_MSGOK); 1273 1274 /* Done, reset message pointer. */ 1275 sc->sc_flags &= ~NCR_DROP_MSGI; 1276 sc->sc_imlen = 0; 1277 } 1278 1279 1280 /* 1281 * Send the highest priority, scheduled message 1282 */ 1283 void 1284 ncr53c9x_msgout(sc) 1285 register struct ncr53c9x_softc *sc; 1286 { 1287 struct ncr53c9x_tinfo *ti; 1288 struct ncr53c9x_ecb *ecb; 1289 size_t size; 1290 1291 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1292 sc->sc_msgpriq, sc->sc_prevphase)); 1293 1294 /* 1295 * XXX - the NCR_ATN flag is not in sync with the actual ATN 1296 * condition on the SCSI bus. The 53c9x chip 1297 * automatically turns off ATN before sending the 1298 * message byte. (see also the comment below in the 1299 * default case when picking out a message to send) 1300 */ 1301 if (sc->sc_flags & NCR_ATN) { 1302 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1303 new: 1304 NCRCMD(sc, NCRCMD_FLUSH); 1305 DELAY(1); 1306 sc->sc_msgoutq = 0; 1307 sc->sc_omlen = 0; 1308 } 1309 } else { 1310 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1311 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1312 goto new; 1313 } else { 1314 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1315 sc->sc_dev.dv_xname, __LINE__); 1316 } 1317 } 1318 1319 if (sc->sc_omlen == 0) { 1320 /* Pick up highest priority message */ 1321 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1322 sc->sc_msgoutq |= sc->sc_msgout; 1323 sc->sc_msgpriq &= ~sc->sc_msgout; 1324 sc->sc_omlen = 1; /* "Default" message len */ 1325 switch (sc->sc_msgout) { 1326 case SEND_SDTR: 1327 ecb = sc->sc_nexus; 1328 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1329 sc->sc_omess[0] = MSG_EXTENDED; 1330 sc->sc_omess[1] = 3; 1331 sc->sc_omess[2] = MSG_EXT_SDTR; 1332 sc->sc_omess[3] = ti->period; 1333 sc->sc_omess[4] = ti->offset; 1334 sc->sc_omlen = 5; 1335 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1336 ti->flags |= T_SYNCMODE; 1337 ncr53c9x_setsync(sc, ti); 1338 } 1339 break; 1340 case SEND_IDENTIFY: 1341 if (sc->sc_state != NCR_CONNECTED) { 1342 printf("%s at line %d: no nexus\n", 1343 sc->sc_dev.dv_xname, __LINE__); 1344 } 1345 ecb = sc->sc_nexus; 1346 sc->sc_omess[0] = 1347 MSG_IDENTIFY(ecb->xs->sc_link->scsipi_scsi.lun, 0); 1348 break; 1349 case SEND_DEV_RESET: 1350 sc->sc_flags |= NCR_ABORTING; 1351 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1352 ecb = sc->sc_nexus; 1353 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1354 ti->flags &= ~T_SYNCMODE; 1355 ti->flags |= T_NEGOTIATE; 1356 break; 1357 case SEND_PARITY_ERROR: 1358 sc->sc_omess[0] = MSG_PARITY_ERROR; 1359 break; 1360 case SEND_ABORT: 1361 sc->sc_flags |= NCR_ABORTING; 1362 sc->sc_omess[0] = MSG_ABORT; 1363 break; 1364 case SEND_INIT_DET_ERR: 1365 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1366 break; 1367 case SEND_REJECT: 1368 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1369 break; 1370 default: 1371 /* 1372 * We normally do not get here, since the chip 1373 * automatically turns off ATN before the last 1374 * byte of a message is sent to the target. 1375 * However, if the target rejects our (multi-byte) 1376 * message early by switching to MSG IN phase 1377 * ATN remains on, so the target may return to 1378 * MSG OUT phase. If there are no scheduled messages 1379 * left we send a NO-OP. 1380 * 1381 * XXX - Note that this leaves no useful purpose for 1382 * the NCR_ATN flag. 1383 */ 1384 sc->sc_flags &= ~NCR_ATN; 1385 sc->sc_omess[0] = MSG_NOOP; 1386 break; 1387 } 1388 sc->sc_omp = sc->sc_omess; 1389 } 1390 1391 /* (re)send the message */ 1392 size = min(sc->sc_omlen, sc->sc_maxxfer); 1393 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1394 /* Program the SCSI counter */ 1395 NCR_WRITE_REG(sc, NCR_TCL, size); 1396 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1397 if (sc->sc_cfg2 & NCRCFG2_FE) { 1398 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1399 } 1400 /* Load the count in and start the message-out transfer */ 1401 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1402 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1403 NCRDMA_GO(sc); 1404 } 1405 1406 /* 1407 * This is the most critical part of the driver, and has to know 1408 * how to deal with *all* error conditions and phases from the SCSI 1409 * bus. If there are no errors and the DMA was active, then call the 1410 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1411 * and we can return from here without further processing. 1412 * 1413 * Most of this needs verifying. 1414 */ 1415 int sdebug = 0; 1416 int 1417 ncr53c9x_intr(sc) 1418 register struct ncr53c9x_softc *sc; 1419 { 1420 register struct ncr53c9x_ecb *ecb; 1421 register struct scsipi_link *sc_link; 1422 struct ncr53c9x_tinfo *ti; 1423 size_t size; 1424 int nfifo; 1425 1426 NCR_TRACE(("[ncr53c9x_intr] ")); 1427 1428 if (!NCRDMA_ISINTR(sc)) 1429 return (0); 1430 1431 again: 1432 /* and what do the registers say... */ 1433 ncr53c9x_readregs(sc); 1434 1435 sc->sc_intrcnt.ev_count++; 1436 1437 /* 1438 * At the moment, only a SCSI Bus Reset or Illegal 1439 * Command are classed as errors. A disconnect is a 1440 * valid condition, and we let the code check is the 1441 * "NCR_BUSFREE_OK" flag was set before declaring it 1442 * and error. 1443 * 1444 * Also, the status register tells us about "Gross 1445 * Errors" and "Parity errors". Only the Gross Error 1446 * is really bad, and the parity errors are dealt 1447 * with later 1448 * 1449 * TODO 1450 * If there are too many parity error, go to slow 1451 * cable mode ? 1452 */ 1453 1454 /* SCSI Reset */ 1455 if (sc->sc_espintr & NCRINTR_SBR) { 1456 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1457 NCRCMD(sc, NCRCMD_FLUSH); 1458 DELAY(1); 1459 } 1460 if (sc->sc_state != NCR_SBR) { 1461 printf("%s: SCSI bus reset\n", 1462 sc->sc_dev.dv_xname); 1463 ncr53c9x_init(sc, 0); /* Restart everything */ 1464 return (1); 1465 } 1466 #if 0 1467 /*XXX*/ printf("<expected bus reset: " 1468 "[intr %x, stat %x, step %d]>\n", 1469 sc->sc_espintr, sc->sc_espstat, 1470 sc->sc_espstep); 1471 #endif 1472 if (sc->sc_nexus) 1473 panic("%s: nexus in reset state", 1474 sc->sc_dev.dv_xname); 1475 goto sched; 1476 } 1477 1478 ecb = sc->sc_nexus; 1479 1480 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1481 if (sc->sc_espintr & NCRINTR_ERR || 1482 sc->sc_espstat & NCRSTAT_GE) { 1483 1484 if (sc->sc_espstat & NCRSTAT_GE) { 1485 /* Gross Error; no target ? */ 1486 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1487 NCRCMD(sc, NCRCMD_FLUSH); 1488 DELAY(1); 1489 } 1490 if (sc->sc_state == NCR_CONNECTED || 1491 sc->sc_state == NCR_SELECTING) { 1492 ecb->xs->error = XS_TIMEOUT; 1493 ncr53c9x_done(sc, ecb); 1494 } 1495 return (1); 1496 } 1497 1498 if (sc->sc_espintr & NCRINTR_ILL) { 1499 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1500 /* 1501 * Eat away "Illegal command" interrupt 1502 * on a ESP100 caused by a re-selection 1503 * while we were trying to select 1504 * another target. 1505 */ 1506 #ifdef DEBUG 1507 printf("%s: ESP100 work-around activated\n", 1508 sc->sc_dev.dv_xname); 1509 #endif 1510 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1511 return (1); 1512 } 1513 /* illegal command, out of sync ? */ 1514 printf("%s: illegal command: 0x%x " 1515 "(state %d, phase %x, prevphase %x)\n", 1516 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1517 sc->sc_state, sc->sc_phase, 1518 sc->sc_prevphase); 1519 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1520 NCRCMD(sc, NCRCMD_FLUSH); 1521 DELAY(1); 1522 } 1523 ncr53c9x_init(sc, 1); /* Restart everything */ 1524 return (1); 1525 } 1526 } 1527 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1528 1529 /* 1530 * Call if DMA is active. 1531 * 1532 * If DMA_INTR returns true, then maybe go 'round the loop 1533 * again in case there is no more DMA queued, but a phase 1534 * change is expected. 1535 */ 1536 if (NCRDMA_ISACTIVE(sc)) { 1537 int r = NCRDMA_INTR(sc); 1538 if (r == -1) { 1539 printf("%s: DMA error; resetting\n", 1540 sc->sc_dev.dv_xname); 1541 ncr53c9x_init(sc, 1); 1542 } 1543 /* If DMA active here, then go back to work... */ 1544 if (NCRDMA_ISACTIVE(sc)) 1545 return (1); 1546 1547 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 1548 /* 1549 * DMA not completed. If we can not find a 1550 * acceptable explanation, print a diagnostic. 1551 */ 1552 if (sc->sc_state == NCR_SELECTING) 1553 /* 1554 * This can happen if we are reselected 1555 * while using DMA to select a target. 1556 */ 1557 /*void*/; 1558 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1559 /* 1560 * Our (multi-byte) message (eg SDTR) was 1561 * interrupted by the target to send 1562 * a MSG REJECT. 1563 * Print diagnostic if current phase 1564 * is not MESSAGE IN. 1565 */ 1566 if (sc->sc_phase != MESSAGE_IN_PHASE) 1567 printf("%s: !TC on MSG OUT" 1568 " [intr %x, stat %x, step %d]" 1569 " prevphase %x, resid %lx\n", 1570 sc->sc_dev.dv_xname, 1571 sc->sc_espintr, 1572 sc->sc_espstat, 1573 sc->sc_espstep, 1574 sc->sc_prevphase, 1575 (u_long)sc->sc_omlen); 1576 } else if (sc->sc_dleft == 0) { 1577 /* 1578 * The DMA operation was started for 1579 * a DATA transfer. Print a diagnostic 1580 * if the DMA counter and TC bit 1581 * appear to be out of sync. 1582 */ 1583 printf("%s: !TC on DATA XFER" 1584 " [intr %x, stat %x, step %d]" 1585 " prevphase %x, resid %x\n", 1586 sc->sc_dev.dv_xname, 1587 sc->sc_espintr, 1588 sc->sc_espstat, 1589 sc->sc_espstep, 1590 sc->sc_prevphase, 1591 ecb?ecb->dleft:-1); 1592 } 1593 } 1594 } 1595 1596 /* 1597 * Check for less serious errors. 1598 */ 1599 if (sc->sc_espstat & NCRSTAT_PE) { 1600 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1601 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1602 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1603 else 1604 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1605 } 1606 1607 if (sc->sc_espintr & NCRINTR_DIS) { 1608 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1609 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1610 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1611 NCRCMD(sc, NCRCMD_FLUSH); 1612 DELAY(1); 1613 } 1614 /* 1615 * This command must (apparently) be issued within 1616 * 250mS of a disconnect. So here you are... 1617 */ 1618 NCRCMD(sc, NCRCMD_ENSEL); 1619 1620 switch (sc->sc_state) { 1621 case NCR_RESELECTED: 1622 goto sched; 1623 1624 case NCR_SELECTING: 1625 ecb->xs->error = XS_SELTIMEOUT; 1626 goto finish; 1627 1628 case NCR_CONNECTED: 1629 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1630 #ifdef NCR53C9X_DEBUG 1631 if (ecb) 1632 scsi_print_addr(ecb->xs->sc_link); 1633 printf("sync nego not completed!\n"); 1634 #endif 1635 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1636 sc->sc_flags &= ~NCR_SYNCHNEGO; 1637 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1638 } 1639 1640 /* it may be OK to disconnect */ 1641 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1642 /* 1643 * Section 5.1.1 of the SCSI 2 spec 1644 * suggests issuing a REQUEST SENSE 1645 * following an unexpected disconnect. 1646 * Some devices go into a contingent 1647 * allegiance condition when 1648 * disconnecting, and this is necessary 1649 * to clean up their state. 1650 */ 1651 printf("%s: unexpected disconnect; ", 1652 sc->sc_dev.dv_xname); 1653 if (ecb->flags & ECB_SENSE) { 1654 printf("resetting\n"); 1655 goto reset; 1656 } 1657 printf("sending REQUEST SENSE\n"); 1658 untimeout(ncr53c9x_timeout, ecb); 1659 ncr53c9x_sense(sc, ecb); 1660 goto out; 1661 } 1662 1663 ecb->xs->error = XS_TIMEOUT; 1664 goto finish; 1665 1666 case NCR_DISCONNECT: 1667 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1668 sc->sc_nexus = NULL; 1669 goto sched; 1670 1671 case NCR_CMDCOMPLETE: 1672 goto finish; 1673 } 1674 } 1675 1676 switch (sc->sc_state) { 1677 1678 case NCR_SBR: 1679 printf("%s: waiting for SCSI Bus Reset to happen\n", 1680 sc->sc_dev.dv_xname); 1681 return (1); 1682 1683 case NCR_RESELECTED: 1684 /* 1685 * we must be continuing a message ? 1686 */ 1687 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1688 printf("%s: target didn't identify\n", 1689 sc->sc_dev.dv_xname); 1690 ncr53c9x_init(sc, 1); 1691 return (1); 1692 } 1693 printf("<<RESELECT CONT'd>>"); 1694 #if XXXX 1695 ncr53c9x_msgin(sc); 1696 if (sc->sc_state != NCR_CONNECTED) { 1697 /* IDENTIFY fail?! */ 1698 printf("%s: identify failed\n", 1699 sc->sc_dev.dv_xname); 1700 ncr53c9x_init(sc, 1); 1701 return (1); 1702 } 1703 #endif 1704 break; 1705 1706 case NCR_IDLE: 1707 case NCR_SELECTING: 1708 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1709 sc->sc_flags = 0; 1710 ecb = sc->sc_nexus; 1711 if (ecb != NULL && (ecb->flags & ECB_NEXUS)) { 1712 scsi_print_addr(ecb->xs->sc_link); 1713 printf("ECB_NEXUS while in state %x\n", sc->sc_state); 1714 } 1715 1716 if (sc->sc_espintr & NCRINTR_RESEL) { 1717 /* 1718 * If we're trying to select a 1719 * target ourselves, push our command 1720 * back into the ready list. 1721 */ 1722 if (sc->sc_state == NCR_SELECTING) { 1723 NCR_MISC(("backoff selector ")); 1724 untimeout(ncr53c9x_timeout, ecb); 1725 sc_link = ecb->xs->sc_link; 1726 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1727 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1728 ecb = sc->sc_nexus = NULL; 1729 } 1730 sc->sc_state = NCR_RESELECTED; 1731 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1732 /* 1733 * Things are seriously fucked up. 1734 * Pull the brakes, i.e. reset 1735 */ 1736 printf("%s: target didn't identify\n", 1737 sc->sc_dev.dv_xname); 1738 ncr53c9x_init(sc, 1); 1739 return (1); 1740 } 1741 /* 1742 * The C90 only inhibits FIFO writes until 1743 * reselection is complete, instead of 1744 * waiting until the interrupt status register 1745 * has been read. So, if the reselect happens 1746 * while we were entering a command bytes (for 1747 * another target) some of those bytes can 1748 * appear in the FIFO here, after the 1749 * interrupt is taken. 1750 */ 1751 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1752 if (nfifo < 2 || 1753 (nfifo > 2 && 1754 sc->sc_rev != NCR_VARIANT_ESP100)) { 1755 printf("%s: RESELECT: %d bytes in FIFO! " 1756 "[intr %x, stat %x, step %d, prevphase %x]\n", 1757 sc->sc_dev.dv_xname, 1758 nfifo, 1759 sc->sc_espintr, 1760 sc->sc_espstat, 1761 sc->sc_espstep, 1762 sc->sc_prevphase); 1763 ncr53c9x_init(sc, 1); 1764 return (1); 1765 } 1766 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1767 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1768 1769 /* Handle identify message */ 1770 ncr53c9x_msgin(sc); 1771 if (nfifo != 2) { 1772 /* 1773 * Note: this should not happen 1774 * with `dmaselect' on. 1775 */ 1776 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1777 NCRCMD(sc, NCRCMD_FLUSH); 1778 } else if (ncr53c9x_dmaselect && 1779 sc->sc_rev == NCR_VARIANT_ESP100) { 1780 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1781 } 1782 1783 if (sc->sc_state != NCR_CONNECTED) { 1784 /* IDENTIFY fail?! */ 1785 printf("%s: identify failed\n", 1786 sc->sc_dev.dv_xname); 1787 ncr53c9x_init(sc, 1); 1788 return (1); 1789 } 1790 goto shortcut; /* ie. next phase expected soon */ 1791 } 1792 1793 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1794 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1795 /* 1796 * Arbitration won; examine the `step' register 1797 * to determine how far the selection could progress. 1798 */ 1799 ecb = sc->sc_nexus; 1800 if (!ecb) 1801 panic("ncr53c9x: no nexus"); 1802 1803 sc_link = ecb->xs->sc_link; 1804 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1805 1806 switch (sc->sc_espstep) { 1807 case 0: 1808 /* 1809 * The target did not respond with a 1810 * message out phase - probably an old 1811 * device that doesn't recognize ATN. 1812 * Clear ATN and just continue, the 1813 * target should be in the command 1814 * phase. 1815 * XXXX check for command phase? 1816 */ 1817 NCRCMD(sc, NCRCMD_RSTATN); 1818 break; 1819 case 1: 1820 if ((ti->flags & T_NEGOTIATE) == 0) { 1821 printf("%s: step 1 & !NEG\n", 1822 sc->sc_dev.dv_xname); 1823 goto reset; 1824 } 1825 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1826 printf("%s: !MSGOUT\n", 1827 sc->sc_dev.dv_xname); 1828 goto reset; 1829 } 1830 /* Start negotiating */ 1831 ti->period = sc->sc_minsync; 1832 ti->offset = 15; 1833 sc->sc_flags |= NCR_SYNCHNEGO; 1834 ncr53c9x_sched_msgout(SEND_SDTR); 1835 break; 1836 case 3: 1837 /* 1838 * Grr, this is supposed to mean 1839 * "target left command phase prematurely". 1840 * It seems to happen regularly when 1841 * sync mode is on. 1842 * Look at FIFO to see if command went out. 1843 * (Timing problems?) 1844 */ 1845 if (ncr53c9x_dmaselect) { 1846 if (sc->sc_cmdlen == 0) 1847 /* Hope for the best.. */ 1848 break; 1849 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1850 & NCRFIFO_FF) == 0) { 1851 /* Hope for the best.. */ 1852 break; 1853 } 1854 printf("(%s:%d:%d): selection failed;" 1855 " %d left in FIFO " 1856 "[intr %x, stat %x, step %d]\n", 1857 sc->sc_dev.dv_xname, 1858 sc_link->scsipi_scsi.target, 1859 sc_link->scsipi_scsi.lun, 1860 NCR_READ_REG(sc, NCR_FFLAG) 1861 & NCRFIFO_FF, 1862 sc->sc_espintr, sc->sc_espstat, 1863 sc->sc_espstep); 1864 NCRCMD(sc, NCRCMD_FLUSH); 1865 ncr53c9x_sched_msgout(SEND_ABORT); 1866 return (1); 1867 case 2: 1868 /* Select stuck at Command Phase */ 1869 NCRCMD(sc, NCRCMD_FLUSH); 1870 break; 1871 case 4: 1872 if (ncr53c9x_dmaselect && 1873 sc->sc_cmdlen != 0) 1874 printf("(%s:%d:%d): select; " 1875 "%lu left in DMA buffer " 1876 "[intr %x, stat %x, step %d]\n", 1877 sc->sc_dev.dv_xname, 1878 sc_link->scsipi_scsi.target, 1879 sc_link->scsipi_scsi.lun, 1880 (u_long)sc->sc_cmdlen, 1881 sc->sc_espintr, 1882 sc->sc_espstat, 1883 sc->sc_espstep); 1884 /* So far, everything went fine */ 1885 break; 1886 } 1887 1888 ecb->flags |= ECB_NEXUS; 1889 ti->lubusy |= (1 << sc_link->scsipi_scsi.lun); 1890 1891 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1892 /* Do an implicit RESTORE POINTERS. */ 1893 sc->sc_dp = ecb->daddr; 1894 sc->sc_dleft = ecb->dleft; 1895 sc->sc_state = NCR_CONNECTED; 1896 break; 1897 1898 } else { 1899 1900 printf("%s: unexpected status after select" 1901 ": [intr %x, stat %x, step %x]\n", 1902 sc->sc_dev.dv_xname, 1903 sc->sc_espintr, sc->sc_espstat, 1904 sc->sc_espstep); 1905 NCRCMD(sc, NCRCMD_FLUSH); 1906 DELAY(1); 1907 goto reset; 1908 } 1909 if (sc->sc_state == NCR_IDLE) { 1910 printf("%s: stray interrupt\n", 1911 sc->sc_dev.dv_xname); 1912 return (0); 1913 } 1914 break; 1915 1916 case NCR_CONNECTED: 1917 if (sc->sc_flags & NCR_ICCS) { 1918 /* "Initiate Command Complete Steps" in progress */ 1919 u_char msg; 1920 1921 sc->sc_flags &= ~NCR_ICCS; 1922 1923 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1924 printf("%s: ICCS: " 1925 ": [intr %x, stat %x, step %x]\n", 1926 sc->sc_dev.dv_xname, 1927 sc->sc_espintr, sc->sc_espstat, 1928 sc->sc_espstep); 1929 } 1930 if ((NCR_READ_REG(sc, NCR_FFLAG) 1931 & NCRFIFO_FF) != 2) { 1932 /* Drop excess bytes from the queue */ 1933 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1934 & NCRFIFO_FF) - 2; 1935 while (i-- > 0) 1936 (void) NCR_READ_REG(sc, NCR_FIFO); 1937 } 1938 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1939 msg = NCR_READ_REG(sc, NCR_FIFO); 1940 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1941 if (msg == MSG_CMDCOMPLETE) { 1942 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1943 ? 0 1944 : sc->sc_dleft; 1945 if ((ecb->flags & ECB_SENSE) == 0) 1946 ecb->xs->resid = ecb->dleft; 1947 sc->sc_state = NCR_CMDCOMPLETE; 1948 } else 1949 printf("%s: STATUS_PHASE: msg %d\n", 1950 sc->sc_dev.dv_xname, msg); 1951 NCRCMD(sc, NCRCMD_MSGOK); 1952 goto shortcut; /* ie. wait for disconnect */ 1953 } 1954 break; 1955 default: 1956 panic("%s: invalid state: %d", 1957 sc->sc_dev.dv_xname, 1958 sc->sc_state); 1959 } 1960 1961 /* 1962 * Driver is now in state NCR_CONNECTED, i.e. we 1963 * have a current command working the SCSI bus. 1964 */ 1965 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1966 panic("ncr53c9x: no nexus"); 1967 } 1968 1969 switch (sc->sc_phase) { 1970 case MESSAGE_OUT_PHASE: 1971 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1972 ncr53c9x_msgout(sc); 1973 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1974 break; 1975 case MESSAGE_IN_PHASE: 1976 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1977 sc->sc_prevphase = MESSAGE_IN_PHASE; 1978 if (sc->sc_espintr & NCRINTR_BS) { 1979 NCRCMD(sc, NCRCMD_FLUSH); 1980 sc->sc_flags |= NCR_WAITI; 1981 NCRCMD(sc, NCRCMD_TRANS); 1982 } else if (sc->sc_espintr & NCRINTR_FC) { 1983 if ((sc->sc_flags & NCR_WAITI) == 0) { 1984 printf("%s: MSGIN: unexpected FC bit: " 1985 "[intr %x, stat %x, step %x]\n", 1986 sc->sc_dev.dv_xname, 1987 sc->sc_espintr, sc->sc_espstat, 1988 sc->sc_espstep); 1989 } 1990 sc->sc_flags &= ~NCR_WAITI; 1991 ncr53c9x_msgin(sc); 1992 } else { 1993 printf("%s: MSGIN: weird bits: " 1994 "[intr %x, stat %x, step %x]\n", 1995 sc->sc_dev.dv_xname, 1996 sc->sc_espintr, sc->sc_espstat, 1997 sc->sc_espstep); 1998 } 1999 goto shortcut; /* i.e. expect data to be ready */ 2000 break; 2001 case COMMAND_PHASE: 2002 /* 2003 * Send the command block. Normally we don't see this 2004 * phase because the SEL_ATN command takes care of 2005 * all this. However, we end up here if either the 2006 * target or we wanted to exchange some more messages 2007 * first (e.g. to start negotiations). 2008 */ 2009 2010 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2011 ecb->cmd.cmd.opcode, ecb->clen)); 2012 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2013 NCRCMD(sc, NCRCMD_FLUSH); 2014 DELAY(1); 2015 } 2016 if (ncr53c9x_dmaselect) { 2017 size_t size; 2018 /* setup DMA transfer for command */ 2019 size = ecb->clen; 2020 sc->sc_cmdlen = size; 2021 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2022 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2023 0, &size); 2024 /* Program the SCSI counter */ 2025 NCR_WRITE_REG(sc, NCR_TCL, size); 2026 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2027 if (sc->sc_cfg2 & NCRCFG2_FE) { 2028 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2029 } 2030 2031 /* load the count in */ 2032 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2033 2034 /* start the command transfer */ 2035 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2036 NCRDMA_GO(sc); 2037 } else { 2038 u_char *cmd = (u_char *)&ecb->cmd.cmd; 2039 int i; 2040 /* Now the command into the FIFO */ 2041 for (i = 0; i < ecb->clen; i++) 2042 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 2043 NCRCMD(sc, NCRCMD_TRANS); 2044 } 2045 sc->sc_prevphase = COMMAND_PHASE; 2046 break; 2047 case DATA_OUT_PHASE: 2048 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 2049 NCRCMD(sc, NCRCMD_FLUSH); 2050 size = min(sc->sc_dleft, sc->sc_maxxfer); 2051 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2052 0, &size); 2053 sc->sc_prevphase = DATA_OUT_PHASE; 2054 goto setup_xfer; 2055 case DATA_IN_PHASE: 2056 NCR_PHASE(("DATA_IN_PHASE ")); 2057 if (sc->sc_rev == NCR_VARIANT_ESP100) 2058 NCRCMD(sc, NCRCMD_FLUSH); 2059 size = min(sc->sc_dleft, sc->sc_maxxfer); 2060 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2061 1, &size); 2062 sc->sc_prevphase = DATA_IN_PHASE; 2063 setup_xfer: 2064 /* Target returned to data phase: wipe "done" memory */ 2065 ecb->flags &= ~ECB_TENTATIVE_DONE; 2066 2067 /* Program the SCSI counter */ 2068 NCR_WRITE_REG(sc, NCR_TCL, size); 2069 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2070 if (sc->sc_cfg2 & NCRCFG2_FE) { 2071 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2072 } 2073 /* load the count in */ 2074 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2075 2076 /* 2077 * Note that if `size' is 0, we've already transceived 2078 * all the bytes we want but we're still in DATA PHASE. 2079 * Apparently, the device needs padding. Also, a 2080 * transfer size of 0 means "maximum" to the chip 2081 * DMA logic. 2082 */ 2083 NCRCMD(sc, 2084 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 2085 NCRDMA_GO(sc); 2086 return (1); 2087 case STATUS_PHASE: 2088 NCR_PHASE(("STATUS_PHASE ")); 2089 sc->sc_flags |= NCR_ICCS; 2090 NCRCMD(sc, NCRCMD_ICCS); 2091 sc->sc_prevphase = STATUS_PHASE; 2092 goto shortcut; /* i.e. expect status results soon */ 2093 break; 2094 case INVALID_PHASE: 2095 break; 2096 default: 2097 printf("%s: unexpected bus phase; resetting\n", 2098 sc->sc_dev.dv_xname); 2099 goto reset; 2100 } 2101 2102 out: 2103 return (1); 2104 2105 reset: 2106 ncr53c9x_init(sc, 1); 2107 goto out; 2108 2109 finish: 2110 ncr53c9x_done(sc, ecb); 2111 goto out; 2112 2113 sched: 2114 sc->sc_state = NCR_IDLE; 2115 ncr53c9x_sched(sc); 2116 goto out; 2117 2118 shortcut: 2119 /* 2120 * The idea is that many of the SCSI operations take very little 2121 * time, and going away and getting interrupted is too high an 2122 * overhead to pay. For example, selecting, sending a message 2123 * and command and then doing some work can be done in one "pass". 2124 * 2125 * The delay is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 2126 * at 40Mhz. This needs testing. 2127 */ 2128 DELAY(50/sc->sc_freq); 2129 if (NCRDMA_ISINTR(sc)) 2130 goto again; 2131 goto out; 2132 } 2133 2134 void 2135 ncr53c9x_abort(sc, ecb) 2136 struct ncr53c9x_softc *sc; 2137 struct ncr53c9x_ecb *ecb; 2138 { 2139 2140 /* 2 secs for the abort */ 2141 ecb->timeout = NCR_ABORT_TIMEOUT; 2142 ecb->flags |= ECB_ABORT; 2143 2144 if (ecb == sc->sc_nexus) { 2145 /* 2146 * If we're still selecting, the message will be scheduled 2147 * after selection is complete. 2148 */ 2149 if (sc->sc_state == NCR_CONNECTED) 2150 ncr53c9x_sched_msgout(SEND_ABORT); 2151 2152 /* 2153 * Reschedule timeout. First, cancel a queued timeout (if any) 2154 * in case someone decides to call ncr53c9x_abort() from 2155 * elsewhere. 2156 */ 2157 untimeout(ncr53c9x_timeout, ecb); 2158 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 2159 } else { 2160 /* The command should be on the nexus list */ 2161 if ((ecb->flags & ECB_NEXUS) == 0) { 2162 scsi_print_addr(ecb->xs->sc_link); 2163 printf("ncr53c9x_abort: not NEXUS\n"); 2164 ncr53c9x_init(sc, 1); 2165 } 2166 /* 2167 * Just leave the command on the nexus list. 2168 * XXX - what choice do we have but to reset the SCSI 2169 * eventually? 2170 */ 2171 if (sc->sc_state == NCR_IDLE) 2172 ncr53c9x_sched(sc); 2173 } 2174 } 2175 2176 void 2177 ncr53c9x_timeout(arg) 2178 void *arg; 2179 { 2180 struct ncr53c9x_ecb *ecb = arg; 2181 struct scsipi_xfer *xs = ecb->xs; 2182 struct scsipi_link *sc_link = xs->sc_link; 2183 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 2184 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 2185 int s; 2186 2187 scsi_print_addr(sc_link); 2188 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2189 "<state %d, nexus %p, phase(l %x, c %x, p %x), resid %lx, " 2190 "msg(q %x,o %x) %s>", 2191 sc->sc_dev.dv_xname, 2192 ecb, ecb->flags, ecb->dleft, ecb->stat, 2193 sc->sc_state, sc->sc_nexus, 2194 NCR_READ_REG(sc, NCR_STAT), 2195 sc->sc_phase, sc->sc_prevphase, 2196 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2197 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2198 #if NCR53C9X_DEBUG > 1 2199 printf("TRACE: %s.", ecb->trace); 2200 #endif 2201 2202 s = splbio(); 2203 2204 if (ecb->flags & ECB_ABORT) { 2205 /* abort timed out */ 2206 printf(" AGAIN\n"); 2207 2208 ncr53c9x_init(sc, 1); 2209 } else { 2210 /* abort the operation that has timed out */ 2211 printf("\n"); 2212 xs->error = XS_TIMEOUT; 2213 ncr53c9x_abort(sc, ecb); 2214 2215 /* Disable sync mode if stuck in a data phase */ 2216 if (ecb == sc->sc_nexus && 2217 (ti->flags & T_SYNCMODE) != 0 && 2218 (sc->sc_phase & (MSGI|CDI)) == 0) { 2219 scsi_print_addr(sc_link); 2220 printf("sync negotiation disabled\n"); 2221 sc->sc_cfflags |= (1<<(sc_link->scsipi_scsi.target+8)); 2222 } 2223 } 2224 2225 splx(s); 2226 } 2227
Indexes created Fri Sep 26 20:09:58 GMT 2025