ncr53c9x.c revision 1.49
1 /* $NetBSD: ncr53c9x.c,v 1.49 2000/03/29 13:57:51 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1994 Peter Galbavy 41 * Copyright (c) 1995 Paul Kranenburg 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/kernel.h> 84 #include <sys/errno.h> 85 #include <sys/ioctl.h> 86 #include <sys/device.h> 87 #include <sys/buf.h> 88 #include <sys/malloc.h> 89 #include <sys/proc.h> 90 #include <sys/user.h> 91 #include <sys/queue.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <machine/cpu.h> 99 100 #include <dev/ic/ncr53c9xreg.h> 101 #include <dev/ic/ncr53c9xvar.h> 102 103 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 104 105 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 106 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 107 struct ncr53c9x_ecb *)); 108 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 109 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 110 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 111 struct scsipi_xfer *, int)); 112 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 113 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 114 struct ncr53c9x_ecb *)); 115 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 116 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 117 /*static*/ void ncr53c9x_timeout __P((void *arg)); 118 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 119 struct ncr53c9x_ecb *)); 120 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 121 struct ncr53c9x_ecb *)); 122 123 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 124 struct ncr53c9x_ecb *)); 125 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 126 struct ncr53c9x_ecb *, int)); 127 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 128 129 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 130 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 131 struct ncr53c9x_tinfo *)); 132 133 /* 134 * Names for the NCR53c9x variants, correspnding to the variant tags 135 * in ncr53c9xvar.h. 136 */ 137 const char *ncr53c9x_variant_names[] = { 138 "ESP100", 139 "ESP100A", 140 "ESP200", 141 "NCR53C94", 142 "NCR53C96", 143 "ESP406", 144 "FAS408", 145 "FAS216", 146 "AM53C974", 147 }; 148 149 /* 150 * Attach this instance, and then all the sub-devices 151 */ 152 void 153 ncr53c9x_attach(sc, dev) 154 struct ncr53c9x_softc *sc; 155 struct scsipi_device *dev; 156 { 157 158 /* 159 * Allocate SCSI message buffers. 160 * Front-ends can override allocation to avoid alignment 161 * handling in the DMA engines. Note that that ncr53c9x_msgout() 162 * can request a 1 byte DMA transfer. 163 */ 164 if (sc->sc_omess == NULL) 165 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 166 167 if (sc->sc_imess == NULL) 168 sc->sc_imess = malloc(NCR_MAX_MSG_LEN+1, M_DEVBUF, M_NOWAIT); 169 170 if (sc->sc_omess == NULL || sc->sc_imess == NULL) { 171 printf("out of memory\n"); 172 return; 173 } 174 175 /* 176 * Note, the front-end has set us up to print the chip variation. 177 */ 178 if (sc->sc_rev >= NCR_VARIANT_MAX) { 179 printf("\n%s: unknown variant %d, devices not attached\n", 180 sc->sc_dev.dv_xname, sc->sc_rev); 181 return; 182 } 183 184 printf(": %s, %dMHz, SCSI ID %d\n", 185 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 186 187 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 188 189 /* The value *must not* be == 1. Make it 2 */ 190 if (sc->sc_ccf == 1) 191 sc->sc_ccf = 2; 192 193 /* 194 * The recommended timeout is 250ms. This register is loaded 195 * with a value calculated as follows, from the docs: 196 * 197 * (timout period) x (CLK frequency) 198 * reg = ------------------------------------- 199 * 8192 x (Clock Conversion Factor) 200 * 201 * Since CCF has a linear relation to CLK, this generally computes 202 * to the constant of 153. 203 */ 204 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 205 206 /* CCF register only has 3 bits; 0 is actually 8 */ 207 sc->sc_ccf &= 7; 208 209 /* 210 * fill in the prototype scsipi_link. 211 */ 212 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 213 sc->sc_link.adapter_softc = sc; 214 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 215 sc->sc_link.adapter = &sc->sc_adapter; 216 sc->sc_link.device = dev; 217 sc->sc_link.openings = 2; 218 sc->sc_link.scsipi_scsi.max_target = 7; 219 sc->sc_link.scsipi_scsi.max_lun = 7; 220 sc->sc_link.type = BUS_SCSI; 221 222 /* 223 * Add reference to adapter so that we drop the reference after 224 * config_found() to make sure the adatper is disabled. 225 */ 226 if (scsipi_adapter_addref(&sc->sc_link) != 0) { 227 printf("%s: unable to enable controller\n", 228 sc->sc_dev.dv_xname); 229 return; 230 } 231 232 /* Reset state & bus */ 233 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 234 sc->sc_state = 0; 235 ncr53c9x_init(sc, 1); 236 237 /* 238 * Now try to attach all the sub-devices 239 */ 240 sc->sc_child = config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 241 242 scsipi_adapter_delref(&sc->sc_link); 243 } 244 245 int 246 ncr53c9x_detach(sc, flags) 247 struct ncr53c9x_softc *sc; 248 int flags; 249 { 250 int error; 251 252 if (sc->sc_child) { 253 error = config_detach(sc->sc_child, flags); 254 if (error) 255 return (error); 256 } 257 258 free(sc->sc_imess, M_DEVBUF); 259 free(sc->sc_omess, M_DEVBUF); 260 261 return (0); 262 } 263 264 /* 265 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus, 266 * only this controller, but kills any on-going commands, and also stops 267 * and resets the DMA. 268 * 269 * After reset, registers are loaded with the defaults from the attach 270 * routine above. 271 */ 272 void 273 ncr53c9x_reset(sc) 274 struct ncr53c9x_softc *sc; 275 { 276 277 /* reset DMA first */ 278 NCRDMA_RESET(sc); 279 280 /* reset SCSI chip */ 281 NCRCMD(sc, NCRCMD_RSTCHIP); 282 NCRCMD(sc, NCRCMD_NOP); 283 DELAY(500); 284 285 /* do these backwards, and fall through */ 286 switch (sc->sc_rev) { 287 case NCR_VARIANT_ESP406: 288 case NCR_VARIANT_FAS408: 289 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT); 290 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4); 291 case NCR_VARIANT_AM53C974: 292 case NCR_VARIANT_FAS216: 293 case NCR_VARIANT_NCR53C94: 294 case NCR_VARIANT_NCR53C96: 295 case NCR_VARIANT_ESP200: 296 sc->sc_features |= NCR_F_HASCFG3; 297 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 298 case NCR_VARIANT_ESP100A: 299 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 300 case NCR_VARIANT_ESP100: 301 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 302 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 303 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 304 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 305 break; 306 default: 307 printf("%s: unknown revision code, assuming ESP100\n", 308 sc->sc_dev.dv_xname); 309 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 310 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 311 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 312 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 313 } 314 315 if (sc->sc_rev == NCR_VARIANT_AM53C974) 316 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4); 317 } 318 319 /* 320 * Reset the SCSI bus, but not the chip 321 */ 322 void 323 ncr53c9x_scsi_reset(sc) 324 struct ncr53c9x_softc *sc; 325 { 326 327 (*sc->sc_glue->gl_dma_stop)(sc); 328 329 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 330 NCRCMD(sc, NCRCMD_RSTSCSI); 331 } 332 333 /* 334 * Initialize ncr53c9x state machine 335 */ 336 void 337 ncr53c9x_init(sc, doreset) 338 struct ncr53c9x_softc *sc; 339 int doreset; 340 { 341 struct ncr53c9x_ecb *ecb; 342 int r; 343 344 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 345 346 if (sc->sc_state == 0) { 347 /* First time through; initialize. */ 348 TAILQ_INIT(&sc->ready_list); 349 TAILQ_INIT(&sc->nexus_list); 350 TAILQ_INIT(&sc->free_list); 351 sc->sc_nexus = NULL; 352 ecb = sc->sc_ecb; 353 bzero(ecb, sizeof(sc->sc_ecb)); 354 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 355 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 356 ecb++; 357 } 358 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 359 } else { 360 /* Cancel any active commands. */ 361 sc->sc_state = NCR_CLEANING; 362 if ((ecb = sc->sc_nexus) != NULL) { 363 ecb->xs->error = XS_TIMEOUT; 364 ncr53c9x_done(sc, ecb); 365 } 366 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 367 ecb->xs->error = XS_TIMEOUT; 368 ncr53c9x_done(sc, ecb); 369 } 370 } 371 372 /* 373 * reset the chip to a known state 374 */ 375 ncr53c9x_reset(sc); 376 377 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 378 for (r = 0; r < 8; r++) { 379 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 380 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 381 382 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8)))) 383 ? T_NEGOTIATE : 0) | 384 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) | 385 T_NEED_TO_RESET; 386 ti->period = sc->sc_minsync; 387 ti->offset = 0; 388 } 389 390 if (doreset) { 391 sc->sc_state = NCR_SBR; 392 NCRCMD(sc, NCRCMD_RSTSCSI); 393 } else { 394 sc->sc_state = NCR_IDLE; 395 ncr53c9x_sched(sc); 396 } 397 } 398 399 /* 400 * Read the NCR registers, and save their contents for later use. 401 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 402 * NCR_INTR - so make sure it is the last read. 403 * 404 * I think that (from reading the docs) most bits in these registers 405 * only make sense when he DMA CSR has an interrupt showing. Call only 406 * if an interrupt is pending. 407 */ 408 __inline__ void 409 ncr53c9x_readregs(sc) 410 struct ncr53c9x_softc *sc; 411 { 412 413 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 414 /* Only the stepo bits are of interest */ 415 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 416 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 417 418 if (sc->sc_glue->gl_clear_latched_intr != NULL) 419 (*sc->sc_glue->gl_clear_latched_intr)(sc); 420 421 /* 422 * Determine the SCSI bus phase, return either a real SCSI bus phase 423 * or some pseudo phase we use to detect certain exceptions. 424 */ 425 426 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 427 ? /* Disconnected */ BUSFREE_PHASE 428 : sc->sc_espstat & NCRSTAT_PHASE; 429 430 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 431 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 432 } 433 434 /* 435 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 436 */ 437 static inline int 438 ncr53c9x_stp2cpb(sc, period) 439 struct ncr53c9x_softc *sc; 440 int period; 441 { 442 int v; 443 v = (sc->sc_freq * period) / 250; 444 if (ncr53c9x_cpb2stp(sc, v) < period) 445 /* Correct round-down error */ 446 v++; 447 return (v); 448 } 449 450 static inline void 451 ncr53c9x_setsync(sc, ti) 452 struct ncr53c9x_softc *sc; 453 struct ncr53c9x_tinfo *ti; 454 { 455 u_char syncoff, synctp, cfg3 = sc->sc_cfg3; 456 457 if (ti->flags & T_SYNCMODE) { 458 syncoff = ti->offset; 459 synctp = ncr53c9x_stp2cpb(sc, ti->period); 460 if (sc->sc_features & NCR_F_FASTSCSI) { 461 /* 462 * If the period is 200ns or less (ti->period <= 50), 463 * put the chip in Fast SCSI mode. 464 */ 465 if (ti->period <= 50) 466 /* 467 * There are (at least) 4 variations of the 468 * configuration 3 register. The drive attach 469 * routine sets the appropriate bit to put the 470 * chip into Fast SCSI mode so that it doesn't 471 * have to be figured out here each time. 472 */ 473 cfg3 |= sc->sc_cfg3_fscsi; 474 } 475 476 /* 477 * Am53c974 requires different SYNCTP values when the 478 * FSCSI bit is off. 479 */ 480 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 481 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 482 synctp--; 483 } else { 484 syncoff = 0; 485 synctp = 0; 486 } 487 488 if (sc->sc_features & NCR_F_HASCFG3) 489 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 490 491 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 492 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 493 } 494 495 int ncr53c9x_dmaselect = 0; 496 /* 497 * Send a command to a target, set the driver state to NCR_SELECTING 498 * and let the caller take care of the rest. 499 * 500 * Keeping this as a function allows me to say that this may be done 501 * by DMA instead of programmed I/O soon. 502 */ 503 void 504 ncr53c9x_select(sc, ecb) 505 struct ncr53c9x_softc *sc; 506 struct ncr53c9x_ecb *ecb; 507 { 508 struct scsipi_link *sc_link = ecb->xs->sc_link; 509 int target = sc_link->scsipi_scsi.target; 510 int lun = sc_link->scsipi_scsi.lun; 511 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 512 int tiflags = ti->flags; 513 u_char *cmd; 514 int clen; 515 size_t dmasize; 516 517 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 518 target, lun, ecb->cmd.cmd.opcode)); 519 520 sc->sc_state = NCR_SELECTING; 521 522 /* 523 * Schedule the timeout now, the first time we will go away 524 * expecting to come back due to an interrupt, because it is 525 * always possible that the interrupt may never happen. 526 */ 527 if ((ecb->xs->xs_control & XS_CTL_POLL) == 0) 528 callout_reset(&ecb->xs->xs_callout, (ecb->timeout * hz) / 1000, 529 ncr53c9x_timeout, ecb); 530 531 /* 532 * The docs say the target register is never reset, and I 533 * can't think of a better place to set it 534 */ 535 NCR_WRITE_REG(sc, NCR_SELID, target); 536 ncr53c9x_setsync(sc, ti); 537 538 if (ecb->flags & ECB_SENSE) { 539 /* 540 * For REQUEST SENSE, we should not send an IDENTIFY or 541 * otherwise mangle the target. There should be no MESSAGE IN 542 * phase. 543 */ 544 if (ncr53c9x_dmaselect) { 545 /* setup DMA transfer for command */ 546 dmasize = clen = ecb->clen; 547 sc->sc_cmdlen = clen; 548 sc->sc_cmdp = (caddr_t)&ecb->cmd + 1; 549 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 550 551 /* Program the SCSI counter */ 552 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 553 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 554 if (sc->sc_cfg2 & NCRCFG2_FE) { 555 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 556 } 557 558 /* load the count in */ 559 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 560 561 /* And get the targets attention */ 562 NCRCMD(sc, NCRCMD_SELNATN | NCRCMD_DMA); 563 NCRDMA_GO(sc); 564 } else { 565 /* Now the command into the FIFO */ 566 cmd = (u_char *)&ecb->cmd.cmd; 567 clen = ecb->clen; 568 while (clen--) 569 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 570 571 NCRCMD(sc, NCRCMD_SELNATN); 572 } 573 return; 574 } 575 576 if (ncr53c9x_dmaselect && (tiflags & T_NEGOTIATE) == 0) { 577 ecb->cmd.id = 578 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1); 579 580 /* setup DMA transfer for command */ 581 dmasize = clen = ecb->clen + 1; 582 sc->sc_cmdlen = clen; 583 sc->sc_cmdp = (caddr_t)&ecb->cmd; 584 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 585 586 /* Program the SCSI counter */ 587 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 588 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 589 if (sc->sc_cfg2 & NCRCFG2_FE) { 590 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 591 } 592 593 /* load the count in */ 594 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 595 596 /* And get the targets attention */ 597 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 598 NCRDMA_GO(sc); 599 return; 600 } 601 602 /* 603 * Who am I. This is where we tell the target that we are 604 * happy for it to disconnect etc. 605 */ 606 NCR_WRITE_REG(sc, NCR_FIFO, 607 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1)); 608 609 if (ti->flags & T_NEGOTIATE) { 610 /* Arbitrate, select and stop after IDENTIFY message */ 611 NCRCMD(sc, NCRCMD_SELATNS); 612 return; 613 } 614 615 /* Now the command into the FIFO */ 616 cmd = (u_char *)&ecb->cmd.cmd; 617 clen = ecb->clen; 618 while (clen--) 619 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 620 621 /* And get the targets attention */ 622 NCRCMD(sc, NCRCMD_SELATN); 623 } 624 625 void 626 ncr53c9x_free_ecb(sc, ecb, flags) 627 struct ncr53c9x_softc *sc; 628 struct ncr53c9x_ecb *ecb; 629 int flags; 630 { 631 int s; 632 633 s = splbio(); 634 635 ecb->flags = 0; 636 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 637 638 /* 639 * If there were none, wake anybody waiting for one to come free, 640 * starting with queued entries. 641 */ 642 if (ecb->chain.tqe_next == 0) 643 wakeup(&sc->free_list); 644 645 splx(s); 646 } 647 648 struct ncr53c9x_ecb * 649 ncr53c9x_get_ecb(sc, flags) 650 struct ncr53c9x_softc *sc; 651 int flags; 652 { 653 struct ncr53c9x_ecb *ecb; 654 int s; 655 656 s = splbio(); 657 658 while ((ecb = sc->free_list.tqh_first) == NULL && 659 (flags & XS_CTL_NOSLEEP) == 0) 660 tsleep(&sc->free_list, PRIBIO, "especb", 0); 661 if (ecb) { 662 TAILQ_REMOVE(&sc->free_list, ecb, chain); 663 ecb->flags |= ECB_ALLOC; 664 } 665 666 splx(s); 667 return (ecb); 668 } 669 670 /* 671 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 672 */ 673 674 /* 675 * Start a SCSI-command 676 * This function is called by the higher level SCSI-driver to queue/run 677 * SCSI-commands. 678 */ 679 int 680 ncr53c9x_scsi_cmd(xs) 681 struct scsipi_xfer *xs; 682 { 683 struct scsipi_link *sc_link = xs->sc_link; 684 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 685 struct ncr53c9x_ecb *ecb; 686 int s, flags; 687 688 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 689 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 690 sc_link->scsipi_scsi.target)); 691 692 flags = xs->xs_control; 693 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) 694 return (TRY_AGAIN_LATER); 695 696 /* Initialize ecb */ 697 ecb->xs = xs; 698 ecb->timeout = xs->timeout; 699 700 if (flags & XS_CTL_RESET) { 701 ecb->flags |= ECB_RESET; 702 ecb->clen = 0; 703 ecb->dleft = 0; 704 } else { 705 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 706 ecb->clen = xs->cmdlen; 707 ecb->daddr = xs->data; 708 ecb->dleft = xs->datalen; 709 } 710 ecb->stat = 0; 711 712 s = splbio(); 713 714 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 715 if (sc->sc_state == NCR_IDLE) 716 ncr53c9x_sched(sc); 717 718 splx(s); 719 720 if ((flags & XS_CTL_POLL) == 0) 721 return (SUCCESSFULLY_QUEUED); 722 723 /* Not allowed to use interrupts, use polling instead */ 724 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 725 ncr53c9x_timeout(ecb); 726 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 727 ncr53c9x_timeout(ecb); 728 } 729 return (COMPLETE); 730 } 731 732 /* 733 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 734 */ 735 int 736 ncr53c9x_poll(sc, xs, count) 737 struct ncr53c9x_softc *sc; 738 struct scsipi_xfer *xs; 739 int count; 740 { 741 742 NCR_TRACE(("[ncr53c9x_poll] ")); 743 while (count) { 744 if (NCRDMA_ISINTR(sc)) { 745 ncr53c9x_intr(sc); 746 } 747 #if alternatively 748 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 749 ncr53c9x_intr(sc); 750 #endif 751 if ((xs->xs_status & XS_STS_DONE) != 0) 752 return (0); 753 if (sc->sc_state == NCR_IDLE) { 754 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 755 ncr53c9x_sched(sc); 756 } 757 DELAY(1000); 758 count--; 759 } 760 return (1); 761 } 762 763 764 /* 765 * LOW LEVEL SCSI UTILITIES 766 */ 767 768 /* 769 * Schedule a scsi operation. This has now been pulled out of the interrupt 770 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 771 * This may save us an unecessary interrupt just to get things going. 772 * Should only be called when state == NCR_IDLE and at bio pl. 773 */ 774 void 775 ncr53c9x_sched(sc) 776 struct ncr53c9x_softc *sc; 777 { 778 struct ncr53c9x_ecb *ecb; 779 struct scsipi_link *sc_link; 780 struct ncr53c9x_tinfo *ti; 781 782 NCR_TRACE(("[ncr53c9x_sched] ")); 783 if (sc->sc_state != NCR_IDLE) 784 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 785 786 /* 787 * Find first ecb in ready queue that is for a target/lunit 788 * combinations that is not busy. 789 */ 790 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 791 sc_link = ecb->xs->sc_link; 792 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 793 if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) { 794 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 795 sc->sc_nexus = ecb; 796 ncr53c9x_select(sc, ecb); 797 break; 798 } else 799 NCR_MISC(("%d:%d busy\n", 800 sc_link->scsipi_scsi.target, 801 sc_link->scsipi_scsi.lun)); 802 } 803 } 804 805 void 806 ncr53c9x_sense(sc, ecb) 807 struct ncr53c9x_softc *sc; 808 struct ncr53c9x_ecb *ecb; 809 { 810 struct scsipi_xfer *xs = ecb->xs; 811 struct scsipi_link *sc_link = xs->sc_link; 812 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 813 struct scsipi_sense *ss = (void *)&ecb->cmd.cmd; 814 815 NCR_MISC(("requesting sense ")); 816 /* Next, setup a request sense command block */ 817 bzero(ss, sizeof(*ss)); 818 ss->opcode = REQUEST_SENSE; 819 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 820 ss->length = sizeof(struct scsipi_sense_data); 821 ecb->clen = sizeof(*ss); 822 ecb->daddr = (char *)&xs->sense.scsi_sense; 823 ecb->dleft = sizeof(struct scsipi_sense_data); 824 ecb->flags |= ECB_SENSE; 825 ecb->timeout = NCR_SENSE_TIMEOUT; 826 ti->senses++; 827 if (ecb->flags & ECB_NEXUS) 828 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 829 if (ecb == sc->sc_nexus) { 830 ecb->flags &= ~ECB_NEXUS; 831 ncr53c9x_select(sc, ecb); 832 } else { 833 ncr53c9x_dequeue(sc, ecb); 834 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 835 if (sc->sc_state == NCR_IDLE) 836 ncr53c9x_sched(sc); 837 } 838 } 839 840 /* 841 * POST PROCESSING OF SCSI_CMD (usually current) 842 */ 843 void 844 ncr53c9x_done(sc, ecb) 845 struct ncr53c9x_softc *sc; 846 struct ncr53c9x_ecb *ecb; 847 { 848 struct scsipi_xfer *xs = ecb->xs; 849 struct scsipi_link *sc_link = xs->sc_link; 850 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 851 852 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 853 854 callout_stop(&ecb->xs->xs_callout); 855 856 /* 857 * Now, if we've come here with no error code, i.e. we've kept the 858 * initial XS_NOERROR, and the status code signals that we should 859 * check sense, we'll need to set up a request sense cmd block and 860 * push the command back into the ready queue *before* any other 861 * commands for this target/lunit, else we lose the sense info. 862 * We don't support chk sense conditions for the request sense cmd. 863 */ 864 if (xs->error == XS_NOERROR) { 865 xs->status = ecb->stat; 866 if ((ecb->flags & ECB_ABORT) != 0) { 867 xs->error = XS_TIMEOUT; 868 } else if ((ecb->flags & ECB_SENSE) != 0) { 869 xs->error = XS_SENSE; 870 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 871 /* First, save the return values */ 872 xs->resid = ecb->dleft; 873 ncr53c9x_sense(sc, ecb); 874 return; 875 } else { 876 xs->resid = ecb->dleft; 877 } 878 } 879 880 xs->xs_status |= XS_STS_DONE; 881 882 #ifdef NCR53C9X_DEBUG 883 if (ncr53c9x_debug & NCR_SHOWMISC) { 884 if (xs->resid != 0) 885 printf("resid=%d ", xs->resid); 886 if (xs->error == XS_SENSE) 887 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 888 else 889 printf("error=%d\n", xs->error); 890 } 891 #endif 892 893 /* 894 * Remove the ECB from whatever queue it's on. 895 */ 896 if (ecb->flags & ECB_NEXUS) 897 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 898 if (ecb == sc->sc_nexus) { 899 sc->sc_nexus = NULL; 900 if (sc->sc_state != NCR_CLEANING) { 901 sc->sc_state = NCR_IDLE; 902 ncr53c9x_sched(sc); 903 } 904 } else 905 ncr53c9x_dequeue(sc, ecb); 906 907 ncr53c9x_free_ecb(sc, ecb, xs->xs_control); 908 ti->cmds++; 909 scsipi_done(xs); 910 } 911 912 void 913 ncr53c9x_dequeue(sc, ecb) 914 struct ncr53c9x_softc *sc; 915 struct ncr53c9x_ecb *ecb; 916 { 917 918 if (ecb->flags & ECB_NEXUS) { 919 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 920 ecb->flags &= ~ECB_NEXUS; 921 } else { 922 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 923 } 924 } 925 926 /* 927 * INTERRUPT/PROTOCOL ENGINE 928 */ 929 930 /* 931 * Schedule an outgoing message by prioritizing it, and asserting 932 * attention on the bus. We can only do this when we are the initiator 933 * else there will be an illegal command interrupt. 934 */ 935 #define ncr53c9x_sched_msgout(m) \ 936 do { \ 937 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 938 NCRCMD(sc, NCRCMD_SETATN); \ 939 sc->sc_flags |= NCR_ATN; \ 940 sc->sc_msgpriq |= (m); \ 941 } while (0) 942 943 int 944 ncr53c9x_reselect(sc, message) 945 struct ncr53c9x_softc *sc; 946 int message; 947 { 948 u_char selid, target, lun; 949 struct ncr53c9x_ecb *ecb; 950 struct scsipi_link *sc_link; 951 struct ncr53c9x_tinfo *ti; 952 953 /* 954 * The SCSI chip made a snapshot of the data bus while the reselection 955 * was being negotiated. This enables us to determine which target did 956 * the reselect. 957 */ 958 selid = sc->sc_selid & ~(1 << sc->sc_id); 959 if (selid & (selid - 1)) { 960 printf("%s: reselect with invalid selid %02x;" 961 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 962 goto reset; 963 } 964 965 /* 966 * Search wait queue for disconnected cmd 967 * The list should be short, so I haven't bothered with 968 * any more sophisticated structures than a simple 969 * singly linked list. 970 */ 971 target = ffs(selid) - 1; 972 lun = message & 0x07; 973 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 974 ecb = ecb->chain.tqe_next) { 975 sc_link = ecb->xs->sc_link; 976 if (sc_link->scsipi_scsi.target == target && 977 sc_link->scsipi_scsi.lun == lun) 978 break; 979 } 980 if (ecb == NULL) { 981 printf("%s: reselect from target %d lun %d with no nexus;" 982 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 983 goto abort; 984 } 985 986 /* Make this nexus active again. */ 987 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 988 sc->sc_state = NCR_CONNECTED; 989 sc->sc_nexus = ecb; 990 ti = &sc->sc_tinfo[target]; 991 #ifdef NCR53C9X_DEBUG 992 if ((ti->lubusy & (1 << lun)) == 0) { 993 printf("%s: reselect: target %d, lun %d: should be busy\n", 994 sc->sc_dev.dv_xname, target, lun); 995 ti->lubusy |= (1 << lun); 996 } 997 #endif 998 ncr53c9x_setsync(sc, ti); 999 1000 if (ecb->flags & ECB_RESET) 1001 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1002 else if (ecb->flags & ECB_ABORT) 1003 ncr53c9x_sched_msgout(SEND_ABORT); 1004 1005 /* Do an implicit RESTORE POINTERS. */ 1006 sc->sc_dp = ecb->daddr; 1007 sc->sc_dleft = ecb->dleft; 1008 1009 return (0); 1010 1011 reset: 1012 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1013 return (1); 1014 1015 abort: 1016 ncr53c9x_sched_msgout(SEND_ABORT); 1017 return (1); 1018 } 1019 1020 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1021 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1022 #define ISEXTMSG(m) ((m) == 1) 1023 1024 /* 1025 * Get an incoming message as initiator. 1026 * 1027 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1028 * byte in the FIFO 1029 */ 1030 void 1031 ncr53c9x_msgin(sc) 1032 struct ncr53c9x_softc *sc; 1033 { 1034 int v; 1035 1036 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1037 1038 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 1039 printf("%s: msgin: no msg byte available\n", 1040 sc->sc_dev.dv_xname); 1041 return; 1042 } 1043 1044 /* 1045 * Prepare for a new message. A message should (according 1046 * to the SCSI standard) be transmitted in one single 1047 * MESSAGE_IN_PHASE. If we have been in some other phase, 1048 * then this is a new message. 1049 */ 1050 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1051 sc->sc_flags &= ~NCR_DROP_MSGI; 1052 sc->sc_imlen = 0; 1053 } 1054 1055 v = NCR_READ_REG(sc, NCR_FIFO); 1056 NCR_MISC(("<msgbyte:0x%02x>", v)); 1057 1058 #if 0 1059 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 1060 /* 1061 * Which target is reselecting us? (The ID bit really) 1062 */ 1063 sc->sc_selid = v; 1064 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1065 return; 1066 } 1067 #endif 1068 1069 sc->sc_imess[sc->sc_imlen] = v; 1070 1071 /* 1072 * If we're going to reject the message, don't bother storing 1073 * the incoming bytes. But still, we need to ACK them. 1074 */ 1075 1076 if ((sc->sc_flags & NCR_DROP_MSGI)) { 1077 NCRCMD(sc, NCRCMD_MSGOK); 1078 printf("<dropping msg byte %x>", 1079 sc->sc_imess[sc->sc_imlen]); 1080 return; 1081 } 1082 1083 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1084 ncr53c9x_sched_msgout(SEND_REJECT); 1085 sc->sc_flags |= NCR_DROP_MSGI; 1086 } else { 1087 sc->sc_imlen++; 1088 /* 1089 * This testing is suboptimal, but most 1090 * messages will be of the one byte variety, so 1091 * it should not effect performance 1092 * significantly. 1093 */ 1094 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1095 goto gotit; 1096 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1097 goto gotit; 1098 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1099 sc->sc_imlen == sc->sc_imess[1] + 2) 1100 goto gotit; 1101 } 1102 /* Ack what we have so far */ 1103 NCRCMD(sc, NCRCMD_MSGOK); 1104 return; 1105 1106 gotit: 1107 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1108 /* 1109 * Now we should have a complete message (1 byte, 2 byte 1110 * and moderately long extended messages). We only handle 1111 * extended messages which total length is shorter than 1112 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1113 */ 1114 switch (sc->sc_state) { 1115 struct ncr53c9x_ecb *ecb; 1116 struct ncr53c9x_tinfo *ti; 1117 1118 case NCR_CONNECTED: 1119 ecb = sc->sc_nexus; 1120 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1121 1122 switch (sc->sc_imess[0]) { 1123 case MSG_CMDCOMPLETE: 1124 NCR_MSGS(("cmdcomplete ")); 1125 if (sc->sc_dleft < 0) { 1126 scsi_print_addr(ecb->xs->sc_link); 1127 printf("got %ld extra bytes\n", 1128 -(long)sc->sc_dleft); 1129 sc->sc_dleft = 0; 1130 } 1131 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1132 ? 0 1133 : sc->sc_dleft; 1134 if ((ecb->flags & ECB_SENSE) == 0) 1135 ecb->xs->resid = ecb->dleft; 1136 sc->sc_state = NCR_CMDCOMPLETE; 1137 break; 1138 1139 case MSG_MESSAGE_REJECT: 1140 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1141 switch (sc->sc_msgout) { 1142 case SEND_SDTR: 1143 sc->sc_flags &= ~NCR_SYNCHNEGO; 1144 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1145 ncr53c9x_setsync(sc, ti); 1146 break; 1147 case SEND_INIT_DET_ERR: 1148 goto abort; 1149 } 1150 break; 1151 1152 case MSG_NOOP: 1153 NCR_MSGS(("noop ")); 1154 break; 1155 1156 case MSG_DISCONNECT: 1157 NCR_MSGS(("disconnect ")); 1158 ti->dconns++; 1159 sc->sc_state = NCR_DISCONNECT; 1160 1161 /* 1162 * Mark the fact that all bytes have moved. The 1163 * target may not bother to do a SAVE POINTERS 1164 * at this stage. This flag will set the residual 1165 * count to zero on MSG COMPLETE. 1166 */ 1167 if (sc->sc_dleft == 0) 1168 ecb->flags |= ECB_TENTATIVE_DONE; 1169 1170 break; 1171 1172 case MSG_SAVEDATAPOINTER: 1173 NCR_MSGS(("save datapointer ")); 1174 ecb->daddr = sc->sc_dp; 1175 ecb->dleft = sc->sc_dleft; 1176 break; 1177 1178 case MSG_RESTOREPOINTERS: 1179 NCR_MSGS(("restore datapointer ")); 1180 sc->sc_dp = ecb->daddr; 1181 sc->sc_dleft = ecb->dleft; 1182 break; 1183 1184 case MSG_EXTENDED: 1185 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1186 switch (sc->sc_imess[2]) { 1187 case MSG_EXT_SDTR: 1188 NCR_MSGS(("SDTR period %d, offset %d ", 1189 sc->sc_imess[3], sc->sc_imess[4])); 1190 if (sc->sc_imess[1] != 3) 1191 goto reject; 1192 ti->period = sc->sc_imess[3]; 1193 ti->offset = sc->sc_imess[4]; 1194 ti->flags &= ~T_NEGOTIATE; 1195 if (sc->sc_minsync == 0 || 1196 ti->offset == 0 || 1197 ti->period > 124) { 1198 #ifdef NCR53C9X_DEBUG 1199 scsi_print_addr(ecb->xs->sc_link); 1200 printf("async mode\n"); 1201 #endif 1202 if ((sc->sc_flags&NCR_SYNCHNEGO) 1203 == 0) { 1204 /* 1205 * target initiated negotiation 1206 */ 1207 ti->offset = 0; 1208 ti->flags &= ~T_SYNCMODE; 1209 ncr53c9x_sched_msgout( 1210 SEND_SDTR); 1211 } else { 1212 /* we are async */ 1213 ti->flags &= ~T_SYNCMODE; 1214 } 1215 } else { 1216 int r = 250/ti->period; 1217 int s = (100*250)/ti->period - 100*r; 1218 int p; 1219 1220 p = ncr53c9x_stp2cpb(sc, ti->period); 1221 ti->period = ncr53c9x_cpb2stp(sc, p); 1222 #ifdef NCR53C9X_DEBUG 1223 scsi_print_addr(ecb->xs->sc_link); 1224 printf("max sync rate %d.%02dMB/s\n", 1225 r, s); 1226 #endif 1227 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) { 1228 /* 1229 * target initiated negotiation 1230 */ 1231 if (ti->period < 1232 sc->sc_minsync) 1233 ti->period = 1234 sc->sc_minsync; 1235 if (ti->offset > 15) 1236 ti->offset = 15; 1237 ti->flags &= ~T_SYNCMODE; 1238 ncr53c9x_sched_msgout( 1239 SEND_SDTR); 1240 } else { 1241 /* we are sync */ 1242 ti->flags |= T_SYNCMODE; 1243 } 1244 } 1245 sc->sc_flags &= ~NCR_SYNCHNEGO; 1246 ncr53c9x_setsync(sc, ti); 1247 break; 1248 1249 default: 1250 scsi_print_addr(ecb->xs->sc_link); 1251 printf("unrecognized MESSAGE EXTENDED;" 1252 " sending REJECT\n"); 1253 goto reject; 1254 } 1255 break; 1256 1257 default: 1258 NCR_MSGS(("ident ")); 1259 scsi_print_addr(ecb->xs->sc_link); 1260 printf("unrecognized MESSAGE; sending REJECT\n"); 1261 reject: 1262 ncr53c9x_sched_msgout(SEND_REJECT); 1263 break; 1264 } 1265 break; 1266 1267 case NCR_RESELECTED: 1268 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1269 printf("%s: reselect without IDENTIFY;" 1270 " sending DEVICE RESET\n", 1271 sc->sc_dev.dv_xname); 1272 goto reset; 1273 } 1274 1275 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1276 break; 1277 1278 default: 1279 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1280 sc->sc_dev.dv_xname); 1281 reset: 1282 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1283 break; 1284 1285 abort: 1286 ncr53c9x_sched_msgout(SEND_ABORT); 1287 break; 1288 } 1289 1290 /* Ack last message byte */ 1291 NCRCMD(sc, NCRCMD_MSGOK); 1292 1293 /* Done, reset message pointer. */ 1294 sc->sc_flags &= ~NCR_DROP_MSGI; 1295 sc->sc_imlen = 0; 1296 } 1297 1298 1299 /* 1300 * Send the highest priority, scheduled message 1301 */ 1302 void 1303 ncr53c9x_msgout(sc) 1304 struct ncr53c9x_softc *sc; 1305 { 1306 struct ncr53c9x_tinfo *ti; 1307 struct ncr53c9x_ecb *ecb; 1308 size_t size; 1309 1310 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1311 sc->sc_msgpriq, sc->sc_prevphase)); 1312 1313 /* 1314 * XXX - the NCR_ATN flag is not in sync with the actual ATN 1315 * condition on the SCSI bus. The 53c9x chip 1316 * automatically turns off ATN before sending the 1317 * message byte. (see also the comment below in the 1318 * default case when picking out a message to send) 1319 */ 1320 if (sc->sc_flags & NCR_ATN) { 1321 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1322 new: 1323 NCRCMD(sc, NCRCMD_FLUSH); 1324 DELAY(1); 1325 sc->sc_msgoutq = 0; 1326 sc->sc_omlen = 0; 1327 } 1328 } else { 1329 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1330 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1331 goto new; 1332 } else { 1333 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1334 sc->sc_dev.dv_xname, __LINE__); 1335 } 1336 } 1337 1338 if (sc->sc_omlen == 0) { 1339 /* Pick up highest priority message */ 1340 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1341 sc->sc_msgoutq |= sc->sc_msgout; 1342 sc->sc_msgpriq &= ~sc->sc_msgout; 1343 sc->sc_omlen = 1; /* "Default" message len */ 1344 switch (sc->sc_msgout) { 1345 case SEND_SDTR: 1346 ecb = sc->sc_nexus; 1347 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1348 sc->sc_omess[0] = MSG_EXTENDED; 1349 sc->sc_omess[1] = 3; 1350 sc->sc_omess[2] = MSG_EXT_SDTR; 1351 sc->sc_omess[3] = ti->period; 1352 sc->sc_omess[4] = ti->offset; 1353 sc->sc_omlen = 5; 1354 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1355 ti->flags |= T_SYNCMODE; 1356 ncr53c9x_setsync(sc, ti); 1357 } 1358 break; 1359 case SEND_IDENTIFY: 1360 if (sc->sc_state != NCR_CONNECTED) { 1361 printf("%s at line %d: no nexus\n", 1362 sc->sc_dev.dv_xname, __LINE__); 1363 } 1364 ecb = sc->sc_nexus; 1365 sc->sc_omess[0] = 1366 MSG_IDENTIFY(ecb->xs->sc_link->scsipi_scsi.lun, 0); 1367 break; 1368 case SEND_DEV_RESET: 1369 sc->sc_flags |= NCR_ABORTING; 1370 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1371 ecb = sc->sc_nexus; 1372 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1373 ti->flags &= ~T_SYNCMODE; 1374 ti->flags |= T_NEGOTIATE; 1375 break; 1376 case SEND_PARITY_ERROR: 1377 sc->sc_omess[0] = MSG_PARITY_ERROR; 1378 break; 1379 case SEND_ABORT: 1380 sc->sc_flags |= NCR_ABORTING; 1381 sc->sc_omess[0] = MSG_ABORT; 1382 break; 1383 case SEND_INIT_DET_ERR: 1384 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1385 break; 1386 case SEND_REJECT: 1387 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1388 break; 1389 default: 1390 /* 1391 * We normally do not get here, since the chip 1392 * automatically turns off ATN before the last 1393 * byte of a message is sent to the target. 1394 * However, if the target rejects our (multi-byte) 1395 * message early by switching to MSG IN phase 1396 * ATN remains on, so the target may return to 1397 * MSG OUT phase. If there are no scheduled messages 1398 * left we send a NO-OP. 1399 * 1400 * XXX - Note that this leaves no useful purpose for 1401 * the NCR_ATN flag. 1402 */ 1403 sc->sc_flags &= ~NCR_ATN; 1404 sc->sc_omess[0] = MSG_NOOP; 1405 break; 1406 } 1407 sc->sc_omp = sc->sc_omess; 1408 } 1409 1410 /* (re)send the message */ 1411 size = min(sc->sc_omlen, sc->sc_maxxfer); 1412 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1413 /* Program the SCSI counter */ 1414 NCR_WRITE_REG(sc, NCR_TCL, size); 1415 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1416 if (sc->sc_cfg2 & NCRCFG2_FE) { 1417 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1418 } 1419 /* Load the count in and start the message-out transfer */ 1420 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1421 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1422 NCRDMA_GO(sc); 1423 } 1424 1425 /* 1426 * This is the most critical part of the driver, and has to know 1427 * how to deal with *all* error conditions and phases from the SCSI 1428 * bus. If there are no errors and the DMA was active, then call the 1429 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1430 * and we can return from here without further processing. 1431 * 1432 * Most of this needs verifying. 1433 */ 1434 int sdebug = 0; 1435 int 1436 ncr53c9x_intr(arg) 1437 void *arg; 1438 { 1439 struct ncr53c9x_softc *sc = arg; 1440 struct ncr53c9x_ecb *ecb; 1441 struct scsipi_link *sc_link; 1442 struct ncr53c9x_tinfo *ti; 1443 size_t size; 1444 int nfifo; 1445 1446 NCR_TRACE(("[ncr53c9x_intr] ")); 1447 1448 if (!NCRDMA_ISINTR(sc)) 1449 return (0); 1450 1451 again: 1452 /* and what do the registers say... */ 1453 ncr53c9x_readregs(sc); 1454 1455 sc->sc_intrcnt.ev_count++; 1456 1457 /* 1458 * At the moment, only a SCSI Bus Reset or Illegal 1459 * Command are classed as errors. A disconnect is a 1460 * valid condition, and we let the code check is the 1461 * "NCR_BUSFREE_OK" flag was set before declaring it 1462 * and error. 1463 * 1464 * Also, the status register tells us about "Gross 1465 * Errors" and "Parity errors". Only the Gross Error 1466 * is really bad, and the parity errors are dealt 1467 * with later 1468 * 1469 * TODO 1470 * If there are too many parity error, go to slow 1471 * cable mode ? 1472 */ 1473 1474 /* SCSI Reset */ 1475 if (sc->sc_espintr & NCRINTR_SBR) { 1476 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1477 NCRCMD(sc, NCRCMD_FLUSH); 1478 DELAY(1); 1479 } 1480 if (sc->sc_state != NCR_SBR) { 1481 printf("%s: SCSI bus reset\n", 1482 sc->sc_dev.dv_xname); 1483 ncr53c9x_init(sc, 0); /* Restart everything */ 1484 return (1); 1485 } 1486 #if 0 1487 /*XXX*/ printf("<expected bus reset: " 1488 "[intr %x, stat %x, step %d]>\n", 1489 sc->sc_espintr, sc->sc_espstat, 1490 sc->sc_espstep); 1491 #endif 1492 if (sc->sc_nexus) 1493 panic("%s: nexus in reset state", 1494 sc->sc_dev.dv_xname); 1495 goto sched; 1496 } 1497 1498 ecb = sc->sc_nexus; 1499 1500 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1501 if (sc->sc_espintr & NCRINTR_ERR || 1502 sc->sc_espstat & NCRSTAT_GE) { 1503 1504 if (sc->sc_espstat & NCRSTAT_GE) { 1505 /* Gross Error; no target ? */ 1506 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1507 NCRCMD(sc, NCRCMD_FLUSH); 1508 DELAY(1); 1509 } 1510 if (sc->sc_state == NCR_CONNECTED || 1511 sc->sc_state == NCR_SELECTING) { 1512 ecb->xs->error = XS_TIMEOUT; 1513 ncr53c9x_done(sc, ecb); 1514 } 1515 return (1); 1516 } 1517 1518 if (sc->sc_espintr & NCRINTR_ILL) { 1519 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1520 /* 1521 * Eat away "Illegal command" interrupt 1522 * on a ESP100 caused by a re-selection 1523 * while we were trying to select 1524 * another target. 1525 */ 1526 #ifdef DEBUG 1527 printf("%s: ESP100 work-around activated\n", 1528 sc->sc_dev.dv_xname); 1529 #endif 1530 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1531 return (1); 1532 } 1533 /* illegal command, out of sync ? */ 1534 printf("%s: illegal command: 0x%x " 1535 "(state %d, phase %x, prevphase %x)\n", 1536 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1537 sc->sc_state, sc->sc_phase, 1538 sc->sc_prevphase); 1539 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1540 NCRCMD(sc, NCRCMD_FLUSH); 1541 DELAY(1); 1542 } 1543 ncr53c9x_init(sc, 1); /* Restart everything */ 1544 return (1); 1545 } 1546 } 1547 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1548 1549 /* 1550 * Call if DMA is active. 1551 * 1552 * If DMA_INTR returns true, then maybe go 'round the loop 1553 * again in case there is no more DMA queued, but a phase 1554 * change is expected. 1555 */ 1556 if (NCRDMA_ISACTIVE(sc)) { 1557 int r = NCRDMA_INTR(sc); 1558 if (r == -1) { 1559 printf("%s: DMA error; resetting\n", 1560 sc->sc_dev.dv_xname); 1561 ncr53c9x_init(sc, 1); 1562 } 1563 /* If DMA active here, then go back to work... */ 1564 if (NCRDMA_ISACTIVE(sc)) 1565 return (1); 1566 1567 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 1568 /* 1569 * DMA not completed. If we can not find a 1570 * acceptable explanation, print a diagnostic. 1571 */ 1572 if (sc->sc_state == NCR_SELECTING) 1573 /* 1574 * This can happen if we are reselected 1575 * while using DMA to select a target. 1576 */ 1577 /*void*/; 1578 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1579 /* 1580 * Our (multi-byte) message (eg SDTR) was 1581 * interrupted by the target to send 1582 * a MSG REJECT. 1583 * Print diagnostic if current phase 1584 * is not MESSAGE IN. 1585 */ 1586 if (sc->sc_phase != MESSAGE_IN_PHASE) 1587 printf("%s: !TC on MSG OUT" 1588 " [intr %x, stat %x, step %d]" 1589 " prevphase %x, resid %lx\n", 1590 sc->sc_dev.dv_xname, 1591 sc->sc_espintr, 1592 sc->sc_espstat, 1593 sc->sc_espstep, 1594 sc->sc_prevphase, 1595 (u_long)sc->sc_omlen); 1596 } else if (sc->sc_dleft == 0) { 1597 /* 1598 * The DMA operation was started for 1599 * a DATA transfer. Print a diagnostic 1600 * if the DMA counter and TC bit 1601 * appear to be out of sync. 1602 */ 1603 printf("%s: !TC on DATA XFER" 1604 " [intr %x, stat %x, step %d]" 1605 " prevphase %x, resid %x\n", 1606 sc->sc_dev.dv_xname, 1607 sc->sc_espintr, 1608 sc->sc_espstat, 1609 sc->sc_espstep, 1610 sc->sc_prevphase, 1611 ecb?ecb->dleft:-1); 1612 } 1613 } 1614 } 1615 1616 /* 1617 * Check for less serious errors. 1618 */ 1619 if (sc->sc_espstat & NCRSTAT_PE) { 1620 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1621 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1622 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1623 else 1624 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1625 } 1626 1627 if (sc->sc_espintr & NCRINTR_DIS) { 1628 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1629 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1630 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1631 NCRCMD(sc, NCRCMD_FLUSH); 1632 DELAY(1); 1633 } 1634 /* 1635 * This command must (apparently) be issued within 1636 * 250mS of a disconnect. So here you are... 1637 */ 1638 NCRCMD(sc, NCRCMD_ENSEL); 1639 1640 switch (sc->sc_state) { 1641 case NCR_RESELECTED: 1642 goto sched; 1643 1644 case NCR_SELECTING: 1645 ecb->xs->error = XS_SELTIMEOUT; 1646 goto finish; 1647 1648 case NCR_CONNECTED: 1649 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1650 #ifdef NCR53C9X_DEBUG 1651 if (ecb) 1652 scsi_print_addr(ecb->xs->sc_link); 1653 printf("sync nego not completed!\n"); 1654 #endif 1655 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1656 sc->sc_flags &= ~NCR_SYNCHNEGO; 1657 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1658 } 1659 1660 /* it may be OK to disconnect */ 1661 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1662 /* 1663 * Section 5.1.1 of the SCSI 2 spec 1664 * suggests issuing a REQUEST SENSE 1665 * following an unexpected disconnect. 1666 * Some devices go into a contingent 1667 * allegiance condition when 1668 * disconnecting, and this is necessary 1669 * to clean up their state. 1670 */ 1671 printf("%s: unexpected disconnect; ", 1672 sc->sc_dev.dv_xname); 1673 if (ecb->flags & ECB_SENSE) { 1674 printf("resetting\n"); 1675 goto reset; 1676 } 1677 printf("sending REQUEST SENSE\n"); 1678 callout_stop(&ecb->xs->xs_callout); 1679 ncr53c9x_sense(sc, ecb); 1680 goto out; 1681 } 1682 1683 ecb->xs->error = XS_TIMEOUT; 1684 goto finish; 1685 1686 case NCR_DISCONNECT: 1687 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1688 sc->sc_nexus = NULL; 1689 goto sched; 1690 1691 case NCR_CMDCOMPLETE: 1692 goto finish; 1693 } 1694 } 1695 1696 switch (sc->sc_state) { 1697 1698 case NCR_SBR: 1699 printf("%s: waiting for SCSI Bus Reset to happen\n", 1700 sc->sc_dev.dv_xname); 1701 return (1); 1702 1703 case NCR_RESELECTED: 1704 /* 1705 * we must be continuing a message ? 1706 */ 1707 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1708 printf("%s: target didn't identify\n", 1709 sc->sc_dev.dv_xname); 1710 ncr53c9x_init(sc, 1); 1711 return (1); 1712 } 1713 printf("<<RESELECT CONT'd>>"); 1714 #if XXXX 1715 ncr53c9x_msgin(sc); 1716 if (sc->sc_state != NCR_CONNECTED) { 1717 /* IDENTIFY fail?! */ 1718 printf("%s: identify failed\n", 1719 sc->sc_dev.dv_xname); 1720 ncr53c9x_init(sc, 1); 1721 return (1); 1722 } 1723 #endif 1724 break; 1725 1726 case NCR_IDLE: 1727 case NCR_SELECTING: 1728 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1729 sc->sc_flags = 0; 1730 ecb = sc->sc_nexus; 1731 if (ecb != NULL && (ecb->flags & ECB_NEXUS)) { 1732 scsi_print_addr(ecb->xs->sc_link); 1733 printf("ECB_NEXUS while in state %x\n", sc->sc_state); 1734 } 1735 1736 if (sc->sc_espintr & NCRINTR_RESEL) { 1737 /* 1738 * If we're trying to select a 1739 * target ourselves, push our command 1740 * back into the ready list. 1741 */ 1742 if (sc->sc_state == NCR_SELECTING) { 1743 NCR_MISC(("backoff selector ")); 1744 callout_stop(&ecb->xs->xs_callout); 1745 sc_link = ecb->xs->sc_link; 1746 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1747 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1748 ecb = sc->sc_nexus = NULL; 1749 } 1750 sc->sc_state = NCR_RESELECTED; 1751 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1752 /* 1753 * Things are seriously fucked up. 1754 * Pull the brakes, i.e. reset 1755 */ 1756 printf("%s: target didn't identify\n", 1757 sc->sc_dev.dv_xname); 1758 ncr53c9x_init(sc, 1); 1759 return (1); 1760 } 1761 /* 1762 * The C90 only inhibits FIFO writes until 1763 * reselection is complete, instead of 1764 * waiting until the interrupt status register 1765 * has been read. So, if the reselect happens 1766 * while we were entering a command bytes (for 1767 * another target) some of those bytes can 1768 * appear in the FIFO here, after the 1769 * interrupt is taken. 1770 */ 1771 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1772 if (nfifo < 2 || 1773 (nfifo > 2 && 1774 sc->sc_rev != NCR_VARIANT_ESP100)) { 1775 printf("%s: RESELECT: %d bytes in FIFO! " 1776 "[intr %x, stat %x, step %d, prevphase %x]\n", 1777 sc->sc_dev.dv_xname, 1778 nfifo, 1779 sc->sc_espintr, 1780 sc->sc_espstat, 1781 sc->sc_espstep, 1782 sc->sc_prevphase); 1783 ncr53c9x_init(sc, 1); 1784 return (1); 1785 } 1786 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1787 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1788 1789 /* Handle identify message */ 1790 ncr53c9x_msgin(sc); 1791 if (nfifo != 2) { 1792 /* 1793 * Note: this should not happen 1794 * with `dmaselect' on. 1795 */ 1796 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1797 NCRCMD(sc, NCRCMD_FLUSH); 1798 } else if (ncr53c9x_dmaselect && 1799 sc->sc_rev == NCR_VARIANT_ESP100) { 1800 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1801 } 1802 1803 if (sc->sc_state != NCR_CONNECTED) { 1804 /* IDENTIFY fail?! */ 1805 printf("%s: identify failed\n", 1806 sc->sc_dev.dv_xname); 1807 ncr53c9x_init(sc, 1); 1808 return (1); 1809 } 1810 goto shortcut; /* ie. next phase expected soon */ 1811 } 1812 1813 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1814 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1815 /* 1816 * Arbitration won; examine the `step' register 1817 * to determine how far the selection could progress. 1818 */ 1819 ecb = sc->sc_nexus; 1820 if (!ecb) 1821 panic("ncr53c9x: no nexus"); 1822 1823 sc_link = ecb->xs->sc_link; 1824 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1825 1826 switch (sc->sc_espstep) { 1827 case 0: 1828 /* 1829 * The target did not respond with a 1830 * message out phase - probably an old 1831 * device that doesn't recognize ATN. 1832 * Clear ATN and just continue, the 1833 * target should be in the command 1834 * phase. 1835 * XXXX check for command phase? 1836 */ 1837 NCRCMD(sc, NCRCMD_RSTATN); 1838 break; 1839 case 1: 1840 if ((ti->flags & T_NEGOTIATE) == 0) { 1841 printf("%s: step 1 & !NEG\n", 1842 sc->sc_dev.dv_xname); 1843 goto reset; 1844 } 1845 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1846 printf("%s: !MSGOUT\n", 1847 sc->sc_dev.dv_xname); 1848 goto reset; 1849 } 1850 /* Start negotiating */ 1851 ti->period = sc->sc_minsync; 1852 ti->offset = 15; 1853 sc->sc_flags |= NCR_SYNCHNEGO; 1854 ncr53c9x_sched_msgout(SEND_SDTR); 1855 break; 1856 case 3: 1857 /* 1858 * Grr, this is supposed to mean 1859 * "target left command phase prematurely". 1860 * It seems to happen regularly when 1861 * sync mode is on. 1862 * Look at FIFO to see if command went out. 1863 * (Timing problems?) 1864 */ 1865 if (ncr53c9x_dmaselect) { 1866 if (sc->sc_cmdlen == 0) 1867 /* Hope for the best.. */ 1868 break; 1869 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1870 & NCRFIFO_FF) == 0) { 1871 /* Hope for the best.. */ 1872 break; 1873 } 1874 printf("(%s:%d:%d): selection failed;" 1875 " %d left in FIFO " 1876 "[intr %x, stat %x, step %d]\n", 1877 sc->sc_dev.dv_xname, 1878 sc_link->scsipi_scsi.target, 1879 sc_link->scsipi_scsi.lun, 1880 NCR_READ_REG(sc, NCR_FFLAG) 1881 & NCRFIFO_FF, 1882 sc->sc_espintr, sc->sc_espstat, 1883 sc->sc_espstep); 1884 NCRCMD(sc, NCRCMD_FLUSH); 1885 ncr53c9x_sched_msgout(SEND_ABORT); 1886 return (1); 1887 case 2: 1888 /* Select stuck at Command Phase */ 1889 NCRCMD(sc, NCRCMD_FLUSH); 1890 break; 1891 case 4: 1892 if (ncr53c9x_dmaselect && 1893 sc->sc_cmdlen != 0) 1894 printf("(%s:%d:%d): select; " 1895 "%lu left in DMA buffer " 1896 "[intr %x, stat %x, step %d]\n", 1897 sc->sc_dev.dv_xname, 1898 sc_link->scsipi_scsi.target, 1899 sc_link->scsipi_scsi.lun, 1900 (u_long)sc->sc_cmdlen, 1901 sc->sc_espintr, 1902 sc->sc_espstat, 1903 sc->sc_espstep); 1904 /* So far, everything went fine */ 1905 break; 1906 } 1907 1908 ecb->flags |= ECB_NEXUS; 1909 ti->lubusy |= (1 << sc_link->scsipi_scsi.lun); 1910 1911 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1912 /* Do an implicit RESTORE POINTERS. */ 1913 sc->sc_dp = ecb->daddr; 1914 sc->sc_dleft = ecb->dleft; 1915 sc->sc_state = NCR_CONNECTED; 1916 break; 1917 1918 } else { 1919 1920 printf("%s: unexpected status after select" 1921 ": [intr %x, stat %x, step %x]\n", 1922 sc->sc_dev.dv_xname, 1923 sc->sc_espintr, sc->sc_espstat, 1924 sc->sc_espstep); 1925 NCRCMD(sc, NCRCMD_FLUSH); 1926 DELAY(1); 1927 goto reset; 1928 } 1929 if (sc->sc_state == NCR_IDLE) { 1930 printf("%s: stray interrupt\n", 1931 sc->sc_dev.dv_xname); 1932 return (0); 1933 } 1934 break; 1935 1936 case NCR_CONNECTED: 1937 if (sc->sc_flags & NCR_ICCS) { 1938 /* "Initiate Command Complete Steps" in progress */ 1939 u_char msg; 1940 1941 sc->sc_flags &= ~NCR_ICCS; 1942 1943 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1944 printf("%s: ICCS: " 1945 ": [intr %x, stat %x, step %x]\n", 1946 sc->sc_dev.dv_xname, 1947 sc->sc_espintr, sc->sc_espstat, 1948 sc->sc_espstep); 1949 } 1950 if ((NCR_READ_REG(sc, NCR_FFLAG) 1951 & NCRFIFO_FF) != 2) { 1952 /* Drop excess bytes from the queue */ 1953 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1954 & NCRFIFO_FF) - 2; 1955 while (i-- > 0) 1956 (void) NCR_READ_REG(sc, NCR_FIFO); 1957 } 1958 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1959 msg = NCR_READ_REG(sc, NCR_FIFO); 1960 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1961 if (msg == MSG_CMDCOMPLETE) { 1962 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1963 ? 0 1964 : sc->sc_dleft; 1965 if ((ecb->flags & ECB_SENSE) == 0) 1966 ecb->xs->resid = ecb->dleft; 1967 sc->sc_state = NCR_CMDCOMPLETE; 1968 } else 1969 printf("%s: STATUS_PHASE: msg %d\n", 1970 sc->sc_dev.dv_xname, msg); 1971 NCRCMD(sc, NCRCMD_MSGOK); 1972 goto shortcut; /* ie. wait for disconnect */ 1973 } 1974 break; 1975 default: 1976 panic("%s: invalid state: %d", 1977 sc->sc_dev.dv_xname, 1978 sc->sc_state); 1979 } 1980 1981 /* 1982 * Driver is now in state NCR_CONNECTED, i.e. we 1983 * have a current command working the SCSI bus. 1984 */ 1985 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1986 panic("ncr53c9x: no nexus"); 1987 } 1988 1989 switch (sc->sc_phase) { 1990 case MESSAGE_OUT_PHASE: 1991 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1992 ncr53c9x_msgout(sc); 1993 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1994 break; 1995 case MESSAGE_IN_PHASE: 1996 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1997 sc->sc_prevphase = MESSAGE_IN_PHASE; 1998 if (sc->sc_espintr & NCRINTR_BS) { 1999 NCRCMD(sc, NCRCMD_FLUSH); 2000 sc->sc_flags |= NCR_WAITI; 2001 NCRCMD(sc, NCRCMD_TRANS); 2002 } else if (sc->sc_espintr & NCRINTR_FC) { 2003 if ((sc->sc_flags & NCR_WAITI) == 0) { 2004 printf("%s: MSGIN: unexpected FC bit: " 2005 "[intr %x, stat %x, step %x]\n", 2006 sc->sc_dev.dv_xname, 2007 sc->sc_espintr, sc->sc_espstat, 2008 sc->sc_espstep); 2009 } 2010 sc->sc_flags &= ~NCR_WAITI; 2011 ncr53c9x_msgin(sc); 2012 } else { 2013 printf("%s: MSGIN: weird bits: " 2014 "[intr %x, stat %x, step %x]\n", 2015 sc->sc_dev.dv_xname, 2016 sc->sc_espintr, sc->sc_espstat, 2017 sc->sc_espstep); 2018 } 2019 goto shortcut; /* i.e. expect data to be ready */ 2020 break; 2021 case COMMAND_PHASE: 2022 /* 2023 * Send the command block. Normally we don't see this 2024 * phase because the SEL_ATN command takes care of 2025 * all this. However, we end up here if either the 2026 * target or we wanted to exchange some more messages 2027 * first (e.g. to start negotiations). 2028 */ 2029 2030 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2031 ecb->cmd.cmd.opcode, ecb->clen)); 2032 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2033 NCRCMD(sc, NCRCMD_FLUSH); 2034 DELAY(1); 2035 } 2036 if (ncr53c9x_dmaselect) { 2037 size_t size; 2038 /* setup DMA transfer for command */ 2039 size = ecb->clen; 2040 sc->sc_cmdlen = size; 2041 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2042 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2043 0, &size); 2044 /* Program the SCSI counter */ 2045 NCR_WRITE_REG(sc, NCR_TCL, size); 2046 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2047 if (sc->sc_cfg2 & NCRCFG2_FE) { 2048 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2049 } 2050 2051 /* load the count in */ 2052 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2053 2054 /* start the command transfer */ 2055 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2056 NCRDMA_GO(sc); 2057 } else { 2058 u_char *cmd = (u_char *)&ecb->cmd.cmd; 2059 int i; 2060 /* Now the command into the FIFO */ 2061 for (i = 0; i < ecb->clen; i++) 2062 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 2063 NCRCMD(sc, NCRCMD_TRANS); 2064 } 2065 sc->sc_prevphase = COMMAND_PHASE; 2066 break; 2067 case DATA_OUT_PHASE: 2068 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 2069 NCRCMD(sc, NCRCMD_FLUSH); 2070 size = min(sc->sc_dleft, sc->sc_maxxfer); 2071 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2072 0, &size); 2073 sc->sc_prevphase = DATA_OUT_PHASE; 2074 goto setup_xfer; 2075 case DATA_IN_PHASE: 2076 NCR_PHASE(("DATA_IN_PHASE ")); 2077 if (sc->sc_rev == NCR_VARIANT_ESP100) 2078 NCRCMD(sc, NCRCMD_FLUSH); 2079 size = min(sc->sc_dleft, sc->sc_maxxfer); 2080 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2081 1, &size); 2082 sc->sc_prevphase = DATA_IN_PHASE; 2083 setup_xfer: 2084 /* Target returned to data phase: wipe "done" memory */ 2085 ecb->flags &= ~ECB_TENTATIVE_DONE; 2086 2087 /* Program the SCSI counter */ 2088 NCR_WRITE_REG(sc, NCR_TCL, size); 2089 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2090 if (sc->sc_cfg2 & NCRCFG2_FE) { 2091 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2092 } 2093 /* load the count in */ 2094 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2095 2096 /* 2097 * Note that if `size' is 0, we've already transceived 2098 * all the bytes we want but we're still in DATA PHASE. 2099 * Apparently, the device needs padding. Also, a 2100 * transfer size of 0 means "maximum" to the chip 2101 * DMA logic. 2102 */ 2103 NCRCMD(sc, 2104 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 2105 NCRDMA_GO(sc); 2106 return (1); 2107 case STATUS_PHASE: 2108 NCR_PHASE(("STATUS_PHASE ")); 2109 sc->sc_flags |= NCR_ICCS; 2110 NCRCMD(sc, NCRCMD_ICCS); 2111 sc->sc_prevphase = STATUS_PHASE; 2112 goto shortcut; /* i.e. expect status results soon */ 2113 break; 2114 case INVALID_PHASE: 2115 break; 2116 default: 2117 printf("%s: unexpected bus phase; resetting\n", 2118 sc->sc_dev.dv_xname); 2119 goto reset; 2120 } 2121 2122 out: 2123 return (1); 2124 2125 reset: 2126 ncr53c9x_init(sc, 1); 2127 goto out; 2128 2129 finish: 2130 ncr53c9x_done(sc, ecb); 2131 goto out; 2132 2133 sched: 2134 sc->sc_state = NCR_IDLE; 2135 ncr53c9x_sched(sc); 2136 goto out; 2137 2138 shortcut: 2139 /* 2140 * The idea is that many of the SCSI operations take very little 2141 * time, and going away and getting interrupted is too high an 2142 * overhead to pay. For example, selecting, sending a message 2143 * and command and then doing some work can be done in one "pass". 2144 * 2145 * The delay is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 2146 * at 40Mhz. This needs testing. 2147 */ 2148 DELAY(50/sc->sc_freq); 2149 if (NCRDMA_ISINTR(sc)) 2150 goto again; 2151 goto out; 2152 } 2153 2154 void 2155 ncr53c9x_abort(sc, ecb) 2156 struct ncr53c9x_softc *sc; 2157 struct ncr53c9x_ecb *ecb; 2158 { 2159 2160 /* 2 secs for the abort */ 2161 ecb->timeout = NCR_ABORT_TIMEOUT; 2162 ecb->flags |= ECB_ABORT; 2163 2164 if (ecb == sc->sc_nexus) { 2165 /* 2166 * If we're still selecting, the message will be scheduled 2167 * after selection is complete. 2168 */ 2169 if (sc->sc_state == NCR_CONNECTED) 2170 ncr53c9x_sched_msgout(SEND_ABORT); 2171 2172 /* 2173 * Reschedule timeout. 2174 */ 2175 callout_reset(&ecb->xs->xs_callout, (ecb->timeout * hz) / 1000, 2176 ncr53c9x_timeout, ecb); 2177 } else { 2178 /* The command should be on the nexus list */ 2179 if ((ecb->flags & ECB_NEXUS) == 0) { 2180 scsi_print_addr(ecb->xs->sc_link); 2181 printf("ncr53c9x_abort: not NEXUS\n"); 2182 ncr53c9x_init(sc, 1); 2183 } 2184 /* 2185 * Just leave the command on the nexus list. 2186 * XXX - what choice do we have but to reset the SCSI 2187 * eventually? 2188 */ 2189 if (sc->sc_state == NCR_IDLE) 2190 ncr53c9x_sched(sc); 2191 } 2192 } 2193 2194 void 2195 ncr53c9x_timeout(arg) 2196 void *arg; 2197 { 2198 struct ncr53c9x_ecb *ecb = arg; 2199 struct scsipi_xfer *xs = ecb->xs; 2200 struct scsipi_link *sc_link = xs->sc_link; 2201 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 2202 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 2203 int s; 2204 2205 scsi_print_addr(sc_link); 2206 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2207 "<state %d, nexus %p, phase(l %x, c %x, p %x), resid %lx, " 2208 "msg(q %x,o %x) %s>", 2209 sc->sc_dev.dv_xname, 2210 ecb, ecb->flags, ecb->dleft, ecb->stat, 2211 sc->sc_state, sc->sc_nexus, 2212 NCR_READ_REG(sc, NCR_STAT), 2213 sc->sc_phase, sc->sc_prevphase, 2214 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2215 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2216 #if NCR53C9X_DEBUG > 1 2217 printf("TRACE: %s.", ecb->trace); 2218 #endif 2219 2220 s = splbio(); 2221 2222 if (ecb->flags & ECB_ABORT) { 2223 /* abort timed out */ 2224 printf(" AGAIN\n"); 2225 2226 ncr53c9x_init(sc, 1); 2227 } else { 2228 /* abort the operation that has timed out */ 2229 printf("\n"); 2230 xs->error = XS_TIMEOUT; 2231 ncr53c9x_abort(sc, ecb); 2232 2233 /* Disable sync mode if stuck in a data phase */ 2234 if (ecb == sc->sc_nexus && 2235 (ti->flags & T_SYNCMODE) != 0 && 2236 (sc->sc_phase & (MSGI|CDI)) == 0) { 2237 scsi_print_addr(sc_link); 2238 printf("sync negotiation disabled\n"); 2239 sc->sc_cfflags |= (1<<(sc_link->scsipi_scsi.target+8)); 2240 } 2241 } 2242 2243 splx(s); 2244 } 2245
Indexes created Fri Sep 26 08:10:20 GMT 2025