ncr53c9x.c revision 1.5
1 /* $NetBSD: ncr53c9x.c,v 1.5 1997/03/27 00:29:57 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 90 #include <dev/ic/ncr53c9xreg.h> 91 #include <dev/ic/ncr53c9xvar.h> 92 93 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 94 95 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 96 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 97 struct ncr53c9x_ecb *)); 98 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 99 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 100 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 101 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 102 struct scsi_xfer *, int)); 103 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 104 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 105 struct ncr53c9x_ecb *)); 106 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 107 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 108 /*static*/ void ncr53c9x_timeout __P((void *arg)); 109 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 110 struct ncr53c9x_ecb *)); 111 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 112 struct ncr53c9x_ecb *)); 113 114 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 115 struct ncr53c9x_ecb *)); 116 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 117 struct ncr53c9x_ecb *, int)); 118 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 119 120 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 121 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 122 struct ncr53c9x_tinfo *)); 123 124 /* 125 * Names for the NCR53c9x variants, correspnding to the variant tags 126 * in ncr53c9xvar.h. 127 */ 128 const char *ncr53c9x_variant_names[] = { 129 "ESP100", 130 "ESP100A", 131 "ESP200", 132 "NCR53C94", 133 "NCR53C96", 134 }; 135 136 /* 137 * Attach this instance, and then all the sub-devices 138 */ 139 void 140 ncr53c9x_attach(sc, adapter, dev) 141 struct ncr53c9x_softc *sc; 142 struct scsi_adapter *adapter; 143 struct scsi_device *dev; 144 { 145 146 /* 147 * Note, the front-end has set us up to print the chip variation. 148 */ 149 150 if (sc->sc_rev >= NCR_VARIANT_MAX) { 151 printf("\n%s: unknown variant %d, devices not attached\n", 152 sc->sc_dev.dv_xname, sc->sc_rev); 153 return; 154 } 155 156 printf(": %s, %dMHz, SCSI ID %d\n", 157 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 158 159 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 160 161 /* The value *must not* be == 1. Make it 2 */ 162 if (sc->sc_ccf == 1) 163 sc->sc_ccf = 2; 164 165 /* 166 * The recommended timeout is 250ms. This register is loaded 167 * with a value calculated as follows, from the docs: 168 * 169 * (timout period) x (CLK frequency) 170 * reg = ------------------------------------- 171 * 8192 x (Clock Conversion Factor) 172 * 173 * Since CCF has a linear relation to CLK, this generally computes 174 * to the constant of 153. 175 */ 176 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 177 178 /* CCF register only has 3 bits; 0 is actually 8 */ 179 sc->sc_ccf &= 7; 180 181 /* Reset state & bus */ 182 sc->sc_state = 0; 183 ncr53c9x_init(sc, 1); 184 185 /* 186 * fill in the prototype scsi_link. 187 */ 188 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 189 sc->sc_link.adapter_softc = sc; 190 sc->sc_link.adapter_target = sc->sc_id; 191 sc->sc_link.adapter = adapter; 192 sc->sc_link.device = dev; 193 sc->sc_link.openings = 2; 194 sc->sc_link.max_target = 7; 195 196 /* 197 * Now try to attach all the sub-devices 198 */ 199 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 200 } 201 202 /* 203 * This is the generic esp reset function. It does not reset the SCSI bus, 204 * only this controllers, but kills any on-going commands, and also stops 205 * and resets the DMA. 206 * 207 * After reset, registers are loaded with the defaults from the attach 208 * routine above. 209 */ 210 void 211 ncr53c9x_reset(sc) 212 struct ncr53c9x_softc *sc; 213 { 214 215 /* reset DMA first */ 216 NCRDMA_RESET(sc); 217 218 /* reset SCSI chip */ 219 NCRCMD(sc, NCRCMD_RSTCHIP); 220 NCRCMD(sc, NCRCMD_NOP); 221 DELAY(500); 222 223 /* do these backwards, and fall through */ 224 switch (sc->sc_rev) { 225 case NCR_VARIANT_NCR53C94: 226 case NCR_VARIANT_NCR53C96: 227 case NCR_VARIANT_ESP200: 228 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 229 case NCR_VARIANT_ESP100A: 230 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 231 case NCR_VARIANT_ESP100: 232 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 233 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 234 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 235 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 236 break; 237 default: 238 printf("%s: unknown revision code, assuming ESP100\n", 239 sc->sc_dev.dv_xname); 240 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 241 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 242 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 243 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 244 } 245 } 246 247 /* 248 * Reset the SCSI bus, but not the chip 249 */ 250 void 251 ncr53c9x_scsi_reset(sc) 252 struct ncr53c9x_softc *sc; 253 { 254 255 (*sc->sc_glue->gl_dma_stop)(sc); 256 257 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 258 NCRCMD(sc, NCRCMD_RSTSCSI); 259 } 260 261 /* 262 * Initialize esp state machine 263 */ 264 void 265 ncr53c9x_init(sc, doreset) 266 struct ncr53c9x_softc *sc; 267 int doreset; 268 { 269 struct ncr53c9x_ecb *ecb; 270 int r; 271 272 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 273 274 if (sc->sc_state == 0) { 275 /* First time through; initialize. */ 276 TAILQ_INIT(&sc->ready_list); 277 TAILQ_INIT(&sc->nexus_list); 278 TAILQ_INIT(&sc->free_list); 279 sc->sc_nexus = NULL; 280 ecb = sc->sc_ecb; 281 bzero(ecb, sizeof(sc->sc_ecb)); 282 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 283 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 284 ecb++; 285 } 286 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 287 } else { 288 /* Cancel any active commands. */ 289 sc->sc_state = NCR_CLEANING; 290 if ((ecb = sc->sc_nexus) != NULL) { 291 ecb->xs->error = XS_DRIVER_STUFFUP; 292 untimeout(ncr53c9x_timeout, ecb); 293 ncr53c9x_done(sc, ecb); 294 } 295 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 296 ecb->xs->error = XS_DRIVER_STUFFUP; 297 untimeout(ncr53c9x_timeout, ecb); 298 ncr53c9x_done(sc, ecb); 299 } 300 } 301 302 /* 303 * reset the chip to a known state 304 */ 305 ncr53c9x_reset(sc); 306 307 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 308 for (r = 0; r < 8; r++) { 309 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 310 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 311 int fl = sc->sc_dev.dv_cfdata->cf_flags; 312 313 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 314 ? T_NEGOTIATE : 0) | 315 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 316 T_NEED_TO_RESET; 317 ti->period = sc->sc_minsync; 318 ti->offset = 0; 319 } 320 321 if (doreset) { 322 sc->sc_state = NCR_SBR; 323 NCRCMD(sc, NCRCMD_RSTSCSI); 324 } else { 325 sc->sc_state = NCR_IDLE; 326 } 327 } 328 329 /* 330 * Read the NCR registers, and save their contents for later use. 331 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 332 * NCR_INTR - so make sure it is the last read. 333 * 334 * I think that (from reading the docs) most bits in these registers 335 * only make sense when he DMA CSR has an interrupt showing. Call only 336 * if an interrupt is pending. 337 */ 338 void 339 ncr53c9x_readregs(sc) 340 struct ncr53c9x_softc *sc; 341 { 342 343 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 344 /* Only the stepo bits are of interest */ 345 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 346 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 347 348 if (sc->sc_glue->gl_clear_latched_intr != NULL) 349 (*sc->sc_glue->gl_clear_latched_intr)(sc); 350 351 /* 352 * Determine the SCSI bus phase, return either a real SCSI bus phase 353 * or some pseudo phase we use to detect certain exceptions. 354 */ 355 356 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 357 ? /* Disconnected */ BUSFREE_PHASE 358 : sc->sc_espstat & NCRSTAT_PHASE; 359 360 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 361 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 362 } 363 364 /* 365 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 366 */ 367 static inline int 368 ncr53c9x_stp2cpb(sc, period) 369 struct ncr53c9x_softc *sc; 370 int period; 371 { 372 int v; 373 v = (sc->sc_freq * period) / 250; 374 if (ncr53c9x_cpb2stp(sc, v) < period) 375 /* Correct round-down error */ 376 v++; 377 return v; 378 } 379 380 static inline void 381 ncr53c9x_setsync(sc, ti) 382 struct ncr53c9x_softc *sc; 383 struct ncr53c9x_tinfo *ti; 384 { 385 386 if (ti->flags & T_SYNCMODE) { 387 NCR_WRITE_REG(sc, NCR_SYNCOFF, ti->offset); 388 NCR_WRITE_REG(sc, NCR_SYNCTP, 389 ncr53c9x_stp2cpb(sc, ti->period)); 390 } else { 391 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 392 NCR_WRITE_REG(sc, NCR_SYNCTP, 0); 393 } 394 } 395 396 /* 397 * Send a command to a target, set the driver state to NCR_SELECTING 398 * and let the caller take care of the rest. 399 * 400 * Keeping this as a function allows me to say that this may be done 401 * by DMA instead of programmed I/O soon. 402 */ 403 void 404 ncr53c9x_select(sc, ecb) 405 struct ncr53c9x_softc *sc; 406 struct ncr53c9x_ecb *ecb; 407 { 408 struct scsi_link *sc_link = ecb->xs->sc_link; 409 int target = sc_link->target; 410 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 411 u_char *cmd; 412 int clen; 413 414 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 415 sc_link->target, sc_link->lun, ecb->cmd.opcode)); 416 417 /* new state NCR_SELECTING */ 418 sc->sc_state = NCR_SELECTING; 419 420 NCRCMD(sc, NCRCMD_FLUSH); 421 422 /* 423 * The docs say the target register is never reset, and I 424 * can't think of a better place to set it 425 */ 426 NCR_WRITE_REG(sc, NCR_SELID, target); 427 ncr53c9x_setsync(sc, ti); 428 429 /* 430 * Who am I. This is where we tell the target that we are 431 * happy for it to disconnect etc. 432 */ 433 NCR_WRITE_REG(sc, NCR_FIFO, 434 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 435 436 if (ti->flags & T_NEGOTIATE) { 437 /* Arbitrate, select and stop after IDENTIFY message */ 438 NCRCMD(sc, NCRCMD_SELATNS); 439 return; 440 } 441 442 /* Now the command into the FIFO */ 443 cmd = (u_char *)&ecb->cmd; 444 clen = ecb->clen; 445 while (clen--) 446 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 447 448 /* And get the targets attention */ 449 NCRCMD(sc, NCRCMD_SELATN); 450 } 451 452 void 453 ncr53c9x_free_ecb(sc, ecb, flags) 454 struct ncr53c9x_softc *sc; 455 struct ncr53c9x_ecb *ecb; 456 int flags; 457 { 458 int s; 459 460 s = splbio(); 461 462 ecb->flags = 0; 463 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 464 465 /* 466 * If there were none, wake anybody waiting for one to come free, 467 * starting with queued entries. 468 */ 469 if (ecb->chain.tqe_next == 0) 470 wakeup(&sc->free_list); 471 472 splx(s); 473 } 474 475 struct ncr53c9x_ecb * 476 ncr53c9x_get_ecb(sc, flags) 477 struct ncr53c9x_softc *sc; 478 int flags; 479 { 480 struct ncr53c9x_ecb *ecb; 481 int s; 482 483 s = splbio(); 484 485 while ((ecb = sc->free_list.tqh_first) == NULL && 486 (flags & SCSI_NOSLEEP) == 0) 487 tsleep(&sc->free_list, PRIBIO, "especb", 0); 488 if (ecb) { 489 TAILQ_REMOVE(&sc->free_list, ecb, chain); 490 ecb->flags |= ECB_ALLOC; 491 } 492 493 splx(s); 494 return ecb; 495 } 496 497 /* 498 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 499 */ 500 501 /* 502 * Start a SCSI-command 503 * This function is called by the higher level SCSI-driver to queue/run 504 * SCSI-commands. 505 */ 506 int 507 ncr53c9x_scsi_cmd(xs) 508 struct scsi_xfer *xs; 509 { 510 struct scsi_link *sc_link = xs->sc_link; 511 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 512 struct ncr53c9x_ecb *ecb; 513 int s, flags; 514 extern int cold; /* XXX */ 515 516 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 517 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 518 sc_link->target)); 519 520 flags = xs->flags; 521 /* 522 * XXX: Hack: During autoconfig, force polling mode. 523 * Needed as long as sdsize() can be called while cold, 524 * otherwise timeouts will never call back (grumble). 525 */ 526 if (cold) 527 flags |= SCSI_POLL; 528 529 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) { 530 xs->error = XS_DRIVER_STUFFUP; 531 return TRY_AGAIN_LATER; 532 } 533 534 /* Initialize ecb */ 535 ecb->xs = xs; 536 ecb->timeout = xs->timeout; 537 538 if (flags & SCSI_RESET) { 539 ecb->flags |= ECB_RESET; 540 ecb->clen = 0; 541 ecb->dleft = 0; 542 } else { 543 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 544 ecb->clen = xs->cmdlen; 545 ecb->daddr = xs->data; 546 ecb->dleft = xs->datalen; 547 } 548 ecb->stat = 0; 549 550 s = splbio(); 551 552 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 553 if (sc->sc_state == NCR_IDLE) 554 ncr53c9x_sched(sc); 555 556 splx(s); 557 558 if ((flags & SCSI_POLL) == 0) 559 return SUCCESSFULLY_QUEUED; 560 561 /* Not allowed to use interrupts, use polling instead */ 562 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 563 ncr53c9x_timeout(ecb); 564 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 565 ncr53c9x_timeout(ecb); 566 } 567 return COMPLETE; 568 } 569 570 /* 571 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 572 */ 573 int 574 ncr53c9x_poll(sc, xs, count) 575 struct ncr53c9x_softc *sc; 576 struct scsi_xfer *xs; 577 int count; 578 { 579 580 NCR_TRACE(("[ncr53c9x_poll] ")); 581 while (count) { 582 if (NCRDMA_ISINTR(sc)) { 583 ncr53c9x_intr(sc); 584 } 585 #if alternatively 586 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 587 ncr53c9x_intr(sc); 588 #endif 589 if ((xs->flags & ITSDONE) != 0) 590 return 0; 591 if (sc->sc_state == NCR_IDLE) { 592 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 593 ncr53c9x_sched(sc); 594 } 595 DELAY(1000); 596 count--; 597 } 598 return 1; 599 } 600 601 602 /* 603 * LOW LEVEL SCSI UTILITIES 604 */ 605 606 /* 607 * Schedule a scsi operation. This has now been pulled out of the interrupt 608 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 609 * This may save us an unecessary interrupt just to get things going. 610 * Should only be called when state == NCR_IDLE and at bio pl. 611 */ 612 void 613 ncr53c9x_sched(sc) 614 struct ncr53c9x_softc *sc; 615 { 616 struct ncr53c9x_ecb *ecb; 617 struct scsi_link *sc_link; 618 struct ncr53c9x_tinfo *ti; 619 620 NCR_TRACE(("[ncr53c9x_sched] ")); 621 if (sc->sc_state != NCR_IDLE) 622 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 623 624 /* 625 * Find first ecb in ready queue that is for a target/lunit 626 * combinations that is not busy. 627 */ 628 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 629 sc_link = ecb->xs->sc_link; 630 ti = &sc->sc_tinfo[sc_link->target]; 631 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 632 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 633 sc->sc_nexus = ecb; 634 ncr53c9x_select(sc, ecb); 635 break; 636 } else 637 NCR_MISC(("%d:%d busy\n", 638 sc_link->target, sc_link->lun)); 639 } 640 } 641 642 void 643 ncr53c9x_sense(sc, ecb) 644 struct ncr53c9x_softc *sc; 645 struct ncr53c9x_ecb *ecb; 646 { 647 struct scsi_xfer *xs = ecb->xs; 648 struct scsi_link *sc_link = xs->sc_link; 649 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 650 struct scsi_sense *ss = (void *)&ecb->cmd; 651 652 NCR_MISC(("requesting sense ")); 653 /* Next, setup a request sense command block */ 654 bzero(ss, sizeof(*ss)); 655 ss->opcode = REQUEST_SENSE; 656 ss->byte2 = sc_link->lun << 5; 657 ss->length = sizeof(struct scsi_sense_data); 658 ecb->clen = sizeof(*ss); 659 ecb->daddr = (char *)&xs->sense; 660 ecb->dleft = sizeof(struct scsi_sense_data); 661 ecb->flags |= ECB_SENSE; 662 ti->senses++; 663 if (ecb->flags & ECB_NEXUS) 664 ti->lubusy &= ~(1 << sc_link->lun); 665 if (ecb == sc->sc_nexus) { 666 ncr53c9x_select(sc, ecb); 667 } else { 668 ncr53c9x_dequeue(sc, ecb); 669 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 670 if (sc->sc_state == NCR_IDLE) 671 ncr53c9x_sched(sc); 672 } 673 } 674 675 /* 676 * POST PROCESSING OF SCSI_CMD (usually current) 677 */ 678 void 679 ncr53c9x_done(sc, ecb) 680 struct ncr53c9x_softc *sc; 681 struct ncr53c9x_ecb *ecb; 682 { 683 struct scsi_xfer *xs = ecb->xs; 684 struct scsi_link *sc_link = xs->sc_link; 685 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 686 687 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 688 689 /* 690 * Now, if we've come here with no error code, i.e. we've kept the 691 * initial XS_NOERROR, and the status code signals that we should 692 * check sense, we'll need to set up a request sense cmd block and 693 * push the command back into the ready queue *before* any other 694 * commands for this target/lunit, else we lose the sense info. 695 * We don't support chk sense conditions for the request sense cmd. 696 */ 697 if (xs->error == XS_NOERROR) { 698 if ((ecb->flags & ECB_ABORT) != 0) { 699 xs->error = XS_DRIVER_STUFFUP; 700 } else if ((ecb->flags & ECB_SENSE) != 0) { 701 xs->error = XS_SENSE; 702 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 703 /* First, save the return values */ 704 xs->resid = ecb->dleft; 705 xs->status = ecb->stat; 706 ncr53c9x_sense(sc, ecb); 707 return; 708 } else { 709 xs->resid = ecb->dleft; 710 } 711 } 712 713 xs->flags |= ITSDONE; 714 715 #ifdef NCR53C9X_DEBUG 716 if (ncr53c9x_debug & NCR_SHOWMISC) { 717 if (xs->resid != 0) 718 printf("resid=%d ", xs->resid); 719 if (xs->error == XS_SENSE) 720 printf("sense=0x%02x\n", xs->sense.error_code); 721 else 722 printf("error=%d\n", xs->error); 723 } 724 #endif 725 726 /* 727 * Remove the ECB from whatever queue it's on. 728 */ 729 if (ecb->flags & ECB_NEXUS) 730 ti->lubusy &= ~(1 << sc_link->lun); 731 if (ecb == sc->sc_nexus) { 732 sc->sc_nexus = NULL; 733 sc->sc_state = NCR_IDLE; 734 ncr53c9x_sched(sc); 735 } else 736 ncr53c9x_dequeue(sc, ecb); 737 738 ncr53c9x_free_ecb(sc, ecb, xs->flags); 739 ti->cmds++; 740 scsi_done(xs); 741 } 742 743 void 744 ncr53c9x_dequeue(sc, ecb) 745 struct ncr53c9x_softc *sc; 746 struct ncr53c9x_ecb *ecb; 747 { 748 749 if (ecb->flags & ECB_NEXUS) { 750 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 751 } else { 752 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 753 } 754 } 755 756 /* 757 * INTERRUPT/PROTOCOL ENGINE 758 */ 759 760 /* 761 * Schedule an outgoing message by prioritizing it, and asserting 762 * attention on the bus. We can only do this when we are the initiator 763 * else there will be an illegal command interrupt. 764 */ 765 #define ncr53c9x_sched_msgout(m) \ 766 do { \ 767 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 768 NCRCMD(sc, NCRCMD_SETATN); \ 769 sc->sc_flags |= NCR_ATN; \ 770 sc->sc_msgpriq |= (m); \ 771 } while (0) 772 773 int 774 ncr53c9x_reselect(sc, message) 775 struct ncr53c9x_softc *sc; 776 int message; 777 { 778 u_char selid, target, lun; 779 struct ncr53c9x_ecb *ecb; 780 struct scsi_link *sc_link; 781 struct ncr53c9x_tinfo *ti; 782 783 /* 784 * The SCSI chip made a snapshot of the data bus while the reselection 785 * was being negotiated. This enables us to determine which target did 786 * the reselect. 787 */ 788 selid = sc->sc_selid & ~(1 << sc->sc_id); 789 if (selid & (selid - 1)) { 790 printf("%s: reselect with invalid selid %02x;" 791 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 792 goto reset; 793 } 794 795 /* 796 * Search wait queue for disconnected cmd 797 * The list should be short, so I haven't bothered with 798 * any more sophisticated structures than a simple 799 * singly linked list. 800 */ 801 target = ffs(selid) - 1; 802 lun = message & 0x07; 803 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 804 ecb = ecb->chain.tqe_next) { 805 sc_link = ecb->xs->sc_link; 806 if (sc_link->target == target && sc_link->lun == lun) 807 break; 808 } 809 if (ecb == NULL) { 810 printf("%s: reselect from target %d lun %d with no nexus;" 811 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 812 goto abort; 813 } 814 815 /* Make this nexus active again. */ 816 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 817 sc->sc_state = NCR_CONNECTED; 818 sc->sc_nexus = ecb; 819 ti = &sc->sc_tinfo[target]; 820 ti->lubusy |= (1 << lun); 821 ncr53c9x_setsync(sc, ti); 822 823 if (ecb->flags & ECB_RESET) 824 ncr53c9x_sched_msgout(SEND_DEV_RESET); 825 else if (ecb->flags & ECB_ABORT) 826 ncr53c9x_sched_msgout(SEND_ABORT); 827 828 /* Do an implicit RESTORE POINTERS. */ 829 sc->sc_dp = ecb->daddr; 830 sc->sc_dleft = ecb->dleft; 831 832 return (0); 833 834 reset: 835 ncr53c9x_sched_msgout(SEND_DEV_RESET); 836 return (1); 837 838 abort: 839 ncr53c9x_sched_msgout(SEND_ABORT); 840 return (1); 841 } 842 843 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 844 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 845 #define ISEXTMSG(m) ((m) == 1) 846 847 /* 848 * Get an incoming message as initiator. 849 * 850 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 851 * byte in the FIFO 852 */ 853 void 854 ncr53c9x_msgin(sc) 855 register struct ncr53c9x_softc *sc; 856 { 857 register int v; 858 859 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 860 861 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 862 printf("%s: msgin: no msg byte available\n", 863 sc->sc_dev.dv_xname); 864 return; 865 } 866 867 /* 868 * Prepare for a new message. A message should (according 869 * to the SCSI standard) be transmitted in one single 870 * MESSAGE_IN_PHASE. If we have been in some other phase, 871 * then this is a new message. 872 */ 873 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 874 sc->sc_flags &= ~NCR_DROP_MSGI; 875 sc->sc_imlen = 0; 876 } 877 878 v = NCR_READ_REG(sc, NCR_FIFO); 879 NCR_MISC(("<msgbyte:0x%02x>", v)); 880 881 #if 0 882 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 883 /* 884 * Which target is reselecting us? (The ID bit really) 885 */ 886 sc->sc_selid = v; 887 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 888 return; 889 } 890 #endif 891 892 sc->sc_imess[sc->sc_imlen] = v; 893 894 /* 895 * If we're going to reject the message, don't bother storing 896 * the incoming bytes. But still, we need to ACK them. 897 */ 898 899 if ((sc->sc_flags & NCR_DROP_MSGI)) { 900 NCRCMD(sc, NCRCMD_MSGOK); 901 printf("<dropping msg byte %x>", 902 sc->sc_imess[sc->sc_imlen]); 903 return; 904 } 905 906 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 907 ncr53c9x_sched_msgout(SEND_REJECT); 908 sc->sc_flags |= NCR_DROP_MSGI; 909 } else { 910 sc->sc_imlen++; 911 /* 912 * This testing is suboptimal, but most 913 * messages will be of the one byte variety, so 914 * it should not effect performance 915 * significantly. 916 */ 917 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 918 goto gotit; 919 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 920 goto gotit; 921 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 922 sc->sc_imlen == sc->sc_imess[1] + 2) 923 goto gotit; 924 } 925 /* Ack what we have so far */ 926 NCRCMD(sc, NCRCMD_MSGOK); 927 return; 928 929 gotit: 930 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 931 /* 932 * Now we should have a complete message (1 byte, 2 byte 933 * and moderately long extended messages). We only handle 934 * extended messages which total length is shorter than 935 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 936 */ 937 switch (sc->sc_state) { 938 struct ncr53c9x_ecb *ecb; 939 struct ncr53c9x_tinfo *ti; 940 941 case NCR_CONNECTED: 942 ecb = sc->sc_nexus; 943 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 944 945 switch (sc->sc_imess[0]) { 946 case MSG_CMDCOMPLETE: 947 NCR_MSGS(("cmdcomplete ")); 948 if (sc->sc_dleft < 0) { 949 struct scsi_link *sc_link = ecb->xs->sc_link; 950 printf("%s: %ld extra bytes from %d:%d\n", 951 sc->sc_dev.dv_xname, -(long)sc->sc_dleft, 952 sc_link->target, sc_link->lun); 953 sc->sc_dleft = 0; 954 } 955 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 956 sc->sc_state = NCR_CMDCOMPLETE; 957 break; 958 959 case MSG_MESSAGE_REJECT: 960 if (ncr53c9x_debug & NCR_SHOWMSGS) 961 printf("%s: our msg rejected by target\n", 962 sc->sc_dev.dv_xname); 963 switch (sc->sc_msgout) { 964 case SEND_SDTR: 965 sc->sc_flags &= ~NCR_SYNCHNEGO; 966 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 967 ncr53c9x_setsync(sc, ti); 968 break; 969 case SEND_INIT_DET_ERR: 970 goto abort; 971 } 972 break; 973 974 case MSG_NOOP: 975 NCR_MSGS(("noop ")); 976 break; 977 978 case MSG_DISCONNECT: 979 NCR_MSGS(("disconnect ")); 980 ti->dconns++; 981 sc->sc_state = NCR_DISCONNECT; 982 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 983 break; 984 /*FALLTHROUGH*/ 985 986 case MSG_SAVEDATAPOINTER: 987 NCR_MSGS(("save datapointer ")); 988 ecb->daddr = sc->sc_dp; 989 ecb->dleft = sc->sc_dleft; 990 break; 991 992 case MSG_RESTOREPOINTERS: 993 NCR_MSGS(("restore datapointer ")); 994 sc->sc_dp = ecb->daddr; 995 sc->sc_dleft = ecb->dleft; 996 break; 997 998 case MSG_EXTENDED: 999 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1000 switch (sc->sc_imess[2]) { 1001 case MSG_EXT_SDTR: 1002 NCR_MSGS(("SDTR period %d, offset %d ", 1003 sc->sc_imess[3], sc->sc_imess[4])); 1004 if (sc->sc_imess[1] != 3) 1005 goto reject; 1006 ti->period = sc->sc_imess[3]; 1007 ti->offset = sc->sc_imess[4]; 1008 ti->flags &= ~T_NEGOTIATE; 1009 if (sc->sc_minsync == 0 || 1010 ti->offset == 0 || 1011 ti->period > 124) { 1012 printf("%s:%d: async\n", "esp", 1013 ecb->xs->sc_link->target); 1014 if ((sc->sc_flags&NCR_SYNCHNEGO) 1015 == 0) { 1016 /* 1017 * target initiated negotiation 1018 */ 1019 ti->offset = 0; 1020 ti->flags &= ~T_SYNCMODE; 1021 ncr53c9x_sched_msgout( 1022 SEND_SDTR); 1023 } else { 1024 /* we are async */ 1025 ti->flags &= ~T_SYNCMODE; 1026 } 1027 } else { 1028 int r = 250/ti->period; 1029 int s = (100*250)/ti->period - 100*r; 1030 int p; 1031 1032 p = ncr53c9x_stp2cpb(sc, ti->period); 1033 ti->period = ncr53c9x_cpb2stp(sc, p); 1034 #ifdef NCR53C9X_DEBUG 1035 sc_print_addr(ecb->xs->sc_link); 1036 printf("max sync rate %d.%02dMb/s\n", 1037 r, s); 1038 #endif 1039 if ((sc->sc_flags&NCR_SYNCHNEGO) 1040 == 0) { 1041 /* 1042 * target initiated negotiation 1043 */ 1044 if (ti->period < 1045 sc->sc_minsync) 1046 ti->period = 1047 sc->sc_minsync; 1048 if (ti->offset > 15) 1049 ti->offset = 15; 1050 ti->flags &= ~T_SYNCMODE; 1051 ncr53c9x_sched_msgout( 1052 SEND_SDTR); 1053 } else { 1054 /* we are sync */ 1055 ti->flags |= T_SYNCMODE; 1056 } 1057 } 1058 sc->sc_flags &= ~NCR_SYNCHNEGO; 1059 ncr53c9x_setsync(sc, ti); 1060 break; 1061 1062 default: 1063 printf("%s: unrecognized MESSAGE EXTENDED;" 1064 " sending REJECT\n", sc->sc_dev.dv_xname); 1065 goto reject; 1066 } 1067 break; 1068 1069 default: 1070 NCR_MSGS(("ident ")); 1071 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1072 sc->sc_dev.dv_xname); 1073 reject: 1074 ncr53c9x_sched_msgout(SEND_REJECT); 1075 break; 1076 } 1077 break; 1078 1079 case NCR_RESELECTED: 1080 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1081 printf("%s: reselect without IDENTIFY;" 1082 " sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1083 goto reset; 1084 } 1085 1086 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1087 break; 1088 1089 default: 1090 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1091 sc->sc_dev.dv_xname); 1092 reset: 1093 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1094 break; 1095 1096 abort: 1097 ncr53c9x_sched_msgout(SEND_ABORT); 1098 break; 1099 } 1100 1101 /* Ack last message byte */ 1102 NCRCMD(sc, NCRCMD_MSGOK); 1103 1104 /* Done, reset message pointer. */ 1105 sc->sc_flags &= ~NCR_DROP_MSGI; 1106 sc->sc_imlen = 0; 1107 } 1108 1109 1110 /* 1111 * Send the highest priority, scheduled message 1112 */ 1113 void 1114 ncr53c9x_msgout(sc) 1115 register struct ncr53c9x_softc *sc; 1116 { 1117 struct ncr53c9x_tinfo *ti; 1118 struct ncr53c9x_ecb *ecb; 1119 size_t size; 1120 1121 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1122 sc->sc_msgpriq, sc->sc_prevphase)); 1123 1124 if (sc->sc_flags & NCR_ATN) { 1125 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1126 new: 1127 NCRCMD(sc, NCRCMD_FLUSH); 1128 DELAY(1); 1129 sc->sc_msgoutq = 0; 1130 sc->sc_omlen = 0; 1131 } 1132 } else { 1133 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1134 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1135 goto new; 1136 } else { 1137 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1138 sc->sc_dev.dv_xname, __LINE__); 1139 } 1140 } 1141 1142 if (sc->sc_omlen == 0) { 1143 /* Pick up highest priority message */ 1144 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1145 sc->sc_msgoutq |= sc->sc_msgout; 1146 sc->sc_msgpriq &= ~sc->sc_msgout; 1147 sc->sc_omlen = 1; /* "Default" message len */ 1148 switch (sc->sc_msgout) { 1149 case SEND_SDTR: 1150 ecb = sc->sc_nexus; 1151 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1152 sc->sc_omess[0] = MSG_EXTENDED; 1153 sc->sc_omess[1] = 3; 1154 sc->sc_omess[2] = MSG_EXT_SDTR; 1155 sc->sc_omess[3] = ti->period; 1156 sc->sc_omess[4] = ti->offset; 1157 sc->sc_omlen = 5; 1158 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1159 ti->flags |= T_SYNCMODE; 1160 ncr53c9x_setsync(sc, ti); 1161 } 1162 break; 1163 case SEND_IDENTIFY: 1164 if (sc->sc_state != NCR_CONNECTED) { 1165 printf("%s at line %d: no nexus\n", 1166 sc->sc_dev.dv_xname, __LINE__); 1167 } 1168 ecb = sc->sc_nexus; 1169 sc->sc_omess[0] = 1170 MSG_IDENTIFY(ecb->xs->sc_link->lun, 0); 1171 break; 1172 case SEND_DEV_RESET: 1173 sc->sc_flags |= NCR_ABORTING; 1174 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1175 ecb = sc->sc_nexus; 1176 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1177 ti->flags &= ~T_SYNCMODE; 1178 ti->flags |= T_NEGOTIATE; 1179 break; 1180 case SEND_PARITY_ERROR: 1181 sc->sc_omess[0] = MSG_PARITY_ERROR; 1182 break; 1183 case SEND_ABORT: 1184 sc->sc_flags |= NCR_ABORTING; 1185 sc->sc_omess[0] = MSG_ABORT; 1186 break; 1187 case SEND_INIT_DET_ERR: 1188 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1189 break; 1190 case SEND_REJECT: 1191 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1192 break; 1193 default: 1194 NCRCMD(sc, NCRCMD_RSTATN); 1195 sc->sc_flags &= ~NCR_ATN; 1196 sc->sc_omess[0] = MSG_NOOP; 1197 break; 1198 } 1199 sc->sc_omp = sc->sc_omess; 1200 } 1201 1202 #if 1 1203 /* (re)send the message */ 1204 size = min(sc->sc_omlen, sc->sc_maxxfer); 1205 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1206 /* Program the SCSI counter */ 1207 NCR_WRITE_REG(sc, NCR_TCL, size); 1208 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1209 if (sc->sc_cfg2 & NCRCFG2_FE) { 1210 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1211 } 1212 /* load the count in */ 1213 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1214 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1215 NCRDMA_GO(sc); 1216 #else 1217 { int i; 1218 for (i = 0; i < sc->sc_omlen; i++) 1219 NCR_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1220 NCRCMD(sc, NCRCMD_TRANS); 1221 sc->sc_omlen = 0; 1222 } 1223 #endif 1224 } 1225 1226 /* 1227 * This is the most critical part of the driver, and has to know 1228 * how to deal with *all* error conditions and phases from the SCSI 1229 * bus. If there are no errors and the DMA was active, then call the 1230 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1231 * and we can return from here without further processing. 1232 * 1233 * Most of this needs verifying. 1234 */ 1235 int 1236 ncr53c9x_intr(sc) 1237 register struct ncr53c9x_softc *sc; 1238 { 1239 register struct ncr53c9x_ecb *ecb; 1240 register struct scsi_link *sc_link; 1241 struct ncr53c9x_tinfo *ti; 1242 int loop; 1243 size_t size; 1244 int nfifo; 1245 1246 NCR_TRACE(("[ncr53c9x_intr]")); 1247 1248 /* 1249 * I have made some (maybe seriously flawed) assumptions here, 1250 * but basic testing (uncomment the printf() below), show that 1251 * certainly something happens when this loop is here. 1252 * 1253 * The idea is that many of the SCSI operations take very little 1254 * time, and going away and getting interrupted is too high an 1255 * overhead to pay. For example, selecting, sending a message 1256 * and command and then doing some work can be done in one "pass". 1257 * 1258 * The DELAY is not variable because I do not understand that the 1259 * DELAY loop should be fixed-time regardless of CPU speed, but 1260 * I am *assuming* that the faster SCSI processors get things done 1261 * quicker (sending a command byte etc), and so there is no 1262 * need to be too slow. 1263 * 1264 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1265 * at 40Mhz. This needs testing. 1266 */ 1267 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1268 /* a feeling of deja-vu */ 1269 if (!NCRDMA_ISINTR(sc)) 1270 return (loop != 0); 1271 #if 0 1272 if (loop) 1273 printf("*"); 1274 #endif 1275 1276 /* and what do the registers say... */ 1277 ncr53c9x_readregs(sc); 1278 1279 sc->sc_intrcnt.ev_count++; 1280 1281 /* 1282 * At the moment, only a SCSI Bus Reset or Illegal 1283 * Command are classed as errors. A disconnect is a 1284 * valid condition, and we let the code check is the 1285 * "NCR_BUSFREE_OK" flag was set before declaring it 1286 * and error. 1287 * 1288 * Also, the status register tells us about "Gross 1289 * Errors" and "Parity errors". Only the Gross Error 1290 * is really bad, and the parity errors are dealt 1291 * with later 1292 * 1293 * TODO 1294 * If there are too many parity error, go to slow 1295 * cable mode ? 1296 */ 1297 1298 /* SCSI Reset */ 1299 if (sc->sc_espintr & NCRINTR_SBR) { 1300 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1301 NCRCMD(sc, NCRCMD_FLUSH); 1302 DELAY(1); 1303 } 1304 if (sc->sc_state != NCR_SBR) { 1305 printf("%s: SCSI bus reset\n", 1306 sc->sc_dev.dv_xname); 1307 ncr53c9x_init(sc, 0); /* Restart everything */ 1308 return 1; 1309 } 1310 #if 0 1311 /*XXX*/ printf("<expected bus reset: " 1312 "[intr %x, stat %x, step %d]>\n", 1313 sc->sc_espintr, sc->sc_espstat, 1314 sc->sc_espstep); 1315 #endif 1316 if (sc->sc_nexus) 1317 panic("%s: nexus in reset state", 1318 sc->sc_dev.dv_xname); 1319 goto sched; 1320 } 1321 1322 ecb = sc->sc_nexus; 1323 1324 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1325 if (sc->sc_espintr & NCRINTR_ERR || 1326 sc->sc_espstat & NCRSTAT_GE) { 1327 1328 if (sc->sc_espstat & NCRSTAT_GE) { 1329 /* no target ? */ 1330 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1331 NCRCMD(sc, NCRCMD_FLUSH); 1332 DELAY(1); 1333 } 1334 if (sc->sc_state == NCR_CONNECTED || 1335 sc->sc_state == NCR_SELECTING) { 1336 ecb->xs->error = XS_DRIVER_STUFFUP; 1337 ncr53c9x_done(sc, ecb); 1338 } 1339 return 1; 1340 } 1341 1342 if (sc->sc_espintr & NCRINTR_ILL) { 1343 /* illegal command, out of sync ? */ 1344 printf("%s: illegal command: 0x%x " 1345 "(state %d, phase %x, prevphase %x)\n", 1346 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1347 sc->sc_state, sc->sc_phase, 1348 sc->sc_prevphase); 1349 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1350 NCRCMD(sc, NCRCMD_FLUSH); 1351 DELAY(1); 1352 } 1353 ncr53c9x_init(sc, 0); /* Restart everything */ 1354 return 1; 1355 } 1356 } 1357 1358 /* 1359 * Call if DMA is active. 1360 * 1361 * If DMA_INTR returns true, then maybe go 'round the loop 1362 * again in case there is no more DMA queued, but a phase 1363 * change is expected. 1364 */ 1365 if (NCRDMA_ISACTIVE(sc)) { 1366 int r = NCRDMA_INTR(sc); 1367 if (r == -1) { 1368 printf("%s: DMA error; resetting\n", 1369 sc->sc_dev.dv_xname); 1370 ncr53c9x_init(sc, 1); 1371 } 1372 /* If DMA active here, then go back to work... */ 1373 if (NCRDMA_ISACTIVE(sc)) 1374 return 1; 1375 1376 if (sc->sc_dleft == 0 && 1377 (sc->sc_espstat & NCRSTAT_TC) == 0) 1378 printf("%s: !TC [intr %x, stat %x, step %d]" 1379 " prevphase %x, resid %x\n", 1380 sc->sc_dev.dv_xname, 1381 sc->sc_espintr, 1382 sc->sc_espstat, 1383 sc->sc_espstep, 1384 sc->sc_prevphase, 1385 ecb?ecb->dleft:-1); 1386 } 1387 1388 #if 0 /* Unreliable on some NCR revisions? */ 1389 if ((sc->sc_espstat & NCRSTAT_INT) == 0) { 1390 printf("%s: spurious interrupt\n", 1391 sc->sc_dev.dv_xname); 1392 return 1; 1393 } 1394 #endif 1395 1396 /* 1397 * check for less serious errors 1398 */ 1399 if (sc->sc_espstat & NCRSTAT_PE) { 1400 printf("%s: SCSI bus parity error\n", 1401 sc->sc_dev.dv_xname); 1402 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1403 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1404 else 1405 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1406 } 1407 1408 if (sc->sc_espintr & NCRINTR_DIS) { 1409 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1410 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1411 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1412 NCRCMD(sc, NCRCMD_FLUSH); 1413 DELAY(1); 1414 } 1415 /* 1416 * This command must (apparently) be issued within 1417 * 250mS of a disconnect. So here you are... 1418 */ 1419 NCRCMD(sc, NCRCMD_ENSEL); 1420 switch (sc->sc_state) { 1421 case NCR_RESELECTED: 1422 goto sched; 1423 1424 case NCR_SELECTING: 1425 ecb->xs->error = XS_SELTIMEOUT; 1426 goto finish; 1427 1428 case NCR_CONNECTED: 1429 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1430 #ifdef NCR53C9X_DEBUG 1431 if (ecb) 1432 sc_print_addr(ecb->xs->sc_link); 1433 printf("sync nego not completed!\n"); 1434 #endif 1435 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1436 sc->sc_flags &= ~NCR_SYNCHNEGO; 1437 ti->flags &= 1438 ~(T_NEGOTIATE | T_SYNCMODE); 1439 } 1440 1441 /* it may be OK to disconnect */ 1442 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1443 /* 1444 * Section 5.1.1 of the SCSI 2 spec 1445 * suggests issuing a REQUEST SENSE 1446 * following an unexpected disconnect. 1447 * Some devices go into a contingent 1448 * allegiance condition when 1449 * disconnecting, and this is necessary 1450 * to clean up their state. 1451 */ 1452 printf("%s: unexpected disconnect; ", 1453 sc->sc_dev.dv_xname); 1454 if (ecb->flags & ECB_SENSE) { 1455 printf("resetting\n"); 1456 goto reset; 1457 } 1458 printf("sending REQUEST SENSE\n"); 1459 ncr53c9x_sense(sc, ecb); 1460 goto out; 1461 } 1462 1463 ecb->xs->error = XS_DRIVER_STUFFUP; 1464 goto finish; 1465 1466 case NCR_DISCONNECT: 1467 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1468 sc->sc_nexus = NULL; 1469 goto sched; 1470 1471 case NCR_CMDCOMPLETE: 1472 goto finish; 1473 } 1474 } 1475 1476 switch (sc->sc_state) { 1477 1478 case NCR_SBR: 1479 printf("%s: waiting for SCSI Bus Reset to happen\n", 1480 sc->sc_dev.dv_xname); 1481 return 1; 1482 1483 case NCR_RESELECTED: 1484 /* 1485 * we must be continuing a message ? 1486 */ 1487 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1488 printf("%s: target didn't identify\n", 1489 sc->sc_dev.dv_xname); 1490 ncr53c9x_init(sc, 1); 1491 return 1; 1492 } 1493 printf("<<RESELECT CONT'd>>"); 1494 #if XXXX 1495 ncr53c9x_msgin(sc); 1496 if (sc->sc_state != NCR_CONNECTED) { 1497 /* IDENTIFY fail?! */ 1498 printf("%s: identify failed\n", 1499 sc->sc_dev.dv_xname); 1500 ncr53c9x_init(sc, 1); 1501 return 1; 1502 } 1503 #endif 1504 break; 1505 1506 case NCR_IDLE: 1507 if (sc->sc_flags & NCR_ICCS) printf("[[esp: BUMMER]]"); 1508 case NCR_SELECTING: 1509 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1510 sc->sc_flags = 0; 1511 1512 if (sc->sc_espintr & NCRINTR_RESEL) { 1513 /* 1514 * If we're trying to select a 1515 * target ourselves, push our command 1516 * back into the ready list. 1517 */ 1518 if (sc->sc_state == NCR_SELECTING) { 1519 NCR_MISC(("backoff selector ")); 1520 sc_link = sc->sc_nexus->xs->sc_link; 1521 ti = &sc->sc_tinfo[sc_link->target]; 1522 TAILQ_INSERT_HEAD(&sc->ready_list, 1523 sc->sc_nexus, chain); 1524 ecb = sc->sc_nexus = NULL; 1525 } 1526 sc->sc_state = NCR_RESELECTED; 1527 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1528 /* 1529 * Things are seriously fucked up. 1530 * Pull the brakes, i.e. reset 1531 */ 1532 printf("%s: target didn't identify\n", 1533 sc->sc_dev.dv_xname); 1534 ncr53c9x_init(sc, 1); 1535 return 1; 1536 } 1537 /* 1538 * The C90 only inhibits FIFO writes until 1539 * reselection is complete, instead of 1540 * waiting until the interrupt status register 1541 * has been read. So, if the reselect happens 1542 * while we were entering a command bytes (for 1543 * another target) some of those bytes can 1544 * appear in the FIFO here, after the 1545 * interrupt is taken. 1546 */ 1547 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1548 if (nfifo < 2 || 1549 (nfifo > 2 && 1550 sc->sc_rev != NCR_VARIANT_ESP100)) { 1551 printf("%s: RESELECT: " 1552 "%d bytes in FIFO!\n", 1553 sc->sc_dev.dv_xname, 1554 nfifo); 1555 ncr53c9x_init(sc, 1); 1556 return 1; 1557 } 1558 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1559 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1560 1561 /* Handle identify message */ 1562 ncr53c9x_msgin(sc); 1563 if (nfifo != 2) 1564 NCRCMD(sc, NCRCMD_FLUSH); 1565 1566 if (sc->sc_state != NCR_CONNECTED) { 1567 /* IDENTIFY fail?! */ 1568 printf("%s: identify failed\n", 1569 sc->sc_dev.dv_xname); 1570 ncr53c9x_init(sc, 1); 1571 return 1; 1572 } 1573 continue; /* ie. next phase expected soon */ 1574 } 1575 1576 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1577 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1578 ecb = sc->sc_nexus; 1579 if (!ecb) 1580 panic("esp: not nexus at sc->sc_nexus"); 1581 1582 sc_link = ecb->xs->sc_link; 1583 ti = &sc->sc_tinfo[sc_link->target]; 1584 1585 switch (sc->sc_espstep) { 1586 case 0: 1587 printf("%s: select timeout/no " 1588 "disconnect\n", 1589 sc->sc_dev.dv_xname); 1590 ecb->xs->error = XS_SELTIMEOUT; 1591 goto finish; 1592 case 1: 1593 if ((ti->flags & T_NEGOTIATE) == 0) { 1594 printf("%s: step 1 & !NEG\n", 1595 sc->sc_dev.dv_xname); 1596 goto reset; 1597 } 1598 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1599 printf("%s: !MSGOUT\n", 1600 sc->sc_dev.dv_xname); 1601 goto reset; 1602 } 1603 /* Start negotiating */ 1604 ti->period = sc->sc_minsync; 1605 ti->offset = 15; 1606 sc->sc_flags |= NCR_SYNCHNEGO; 1607 ncr53c9x_sched_msgout(SEND_SDTR); 1608 break; 1609 case 3: 1610 /* 1611 * Grr, this is supposed to mean 1612 * "target left command phase 1613 * prematurely". It seems to happen 1614 * regularly when sync mode is on. 1615 * Look at FIFO to see if command 1616 * went out. 1617 * (Timing problems?) 1618 */ 1619 if ((NCR_READ_REG(sc, NCR_FFLAG) 1620 & NCRFIFO_FF) == 0) { 1621 /* Hope for the best.. */ 1622 break; 1623 } 1624 printf("(%s:%d:%d): selection failed;" 1625 " %d left in FIFO " 1626 "[intr %x, stat %x, step %d]\n", 1627 sc->sc_dev.dv_xname, 1628 sc_link->target, 1629 sc_link->lun, 1630 NCR_READ_REG(sc, NCR_FFLAG) 1631 & NCRFIFO_FF, 1632 sc->sc_espintr, sc->sc_espstat, 1633 sc->sc_espstep); 1634 NCRCMD(sc, NCRCMD_FLUSH); 1635 ncr53c9x_sched_msgout(SEND_ABORT); 1636 return 1; 1637 case 2: 1638 /* Select stuck at Command Phase */ 1639 NCRCMD(sc, NCRCMD_FLUSH); 1640 case 4: 1641 /* So far, everything went fine */ 1642 break; 1643 } 1644 #if 0 1645 if (ecb->xs->flags & SCSI_RESET) 1646 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1647 else if (ti->flags & T_NEGOTIATE) 1648 ncr53c9x_sched_msgout( 1649 SEND_IDENTIFY | SEND_SDTR); 1650 else 1651 ncr53c9x_sched_msgout(SEND_IDENTIFY); 1652 #endif 1653 1654 ecb->flags |= ECB_NEXUS; 1655 ti->lubusy |= (1 << sc_link->lun); 1656 1657 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1658 /* Do an implicit RESTORE POINTERS. */ 1659 sc->sc_dp = ecb->daddr; 1660 sc->sc_dleft = ecb->dleft; 1661 1662 /* On our first connection, schedule a timeout. */ 1663 if ((ecb->xs->flags & SCSI_POLL) == 0) 1664 timeout(ncr53c9x_timeout, ecb, 1665 (ecb->timeout * hz) / 1000); 1666 1667 sc->sc_state = NCR_CONNECTED; 1668 break; 1669 } else { 1670 printf("%s: unexpected status after select" 1671 ": [intr %x, stat %x, step %x]\n", 1672 sc->sc_dev.dv_xname, 1673 sc->sc_espintr, sc->sc_espstat, 1674 sc->sc_espstep); 1675 NCRCMD(sc, NCRCMD_FLUSH); 1676 DELAY(1); 1677 goto reset; 1678 } 1679 if (sc->sc_state == NCR_IDLE) { 1680 printf("%s: stray interrupt\n", 1681 sc->sc_dev.dv_xname); 1682 return 0; 1683 } 1684 break; 1685 1686 case NCR_CONNECTED: 1687 if (sc->sc_flags & NCR_ICCS) { 1688 u_char msg; 1689 1690 sc->sc_flags &= ~NCR_ICCS; 1691 1692 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1693 printf("%s: ICCS: " 1694 ": [intr %x, stat %x, step %x]\n", 1695 sc->sc_dev.dv_xname, 1696 sc->sc_espintr, sc->sc_espstat, 1697 sc->sc_espstep); 1698 } 1699 if ((NCR_READ_REG(sc, NCR_FFLAG) 1700 & NCRFIFO_FF) != 2) { 1701 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1702 & NCRFIFO_FF) - 2; 1703 while (i--) 1704 (void) NCR_READ_REG(sc, 1705 NCR_FIFO); 1706 } 1707 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1708 msg = NCR_READ_REG(sc, NCR_FIFO); 1709 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1710 if (msg == MSG_CMDCOMPLETE) { 1711 ecb->xs->resid = ecb->dleft = 1712 sc->sc_dleft; 1713 sc->sc_state = NCR_CMDCOMPLETE; 1714 } else 1715 printf("%s: STATUS_PHASE: msg %d\n", 1716 sc->sc_dev.dv_xname, msg); 1717 NCRCMD(sc, NCRCMD_MSGOK); 1718 continue; /* ie. wait for disconnect */ 1719 } 1720 break; 1721 default: 1722 panic("%s: invalid state: %d", 1723 sc->sc_dev.dv_xname, 1724 sc->sc_state); 1725 } 1726 1727 /* 1728 * Driver is now in state NCR_CONNECTED, i.e. we 1729 * have a current command working the SCSI bus. 1730 */ 1731 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1732 panic("esp no nexus"); 1733 } 1734 1735 switch (sc->sc_phase) { 1736 case MESSAGE_OUT_PHASE: 1737 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1738 ncr53c9x_msgout(sc); 1739 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1740 break; 1741 case MESSAGE_IN_PHASE: 1742 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1743 if (sc->sc_espintr & NCRINTR_BS) { 1744 NCRCMD(sc, NCRCMD_FLUSH); 1745 sc->sc_flags |= NCR_WAITI; 1746 NCRCMD(sc, NCRCMD_TRANS); 1747 } else if (sc->sc_espintr & NCRINTR_FC) { 1748 if ((sc->sc_flags & NCR_WAITI) == 0) { 1749 printf("%s: MSGIN: unexpected FC bit: " 1750 "[intr %x, stat %x, step %x]\n", 1751 sc->sc_dev.dv_xname, 1752 sc->sc_espintr, sc->sc_espstat, 1753 sc->sc_espstep); 1754 } 1755 sc->sc_flags &= ~NCR_WAITI; 1756 ncr53c9x_msgin(sc); 1757 } else { 1758 printf("%s: MSGIN: weird bits: " 1759 "[intr %x, stat %x, step %x]\n", 1760 sc->sc_dev.dv_xname, 1761 sc->sc_espintr, sc->sc_espstat, 1762 sc->sc_espstep); 1763 } 1764 sc->sc_prevphase = MESSAGE_IN_PHASE; 1765 break; 1766 case COMMAND_PHASE: { 1767 /* well, this means send the command again */ 1768 u_char *cmd = (u_char *)&ecb->cmd; 1769 int i; 1770 1771 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 1772 ecb->cmd.opcode, ecb->clen)); 1773 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1774 NCRCMD(sc, NCRCMD_FLUSH); 1775 DELAY(1); 1776 } 1777 /* Now the command into the FIFO */ 1778 for (i = 0; i < ecb->clen; i++) 1779 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 1780 NCRCMD(sc, NCRCMD_TRANS); 1781 sc->sc_prevphase = COMMAND_PHASE; 1782 } 1783 break; 1784 case DATA_OUT_PHASE: 1785 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 1786 NCRCMD(sc, NCRCMD_FLUSH); 1787 size = min(sc->sc_dleft, sc->sc_maxxfer); 1788 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1789 0, &size); 1790 sc->sc_prevphase = DATA_OUT_PHASE; 1791 goto setup_xfer; 1792 case DATA_IN_PHASE: 1793 NCR_PHASE(("DATA_IN_PHASE ")); 1794 if (sc->sc_rev == NCR_VARIANT_ESP100) 1795 NCRCMD(sc, NCRCMD_FLUSH); 1796 size = min(sc->sc_dleft, sc->sc_maxxfer); 1797 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1798 1, &size); 1799 sc->sc_prevphase = DATA_IN_PHASE; 1800 setup_xfer: 1801 /* Program the SCSI counter */ 1802 NCR_WRITE_REG(sc, NCR_TCL, size); 1803 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1804 if (sc->sc_cfg2 & NCRCFG2_FE) { 1805 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1806 } 1807 /* load the count in */ 1808 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1809 1810 /* 1811 * Note that if `size' is 0, we've already transceived 1812 * all the bytes we want but we're still in DATA PHASE. 1813 * Apparently, the device needs padding. Also, a 1814 * transfer size of 0 means "maximum" to the chip 1815 * DMA logic. 1816 */ 1817 NCRCMD(sc, 1818 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 1819 NCRDMA_GO(sc); 1820 return 1; 1821 case STATUS_PHASE: 1822 NCR_PHASE(("STATUS_PHASE ")); 1823 sc->sc_flags |= NCR_ICCS; 1824 NCRCMD(sc, NCRCMD_ICCS); 1825 sc->sc_prevphase = STATUS_PHASE; 1826 break; 1827 case INVALID_PHASE: 1828 break; 1829 default: 1830 printf("%s: unexpected bus phase; resetting\n", 1831 sc->sc_dev.dv_xname); 1832 goto reset; 1833 } 1834 } 1835 panic("esp: should not get here.."); 1836 1837 reset: 1838 ncr53c9x_init(sc, 1); 1839 return 1; 1840 1841 finish: 1842 untimeout(ncr53c9x_timeout, ecb); 1843 ncr53c9x_done(sc, ecb); 1844 goto out; 1845 1846 sched: 1847 sc->sc_state = NCR_IDLE; 1848 ncr53c9x_sched(sc); 1849 goto out; 1850 1851 out: 1852 return 1; 1853 } 1854 1855 void 1856 ncr53c9x_abort(sc, ecb) 1857 struct ncr53c9x_softc *sc; 1858 struct ncr53c9x_ecb *ecb; 1859 { 1860 1861 /* 2 secs for the abort */ 1862 ecb->timeout = NCR_ABORT_TIMEOUT; 1863 ecb->flags |= ECB_ABORT; 1864 1865 if (ecb == sc->sc_nexus) { 1866 /* 1867 * If we're still selecting, the message will be scheduled 1868 * after selection is complete. 1869 */ 1870 if (sc->sc_state == NCR_CONNECTED) 1871 ncr53c9x_sched_msgout(SEND_ABORT); 1872 1873 /* 1874 * Reschedule timeout. First, cancel a queued timeout (if any) 1875 * in case someone decides to call ncr53c9x_abort() from 1876 * elsewhere. 1877 */ 1878 untimeout(ncr53c9x_timeout, ecb); 1879 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 1880 } else { 1881 ncr53c9x_dequeue(sc, ecb); 1882 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1883 if (sc->sc_state == NCR_IDLE) 1884 ncr53c9x_sched(sc); 1885 } 1886 } 1887 1888 void 1889 ncr53c9x_timeout(arg) 1890 void *arg; 1891 { 1892 struct ncr53c9x_ecb *ecb = arg; 1893 struct scsi_xfer *xs = ecb->xs; 1894 struct scsi_link *sc_link = xs->sc_link; 1895 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 1896 int s; 1897 1898 sc_print_addr(sc_link); 1899 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 1900 "<state %d, nexus %p, phase(c %x, p %x), resid %lx, " 1901 "msg(q %x,o %x) %s>", 1902 sc->sc_dev.dv_xname, 1903 ecb, ecb->flags, ecb->dleft, ecb->stat, 1904 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 1905 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 1906 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 1907 #if NCR53C9X_DEBUG > 0 1908 printf("TRACE: %s.", ecb->trace); 1909 #endif 1910 1911 s = splbio(); 1912 1913 if (ecb->flags & ECB_ABORT) { 1914 /* abort timed out */ 1915 printf(" AGAIN\n"); 1916 ncr53c9x_init(sc, 1); 1917 } else { 1918 /* abort the operation that has timed out */ 1919 printf("\n"); 1920 xs->error = XS_TIMEOUT; 1921 ncr53c9x_abort(sc, ecb); 1922 } 1923 1924 splx(s); 1925 } 1926
Indexes created Fri Sep 26 20:09:58 GMT 2025