ncr53c9x.c revision 1.50 1 /* $NetBSD: ncr53c9x.c,v 1.50 2000/06/05 07:59:54 nisimura Exp $ */
2
3 /*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Copyright (c) 1994 Peter Galbavy
41 * Copyright (c) 1995 Paul Kranenburg
42 * All rights reserved.
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
46 * are met:
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. All advertising materials mentioning features or use of this software
53 * must display the following acknowledgement:
54 * This product includes software developed by Peter Galbavy
55 * 4. The name of the author may not be used to endorse or promote products
56 * derived from this software without specific prior written permission.
57 *
58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
68 * POSSIBILITY OF SUCH DAMAGE.
69 */
70
71 /*
72 * Based on aic6360 by Jarle Greipsland
73 *
74 * Acknowledgements: Many of the algorithms used in this driver are
75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and
76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million!
77 */
78
79 #include <sys/types.h>
80 #include <sys/param.h>
81 #include <sys/systm.h>
82 #include <sys/callout.h>
83 #include <sys/kernel.h>
84 #include <sys/errno.h>
85 #include <sys/ioctl.h>
86 #include <sys/device.h>
87 #include <sys/buf.h>
88 #include <sys/malloc.h>
89 #include <sys/proc.h>
90 #include <sys/user.h>
91 #include <sys/queue.h>
92
93 #include <dev/scsipi/scsi_all.h>
94 #include <dev/scsipi/scsipi_all.h>
95 #include <dev/scsipi/scsiconf.h>
96 #include <dev/scsipi/scsi_message.h>
97
98 #include <machine/cpu.h>
99
100 #include <dev/ic/ncr53c9xreg.h>
101 #include <dev/ic/ncr53c9xvar.h>
102
103 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/
104
105 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *));
106 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *,
107 struct ncr53c9x_ecb *));
108 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int));
109 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *));
110 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *,
111 struct scsipi_xfer *, int));
112 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *));
113 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *,
114 struct ncr53c9x_ecb *));
115 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *));
116 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *));
117 /*static*/ void ncr53c9x_timeout __P((void *arg));
118 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *,
119 struct ncr53c9x_ecb *));
120 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *,
121 struct ncr53c9x_ecb *));
122
123 void ncr53c9x_sense __P((struct ncr53c9x_softc *,
124 struct ncr53c9x_ecb *));
125 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *,
126 struct ncr53c9x_ecb *, int));
127 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int));
128
129 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int));
130 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *,
131 struct ncr53c9x_tinfo *));
132
133 /*
134 * Names for the NCR53c9x variants, correspnding to the variant tags
135 * in ncr53c9xvar.h.
136 */
137 static const char *ncr53c9x_variant_names[] = {
138 "ESP100",
139 "ESP100A",
140 "ESP200",
141 "NCR53C94",
142 "NCR53C96",
143 "ESP406",
144 "FAS408",
145 "FAS216",
146 "AM53C974",
147 };
148
149 static struct scsipi_adapter ncr53c9x_adapter = {
150 0, /* adapter refcnt */
151 ncr53c9x_scsi_cmd, /* cmd */
152 minphys, /* minphys */
153 NULL, /* ioctl */
154 NULL, /* getgeom */
155 };
156
157 static struct scsipi_device ncr53c9x_device = {
158 NULL, /* use default error handler */
159 NULL, /* have a queue, served by this */
160 NULL, /* have no async handler */
161 NULL, /* use default 'done' routine */
162 };
163
164 /*
165 * Attach this instance, and then all the sub-devices
166 */
167 void
168 ncr53c9x_attach(sc, adapter, device)
169 struct ncr53c9x_softc *sc;
170 struct scsipi_adapter *adapter;
171 struct scsipi_device *device;
172 {
173
174 /*
175 * Allocate SCSI message buffers.
176 * Front-ends can override allocation to avoid alignment
177 * handling in the DMA engines. Note that that ncr53c9x_msgout()
178 * can request a 1 byte DMA transfer.
179 */
180 if (sc->sc_omess == NULL)
181 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT);
182
183 if (sc->sc_imess == NULL)
184 sc->sc_imess = malloc(NCR_MAX_MSG_LEN+1, M_DEVBUF, M_NOWAIT);
185
186 if (sc->sc_omess == NULL || sc->sc_imess == NULL) {
187 printf("out of memory\n");
188 return;
189 }
190
191 /*
192 * Note, the front-end has set us up to print the chip variation.
193 */
194 if (sc->sc_rev >= NCR_VARIANT_MAX) {
195 printf("\n%s: unknown variant %d, devices not attached\n",
196 sc->sc_dev.dv_xname, sc->sc_rev);
197 return;
198 }
199
200 printf(": %s, %dMHz, SCSI ID %d\n",
201 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id);
202
203 sc->sc_ccf = FREQTOCCF(sc->sc_freq);
204
205 /* The value *must not* be == 1. Make it 2 */
206 if (sc->sc_ccf == 1)
207 sc->sc_ccf = 2;
208
209 /*
210 * The recommended timeout is 250ms. This register is loaded
211 * with a value calculated as follows, from the docs:
212 *
213 * (timout period) x (CLK frequency)
214 * reg = -------------------------------------
215 * 8192 x (Clock Conversion Factor)
216 *
217 * Since CCF has a linear relation to CLK, this generally computes
218 * to the constant of 153.
219 */
220 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf);
221
222 /* CCF register only has 3 bits; 0 is actually 8 */
223 sc->sc_ccf &= 7;
224
225 /*
226 * fill in the prototype scsipi_link.
227 */
228 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
229 sc->sc_link.adapter_softc = sc;
230 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id;
231 sc->sc_link.adapter = (adapter) ? adapter : &ncr53c9x_adapter;
232 sc->sc_link.device = (device) ? device : &ncr53c9x_device;
233 sc->sc_link.openings = 2;
234 sc->sc_link.scsipi_scsi.max_target = 7;
235 sc->sc_link.scsipi_scsi.max_lun = 7;
236 sc->sc_link.type = BUS_SCSI;
237
238 /*
239 * Add reference to adapter so that we drop the reference after
240 * config_found() to make sure the adatper is disabled.
241 */
242 if (scsipi_adapter_addref(&sc->sc_link) != 0) {
243 printf("%s: unable to enable controller\n",
244 sc->sc_dev.dv_xname);
245 return;
246 }
247
248 /* Reset state & bus */
249 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags;
250 sc->sc_state = 0;
251 ncr53c9x_init(sc, 1);
252
253 /*
254 * Now try to attach all the sub-devices
255 */
256 sc->sc_child = config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
257
258 scsipi_adapter_delref(&sc->sc_link);
259 }
260
261 int
262 ncr53c9x_detach(sc, flags)
263 struct ncr53c9x_softc *sc;
264 int flags;
265 {
266 int error;
267
268 if (sc->sc_child) {
269 error = config_detach(sc->sc_child, flags);
270 if (error)
271 return (error);
272 }
273
274 free(sc->sc_imess, M_DEVBUF);
275 free(sc->sc_omess, M_DEVBUF);
276
277 return (0);
278 }
279
280 /*
281 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus,
282 * only this controller, but kills any on-going commands, and also stops
283 * and resets the DMA.
284 *
285 * After reset, registers are loaded with the defaults from the attach
286 * routine above.
287 */
288 void
289 ncr53c9x_reset(sc)
290 struct ncr53c9x_softc *sc;
291 {
292
293 /* reset DMA first */
294 NCRDMA_RESET(sc);
295
296 /* reset SCSI chip */
297 NCRCMD(sc, NCRCMD_RSTCHIP);
298 NCRCMD(sc, NCRCMD_NOP);
299 DELAY(500);
300
301 /* do these backwards, and fall through */
302 switch (sc->sc_rev) {
303 case NCR_VARIANT_ESP406:
304 case NCR_VARIANT_FAS408:
305 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT);
306 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4);
307 case NCR_VARIANT_AM53C974:
308 case NCR_VARIANT_FAS216:
309 case NCR_VARIANT_NCR53C94:
310 case NCR_VARIANT_NCR53C96:
311 case NCR_VARIANT_ESP200:
312 sc->sc_features |= NCR_F_HASCFG3;
313 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
314 case NCR_VARIANT_ESP100A:
315 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
316 case NCR_VARIANT_ESP100:
317 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
318 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
319 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
320 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
321 break;
322 default:
323 printf("%s: unknown revision code, assuming ESP100\n",
324 sc->sc_dev.dv_xname);
325 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
326 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
327 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
328 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
329 }
330
331 if (sc->sc_rev == NCR_VARIANT_AM53C974)
332 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4);
333 }
334
335 /*
336 * Reset the SCSI bus, but not the chip
337 */
338 void
339 ncr53c9x_scsi_reset(sc)
340 struct ncr53c9x_softc *sc;
341 {
342
343 (*sc->sc_glue->gl_dma_stop)(sc);
344
345 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname);
346 NCRCMD(sc, NCRCMD_RSTSCSI);
347 }
348
349 /*
350 * Initialize ncr53c9x state machine
351 */
352 void
353 ncr53c9x_init(sc, doreset)
354 struct ncr53c9x_softc *sc;
355 int doreset;
356 {
357 struct ncr53c9x_ecb *ecb;
358 int r;
359
360 NCR_TRACE(("[NCR_INIT(%d)] ", doreset));
361
362 if (sc->sc_state == 0) {
363 /* First time through; initialize. */
364 TAILQ_INIT(&sc->ready_list);
365 TAILQ_INIT(&sc->nexus_list);
366 TAILQ_INIT(&sc->free_list);
367 sc->sc_nexus = NULL;
368 ecb = sc->sc_ecb;
369 bzero(ecb, sizeof(sc->sc_ecb));
370 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) {
371 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain);
372 ecb++;
373 }
374 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo));
375 } else {
376 /* Cancel any active commands. */
377 sc->sc_state = NCR_CLEANING;
378 if ((ecb = sc->sc_nexus) != NULL) {
379 ecb->xs->error = XS_TIMEOUT;
380 ncr53c9x_done(sc, ecb);
381 }
382 while ((ecb = sc->nexus_list.tqh_first) != NULL) {
383 ecb->xs->error = XS_TIMEOUT;
384 ncr53c9x_done(sc, ecb);
385 }
386 }
387
388 /*
389 * reset the chip to a known state
390 */
391 ncr53c9x_reset(sc);
392
393 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
394 for (r = 0; r < 8; r++) {
395 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r];
396 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */
397
398 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<(r+8))))
399 ? T_NEGOTIATE : 0) |
400 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) |
401 T_NEED_TO_RESET;
402 ti->period = sc->sc_minsync;
403 ti->offset = 0;
404 }
405
406 if (doreset) {
407 sc->sc_state = NCR_SBR;
408 NCRCMD(sc, NCRCMD_RSTSCSI);
409 } else {
410 sc->sc_state = NCR_IDLE;
411 ncr53c9x_sched(sc);
412 }
413 }
414
415 /*
416 * Read the NCR registers, and save their contents for later use.
417 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading
418 * NCR_INTR - so make sure it is the last read.
419 *
420 * I think that (from reading the docs) most bits in these registers
421 * only make sense when he DMA CSR has an interrupt showing. Call only
422 * if an interrupt is pending.
423 */
424 __inline__ void
425 ncr53c9x_readregs(sc)
426 struct ncr53c9x_softc *sc;
427 {
428
429 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT);
430 /* Only the stepo bits are of interest */
431 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK;
432 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR);
433
434 if (sc->sc_glue->gl_clear_latched_intr != NULL)
435 (*sc->sc_glue->gl_clear_latched_intr)(sc);
436
437 /*
438 * Determine the SCSI bus phase, return either a real SCSI bus phase
439 * or some pseudo phase we use to detect certain exceptions.
440 */
441
442 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS)
443 ? /* Disconnected */ BUSFREE_PHASE
444 : sc->sc_espstat & NCRSTAT_PHASE;
445
446 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ",
447 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep));
448 }
449
450 /*
451 * Convert Synchronous Transfer Period to chip register Clock Per Byte value.
452 */
453 static inline int
454 ncr53c9x_stp2cpb(sc, period)
455 struct ncr53c9x_softc *sc;
456 int period;
457 {
458 int v;
459 v = (sc->sc_freq * period) / 250;
460 if (ncr53c9x_cpb2stp(sc, v) < period)
461 /* Correct round-down error */
462 v++;
463 return (v);
464 }
465
466 static inline void
467 ncr53c9x_setsync(sc, ti)
468 struct ncr53c9x_softc *sc;
469 struct ncr53c9x_tinfo *ti;
470 {
471 u_char syncoff, synctp, cfg3 = sc->sc_cfg3;
472
473 if (ti->flags & T_SYNCMODE) {
474 syncoff = ti->offset;
475 synctp = ncr53c9x_stp2cpb(sc, ti->period);
476 if (sc->sc_features & NCR_F_FASTSCSI) {
477 /*
478 * If the period is 200ns or less (ti->period <= 50),
479 * put the chip in Fast SCSI mode.
480 */
481 if (ti->period <= 50)
482 /*
483 * There are (at least) 4 variations of the
484 * configuration 3 register. The drive attach
485 * routine sets the appropriate bit to put the
486 * chip into Fast SCSI mode so that it doesn't
487 * have to be figured out here each time.
488 */
489 cfg3 |= sc->sc_cfg3_fscsi;
490 }
491
492 /*
493 * Am53c974 requires different SYNCTP values when the
494 * FSCSI bit is off.
495 */
496 if (sc->sc_rev == NCR_VARIANT_AM53C974 &&
497 (cfg3 & NCRAMDCFG3_FSCSI) == 0)
498 synctp--;
499 } else {
500 syncoff = 0;
501 synctp = 0;
502 }
503
504 if (sc->sc_features & NCR_F_HASCFG3)
505 NCR_WRITE_REG(sc, NCR_CFG3, cfg3);
506
507 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff);
508 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp);
509 }
510
511 int ncr53c9x_dmaselect = 0;
512 /*
513 * Send a command to a target, set the driver state to NCR_SELECTING
514 * and let the caller take care of the rest.
515 *
516 * Keeping this as a function allows me to say that this may be done
517 * by DMA instead of programmed I/O soon.
518 */
519 void
520 ncr53c9x_select(sc, ecb)
521 struct ncr53c9x_softc *sc;
522 struct ncr53c9x_ecb *ecb;
523 {
524 struct scsipi_link *sc_link = ecb->xs->sc_link;
525 int target = sc_link->scsipi_scsi.target;
526 int lun = sc_link->scsipi_scsi.lun;
527 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target];
528 int tiflags = ti->flags;
529 u_char *cmd;
530 int clen;
531 size_t dmasize;
532
533 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ",
534 target, lun, ecb->cmd.cmd.opcode));
535
536 sc->sc_state = NCR_SELECTING;
537
538 /*
539 * Schedule the timeout now, the first time we will go away
540 * expecting to come back due to an interrupt, because it is
541 * always possible that the interrupt may never happen.
542 */
543 if ((ecb->xs->xs_control & XS_CTL_POLL) == 0)
544 callout_reset(&ecb->xs->xs_callout, (ecb->timeout * hz) / 1000,
545 ncr53c9x_timeout, ecb);
546
547 /*
548 * The docs say the target register is never reset, and I
549 * can't think of a better place to set it
550 */
551 NCR_WRITE_REG(sc, NCR_SELID, target);
552 ncr53c9x_setsync(sc, ti);
553
554 if (ecb->flags & ECB_SENSE) {
555 /*
556 * For REQUEST SENSE, we should not send an IDENTIFY or
557 * otherwise mangle the target. There should be no MESSAGE IN
558 * phase.
559 */
560 if (ncr53c9x_dmaselect) {
561 /* setup DMA transfer for command */
562 dmasize = clen = ecb->clen;
563 sc->sc_cmdlen = clen;
564 sc->sc_cmdp = (caddr_t)&ecb->cmd + 1;
565 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize);
566
567 /* Program the SCSI counter */
568 NCR_WRITE_REG(sc, NCR_TCL, dmasize);
569 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8);
570 if (sc->sc_cfg2 & NCRCFG2_FE) {
571 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16);
572 }
573
574 /* load the count in */
575 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
576
577 /* And get the targets attention */
578 NCRCMD(sc, NCRCMD_SELNATN | NCRCMD_DMA);
579 NCRDMA_GO(sc);
580 } else {
581 /* Now the command into the FIFO */
582 cmd = (u_char *)&ecb->cmd.cmd;
583 clen = ecb->clen;
584 while (clen--)
585 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++);
586
587 NCRCMD(sc, NCRCMD_SELNATN);
588 }
589 return;
590 }
591
592 if (ncr53c9x_dmaselect && (tiflags & T_NEGOTIATE) == 0) {
593 ecb->cmd.id =
594 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1);
595
596 /* setup DMA transfer for command */
597 dmasize = clen = ecb->clen + 1;
598 sc->sc_cmdlen = clen;
599 sc->sc_cmdp = (caddr_t)&ecb->cmd;
600 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize);
601
602 /* Program the SCSI counter */
603 NCR_WRITE_REG(sc, NCR_TCL, dmasize);
604 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8);
605 if (sc->sc_cfg2 & NCRCFG2_FE) {
606 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16);
607 }
608
609 /* load the count in */
610 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
611
612 /* And get the targets attention */
613 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA);
614 NCRDMA_GO(sc);
615 return;
616 }
617
618 /*
619 * Who am I. This is where we tell the target that we are
620 * happy for it to disconnect etc.
621 */
622 NCR_WRITE_REG(sc, NCR_FIFO,
623 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1));
624
625 if (ti->flags & T_NEGOTIATE) {
626 /* Arbitrate, select and stop after IDENTIFY message */
627 NCRCMD(sc, NCRCMD_SELATNS);
628 return;
629 }
630
631 /* Now the command into the FIFO */
632 cmd = (u_char *)&ecb->cmd.cmd;
633 clen = ecb->clen;
634 while (clen--)
635 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++);
636
637 /* And get the targets attention */
638 NCRCMD(sc, NCRCMD_SELATN);
639 }
640
641 void
642 ncr53c9x_free_ecb(sc, ecb, flags)
643 struct ncr53c9x_softc *sc;
644 struct ncr53c9x_ecb *ecb;
645 int flags;
646 {
647 int s;
648
649 s = splbio();
650
651 ecb->flags = 0;
652 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain);
653
654 /*
655 * If there were none, wake anybody waiting for one to come free,
656 * starting with queued entries.
657 */
658 if (ecb->chain.tqe_next == 0)
659 wakeup(&sc->free_list);
660
661 splx(s);
662 }
663
664 struct ncr53c9x_ecb *
665 ncr53c9x_get_ecb(sc, flags)
666 struct ncr53c9x_softc *sc;
667 int flags;
668 {
669 struct ncr53c9x_ecb *ecb;
670 int s;
671
672 s = splbio();
673
674 while ((ecb = sc->free_list.tqh_first) == NULL &&
675 (flags & XS_CTL_NOSLEEP) == 0)
676 tsleep(&sc->free_list, PRIBIO, "especb", 0);
677 if (ecb) {
678 TAILQ_REMOVE(&sc->free_list, ecb, chain);
679 ecb->flags |= ECB_ALLOC;
680 }
681
682 splx(s);
683 return (ecb);
684 }
685
686 /*
687 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
688 */
689
690 /*
691 * Start a SCSI-command
692 * This function is called by the higher level SCSI-driver to queue/run
693 * SCSI-commands.
694 */
695 int
696 ncr53c9x_scsi_cmd(xs)
697 struct scsipi_xfer *xs;
698 {
699 struct scsipi_link *sc_link = xs->sc_link;
700 struct ncr53c9x_softc *sc = sc_link->adapter_softc;
701 struct ncr53c9x_ecb *ecb;
702 int s, flags;
703
704 NCR_TRACE(("[ncr53c9x_scsi_cmd] "));
705 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen,
706 sc_link->scsipi_scsi.target));
707
708 flags = xs->xs_control;
709 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL)
710 return (TRY_AGAIN_LATER);
711
712 /* Initialize ecb */
713 ecb->xs = xs;
714 ecb->timeout = xs->timeout;
715
716 if (flags & XS_CTL_RESET) {
717 ecb->flags |= ECB_RESET;
718 ecb->clen = 0;
719 ecb->dleft = 0;
720 } else {
721 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen);
722 ecb->clen = xs->cmdlen;
723 ecb->daddr = xs->data;
724 ecb->dleft = xs->datalen;
725 }
726 ecb->stat = 0;
727
728 s = splbio();
729
730 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain);
731 if (sc->sc_state == NCR_IDLE)
732 ncr53c9x_sched(sc);
733
734 splx(s);
735
736 if ((flags & XS_CTL_POLL) == 0)
737 return (SUCCESSFULLY_QUEUED);
738
739 /* Not allowed to use interrupts, use polling instead */
740 if (ncr53c9x_poll(sc, xs, ecb->timeout)) {
741 ncr53c9x_timeout(ecb);
742 if (ncr53c9x_poll(sc, xs, ecb->timeout))
743 ncr53c9x_timeout(ecb);
744 }
745 return (COMPLETE);
746 }
747
748 /*
749 * Used when interrupt driven I/O isn't allowed, e.g. during boot.
750 */
751 int
752 ncr53c9x_poll(sc, xs, count)
753 struct ncr53c9x_softc *sc;
754 struct scsipi_xfer *xs;
755 int count;
756 {
757
758 NCR_TRACE(("[ncr53c9x_poll] "));
759 while (count) {
760 if (NCRDMA_ISINTR(sc)) {
761 ncr53c9x_intr(sc);
762 }
763 #if alternatively
764 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT)
765 ncr53c9x_intr(sc);
766 #endif
767 if ((xs->xs_status & XS_STS_DONE) != 0)
768 return (0);
769 if (sc->sc_state == NCR_IDLE) {
770 NCR_TRACE(("[ncr53c9x_poll: rescheduling] "));
771 ncr53c9x_sched(sc);
772 }
773 DELAY(1000);
774 count--;
775 }
776 return (1);
777 }
778
779
780 /*
781 * LOW LEVEL SCSI UTILITIES
782 */
783
784 /*
785 * Schedule a scsi operation. This has now been pulled out of the interrupt
786 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done.
787 * This may save us an unecessary interrupt just to get things going.
788 * Should only be called when state == NCR_IDLE and at bio pl.
789 */
790 void
791 ncr53c9x_sched(sc)
792 struct ncr53c9x_softc *sc;
793 {
794 struct ncr53c9x_ecb *ecb;
795 struct scsipi_link *sc_link;
796 struct ncr53c9x_tinfo *ti;
797
798 NCR_TRACE(("[ncr53c9x_sched] "));
799 if (sc->sc_state != NCR_IDLE)
800 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state);
801
802 /*
803 * Find first ecb in ready queue that is for a target/lunit
804 * combinations that is not busy.
805 */
806 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) {
807 sc_link = ecb->xs->sc_link;
808 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
809 if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) {
810 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
811 sc->sc_nexus = ecb;
812 ncr53c9x_select(sc, ecb);
813 break;
814 } else
815 NCR_MISC(("%d:%d busy\n",
816 sc_link->scsipi_scsi.target,
817 sc_link->scsipi_scsi.lun));
818 }
819 }
820
821 void
822 ncr53c9x_sense(sc, ecb)
823 struct ncr53c9x_softc *sc;
824 struct ncr53c9x_ecb *ecb;
825 {
826 struct scsipi_xfer *xs = ecb->xs;
827 struct scsipi_link *sc_link = xs->sc_link;
828 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
829 struct scsipi_sense *ss = (void *)&ecb->cmd.cmd;
830
831 NCR_MISC(("requesting sense "));
832 /* Next, setup a request sense command block */
833 bzero(ss, sizeof(*ss));
834 ss->opcode = REQUEST_SENSE;
835 ss->byte2 = sc_link->scsipi_scsi.lun << 5;
836 ss->length = sizeof(struct scsipi_sense_data);
837 ecb->clen = sizeof(*ss);
838 ecb->daddr = (char *)&xs->sense.scsi_sense;
839 ecb->dleft = sizeof(struct scsipi_sense_data);
840 ecb->flags |= ECB_SENSE;
841 ecb->timeout = NCR_SENSE_TIMEOUT;
842 ti->senses++;
843 if (ecb->flags & ECB_NEXUS)
844 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun);
845 if (ecb == sc->sc_nexus) {
846 ecb->flags &= ~ECB_NEXUS;
847 ncr53c9x_select(sc, ecb);
848 } else {
849 ncr53c9x_dequeue(sc, ecb);
850 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
851 if (sc->sc_state == NCR_IDLE)
852 ncr53c9x_sched(sc);
853 }
854 }
855
856 /*
857 * POST PROCESSING OF SCSI_CMD (usually current)
858 */
859 void
860 ncr53c9x_done(sc, ecb)
861 struct ncr53c9x_softc *sc;
862 struct ncr53c9x_ecb *ecb;
863 {
864 struct scsipi_xfer *xs = ecb->xs;
865 struct scsipi_link *sc_link = xs->sc_link;
866 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
867
868 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error));
869
870 callout_stop(&ecb->xs->xs_callout);
871
872 /*
873 * Now, if we've come here with no error code, i.e. we've kept the
874 * initial XS_NOERROR, and the status code signals that we should
875 * check sense, we'll need to set up a request sense cmd block and
876 * push the command back into the ready queue *before* any other
877 * commands for this target/lunit, else we lose the sense info.
878 * We don't support chk sense conditions for the request sense cmd.
879 */
880 if (xs->error == XS_NOERROR) {
881 xs->status = ecb->stat;
882 if ((ecb->flags & ECB_ABORT) != 0) {
883 xs->error = XS_TIMEOUT;
884 } else if ((ecb->flags & ECB_SENSE) != 0) {
885 xs->error = XS_SENSE;
886 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) {
887 /* First, save the return values */
888 xs->resid = ecb->dleft;
889 ncr53c9x_sense(sc, ecb);
890 return;
891 } else {
892 xs->resid = ecb->dleft;
893 }
894 }
895
896 xs->xs_status |= XS_STS_DONE;
897
898 #ifdef NCR53C9X_DEBUG
899 if (ncr53c9x_debug & NCR_SHOWMISC) {
900 if (xs->resid != 0)
901 printf("resid=%d ", xs->resid);
902 if (xs->error == XS_SENSE)
903 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code);
904 else
905 printf("error=%d\n", xs->error);
906 }
907 #endif
908
909 /*
910 * Remove the ECB from whatever queue it's on.
911 */
912 if (ecb->flags & ECB_NEXUS)
913 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun);
914 if (ecb == sc->sc_nexus) {
915 sc->sc_nexus = NULL;
916 if (sc->sc_state != NCR_CLEANING) {
917 sc->sc_state = NCR_IDLE;
918 ncr53c9x_sched(sc);
919 }
920 } else
921 ncr53c9x_dequeue(sc, ecb);
922
923 ncr53c9x_free_ecb(sc, ecb, xs->xs_control);
924 ti->cmds++;
925 scsipi_done(xs);
926 }
927
928 void
929 ncr53c9x_dequeue(sc, ecb)
930 struct ncr53c9x_softc *sc;
931 struct ncr53c9x_ecb *ecb;
932 {
933
934 if (ecb->flags & ECB_NEXUS) {
935 TAILQ_REMOVE(&sc->nexus_list, ecb, chain);
936 ecb->flags &= ~ECB_NEXUS;
937 } else {
938 TAILQ_REMOVE(&sc->ready_list, ecb, chain);
939 }
940 }
941
942 /*
943 * INTERRUPT/PROTOCOL ENGINE
944 */
945
946 /*
947 * Schedule an outgoing message by prioritizing it, and asserting
948 * attention on the bus. We can only do this when we are the initiator
949 * else there will be an illegal command interrupt.
950 */
951 #define ncr53c9x_sched_msgout(m) \
952 do { \
953 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \
954 NCRCMD(sc, NCRCMD_SETATN); \
955 sc->sc_flags |= NCR_ATN; \
956 sc->sc_msgpriq |= (m); \
957 } while (0)
958
959 int
960 ncr53c9x_reselect(sc, message)
961 struct ncr53c9x_softc *sc;
962 int message;
963 {
964 u_char selid, target, lun;
965 struct ncr53c9x_ecb *ecb;
966 struct scsipi_link *sc_link;
967 struct ncr53c9x_tinfo *ti;
968
969 /*
970 * The SCSI chip made a snapshot of the data bus while the reselection
971 * was being negotiated. This enables us to determine which target did
972 * the reselect.
973 */
974 selid = sc->sc_selid & ~(1 << sc->sc_id);
975 if (selid & (selid - 1)) {
976 printf("%s: reselect with invalid selid %02x;"
977 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid);
978 goto reset;
979 }
980
981 /*
982 * Search wait queue for disconnected cmd
983 * The list should be short, so I haven't bothered with
984 * any more sophisticated structures than a simple
985 * singly linked list.
986 */
987 target = ffs(selid) - 1;
988 lun = message & 0x07;
989 for (ecb = sc->nexus_list.tqh_first; ecb != NULL;
990 ecb = ecb->chain.tqe_next) {
991 sc_link = ecb->xs->sc_link;
992 if (sc_link->scsipi_scsi.target == target &&
993 sc_link->scsipi_scsi.lun == lun)
994 break;
995 }
996 if (ecb == NULL) {
997 printf("%s: reselect from target %d lun %d with no nexus;"
998 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun);
999 goto abort;
1000 }
1001
1002 /* Make this nexus active again. */
1003 TAILQ_REMOVE(&sc->nexus_list, ecb, chain);
1004 sc->sc_state = NCR_CONNECTED;
1005 sc->sc_nexus = ecb;
1006 ti = &sc->sc_tinfo[target];
1007 #ifdef NCR53C9X_DEBUG
1008 if ((ti->lubusy & (1 << lun)) == 0) {
1009 printf("%s: reselect: target %d, lun %d: should be busy\n",
1010 sc->sc_dev.dv_xname, target, lun);
1011 ti->lubusy |= (1 << lun);
1012 }
1013 #endif
1014 ncr53c9x_setsync(sc, ti);
1015
1016 if (ecb->flags & ECB_RESET)
1017 ncr53c9x_sched_msgout(SEND_DEV_RESET);
1018 else if (ecb->flags & ECB_ABORT)
1019 ncr53c9x_sched_msgout(SEND_ABORT);
1020
1021 /* Do an implicit RESTORE POINTERS. */
1022 sc->sc_dp = ecb->daddr;
1023 sc->sc_dleft = ecb->dleft;
1024
1025 return (0);
1026
1027 reset:
1028 ncr53c9x_sched_msgout(SEND_DEV_RESET);
1029 return (1);
1030
1031 abort:
1032 ncr53c9x_sched_msgout(SEND_ABORT);
1033 return (1);
1034 }
1035
1036 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80)
1037 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20)
1038 #define ISEXTMSG(m) ((m) == 1)
1039
1040 /*
1041 * Get an incoming message as initiator.
1042 *
1043 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a
1044 * byte in the FIFO
1045 */
1046 void
1047 ncr53c9x_msgin(sc)
1048 struct ncr53c9x_softc *sc;
1049 {
1050 int v;
1051
1052 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen));
1053
1054 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) {
1055 printf("%s: msgin: no msg byte available\n",
1056 sc->sc_dev.dv_xname);
1057 return;
1058 }
1059
1060 /*
1061 * Prepare for a new message. A message should (according
1062 * to the SCSI standard) be transmitted in one single
1063 * MESSAGE_IN_PHASE. If we have been in some other phase,
1064 * then this is a new message.
1065 */
1066 if (sc->sc_prevphase != MESSAGE_IN_PHASE) {
1067 sc->sc_flags &= ~NCR_DROP_MSGI;
1068 sc->sc_imlen = 0;
1069 }
1070
1071 v = NCR_READ_REG(sc, NCR_FIFO);
1072 NCR_MISC(("<msgbyte:0x%02x>", v));
1073
1074 #if 0
1075 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) {
1076 /*
1077 * Which target is reselecting us? (The ID bit really)
1078 */
1079 sc->sc_selid = v;
1080 NCR_MISC(("selid=0x%2x ", sc->sc_selid));
1081 return;
1082 }
1083 #endif
1084
1085 sc->sc_imess[sc->sc_imlen] = v;
1086
1087 /*
1088 * If we're going to reject the message, don't bother storing
1089 * the incoming bytes. But still, we need to ACK them.
1090 */
1091
1092 if ((sc->sc_flags & NCR_DROP_MSGI)) {
1093 NCRCMD(sc, NCRCMD_MSGOK);
1094 printf("<dropping msg byte %x>",
1095 sc->sc_imess[sc->sc_imlen]);
1096 return;
1097 }
1098
1099 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) {
1100 ncr53c9x_sched_msgout(SEND_REJECT);
1101 sc->sc_flags |= NCR_DROP_MSGI;
1102 } else {
1103 sc->sc_imlen++;
1104 /*
1105 * This testing is suboptimal, but most
1106 * messages will be of the one byte variety, so
1107 * it should not effect performance
1108 * significantly.
1109 */
1110 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0]))
1111 goto gotit;
1112 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0]))
1113 goto gotit;
1114 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) &&
1115 sc->sc_imlen == sc->sc_imess[1] + 2)
1116 goto gotit;
1117 }
1118 /* Ack what we have so far */
1119 NCRCMD(sc, NCRCMD_MSGOK);
1120 return;
1121
1122 gotit:
1123 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0]));
1124 /*
1125 * Now we should have a complete message (1 byte, 2 byte
1126 * and moderately long extended messages). We only handle
1127 * extended messages which total length is shorter than
1128 * NCR_MAX_MSG_LEN. Longer messages will be amputated.
1129 */
1130 switch (sc->sc_state) {
1131 struct ncr53c9x_ecb *ecb;
1132 struct ncr53c9x_tinfo *ti;
1133
1134 case NCR_CONNECTED:
1135 ecb = sc->sc_nexus;
1136 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
1137
1138 switch (sc->sc_imess[0]) {
1139 case MSG_CMDCOMPLETE:
1140 NCR_MSGS(("cmdcomplete "));
1141 if (sc->sc_dleft < 0) {
1142 scsi_print_addr(ecb->xs->sc_link);
1143 printf("got %ld extra bytes\n",
1144 -(long)sc->sc_dleft);
1145 sc->sc_dleft = 0;
1146 }
1147 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE)
1148 ? 0
1149 : sc->sc_dleft;
1150 if ((ecb->flags & ECB_SENSE) == 0)
1151 ecb->xs->resid = ecb->dleft;
1152 sc->sc_state = NCR_CMDCOMPLETE;
1153 break;
1154
1155 case MSG_MESSAGE_REJECT:
1156 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout));
1157 switch (sc->sc_msgout) {
1158 case SEND_SDTR:
1159 sc->sc_flags &= ~NCR_SYNCHNEGO;
1160 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE);
1161 ncr53c9x_setsync(sc, ti);
1162 break;
1163 case SEND_INIT_DET_ERR:
1164 goto abort;
1165 }
1166 break;
1167
1168 case MSG_NOOP:
1169 NCR_MSGS(("noop "));
1170 break;
1171
1172 case MSG_DISCONNECT:
1173 NCR_MSGS(("disconnect "));
1174 ti->dconns++;
1175 sc->sc_state = NCR_DISCONNECT;
1176
1177 /*
1178 * Mark the fact that all bytes have moved. The
1179 * target may not bother to do a SAVE POINTERS
1180 * at this stage. This flag will set the residual
1181 * count to zero on MSG COMPLETE.
1182 */
1183 if (sc->sc_dleft == 0)
1184 ecb->flags |= ECB_TENTATIVE_DONE;
1185
1186 break;
1187
1188 case MSG_SAVEDATAPOINTER:
1189 NCR_MSGS(("save datapointer "));
1190 ecb->daddr = sc->sc_dp;
1191 ecb->dleft = sc->sc_dleft;
1192 break;
1193
1194 case MSG_RESTOREPOINTERS:
1195 NCR_MSGS(("restore datapointer "));
1196 sc->sc_dp = ecb->daddr;
1197 sc->sc_dleft = ecb->dleft;
1198 break;
1199
1200 case MSG_EXTENDED:
1201 NCR_MSGS(("extended(%x) ", sc->sc_imess[2]));
1202 switch (sc->sc_imess[2]) {
1203 case MSG_EXT_SDTR:
1204 NCR_MSGS(("SDTR period %d, offset %d ",
1205 sc->sc_imess[3], sc->sc_imess[4]));
1206 if (sc->sc_imess[1] != 3)
1207 goto reject;
1208 ti->period = sc->sc_imess[3];
1209 ti->offset = sc->sc_imess[4];
1210 ti->flags &= ~T_NEGOTIATE;
1211 if (sc->sc_minsync == 0 ||
1212 ti->offset == 0 ||
1213 ti->period > 124) {
1214 #ifdef NCR53C9X_DEBUG
1215 scsi_print_addr(ecb->xs->sc_link);
1216 printf("async mode\n");
1217 #endif
1218 if ((sc->sc_flags&NCR_SYNCHNEGO)
1219 == 0) {
1220 /*
1221 * target initiated negotiation
1222 */
1223 ti->offset = 0;
1224 ti->flags &= ~T_SYNCMODE;
1225 ncr53c9x_sched_msgout(
1226 SEND_SDTR);
1227 } else {
1228 /* we are async */
1229 ti->flags &= ~T_SYNCMODE;
1230 }
1231 } else {
1232 int r = 250/ti->period;
1233 int s = (100*250)/ti->period - 100*r;
1234 int p;
1235
1236 p = ncr53c9x_stp2cpb(sc, ti->period);
1237 ti->period = ncr53c9x_cpb2stp(sc, p);
1238 #ifdef NCR53C9X_DEBUG
1239 scsi_print_addr(ecb->xs->sc_link);
1240 printf("max sync rate %d.%02dMB/s\n",
1241 r, s);
1242 #endif
1243 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) {
1244 /*
1245 * target initiated negotiation
1246 */
1247 if (ti->period <
1248 sc->sc_minsync)
1249 ti->period =
1250 sc->sc_minsync;
1251 if (ti->offset > 15)
1252 ti->offset = 15;
1253 ti->flags &= ~T_SYNCMODE;
1254 ncr53c9x_sched_msgout(
1255 SEND_SDTR);
1256 } else {
1257 /* we are sync */
1258 ti->flags |= T_SYNCMODE;
1259 }
1260 }
1261 sc->sc_flags &= ~NCR_SYNCHNEGO;
1262 ncr53c9x_setsync(sc, ti);
1263 break;
1264
1265 default:
1266 scsi_print_addr(ecb->xs->sc_link);
1267 printf("unrecognized MESSAGE EXTENDED;"
1268 " sending REJECT\n");
1269 goto reject;
1270 }
1271 break;
1272
1273 default:
1274 NCR_MSGS(("ident "));
1275 scsi_print_addr(ecb->xs->sc_link);
1276 printf("unrecognized MESSAGE; sending REJECT\n");
1277 reject:
1278 ncr53c9x_sched_msgout(SEND_REJECT);
1279 break;
1280 }
1281 break;
1282
1283 case NCR_RESELECTED:
1284 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) {
1285 printf("%s: reselect without IDENTIFY;"
1286 " sending DEVICE RESET\n",
1287 sc->sc_dev.dv_xname);
1288 goto reset;
1289 }
1290
1291 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]);
1292 break;
1293
1294 default:
1295 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n",
1296 sc->sc_dev.dv_xname);
1297 reset:
1298 ncr53c9x_sched_msgout(SEND_DEV_RESET);
1299 break;
1300
1301 abort:
1302 ncr53c9x_sched_msgout(SEND_ABORT);
1303 break;
1304 }
1305
1306 /* Ack last message byte */
1307 NCRCMD(sc, NCRCMD_MSGOK);
1308
1309 /* Done, reset message pointer. */
1310 sc->sc_flags &= ~NCR_DROP_MSGI;
1311 sc->sc_imlen = 0;
1312 }
1313
1314
1315 /*
1316 * Send the highest priority, scheduled message
1317 */
1318 void
1319 ncr53c9x_msgout(sc)
1320 struct ncr53c9x_softc *sc;
1321 {
1322 struct ncr53c9x_tinfo *ti;
1323 struct ncr53c9x_ecb *ecb;
1324 size_t size;
1325
1326 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]",
1327 sc->sc_msgpriq, sc->sc_prevphase));
1328
1329 /*
1330 * XXX - the NCR_ATN flag is not in sync with the actual ATN
1331 * condition on the SCSI bus. The 53c9x chip
1332 * automatically turns off ATN before sending the
1333 * message byte. (see also the comment below in the
1334 * default case when picking out a message to send)
1335 */
1336 if (sc->sc_flags & NCR_ATN) {
1337 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) {
1338 new:
1339 NCRCMD(sc, NCRCMD_FLUSH);
1340 DELAY(1);
1341 sc->sc_msgoutq = 0;
1342 sc->sc_omlen = 0;
1343 }
1344 } else {
1345 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
1346 ncr53c9x_sched_msgout(sc->sc_msgoutq);
1347 goto new;
1348 } else {
1349 printf("%s at line %d: unexpected MESSAGE OUT phase\n",
1350 sc->sc_dev.dv_xname, __LINE__);
1351 }
1352 }
1353
1354 if (sc->sc_omlen == 0) {
1355 /* Pick up highest priority message */
1356 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq;
1357 sc->sc_msgoutq |= sc->sc_msgout;
1358 sc->sc_msgpriq &= ~sc->sc_msgout;
1359 sc->sc_omlen = 1; /* "Default" message len */
1360 switch (sc->sc_msgout) {
1361 case SEND_SDTR:
1362 ecb = sc->sc_nexus;
1363 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
1364 sc->sc_omess[0] = MSG_EXTENDED;
1365 sc->sc_omess[1] = 3;
1366 sc->sc_omess[2] = MSG_EXT_SDTR;
1367 sc->sc_omess[3] = ti->period;
1368 sc->sc_omess[4] = ti->offset;
1369 sc->sc_omlen = 5;
1370 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) {
1371 ti->flags |= T_SYNCMODE;
1372 ncr53c9x_setsync(sc, ti);
1373 }
1374 break;
1375 case SEND_IDENTIFY:
1376 if (sc->sc_state != NCR_CONNECTED) {
1377 printf("%s at line %d: no nexus\n",
1378 sc->sc_dev.dv_xname, __LINE__);
1379 }
1380 ecb = sc->sc_nexus;
1381 sc->sc_omess[0] =
1382 MSG_IDENTIFY(ecb->xs->sc_link->scsipi_scsi.lun, 0);
1383 break;
1384 case SEND_DEV_RESET:
1385 sc->sc_flags |= NCR_ABORTING;
1386 sc->sc_omess[0] = MSG_BUS_DEV_RESET;
1387 ecb = sc->sc_nexus;
1388 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
1389 ti->flags &= ~T_SYNCMODE;
1390 ti->flags |= T_NEGOTIATE;
1391 break;
1392 case SEND_PARITY_ERROR:
1393 sc->sc_omess[0] = MSG_PARITY_ERROR;
1394 break;
1395 case SEND_ABORT:
1396 sc->sc_flags |= NCR_ABORTING;
1397 sc->sc_omess[0] = MSG_ABORT;
1398 break;
1399 case SEND_INIT_DET_ERR:
1400 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
1401 break;
1402 case SEND_REJECT:
1403 sc->sc_omess[0] = MSG_MESSAGE_REJECT;
1404 break;
1405 default:
1406 /*
1407 * We normally do not get here, since the chip
1408 * automatically turns off ATN before the last
1409 * byte of a message is sent to the target.
1410 * However, if the target rejects our (multi-byte)
1411 * message early by switching to MSG IN phase
1412 * ATN remains on, so the target may return to
1413 * MSG OUT phase. If there are no scheduled messages
1414 * left we send a NO-OP.
1415 *
1416 * XXX - Note that this leaves no useful purpose for
1417 * the NCR_ATN flag.
1418 */
1419 sc->sc_flags &= ~NCR_ATN;
1420 sc->sc_omess[0] = MSG_NOOP;
1421 break;
1422 }
1423 sc->sc_omp = sc->sc_omess;
1424 }
1425
1426 /* (re)send the message */
1427 size = min(sc->sc_omlen, sc->sc_maxxfer);
1428 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size);
1429 /* Program the SCSI counter */
1430 NCR_WRITE_REG(sc, NCR_TCL, size);
1431 NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
1432 if (sc->sc_cfg2 & NCRCFG2_FE) {
1433 NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
1434 }
1435 /* Load the count in and start the message-out transfer */
1436 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
1437 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA);
1438 NCRDMA_GO(sc);
1439 }
1440
1441 /*
1442 * This is the most critical part of the driver, and has to know
1443 * how to deal with *all* error conditions and phases from the SCSI
1444 * bus. If there are no errors and the DMA was active, then call the
1445 * DMA pseudo-interrupt handler. If this returns 1, then that was it
1446 * and we can return from here without further processing.
1447 *
1448 * Most of this needs verifying.
1449 */
1450 int sdebug = 0;
1451 int
1452 ncr53c9x_intr(arg)
1453 void *arg;
1454 {
1455 struct ncr53c9x_softc *sc = arg;
1456 struct ncr53c9x_ecb *ecb;
1457 struct scsipi_link *sc_link;
1458 struct ncr53c9x_tinfo *ti;
1459 size_t size;
1460 int nfifo;
1461
1462 NCR_TRACE(("[ncr53c9x_intr] "));
1463
1464 if (!NCRDMA_ISINTR(sc))
1465 return (0);
1466
1467 again:
1468 /* and what do the registers say... */
1469 ncr53c9x_readregs(sc);
1470
1471 sc->sc_intrcnt.ev_count++;
1472
1473 /*
1474 * At the moment, only a SCSI Bus Reset or Illegal
1475 * Command are classed as errors. A disconnect is a
1476 * valid condition, and we let the code check is the
1477 * "NCR_BUSFREE_OK" flag was set before declaring it
1478 * and error.
1479 *
1480 * Also, the status register tells us about "Gross
1481 * Errors" and "Parity errors". Only the Gross Error
1482 * is really bad, and the parity errors are dealt
1483 * with later
1484 *
1485 * TODO
1486 * If there are too many parity error, go to slow
1487 * cable mode ?
1488 */
1489
1490 /* SCSI Reset */
1491 if (sc->sc_espintr & NCRINTR_SBR) {
1492 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
1493 NCRCMD(sc, NCRCMD_FLUSH);
1494 DELAY(1);
1495 }
1496 if (sc->sc_state != NCR_SBR) {
1497 printf("%s: SCSI bus reset\n",
1498 sc->sc_dev.dv_xname);
1499 ncr53c9x_init(sc, 0); /* Restart everything */
1500 return (1);
1501 }
1502 #if 0
1503 /*XXX*/ printf("<expected bus reset: "
1504 "[intr %x, stat %x, step %d]>\n",
1505 sc->sc_espintr, sc->sc_espstat,
1506 sc->sc_espstep);
1507 #endif
1508 if (sc->sc_nexus)
1509 panic("%s: nexus in reset state",
1510 sc->sc_dev.dv_xname);
1511 goto sched;
1512 }
1513
1514 ecb = sc->sc_nexus;
1515
1516 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL)
1517 if (sc->sc_espintr & NCRINTR_ERR ||
1518 sc->sc_espstat & NCRSTAT_GE) {
1519
1520 if (sc->sc_espstat & NCRSTAT_GE) {
1521 /* Gross Error; no target ? */
1522 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
1523 NCRCMD(sc, NCRCMD_FLUSH);
1524 DELAY(1);
1525 }
1526 if (sc->sc_state == NCR_CONNECTED ||
1527 sc->sc_state == NCR_SELECTING) {
1528 ecb->xs->error = XS_TIMEOUT;
1529 ncr53c9x_done(sc, ecb);
1530 }
1531 return (1);
1532 }
1533
1534 if (sc->sc_espintr & NCRINTR_ILL) {
1535 if (sc->sc_flags & NCR_EXPECT_ILLCMD) {
1536 /*
1537 * Eat away "Illegal command" interrupt
1538 * on a ESP100 caused by a re-selection
1539 * while we were trying to select
1540 * another target.
1541 */
1542 #ifdef DEBUG
1543 printf("%s: ESP100 work-around activated\n",
1544 sc->sc_dev.dv_xname);
1545 #endif
1546 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
1547 return (1);
1548 }
1549 /* illegal command, out of sync ? */
1550 printf("%s: illegal command: 0x%x "
1551 "(state %d, phase %x, prevphase %x)\n",
1552 sc->sc_dev.dv_xname, sc->sc_lastcmd,
1553 sc->sc_state, sc->sc_phase,
1554 sc->sc_prevphase);
1555 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
1556 NCRCMD(sc, NCRCMD_FLUSH);
1557 DELAY(1);
1558 }
1559 ncr53c9x_init(sc, 1); /* Restart everything */
1560 return (1);
1561 }
1562 }
1563 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
1564
1565 /*
1566 * Call if DMA is active.
1567 *
1568 * If DMA_INTR returns true, then maybe go 'round the loop
1569 * again in case there is no more DMA queued, but a phase
1570 * change is expected.
1571 */
1572 if (NCRDMA_ISACTIVE(sc)) {
1573 int r = NCRDMA_INTR(sc);
1574 if (r == -1) {
1575 printf("%s: DMA error; resetting\n",
1576 sc->sc_dev.dv_xname);
1577 ncr53c9x_init(sc, 1);
1578 }
1579 /* If DMA active here, then go back to work... */
1580 if (NCRDMA_ISACTIVE(sc))
1581 return (1);
1582
1583 if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
1584 /*
1585 * DMA not completed. If we can not find a
1586 * acceptable explanation, print a diagnostic.
1587 */
1588 if (sc->sc_state == NCR_SELECTING)
1589 /*
1590 * This can happen if we are reselected
1591 * while using DMA to select a target.
1592 */
1593 /*void*/;
1594 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
1595 /*
1596 * Our (multi-byte) message (eg SDTR) was
1597 * interrupted by the target to send
1598 * a MSG REJECT.
1599 * Print diagnostic if current phase
1600 * is not MESSAGE IN.
1601 */
1602 if (sc->sc_phase != MESSAGE_IN_PHASE)
1603 printf("%s: !TC on MSG OUT"
1604 " [intr %x, stat %x, step %d]"
1605 " prevphase %x, resid %lx\n",
1606 sc->sc_dev.dv_xname,
1607 sc->sc_espintr,
1608 sc->sc_espstat,
1609 sc->sc_espstep,
1610 sc->sc_prevphase,
1611 (u_long)sc->sc_omlen);
1612 } else if (sc->sc_dleft == 0) {
1613 /*
1614 * The DMA operation was started for
1615 * a DATA transfer. Print a diagnostic
1616 * if the DMA counter and TC bit
1617 * appear to be out of sync.
1618 */
1619 printf("%s: !TC on DATA XFER"
1620 " [intr %x, stat %x, step %d]"
1621 " prevphase %x, resid %x\n",
1622 sc->sc_dev.dv_xname,
1623 sc->sc_espintr,
1624 sc->sc_espstat,
1625 sc->sc_espstep,
1626 sc->sc_prevphase,
1627 ecb?ecb->dleft:-1);
1628 }
1629 }
1630 }
1631
1632 /*
1633 * Check for less serious errors.
1634 */
1635 if (sc->sc_espstat & NCRSTAT_PE) {
1636 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname);
1637 if (sc->sc_prevphase == MESSAGE_IN_PHASE)
1638 ncr53c9x_sched_msgout(SEND_PARITY_ERROR);
1639 else
1640 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR);
1641 }
1642
1643 if (sc->sc_espintr & NCRINTR_DIS) {
1644 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>",
1645 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep));
1646 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
1647 NCRCMD(sc, NCRCMD_FLUSH);
1648 DELAY(1);
1649 }
1650 /*
1651 * This command must (apparently) be issued within
1652 * 250mS of a disconnect. So here you are...
1653 */
1654 NCRCMD(sc, NCRCMD_ENSEL);
1655
1656 switch (sc->sc_state) {
1657 case NCR_RESELECTED:
1658 goto sched;
1659
1660 case NCR_SELECTING:
1661 ecb->xs->error = XS_SELTIMEOUT;
1662 goto finish;
1663
1664 case NCR_CONNECTED:
1665 if ((sc->sc_flags & NCR_SYNCHNEGO)) {
1666 #ifdef NCR53C9X_DEBUG
1667 if (ecb)
1668 scsi_print_addr(ecb->xs->sc_link);
1669 printf("sync nego not completed!\n");
1670 #endif
1671 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target];
1672 sc->sc_flags &= ~NCR_SYNCHNEGO;
1673 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE);
1674 }
1675
1676 /* it may be OK to disconnect */
1677 if ((sc->sc_flags & NCR_ABORTING) == 0) {
1678 /*
1679 * Section 5.1.1 of the SCSI 2 spec
1680 * suggests issuing a REQUEST SENSE
1681 * following an unexpected disconnect.
1682 * Some devices go into a contingent
1683 * allegiance condition when
1684 * disconnecting, and this is necessary
1685 * to clean up their state.
1686 */
1687 printf("%s: unexpected disconnect; ",
1688 sc->sc_dev.dv_xname);
1689 if (ecb->flags & ECB_SENSE) {
1690 printf("resetting\n");
1691 goto reset;
1692 }
1693 printf("sending REQUEST SENSE\n");
1694 callout_stop(&ecb->xs->xs_callout);
1695 ncr53c9x_sense(sc, ecb);
1696 goto out;
1697 }
1698
1699 ecb->xs->error = XS_TIMEOUT;
1700 goto finish;
1701
1702 case NCR_DISCONNECT:
1703 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain);
1704 sc->sc_nexus = NULL;
1705 goto sched;
1706
1707 case NCR_CMDCOMPLETE:
1708 goto finish;
1709 }
1710 }
1711
1712 switch (sc->sc_state) {
1713
1714 case NCR_SBR:
1715 printf("%s: waiting for SCSI Bus Reset to happen\n",
1716 sc->sc_dev.dv_xname);
1717 return (1);
1718
1719 case NCR_RESELECTED:
1720 /*
1721 * we must be continuing a message ?
1722 */
1723 if (sc->sc_phase != MESSAGE_IN_PHASE) {
1724 printf("%s: target didn't identify\n",
1725 sc->sc_dev.dv_xname);
1726 ncr53c9x_init(sc, 1);
1727 return (1);
1728 }
1729 printf("<<RESELECT CONT'd>>");
1730 #if XXXX
1731 ncr53c9x_msgin(sc);
1732 if (sc->sc_state != NCR_CONNECTED) {
1733 /* IDENTIFY fail?! */
1734 printf("%s: identify failed\n",
1735 sc->sc_dev.dv_xname);
1736 ncr53c9x_init(sc, 1);
1737 return (1);
1738 }
1739 #endif
1740 break;
1741
1742 case NCR_IDLE:
1743 case NCR_SELECTING:
1744 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
1745 sc->sc_flags = 0;
1746 ecb = sc->sc_nexus;
1747 if (ecb != NULL && (ecb->flags & ECB_NEXUS)) {
1748 scsi_print_addr(ecb->xs->sc_link);
1749 printf("ECB_NEXUS while in state %x\n", sc->sc_state);
1750 }
1751
1752 if (sc->sc_espintr & NCRINTR_RESEL) {
1753 /*
1754 * If we're trying to select a
1755 * target ourselves, push our command
1756 * back into the ready list.
1757 */
1758 if (sc->sc_state == NCR_SELECTING) {
1759 NCR_MISC(("backoff selector "));
1760 callout_stop(&ecb->xs->xs_callout);
1761 sc_link = ecb->xs->sc_link;
1762 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
1763 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
1764 ecb = sc->sc_nexus = NULL;
1765 }
1766 sc->sc_state = NCR_RESELECTED;
1767 if (sc->sc_phase != MESSAGE_IN_PHASE) {
1768 /*
1769 * Things are seriously fucked up.
1770 * Pull the brakes, i.e. reset
1771 */
1772 printf("%s: target didn't identify\n",
1773 sc->sc_dev.dv_xname);
1774 ncr53c9x_init(sc, 1);
1775 return (1);
1776 }
1777 /*
1778 * The C90 only inhibits FIFO writes until
1779 * reselection is complete, instead of
1780 * waiting until the interrupt status register
1781 * has been read. So, if the reselect happens
1782 * while we were entering a command bytes (for
1783 * another target) some of those bytes can
1784 * appear in the FIFO here, after the
1785 * interrupt is taken.
1786 */
1787 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF;
1788 if (nfifo < 2 ||
1789 (nfifo > 2 &&
1790 sc->sc_rev != NCR_VARIANT_ESP100)) {
1791 printf("%s: RESELECT: %d bytes in FIFO! "
1792 "[intr %x, stat %x, step %d, prevphase %x]\n",
1793 sc->sc_dev.dv_xname,
1794 nfifo,
1795 sc->sc_espintr,
1796 sc->sc_espstat,
1797 sc->sc_espstep,
1798 sc->sc_prevphase);
1799 ncr53c9x_init(sc, 1);
1800 return (1);
1801 }
1802 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO);
1803 NCR_MISC(("selid=0x%2x ", sc->sc_selid));
1804
1805 /* Handle identify message */
1806 ncr53c9x_msgin(sc);
1807 if (nfifo != 2) {
1808 /*
1809 * Note: this should not happen
1810 * with `dmaselect' on.
1811 */
1812 sc->sc_flags |= NCR_EXPECT_ILLCMD;
1813 NCRCMD(sc, NCRCMD_FLUSH);
1814 } else if (ncr53c9x_dmaselect &&
1815 sc->sc_rev == NCR_VARIANT_ESP100) {
1816 sc->sc_flags |= NCR_EXPECT_ILLCMD;
1817 }
1818
1819 if (sc->sc_state != NCR_CONNECTED) {
1820 /* IDENTIFY fail?! */
1821 printf("%s: identify failed\n",
1822 sc->sc_dev.dv_xname);
1823 ncr53c9x_init(sc, 1);
1824 return (1);
1825 }
1826 goto shortcut; /* ie. next phase expected soon */
1827 }
1828
1829 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS)
1830 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) {
1831 /*
1832 * Arbitration won; examine the `step' register
1833 * to determine how far the selection could progress.
1834 */
1835 ecb = sc->sc_nexus;
1836 if (!ecb)
1837 panic("ncr53c9x: no nexus");
1838
1839 sc_link = ecb->xs->sc_link;
1840 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
1841
1842 switch (sc->sc_espstep) {
1843 case 0:
1844 /*
1845 * The target did not respond with a
1846 * message out phase - probably an old
1847 * device that doesn't recognize ATN.
1848 * Clear ATN and just continue, the
1849 * target should be in the command
1850 * phase.
1851 * XXXX check for command phase?
1852 */
1853 NCRCMD(sc, NCRCMD_RSTATN);
1854 break;
1855 case 1:
1856 if ((ti->flags & T_NEGOTIATE) == 0) {
1857 printf("%s: step 1 & !NEG\n",
1858 sc->sc_dev.dv_xname);
1859 goto reset;
1860 }
1861 if (sc->sc_phase != MESSAGE_OUT_PHASE) {
1862 printf("%s: !MSGOUT\n",
1863 sc->sc_dev.dv_xname);
1864 goto reset;
1865 }
1866 /* Start negotiating */
1867 ti->period = sc->sc_minsync;
1868 ti->offset = 15;
1869 sc->sc_flags |= NCR_SYNCHNEGO;
1870 ncr53c9x_sched_msgout(SEND_SDTR);
1871 break;
1872 case 3:
1873 /*
1874 * Grr, this is supposed to mean
1875 * "target left command phase prematurely".
1876 * It seems to happen regularly when
1877 * sync mode is on.
1878 * Look at FIFO to see if command went out.
1879 * (Timing problems?)
1880 */
1881 if (ncr53c9x_dmaselect) {
1882 if (sc->sc_cmdlen == 0)
1883 /* Hope for the best.. */
1884 break;
1885 } else if ((NCR_READ_REG(sc, NCR_FFLAG)
1886 & NCRFIFO_FF) == 0) {
1887 /* Hope for the best.. */
1888 break;
1889 }
1890 printf("(%s:%d:%d): selection failed;"
1891 " %d left in FIFO "
1892 "[intr %x, stat %x, step %d]\n",
1893 sc->sc_dev.dv_xname,
1894 sc_link->scsipi_scsi.target,
1895 sc_link->scsipi_scsi.lun,
1896 NCR_READ_REG(sc, NCR_FFLAG)
1897 & NCRFIFO_FF,
1898 sc->sc_espintr, sc->sc_espstat,
1899 sc->sc_espstep);
1900 NCRCMD(sc, NCRCMD_FLUSH);
1901 ncr53c9x_sched_msgout(SEND_ABORT);
1902 return (1);
1903 case 2:
1904 /* Select stuck at Command Phase */
1905 NCRCMD(sc, NCRCMD_FLUSH);
1906 break;
1907 case 4:
1908 if (ncr53c9x_dmaselect &&
1909 sc->sc_cmdlen != 0)
1910 printf("(%s:%d:%d): select; "
1911 "%lu left in DMA buffer "
1912 "[intr %x, stat %x, step %d]\n",
1913 sc->sc_dev.dv_xname,
1914 sc_link->scsipi_scsi.target,
1915 sc_link->scsipi_scsi.lun,
1916 (u_long)sc->sc_cmdlen,
1917 sc->sc_espintr,
1918 sc->sc_espstat,
1919 sc->sc_espstep);
1920 /* So far, everything went fine */
1921 break;
1922 }
1923
1924 ecb->flags |= ECB_NEXUS;
1925 ti->lubusy |= (1 << sc_link->scsipi_scsi.lun);
1926
1927 sc->sc_prevphase = INVALID_PHASE; /* ?? */
1928 /* Do an implicit RESTORE POINTERS. */
1929 sc->sc_dp = ecb->daddr;
1930 sc->sc_dleft = ecb->dleft;
1931 sc->sc_state = NCR_CONNECTED;
1932 break;
1933
1934 } else {
1935
1936 printf("%s: unexpected status after select"
1937 ": [intr %x, stat %x, step %x]\n",
1938 sc->sc_dev.dv_xname,
1939 sc->sc_espintr, sc->sc_espstat,
1940 sc->sc_espstep);
1941 NCRCMD(sc, NCRCMD_FLUSH);
1942 DELAY(1);
1943 goto reset;
1944 }
1945 if (sc->sc_state == NCR_IDLE) {
1946 printf("%s: stray interrupt\n",
1947 sc->sc_dev.dv_xname);
1948 return (0);
1949 }
1950 break;
1951
1952 case NCR_CONNECTED:
1953 if (sc->sc_flags & NCR_ICCS) {
1954 /* "Initiate Command Complete Steps" in progress */
1955 u_char msg;
1956
1957 sc->sc_flags &= ~NCR_ICCS;
1958
1959 if (!(sc->sc_espintr & NCRINTR_DONE)) {
1960 printf("%s: ICCS: "
1961 ": [intr %x, stat %x, step %x]\n",
1962 sc->sc_dev.dv_xname,
1963 sc->sc_espintr, sc->sc_espstat,
1964 sc->sc_espstep);
1965 }
1966 if ((NCR_READ_REG(sc, NCR_FFLAG)
1967 & NCRFIFO_FF) != 2) {
1968 /* Drop excess bytes from the queue */
1969 int i = (NCR_READ_REG(sc, NCR_FFLAG)
1970 & NCRFIFO_FF) - 2;
1971 while (i-- > 0)
1972 (void) NCR_READ_REG(sc, NCR_FIFO);
1973 }
1974 ecb->stat = NCR_READ_REG(sc, NCR_FIFO);
1975 msg = NCR_READ_REG(sc, NCR_FIFO);
1976 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg));
1977 if (msg == MSG_CMDCOMPLETE) {
1978 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE)
1979 ? 0
1980 : sc->sc_dleft;
1981 if ((ecb->flags & ECB_SENSE) == 0)
1982 ecb->xs->resid = ecb->dleft;
1983 sc->sc_state = NCR_CMDCOMPLETE;
1984 } else
1985 printf("%s: STATUS_PHASE: msg %d\n",
1986 sc->sc_dev.dv_xname, msg);
1987 NCRCMD(sc, NCRCMD_MSGOK);
1988 goto shortcut; /* ie. wait for disconnect */
1989 }
1990 break;
1991 default:
1992 panic("%s: invalid state: %d",
1993 sc->sc_dev.dv_xname,
1994 sc->sc_state);
1995 }
1996
1997 /*
1998 * Driver is now in state NCR_CONNECTED, i.e. we
1999 * have a current command working the SCSI bus.
2000 */
2001 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) {
2002 panic("ncr53c9x: no nexus");
2003 }
2004
2005 switch (sc->sc_phase) {
2006 case MESSAGE_OUT_PHASE:
2007 NCR_PHASE(("MESSAGE_OUT_PHASE "));
2008 ncr53c9x_msgout(sc);
2009 sc->sc_prevphase = MESSAGE_OUT_PHASE;
2010 break;
2011 case MESSAGE_IN_PHASE:
2012 NCR_PHASE(("MESSAGE_IN_PHASE "));
2013 sc->sc_prevphase = MESSAGE_IN_PHASE;
2014 if (sc->sc_espintr & NCRINTR_BS) {
2015 NCRCMD(sc, NCRCMD_FLUSH);
2016 sc->sc_flags |= NCR_WAITI;
2017 NCRCMD(sc, NCRCMD_TRANS);
2018 } else if (sc->sc_espintr & NCRINTR_FC) {
2019 if ((sc->sc_flags & NCR_WAITI) == 0) {
2020 printf("%s: MSGIN: unexpected FC bit: "
2021 "[intr %x, stat %x, step %x]\n",
2022 sc->sc_dev.dv_xname,
2023 sc->sc_espintr, sc->sc_espstat,
2024 sc->sc_espstep);
2025 }
2026 sc->sc_flags &= ~NCR_WAITI;
2027 ncr53c9x_msgin(sc);
2028 } else {
2029 printf("%s: MSGIN: weird bits: "
2030 "[intr %x, stat %x, step %x]\n",
2031 sc->sc_dev.dv_xname,
2032 sc->sc_espintr, sc->sc_espstat,
2033 sc->sc_espstep);
2034 }
2035 goto shortcut; /* i.e. expect data to be ready */
2036 break;
2037 case COMMAND_PHASE:
2038 /*
2039 * Send the command block. Normally we don't see this
2040 * phase because the SEL_ATN command takes care of
2041 * all this. However, we end up here if either the
2042 * target or we wanted to exchange some more messages
2043 * first (e.g. to start negotiations).
2044 */
2045
2046 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ",
2047 ecb->cmd.cmd.opcode, ecb->clen));
2048 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
2049 NCRCMD(sc, NCRCMD_FLUSH);
2050 DELAY(1);
2051 }
2052 if (ncr53c9x_dmaselect) {
2053 size_t size;
2054 /* setup DMA transfer for command */
2055 size = ecb->clen;
2056 sc->sc_cmdlen = size;
2057 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd;
2058 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen,
2059 0, &size);
2060 /* Program the SCSI counter */
2061 NCR_WRITE_REG(sc, NCR_TCL, size);
2062 NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
2063 if (sc->sc_cfg2 & NCRCFG2_FE) {
2064 NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
2065 }
2066
2067 /* load the count in */
2068 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
2069
2070 /* start the command transfer */
2071 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
2072 NCRDMA_GO(sc);
2073 } else {
2074 u_char *cmd = (u_char *)&ecb->cmd.cmd;
2075 int i;
2076 /* Now the command into the FIFO */
2077 for (i = 0; i < ecb->clen; i++)
2078 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++);
2079 NCRCMD(sc, NCRCMD_TRANS);
2080 }
2081 sc->sc_prevphase = COMMAND_PHASE;
2082 break;
2083 case DATA_OUT_PHASE:
2084 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft));
2085 NCRCMD(sc, NCRCMD_FLUSH);
2086 size = min(sc->sc_dleft, sc->sc_maxxfer);
2087 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft,
2088 0, &size);
2089 sc->sc_prevphase = DATA_OUT_PHASE;
2090 goto setup_xfer;
2091 case DATA_IN_PHASE:
2092 NCR_PHASE(("DATA_IN_PHASE "));
2093 if (sc->sc_rev == NCR_VARIANT_ESP100)
2094 NCRCMD(sc, NCRCMD_FLUSH);
2095 size = min(sc->sc_dleft, sc->sc_maxxfer);
2096 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft,
2097 1, &size);
2098 sc->sc_prevphase = DATA_IN_PHASE;
2099 setup_xfer:
2100 /* Target returned to data phase: wipe "done" memory */
2101 ecb->flags &= ~ECB_TENTATIVE_DONE;
2102
2103 /* Program the SCSI counter */
2104 NCR_WRITE_REG(sc, NCR_TCL, size);
2105 NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
2106 if (sc->sc_cfg2 & NCRCFG2_FE) {
2107 NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
2108 }
2109 /* load the count in */
2110 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
2111
2112 /*
2113 * Note that if `size' is 0, we've already transceived
2114 * all the bytes we want but we're still in DATA PHASE.
2115 * Apparently, the device needs padding. Also, a
2116 * transfer size of 0 means "maximum" to the chip
2117 * DMA logic.
2118 */
2119 NCRCMD(sc,
2120 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA);
2121 NCRDMA_GO(sc);
2122 return (1);
2123 case STATUS_PHASE:
2124 NCR_PHASE(("STATUS_PHASE "));
2125 sc->sc_flags |= NCR_ICCS;
2126 NCRCMD(sc, NCRCMD_ICCS);
2127 sc->sc_prevphase = STATUS_PHASE;
2128 goto shortcut; /* i.e. expect status results soon */
2129 break;
2130 case INVALID_PHASE:
2131 break;
2132 default:
2133 printf("%s: unexpected bus phase; resetting\n",
2134 sc->sc_dev.dv_xname);
2135 goto reset;
2136 }
2137
2138 out:
2139 return (1);
2140
2141 reset:
2142 ncr53c9x_init(sc, 1);
2143 goto out;
2144
2145 finish:
2146 ncr53c9x_done(sc, ecb);
2147 goto out;
2148
2149 sched:
2150 sc->sc_state = NCR_IDLE;
2151 ncr53c9x_sched(sc);
2152 goto out;
2153
2154 shortcut:
2155 /*
2156 * The idea is that many of the SCSI operations take very little
2157 * time, and going away and getting interrupted is too high an
2158 * overhead to pay. For example, selecting, sending a message
2159 * and command and then doing some work can be done in one "pass".
2160 *
2161 * The delay is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1
2162 * at 40Mhz. This needs testing.
2163 */
2164 DELAY(50/sc->sc_freq);
2165 if (NCRDMA_ISINTR(sc))
2166 goto again;
2167 goto out;
2168 }
2169
2170 void
2171 ncr53c9x_abort(sc, ecb)
2172 struct ncr53c9x_softc *sc;
2173 struct ncr53c9x_ecb *ecb;
2174 {
2175
2176 /* 2 secs for the abort */
2177 ecb->timeout = NCR_ABORT_TIMEOUT;
2178 ecb->flags |= ECB_ABORT;
2179
2180 if (ecb == sc->sc_nexus) {
2181 /*
2182 * If we're still selecting, the message will be scheduled
2183 * after selection is complete.
2184 */
2185 if (sc->sc_state == NCR_CONNECTED)
2186 ncr53c9x_sched_msgout(SEND_ABORT);
2187
2188 /*
2189 * Reschedule timeout.
2190 */
2191 callout_reset(&ecb->xs->xs_callout, (ecb->timeout * hz) / 1000,
2192 ncr53c9x_timeout, ecb);
2193 } else {
2194 /* The command should be on the nexus list */
2195 if ((ecb->flags & ECB_NEXUS) == 0) {
2196 scsi_print_addr(ecb->xs->sc_link);
2197 printf("ncr53c9x_abort: not NEXUS\n");
2198 ncr53c9x_init(sc, 1);
2199 }
2200 /*
2201 * Just leave the command on the nexus list.
2202 * XXX - what choice do we have but to reset the SCSI
2203 * eventually?
2204 */
2205 if (sc->sc_state == NCR_IDLE)
2206 ncr53c9x_sched(sc);
2207 }
2208 }
2209
2210 void
2211 ncr53c9x_timeout(arg)
2212 void *arg;
2213 {
2214 struct ncr53c9x_ecb *ecb = arg;
2215 struct scsipi_xfer *xs = ecb->xs;
2216 struct scsipi_link *sc_link = xs->sc_link;
2217 struct ncr53c9x_softc *sc = sc_link->adapter_softc;
2218 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target];
2219 int s;
2220
2221 scsi_print_addr(sc_link);
2222 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], "
2223 "<state %d, nexus %p, phase(l %x, c %x, p %x), resid %lx, "
2224 "msg(q %x,o %x) %s>",
2225 sc->sc_dev.dv_xname,
2226 ecb, ecb->flags, ecb->dleft, ecb->stat,
2227 sc->sc_state, sc->sc_nexus,
2228 NCR_READ_REG(sc, NCR_STAT),
2229 sc->sc_phase, sc->sc_prevphase,
2230 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout,
2231 NCRDMA_ISACTIVE(sc) ? "DMA active" : "");
2232 #if NCR53C9X_DEBUG > 1
2233 printf("TRACE: %s.", ecb->trace);
2234 #endif
2235
2236 s = splbio();
2237
2238 if (ecb->flags & ECB_ABORT) {
2239 /* abort timed out */
2240 printf(" AGAIN\n");
2241
2242 ncr53c9x_init(sc, 1);
2243 } else {
2244 /* abort the operation that has timed out */
2245 printf("\n");
2246 xs->error = XS_TIMEOUT;
2247 ncr53c9x_abort(sc, ecb);
2248
2249 /* Disable sync mode if stuck in a data phase */
2250 if (ecb == sc->sc_nexus &&
2251 (ti->flags & T_SYNCMODE) != 0 &&
2252 (sc->sc_phase & (MSGI|CDI)) == 0) {
2253 scsi_print_addr(sc_link);
2254 printf("sync negotiation disabled\n");
2255 sc->sc_cfflags |= (1<<(sc_link->scsipi_scsi.target+8));
2256 }
2257 }
2258
2259 splx(s);
2260 }
2261