ncr53c9x.c revision 1.53
1 /* $NetBSD: ncr53c9x.c,v 1.53 2000/11/13 15:24:22 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1994 Peter Galbavy 41 * Copyright (c) 1995 Paul Kranenburg 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/kernel.h> 84 #include <sys/errno.h> 85 #include <sys/ioctl.h> 86 #include <sys/device.h> 87 #include <sys/buf.h> 88 #include <sys/malloc.h> 89 #include <sys/proc.h> 90 #include <sys/user.h> 91 #include <sys/queue.h> 92 #include <sys/scsiio.h> 93 94 #include <dev/scsipi/scsi_all.h> 95 #include <dev/scsipi/scsipi_all.h> 96 #include <dev/scsipi/scsiconf.h> 97 #include <dev/scsipi/scsi_message.h> 98 99 #include <machine/cpu.h> 100 101 #include <dev/ic/ncr53c9xreg.h> 102 #include <dev/ic/ncr53c9xvar.h> 103 104 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 105 106 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 107 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 108 struct ncr53c9x_ecb *)); 109 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 110 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 111 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 112 struct scsipi_xfer *, int)); 113 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 114 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 115 struct ncr53c9x_ecb *)); 116 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 117 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 118 /*static*/ void ncr53c9x_timeout __P((void *arg)); 119 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 120 struct ncr53c9x_ecb *)); 121 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 122 struct ncr53c9x_ecb *)); 123 /*static*/ int ncr53c9x_ioctl __P((struct scsipi_link *, u_long, 124 caddr_t, int, struct proc *)); 125 126 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 127 struct ncr53c9x_ecb *)); 128 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 129 struct ncr53c9x_ecb *, int)); 130 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 131 132 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 133 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 134 struct ncr53c9x_tinfo *)); 135 136 /* 137 * Names for the NCR53c9x variants, correspnding to the variant tags 138 * in ncr53c9xvar.h. 139 */ 140 static const char *ncr53c9x_variant_names[] = { 141 "ESP100", 142 "ESP100A", 143 "ESP200", 144 "NCR53C94", 145 "NCR53C96", 146 "ESP406", 147 "FAS408", 148 "FAS216", 149 "AM53C974", 150 }; 151 152 static struct scsipi_adapter ncr53c9x_adapter = { 153 0, /* adapter refcnt */ 154 ncr53c9x_scsi_cmd, /* cmd */ 155 minphys, /* minphys */ 156 ncr53c9x_ioctl, /* ioctl */ 157 NULL, /* enable */ 158 NULL, /* getgeom */ 159 }; 160 161 static struct scsipi_device ncr53c9x_device = { 162 NULL, /* use default error handler */ 163 NULL, /* have a queue, served by this */ 164 NULL, /* have no async handler */ 165 NULL, /* use default 'done' routine */ 166 }; 167 168 /* 169 * Attach this instance, and then all the sub-devices 170 */ 171 void 172 ncr53c9x_attach(sc, adapter, device) 173 struct ncr53c9x_softc *sc; 174 struct scsipi_adapter *adapter; 175 struct scsipi_device *device; 176 { 177 178 /* 179 * Allocate SCSI message buffers. 180 * Front-ends can override allocation to avoid alignment 181 * handling in the DMA engines. Note that that ncr53c9x_msgout() 182 * can request a 1 byte DMA transfer. 183 */ 184 if (sc->sc_omess == NULL) 185 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 186 187 if (sc->sc_imess == NULL) 188 sc->sc_imess = malloc(NCR_MAX_MSG_LEN+1, M_DEVBUF, M_NOWAIT); 189 190 if (sc->sc_omess == NULL || sc->sc_imess == NULL) { 191 printf("out of memory\n"); 192 return; 193 } 194 195 /* 196 * Note, the front-end has set us up to print the chip variation. 197 */ 198 if (sc->sc_rev >= NCR_VARIANT_MAX) { 199 printf("\n%s: unknown variant %d, devices not attached\n", 200 sc->sc_dev.dv_xname, sc->sc_rev); 201 return; 202 } 203 204 printf(": %s, %dMHz, SCSI ID %d\n", 205 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 206 207 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 208 209 /* The value *must not* be == 1. Make it 2 */ 210 if (sc->sc_ccf == 1) 211 sc->sc_ccf = 2; 212 213 /* 214 * The recommended timeout is 250ms. This register is loaded 215 * with a value calculated as follows, from the docs: 216 * 217 * (timout period) x (CLK frequency) 218 * reg = ------------------------------------- 219 * 8192 x (Clock Conversion Factor) 220 * 221 * Since CCF has a linear relation to CLK, this generally computes 222 * to the constant of 153. 223 */ 224 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 225 226 /* CCF register only has 3 bits; 0 is actually 8 */ 227 sc->sc_ccf &= 7; 228 229 /* 230 * fill in the prototype scsipi_link. 231 */ 232 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 233 sc->sc_link.adapter_softc = sc; 234 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 235 sc->sc_link.adapter = (adapter) ? adapter : &ncr53c9x_adapter; 236 sc->sc_link.device = (device) ? device : &ncr53c9x_device; 237 sc->sc_link.openings = 2; 238 sc->sc_link.scsipi_scsi.max_target = 7; 239 sc->sc_link.scsipi_scsi.max_lun = 7; 240 sc->sc_link.type = BUS_SCSI; 241 242 /* 243 * Add reference to adapter so that we drop the reference after 244 * config_found() to make sure the adatper is disabled. 245 */ 246 if (scsipi_adapter_addref(&sc->sc_link) != 0) { 247 printf("%s: unable to enable controller\n", 248 sc->sc_dev.dv_xname); 249 return; 250 } 251 252 /* Reset state & bus */ 253 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 254 sc->sc_state = 0; 255 ncr53c9x_init(sc, 1); 256 257 /* 258 * Now try to attach all the sub-devices 259 */ 260 sc->sc_child = config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 261 262 scsipi_adapter_delref(&sc->sc_link); 263 } 264 265 int 266 ncr53c9x_detach(sc, flags) 267 struct ncr53c9x_softc *sc; 268 int flags; 269 { 270 int error; 271 272 if (sc->sc_child) { 273 error = config_detach(sc->sc_child, flags); 274 if (error) 275 return (error); 276 } 277 278 free(sc->sc_imess, M_DEVBUF); 279 free(sc->sc_omess, M_DEVBUF); 280 281 return (0); 282 } 283 284 /* 285 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus, 286 * only this controller, but kills any on-going commands, and also stops 287 * and resets the DMA. 288 * 289 * After reset, registers are loaded with the defaults from the attach 290 * routine above. 291 */ 292 void 293 ncr53c9x_reset(sc) 294 struct ncr53c9x_softc *sc; 295 { 296 297 /* reset DMA first */ 298 NCRDMA_RESET(sc); 299 300 /* reset SCSI chip */ 301 NCRCMD(sc, NCRCMD_RSTCHIP); 302 NCRCMD(sc, NCRCMD_NOP); 303 DELAY(500); 304 305 /* do these backwards, and fall through */ 306 switch (sc->sc_rev) { 307 case NCR_VARIANT_ESP406: 308 case NCR_VARIANT_FAS408: 309 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT); 310 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4); 311 case NCR_VARIANT_AM53C974: 312 case NCR_VARIANT_FAS216: 313 case NCR_VARIANT_NCR53C94: 314 case NCR_VARIANT_NCR53C96: 315 case NCR_VARIANT_ESP200: 316 sc->sc_features |= NCR_F_HASCFG3; 317 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 318 case NCR_VARIANT_ESP100A: 319 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 320 case NCR_VARIANT_ESP100: 321 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 322 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 323 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 324 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 325 break; 326 default: 327 printf("%s: unknown revision code, assuming ESP100\n", 328 sc->sc_dev.dv_xname); 329 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 330 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 331 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 332 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 333 } 334 335 if (sc->sc_rev == NCR_VARIANT_AM53C974) 336 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4); 337 } 338 339 /* 340 * Reset the SCSI bus, but not the chip 341 */ 342 void 343 ncr53c9x_scsi_reset(sc) 344 struct ncr53c9x_softc *sc; 345 { 346 347 (*sc->sc_glue->gl_dma_stop)(sc); 348 349 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 350 NCRCMD(sc, NCRCMD_RSTSCSI); 351 } 352 353 /* 354 * Initialize ncr53c9x state machine 355 */ 356 void 357 ncr53c9x_init(sc, doreset) 358 struct ncr53c9x_softc *sc; 359 int doreset; 360 { 361 struct ncr53c9x_ecb *ecb; 362 int r; 363 364 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 365 366 if (sc->sc_state == 0) { 367 /* First time through; initialize. */ 368 TAILQ_INIT(&sc->ready_list); 369 TAILQ_INIT(&sc->nexus_list); 370 TAILQ_INIT(&sc->free_list); 371 sc->sc_nexus = NULL; 372 ecb = sc->sc_ecb; 373 bzero(ecb, sizeof(sc->sc_ecb)); 374 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 375 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 376 ecb++; 377 } 378 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 379 } else { 380 /* Cancel any active commands. */ 381 sc->sc_state = NCR_CLEANING; 382 if ((ecb = sc->sc_nexus) != NULL) { 383 ecb->xs->error = XS_TIMEOUT; 384 ncr53c9x_done(sc, ecb); 385 } 386 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 387 ecb->xs->error = XS_TIMEOUT; 388 ncr53c9x_done(sc, ecb); 389 } 390 } 391 392 /* 393 * reset the chip to a known state 394 */ 395 ncr53c9x_reset(sc); 396 397 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 398 for (r = 0; r < 8; r++) { 399 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 400 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 401 402 ti->flags = (((sc->sc_cfflags & (1<<(r+8))) != 0) 403 ? T_SYNCHOFF : 0) | 404 ((sc->sc_cfflags & (1<<r)) ? T_RSELECTOFF : 0) | 405 T_NEED_TO_RESET; 406 ti->period = sc->sc_minsync; 407 ti->offset = 0; 408 } 409 410 if (doreset) { 411 sc->sc_state = NCR_SBR; 412 NCRCMD(sc, NCRCMD_RSTSCSI); 413 } else { 414 sc->sc_state = NCR_IDLE; 415 ncr53c9x_sched(sc); 416 } 417 } 418 419 /* 420 * Read the NCR registers, and save their contents for later use. 421 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 422 * NCR_INTR - so make sure it is the last read. 423 * 424 * I think that (from reading the docs) most bits in these registers 425 * only make sense when he DMA CSR has an interrupt showing. Call only 426 * if an interrupt is pending. 427 */ 428 __inline__ void 429 ncr53c9x_readregs(sc) 430 struct ncr53c9x_softc *sc; 431 { 432 433 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 434 /* Only the stepo bits are of interest */ 435 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 436 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 437 438 if (sc->sc_glue->gl_clear_latched_intr != NULL) 439 (*sc->sc_glue->gl_clear_latched_intr)(sc); 440 441 /* 442 * Determine the SCSI bus phase, return either a real SCSI bus phase 443 * or some pseudo phase we use to detect certain exceptions. 444 */ 445 446 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 447 ? /* Disconnected */ BUSFREE_PHASE 448 : sc->sc_espstat & NCRSTAT_PHASE; 449 450 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 451 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 452 } 453 454 /* 455 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 456 */ 457 static inline int 458 ncr53c9x_stp2cpb(sc, period) 459 struct ncr53c9x_softc *sc; 460 int period; 461 { 462 int v; 463 v = (sc->sc_freq * period) / 250; 464 if (ncr53c9x_cpb2stp(sc, v) < period) 465 /* Correct round-down error */ 466 v++; 467 return (v); 468 } 469 470 static inline void 471 ncr53c9x_setsync(sc, ti) 472 struct ncr53c9x_softc *sc; 473 struct ncr53c9x_tinfo *ti; 474 { 475 u_char syncoff, synctp, cfg3 = sc->sc_cfg3; 476 477 if (ti->flags & T_SYNCMODE) { 478 syncoff = ti->offset; 479 synctp = ncr53c9x_stp2cpb(sc, ti->period); 480 if (sc->sc_features & NCR_F_FASTSCSI) { 481 /* 482 * If the period is 200ns or less (ti->period <= 50), 483 * put the chip in Fast SCSI mode. 484 */ 485 if (ti->period <= 50) 486 /* 487 * There are (at least) 4 variations of the 488 * configuration 3 register. The drive attach 489 * routine sets the appropriate bit to put the 490 * chip into Fast SCSI mode so that it doesn't 491 * have to be figured out here each time. 492 */ 493 cfg3 |= sc->sc_cfg3_fscsi; 494 } 495 496 /* 497 * Am53c974 requires different SYNCTP values when the 498 * FSCSI bit is off. 499 */ 500 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 501 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 502 synctp--; 503 } else { 504 syncoff = 0; 505 synctp = 0; 506 } 507 508 if (sc->sc_features & NCR_F_HASCFG3) 509 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 510 511 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 512 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 513 } 514 515 int ncr53c9x_dmaselect = 0; 516 /* 517 * Send a command to a target, set the driver state to NCR_SELECTING 518 * and let the caller take care of the rest. 519 * 520 * Keeping this as a function allows me to say that this may be done 521 * by DMA instead of programmed I/O soon. 522 */ 523 void 524 ncr53c9x_select(sc, ecb) 525 struct ncr53c9x_softc *sc; 526 struct ncr53c9x_ecb *ecb; 527 { 528 struct scsipi_link *sc_link = ecb->xs->sc_link; 529 int target = sc_link->scsipi_scsi.target; 530 int lun = sc_link->scsipi_scsi.lun; 531 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 532 int tiflags = ti->flags; 533 u_char *cmd; 534 int clen; 535 size_t dmasize; 536 537 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 538 target, lun, ecb->cmd.cmd.opcode)); 539 540 sc->sc_state = NCR_SELECTING; 541 542 /* 543 * Schedule the timeout now, the first time we will go away 544 * expecting to come back due to an interrupt, because it is 545 * always possible that the interrupt may never happen. 546 */ 547 if ((ecb->xs->xs_control & XS_CTL_POLL) == 0) { 548 int timeout = ecb->timeout; 549 550 if (hz > 100 && timeout > 1000) 551 timeout = (timeout / 1000) * hz; 552 else 553 timeout = (timeout * hz) / 1000; 554 callout_reset(&ecb->xs->xs_callout, timeout, 555 ncr53c9x_timeout, ecb); 556 } 557 558 /* 559 * The docs say the target register is never reset, and I 560 * can't think of a better place to set it 561 */ 562 NCR_WRITE_REG(sc, NCR_SELID, target); 563 ncr53c9x_setsync(sc, ti); 564 565 if (ecb->flags & ECB_SENSE) { 566 /* 567 * For REQUEST SENSE, we should not send an IDENTIFY or 568 * otherwise mangle the target. There should be no MESSAGE IN 569 * phase. 570 */ 571 if (ncr53c9x_dmaselect) { 572 /* setup DMA transfer for command */ 573 dmasize = clen = ecb->clen; 574 sc->sc_cmdlen = clen; 575 sc->sc_cmdp = (caddr_t)&ecb->cmd + 1; 576 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 577 578 /* Program the SCSI counter */ 579 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 580 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 581 if (sc->sc_cfg2 & NCRCFG2_FE) { 582 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 583 } 584 585 /* load the count in */ 586 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 587 588 /* And get the targets attention */ 589 NCRCMD(sc, NCRCMD_SELNATN | NCRCMD_DMA); 590 NCRDMA_GO(sc); 591 } else { 592 /* Now the command into the FIFO */ 593 cmd = (u_char *)&ecb->cmd.cmd; 594 clen = ecb->clen; 595 while (clen--) 596 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 597 598 NCRCMD(sc, NCRCMD_SELNATN); 599 } 600 return; 601 } 602 603 if (ncr53c9x_dmaselect && (tiflags & T_NEGOTIATE) == 0) { 604 ecb->cmd.id = 605 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1); 606 607 /* setup DMA transfer for command */ 608 dmasize = clen = ecb->clen + 1; 609 sc->sc_cmdlen = clen; 610 sc->sc_cmdp = (caddr_t)&ecb->cmd; 611 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 612 613 /* Program the SCSI counter */ 614 NCR_WRITE_REG(sc, NCR_TCL, dmasize); 615 NCR_WRITE_REG(sc, NCR_TCM, dmasize >> 8); 616 if (sc->sc_cfg2 & NCRCFG2_FE) { 617 NCR_WRITE_REG(sc, NCR_TCH, dmasize >> 16); 618 } 619 620 /* load the count in */ 621 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 622 623 /* And get the targets attention */ 624 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 625 NCRDMA_GO(sc); 626 return; 627 } 628 629 /* 630 * Who am I. This is where we tell the target that we are 631 * happy for it to disconnect etc. 632 */ 633 NCR_WRITE_REG(sc, NCR_FIFO, 634 MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF)?0:1)); 635 636 if (ti->flags & T_NEGOTIATE) { 637 /* Arbitrate, select and stop after IDENTIFY message */ 638 NCRCMD(sc, NCRCMD_SELATNS); 639 return; 640 } 641 642 /* Now the command into the FIFO */ 643 cmd = (u_char *)&ecb->cmd.cmd; 644 clen = ecb->clen; 645 while (clen--) 646 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 647 648 /* And get the targets attention */ 649 NCRCMD(sc, NCRCMD_SELATN); 650 } 651 652 void 653 ncr53c9x_free_ecb(sc, ecb, flags) 654 struct ncr53c9x_softc *sc; 655 struct ncr53c9x_ecb *ecb; 656 int flags; 657 { 658 int s; 659 660 s = splbio(); 661 662 ecb->flags = 0; 663 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 664 665 /* 666 * If there were none, wake anybody waiting for one to come free, 667 * starting with queued entries. 668 */ 669 if (ecb->chain.tqe_next == 0) 670 wakeup(&sc->free_list); 671 672 splx(s); 673 } 674 675 struct ncr53c9x_ecb * 676 ncr53c9x_get_ecb(sc, flags) 677 struct ncr53c9x_softc *sc; 678 int flags; 679 { 680 struct ncr53c9x_ecb *ecb; 681 int s; 682 683 s = splbio(); 684 685 while ((ecb = sc->free_list.tqh_first) == NULL && 686 (flags & XS_CTL_NOSLEEP) == 0) 687 tsleep(&sc->free_list, PRIBIO, "especb", 0); 688 if (ecb) { 689 TAILQ_REMOVE(&sc->free_list, ecb, chain); 690 ecb->flags |= ECB_ALLOC; 691 } 692 693 splx(s); 694 return (ecb); 695 } 696 697 /* 698 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 699 */ 700 701 /* 702 * Start a SCSI-command 703 * This function is called by the higher level SCSI-driver to queue/run 704 * SCSI-commands. 705 */ 706 int 707 ncr53c9x_scsi_cmd(xs) 708 struct scsipi_xfer *xs; 709 { 710 struct scsipi_link *sc_link = xs->sc_link; 711 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 712 struct ncr53c9x_ecb *ecb; 713 int s, flags; 714 715 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 716 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 717 sc_link->scsipi_scsi.target)); 718 719 flags = xs->xs_control; 720 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) 721 return (TRY_AGAIN_LATER); 722 723 /* Initialize ecb */ 724 ecb->xs = xs; 725 ecb->timeout = xs->timeout; 726 727 if (flags & XS_CTL_RESET) { 728 ecb->flags |= ECB_RESET; 729 ecb->clen = 0; 730 ecb->dleft = 0; 731 } else { 732 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 733 ecb->clen = xs->cmdlen; 734 ecb->daddr = xs->data; 735 ecb->dleft = xs->datalen; 736 } 737 ecb->stat = 0; 738 739 s = splbio(); 740 741 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 742 if (sc->sc_state == NCR_IDLE) 743 ncr53c9x_sched(sc); 744 745 splx(s); 746 747 if ((flags & XS_CTL_POLL) == 0) 748 return (SUCCESSFULLY_QUEUED); 749 750 /* Not allowed to use interrupts, use polling instead */ 751 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 752 ncr53c9x_timeout(ecb); 753 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 754 ncr53c9x_timeout(ecb); 755 } 756 return (COMPLETE); 757 } 758 759 /* 760 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 761 */ 762 int 763 ncr53c9x_poll(sc, xs, count) 764 struct ncr53c9x_softc *sc; 765 struct scsipi_xfer *xs; 766 int count; 767 { 768 769 NCR_TRACE(("[ncr53c9x_poll] ")); 770 while (count) { 771 if (NCRDMA_ISINTR(sc)) { 772 ncr53c9x_intr(sc); 773 } 774 #if alternatively 775 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 776 ncr53c9x_intr(sc); 777 #endif 778 if ((xs->xs_status & XS_STS_DONE) != 0) 779 return (0); 780 if (sc->sc_state == NCR_IDLE) { 781 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 782 ncr53c9x_sched(sc); 783 } 784 DELAY(1000); 785 count--; 786 } 787 return (1); 788 } 789 790 int 791 ncr53c9x_ioctl(link, cmd, arg, flag, p) 792 struct scsipi_link *link; 793 u_long cmd; 794 caddr_t arg; 795 int flag; 796 struct proc *p; 797 { 798 struct ncr53c9x_softc *sc = link->adapter_softc; 799 int s, error; 800 801 s = splbio(); 802 803 switch (cmd) { 804 case SCBUSACCEL: { 805 struct scbusaccel_args *sp = (struct scbusaccel_args *)arg; 806 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sp->sa_target]; 807 808 if (sp->sa_lun != 0) 809 break; 810 811 if ((sp->sa_flags & SC_ACCEL_SYNC) != 0) { 812 /* If this adapter can't do sync; drop it */ 813 if (sc->sc_minsync == 0) 814 break; 815 816 /* 817 * Check whether target is already clamped at 818 * non-sync operation on user request. 819 */ 820 if ((ti->flags & T_SYNCHOFF) != 0) 821 break; 822 823 printf("%s: target %d: sync negotiation\n", 824 sc->sc_dev.dv_xname, sp->sa_target); 825 ti->flags |= T_NEGOTIATE; 826 } 827 break; 828 } 829 default: 830 error = ENOTTY; 831 break; 832 } 833 splx(s); 834 return (error); 835 } 836 837 838 /* 839 * LOW LEVEL SCSI UTILITIES 840 */ 841 842 /* 843 * Schedule a scsi operation. This has now been pulled out of the interrupt 844 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 845 * This may save us an unecessary interrupt just to get things going. 846 * Should only be called when state == NCR_IDLE and at bio pl. 847 */ 848 void 849 ncr53c9x_sched(sc) 850 struct ncr53c9x_softc *sc; 851 { 852 struct ncr53c9x_ecb *ecb; 853 struct scsipi_link *sc_link; 854 struct ncr53c9x_tinfo *ti; 855 856 NCR_TRACE(("[ncr53c9x_sched] ")); 857 if (sc->sc_state != NCR_IDLE) 858 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 859 860 /* 861 * Find first ecb in ready queue that is for a target/lunit 862 * combinations that is not busy. 863 */ 864 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 865 sc_link = ecb->xs->sc_link; 866 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 867 if ((ti->lubusy & (1 << sc_link->scsipi_scsi.lun)) == 0) { 868 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 869 sc->sc_nexus = ecb; 870 ncr53c9x_select(sc, ecb); 871 break; 872 } else 873 NCR_MISC(("%d:%d busy\n", 874 sc_link->scsipi_scsi.target, 875 sc_link->scsipi_scsi.lun)); 876 } 877 } 878 879 void 880 ncr53c9x_sense(sc, ecb) 881 struct ncr53c9x_softc *sc; 882 struct ncr53c9x_ecb *ecb; 883 { 884 struct scsipi_xfer *xs = ecb->xs; 885 struct scsipi_link *sc_link = xs->sc_link; 886 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 887 struct scsipi_sense *ss = (void *)&ecb->cmd.cmd; 888 889 NCR_MISC(("requesting sense ")); 890 /* Next, setup a request sense command block */ 891 bzero(ss, sizeof(*ss)); 892 ss->opcode = REQUEST_SENSE; 893 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 894 ss->length = sizeof(struct scsipi_sense_data); 895 ecb->clen = sizeof(*ss); 896 ecb->daddr = (char *)&xs->sense.scsi_sense; 897 ecb->dleft = sizeof(struct scsipi_sense_data); 898 ecb->flags |= ECB_SENSE; 899 ecb->timeout = NCR_SENSE_TIMEOUT; 900 ti->senses++; 901 if (ecb->flags & ECB_NEXUS) 902 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 903 if (ecb == sc->sc_nexus) { 904 ecb->flags &= ~ECB_NEXUS; 905 ncr53c9x_select(sc, ecb); 906 } else { 907 ncr53c9x_dequeue(sc, ecb); 908 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 909 if (sc->sc_state == NCR_IDLE) 910 ncr53c9x_sched(sc); 911 } 912 } 913 914 /* 915 * POST PROCESSING OF SCSI_CMD (usually current) 916 */ 917 void 918 ncr53c9x_done(sc, ecb) 919 struct ncr53c9x_softc *sc; 920 struct ncr53c9x_ecb *ecb; 921 { 922 struct scsipi_xfer *xs = ecb->xs; 923 struct scsipi_link *sc_link = xs->sc_link; 924 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 925 926 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 927 928 callout_stop(&ecb->xs->xs_callout); 929 930 /* 931 * Now, if we've come here with no error code, i.e. we've kept the 932 * initial XS_NOERROR, and the status code signals that we should 933 * check sense, we'll need to set up a request sense cmd block and 934 * push the command back into the ready queue *before* any other 935 * commands for this target/lunit, else we lose the sense info. 936 * We don't support chk sense conditions for the request sense cmd. 937 */ 938 if (xs->error == XS_NOERROR) { 939 xs->status = ecb->stat; 940 if ((ecb->flags & ECB_ABORT) != 0) { 941 xs->error = XS_TIMEOUT; 942 } else if ((ecb->flags & ECB_SENSE) != 0) { 943 xs->error = XS_SENSE; 944 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 945 /* First, save the return values */ 946 xs->resid = ecb->dleft; 947 ncr53c9x_sense(sc, ecb); 948 return; 949 } else { 950 xs->resid = ecb->dleft; 951 } 952 } 953 954 xs->xs_status |= XS_STS_DONE; 955 956 #ifdef NCR53C9X_DEBUG 957 if (ncr53c9x_debug & NCR_SHOWMISC) { 958 if (xs->resid != 0) 959 printf("resid=%d ", xs->resid); 960 if (xs->error == XS_SENSE) 961 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 962 else 963 printf("error=%d\n", xs->error); 964 } 965 #endif 966 967 /* 968 * Remove the ECB from whatever queue it's on. 969 */ 970 if (ecb->flags & ECB_NEXUS) 971 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 972 if (ecb == sc->sc_nexus) { 973 sc->sc_nexus = NULL; 974 if (sc->sc_state != NCR_CLEANING) { 975 sc->sc_state = NCR_IDLE; 976 ncr53c9x_sched(sc); 977 } 978 } else 979 ncr53c9x_dequeue(sc, ecb); 980 981 ncr53c9x_free_ecb(sc, ecb, xs->xs_control); 982 ti->cmds++; 983 scsipi_done(xs); 984 } 985 986 void 987 ncr53c9x_dequeue(sc, ecb) 988 struct ncr53c9x_softc *sc; 989 struct ncr53c9x_ecb *ecb; 990 { 991 992 if (ecb->flags & ECB_NEXUS) { 993 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 994 ecb->flags &= ~ECB_NEXUS; 995 } else { 996 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 997 } 998 } 999 1000 /* 1001 * INTERRUPT/PROTOCOL ENGINE 1002 */ 1003 1004 /* 1005 * Schedule an outgoing message by prioritizing it, and asserting 1006 * attention on the bus. We can only do this when we are the initiator 1007 * else there will be an illegal command interrupt. 1008 */ 1009 #define ncr53c9x_sched_msgout(m) \ 1010 do { \ 1011 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 1012 NCRCMD(sc, NCRCMD_SETATN); \ 1013 sc->sc_flags |= NCR_ATN; \ 1014 sc->sc_msgpriq |= (m); \ 1015 } while (0) 1016 1017 int 1018 ncr53c9x_reselect(sc, message) 1019 struct ncr53c9x_softc *sc; 1020 int message; 1021 { 1022 u_char selid, target, lun; 1023 struct ncr53c9x_ecb *ecb; 1024 struct scsipi_link *sc_link; 1025 struct ncr53c9x_tinfo *ti; 1026 1027 /* 1028 * The SCSI chip made a snapshot of the data bus while the reselection 1029 * was being negotiated. This enables us to determine which target did 1030 * the reselect. 1031 */ 1032 selid = sc->sc_selid & ~(1 << sc->sc_id); 1033 if (selid & (selid - 1)) { 1034 printf("%s: reselect with invalid selid %02x;" 1035 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 1036 goto reset; 1037 } 1038 1039 /* 1040 * Search wait queue for disconnected cmd 1041 * The list should be short, so I haven't bothered with 1042 * any more sophisticated structures than a simple 1043 * singly linked list. 1044 */ 1045 target = ffs(selid) - 1; 1046 lun = message & 0x07; 1047 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 1048 ecb = ecb->chain.tqe_next) { 1049 sc_link = ecb->xs->sc_link; 1050 if (sc_link->scsipi_scsi.target == target && 1051 sc_link->scsipi_scsi.lun == lun) 1052 break; 1053 } 1054 if (ecb == NULL) { 1055 printf("%s: reselect from target %d lun %d with no nexus;" 1056 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 1057 goto abort; 1058 } 1059 1060 /* Make this nexus active again. */ 1061 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 1062 sc->sc_state = NCR_CONNECTED; 1063 sc->sc_nexus = ecb; 1064 ti = &sc->sc_tinfo[target]; 1065 #ifdef NCR53C9X_DEBUG 1066 if ((ti->lubusy & (1 << lun)) == 0) { 1067 printf("%s: reselect: target %d, lun %d: should be busy\n", 1068 sc->sc_dev.dv_xname, target, lun); 1069 ti->lubusy |= (1 << lun); 1070 } 1071 #endif 1072 ncr53c9x_setsync(sc, ti); 1073 1074 if (ecb->flags & ECB_RESET) 1075 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1076 else if (ecb->flags & ECB_ABORT) 1077 ncr53c9x_sched_msgout(SEND_ABORT); 1078 1079 /* Do an implicit RESTORE POINTERS. */ 1080 sc->sc_dp = ecb->daddr; 1081 sc->sc_dleft = ecb->dleft; 1082 1083 return (0); 1084 1085 reset: 1086 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1087 return (1); 1088 1089 abort: 1090 ncr53c9x_sched_msgout(SEND_ABORT); 1091 return (1); 1092 } 1093 1094 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 1095 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1096 #define ISEXTMSG(m) ((m) == 1) 1097 1098 /* 1099 * Get an incoming message as initiator. 1100 * 1101 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1102 * byte in the FIFO 1103 */ 1104 void 1105 ncr53c9x_msgin(sc) 1106 struct ncr53c9x_softc *sc; 1107 { 1108 int v; 1109 1110 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1111 1112 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 1113 printf("%s: msgin: no msg byte available\n", 1114 sc->sc_dev.dv_xname); 1115 return; 1116 } 1117 1118 /* 1119 * Prepare for a new message. A message should (according 1120 * to the SCSI standard) be transmitted in one single 1121 * MESSAGE_IN_PHASE. If we have been in some other phase, 1122 * then this is a new message. 1123 */ 1124 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1125 sc->sc_flags &= ~NCR_DROP_MSGI; 1126 sc->sc_imlen = 0; 1127 } 1128 1129 v = NCR_READ_REG(sc, NCR_FIFO); 1130 NCR_MISC(("<msgbyte:0x%02x>", v)); 1131 1132 #if 0 1133 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 1134 /* 1135 * Which target is reselecting us? (The ID bit really) 1136 */ 1137 sc->sc_selid = v; 1138 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1139 return; 1140 } 1141 #endif 1142 1143 sc->sc_imess[sc->sc_imlen] = v; 1144 1145 /* 1146 * If we're going to reject the message, don't bother storing 1147 * the incoming bytes. But still, we need to ACK them. 1148 */ 1149 1150 if ((sc->sc_flags & NCR_DROP_MSGI)) { 1151 NCRCMD(sc, NCRCMD_MSGOK); 1152 printf("<dropping msg byte %x>", 1153 sc->sc_imess[sc->sc_imlen]); 1154 return; 1155 } 1156 1157 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1158 ncr53c9x_sched_msgout(SEND_REJECT); 1159 sc->sc_flags |= NCR_DROP_MSGI; 1160 } else { 1161 sc->sc_imlen++; 1162 /* 1163 * This testing is suboptimal, but most 1164 * messages will be of the one byte variety, so 1165 * it should not effect performance 1166 * significantly. 1167 */ 1168 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1169 goto gotit; 1170 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1171 goto gotit; 1172 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1173 sc->sc_imlen == sc->sc_imess[1] + 2) 1174 goto gotit; 1175 } 1176 /* Ack what we have so far */ 1177 NCRCMD(sc, NCRCMD_MSGOK); 1178 return; 1179 1180 gotit: 1181 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1182 /* 1183 * Now we should have a complete message (1 byte, 2 byte 1184 * and moderately long extended messages). We only handle 1185 * extended messages which total length is shorter than 1186 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1187 */ 1188 switch (sc->sc_state) { 1189 struct ncr53c9x_ecb *ecb; 1190 struct ncr53c9x_tinfo *ti; 1191 1192 case NCR_CONNECTED: 1193 ecb = sc->sc_nexus; 1194 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1195 1196 switch (sc->sc_imess[0]) { 1197 case MSG_CMDCOMPLETE: 1198 NCR_MSGS(("cmdcomplete ")); 1199 if (sc->sc_dleft < 0) { 1200 scsi_print_addr(ecb->xs->sc_link); 1201 printf("got %ld extra bytes\n", 1202 -(long)sc->sc_dleft); 1203 sc->sc_dleft = 0; 1204 } 1205 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 1206 ? 0 1207 : sc->sc_dleft; 1208 if ((ecb->flags & ECB_SENSE) == 0) 1209 ecb->xs->resid = ecb->dleft; 1210 sc->sc_state = NCR_CMDCOMPLETE; 1211 break; 1212 1213 case MSG_MESSAGE_REJECT: 1214 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1215 switch (sc->sc_msgout) { 1216 case SEND_SDTR: 1217 sc->sc_flags &= ~NCR_SYNCHNEGO; 1218 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1219 ncr53c9x_setsync(sc, ti); 1220 break; 1221 case SEND_INIT_DET_ERR: 1222 goto abort; 1223 } 1224 break; 1225 1226 case MSG_NOOP: 1227 NCR_MSGS(("noop ")); 1228 break; 1229 1230 case MSG_DISCONNECT: 1231 NCR_MSGS(("disconnect ")); 1232 ti->dconns++; 1233 sc->sc_state = NCR_DISCONNECT; 1234 1235 /* 1236 * Mark the fact that all bytes have moved. The 1237 * target may not bother to do a SAVE POINTERS 1238 * at this stage. This flag will set the residual 1239 * count to zero on MSG COMPLETE. 1240 */ 1241 if (sc->sc_dleft == 0) 1242 ecb->flags |= ECB_TENTATIVE_DONE; 1243 1244 break; 1245 1246 case MSG_SAVEDATAPOINTER: 1247 NCR_MSGS(("save datapointer ")); 1248 ecb->daddr = sc->sc_dp; 1249 ecb->dleft = sc->sc_dleft; 1250 break; 1251 1252 case MSG_RESTOREPOINTERS: 1253 NCR_MSGS(("restore datapointer ")); 1254 sc->sc_dp = ecb->daddr; 1255 sc->sc_dleft = ecb->dleft; 1256 break; 1257 1258 case MSG_EXTENDED: 1259 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1260 switch (sc->sc_imess[2]) { 1261 case MSG_EXT_SDTR: 1262 NCR_MSGS(("SDTR period %d, offset %d ", 1263 sc->sc_imess[3], sc->sc_imess[4])); 1264 if (sc->sc_imess[1] != 3) 1265 goto reject; 1266 ti->period = sc->sc_imess[3]; 1267 ti->offset = sc->sc_imess[4]; 1268 ti->flags &= ~T_NEGOTIATE; 1269 if (sc->sc_minsync == 0 || 1270 ti->offset == 0 || 1271 ti->period > 124) { 1272 #ifdef NCR53C9X_DEBUG 1273 scsi_print_addr(ecb->xs->sc_link); 1274 printf("async mode\n"); 1275 #endif 1276 if ((sc->sc_flags&NCR_SYNCHNEGO) 1277 == 0) { 1278 /* 1279 * target initiated negotiation 1280 */ 1281 ti->offset = 0; 1282 ti->flags &= ~T_SYNCMODE; 1283 ncr53c9x_sched_msgout( 1284 SEND_SDTR); 1285 } else { 1286 /* we are async */ 1287 ti->flags &= ~T_SYNCMODE; 1288 } 1289 } else { 1290 int r = 250/ti->period; 1291 int s = (100*250)/ti->period - 100*r; 1292 int p; 1293 1294 p = ncr53c9x_stp2cpb(sc, ti->period); 1295 ti->period = ncr53c9x_cpb2stp(sc, p); 1296 #ifdef NCR53C9X_DEBUG 1297 scsi_print_addr(ecb->xs->sc_link); 1298 printf("max sync rate %d.%02dMB/s\n", 1299 r, s); 1300 #endif 1301 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) { 1302 /* 1303 * target initiated negotiation 1304 */ 1305 if (ti->period < 1306 sc->sc_minsync) 1307 ti->period = 1308 sc->sc_minsync; 1309 if (ti->offset > 15) 1310 ti->offset = 15; 1311 ti->flags &= ~T_SYNCMODE; 1312 ncr53c9x_sched_msgout( 1313 SEND_SDTR); 1314 } else { 1315 /* we are sync */ 1316 ti->flags |= T_SYNCMODE; 1317 } 1318 } 1319 sc->sc_flags &= ~NCR_SYNCHNEGO; 1320 ncr53c9x_setsync(sc, ti); 1321 break; 1322 1323 default: 1324 scsi_print_addr(ecb->xs->sc_link); 1325 printf("unrecognized MESSAGE EXTENDED;" 1326 " sending REJECT\n"); 1327 goto reject; 1328 } 1329 break; 1330 1331 default: 1332 NCR_MSGS(("ident ")); 1333 scsi_print_addr(ecb->xs->sc_link); 1334 printf("unrecognized MESSAGE; sending REJECT\n"); 1335 reject: 1336 ncr53c9x_sched_msgout(SEND_REJECT); 1337 break; 1338 } 1339 break; 1340 1341 case NCR_RESELECTED: 1342 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1343 printf("%s: reselect without IDENTIFY;" 1344 " sending DEVICE RESET\n", 1345 sc->sc_dev.dv_xname); 1346 goto reset; 1347 } 1348 1349 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1350 break; 1351 1352 default: 1353 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1354 sc->sc_dev.dv_xname); 1355 reset: 1356 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1357 break; 1358 1359 abort: 1360 ncr53c9x_sched_msgout(SEND_ABORT); 1361 break; 1362 } 1363 1364 /* Ack last message byte */ 1365 NCRCMD(sc, NCRCMD_MSGOK); 1366 1367 /* Done, reset message pointer. */ 1368 sc->sc_flags &= ~NCR_DROP_MSGI; 1369 sc->sc_imlen = 0; 1370 } 1371 1372 1373 /* 1374 * Send the highest priority, scheduled message 1375 */ 1376 void 1377 ncr53c9x_msgout(sc) 1378 struct ncr53c9x_softc *sc; 1379 { 1380 struct ncr53c9x_tinfo *ti; 1381 struct ncr53c9x_ecb *ecb; 1382 size_t size; 1383 1384 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1385 sc->sc_msgpriq, sc->sc_prevphase)); 1386 1387 /* 1388 * XXX - the NCR_ATN flag is not in sync with the actual ATN 1389 * condition on the SCSI bus. The 53c9x chip 1390 * automatically turns off ATN before sending the 1391 * message byte. (see also the comment below in the 1392 * default case when picking out a message to send) 1393 */ 1394 if (sc->sc_flags & NCR_ATN) { 1395 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1396 new: 1397 NCRCMD(sc, NCRCMD_FLUSH); 1398 DELAY(1); 1399 sc->sc_msgoutq = 0; 1400 sc->sc_omlen = 0; 1401 } 1402 } else { 1403 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1404 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1405 goto new; 1406 } else { 1407 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1408 sc->sc_dev.dv_xname, __LINE__); 1409 } 1410 } 1411 1412 if (sc->sc_omlen == 0) { 1413 /* Pick up highest priority message */ 1414 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1415 sc->sc_msgoutq |= sc->sc_msgout; 1416 sc->sc_msgpriq &= ~sc->sc_msgout; 1417 sc->sc_omlen = 1; /* "Default" message len */ 1418 switch (sc->sc_msgout) { 1419 case SEND_SDTR: 1420 ecb = sc->sc_nexus; 1421 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1422 sc->sc_omess[0] = MSG_EXTENDED; 1423 sc->sc_omess[1] = 3; 1424 sc->sc_omess[2] = MSG_EXT_SDTR; 1425 sc->sc_omess[3] = ti->period; 1426 sc->sc_omess[4] = ti->offset; 1427 sc->sc_omlen = 5; 1428 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1429 ti->flags |= T_SYNCMODE; 1430 ncr53c9x_setsync(sc, ti); 1431 } 1432 break; 1433 case SEND_IDENTIFY: 1434 if (sc->sc_state != NCR_CONNECTED) { 1435 printf("%s at line %d: no nexus\n", 1436 sc->sc_dev.dv_xname, __LINE__); 1437 } 1438 ecb = sc->sc_nexus; 1439 sc->sc_omess[0] = 1440 MSG_IDENTIFY(ecb->xs->sc_link->scsipi_scsi.lun, 0); 1441 break; 1442 case SEND_DEV_RESET: 1443 sc->sc_flags |= NCR_ABORTING; 1444 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1445 ecb = sc->sc_nexus; 1446 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1447 ti->flags &= ~T_SYNCMODE; 1448 if ((ti->flags & T_SYNCHOFF) == 0) 1449 /* We can re-start sync negotiation */ 1450 ti->flags |= T_NEGOTIATE; 1451 break; 1452 case SEND_PARITY_ERROR: 1453 sc->sc_omess[0] = MSG_PARITY_ERROR; 1454 break; 1455 case SEND_ABORT: 1456 sc->sc_flags |= NCR_ABORTING; 1457 sc->sc_omess[0] = MSG_ABORT; 1458 break; 1459 case SEND_INIT_DET_ERR: 1460 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1461 break; 1462 case SEND_REJECT: 1463 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1464 break; 1465 default: 1466 /* 1467 * We normally do not get here, since the chip 1468 * automatically turns off ATN before the last 1469 * byte of a message is sent to the target. 1470 * However, if the target rejects our (multi-byte) 1471 * message early by switching to MSG IN phase 1472 * ATN remains on, so the target may return to 1473 * MSG OUT phase. If there are no scheduled messages 1474 * left we send a NO-OP. 1475 * 1476 * XXX - Note that this leaves no useful purpose for 1477 * the NCR_ATN flag. 1478 */ 1479 sc->sc_flags &= ~NCR_ATN; 1480 sc->sc_omess[0] = MSG_NOOP; 1481 break; 1482 } 1483 sc->sc_omp = sc->sc_omess; 1484 } 1485 1486 /* (re)send the message */ 1487 size = min(sc->sc_omlen, sc->sc_maxxfer); 1488 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1489 /* Program the SCSI counter */ 1490 NCR_WRITE_REG(sc, NCR_TCL, size); 1491 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1492 if (sc->sc_cfg2 & NCRCFG2_FE) { 1493 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1494 } 1495 /* Load the count in and start the message-out transfer */ 1496 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1497 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1498 NCRDMA_GO(sc); 1499 } 1500 1501 /* 1502 * This is the most critical part of the driver, and has to know 1503 * how to deal with *all* error conditions and phases from the SCSI 1504 * bus. If there are no errors and the DMA was active, then call the 1505 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1506 * and we can return from here without further processing. 1507 * 1508 * Most of this needs verifying. 1509 */ 1510 int sdebug = 0; 1511 int 1512 ncr53c9x_intr(arg) 1513 void *arg; 1514 { 1515 struct ncr53c9x_softc *sc = arg; 1516 struct ncr53c9x_ecb *ecb; 1517 struct scsipi_link *sc_link; 1518 struct ncr53c9x_tinfo *ti; 1519 size_t size; 1520 int nfifo; 1521 1522 NCR_TRACE(("[ncr53c9x_intr] ")); 1523 1524 if (!NCRDMA_ISINTR(sc)) 1525 return (0); 1526 1527 again: 1528 /* and what do the registers say... */ 1529 ncr53c9x_readregs(sc); 1530 1531 sc->sc_intrcnt.ev_count++; 1532 1533 /* 1534 * At the moment, only a SCSI Bus Reset or Illegal 1535 * Command are classed as errors. A disconnect is a 1536 * valid condition, and we let the code check is the 1537 * "NCR_BUSFREE_OK" flag was set before declaring it 1538 * and error. 1539 * 1540 * Also, the status register tells us about "Gross 1541 * Errors" and "Parity errors". Only the Gross Error 1542 * is really bad, and the parity errors are dealt 1543 * with later 1544 * 1545 * TODO 1546 * If there are too many parity error, go to slow 1547 * cable mode ? 1548 */ 1549 1550 /* SCSI Reset */ 1551 if (sc->sc_espintr & NCRINTR_SBR) { 1552 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1553 NCRCMD(sc, NCRCMD_FLUSH); 1554 DELAY(1); 1555 } 1556 if (sc->sc_state != NCR_SBR) { 1557 printf("%s: SCSI bus reset\n", 1558 sc->sc_dev.dv_xname); 1559 ncr53c9x_init(sc, 0); /* Restart everything */ 1560 return (1); 1561 } 1562 #if 0 1563 /*XXX*/ printf("<expected bus reset: " 1564 "[intr %x, stat %x, step %d]>\n", 1565 sc->sc_espintr, sc->sc_espstat, 1566 sc->sc_espstep); 1567 #endif 1568 if (sc->sc_nexus) 1569 panic("%s: nexus in reset state", 1570 sc->sc_dev.dv_xname); 1571 goto sched; 1572 } 1573 1574 ecb = sc->sc_nexus; 1575 1576 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1577 if (sc->sc_espintr & NCRINTR_ERR || 1578 sc->sc_espstat & NCRSTAT_GE) { 1579 1580 if (sc->sc_espstat & NCRSTAT_GE) { 1581 /* Gross Error; no target ? */ 1582 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1583 NCRCMD(sc, NCRCMD_FLUSH); 1584 DELAY(1); 1585 } 1586 if (sc->sc_state == NCR_CONNECTED || 1587 sc->sc_state == NCR_SELECTING) { 1588 ecb->xs->error = XS_TIMEOUT; 1589 ncr53c9x_done(sc, ecb); 1590 } 1591 return (1); 1592 } 1593 1594 if (sc->sc_espintr & NCRINTR_ILL) { 1595 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1596 /* 1597 * Eat away "Illegal command" interrupt 1598 * on a ESP100 caused by a re-selection 1599 * while we were trying to select 1600 * another target. 1601 */ 1602 #ifdef DEBUG 1603 printf("%s: ESP100 work-around activated\n", 1604 sc->sc_dev.dv_xname); 1605 #endif 1606 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1607 return (1); 1608 } 1609 /* illegal command, out of sync ? */ 1610 printf("%s: illegal command: 0x%x " 1611 "(state %d, phase %x, prevphase %x)\n", 1612 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1613 sc->sc_state, sc->sc_phase, 1614 sc->sc_prevphase); 1615 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1616 NCRCMD(sc, NCRCMD_FLUSH); 1617 DELAY(1); 1618 } 1619 ncr53c9x_init(sc, 1); /* Restart everything */ 1620 return (1); 1621 } 1622 } 1623 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1624 1625 /* 1626 * Call if DMA is active. 1627 * 1628 * If DMA_INTR returns true, then maybe go 'round the loop 1629 * again in case there is no more DMA queued, but a phase 1630 * change is expected. 1631 */ 1632 if (NCRDMA_ISACTIVE(sc)) { 1633 int r = NCRDMA_INTR(sc); 1634 if (r == -1) { 1635 printf("%s: DMA error; resetting\n", 1636 sc->sc_dev.dv_xname); 1637 ncr53c9x_init(sc, 1); 1638 } 1639 /* If DMA active here, then go back to work... */ 1640 if (NCRDMA_ISACTIVE(sc)) 1641 return (1); 1642 1643 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 1644 /* 1645 * DMA not completed. If we can not find a 1646 * acceptable explanation, print a diagnostic. 1647 */ 1648 if (sc->sc_state == NCR_SELECTING) 1649 /* 1650 * This can happen if we are reselected 1651 * while using DMA to select a target. 1652 */ 1653 /*void*/; 1654 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1655 /* 1656 * Our (multi-byte) message (eg SDTR) was 1657 * interrupted by the target to send 1658 * a MSG REJECT. 1659 * Print diagnostic if current phase 1660 * is not MESSAGE IN. 1661 */ 1662 if (sc->sc_phase != MESSAGE_IN_PHASE) 1663 printf("%s: !TC on MSG OUT" 1664 " [intr %x, stat %x, step %d]" 1665 " prevphase %x, resid %lx\n", 1666 sc->sc_dev.dv_xname, 1667 sc->sc_espintr, 1668 sc->sc_espstat, 1669 sc->sc_espstep, 1670 sc->sc_prevphase, 1671 (u_long)sc->sc_omlen); 1672 } else if (sc->sc_dleft == 0) { 1673 /* 1674 * The DMA operation was started for 1675 * a DATA transfer. Print a diagnostic 1676 * if the DMA counter and TC bit 1677 * appear to be out of sync. 1678 */ 1679 printf("%s: !TC on DATA XFER" 1680 " [intr %x, stat %x, step %d]" 1681 " prevphase %x, resid %x\n", 1682 sc->sc_dev.dv_xname, 1683 sc->sc_espintr, 1684 sc->sc_espstat, 1685 sc->sc_espstep, 1686 sc->sc_prevphase, 1687 ecb?ecb->dleft:-1); 1688 } 1689 } 1690 } 1691 1692 /* 1693 * Check for less serious errors. 1694 */ 1695 if (sc->sc_espstat & NCRSTAT_PE) { 1696 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1697 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1698 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1699 else 1700 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1701 } 1702 1703 if (sc->sc_espintr & NCRINTR_DIS) { 1704 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1705 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1706 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1707 NCRCMD(sc, NCRCMD_FLUSH); 1708 DELAY(1); 1709 } 1710 /* 1711 * This command must (apparently) be issued within 1712 * 250mS of a disconnect. So here you are... 1713 */ 1714 NCRCMD(sc, NCRCMD_ENSEL); 1715 1716 switch (sc->sc_state) { 1717 case NCR_RESELECTED: 1718 goto sched; 1719 1720 case NCR_SELECTING: 1721 ecb->xs->error = XS_SELTIMEOUT; 1722 goto finish; 1723 1724 case NCR_CONNECTED: 1725 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1726 #ifdef NCR53C9X_DEBUG 1727 if (ecb) 1728 scsi_print_addr(ecb->xs->sc_link); 1729 printf("sync nego not completed!\n"); 1730 #endif 1731 ti = &sc->sc_tinfo[ecb->xs->sc_link->scsipi_scsi.target]; 1732 sc->sc_flags &= ~NCR_SYNCHNEGO; 1733 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1734 } 1735 1736 /* it may be OK to disconnect */ 1737 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1738 /* 1739 * Section 5.1.1 of the SCSI 2 spec 1740 * suggests issuing a REQUEST SENSE 1741 * following an unexpected disconnect. 1742 * Some devices go into a contingent 1743 * allegiance condition when 1744 * disconnecting, and this is necessary 1745 * to clean up their state. 1746 */ 1747 printf("%s: unexpected disconnect; ", 1748 sc->sc_dev.dv_xname); 1749 if (ecb->flags & ECB_SENSE) { 1750 printf("resetting\n"); 1751 goto reset; 1752 } 1753 printf("sending REQUEST SENSE\n"); 1754 callout_stop(&ecb->xs->xs_callout); 1755 ncr53c9x_sense(sc, ecb); 1756 goto out; 1757 } 1758 1759 ecb->xs->error = XS_TIMEOUT; 1760 goto finish; 1761 1762 case NCR_DISCONNECT: 1763 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1764 sc->sc_nexus = NULL; 1765 goto sched; 1766 1767 case NCR_CMDCOMPLETE: 1768 goto finish; 1769 } 1770 } 1771 1772 switch (sc->sc_state) { 1773 1774 case NCR_SBR: 1775 printf("%s: waiting for SCSI Bus Reset to happen\n", 1776 sc->sc_dev.dv_xname); 1777 return (1); 1778 1779 case NCR_RESELECTED: 1780 /* 1781 * we must be continuing a message ? 1782 */ 1783 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1784 printf("%s: target didn't identify\n", 1785 sc->sc_dev.dv_xname); 1786 ncr53c9x_init(sc, 1); 1787 return (1); 1788 } 1789 printf("<<RESELECT CONT'd>>"); 1790 #if XXXX 1791 ncr53c9x_msgin(sc); 1792 if (sc->sc_state != NCR_CONNECTED) { 1793 /* IDENTIFY fail?! */ 1794 printf("%s: identify failed\n", 1795 sc->sc_dev.dv_xname); 1796 ncr53c9x_init(sc, 1); 1797 return (1); 1798 } 1799 #endif 1800 break; 1801 1802 case NCR_IDLE: 1803 case NCR_SELECTING: 1804 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1805 sc->sc_flags = 0; 1806 ecb = sc->sc_nexus; 1807 if (ecb != NULL && (ecb->flags & ECB_NEXUS)) { 1808 scsi_print_addr(ecb->xs->sc_link); 1809 printf("ECB_NEXUS while in state %x\n", sc->sc_state); 1810 } 1811 1812 if (sc->sc_espintr & NCRINTR_RESEL) { 1813 /* 1814 * If we're trying to select a 1815 * target ourselves, push our command 1816 * back into the ready list. 1817 */ 1818 if (sc->sc_state == NCR_SELECTING) { 1819 NCR_MISC(("backoff selector ")); 1820 callout_stop(&ecb->xs->xs_callout); 1821 sc_link = ecb->xs->sc_link; 1822 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1823 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1824 ecb = sc->sc_nexus = NULL; 1825 } 1826 sc->sc_state = NCR_RESELECTED; 1827 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1828 /* 1829 * Things are seriously fucked up. 1830 * Pull the brakes, i.e. reset 1831 */ 1832 printf("%s: target didn't identify\n", 1833 sc->sc_dev.dv_xname); 1834 ncr53c9x_init(sc, 1); 1835 return (1); 1836 } 1837 /* 1838 * The C90 only inhibits FIFO writes until 1839 * reselection is complete, instead of 1840 * waiting until the interrupt status register 1841 * has been read. So, if the reselect happens 1842 * while we were entering a command bytes (for 1843 * another target) some of those bytes can 1844 * appear in the FIFO here, after the 1845 * interrupt is taken. 1846 */ 1847 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1848 if (nfifo < 2 || 1849 (nfifo > 2 && 1850 sc->sc_rev != NCR_VARIANT_ESP100)) { 1851 printf("%s: RESELECT: %d bytes in FIFO! " 1852 "[intr %x, stat %x, step %d, prevphase %x]\n", 1853 sc->sc_dev.dv_xname, 1854 nfifo, 1855 sc->sc_espintr, 1856 sc->sc_espstat, 1857 sc->sc_espstep, 1858 sc->sc_prevphase); 1859 ncr53c9x_init(sc, 1); 1860 return (1); 1861 } 1862 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1863 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1864 1865 /* Handle identify message */ 1866 ncr53c9x_msgin(sc); 1867 if (nfifo != 2) { 1868 /* 1869 * Note: this should not happen 1870 * with `dmaselect' on. 1871 */ 1872 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1873 NCRCMD(sc, NCRCMD_FLUSH); 1874 } else if (ncr53c9x_dmaselect && 1875 sc->sc_rev == NCR_VARIANT_ESP100) { 1876 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1877 } 1878 1879 if (sc->sc_state != NCR_CONNECTED) { 1880 /* IDENTIFY fail?! */ 1881 printf("%s: identify failed\n", 1882 sc->sc_dev.dv_xname); 1883 ncr53c9x_init(sc, 1); 1884 return (1); 1885 } 1886 goto shortcut; /* ie. next phase expected soon */ 1887 } 1888 1889 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1890 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1891 /* 1892 * Arbitration won; examine the `step' register 1893 * to determine how far the selection could progress. 1894 */ 1895 ecb = sc->sc_nexus; 1896 if (!ecb) 1897 panic("ncr53c9x: no nexus"); 1898 1899 sc_link = ecb->xs->sc_link; 1900 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1901 1902 switch (sc->sc_espstep) { 1903 case 0: 1904 /* 1905 * The target did not respond with a 1906 * message out phase - probably an old 1907 * device that doesn't recognize ATN. 1908 * Clear ATN and just continue, the 1909 * target should be in the command 1910 * phase. 1911 * XXXX check for command phase? 1912 */ 1913 NCRCMD(sc, NCRCMD_RSTATN); 1914 break; 1915 case 1: 1916 if ((ti->flags & T_NEGOTIATE) == 0) { 1917 printf("%s: step 1 & !NEG\n", 1918 sc->sc_dev.dv_xname); 1919 goto reset; 1920 } 1921 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1922 printf("%s: !MSGOUT\n", 1923 sc->sc_dev.dv_xname); 1924 goto reset; 1925 } 1926 /* Start negotiating */ 1927 ti->period = sc->sc_minsync; 1928 ti->offset = 15; 1929 sc->sc_flags |= NCR_SYNCHNEGO; 1930 ncr53c9x_sched_msgout(SEND_SDTR); 1931 break; 1932 case 3: 1933 /* 1934 * Grr, this is supposed to mean 1935 * "target left command phase prematurely". 1936 * It seems to happen regularly when 1937 * sync mode is on. 1938 * Look at FIFO to see if command went out. 1939 * (Timing problems?) 1940 */ 1941 if (ncr53c9x_dmaselect) { 1942 if (sc->sc_cmdlen == 0) 1943 /* Hope for the best.. */ 1944 break; 1945 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1946 & NCRFIFO_FF) == 0) { 1947 /* Hope for the best.. */ 1948 break; 1949 } 1950 printf("(%s:%d:%d): selection failed;" 1951 " %d left in FIFO " 1952 "[intr %x, stat %x, step %d]\n", 1953 sc->sc_dev.dv_xname, 1954 sc_link->scsipi_scsi.target, 1955 sc_link->scsipi_scsi.lun, 1956 NCR_READ_REG(sc, NCR_FFLAG) 1957 & NCRFIFO_FF, 1958 sc->sc_espintr, sc->sc_espstat, 1959 sc->sc_espstep); 1960 NCRCMD(sc, NCRCMD_FLUSH); 1961 ncr53c9x_sched_msgout(SEND_ABORT); 1962 return (1); 1963 case 2: 1964 /* Select stuck at Command Phase */ 1965 NCRCMD(sc, NCRCMD_FLUSH); 1966 break; 1967 case 4: 1968 if (ncr53c9x_dmaselect && 1969 sc->sc_cmdlen != 0) 1970 printf("(%s:%d:%d): select; " 1971 "%lu left in DMA buffer " 1972 "[intr %x, stat %x, step %d]\n", 1973 sc->sc_dev.dv_xname, 1974 sc_link->scsipi_scsi.target, 1975 sc_link->scsipi_scsi.lun, 1976 (u_long)sc->sc_cmdlen, 1977 sc->sc_espintr, 1978 sc->sc_espstat, 1979 sc->sc_espstep); 1980 /* So far, everything went fine */ 1981 break; 1982 } 1983 1984 ecb->flags |= ECB_NEXUS; 1985 ti->lubusy |= (1 << sc_link->scsipi_scsi.lun); 1986 1987 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1988 /* Do an implicit RESTORE POINTERS. */ 1989 sc->sc_dp = ecb->daddr; 1990 sc->sc_dleft = ecb->dleft; 1991 sc->sc_state = NCR_CONNECTED; 1992 break; 1993 1994 } else { 1995 1996 printf("%s: unexpected status after select" 1997 ": [intr %x, stat %x, step %x]\n", 1998 sc->sc_dev.dv_xname, 1999 sc->sc_espintr, sc->sc_espstat, 2000 sc->sc_espstep); 2001 NCRCMD(sc, NCRCMD_FLUSH); 2002 DELAY(1); 2003 goto reset; 2004 } 2005 if (sc->sc_state == NCR_IDLE) { 2006 printf("%s: stray interrupt\n", 2007 sc->sc_dev.dv_xname); 2008 return (0); 2009 } 2010 break; 2011 2012 case NCR_CONNECTED: 2013 if (sc->sc_flags & NCR_ICCS) { 2014 /* "Initiate Command Complete Steps" in progress */ 2015 u_char msg; 2016 2017 sc->sc_flags &= ~NCR_ICCS; 2018 2019 if (!(sc->sc_espintr & NCRINTR_DONE)) { 2020 printf("%s: ICCS: " 2021 ": [intr %x, stat %x, step %x]\n", 2022 sc->sc_dev.dv_xname, 2023 sc->sc_espintr, sc->sc_espstat, 2024 sc->sc_espstep); 2025 } 2026 if ((NCR_READ_REG(sc, NCR_FFLAG) 2027 & NCRFIFO_FF) != 2) { 2028 /* Drop excess bytes from the queue */ 2029 int i = (NCR_READ_REG(sc, NCR_FFLAG) 2030 & NCRFIFO_FF) - 2; 2031 while (i-- > 0) 2032 (void) NCR_READ_REG(sc, NCR_FIFO); 2033 } 2034 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 2035 msg = NCR_READ_REG(sc, NCR_FIFO); 2036 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2037 if (msg == MSG_CMDCOMPLETE) { 2038 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 2039 ? 0 2040 : sc->sc_dleft; 2041 if ((ecb->flags & ECB_SENSE) == 0) 2042 ecb->xs->resid = ecb->dleft; 2043 sc->sc_state = NCR_CMDCOMPLETE; 2044 } else 2045 printf("%s: STATUS_PHASE: msg %d\n", 2046 sc->sc_dev.dv_xname, msg); 2047 NCRCMD(sc, NCRCMD_MSGOK); 2048 goto shortcut; /* ie. wait for disconnect */ 2049 } 2050 break; 2051 default: 2052 panic("%s: invalid state: %d", 2053 sc->sc_dev.dv_xname, 2054 sc->sc_state); 2055 } 2056 2057 /* 2058 * Driver is now in state NCR_CONNECTED, i.e. we 2059 * have a current command working the SCSI bus. 2060 */ 2061 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 2062 panic("ncr53c9x: no nexus"); 2063 } 2064 2065 switch (sc->sc_phase) { 2066 case MESSAGE_OUT_PHASE: 2067 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 2068 ncr53c9x_msgout(sc); 2069 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2070 break; 2071 case MESSAGE_IN_PHASE: 2072 NCR_PHASE(("MESSAGE_IN_PHASE ")); 2073 sc->sc_prevphase = MESSAGE_IN_PHASE; 2074 if (sc->sc_espintr & NCRINTR_BS) { 2075 NCRCMD(sc, NCRCMD_FLUSH); 2076 sc->sc_flags |= NCR_WAITI; 2077 NCRCMD(sc, NCRCMD_TRANS); 2078 } else if (sc->sc_espintr & NCRINTR_FC) { 2079 if ((sc->sc_flags & NCR_WAITI) == 0) { 2080 printf("%s: MSGIN: unexpected FC bit: " 2081 "[intr %x, stat %x, step %x]\n", 2082 sc->sc_dev.dv_xname, 2083 sc->sc_espintr, sc->sc_espstat, 2084 sc->sc_espstep); 2085 } 2086 sc->sc_flags &= ~NCR_WAITI; 2087 ncr53c9x_msgin(sc); 2088 } else { 2089 printf("%s: MSGIN: weird bits: " 2090 "[intr %x, stat %x, step %x]\n", 2091 sc->sc_dev.dv_xname, 2092 sc->sc_espintr, sc->sc_espstat, 2093 sc->sc_espstep); 2094 } 2095 goto shortcut; /* i.e. expect data to be ready */ 2096 break; 2097 case COMMAND_PHASE: 2098 /* 2099 * Send the command block. Normally we don't see this 2100 * phase because the SEL_ATN command takes care of 2101 * all this. However, we end up here if either the 2102 * target or we wanted to exchange some more messages 2103 * first (e.g. to start negotiations). 2104 */ 2105 2106 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2107 ecb->cmd.cmd.opcode, ecb->clen)); 2108 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2109 NCRCMD(sc, NCRCMD_FLUSH); 2110 DELAY(1); 2111 } 2112 if (ncr53c9x_dmaselect) { 2113 size_t size; 2114 /* setup DMA transfer for command */ 2115 size = ecb->clen; 2116 sc->sc_cmdlen = size; 2117 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2118 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2119 0, &size); 2120 /* Program the SCSI counter */ 2121 NCR_WRITE_REG(sc, NCR_TCL, size); 2122 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2123 if (sc->sc_cfg2 & NCRCFG2_FE) { 2124 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2125 } 2126 2127 /* load the count in */ 2128 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2129 2130 /* start the command transfer */ 2131 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2132 NCRDMA_GO(sc); 2133 } else { 2134 u_char *cmd = (u_char *)&ecb->cmd.cmd; 2135 int i; 2136 /* Now the command into the FIFO */ 2137 for (i = 0; i < ecb->clen; i++) 2138 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 2139 NCRCMD(sc, NCRCMD_TRANS); 2140 } 2141 sc->sc_prevphase = COMMAND_PHASE; 2142 break; 2143 case DATA_OUT_PHASE: 2144 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 2145 NCRCMD(sc, NCRCMD_FLUSH); 2146 size = min(sc->sc_dleft, sc->sc_maxxfer); 2147 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2148 0, &size); 2149 sc->sc_prevphase = DATA_OUT_PHASE; 2150 goto setup_xfer; 2151 case DATA_IN_PHASE: 2152 NCR_PHASE(("DATA_IN_PHASE ")); 2153 if (sc->sc_rev == NCR_VARIANT_ESP100) 2154 NCRCMD(sc, NCRCMD_FLUSH); 2155 size = min(sc->sc_dleft, sc->sc_maxxfer); 2156 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 2157 1, &size); 2158 sc->sc_prevphase = DATA_IN_PHASE; 2159 setup_xfer: 2160 /* Target returned to data phase: wipe "done" memory */ 2161 ecb->flags &= ~ECB_TENTATIVE_DONE; 2162 2163 /* Program the SCSI counter */ 2164 NCR_WRITE_REG(sc, NCR_TCL, size); 2165 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 2166 if (sc->sc_cfg2 & NCRCFG2_FE) { 2167 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 2168 } 2169 /* load the count in */ 2170 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2171 2172 /* 2173 * Note that if `size' is 0, we've already transceived 2174 * all the bytes we want but we're still in DATA PHASE. 2175 * Apparently, the device needs padding. Also, a 2176 * transfer size of 0 means "maximum" to the chip 2177 * DMA logic. 2178 */ 2179 NCRCMD(sc, 2180 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 2181 NCRDMA_GO(sc); 2182 return (1); 2183 case STATUS_PHASE: 2184 NCR_PHASE(("STATUS_PHASE ")); 2185 sc->sc_flags |= NCR_ICCS; 2186 NCRCMD(sc, NCRCMD_ICCS); 2187 sc->sc_prevphase = STATUS_PHASE; 2188 goto shortcut; /* i.e. expect status results soon */ 2189 break; 2190 case INVALID_PHASE: 2191 break; 2192 default: 2193 printf("%s: unexpected bus phase; resetting\n", 2194 sc->sc_dev.dv_xname); 2195 goto reset; 2196 } 2197 2198 out: 2199 return (1); 2200 2201 reset: 2202 ncr53c9x_init(sc, 1); 2203 goto out; 2204 2205 finish: 2206 ncr53c9x_done(sc, ecb); 2207 goto out; 2208 2209 sched: 2210 sc->sc_state = NCR_IDLE; 2211 ncr53c9x_sched(sc); 2212 goto out; 2213 2214 shortcut: 2215 /* 2216 * The idea is that many of the SCSI operations take very little 2217 * time, and going away and getting interrupted is too high an 2218 * overhead to pay. For example, selecting, sending a message 2219 * and command and then doing some work can be done in one "pass". 2220 * 2221 * The delay is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 2222 * at 40Mhz. This needs testing. 2223 */ 2224 DELAY(50/sc->sc_freq); 2225 if (NCRDMA_ISINTR(sc)) 2226 goto again; 2227 goto out; 2228 } 2229 2230 void 2231 ncr53c9x_abort(sc, ecb) 2232 struct ncr53c9x_softc *sc; 2233 struct ncr53c9x_ecb *ecb; 2234 { 2235 2236 /* 2 secs for the abort */ 2237 ecb->timeout = NCR_ABORT_TIMEOUT; 2238 ecb->flags |= ECB_ABORT; 2239 2240 if (ecb == sc->sc_nexus) { 2241 int timeout; 2242 2243 /* 2244 * If we're still selecting, the message will be scheduled 2245 * after selection is complete. 2246 */ 2247 if (sc->sc_state == NCR_CONNECTED) 2248 ncr53c9x_sched_msgout(SEND_ABORT); 2249 2250 /* 2251 * Reschedule timeout. 2252 */ 2253 timeout = ecb->timeout; 2254 if (hz > 100 && timeout > 1000) 2255 timeout = (timeout / 1000) * hz; 2256 else 2257 timeout = (timeout * hz) / 1000; 2258 callout_reset(&ecb->xs->xs_callout, timeout, 2259 ncr53c9x_timeout, ecb); 2260 } else { 2261 /* The command should be on the nexus list */ 2262 if ((ecb->flags & ECB_NEXUS) == 0) { 2263 scsi_print_addr(ecb->xs->sc_link); 2264 printf("ncr53c9x_abort: not NEXUS\n"); 2265 ncr53c9x_init(sc, 1); 2266 } 2267 /* 2268 * Just leave the command on the nexus list. 2269 * XXX - what choice do we have but to reset the SCSI 2270 * eventually? 2271 */ 2272 if (sc->sc_state == NCR_IDLE) 2273 ncr53c9x_sched(sc); 2274 } 2275 } 2276 2277 void 2278 ncr53c9x_timeout(arg) 2279 void *arg; 2280 { 2281 struct ncr53c9x_ecb *ecb = arg; 2282 struct scsipi_xfer *xs = ecb->xs; 2283 struct scsipi_link *sc_link = xs->sc_link; 2284 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 2285 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 2286 int s; 2287 2288 scsi_print_addr(sc_link); 2289 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 2290 "<state %d, nexus %p, phase(l %x, c %x, p %x), resid %lx, " 2291 "msg(q %x,o %x) %s>", 2292 sc->sc_dev.dv_xname, 2293 ecb, ecb->flags, ecb->dleft, ecb->stat, 2294 sc->sc_state, sc->sc_nexus, 2295 NCR_READ_REG(sc, NCR_STAT), 2296 sc->sc_phase, sc->sc_prevphase, 2297 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2298 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2299 #if NCR53C9X_DEBUG > 1 2300 printf("TRACE: %s.", ecb->trace); 2301 #endif 2302 2303 s = splbio(); 2304 2305 if (ecb->flags & ECB_ABORT) { 2306 /* abort timed out */ 2307 printf(" AGAIN\n"); 2308 2309 ncr53c9x_init(sc, 1); 2310 } else { 2311 /* abort the operation that has timed out */ 2312 printf("\n"); 2313 xs->error = XS_TIMEOUT; 2314 ncr53c9x_abort(sc, ecb); 2315 2316 /* Disable sync mode if stuck in a data phase */ 2317 if (ecb == sc->sc_nexus && 2318 (ti->flags & T_SYNCMODE) != 0 && 2319 (sc->sc_phase & (MSGI|CDI)) == 0) { 2320 scsi_print_addr(sc_link); 2321 printf("sync negotiation disabled\n"); 2322 sc->sc_cfflags |= (1<<(sc_link->scsipi_scsi.target+8)); 2323 } 2324 } 2325 2326 splx(s); 2327 } 2328
Indexes created Mon Sep 29 21:09:56 GMT 2025