ncr53c9x.c revision 1.7
1 /* $NetBSD: ncr53c9x.c,v 1.7 1997/04/01 22:10:04 gwr Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 90 #include <dev/ic/ncr53c9xreg.h> 91 #include <dev/ic/ncr53c9xvar.h> 92 93 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 94 95 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 96 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 97 struct ncr53c9x_ecb *)); 98 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 99 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 100 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 101 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 102 struct scsi_xfer *, int)); 103 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 104 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 105 struct ncr53c9x_ecb *)); 106 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 107 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 108 /*static*/ void ncr53c9x_timeout __P((void *arg)); 109 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 110 struct ncr53c9x_ecb *)); 111 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 112 struct ncr53c9x_ecb *)); 113 114 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 115 struct ncr53c9x_ecb *)); 116 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 117 struct ncr53c9x_ecb *, int)); 118 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 119 120 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 121 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 122 struct ncr53c9x_tinfo *)); 123 124 /* 125 * Names for the NCR53c9x variants, correspnding to the variant tags 126 * in ncr53c9xvar.h. 127 */ 128 const char *ncr53c9x_variant_names[] = { 129 "ESP100", 130 "ESP100A", 131 "ESP200", 132 "NCR53C94", 133 "NCR53C96", 134 }; 135 136 /* 137 * Attach this instance, and then all the sub-devices 138 */ 139 void 140 ncr53c9x_attach(sc, adapter, dev) 141 struct ncr53c9x_softc *sc; 142 struct scsi_adapter *adapter; 143 struct scsi_device *dev; 144 { 145 146 /* 147 * Note, the front-end has set us up to print the chip variation. 148 */ 149 150 if (sc->sc_rev >= NCR_VARIANT_MAX) { 151 printf("\n%s: unknown variant %d, devices not attached\n", 152 sc->sc_dev.dv_xname, sc->sc_rev); 153 return; 154 } 155 156 printf(": %s, %dMHz, SCSI ID %d\n", 157 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 158 159 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 160 161 /* The value *must not* be == 1. Make it 2 */ 162 if (sc->sc_ccf == 1) 163 sc->sc_ccf = 2; 164 165 /* 166 * The recommended timeout is 250ms. This register is loaded 167 * with a value calculated as follows, from the docs: 168 * 169 * (timout period) x (CLK frequency) 170 * reg = ------------------------------------- 171 * 8192 x (Clock Conversion Factor) 172 * 173 * Since CCF has a linear relation to CLK, this generally computes 174 * to the constant of 153. 175 */ 176 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 177 178 /* CCF register only has 3 bits; 0 is actually 8 */ 179 sc->sc_ccf &= 7; 180 181 /* Reset state & bus */ 182 sc->sc_state = 0; 183 ncr53c9x_init(sc, 1); 184 185 /* 186 * fill in the prototype scsi_link. 187 */ 188 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 189 sc->sc_link.adapter_softc = sc; 190 sc->sc_link.adapter_target = sc->sc_id; 191 sc->sc_link.adapter = adapter; 192 sc->sc_link.device = dev; 193 sc->sc_link.openings = 2; 194 sc->sc_link.max_target = 7; 195 196 /* 197 * Now try to attach all the sub-devices 198 */ 199 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 200 } 201 202 /* 203 * This is the generic esp reset function. It does not reset the SCSI bus, 204 * only this controllers, but kills any on-going commands, and also stops 205 * and resets the DMA. 206 * 207 * After reset, registers are loaded with the defaults from the attach 208 * routine above. 209 */ 210 void 211 ncr53c9x_reset(sc) 212 struct ncr53c9x_softc *sc; 213 { 214 215 /* reset DMA first */ 216 NCRDMA_RESET(sc); 217 218 /* reset SCSI chip */ 219 NCRCMD(sc, NCRCMD_RSTCHIP); 220 NCRCMD(sc, NCRCMD_NOP); 221 DELAY(500); 222 223 /* do these backwards, and fall through */ 224 switch (sc->sc_rev) { 225 case NCR_VARIANT_NCR53C94: 226 case NCR_VARIANT_NCR53C96: 227 case NCR_VARIANT_ESP200: 228 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 229 case NCR_VARIANT_ESP100A: 230 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 231 case NCR_VARIANT_ESP100: 232 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 233 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 234 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 235 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 236 break; 237 default: 238 printf("%s: unknown revision code, assuming ESP100\n", 239 sc->sc_dev.dv_xname); 240 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 241 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 242 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 243 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 244 } 245 } 246 247 /* 248 * Reset the SCSI bus, but not the chip 249 */ 250 void 251 ncr53c9x_scsi_reset(sc) 252 struct ncr53c9x_softc *sc; 253 { 254 255 (*sc->sc_glue->gl_dma_stop)(sc); 256 257 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 258 NCRCMD(sc, NCRCMD_RSTSCSI); 259 } 260 261 /* 262 * Initialize esp state machine 263 */ 264 void 265 ncr53c9x_init(sc, doreset) 266 struct ncr53c9x_softc *sc; 267 int doreset; 268 { 269 struct ncr53c9x_ecb *ecb; 270 int r; 271 272 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 273 274 if (sc->sc_state == 0) { 275 /* First time through; initialize. */ 276 TAILQ_INIT(&sc->ready_list); 277 TAILQ_INIT(&sc->nexus_list); 278 TAILQ_INIT(&sc->free_list); 279 sc->sc_nexus = NULL; 280 ecb = sc->sc_ecb; 281 bzero(ecb, sizeof(sc->sc_ecb)); 282 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 283 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 284 ecb++; 285 } 286 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 287 } else { 288 /* Cancel any active commands. */ 289 sc->sc_state = NCR_CLEANING; 290 if ((ecb = sc->sc_nexus) != NULL) { 291 ecb->xs->error = XS_DRIVER_STUFFUP; 292 ncr53c9x_done(sc, ecb); 293 } 294 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 295 ecb->xs->error = XS_DRIVER_STUFFUP; 296 ncr53c9x_done(sc, ecb); 297 } 298 } 299 300 /* 301 * reset the chip to a known state 302 */ 303 ncr53c9x_reset(sc); 304 305 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 306 for (r = 0; r < 8; r++) { 307 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 308 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 309 int fl = sc->sc_dev.dv_cfdata->cf_flags; 310 311 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 312 ? T_NEGOTIATE : 0) | 313 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 314 T_NEED_TO_RESET; 315 ti->period = sc->sc_minsync; 316 ti->offset = 0; 317 } 318 319 if (doreset) { 320 sc->sc_state = NCR_SBR; 321 NCRCMD(sc, NCRCMD_RSTSCSI); 322 } else { 323 sc->sc_state = NCR_IDLE; 324 } 325 } 326 327 /* 328 * Read the NCR registers, and save their contents for later use. 329 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 330 * NCR_INTR - so make sure it is the last read. 331 * 332 * I think that (from reading the docs) most bits in these registers 333 * only make sense when he DMA CSR has an interrupt showing. Call only 334 * if an interrupt is pending. 335 */ 336 void 337 ncr53c9x_readregs(sc) 338 struct ncr53c9x_softc *sc; 339 { 340 341 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 342 /* Only the stepo bits are of interest */ 343 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 344 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 345 346 if (sc->sc_glue->gl_clear_latched_intr != NULL) 347 (*sc->sc_glue->gl_clear_latched_intr)(sc); 348 349 /* 350 * Determine the SCSI bus phase, return either a real SCSI bus phase 351 * or some pseudo phase we use to detect certain exceptions. 352 */ 353 354 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 355 ? /* Disconnected */ BUSFREE_PHASE 356 : sc->sc_espstat & NCRSTAT_PHASE; 357 358 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 359 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 360 } 361 362 /* 363 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 364 */ 365 static inline int 366 ncr53c9x_stp2cpb(sc, period) 367 struct ncr53c9x_softc *sc; 368 int period; 369 { 370 int v; 371 v = (sc->sc_freq * period) / 250; 372 if (ncr53c9x_cpb2stp(sc, v) < period) 373 /* Correct round-down error */ 374 v++; 375 return v; 376 } 377 378 static inline void 379 ncr53c9x_setsync(sc, ti) 380 struct ncr53c9x_softc *sc; 381 struct ncr53c9x_tinfo *ti; 382 { 383 384 if (ti->flags & T_SYNCMODE) { 385 NCR_WRITE_REG(sc, NCR_SYNCOFF, ti->offset); 386 NCR_WRITE_REG(sc, NCR_SYNCTP, 387 ncr53c9x_stp2cpb(sc, ti->period)); 388 } else { 389 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 390 NCR_WRITE_REG(sc, NCR_SYNCTP, 0); 391 } 392 } 393 394 /* 395 * Send a command to a target, set the driver state to NCR_SELECTING 396 * and let the caller take care of the rest. 397 * 398 * Keeping this as a function allows me to say that this may be done 399 * by DMA instead of programmed I/O soon. 400 */ 401 void 402 ncr53c9x_select(sc, ecb) 403 struct ncr53c9x_softc *sc; 404 struct ncr53c9x_ecb *ecb; 405 { 406 struct scsi_link *sc_link = ecb->xs->sc_link; 407 int target = sc_link->target; 408 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 409 u_char *cmd; 410 int clen; 411 412 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 413 sc_link->target, sc_link->lun, ecb->cmd.opcode)); 414 415 /* new state NCR_SELECTING */ 416 sc->sc_state = NCR_SELECTING; 417 418 /* 419 * Schedule the timeout now, the first time we will go away 420 * expecting to come back due to an interrupt, because it is 421 * always possible that the interrupt may never happen. 422 */ 423 if ((ecb->xs->flags & SCSI_POLL) == 0) 424 timeout(ncr53c9x_timeout, ecb, 425 (ecb->timeout * hz) / 1000); 426 427 NCRCMD(sc, NCRCMD_FLUSH); 428 429 /* 430 * The docs say the target register is never reset, and I 431 * can't think of a better place to set it 432 */ 433 NCR_WRITE_REG(sc, NCR_SELID, target); 434 ncr53c9x_setsync(sc, ti); 435 436 /* 437 * Who am I. This is where we tell the target that we are 438 * happy for it to disconnect etc. 439 */ 440 NCR_WRITE_REG(sc, NCR_FIFO, 441 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 442 443 if (ti->flags & T_NEGOTIATE) { 444 /* Arbitrate, select and stop after IDENTIFY message */ 445 NCRCMD(sc, NCRCMD_SELATNS); 446 return; 447 } 448 449 /* Now the command into the FIFO */ 450 cmd = (u_char *)&ecb->cmd; 451 clen = ecb->clen; 452 while (clen--) 453 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 454 455 /* And get the targets attention */ 456 NCRCMD(sc, NCRCMD_SELATN); 457 } 458 459 void 460 ncr53c9x_free_ecb(sc, ecb, flags) 461 struct ncr53c9x_softc *sc; 462 struct ncr53c9x_ecb *ecb; 463 int flags; 464 { 465 int s; 466 467 s = splbio(); 468 469 ecb->flags = 0; 470 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 471 472 /* 473 * If there were none, wake anybody waiting for one to come free, 474 * starting with queued entries. 475 */ 476 if (ecb->chain.tqe_next == 0) 477 wakeup(&sc->free_list); 478 479 splx(s); 480 } 481 482 struct ncr53c9x_ecb * 483 ncr53c9x_get_ecb(sc, flags) 484 struct ncr53c9x_softc *sc; 485 int flags; 486 { 487 struct ncr53c9x_ecb *ecb; 488 int s; 489 490 s = splbio(); 491 492 while ((ecb = sc->free_list.tqh_first) == NULL && 493 (flags & SCSI_NOSLEEP) == 0) 494 tsleep(&sc->free_list, PRIBIO, "especb", 0); 495 if (ecb) { 496 TAILQ_REMOVE(&sc->free_list, ecb, chain); 497 ecb->flags |= ECB_ALLOC; 498 } 499 500 splx(s); 501 return ecb; 502 } 503 504 /* 505 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 506 */ 507 508 /* 509 * Start a SCSI-command 510 * This function is called by the higher level SCSI-driver to queue/run 511 * SCSI-commands. 512 */ 513 int 514 ncr53c9x_scsi_cmd(xs) 515 struct scsi_xfer *xs; 516 { 517 struct scsi_link *sc_link = xs->sc_link; 518 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 519 struct ncr53c9x_ecb *ecb; 520 int s, flags; 521 522 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 523 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 524 sc_link->target)); 525 526 flags = xs->flags; 527 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) { 528 xs->error = XS_DRIVER_STUFFUP; 529 return TRY_AGAIN_LATER; 530 } 531 532 /* Initialize ecb */ 533 ecb->xs = xs; 534 ecb->timeout = xs->timeout; 535 536 if (flags & SCSI_RESET) { 537 ecb->flags |= ECB_RESET; 538 ecb->clen = 0; 539 ecb->dleft = 0; 540 } else { 541 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 542 ecb->clen = xs->cmdlen; 543 ecb->daddr = xs->data; 544 ecb->dleft = xs->datalen; 545 } 546 ecb->stat = 0; 547 548 s = splbio(); 549 550 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 551 if (sc->sc_state == NCR_IDLE) 552 ncr53c9x_sched(sc); 553 554 splx(s); 555 556 if ((flags & SCSI_POLL) == 0) 557 return SUCCESSFULLY_QUEUED; 558 559 /* Not allowed to use interrupts, use polling instead */ 560 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 561 ncr53c9x_timeout(ecb); 562 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 563 ncr53c9x_timeout(ecb); 564 } 565 return COMPLETE; 566 } 567 568 /* 569 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 570 */ 571 int 572 ncr53c9x_poll(sc, xs, count) 573 struct ncr53c9x_softc *sc; 574 struct scsi_xfer *xs; 575 int count; 576 { 577 578 NCR_TRACE(("[ncr53c9x_poll] ")); 579 while (count) { 580 if (NCRDMA_ISINTR(sc)) { 581 ncr53c9x_intr(sc); 582 } 583 #if alternatively 584 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 585 ncr53c9x_intr(sc); 586 #endif 587 if ((xs->flags & ITSDONE) != 0) 588 return 0; 589 if (sc->sc_state == NCR_IDLE) { 590 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 591 ncr53c9x_sched(sc); 592 } 593 DELAY(1000); 594 count--; 595 } 596 return 1; 597 } 598 599 600 /* 601 * LOW LEVEL SCSI UTILITIES 602 */ 603 604 /* 605 * Schedule a scsi operation. This has now been pulled out of the interrupt 606 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 607 * This may save us an unecessary interrupt just to get things going. 608 * Should only be called when state == NCR_IDLE and at bio pl. 609 */ 610 void 611 ncr53c9x_sched(sc) 612 struct ncr53c9x_softc *sc; 613 { 614 struct ncr53c9x_ecb *ecb; 615 struct scsi_link *sc_link; 616 struct ncr53c9x_tinfo *ti; 617 618 NCR_TRACE(("[ncr53c9x_sched] ")); 619 if (sc->sc_state != NCR_IDLE) 620 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 621 622 /* 623 * Find first ecb in ready queue that is for a target/lunit 624 * combinations that is not busy. 625 */ 626 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 627 sc_link = ecb->xs->sc_link; 628 ti = &sc->sc_tinfo[sc_link->target]; 629 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 630 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 631 sc->sc_nexus = ecb; 632 ncr53c9x_select(sc, ecb); 633 break; 634 } else 635 NCR_MISC(("%d:%d busy\n", 636 sc_link->target, sc_link->lun)); 637 } 638 } 639 640 void 641 ncr53c9x_sense(sc, ecb) 642 struct ncr53c9x_softc *sc; 643 struct ncr53c9x_ecb *ecb; 644 { 645 struct scsi_xfer *xs = ecb->xs; 646 struct scsi_link *sc_link = xs->sc_link; 647 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 648 struct scsi_sense *ss = (void *)&ecb->cmd; 649 650 NCR_MISC(("requesting sense ")); 651 /* Next, setup a request sense command block */ 652 bzero(ss, sizeof(*ss)); 653 ss->opcode = REQUEST_SENSE; 654 ss->byte2 = sc_link->lun << 5; 655 ss->length = sizeof(struct scsi_sense_data); 656 ecb->clen = sizeof(*ss); 657 ecb->daddr = (char *)&xs->sense; 658 ecb->dleft = sizeof(struct scsi_sense_data); 659 ecb->flags |= ECB_SENSE; 660 ecb->timeout = NCR_SENSE_TIMEOUT; 661 ti->senses++; 662 if (ecb->flags & ECB_NEXUS) 663 ti->lubusy &= ~(1 << sc_link->lun); 664 if (ecb == sc->sc_nexus) { 665 ncr53c9x_select(sc, ecb); 666 } else { 667 ncr53c9x_dequeue(sc, ecb); 668 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 669 if (sc->sc_state == NCR_IDLE) 670 ncr53c9x_sched(sc); 671 } 672 } 673 674 /* 675 * POST PROCESSING OF SCSI_CMD (usually current) 676 */ 677 void 678 ncr53c9x_done(sc, ecb) 679 struct ncr53c9x_softc *sc; 680 struct ncr53c9x_ecb *ecb; 681 { 682 struct scsi_xfer *xs = ecb->xs; 683 struct scsi_link *sc_link = xs->sc_link; 684 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 685 686 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 687 688 untimeout(ncr53c9x_timeout, ecb); 689 690 /* 691 * Now, if we've come here with no error code, i.e. we've kept the 692 * initial XS_NOERROR, and the status code signals that we should 693 * check sense, we'll need to set up a request sense cmd block and 694 * push the command back into the ready queue *before* any other 695 * commands for this target/lunit, else we lose the sense info. 696 * We don't support chk sense conditions for the request sense cmd. 697 */ 698 if (xs->error == XS_NOERROR) { 699 if ((ecb->flags & ECB_ABORT) != 0) { 700 xs->error = XS_DRIVER_STUFFUP; 701 } else if ((ecb->flags & ECB_SENSE) != 0) { 702 xs->error = XS_SENSE; 703 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 704 /* First, save the return values */ 705 xs->resid = ecb->dleft; 706 xs->status = ecb->stat; 707 ncr53c9x_sense(sc, ecb); 708 return; 709 } else { 710 xs->resid = ecb->dleft; 711 } 712 } 713 714 xs->flags |= ITSDONE; 715 716 #ifdef NCR53C9X_DEBUG 717 if (ncr53c9x_debug & NCR_SHOWMISC) { 718 if (xs->resid != 0) 719 printf("resid=%d ", xs->resid); 720 if (xs->error == XS_SENSE) 721 printf("sense=0x%02x\n", xs->sense.error_code); 722 else 723 printf("error=%d\n", xs->error); 724 } 725 #endif 726 727 /* 728 * Remove the ECB from whatever queue it's on. 729 */ 730 if (ecb->flags & ECB_NEXUS) 731 ti->lubusy &= ~(1 << sc_link->lun); 732 if (ecb == sc->sc_nexus) { 733 sc->sc_nexus = NULL; 734 sc->sc_state = NCR_IDLE; 735 ncr53c9x_sched(sc); 736 } else 737 ncr53c9x_dequeue(sc, ecb); 738 739 ncr53c9x_free_ecb(sc, ecb, xs->flags); 740 ti->cmds++; 741 scsi_done(xs); 742 } 743 744 void 745 ncr53c9x_dequeue(sc, ecb) 746 struct ncr53c9x_softc *sc; 747 struct ncr53c9x_ecb *ecb; 748 { 749 750 if (ecb->flags & ECB_NEXUS) { 751 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 752 } else { 753 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 754 } 755 } 756 757 /* 758 * INTERRUPT/PROTOCOL ENGINE 759 */ 760 761 /* 762 * Schedule an outgoing message by prioritizing it, and asserting 763 * attention on the bus. We can only do this when we are the initiator 764 * else there will be an illegal command interrupt. 765 */ 766 #define ncr53c9x_sched_msgout(m) \ 767 do { \ 768 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 769 NCRCMD(sc, NCRCMD_SETATN); \ 770 sc->sc_flags |= NCR_ATN; \ 771 sc->sc_msgpriq |= (m); \ 772 } while (0) 773 774 int 775 ncr53c9x_reselect(sc, message) 776 struct ncr53c9x_softc *sc; 777 int message; 778 { 779 u_char selid, target, lun; 780 struct ncr53c9x_ecb *ecb; 781 struct scsi_link *sc_link; 782 struct ncr53c9x_tinfo *ti; 783 784 /* 785 * The SCSI chip made a snapshot of the data bus while the reselection 786 * was being negotiated. This enables us to determine which target did 787 * the reselect. 788 */ 789 selid = sc->sc_selid & ~(1 << sc->sc_id); 790 if (selid & (selid - 1)) { 791 printf("%s: reselect with invalid selid %02x;" 792 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 793 goto reset; 794 } 795 796 /* 797 * Search wait queue for disconnected cmd 798 * The list should be short, so I haven't bothered with 799 * any more sophisticated structures than a simple 800 * singly linked list. 801 */ 802 target = ffs(selid) - 1; 803 lun = message & 0x07; 804 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 805 ecb = ecb->chain.tqe_next) { 806 sc_link = ecb->xs->sc_link; 807 if (sc_link->target == target && sc_link->lun == lun) 808 break; 809 } 810 if (ecb == NULL) { 811 printf("%s: reselect from target %d lun %d with no nexus;" 812 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 813 goto abort; 814 } 815 816 /* Make this nexus active again. */ 817 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 818 sc->sc_state = NCR_CONNECTED; 819 sc->sc_nexus = ecb; 820 ti = &sc->sc_tinfo[target]; 821 ti->lubusy |= (1 << lun); 822 ncr53c9x_setsync(sc, ti); 823 824 if (ecb->flags & ECB_RESET) 825 ncr53c9x_sched_msgout(SEND_DEV_RESET); 826 else if (ecb->flags & ECB_ABORT) 827 ncr53c9x_sched_msgout(SEND_ABORT); 828 829 /* Do an implicit RESTORE POINTERS. */ 830 sc->sc_dp = ecb->daddr; 831 sc->sc_dleft = ecb->dleft; 832 833 return (0); 834 835 reset: 836 ncr53c9x_sched_msgout(SEND_DEV_RESET); 837 return (1); 838 839 abort: 840 ncr53c9x_sched_msgout(SEND_ABORT); 841 return (1); 842 } 843 844 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 845 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 846 #define ISEXTMSG(m) ((m) == 1) 847 848 /* 849 * Get an incoming message as initiator. 850 * 851 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 852 * byte in the FIFO 853 */ 854 void 855 ncr53c9x_msgin(sc) 856 register struct ncr53c9x_softc *sc; 857 { 858 register int v; 859 860 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 861 862 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 863 printf("%s: msgin: no msg byte available\n", 864 sc->sc_dev.dv_xname); 865 return; 866 } 867 868 /* 869 * Prepare for a new message. A message should (according 870 * to the SCSI standard) be transmitted in one single 871 * MESSAGE_IN_PHASE. If we have been in some other phase, 872 * then this is a new message. 873 */ 874 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 875 sc->sc_flags &= ~NCR_DROP_MSGI; 876 sc->sc_imlen = 0; 877 } 878 879 v = NCR_READ_REG(sc, NCR_FIFO); 880 NCR_MISC(("<msgbyte:0x%02x>", v)); 881 882 #if 0 883 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 884 /* 885 * Which target is reselecting us? (The ID bit really) 886 */ 887 sc->sc_selid = v; 888 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 889 return; 890 } 891 #endif 892 893 sc->sc_imess[sc->sc_imlen] = v; 894 895 /* 896 * If we're going to reject the message, don't bother storing 897 * the incoming bytes. But still, we need to ACK them. 898 */ 899 900 if ((sc->sc_flags & NCR_DROP_MSGI)) { 901 NCRCMD(sc, NCRCMD_MSGOK); 902 printf("<dropping msg byte %x>", 903 sc->sc_imess[sc->sc_imlen]); 904 return; 905 } 906 907 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 908 ncr53c9x_sched_msgout(SEND_REJECT); 909 sc->sc_flags |= NCR_DROP_MSGI; 910 } else { 911 sc->sc_imlen++; 912 /* 913 * This testing is suboptimal, but most 914 * messages will be of the one byte variety, so 915 * it should not effect performance 916 * significantly. 917 */ 918 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 919 goto gotit; 920 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 921 goto gotit; 922 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 923 sc->sc_imlen == sc->sc_imess[1] + 2) 924 goto gotit; 925 } 926 /* Ack what we have so far */ 927 NCRCMD(sc, NCRCMD_MSGOK); 928 return; 929 930 gotit: 931 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 932 /* 933 * Now we should have a complete message (1 byte, 2 byte 934 * and moderately long extended messages). We only handle 935 * extended messages which total length is shorter than 936 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 937 */ 938 switch (sc->sc_state) { 939 struct ncr53c9x_ecb *ecb; 940 struct ncr53c9x_tinfo *ti; 941 942 case NCR_CONNECTED: 943 ecb = sc->sc_nexus; 944 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 945 946 switch (sc->sc_imess[0]) { 947 case MSG_CMDCOMPLETE: 948 NCR_MSGS(("cmdcomplete ")); 949 if (sc->sc_dleft < 0) { 950 struct scsi_link *sc_link = ecb->xs->sc_link; 951 printf("%s: %ld extra bytes from %d:%d\n", 952 sc->sc_dev.dv_xname, -(long)sc->sc_dleft, 953 sc_link->target, sc_link->lun); 954 sc->sc_dleft = 0; 955 } 956 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 957 sc->sc_state = NCR_CMDCOMPLETE; 958 break; 959 960 case MSG_MESSAGE_REJECT: 961 if (ncr53c9x_debug & NCR_SHOWMSGS) 962 printf("%s: our msg rejected by target\n", 963 sc->sc_dev.dv_xname); 964 switch (sc->sc_msgout) { 965 case SEND_SDTR: 966 sc->sc_flags &= ~NCR_SYNCHNEGO; 967 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 968 ncr53c9x_setsync(sc, ti); 969 break; 970 case SEND_INIT_DET_ERR: 971 goto abort; 972 } 973 break; 974 975 case MSG_NOOP: 976 NCR_MSGS(("noop ")); 977 break; 978 979 case MSG_DISCONNECT: 980 NCR_MSGS(("disconnect ")); 981 ti->dconns++; 982 sc->sc_state = NCR_DISCONNECT; 983 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 984 break; 985 /*FALLTHROUGH*/ 986 987 case MSG_SAVEDATAPOINTER: 988 NCR_MSGS(("save datapointer ")); 989 ecb->daddr = sc->sc_dp; 990 ecb->dleft = sc->sc_dleft; 991 break; 992 993 case MSG_RESTOREPOINTERS: 994 NCR_MSGS(("restore datapointer ")); 995 sc->sc_dp = ecb->daddr; 996 sc->sc_dleft = ecb->dleft; 997 break; 998 999 case MSG_EXTENDED: 1000 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1001 switch (sc->sc_imess[2]) { 1002 case MSG_EXT_SDTR: 1003 NCR_MSGS(("SDTR period %d, offset %d ", 1004 sc->sc_imess[3], sc->sc_imess[4])); 1005 if (sc->sc_imess[1] != 3) 1006 goto reject; 1007 ti->period = sc->sc_imess[3]; 1008 ti->offset = sc->sc_imess[4]; 1009 ti->flags &= ~T_NEGOTIATE; 1010 if (sc->sc_minsync == 0 || 1011 ti->offset == 0 || 1012 ti->period > 124) { 1013 printf("%s:%d: async\n", "esp", 1014 ecb->xs->sc_link->target); 1015 if ((sc->sc_flags&NCR_SYNCHNEGO) 1016 == 0) { 1017 /* 1018 * target initiated negotiation 1019 */ 1020 ti->offset = 0; 1021 ti->flags &= ~T_SYNCMODE; 1022 ncr53c9x_sched_msgout( 1023 SEND_SDTR); 1024 } else { 1025 /* we are async */ 1026 ti->flags &= ~T_SYNCMODE; 1027 } 1028 } else { 1029 int r = 250/ti->period; 1030 int s = (100*250)/ti->period - 100*r; 1031 int p; 1032 1033 p = ncr53c9x_stp2cpb(sc, ti->period); 1034 ti->period = ncr53c9x_cpb2stp(sc, p); 1035 #ifdef NCR53C9X_DEBUG 1036 sc_print_addr(ecb->xs->sc_link); 1037 printf("max sync rate %d.%02dMb/s\n", 1038 r, s); 1039 #endif 1040 if ((sc->sc_flags&NCR_SYNCHNEGO) 1041 == 0) { 1042 /* 1043 * target initiated negotiation 1044 */ 1045 if (ti->period < 1046 sc->sc_minsync) 1047 ti->period = 1048 sc->sc_minsync; 1049 if (ti->offset > 15) 1050 ti->offset = 15; 1051 ti->flags &= ~T_SYNCMODE; 1052 ncr53c9x_sched_msgout( 1053 SEND_SDTR); 1054 } else { 1055 /* we are sync */ 1056 ti->flags |= T_SYNCMODE; 1057 } 1058 } 1059 sc->sc_flags &= ~NCR_SYNCHNEGO; 1060 ncr53c9x_setsync(sc, ti); 1061 break; 1062 1063 default: 1064 printf("%s: unrecognized MESSAGE EXTENDED;" 1065 " sending REJECT\n", sc->sc_dev.dv_xname); 1066 goto reject; 1067 } 1068 break; 1069 1070 default: 1071 NCR_MSGS(("ident ")); 1072 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1073 sc->sc_dev.dv_xname); 1074 reject: 1075 ncr53c9x_sched_msgout(SEND_REJECT); 1076 break; 1077 } 1078 break; 1079 1080 case NCR_RESELECTED: 1081 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1082 printf("%s: reselect without IDENTIFY;" 1083 " sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1084 goto reset; 1085 } 1086 1087 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1088 break; 1089 1090 default: 1091 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1092 sc->sc_dev.dv_xname); 1093 reset: 1094 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1095 break; 1096 1097 abort: 1098 ncr53c9x_sched_msgout(SEND_ABORT); 1099 break; 1100 } 1101 1102 /* Ack last message byte */ 1103 NCRCMD(sc, NCRCMD_MSGOK); 1104 1105 /* Done, reset message pointer. */ 1106 sc->sc_flags &= ~NCR_DROP_MSGI; 1107 sc->sc_imlen = 0; 1108 } 1109 1110 1111 /* 1112 * Send the highest priority, scheduled message 1113 */ 1114 void 1115 ncr53c9x_msgout(sc) 1116 register struct ncr53c9x_softc *sc; 1117 { 1118 struct ncr53c9x_tinfo *ti; 1119 struct ncr53c9x_ecb *ecb; 1120 size_t size; 1121 1122 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1123 sc->sc_msgpriq, sc->sc_prevphase)); 1124 1125 if (sc->sc_flags & NCR_ATN) { 1126 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1127 new: 1128 NCRCMD(sc, NCRCMD_FLUSH); 1129 DELAY(1); 1130 sc->sc_msgoutq = 0; 1131 sc->sc_omlen = 0; 1132 } 1133 } else { 1134 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1135 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1136 goto new; 1137 } else { 1138 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1139 sc->sc_dev.dv_xname, __LINE__); 1140 } 1141 } 1142 1143 if (sc->sc_omlen == 0) { 1144 /* Pick up highest priority message */ 1145 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1146 sc->sc_msgoutq |= sc->sc_msgout; 1147 sc->sc_msgpriq &= ~sc->sc_msgout; 1148 sc->sc_omlen = 1; /* "Default" message len */ 1149 switch (sc->sc_msgout) { 1150 case SEND_SDTR: 1151 ecb = sc->sc_nexus; 1152 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1153 sc->sc_omess[0] = MSG_EXTENDED; 1154 sc->sc_omess[1] = 3; 1155 sc->sc_omess[2] = MSG_EXT_SDTR; 1156 sc->sc_omess[3] = ti->period; 1157 sc->sc_omess[4] = ti->offset; 1158 sc->sc_omlen = 5; 1159 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1160 ti->flags |= T_SYNCMODE; 1161 ncr53c9x_setsync(sc, ti); 1162 } 1163 break; 1164 case SEND_IDENTIFY: 1165 if (sc->sc_state != NCR_CONNECTED) { 1166 printf("%s at line %d: no nexus\n", 1167 sc->sc_dev.dv_xname, __LINE__); 1168 } 1169 ecb = sc->sc_nexus; 1170 sc->sc_omess[0] = 1171 MSG_IDENTIFY(ecb->xs->sc_link->lun, 0); 1172 break; 1173 case SEND_DEV_RESET: 1174 sc->sc_flags |= NCR_ABORTING; 1175 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1176 ecb = sc->sc_nexus; 1177 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1178 ti->flags &= ~T_SYNCMODE; 1179 ti->flags |= T_NEGOTIATE; 1180 break; 1181 case SEND_PARITY_ERROR: 1182 sc->sc_omess[0] = MSG_PARITY_ERROR; 1183 break; 1184 case SEND_ABORT: 1185 sc->sc_flags |= NCR_ABORTING; 1186 sc->sc_omess[0] = MSG_ABORT; 1187 break; 1188 case SEND_INIT_DET_ERR: 1189 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1190 break; 1191 case SEND_REJECT: 1192 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1193 break; 1194 default: 1195 NCRCMD(sc, NCRCMD_RSTATN); 1196 sc->sc_flags &= ~NCR_ATN; 1197 sc->sc_omess[0] = MSG_NOOP; 1198 break; 1199 } 1200 sc->sc_omp = sc->sc_omess; 1201 } 1202 1203 #if 1 1204 /* (re)send the message */ 1205 size = min(sc->sc_omlen, sc->sc_maxxfer); 1206 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1207 /* Program the SCSI counter */ 1208 NCR_WRITE_REG(sc, NCR_TCL, size); 1209 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1210 if (sc->sc_cfg2 & NCRCFG2_FE) { 1211 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1212 } 1213 /* load the count in */ 1214 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1215 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1216 NCRDMA_GO(sc); 1217 #else 1218 { int i; 1219 for (i = 0; i < sc->sc_omlen; i++) 1220 NCR_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1221 NCRCMD(sc, NCRCMD_TRANS); 1222 sc->sc_omlen = 0; 1223 } 1224 #endif 1225 } 1226 1227 /* 1228 * This is the most critical part of the driver, and has to know 1229 * how to deal with *all* error conditions and phases from the SCSI 1230 * bus. If there are no errors and the DMA was active, then call the 1231 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1232 * and we can return from here without further processing. 1233 * 1234 * Most of this needs verifying. 1235 */ 1236 int 1237 ncr53c9x_intr(sc) 1238 register struct ncr53c9x_softc *sc; 1239 { 1240 register struct ncr53c9x_ecb *ecb; 1241 register struct scsi_link *sc_link; 1242 struct ncr53c9x_tinfo *ti; 1243 int loop; 1244 size_t size; 1245 int nfifo; 1246 1247 NCR_TRACE(("[ncr53c9x_intr]")); 1248 1249 /* 1250 * I have made some (maybe seriously flawed) assumptions here, 1251 * but basic testing (uncomment the printf() below), show that 1252 * certainly something happens when this loop is here. 1253 * 1254 * The idea is that many of the SCSI operations take very little 1255 * time, and going away and getting interrupted is too high an 1256 * overhead to pay. For example, selecting, sending a message 1257 * and command and then doing some work can be done in one "pass". 1258 * 1259 * The DELAY is not variable because I do not understand that the 1260 * DELAY loop should be fixed-time regardless of CPU speed, but 1261 * I am *assuming* that the faster SCSI processors get things done 1262 * quicker (sending a command byte etc), and so there is no 1263 * need to be too slow. 1264 * 1265 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1266 * at 40Mhz. This needs testing. 1267 */ 1268 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1269 /* a feeling of deja-vu */ 1270 if (!NCRDMA_ISINTR(sc)) 1271 return (loop != 0); 1272 #if 0 1273 if (loop) 1274 printf("*"); 1275 #endif 1276 1277 /* and what do the registers say... */ 1278 ncr53c9x_readregs(sc); 1279 1280 sc->sc_intrcnt.ev_count++; 1281 1282 /* 1283 * At the moment, only a SCSI Bus Reset or Illegal 1284 * Command are classed as errors. A disconnect is a 1285 * valid condition, and we let the code check is the 1286 * "NCR_BUSFREE_OK" flag was set before declaring it 1287 * and error. 1288 * 1289 * Also, the status register tells us about "Gross 1290 * Errors" and "Parity errors". Only the Gross Error 1291 * is really bad, and the parity errors are dealt 1292 * with later 1293 * 1294 * TODO 1295 * If there are too many parity error, go to slow 1296 * cable mode ? 1297 */ 1298 1299 /* SCSI Reset */ 1300 if (sc->sc_espintr & NCRINTR_SBR) { 1301 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1302 NCRCMD(sc, NCRCMD_FLUSH); 1303 DELAY(1); 1304 } 1305 if (sc->sc_state != NCR_SBR) { 1306 printf("%s: SCSI bus reset\n", 1307 sc->sc_dev.dv_xname); 1308 ncr53c9x_init(sc, 0); /* Restart everything */ 1309 return 1; 1310 } 1311 #if 0 1312 /*XXX*/ printf("<expected bus reset: " 1313 "[intr %x, stat %x, step %d]>\n", 1314 sc->sc_espintr, sc->sc_espstat, 1315 sc->sc_espstep); 1316 #endif 1317 if (sc->sc_nexus) 1318 panic("%s: nexus in reset state", 1319 sc->sc_dev.dv_xname); 1320 goto sched; 1321 } 1322 1323 ecb = sc->sc_nexus; 1324 1325 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1326 if (sc->sc_espintr & NCRINTR_ERR || 1327 sc->sc_espstat & NCRSTAT_GE) { 1328 1329 if (sc->sc_espstat & NCRSTAT_GE) { 1330 /* no target ? */ 1331 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1332 NCRCMD(sc, NCRCMD_FLUSH); 1333 DELAY(1); 1334 } 1335 if (sc->sc_state == NCR_CONNECTED || 1336 sc->sc_state == NCR_SELECTING) { 1337 ecb->xs->error = XS_DRIVER_STUFFUP; 1338 ncr53c9x_done(sc, ecb); 1339 } 1340 return 1; 1341 } 1342 1343 if (sc->sc_espintr & NCRINTR_ILL) { 1344 /* illegal command, out of sync ? */ 1345 printf("%s: illegal command: 0x%x " 1346 "(state %d, phase %x, prevphase %x)\n", 1347 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1348 sc->sc_state, sc->sc_phase, 1349 sc->sc_prevphase); 1350 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1351 NCRCMD(sc, NCRCMD_FLUSH); 1352 DELAY(1); 1353 } 1354 ncr53c9x_init(sc, 0); /* Restart everything */ 1355 return 1; 1356 } 1357 } 1358 1359 /* 1360 * Call if DMA is active. 1361 * 1362 * If DMA_INTR returns true, then maybe go 'round the loop 1363 * again in case there is no more DMA queued, but a phase 1364 * change is expected. 1365 */ 1366 if (NCRDMA_ISACTIVE(sc)) { 1367 int r = NCRDMA_INTR(sc); 1368 if (r == -1) { 1369 printf("%s: DMA error; resetting\n", 1370 sc->sc_dev.dv_xname); 1371 ncr53c9x_init(sc, 1); 1372 } 1373 /* If DMA active here, then go back to work... */ 1374 if (NCRDMA_ISACTIVE(sc)) 1375 return 1; 1376 1377 if (sc->sc_dleft == 0 && 1378 (sc->sc_espstat & NCRSTAT_TC) == 0) 1379 printf("%s: !TC [intr %x, stat %x, step %d]" 1380 " prevphase %x, resid %x\n", 1381 sc->sc_dev.dv_xname, 1382 sc->sc_espintr, 1383 sc->sc_espstat, 1384 sc->sc_espstep, 1385 sc->sc_prevphase, 1386 ecb?ecb->dleft:-1); 1387 } 1388 1389 #if 0 /* Unreliable on some NCR revisions? */ 1390 if ((sc->sc_espstat & NCRSTAT_INT) == 0) { 1391 printf("%s: spurious interrupt\n", 1392 sc->sc_dev.dv_xname); 1393 return 1; 1394 } 1395 #endif 1396 1397 /* 1398 * check for less serious errors 1399 */ 1400 if (sc->sc_espstat & NCRSTAT_PE) { 1401 printf("%s: SCSI bus parity error\n", 1402 sc->sc_dev.dv_xname); 1403 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1404 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1405 else 1406 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1407 } 1408 1409 if (sc->sc_espintr & NCRINTR_DIS) { 1410 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1411 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1412 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1413 NCRCMD(sc, NCRCMD_FLUSH); 1414 DELAY(1); 1415 } 1416 /* 1417 * This command must (apparently) be issued within 1418 * 250mS of a disconnect. So here you are... 1419 */ 1420 NCRCMD(sc, NCRCMD_ENSEL); 1421 switch (sc->sc_state) { 1422 case NCR_RESELECTED: 1423 goto sched; 1424 1425 case NCR_SELECTING: 1426 ecb->xs->error = XS_SELTIMEOUT; 1427 goto finish; 1428 1429 case NCR_CONNECTED: 1430 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1431 #ifdef NCR53C9X_DEBUG 1432 if (ecb) 1433 sc_print_addr(ecb->xs->sc_link); 1434 printf("sync nego not completed!\n"); 1435 #endif 1436 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1437 sc->sc_flags &= ~NCR_SYNCHNEGO; 1438 ti->flags &= 1439 ~(T_NEGOTIATE | T_SYNCMODE); 1440 } 1441 1442 /* it may be OK to disconnect */ 1443 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1444 /* 1445 * Section 5.1.1 of the SCSI 2 spec 1446 * suggests issuing a REQUEST SENSE 1447 * following an unexpected disconnect. 1448 * Some devices go into a contingent 1449 * allegiance condition when 1450 * disconnecting, and this is necessary 1451 * to clean up their state. 1452 */ 1453 printf("%s: unexpected disconnect; ", 1454 sc->sc_dev.dv_xname); 1455 if (ecb->flags & ECB_SENSE) { 1456 printf("resetting\n"); 1457 goto reset; 1458 } 1459 printf("sending REQUEST SENSE\n"); 1460 untimeout(ncr53c9x_timeout, ecb); 1461 ncr53c9x_sense(sc, ecb); 1462 goto out; 1463 } 1464 1465 ecb->xs->error = XS_DRIVER_STUFFUP; 1466 goto finish; 1467 1468 case NCR_DISCONNECT: 1469 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1470 sc->sc_nexus = NULL; 1471 goto sched; 1472 1473 case NCR_CMDCOMPLETE: 1474 goto finish; 1475 } 1476 } 1477 1478 switch (sc->sc_state) { 1479 1480 case NCR_SBR: 1481 printf("%s: waiting for SCSI Bus Reset to happen\n", 1482 sc->sc_dev.dv_xname); 1483 return 1; 1484 1485 case NCR_RESELECTED: 1486 /* 1487 * we must be continuing a message ? 1488 */ 1489 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1490 printf("%s: target didn't identify\n", 1491 sc->sc_dev.dv_xname); 1492 ncr53c9x_init(sc, 1); 1493 return 1; 1494 } 1495 printf("<<RESELECT CONT'd>>"); 1496 #if XXXX 1497 ncr53c9x_msgin(sc); 1498 if (sc->sc_state != NCR_CONNECTED) { 1499 /* IDENTIFY fail?! */ 1500 printf("%s: identify failed\n", 1501 sc->sc_dev.dv_xname); 1502 ncr53c9x_init(sc, 1); 1503 return 1; 1504 } 1505 #endif 1506 break; 1507 1508 case NCR_IDLE: 1509 if (sc->sc_flags & NCR_ICCS) printf("[[esp: BUMMER]]"); 1510 case NCR_SELECTING: 1511 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1512 sc->sc_flags = 0; 1513 ecb = sc->sc_nexus; 1514 1515 if (sc->sc_espintr & NCRINTR_RESEL) { 1516 /* 1517 * If we're trying to select a 1518 * target ourselves, push our command 1519 * back into the ready list. 1520 */ 1521 if (sc->sc_state == NCR_SELECTING) { 1522 NCR_MISC(("backoff selector ")); 1523 untimeout(ncr53c9x_timeout, ecb); 1524 sc_link = ecb->xs->sc_link; 1525 ti = &sc->sc_tinfo[sc_link->target]; 1526 TAILQ_INSERT_HEAD(&sc->ready_list, 1527 ecb, chain); 1528 ecb = sc->sc_nexus = NULL; 1529 } 1530 sc->sc_state = NCR_RESELECTED; 1531 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1532 /* 1533 * Things are seriously fucked up. 1534 * Pull the brakes, i.e. reset 1535 */ 1536 printf("%s: target didn't identify\n", 1537 sc->sc_dev.dv_xname); 1538 ncr53c9x_init(sc, 1); 1539 return 1; 1540 } 1541 /* 1542 * The C90 only inhibits FIFO writes until 1543 * reselection is complete, instead of 1544 * waiting until the interrupt status register 1545 * has been read. So, if the reselect happens 1546 * while we were entering a command bytes (for 1547 * another target) some of those bytes can 1548 * appear in the FIFO here, after the 1549 * interrupt is taken. 1550 */ 1551 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1552 if (nfifo < 2 || 1553 (nfifo > 2 && 1554 sc->sc_rev != NCR_VARIANT_ESP100)) { 1555 printf("%s: RESELECT: " 1556 "%d bytes in FIFO!\n", 1557 sc->sc_dev.dv_xname, 1558 nfifo); 1559 ncr53c9x_init(sc, 1); 1560 return 1; 1561 } 1562 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1563 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1564 1565 /* Handle identify message */ 1566 ncr53c9x_msgin(sc); 1567 if (nfifo != 2) 1568 NCRCMD(sc, NCRCMD_FLUSH); 1569 1570 if (sc->sc_state != NCR_CONNECTED) { 1571 /* IDENTIFY fail?! */ 1572 printf("%s: identify failed\n", 1573 sc->sc_dev.dv_xname); 1574 ncr53c9x_init(sc, 1); 1575 return 1; 1576 } 1577 continue; /* ie. next phase expected soon */ 1578 } 1579 1580 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1581 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1582 ecb = sc->sc_nexus; 1583 if (!ecb) 1584 panic("esp: not nexus at sc->sc_nexus"); 1585 1586 sc_link = ecb->xs->sc_link; 1587 ti = &sc->sc_tinfo[sc_link->target]; 1588 1589 switch (sc->sc_espstep) { 1590 case 0: 1591 printf("%s: select timeout/no " 1592 "disconnect\n", 1593 sc->sc_dev.dv_xname); 1594 ecb->xs->error = XS_SELTIMEOUT; 1595 goto finish; 1596 case 1: 1597 if ((ti->flags & T_NEGOTIATE) == 0) { 1598 printf("%s: step 1 & !NEG\n", 1599 sc->sc_dev.dv_xname); 1600 goto reset; 1601 } 1602 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1603 printf("%s: !MSGOUT\n", 1604 sc->sc_dev.dv_xname); 1605 goto reset; 1606 } 1607 /* Start negotiating */ 1608 ti->period = sc->sc_minsync; 1609 ti->offset = 15; 1610 sc->sc_flags |= NCR_SYNCHNEGO; 1611 ncr53c9x_sched_msgout(SEND_SDTR); 1612 break; 1613 case 3: 1614 /* 1615 * Grr, this is supposed to mean 1616 * "target left command phase 1617 * prematurely". It seems to happen 1618 * regularly when sync mode is on. 1619 * Look at FIFO to see if command 1620 * went out. 1621 * (Timing problems?) 1622 */ 1623 if ((NCR_READ_REG(sc, NCR_FFLAG) 1624 & NCRFIFO_FF) == 0) { 1625 /* Hope for the best.. */ 1626 break; 1627 } 1628 printf("(%s:%d:%d): selection failed;" 1629 " %d left in FIFO " 1630 "[intr %x, stat %x, step %d]\n", 1631 sc->sc_dev.dv_xname, 1632 sc_link->target, 1633 sc_link->lun, 1634 NCR_READ_REG(sc, NCR_FFLAG) 1635 & NCRFIFO_FF, 1636 sc->sc_espintr, sc->sc_espstat, 1637 sc->sc_espstep); 1638 NCRCMD(sc, NCRCMD_FLUSH); 1639 ncr53c9x_sched_msgout(SEND_ABORT); 1640 return 1; 1641 case 2: 1642 /* Select stuck at Command Phase */ 1643 NCRCMD(sc, NCRCMD_FLUSH); 1644 case 4: 1645 /* So far, everything went fine */ 1646 break; 1647 } 1648 #if 0 1649 if (ecb->xs->flags & SCSI_RESET) 1650 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1651 else if (ti->flags & T_NEGOTIATE) 1652 ncr53c9x_sched_msgout( 1653 SEND_IDENTIFY | SEND_SDTR); 1654 else 1655 ncr53c9x_sched_msgout(SEND_IDENTIFY); 1656 #endif 1657 1658 ecb->flags |= ECB_NEXUS; 1659 ti->lubusy |= (1 << sc_link->lun); 1660 1661 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1662 /* Do an implicit RESTORE POINTERS. */ 1663 sc->sc_dp = ecb->daddr; 1664 sc->sc_dleft = ecb->dleft; 1665 sc->sc_state = NCR_CONNECTED; 1666 break; 1667 } else { 1668 printf("%s: unexpected status after select" 1669 ": [intr %x, stat %x, step %x]\n", 1670 sc->sc_dev.dv_xname, 1671 sc->sc_espintr, sc->sc_espstat, 1672 sc->sc_espstep); 1673 NCRCMD(sc, NCRCMD_FLUSH); 1674 DELAY(1); 1675 goto reset; 1676 } 1677 if (sc->sc_state == NCR_IDLE) { 1678 printf("%s: stray interrupt\n", 1679 sc->sc_dev.dv_xname); 1680 return 0; 1681 } 1682 break; 1683 1684 case NCR_CONNECTED: 1685 if (sc->sc_flags & NCR_ICCS) { 1686 u_char msg; 1687 1688 sc->sc_flags &= ~NCR_ICCS; 1689 1690 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1691 printf("%s: ICCS: " 1692 ": [intr %x, stat %x, step %x]\n", 1693 sc->sc_dev.dv_xname, 1694 sc->sc_espintr, sc->sc_espstat, 1695 sc->sc_espstep); 1696 } 1697 if ((NCR_READ_REG(sc, NCR_FFLAG) 1698 & NCRFIFO_FF) != 2) { 1699 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1700 & NCRFIFO_FF) - 2; 1701 while (i--) 1702 (void) NCR_READ_REG(sc, 1703 NCR_FIFO); 1704 } 1705 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1706 msg = NCR_READ_REG(sc, NCR_FIFO); 1707 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1708 if (msg == MSG_CMDCOMPLETE) { 1709 ecb->xs->resid = ecb->dleft = 1710 sc->sc_dleft; 1711 sc->sc_state = NCR_CMDCOMPLETE; 1712 } else 1713 printf("%s: STATUS_PHASE: msg %d\n", 1714 sc->sc_dev.dv_xname, msg); 1715 NCRCMD(sc, NCRCMD_MSGOK); 1716 continue; /* ie. wait for disconnect */ 1717 } 1718 break; 1719 default: 1720 panic("%s: invalid state: %d", 1721 sc->sc_dev.dv_xname, 1722 sc->sc_state); 1723 } 1724 1725 /* 1726 * Driver is now in state NCR_CONNECTED, i.e. we 1727 * have a current command working the SCSI bus. 1728 */ 1729 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1730 panic("esp no nexus"); 1731 } 1732 1733 switch (sc->sc_phase) { 1734 case MESSAGE_OUT_PHASE: 1735 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1736 ncr53c9x_msgout(sc); 1737 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1738 break; 1739 case MESSAGE_IN_PHASE: 1740 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1741 if (sc->sc_espintr & NCRINTR_BS) { 1742 NCRCMD(sc, NCRCMD_FLUSH); 1743 sc->sc_flags |= NCR_WAITI; 1744 NCRCMD(sc, NCRCMD_TRANS); 1745 } else if (sc->sc_espintr & NCRINTR_FC) { 1746 if ((sc->sc_flags & NCR_WAITI) == 0) { 1747 printf("%s: MSGIN: unexpected FC bit: " 1748 "[intr %x, stat %x, step %x]\n", 1749 sc->sc_dev.dv_xname, 1750 sc->sc_espintr, sc->sc_espstat, 1751 sc->sc_espstep); 1752 } 1753 sc->sc_flags &= ~NCR_WAITI; 1754 ncr53c9x_msgin(sc); 1755 } else { 1756 printf("%s: MSGIN: weird bits: " 1757 "[intr %x, stat %x, step %x]\n", 1758 sc->sc_dev.dv_xname, 1759 sc->sc_espintr, sc->sc_espstat, 1760 sc->sc_espstep); 1761 } 1762 sc->sc_prevphase = MESSAGE_IN_PHASE; 1763 break; 1764 case COMMAND_PHASE: { 1765 /* well, this means send the command again */ 1766 u_char *cmd = (u_char *)&ecb->cmd; 1767 int i; 1768 1769 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 1770 ecb->cmd.opcode, ecb->clen)); 1771 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1772 NCRCMD(sc, NCRCMD_FLUSH); 1773 DELAY(1); 1774 } 1775 /* Now the command into the FIFO */ 1776 for (i = 0; i < ecb->clen; i++) 1777 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 1778 NCRCMD(sc, NCRCMD_TRANS); 1779 sc->sc_prevphase = COMMAND_PHASE; 1780 } 1781 break; 1782 case DATA_OUT_PHASE: 1783 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 1784 NCRCMD(sc, NCRCMD_FLUSH); 1785 size = min(sc->sc_dleft, sc->sc_maxxfer); 1786 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1787 0, &size); 1788 sc->sc_prevphase = DATA_OUT_PHASE; 1789 goto setup_xfer; 1790 case DATA_IN_PHASE: 1791 NCR_PHASE(("DATA_IN_PHASE ")); 1792 if (sc->sc_rev == NCR_VARIANT_ESP100) 1793 NCRCMD(sc, NCRCMD_FLUSH); 1794 size = min(sc->sc_dleft, sc->sc_maxxfer); 1795 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1796 1, &size); 1797 sc->sc_prevphase = DATA_IN_PHASE; 1798 setup_xfer: 1799 /* Program the SCSI counter */ 1800 NCR_WRITE_REG(sc, NCR_TCL, size); 1801 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1802 if (sc->sc_cfg2 & NCRCFG2_FE) { 1803 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1804 } 1805 /* load the count in */ 1806 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1807 1808 /* 1809 * Note that if `size' is 0, we've already transceived 1810 * all the bytes we want but we're still in DATA PHASE. 1811 * Apparently, the device needs padding. Also, a 1812 * transfer size of 0 means "maximum" to the chip 1813 * DMA logic. 1814 */ 1815 NCRCMD(sc, 1816 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 1817 NCRDMA_GO(sc); 1818 return 1; 1819 case STATUS_PHASE: 1820 NCR_PHASE(("STATUS_PHASE ")); 1821 sc->sc_flags |= NCR_ICCS; 1822 NCRCMD(sc, NCRCMD_ICCS); 1823 sc->sc_prevphase = STATUS_PHASE; 1824 break; 1825 case INVALID_PHASE: 1826 break; 1827 default: 1828 printf("%s: unexpected bus phase; resetting\n", 1829 sc->sc_dev.dv_xname); 1830 goto reset; 1831 } 1832 } 1833 panic("esp: should not get here.."); 1834 1835 reset: 1836 ncr53c9x_init(sc, 1); 1837 return 1; 1838 1839 finish: 1840 ncr53c9x_done(sc, ecb); 1841 goto out; 1842 1843 sched: 1844 sc->sc_state = NCR_IDLE; 1845 ncr53c9x_sched(sc); 1846 goto out; 1847 1848 out: 1849 return 1; 1850 } 1851 1852 void 1853 ncr53c9x_abort(sc, ecb) 1854 struct ncr53c9x_softc *sc; 1855 struct ncr53c9x_ecb *ecb; 1856 { 1857 1858 /* 2 secs for the abort */ 1859 ecb->timeout = NCR_ABORT_TIMEOUT; 1860 ecb->flags |= ECB_ABORT; 1861 1862 if (ecb == sc->sc_nexus) { 1863 /* 1864 * If we're still selecting, the message will be scheduled 1865 * after selection is complete. 1866 */ 1867 if (sc->sc_state == NCR_CONNECTED) 1868 ncr53c9x_sched_msgout(SEND_ABORT); 1869 1870 /* 1871 * Reschedule timeout. First, cancel a queued timeout (if any) 1872 * in case someone decides to call ncr53c9x_abort() from 1873 * elsewhere. 1874 */ 1875 untimeout(ncr53c9x_timeout, ecb); 1876 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 1877 } else { 1878 ncr53c9x_dequeue(sc, ecb); 1879 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1880 if (sc->sc_state == NCR_IDLE) 1881 ncr53c9x_sched(sc); 1882 } 1883 } 1884 1885 void 1886 ncr53c9x_timeout(arg) 1887 void *arg; 1888 { 1889 struct ncr53c9x_ecb *ecb = arg; 1890 struct scsi_xfer *xs = ecb->xs; 1891 struct scsi_link *sc_link = xs->sc_link; 1892 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 1893 int s; 1894 1895 sc_print_addr(sc_link); 1896 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 1897 "<state %d, nexus %p, phase(c %x, p %x), resid %lx, " 1898 "msg(q %x,o %x) %s>", 1899 sc->sc_dev.dv_xname, 1900 ecb, ecb->flags, ecb->dleft, ecb->stat, 1901 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 1902 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 1903 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 1904 #if NCR53C9X_DEBUG > 1 1905 printf("TRACE: %s.", ecb->trace); 1906 #endif 1907 1908 s = splbio(); 1909 1910 if (ecb->flags & ECB_ABORT) { 1911 /* abort timed out */ 1912 printf(" AGAIN\n"); 1913 ncr53c9x_init(sc, 1); 1914 } else { 1915 /* abort the operation that has timed out */ 1916 printf("\n"); 1917 xs->error = XS_TIMEOUT; 1918 ncr53c9x_abort(sc, ecb); 1919 } 1920 1921 splx(s); 1922 } 1923
Indexes created Fri Sep 26 20:09:58 GMT 2025