ncr53c9x.c revision 1.8
1 /* $NetBSD: ncr53c9x.c,v 1.8 1997/04/27 22:08:51 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 84 #include <scsi/scsi_all.h> 85 #include <scsi/scsiconf.h> 86 #include <scsi/scsi_message.h> 87 88 #include <machine/cpu.h> 89 90 #include <dev/ic/ncr53c9xreg.h> 91 #include <dev/ic/ncr53c9xvar.h> 92 93 int ncr53c9x_debug = 0; /*NCR_SHOWPHASE|NCR_SHOWMISC|NCR_SHOWTRAC|NCR_SHOWCMDS;*/ 94 95 /*static*/ void ncr53c9x_readregs __P((struct ncr53c9x_softc *)); 96 /*static*/ void ncr53c9x_select __P((struct ncr53c9x_softc *, 97 struct ncr53c9x_ecb *)); 98 /*static*/ int ncr53c9x_reselect __P((struct ncr53c9x_softc *, int)); 99 /*static*/ void ncr53c9x_scsi_reset __P((struct ncr53c9x_softc *)); 100 /*static*/ void ncr53c9x_init __P((struct ncr53c9x_softc *, int)); 101 /*static*/ int ncr53c9x_poll __P((struct ncr53c9x_softc *, 102 struct scsi_xfer *, int)); 103 /*static*/ void ncr53c9x_sched __P((struct ncr53c9x_softc *)); 104 /*static*/ void ncr53c9x_done __P((struct ncr53c9x_softc *, 105 struct ncr53c9x_ecb *)); 106 /*static*/ void ncr53c9x_msgin __P((struct ncr53c9x_softc *)); 107 /*static*/ void ncr53c9x_msgout __P((struct ncr53c9x_softc *)); 108 /*static*/ void ncr53c9x_timeout __P((void *arg)); 109 /*static*/ void ncr53c9x_abort __P((struct ncr53c9x_softc *, 110 struct ncr53c9x_ecb *)); 111 /*static*/ void ncr53c9x_dequeue __P((struct ncr53c9x_softc *, 112 struct ncr53c9x_ecb *)); 113 114 void ncr53c9x_sense __P((struct ncr53c9x_softc *, 115 struct ncr53c9x_ecb *)); 116 void ncr53c9x_free_ecb __P((struct ncr53c9x_softc *, 117 struct ncr53c9x_ecb *, int)); 118 struct ncr53c9x_ecb *ncr53c9x_get_ecb __P((struct ncr53c9x_softc *, int)); 119 120 static inline int ncr53c9x_stp2cpb __P((struct ncr53c9x_softc *, int)); 121 static inline void ncr53c9x_setsync __P((struct ncr53c9x_softc *, 122 struct ncr53c9x_tinfo *)); 123 124 /* 125 * Names for the NCR53c9x variants, correspnding to the variant tags 126 * in ncr53c9xvar.h. 127 */ 128 const char *ncr53c9x_variant_names[] = { 129 "ESP100", 130 "ESP100A", 131 "ESP200", 132 "NCR53C94", 133 "NCR53C96", 134 }; 135 136 /* 137 * Attach this instance, and then all the sub-devices 138 */ 139 void 140 ncr53c9x_attach(sc, adapter, dev) 141 struct ncr53c9x_softc *sc; 142 struct scsi_adapter *adapter; 143 struct scsi_device *dev; 144 { 145 146 /* 147 * Note, the front-end has set us up to print the chip variation. 148 */ 149 150 if (sc->sc_rev >= NCR_VARIANT_MAX) { 151 printf("\n%s: unknown variant %d, devices not attached\n", 152 sc->sc_dev.dv_xname, sc->sc_rev); 153 return; 154 } 155 156 printf(": %s, %dMHz, SCSI ID %d\n", 157 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 158 159 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 160 161 /* The value *must not* be == 1. Make it 2 */ 162 if (sc->sc_ccf == 1) 163 sc->sc_ccf = 2; 164 165 /* 166 * The recommended timeout is 250ms. This register is loaded 167 * with a value calculated as follows, from the docs: 168 * 169 * (timout period) x (CLK frequency) 170 * reg = ------------------------------------- 171 * 8192 x (Clock Conversion Factor) 172 * 173 * Since CCF has a linear relation to CLK, this generally computes 174 * to the constant of 153. 175 */ 176 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 177 178 /* CCF register only has 3 bits; 0 is actually 8 */ 179 sc->sc_ccf &= 7; 180 181 /* Reset state & bus */ 182 sc->sc_state = 0; 183 ncr53c9x_init(sc, 1); 184 185 /* 186 * fill in the prototype scsi_link. 187 */ 188 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 189 sc->sc_link.adapter_softc = sc; 190 sc->sc_link.adapter_target = sc->sc_id; 191 sc->sc_link.adapter = adapter; 192 sc->sc_link.device = dev; 193 sc->sc_link.openings = 2; 194 sc->sc_link.max_target = 7; 195 196 /* 197 * Now try to attach all the sub-devices 198 */ 199 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 200 } 201 202 /* 203 * This is the generic esp reset function. It does not reset the SCSI bus, 204 * only this controllers, but kills any on-going commands, and also stops 205 * and resets the DMA. 206 * 207 * After reset, registers are loaded with the defaults from the attach 208 * routine above. 209 */ 210 void 211 ncr53c9x_reset(sc) 212 struct ncr53c9x_softc *sc; 213 { 214 215 /* reset DMA first */ 216 NCRDMA_RESET(sc); 217 218 /* reset SCSI chip */ 219 NCRCMD(sc, NCRCMD_RSTCHIP); 220 NCRCMD(sc, NCRCMD_NOP); 221 DELAY(500); 222 223 /* do these backwards, and fall through */ 224 switch (sc->sc_rev) { 225 case NCR_VARIANT_NCR53C94: 226 case NCR_VARIANT_NCR53C96: 227 case NCR_VARIANT_ESP200: 228 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 229 case NCR_VARIANT_ESP100A: 230 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 231 case NCR_VARIANT_ESP100: 232 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 233 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 234 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 235 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 236 break; 237 default: 238 printf("%s: unknown revision code, assuming ESP100\n", 239 sc->sc_dev.dv_xname); 240 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 241 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 242 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 243 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 244 } 245 } 246 247 /* 248 * Reset the SCSI bus, but not the chip 249 */ 250 void 251 ncr53c9x_scsi_reset(sc) 252 struct ncr53c9x_softc *sc; 253 { 254 255 (*sc->sc_glue->gl_dma_stop)(sc); 256 257 printf("%s: resetting SCSI bus\n", sc->sc_dev.dv_xname); 258 NCRCMD(sc, NCRCMD_RSTSCSI); 259 } 260 261 /* 262 * Initialize esp state machine 263 */ 264 void 265 ncr53c9x_init(sc, doreset) 266 struct ncr53c9x_softc *sc; 267 int doreset; 268 { 269 struct ncr53c9x_ecb *ecb; 270 int r; 271 272 NCR_TRACE(("[NCR_INIT(%d)] ", doreset)); 273 274 if (sc->sc_state == 0) { 275 /* First time through; initialize. */ 276 TAILQ_INIT(&sc->ready_list); 277 TAILQ_INIT(&sc->nexus_list); 278 TAILQ_INIT(&sc->free_list); 279 sc->sc_nexus = NULL; 280 ecb = sc->sc_ecb; 281 bzero(ecb, sizeof(sc->sc_ecb)); 282 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 283 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 284 ecb++; 285 } 286 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 287 } else { 288 /* Cancel any active commands. */ 289 sc->sc_state = NCR_CLEANING; 290 if ((ecb = sc->sc_nexus) != NULL) { 291 ecb->xs->error = XS_DRIVER_STUFFUP; 292 ncr53c9x_done(sc, ecb); 293 } 294 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 295 ecb->xs->error = XS_DRIVER_STUFFUP; 296 ncr53c9x_done(sc, ecb); 297 } 298 } 299 300 /* 301 * reset the chip to a known state 302 */ 303 ncr53c9x_reset(sc); 304 305 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 306 for (r = 0; r < 8; r++) { 307 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 308 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 309 int fl = sc->sc_dev.dv_cfdata->cf_flags; 310 311 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 312 ? T_NEGOTIATE : 0) | 313 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 314 T_NEED_TO_RESET; 315 ti->period = sc->sc_minsync; 316 ti->offset = 0; 317 } 318 319 if (doreset) { 320 sc->sc_state = NCR_SBR; 321 NCRCMD(sc, NCRCMD_RSTSCSI); 322 } else { 323 sc->sc_state = NCR_IDLE; 324 } 325 } 326 327 /* 328 * Read the NCR registers, and save their contents for later use. 329 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 330 * NCR_INTR - so make sure it is the last read. 331 * 332 * I think that (from reading the docs) most bits in these registers 333 * only make sense when he DMA CSR has an interrupt showing. Call only 334 * if an interrupt is pending. 335 */ 336 void 337 ncr53c9x_readregs(sc) 338 struct ncr53c9x_softc *sc; 339 { 340 341 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 342 /* Only the stepo bits are of interest */ 343 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 344 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 345 346 if (sc->sc_glue->gl_clear_latched_intr != NULL) 347 (*sc->sc_glue->gl_clear_latched_intr)(sc); 348 349 /* 350 * Determine the SCSI bus phase, return either a real SCSI bus phase 351 * or some pseudo phase we use to detect certain exceptions. 352 */ 353 354 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) 355 ? /* Disconnected */ BUSFREE_PHASE 356 : sc->sc_espstat & NCRSTAT_PHASE; 357 358 NCR_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 359 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 360 } 361 362 /* 363 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 364 */ 365 static inline int 366 ncr53c9x_stp2cpb(sc, period) 367 struct ncr53c9x_softc *sc; 368 int period; 369 { 370 int v; 371 v = (sc->sc_freq * period) / 250; 372 if (ncr53c9x_cpb2stp(sc, v) < period) 373 /* Correct round-down error */ 374 v++; 375 return v; 376 } 377 378 static inline void 379 ncr53c9x_setsync(sc, ti) 380 struct ncr53c9x_softc *sc; 381 struct ncr53c9x_tinfo *ti; 382 { 383 384 if (ti->flags & T_SYNCMODE) { 385 NCR_WRITE_REG(sc, NCR_SYNCOFF, ti->offset); 386 NCR_WRITE_REG(sc, NCR_SYNCTP, 387 ncr53c9x_stp2cpb(sc, ti->period)); 388 } else { 389 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 390 NCR_WRITE_REG(sc, NCR_SYNCTP, 0); 391 } 392 } 393 394 int ncr53c9x_dmaselect = 0; 395 /* 396 * Send a command to a target, set the driver state to NCR_SELECTING 397 * and let the caller take care of the rest. 398 * 399 * Keeping this as a function allows me to say that this may be done 400 * by DMA instead of programmed I/O soon. 401 */ 402 void 403 ncr53c9x_select(sc, ecb) 404 struct ncr53c9x_softc *sc; 405 struct ncr53c9x_ecb *ecb; 406 { 407 struct scsi_link *sc_link = ecb->xs->sc_link; 408 int target = sc_link->target; 409 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[target]; 410 u_char *cmd; 411 int clen; 412 413 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x)] ", 414 sc_link->target, sc_link->lun, ecb->cmd.cmd.opcode)); 415 416 /* new state NCR_SELECTING */ 417 sc->sc_state = NCR_SELECTING; 418 419 /* 420 * Schedule the timeout now, the first time we will go away 421 * expecting to come back due to an interrupt, because it is 422 * always possible that the interrupt may never happen. 423 */ 424 if ((ecb->xs->flags & SCSI_POLL) == 0) 425 timeout(ncr53c9x_timeout, ecb, 426 (ecb->timeout * hz) / 1000); 427 428 NCRCMD(sc, NCRCMD_FLUSH); 429 430 /* 431 * The docs say the target register is never reset, and I 432 * can't think of a better place to set it 433 */ 434 NCR_WRITE_REG(sc, NCR_SELID, target); 435 ncr53c9x_setsync(sc, ti); 436 437 if (ncr53c9x_dmaselect && (ti->flags & T_NEGOTIATE) == 0) { 438 ecb->cmd.id = 439 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1); 440 441 /* setup DMA transfer for command */ 442 clen = ecb->clen + 1; 443 sc->sc_cmdlen = clen; 444 sc->sc_cmdp = (caddr_t)&ecb->cmd; 445 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &clen); 446 /* Program the SCSI counter */ 447 NCR_WRITE_REG(sc, NCR_TCL, clen); 448 NCR_WRITE_REG(sc, NCR_TCM, clen >> 8); 449 if (sc->sc_cfg2 & NCRCFG2_FE) { 450 NCR_WRITE_REG(sc, NCR_TCH, clen >> 16); 451 } 452 453 /* And get the targets attention */ 454 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 455 NCRDMA_GO(sc); 456 return; 457 } 458 /* 459 * Who am I. This is where we tell the target that we are 460 * happy for it to disconnect etc. 461 */ 462 NCR_WRITE_REG(sc, NCR_FIFO, 463 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 464 465 if (ti->flags & T_NEGOTIATE) { 466 /* Arbitrate, select and stop after IDENTIFY message */ 467 NCRCMD(sc, NCRCMD_SELATNS); 468 return; 469 } 470 471 /* Now the command into the FIFO */ 472 cmd = (u_char *)&ecb->cmd.cmd; 473 clen = ecb->clen; 474 while (clen--) 475 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 476 477 /* And get the targets attention */ 478 NCRCMD(sc, NCRCMD_SELATN); 479 } 480 481 void 482 ncr53c9x_free_ecb(sc, ecb, flags) 483 struct ncr53c9x_softc *sc; 484 struct ncr53c9x_ecb *ecb; 485 int flags; 486 { 487 int s; 488 489 s = splbio(); 490 491 ecb->flags = 0; 492 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 493 494 /* 495 * If there were none, wake anybody waiting for one to come free, 496 * starting with queued entries. 497 */ 498 if (ecb->chain.tqe_next == 0) 499 wakeup(&sc->free_list); 500 501 splx(s); 502 } 503 504 struct ncr53c9x_ecb * 505 ncr53c9x_get_ecb(sc, flags) 506 struct ncr53c9x_softc *sc; 507 int flags; 508 { 509 struct ncr53c9x_ecb *ecb; 510 int s; 511 512 s = splbio(); 513 514 while ((ecb = sc->free_list.tqh_first) == NULL && 515 (flags & SCSI_NOSLEEP) == 0) 516 tsleep(&sc->free_list, PRIBIO, "especb", 0); 517 if (ecb) { 518 TAILQ_REMOVE(&sc->free_list, ecb, chain); 519 ecb->flags |= ECB_ALLOC; 520 } 521 522 splx(s); 523 return ecb; 524 } 525 526 /* 527 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 528 */ 529 530 /* 531 * Start a SCSI-command 532 * This function is called by the higher level SCSI-driver to queue/run 533 * SCSI-commands. 534 */ 535 int 536 ncr53c9x_scsi_cmd(xs) 537 struct scsi_xfer *xs; 538 { 539 struct scsi_link *sc_link = xs->sc_link; 540 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 541 struct ncr53c9x_ecb *ecb; 542 int s, flags; 543 544 NCR_TRACE(("[ncr53c9x_scsi_cmd] ")); 545 NCR_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 546 sc_link->target)); 547 548 flags = xs->flags; 549 if ((ecb = ncr53c9x_get_ecb(sc, flags)) == NULL) { 550 xs->error = XS_DRIVER_STUFFUP; 551 return TRY_AGAIN_LATER; 552 } 553 554 /* Initialize ecb */ 555 ecb->xs = xs; 556 ecb->timeout = xs->timeout; 557 558 if (flags & SCSI_RESET) { 559 ecb->flags |= ECB_RESET; 560 ecb->clen = 0; 561 ecb->dleft = 0; 562 } else { 563 bcopy(xs->cmd, &ecb->cmd.cmd, xs->cmdlen); 564 ecb->clen = xs->cmdlen; 565 ecb->daddr = xs->data; 566 ecb->dleft = xs->datalen; 567 } 568 ecb->stat = 0; 569 570 s = splbio(); 571 572 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 573 if (sc->sc_state == NCR_IDLE) 574 ncr53c9x_sched(sc); 575 576 splx(s); 577 578 if ((flags & SCSI_POLL) == 0) 579 return SUCCESSFULLY_QUEUED; 580 581 /* Not allowed to use interrupts, use polling instead */ 582 if (ncr53c9x_poll(sc, xs, ecb->timeout)) { 583 ncr53c9x_timeout(ecb); 584 if (ncr53c9x_poll(sc, xs, ecb->timeout)) 585 ncr53c9x_timeout(ecb); 586 } 587 return COMPLETE; 588 } 589 590 /* 591 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 592 */ 593 int 594 ncr53c9x_poll(sc, xs, count) 595 struct ncr53c9x_softc *sc; 596 struct scsi_xfer *xs; 597 int count; 598 { 599 600 NCR_TRACE(("[ncr53c9x_poll] ")); 601 while (count) { 602 if (NCRDMA_ISINTR(sc)) { 603 ncr53c9x_intr(sc); 604 } 605 #if alternatively 606 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) 607 ncr53c9x_intr(sc); 608 #endif 609 if ((xs->flags & ITSDONE) != 0) 610 return 0; 611 if (sc->sc_state == NCR_IDLE) { 612 NCR_TRACE(("[ncr53c9x_poll: rescheduling] ")); 613 ncr53c9x_sched(sc); 614 } 615 DELAY(1000); 616 count--; 617 } 618 return 1; 619 } 620 621 622 /* 623 * LOW LEVEL SCSI UTILITIES 624 */ 625 626 /* 627 * Schedule a scsi operation. This has now been pulled out of the interrupt 628 * handler so that we may call it from ncr53c9x_scsi_cmd and ncr53c9x_done. 629 * This may save us an unecessary interrupt just to get things going. 630 * Should only be called when state == NCR_IDLE and at bio pl. 631 */ 632 void 633 ncr53c9x_sched(sc) 634 struct ncr53c9x_softc *sc; 635 { 636 struct ncr53c9x_ecb *ecb; 637 struct scsi_link *sc_link; 638 struct ncr53c9x_tinfo *ti; 639 640 NCR_TRACE(("[ncr53c9x_sched] ")); 641 if (sc->sc_state != NCR_IDLE) 642 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 643 644 /* 645 * Find first ecb in ready queue that is for a target/lunit 646 * combinations that is not busy. 647 */ 648 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 649 sc_link = ecb->xs->sc_link; 650 ti = &sc->sc_tinfo[sc_link->target]; 651 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 652 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 653 sc->sc_nexus = ecb; 654 ncr53c9x_select(sc, ecb); 655 break; 656 } else 657 NCR_MISC(("%d:%d busy\n", 658 sc_link->target, sc_link->lun)); 659 } 660 } 661 662 void 663 ncr53c9x_sense(sc, ecb) 664 struct ncr53c9x_softc *sc; 665 struct ncr53c9x_ecb *ecb; 666 { 667 struct scsi_xfer *xs = ecb->xs; 668 struct scsi_link *sc_link = xs->sc_link; 669 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 670 struct scsi_sense *ss = (void *)&ecb->cmd.cmd; 671 672 NCR_MISC(("requesting sense ")); 673 /* Next, setup a request sense command block */ 674 bzero(ss, sizeof(*ss)); 675 ss->opcode = REQUEST_SENSE; 676 ss->byte2 = sc_link->lun << 5; 677 ss->length = sizeof(struct scsi_sense_data); 678 ecb->clen = sizeof(*ss); 679 ecb->daddr = (char *)&xs->sense; 680 ecb->dleft = sizeof(struct scsi_sense_data); 681 ecb->flags |= ECB_SENSE; 682 ecb->timeout = NCR_SENSE_TIMEOUT; 683 ti->senses++; 684 if (ecb->flags & ECB_NEXUS) 685 ti->lubusy &= ~(1 << sc_link->lun); 686 if (ecb == sc->sc_nexus) { 687 ncr53c9x_select(sc, ecb); 688 } else { 689 ncr53c9x_dequeue(sc, ecb); 690 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 691 if (sc->sc_state == NCR_IDLE) 692 ncr53c9x_sched(sc); 693 } 694 } 695 696 /* 697 * POST PROCESSING OF SCSI_CMD (usually current) 698 */ 699 void 700 ncr53c9x_done(sc, ecb) 701 struct ncr53c9x_softc *sc; 702 struct ncr53c9x_ecb *ecb; 703 { 704 struct scsi_xfer *xs = ecb->xs; 705 struct scsi_link *sc_link = xs->sc_link; 706 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 707 708 NCR_TRACE(("[ncr53c9x_done(error:%x)] ", xs->error)); 709 710 untimeout(ncr53c9x_timeout, ecb); 711 712 /* 713 * Now, if we've come here with no error code, i.e. we've kept the 714 * initial XS_NOERROR, and the status code signals that we should 715 * check sense, we'll need to set up a request sense cmd block and 716 * push the command back into the ready queue *before* any other 717 * commands for this target/lunit, else we lose the sense info. 718 * We don't support chk sense conditions for the request sense cmd. 719 */ 720 if (xs->error == XS_NOERROR) { 721 if ((ecb->flags & ECB_ABORT) != 0) { 722 xs->error = XS_DRIVER_STUFFUP; 723 } else if ((ecb->flags & ECB_SENSE) != 0) { 724 xs->error = XS_SENSE; 725 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 726 /* First, save the return values */ 727 xs->resid = ecb->dleft; 728 xs->status = ecb->stat; 729 ncr53c9x_sense(sc, ecb); 730 return; 731 } else { 732 xs->resid = ecb->dleft; 733 } 734 } 735 736 xs->flags |= ITSDONE; 737 738 #ifdef NCR53C9X_DEBUG 739 if (ncr53c9x_debug & NCR_SHOWMISC) { 740 if (xs->resid != 0) 741 printf("resid=%d ", xs->resid); 742 if (xs->error == XS_SENSE) 743 printf("sense=0x%02x\n", xs->sense.error_code); 744 else 745 printf("error=%d\n", xs->error); 746 } 747 #endif 748 749 /* 750 * Remove the ECB from whatever queue it's on. 751 */ 752 if (ecb->flags & ECB_NEXUS) 753 ti->lubusy &= ~(1 << sc_link->lun); 754 if (ecb == sc->sc_nexus) { 755 sc->sc_nexus = NULL; 756 sc->sc_state = NCR_IDLE; 757 ncr53c9x_sched(sc); 758 } else 759 ncr53c9x_dequeue(sc, ecb); 760 761 ncr53c9x_free_ecb(sc, ecb, xs->flags); 762 ti->cmds++; 763 scsi_done(xs); 764 } 765 766 void 767 ncr53c9x_dequeue(sc, ecb) 768 struct ncr53c9x_softc *sc; 769 struct ncr53c9x_ecb *ecb; 770 { 771 772 if (ecb->flags & ECB_NEXUS) { 773 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 774 } else { 775 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 776 } 777 } 778 779 /* 780 * INTERRUPT/PROTOCOL ENGINE 781 */ 782 783 /* 784 * Schedule an outgoing message by prioritizing it, and asserting 785 * attention on the bus. We can only do this when we are the initiator 786 * else there will be an illegal command interrupt. 787 */ 788 #define ncr53c9x_sched_msgout(m) \ 789 do { \ 790 NCR_MISC(("ncr53c9x_sched_msgout %d ", m)); \ 791 NCRCMD(sc, NCRCMD_SETATN); \ 792 sc->sc_flags |= NCR_ATN; \ 793 sc->sc_msgpriq |= (m); \ 794 } while (0) 795 796 int 797 ncr53c9x_reselect(sc, message) 798 struct ncr53c9x_softc *sc; 799 int message; 800 { 801 u_char selid, target, lun; 802 struct ncr53c9x_ecb *ecb; 803 struct scsi_link *sc_link; 804 struct ncr53c9x_tinfo *ti; 805 806 /* 807 * The SCSI chip made a snapshot of the data bus while the reselection 808 * was being negotiated. This enables us to determine which target did 809 * the reselect. 810 */ 811 selid = sc->sc_selid & ~(1 << sc->sc_id); 812 if (selid & (selid - 1)) { 813 printf("%s: reselect with invalid selid %02x;" 814 " sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 815 goto reset; 816 } 817 818 /* 819 * Search wait queue for disconnected cmd 820 * The list should be short, so I haven't bothered with 821 * any more sophisticated structures than a simple 822 * singly linked list. 823 */ 824 target = ffs(selid) - 1; 825 lun = message & 0x07; 826 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 827 ecb = ecb->chain.tqe_next) { 828 sc_link = ecb->xs->sc_link; 829 if (sc_link->target == target && sc_link->lun == lun) 830 break; 831 } 832 if (ecb == NULL) { 833 printf("%s: reselect from target %d lun %d with no nexus;" 834 " sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 835 goto abort; 836 } 837 838 /* Make this nexus active again. */ 839 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 840 sc->sc_state = NCR_CONNECTED; 841 sc->sc_nexus = ecb; 842 ti = &sc->sc_tinfo[target]; 843 ti->lubusy |= (1 << lun); 844 ncr53c9x_setsync(sc, ti); 845 846 if (ecb->flags & ECB_RESET) 847 ncr53c9x_sched_msgout(SEND_DEV_RESET); 848 else if (ecb->flags & ECB_ABORT) 849 ncr53c9x_sched_msgout(SEND_ABORT); 850 851 /* Do an implicit RESTORE POINTERS. */ 852 sc->sc_dp = ecb->daddr; 853 sc->sc_dleft = ecb->dleft; 854 855 return (0); 856 857 reset: 858 ncr53c9x_sched_msgout(SEND_DEV_RESET); 859 return (1); 860 861 abort: 862 ncr53c9x_sched_msgout(SEND_ABORT); 863 return (1); 864 } 865 866 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 867 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 868 #define ISEXTMSG(m) ((m) == 1) 869 870 /* 871 * Get an incoming message as initiator. 872 * 873 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 874 * byte in the FIFO 875 */ 876 void 877 ncr53c9x_msgin(sc) 878 register struct ncr53c9x_softc *sc; 879 { 880 register int v; 881 882 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 883 884 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) == 0) { 885 printf("%s: msgin: no msg byte available\n", 886 sc->sc_dev.dv_xname); 887 return; 888 } 889 890 /* 891 * Prepare for a new message. A message should (according 892 * to the SCSI standard) be transmitted in one single 893 * MESSAGE_IN_PHASE. If we have been in some other phase, 894 * then this is a new message. 895 */ 896 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 897 sc->sc_flags &= ~NCR_DROP_MSGI; 898 sc->sc_imlen = 0; 899 } 900 901 v = NCR_READ_REG(sc, NCR_FIFO); 902 NCR_MISC(("<msgbyte:0x%02x>", v)); 903 904 #if 0 905 if (sc->sc_state == NCR_RESELECTED && sc->sc_imlen == 0) { 906 /* 907 * Which target is reselecting us? (The ID bit really) 908 */ 909 sc->sc_selid = v; 910 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 911 return; 912 } 913 #endif 914 915 sc->sc_imess[sc->sc_imlen] = v; 916 917 /* 918 * If we're going to reject the message, don't bother storing 919 * the incoming bytes. But still, we need to ACK them. 920 */ 921 922 if ((sc->sc_flags & NCR_DROP_MSGI)) { 923 NCRCMD(sc, NCRCMD_MSGOK); 924 printf("<dropping msg byte %x>", 925 sc->sc_imess[sc->sc_imlen]); 926 return; 927 } 928 929 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 930 ncr53c9x_sched_msgout(SEND_REJECT); 931 sc->sc_flags |= NCR_DROP_MSGI; 932 } else { 933 sc->sc_imlen++; 934 /* 935 * This testing is suboptimal, but most 936 * messages will be of the one byte variety, so 937 * it should not effect performance 938 * significantly. 939 */ 940 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 941 goto gotit; 942 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 943 goto gotit; 944 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 945 sc->sc_imlen == sc->sc_imess[1] + 2) 946 goto gotit; 947 } 948 /* Ack what we have so far */ 949 NCRCMD(sc, NCRCMD_MSGOK); 950 return; 951 952 gotit: 953 NCR_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 954 /* 955 * Now we should have a complete message (1 byte, 2 byte 956 * and moderately long extended messages). We only handle 957 * extended messages which total length is shorter than 958 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 959 */ 960 switch (sc->sc_state) { 961 struct ncr53c9x_ecb *ecb; 962 struct ncr53c9x_tinfo *ti; 963 964 case NCR_CONNECTED: 965 ecb = sc->sc_nexus; 966 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 967 968 switch (sc->sc_imess[0]) { 969 case MSG_CMDCOMPLETE: 970 NCR_MSGS(("cmdcomplete ")); 971 if (sc->sc_dleft < 0) { 972 struct scsi_link *sc_link = ecb->xs->sc_link; 973 printf("%s: %ld extra bytes from %d:%d\n", 974 sc->sc_dev.dv_xname, -(long)sc->sc_dleft, 975 sc_link->target, sc_link->lun); 976 sc->sc_dleft = 0; 977 } 978 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 979 sc->sc_state = NCR_CMDCOMPLETE; 980 break; 981 982 case MSG_MESSAGE_REJECT: 983 if (ncr53c9x_debug & NCR_SHOWMSGS) 984 printf("%s: our msg rejected by target\n", 985 sc->sc_dev.dv_xname); 986 switch (sc->sc_msgout) { 987 case SEND_SDTR: 988 sc->sc_flags &= ~NCR_SYNCHNEGO; 989 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 990 ncr53c9x_setsync(sc, ti); 991 break; 992 case SEND_INIT_DET_ERR: 993 goto abort; 994 } 995 break; 996 997 case MSG_NOOP: 998 NCR_MSGS(("noop ")); 999 break; 1000 1001 case MSG_DISCONNECT: 1002 NCR_MSGS(("disconnect ")); 1003 ti->dconns++; 1004 sc->sc_state = NCR_DISCONNECT; 1005 1006 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1007 break; 1008 /*FALLTHROUGH*/ 1009 1010 case MSG_SAVEDATAPOINTER: 1011 NCR_MSGS(("save datapointer ")); 1012 ecb->daddr = sc->sc_dp; 1013 ecb->dleft = sc->sc_dleft; 1014 break; 1015 1016 case MSG_RESTOREPOINTERS: 1017 NCR_MSGS(("restore datapointer ")); 1018 sc->sc_dp = ecb->daddr; 1019 sc->sc_dleft = ecb->dleft; 1020 break; 1021 1022 case MSG_EXTENDED: 1023 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1024 switch (sc->sc_imess[2]) { 1025 case MSG_EXT_SDTR: 1026 NCR_MSGS(("SDTR period %d, offset %d ", 1027 sc->sc_imess[3], sc->sc_imess[4])); 1028 if (sc->sc_imess[1] != 3) 1029 goto reject; 1030 ti->period = sc->sc_imess[3]; 1031 ti->offset = sc->sc_imess[4]; 1032 ti->flags &= ~T_NEGOTIATE; 1033 if (sc->sc_minsync == 0 || 1034 ti->offset == 0 || 1035 ti->period > 124) { 1036 printf("%s:%d: async\n", "esp", 1037 ecb->xs->sc_link->target); 1038 if ((sc->sc_flags&NCR_SYNCHNEGO) 1039 == 0) { 1040 /* 1041 * target initiated negotiation 1042 */ 1043 ti->offset = 0; 1044 ti->flags &= ~T_SYNCMODE; 1045 ncr53c9x_sched_msgout( 1046 SEND_SDTR); 1047 } else { 1048 /* we are async */ 1049 ti->flags &= ~T_SYNCMODE; 1050 } 1051 } else { 1052 int r = 250/ti->period; 1053 int s = (100*250)/ti->period - 100*r; 1054 int p; 1055 1056 p = ncr53c9x_stp2cpb(sc, ti->period); 1057 ti->period = ncr53c9x_cpb2stp(sc, p); 1058 #ifdef NCR53C9X_DEBUG 1059 sc_print_addr(ecb->xs->sc_link); 1060 printf("max sync rate %d.%02dMb/s\n", 1061 r, s); 1062 #endif 1063 if ((sc->sc_flags&NCR_SYNCHNEGO) 1064 == 0) { 1065 /* 1066 * target initiated negotiation 1067 */ 1068 if (ti->period < 1069 sc->sc_minsync) 1070 ti->period = 1071 sc->sc_minsync; 1072 if (ti->offset > 15) 1073 ti->offset = 15; 1074 ti->flags &= ~T_SYNCMODE; 1075 ncr53c9x_sched_msgout( 1076 SEND_SDTR); 1077 } else { 1078 /* we are sync */ 1079 ti->flags |= T_SYNCMODE; 1080 } 1081 } 1082 sc->sc_flags &= ~NCR_SYNCHNEGO; 1083 ncr53c9x_setsync(sc, ti); 1084 break; 1085 1086 default: 1087 printf("%s: unrecognized MESSAGE EXTENDED;" 1088 " sending REJECT\n", sc->sc_dev.dv_xname); 1089 goto reject; 1090 } 1091 break; 1092 1093 default: 1094 NCR_MSGS(("ident ")); 1095 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1096 sc->sc_dev.dv_xname); 1097 reject: 1098 ncr53c9x_sched_msgout(SEND_REJECT); 1099 break; 1100 } 1101 break; 1102 1103 case NCR_RESELECTED: 1104 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1105 printf("%s: reselect without IDENTIFY;" 1106 " sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1107 goto reset; 1108 } 1109 1110 (void) ncr53c9x_reselect(sc, sc->sc_imess[0]); 1111 break; 1112 1113 default: 1114 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1115 sc->sc_dev.dv_xname); 1116 reset: 1117 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1118 break; 1119 1120 abort: 1121 ncr53c9x_sched_msgout(SEND_ABORT); 1122 break; 1123 } 1124 1125 /* Ack last message byte */ 1126 NCRCMD(sc, NCRCMD_MSGOK); 1127 1128 /* Done, reset message pointer. */ 1129 sc->sc_flags &= ~NCR_DROP_MSGI; 1130 sc->sc_imlen = 0; 1131 } 1132 1133 1134 /* 1135 * Send the highest priority, scheduled message 1136 */ 1137 void 1138 ncr53c9x_msgout(sc) 1139 register struct ncr53c9x_softc *sc; 1140 { 1141 struct ncr53c9x_tinfo *ti; 1142 struct ncr53c9x_ecb *ecb; 1143 size_t size; 1144 1145 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1146 sc->sc_msgpriq, sc->sc_prevphase)); 1147 1148 if (sc->sc_flags & NCR_ATN) { 1149 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1150 new: 1151 NCRCMD(sc, NCRCMD_FLUSH); 1152 DELAY(1); 1153 sc->sc_msgoutq = 0; 1154 sc->sc_omlen = 0; 1155 } 1156 } else { 1157 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1158 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1159 goto new; 1160 } else { 1161 printf("%s at line %d: unexpected MESSAGE OUT phase\n", 1162 sc->sc_dev.dv_xname, __LINE__); 1163 } 1164 } 1165 1166 if (sc->sc_omlen == 0) { 1167 /* Pick up highest priority message */ 1168 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1169 sc->sc_msgoutq |= sc->sc_msgout; 1170 sc->sc_msgpriq &= ~sc->sc_msgout; 1171 sc->sc_omlen = 1; /* "Default" message len */ 1172 switch (sc->sc_msgout) { 1173 case SEND_SDTR: 1174 ecb = sc->sc_nexus; 1175 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1176 sc->sc_omess[0] = MSG_EXTENDED; 1177 sc->sc_omess[1] = 3; 1178 sc->sc_omess[2] = MSG_EXT_SDTR; 1179 sc->sc_omess[3] = ti->period; 1180 sc->sc_omess[4] = ti->offset; 1181 sc->sc_omlen = 5; 1182 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1183 ti->flags |= T_SYNCMODE; 1184 ncr53c9x_setsync(sc, ti); 1185 } 1186 break; 1187 case SEND_IDENTIFY: 1188 if (sc->sc_state != NCR_CONNECTED) { 1189 printf("%s at line %d: no nexus\n", 1190 sc->sc_dev.dv_xname, __LINE__); 1191 } 1192 ecb = sc->sc_nexus; 1193 sc->sc_omess[0] = 1194 MSG_IDENTIFY(ecb->xs->sc_link->lun, 0); 1195 break; 1196 case SEND_DEV_RESET: 1197 sc->sc_flags |= NCR_ABORTING; 1198 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1199 ecb = sc->sc_nexus; 1200 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1201 ti->flags &= ~T_SYNCMODE; 1202 ti->flags |= T_NEGOTIATE; 1203 break; 1204 case SEND_PARITY_ERROR: 1205 sc->sc_omess[0] = MSG_PARITY_ERROR; 1206 break; 1207 case SEND_ABORT: 1208 sc->sc_flags |= NCR_ABORTING; 1209 sc->sc_omess[0] = MSG_ABORT; 1210 break; 1211 case SEND_INIT_DET_ERR: 1212 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1213 break; 1214 case SEND_REJECT: 1215 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1216 break; 1217 default: 1218 NCRCMD(sc, NCRCMD_RSTATN); 1219 sc->sc_flags &= ~NCR_ATN; 1220 sc->sc_omess[0] = MSG_NOOP; 1221 break; 1222 } 1223 sc->sc_omp = sc->sc_omess; 1224 } 1225 1226 #if 1 1227 /* (re)send the message */ 1228 size = min(sc->sc_omlen, sc->sc_maxxfer); 1229 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1230 /* Program the SCSI counter */ 1231 NCR_WRITE_REG(sc, NCR_TCL, size); 1232 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1233 if (sc->sc_cfg2 & NCRCFG2_FE) { 1234 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1235 } 1236 /* load the count in */ 1237 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1238 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 1239 NCRDMA_GO(sc); 1240 #else 1241 { int i; 1242 for (i = 0; i < sc->sc_omlen; i++) 1243 NCR_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1244 NCRCMD(sc, NCRCMD_TRANS); 1245 sc->sc_omlen = 0; 1246 } 1247 #endif 1248 } 1249 1250 /* 1251 * This is the most critical part of the driver, and has to know 1252 * how to deal with *all* error conditions and phases from the SCSI 1253 * bus. If there are no errors and the DMA was active, then call the 1254 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1255 * and we can return from here without further processing. 1256 * 1257 * Most of this needs verifying. 1258 */ 1259 int 1260 ncr53c9x_intr(sc) 1261 register struct ncr53c9x_softc *sc; 1262 { 1263 register struct ncr53c9x_ecb *ecb; 1264 register struct scsi_link *sc_link; 1265 struct ncr53c9x_tinfo *ti; 1266 int loop; 1267 size_t size; 1268 int nfifo; 1269 1270 NCR_TRACE(("[ncr53c9x_intr]")); 1271 1272 /* 1273 * I have made some (maybe seriously flawed) assumptions here, 1274 * but basic testing (uncomment the printf() below), show that 1275 * certainly something happens when this loop is here. 1276 * 1277 * The idea is that many of the SCSI operations take very little 1278 * time, and going away and getting interrupted is too high an 1279 * overhead to pay. For example, selecting, sending a message 1280 * and command and then doing some work can be done in one "pass". 1281 * 1282 * The DELAY is not variable because I do not understand that the 1283 * DELAY loop should be fixed-time regardless of CPU speed, but 1284 * I am *assuming* that the faster SCSI processors get things done 1285 * quicker (sending a command byte etc), and so there is no 1286 * need to be too slow. 1287 * 1288 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1289 * at 40Mhz. This needs testing. 1290 */ 1291 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1292 /* a feeling of deja-vu */ 1293 if (!NCRDMA_ISINTR(sc)) 1294 return (loop != 0); 1295 #if 0 1296 if (loop) 1297 printf("*"); 1298 #endif 1299 1300 /* and what do the registers say... */ 1301 ncr53c9x_readregs(sc); 1302 1303 sc->sc_intrcnt.ev_count++; 1304 1305 /* 1306 * At the moment, only a SCSI Bus Reset or Illegal 1307 * Command are classed as errors. A disconnect is a 1308 * valid condition, and we let the code check is the 1309 * "NCR_BUSFREE_OK" flag was set before declaring it 1310 * and error. 1311 * 1312 * Also, the status register tells us about "Gross 1313 * Errors" and "Parity errors". Only the Gross Error 1314 * is really bad, and the parity errors are dealt 1315 * with later 1316 * 1317 * TODO 1318 * If there are too many parity error, go to slow 1319 * cable mode ? 1320 */ 1321 1322 /* SCSI Reset */ 1323 if (sc->sc_espintr & NCRINTR_SBR) { 1324 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1325 NCRCMD(sc, NCRCMD_FLUSH); 1326 DELAY(1); 1327 } 1328 if (sc->sc_state != NCR_SBR) { 1329 printf("%s: SCSI bus reset\n", 1330 sc->sc_dev.dv_xname); 1331 ncr53c9x_init(sc, 0); /* Restart everything */ 1332 return 1; 1333 } 1334 #if 0 1335 /*XXX*/ printf("<expected bus reset: " 1336 "[intr %x, stat %x, step %d]>\n", 1337 sc->sc_espintr, sc->sc_espstat, 1338 sc->sc_espstep); 1339 #endif 1340 if (sc->sc_nexus) 1341 panic("%s: nexus in reset state", 1342 sc->sc_dev.dv_xname); 1343 goto sched; 1344 } 1345 1346 ecb = sc->sc_nexus; 1347 1348 #define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 1349 if (sc->sc_espintr & NCRINTR_ERR || 1350 sc->sc_espstat & NCRSTAT_GE) { 1351 1352 if (sc->sc_espstat & NCRSTAT_GE) { 1353 /* no target ? */ 1354 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1355 NCRCMD(sc, NCRCMD_FLUSH); 1356 DELAY(1); 1357 } 1358 if (sc->sc_state == NCR_CONNECTED || 1359 sc->sc_state == NCR_SELECTING) { 1360 ecb->xs->error = XS_DRIVER_STUFFUP; 1361 ncr53c9x_done(sc, ecb); 1362 } 1363 return 1; 1364 } 1365 1366 if (sc->sc_espintr & NCRINTR_ILL) { 1367 if (sc->sc_flags & NCR_EXPECT_ILLCMD) { 1368 printf("%s: ILL: ESP100 work-around activated\n", sc->sc_dev.dv_xname); 1369 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1370 continue; 1371 } 1372 /* illegal command, out of sync ? */ 1373 printf("%s: illegal command: 0x%x " 1374 "(state %d, phase %x, prevphase %x)\n", 1375 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1376 sc->sc_state, sc->sc_phase, 1377 sc->sc_prevphase); 1378 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1379 NCRCMD(sc, NCRCMD_FLUSH); 1380 DELAY(1); 1381 } 1382 ncr53c9x_init(sc, 1); /* Restart everything */ 1383 return 1; 1384 } 1385 } 1386 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 1387 1388 /* 1389 * Call if DMA is active. 1390 * 1391 * If DMA_INTR returns true, then maybe go 'round the loop 1392 * again in case there is no more DMA queued, but a phase 1393 * change is expected. 1394 */ 1395 if (NCRDMA_ISACTIVE(sc)) { 1396 int r = NCRDMA_INTR(sc); 1397 if (r == -1) { 1398 printf("%s: DMA error; resetting\n", 1399 sc->sc_dev.dv_xname); 1400 ncr53c9x_init(sc, 1); 1401 } 1402 /* If DMA active here, then go back to work... */ 1403 if (NCRDMA_ISACTIVE(sc)) 1404 return 1; 1405 1406 if (sc->sc_dleft == 0 && 1407 (sc->sc_espstat & NCRSTAT_TC) == 0) 1408 printf("%s: !TC [intr %x, stat %x, step %d]" 1409 " prevphase %x, resid %x\n", 1410 sc->sc_dev.dv_xname, 1411 sc->sc_espintr, 1412 sc->sc_espstat, 1413 sc->sc_espstep, 1414 sc->sc_prevphase, 1415 ecb?ecb->dleft:-1); 1416 } 1417 1418 #if 0 /* Unreliable on some NCR revisions? */ 1419 if ((sc->sc_espstat & NCRSTAT_INT) == 0) { 1420 printf("%s: spurious interrupt\n", 1421 sc->sc_dev.dv_xname); 1422 return 1; 1423 } 1424 #endif 1425 1426 /* 1427 * check for less serious errors 1428 */ 1429 if (sc->sc_espstat & NCRSTAT_PE) { 1430 printf("%s: SCSI bus parity error\n", 1431 sc->sc_dev.dv_xname); 1432 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1433 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 1434 else 1435 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 1436 } 1437 1438 if (sc->sc_espintr & NCRINTR_DIS) { 1439 NCR_MISC(("<DISC [intr %x, stat %x, step %d]>", 1440 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1441 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1442 NCRCMD(sc, NCRCMD_FLUSH); 1443 DELAY(1); 1444 } 1445 /* 1446 * This command must (apparently) be issued within 1447 * 250mS of a disconnect. So here you are... 1448 */ 1449 NCRCMD(sc, NCRCMD_ENSEL); 1450 switch (sc->sc_state) { 1451 case NCR_RESELECTED: 1452 goto sched; 1453 1454 case NCR_SELECTING: 1455 ecb->xs->error = XS_SELTIMEOUT; 1456 goto finish; 1457 1458 case NCR_CONNECTED: 1459 if ((sc->sc_flags & NCR_SYNCHNEGO)) { 1460 #ifdef NCR53C9X_DEBUG 1461 if (ecb) 1462 sc_print_addr(ecb->xs->sc_link); 1463 printf("sync nego not completed!\n"); 1464 #endif 1465 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1466 sc->sc_flags &= ~NCR_SYNCHNEGO; 1467 ti->flags &= 1468 ~(T_NEGOTIATE | T_SYNCMODE); 1469 } 1470 1471 /* it may be OK to disconnect */ 1472 if ((sc->sc_flags & NCR_ABORTING) == 0) { 1473 /* 1474 * Section 5.1.1 of the SCSI 2 spec 1475 * suggests issuing a REQUEST SENSE 1476 * following an unexpected disconnect. 1477 * Some devices go into a contingent 1478 * allegiance condition when 1479 * disconnecting, and this is necessary 1480 * to clean up their state. 1481 */ 1482 printf("%s: unexpected disconnect; ", 1483 sc->sc_dev.dv_xname); 1484 if (ecb->flags & ECB_SENSE) { 1485 printf("resetting\n"); 1486 goto reset; 1487 } 1488 printf("sending REQUEST SENSE\n"); 1489 untimeout(ncr53c9x_timeout, ecb); 1490 ncr53c9x_sense(sc, ecb); 1491 goto out; 1492 } 1493 1494 ecb->xs->error = XS_DRIVER_STUFFUP; 1495 goto finish; 1496 1497 case NCR_DISCONNECT: 1498 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1499 sc->sc_nexus = NULL; 1500 goto sched; 1501 1502 case NCR_CMDCOMPLETE: 1503 goto finish; 1504 } 1505 } 1506 1507 switch (sc->sc_state) { 1508 1509 case NCR_SBR: 1510 printf("%s: waiting for SCSI Bus Reset to happen\n", 1511 sc->sc_dev.dv_xname); 1512 return 1; 1513 1514 case NCR_RESELECTED: 1515 /* 1516 * we must be continuing a message ? 1517 */ 1518 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1519 printf("%s: target didn't identify\n", 1520 sc->sc_dev.dv_xname); 1521 ncr53c9x_init(sc, 1); 1522 return 1; 1523 } 1524 printf("<<RESELECT CONT'd>>"); 1525 #if XXXX 1526 ncr53c9x_msgin(sc); 1527 if (sc->sc_state != NCR_CONNECTED) { 1528 /* IDENTIFY fail?! */ 1529 printf("%s: identify failed\n", 1530 sc->sc_dev.dv_xname); 1531 ncr53c9x_init(sc, 1); 1532 return 1; 1533 } 1534 #endif 1535 break; 1536 1537 case NCR_IDLE: 1538 if (sc->sc_flags & NCR_ICCS) printf("[[esp: BUMMER]]"); 1539 case NCR_SELECTING: 1540 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1541 sc->sc_flags = 0; 1542 ecb = sc->sc_nexus; 1543 1544 if (sc->sc_espintr & NCRINTR_RESEL) { 1545 /* 1546 * If we're trying to select a 1547 * target ourselves, push our command 1548 * back into the ready list. 1549 */ 1550 if (sc->sc_state == NCR_SELECTING) { 1551 NCR_MISC(("backoff selector ")); 1552 untimeout(ncr53c9x_timeout, ecb); 1553 sc_link = ecb->xs->sc_link; 1554 ti = &sc->sc_tinfo[sc_link->target]; 1555 TAILQ_INSERT_HEAD(&sc->ready_list, 1556 ecb, chain); 1557 ecb = sc->sc_nexus = NULL; 1558 } 1559 sc->sc_state = NCR_RESELECTED; 1560 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1561 /* 1562 * Things are seriously fucked up. 1563 * Pull the brakes, i.e. reset 1564 */ 1565 printf("%s: target didn't identify\n", 1566 sc->sc_dev.dv_xname); 1567 ncr53c9x_init(sc, 1); 1568 return 1; 1569 } 1570 /* 1571 * The C90 only inhibits FIFO writes until 1572 * reselection is complete, instead of 1573 * waiting until the interrupt status register 1574 * has been read. So, if the reselect happens 1575 * while we were entering a command bytes (for 1576 * another target) some of those bytes can 1577 * appear in the FIFO here, after the 1578 * interrupt is taken. 1579 */ 1580 nfifo = NCR_READ_REG(sc,NCR_FFLAG) & NCRFIFO_FF; 1581 if (nfifo < 2 || 1582 (nfifo > 2 && 1583 sc->sc_rev != NCR_VARIANT_ESP100)) { 1584 printf("%s: RESELECT: " 1585 "%d bytes in FIFO! " 1586 "[intr %x, stat %x, step %d, prevphase %x]\n", 1587 sc->sc_dev.dv_xname, 1588 nfifo, 1589 sc->sc_espintr, 1590 sc->sc_espstat, 1591 sc->sc_espstep, 1592 sc->sc_prevphase); 1593 ncr53c9x_init(sc, 1); 1594 return 1; 1595 } 1596 sc->sc_selid = NCR_READ_REG(sc, NCR_FIFO); 1597 NCR_MISC(("selid=0x%2x ", sc->sc_selid)); 1598 1599 /* Handle identify message */ 1600 ncr53c9x_msgin(sc); 1601 if (nfifo != 2) { 1602 sc->sc_flags |= NCR_EXPECT_ILLCMD; 1603 NCRCMD(sc, NCRCMD_FLUSH); 1604 } 1605 1606 if (sc->sc_state != NCR_CONNECTED) { 1607 /* IDENTIFY fail?! */ 1608 printf("%s: identify failed\n", 1609 sc->sc_dev.dv_xname); 1610 ncr53c9x_init(sc, 1); 1611 return 1; 1612 } 1613 continue; /* ie. next phase expected soon */ 1614 } 1615 1616 #define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 1617 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 1618 ecb = sc->sc_nexus; 1619 if (!ecb) 1620 panic("esp: not nexus at sc->sc_nexus"); 1621 1622 sc_link = ecb->xs->sc_link; 1623 ti = &sc->sc_tinfo[sc_link->target]; 1624 1625 switch (sc->sc_espstep) { 1626 case 0: 1627 printf("%s: select timeout/no " 1628 "disconnect\n", 1629 sc->sc_dev.dv_xname); 1630 ecb->xs->error = XS_SELTIMEOUT; 1631 goto finish; 1632 case 1: 1633 if ((ti->flags & T_NEGOTIATE) == 0) { 1634 printf("%s: step 1 & !NEG\n", 1635 sc->sc_dev.dv_xname); 1636 goto reset; 1637 } 1638 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1639 printf("%s: !MSGOUT\n", 1640 sc->sc_dev.dv_xname); 1641 goto reset; 1642 } 1643 /* Start negotiating */ 1644 ti->period = sc->sc_minsync; 1645 ti->offset = 15; 1646 sc->sc_flags |= NCR_SYNCHNEGO; 1647 ncr53c9x_sched_msgout(SEND_SDTR); 1648 break; 1649 case 3: 1650 /* 1651 * Grr, this is supposed to mean 1652 * "target left command phase 1653 * prematurely". It seems to happen 1654 * regularly when sync mode is on. 1655 * Look at FIFO to see if command 1656 * went out. 1657 * (Timing problems?) 1658 */ 1659 if (ncr53c9x_dmaselect) { 1660 if (sc->sc_cmdlen == 0) 1661 /* Hope for the best.. */ 1662 break; 1663 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 1664 & NCRFIFO_FF) == 0) { 1665 /* Hope for the best.. */ 1666 break; 1667 } 1668 printf("(%s:%d:%d): selection failed;" 1669 " %d left in FIFO " 1670 "[intr %x, stat %x, step %d]\n", 1671 sc->sc_dev.dv_xname, 1672 sc_link->target, 1673 sc_link->lun, 1674 NCR_READ_REG(sc, NCR_FFLAG) 1675 & NCRFIFO_FF, 1676 sc->sc_espintr, sc->sc_espstat, 1677 sc->sc_espstep); 1678 NCRCMD(sc, NCRCMD_FLUSH); 1679 ncr53c9x_sched_msgout(SEND_ABORT); 1680 return 1; 1681 case 2: 1682 /* Select stuck at Command Phase */ 1683 NCRCMD(sc, NCRCMD_FLUSH); 1684 case 4: 1685 if (ncr53c9x_dmaselect && 1686 sc->sc_cmdlen != 0) 1687 printf("(%s:%d:%d): select; " 1688 "%d left in DMA buffer\n", 1689 sc->sc_dev.dv_xname, 1690 sc_link->target, 1691 sc_link->lun, 1692 sc->sc_cmdlen); 1693 /* So far, everything went fine */ 1694 break; 1695 } 1696 #if 0 1697 if (ecb->xs->flags & SCSI_RESET) 1698 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1699 else if (ti->flags & T_NEGOTIATE) 1700 ncr53c9x_sched_msgout( 1701 SEND_IDENTIFY | SEND_SDTR); 1702 else 1703 ncr53c9x_sched_msgout(SEND_IDENTIFY); 1704 #endif 1705 1706 ecb->flags |= ECB_NEXUS; 1707 ti->lubusy |= (1 << sc_link->lun); 1708 1709 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1710 /* Do an implicit RESTORE POINTERS. */ 1711 sc->sc_dp = ecb->daddr; 1712 sc->sc_dleft = ecb->dleft; 1713 sc->sc_state = NCR_CONNECTED; 1714 break; 1715 } else { 1716 printf("%s: unexpected status after select" 1717 ": [intr %x, stat %x, step %x]\n", 1718 sc->sc_dev.dv_xname, 1719 sc->sc_espintr, sc->sc_espstat, 1720 sc->sc_espstep); 1721 NCRCMD(sc, NCRCMD_FLUSH); 1722 DELAY(1); 1723 goto reset; 1724 } 1725 if (sc->sc_state == NCR_IDLE) { 1726 printf("%s: stray interrupt\n", 1727 sc->sc_dev.dv_xname); 1728 return 0; 1729 } 1730 break; 1731 1732 case NCR_CONNECTED: 1733 if (sc->sc_flags & NCR_ICCS) { 1734 u_char msg; 1735 1736 sc->sc_flags &= ~NCR_ICCS; 1737 1738 if (!(sc->sc_espintr & NCRINTR_DONE)) { 1739 printf("%s: ICCS: " 1740 ": [intr %x, stat %x, step %x]\n", 1741 sc->sc_dev.dv_xname, 1742 sc->sc_espintr, sc->sc_espstat, 1743 sc->sc_espstep); 1744 } 1745 if ((NCR_READ_REG(sc, NCR_FFLAG) 1746 & NCRFIFO_FF) != 2) { 1747 int i = (NCR_READ_REG(sc, NCR_FFLAG) 1748 & NCRFIFO_FF) - 2; 1749 while (i--) 1750 (void) NCR_READ_REG(sc, 1751 NCR_FIFO); 1752 } 1753 ecb->stat = NCR_READ_REG(sc, NCR_FIFO); 1754 msg = NCR_READ_REG(sc, NCR_FIFO); 1755 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1756 if (msg == MSG_CMDCOMPLETE) { 1757 ecb->xs->resid = ecb->dleft = 1758 sc->sc_dleft; 1759 sc->sc_state = NCR_CMDCOMPLETE; 1760 } else 1761 printf("%s: STATUS_PHASE: msg %d\n", 1762 sc->sc_dev.dv_xname, msg); 1763 NCRCMD(sc, NCRCMD_MSGOK); 1764 continue; /* ie. wait for disconnect */ 1765 } 1766 break; 1767 default: 1768 panic("%s: invalid state: %d", 1769 sc->sc_dev.dv_xname, 1770 sc->sc_state); 1771 } 1772 1773 /* 1774 * Driver is now in state NCR_CONNECTED, i.e. we 1775 * have a current command working the SCSI bus. 1776 */ 1777 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 1778 panic("esp no nexus"); 1779 } 1780 1781 switch (sc->sc_phase) { 1782 case MESSAGE_OUT_PHASE: 1783 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 1784 ncr53c9x_msgout(sc); 1785 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1786 break; 1787 case MESSAGE_IN_PHASE: 1788 NCR_PHASE(("MESSAGE_IN_PHASE ")); 1789 if (sc->sc_espintr & NCRINTR_BS) { 1790 NCRCMD(sc, NCRCMD_FLUSH); 1791 sc->sc_flags |= NCR_WAITI; 1792 NCRCMD(sc, NCRCMD_TRANS); 1793 } else if (sc->sc_espintr & NCRINTR_FC) { 1794 if ((sc->sc_flags & NCR_WAITI) == 0) { 1795 printf("%s: MSGIN: unexpected FC bit: " 1796 "[intr %x, stat %x, step %x]\n", 1797 sc->sc_dev.dv_xname, 1798 sc->sc_espintr, sc->sc_espstat, 1799 sc->sc_espstep); 1800 } 1801 sc->sc_flags &= ~NCR_WAITI; 1802 ncr53c9x_msgin(sc); 1803 } else { 1804 printf("%s: MSGIN: weird bits: " 1805 "[intr %x, stat %x, step %x]\n", 1806 sc->sc_dev.dv_xname, 1807 sc->sc_espintr, sc->sc_espstat, 1808 sc->sc_espstep); 1809 } 1810 sc->sc_prevphase = MESSAGE_IN_PHASE; 1811 break; 1812 case COMMAND_PHASE: 1813 /* 1814 * Send the command block. Normally we don't see this 1815 * phase because the SEL_ATN command takes care of 1816 * all this. However, we end up here if either the 1817 * target or we wanted exchange some more messages 1818 * first (e.g. to start negotiations). 1819 */ 1820 1821 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 1822 ecb->cmd.cmd.opcode, ecb->clen)); 1823 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 1824 NCRCMD(sc, NCRCMD_FLUSH); 1825 DELAY(1); 1826 } 1827 if (ncr53c9x_dmaselect) { 1828 size_t size; 1829 /* setup DMA transfer for command */ 1830 size = ecb->clen; 1831 sc->sc_cmdlen = size; 1832 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 1833 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 1834 0, &size); 1835 /* Program the SCSI counter */ 1836 NCR_WRITE_REG(sc, NCR_TCL, size); 1837 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1838 if (sc->sc_cfg2 & NCRCFG2_FE) { 1839 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1840 } 1841 1842 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 1843 NCRDMA_GO(sc); 1844 } else { 1845 u_char *cmd = (u_char *)&ecb->cmd.cmd; 1846 int i; 1847 /* Now the command into the FIFO */ 1848 for (i = 0; i < ecb->clen; i++) 1849 NCR_WRITE_REG(sc, NCR_FIFO, *cmd++); 1850 NCRCMD(sc, NCRCMD_TRANS); 1851 } 1852 sc->sc_prevphase = COMMAND_PHASE; 1853 break; 1854 case DATA_OUT_PHASE: 1855 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 1856 NCRCMD(sc, NCRCMD_FLUSH); 1857 size = min(sc->sc_dleft, sc->sc_maxxfer); 1858 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1859 0, &size); 1860 sc->sc_prevphase = DATA_OUT_PHASE; 1861 goto setup_xfer; 1862 case DATA_IN_PHASE: 1863 NCR_PHASE(("DATA_IN_PHASE ")); 1864 if (sc->sc_rev == NCR_VARIANT_ESP100) 1865 NCRCMD(sc, NCRCMD_FLUSH); 1866 size = min(sc->sc_dleft, sc->sc_maxxfer); 1867 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1868 1, &size); 1869 sc->sc_prevphase = DATA_IN_PHASE; 1870 setup_xfer: 1871 /* Program the SCSI counter */ 1872 NCR_WRITE_REG(sc, NCR_TCL, size); 1873 NCR_WRITE_REG(sc, NCR_TCM, size >> 8); 1874 if (sc->sc_cfg2 & NCRCFG2_FE) { 1875 NCR_WRITE_REG(sc, NCR_TCH, size >> 16); 1876 } 1877 /* load the count in */ 1878 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 1879 1880 /* 1881 * Note that if `size' is 0, we've already transceived 1882 * all the bytes we want but we're still in DATA PHASE. 1883 * Apparently, the device needs padding. Also, a 1884 * transfer size of 0 means "maximum" to the chip 1885 * DMA logic. 1886 */ 1887 NCRCMD(sc, 1888 (size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA); 1889 NCRDMA_GO(sc); 1890 return 1; 1891 case STATUS_PHASE: 1892 NCR_PHASE(("STATUS_PHASE ")); 1893 sc->sc_flags |= NCR_ICCS; 1894 NCRCMD(sc, NCRCMD_ICCS); 1895 sc->sc_prevphase = STATUS_PHASE; 1896 break; 1897 case INVALID_PHASE: 1898 break; 1899 default: 1900 printf("%s: unexpected bus phase; resetting\n", 1901 sc->sc_dev.dv_xname); 1902 goto reset; 1903 } 1904 } 1905 panic("esp: should not get here.."); 1906 1907 reset: 1908 ncr53c9x_init(sc, 1); 1909 return 1; 1910 1911 finish: 1912 ncr53c9x_done(sc, ecb); 1913 goto out; 1914 1915 sched: 1916 sc->sc_state = NCR_IDLE; 1917 ncr53c9x_sched(sc); 1918 goto out; 1919 1920 out: 1921 return 1; 1922 } 1923 1924 void 1925 ncr53c9x_abort(sc, ecb) 1926 struct ncr53c9x_softc *sc; 1927 struct ncr53c9x_ecb *ecb; 1928 { 1929 1930 /* 2 secs for the abort */ 1931 ecb->timeout = NCR_ABORT_TIMEOUT; 1932 ecb->flags |= ECB_ABORT; 1933 1934 if (ecb == sc->sc_nexus) { 1935 /* 1936 * If we're still selecting, the message will be scheduled 1937 * after selection is complete. 1938 */ 1939 if (sc->sc_state == NCR_CONNECTED) 1940 ncr53c9x_sched_msgout(SEND_ABORT); 1941 1942 /* 1943 * Reschedule timeout. First, cancel a queued timeout (if any) 1944 * in case someone decides to call ncr53c9x_abort() from 1945 * elsewhere. 1946 */ 1947 untimeout(ncr53c9x_timeout, ecb); 1948 timeout(ncr53c9x_timeout, ecb, (ecb->timeout * hz) / 1000); 1949 } else { 1950 ncr53c9x_dequeue(sc, ecb); 1951 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1952 if (sc->sc_state == NCR_IDLE) 1953 ncr53c9x_sched(sc); 1954 } 1955 } 1956 1957 void 1958 ncr53c9x_timeout(arg) 1959 void *arg; 1960 { 1961 struct ncr53c9x_ecb *ecb = arg; 1962 struct scsi_xfer *xs = ecb->xs; 1963 struct scsi_link *sc_link = xs->sc_link; 1964 struct ncr53c9x_softc *sc = sc_link->adapter_softc; 1965 int s; 1966 1967 sc_print_addr(sc_link); 1968 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 1969 "<state %d, nexus %p, phase(c %x, p %x), resid %lx, " 1970 "msg(q %x,o %x) %s>", 1971 sc->sc_dev.dv_xname, 1972 ecb, ecb->flags, ecb->dleft, ecb->stat, 1973 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 1974 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 1975 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 1976 #if NCR53C9X_DEBUG > 1 1977 printf("TRACE: %s.", ecb->trace); 1978 #endif 1979 1980 s = splbio(); 1981 1982 if (ecb->flags & ECB_ABORT) { 1983 /* abort timed out */ 1984 printf(" AGAIN\n"); 1985 ncr53c9x_init(sc, 1); 1986 } else { 1987 /* abort the operation that has timed out */ 1988 printf("\n"); 1989 xs->error = XS_TIMEOUT; 1990 ncr53c9x_abort(sc, ecb); 1991 } 1992 1993 splx(s); 1994 } 1995
Indexes created Sat Sep 27 14:09:57 GMT 2025