ncr53c9xvar.h revision 1.15
1 /* $NetBSD: ncr53c9xvar.h,v 1.15 1998/09/01 22:56:00 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* Set this to 1 for normal debug, or 2 for per-target tracing. */ 70 #define NCR53C9X_DEBUG 1 71 72 #define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */ 73 #define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */ 74 75 #define FREQTOCCF(freq) (((freq + 4) / 5)) 76 77 /* 78 * NCR 53c9x variants. Note, these values are used as indexes into 79 * a table; don't modify them unless you know what you're doing. 80 */ 81 #define NCR_VARIANT_ESP100 0 82 #define NCR_VARIANT_ESP100A 1 83 #define NCR_VARIANT_ESP200 2 84 #define NCR_VARIANT_NCR53C94 3 85 #define NCR_VARIANT_NCR53C96 4 86 #define NCR_VARIANT_ESP406 5 87 #define NCR_VARIANT_FAS408 6 88 #define NCR_VARIANT_FAS216 7 89 #define NCR_VARIANT_MAX 8 90 91 /* 92 * ECB. Holds additional information for each SCSI command Comments: We 93 * need a separate scsi command block because we may need to overwrite it 94 * with a request sense command. Basicly, we refrain from fiddling with 95 * the scsipi_xfer struct (except do the expected updating of return values). 96 * We'll generally update: xs->{flags,resid,error,sense,status} and 97 * occasionally xs->retries. 98 */ 99 struct ncr53c9x_ecb { 100 TAILQ_ENTRY(ncr53c9x_ecb) chain; 101 struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */ 102 int flags; 103 #define ECB_ALLOC 0x01 104 #define ECB_NEXUS 0x02 105 #define ECB_SENSE 0x04 106 #define ECB_ABORT 0x40 107 #define ECB_RESET 0x80 108 #define ECB_TENTATIVE_DONE 0x100 109 int timeout; 110 111 struct { 112 u_char id; /* Selection Id msg */ 113 struct scsi_generic cmd; /* SCSI command block */ 114 } cmd; 115 int clen; /* Size of command in cmd.cmd */ 116 char *daddr; /* Saved data pointer */ 117 int dleft; /* Residue */ 118 u_char stat; /* SCSI status byte */ 119 u_char pad[3]; 120 121 #if NCR53C9X_DEBUG > 1 122 char trace[1000]; 123 #endif 124 }; 125 #if NCR53C9X_DEBUG > 1 126 #define ECB_TRACE(ecb, msg, a, b) do { \ 127 const char *f = "[" msg "]"; \ 128 int n = strlen((ecb)->trace); \ 129 if (n < (sizeof((ecb)->trace)-100)) \ 130 sprintf((ecb)->trace + n, f, a, b); \ 131 } while(0) 132 #else 133 #define ECB_TRACE(ecb, msg, a, b) 134 #endif 135 136 /* 137 * Some info about each (possible) target on the SCSI bus. This should 138 * probably have been a "per target+lunit" structure, but we'll leave it at 139 * this for now. Is there a way to reliably hook it up to sc->fordriver?? 140 */ 141 struct ncr53c9x_tinfo { 142 int cmds; /* #commands processed */ 143 int dconns; /* #disconnects */ 144 int touts; /* #timeouts */ 145 int perrs; /* #parity errors */ 146 int senses; /* #request sense commands sent */ 147 ushort lubusy; /* What local units/subr. are busy? */ 148 u_char flags; 149 #define T_NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */ 150 #define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */ 151 #define T_BUSY 0x04 /* Target is busy, i.e. cmd in progress */ 152 #define T_SYNCMODE 0x08 /* sync mode has been negotiated */ 153 #define T_SYNCHOFF 0x10 /* .. */ 154 #define T_RSELECTOFF 0x20 /* .. */ 155 u_char period; /* Period suggestion */ 156 u_char offset; /* Offset suggestion */ 157 u_char pad[3]; 158 } tinfo_t; 159 160 /* Register a linenumber (for debugging) */ 161 #define LOGLINE(p) 162 163 #define NCR_SHOWECBS 0x01 164 #define NCR_SHOWINTS 0x02 165 #define NCR_SHOWCMDS 0x04 166 #define NCR_SHOWMISC 0x08 167 #define NCR_SHOWTRAC 0x10 168 #define NCR_SHOWSTART 0x20 169 #define NCR_SHOWPHASE 0x40 170 #define NCR_SHOWDMA 0x80 171 #define NCR_SHOWCCMDS 0x100 172 #define NCR_SHOWMSGS 0x200 173 174 #ifdef NCR53C9X_DEBUG 175 extern int ncr53c9x_debug; 176 #define NCR_ECBS(str) \ 177 do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0) 178 #define NCR_MISC(str) \ 179 do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0) 180 #define NCR_INTS(str) \ 181 do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0) 182 #define NCR_TRACE(str) \ 183 do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0) 184 #define NCR_CMDS(str) \ 185 do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0) 186 #define NCR_START(str) \ 187 do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0) 188 #define NCR_PHASE(str) \ 189 do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0) 190 #define NCR_DMA(str) \ 191 do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0) 192 #define NCR_MSGS(str) \ 193 do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0) 194 #else 195 #define NCR_ECBS(str) 196 #define NCR_MISC(str) 197 #define NCR_INTS(str) 198 #define NCR_TRACE(str) 199 #define NCR_CMDS(str) 200 #define NCR_START(str) 201 #define NCR_PHASE(str) 202 #define NCR_DMA(str) 203 #define NCR_MSGS(str) 204 #endif 205 206 #define NCR_MAX_MSG_LEN 8 207 208 struct ncr53c9x_softc; 209 210 /* 211 * Function switch used as glue to MD code. 212 */ 213 struct ncr53c9x_glue { 214 /* Mandatory entry points. */ 215 u_char (*gl_read_reg) __P((struct ncr53c9x_softc *, int)); 216 void (*gl_write_reg) __P((struct ncr53c9x_softc *, int, u_char)); 217 int (*gl_dma_isintr) __P((struct ncr53c9x_softc *)); 218 void (*gl_dma_reset) __P((struct ncr53c9x_softc *)); 219 int (*gl_dma_intr) __P((struct ncr53c9x_softc *)); 220 int (*gl_dma_setup) __P((struct ncr53c9x_softc *, 221 caddr_t *, size_t *, int, size_t *)); 222 void (*gl_dma_go) __P((struct ncr53c9x_softc *)); 223 void (*gl_dma_stop) __P((struct ncr53c9x_softc *)); 224 int (*gl_dma_isactive) __P((struct ncr53c9x_softc *)); 225 226 /* Optional entry points. */ 227 void (*gl_clear_latched_intr) __P((struct ncr53c9x_softc *)); 228 }; 229 230 struct ncr53c9x_softc { 231 struct device sc_dev; /* us as a device */ 232 233 struct evcnt sc_intrcnt; /* intr count */ 234 struct scsipi_link sc_link; /* scsipi lint struct */ 235 236 struct ncr53c9x_glue *sc_glue; /* glue to MD code */ 237 238 int sc_cfflags; /* Copy of config flags */ 239 240 /* register defaults */ 241 u_char sc_cfg1; /* Config 1 */ 242 u_char sc_cfg2; /* Config 2, not ESP100 */ 243 u_char sc_cfg3; /* Config 3, only ESP200 */ 244 u_char sc_ccf; /* Clock Conversion */ 245 u_char sc_timeout; 246 247 /* register copies, see espreadregs() */ 248 u_char sc_espintr; 249 u_char sc_espstat; 250 u_char sc_espstep; 251 u_char sc_espfflags; 252 253 /* Lists of command blocks */ 254 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) 255 free_list, 256 ready_list, 257 nexus_list; 258 259 struct ncr53c9x_ecb *sc_nexus; /* Current command */ 260 struct ncr53c9x_ecb sc_ecb[3*8]; /* Three per target */ 261 struct ncr53c9x_tinfo sc_tinfo[8]; 262 263 /* Data about the current nexus (updated for every cmd switch) */ 264 caddr_t sc_dp; /* Current data pointer */ 265 ssize_t sc_dleft; /* Data left to transfer */ 266 267 /* Adapter state */ 268 int sc_phase; /* Copy of what bus phase we are in */ 269 int sc_prevphase; /* Copy of what bus phase we were in */ 270 u_char sc_state; /* State applicable to the adapter */ 271 u_char sc_flags; /* See below */ 272 u_char sc_selid; 273 u_char sc_lastcmd; 274 275 /* Message stuff */ 276 u_char sc_msgpriq; /* One or more messages to send (encoded) */ 277 u_char sc_msgout; /* What message is on its way out? */ 278 u_char sc_msgoutq; /* What messages have been sent so far? */ 279 u_char *sc_omess; /* MSGOUT buffer */ 280 caddr_t sc_omp; /* Message pointer (for multibyte messages) */ 281 size_t sc_omlen; 282 u_char *sc_imess; /* MSGIN buffer */ 283 caddr_t sc_imp; /* Message pointer (for multibyte messages) */ 284 size_t sc_imlen; 285 286 caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */ 287 size_t sc_cmdlen; /* Size of command in transit */ 288 289 /* Hardware attributes */ 290 int sc_freq; /* SCSI bus frequency in MHz */ 291 int sc_id; /* Our SCSI id */ 292 int sc_rev; /* Chip revision */ 293 int sc_features; /* Chip features */ 294 int sc_minsync; /* Minimum sync period / 4 */ 295 int sc_maxxfer; /* Maximum transfer size */ 296 }; 297 298 /* values for sc_state */ 299 #define NCR_IDLE 1 /* waiting for something to do */ 300 #define NCR_SELECTING 2 /* SCSI command is arbiting */ 301 #define NCR_RESELECTED 3 /* Has been reselected */ 302 #define NCR_CONNECTED 4 /* Actively using the SCSI bus */ 303 #define NCR_DISCONNECT 5 /* MSG_DISCONNECT received */ 304 #define NCR_CMDCOMPLETE 6 /* MSG_CMDCOMPLETE received */ 305 #define NCR_CLEANING 7 306 #define NCR_SBR 8 /* Expect a SCSI RST because we commanded it */ 307 308 /* values for sc_flags */ 309 #define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 310 #define NCR_ABORTING 0x02 /* Bailing out */ 311 #define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */ 312 #define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */ 313 #define NCR_ICCS 0x10 /* Expect status phase results */ 314 #define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */ 315 #define NCR_ATN 0x40 /* ATN asserted */ 316 #define NCR_EXPECT_ILLCMD 0x80 /* Expect Illegal Command Interrupt */ 317 318 /* values for sc_features */ 319 #define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 320 #define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 321 322 /* values for sc_msgout */ 323 #define SEND_DEV_RESET 0x01 324 #define SEND_PARITY_ERROR 0x02 325 #define SEND_INIT_DET_ERR 0x04 326 #define SEND_REJECT 0x08 327 #define SEND_IDENTIFY 0x10 328 #define SEND_ABORT 0x20 329 #define SEND_SDTR 0x40 330 #define SEND_WDTR 0x80 331 332 /* SCSI Status codes */ 333 #define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 334 335 /* phase bits */ 336 #define IOI 0x01 337 #define CDI 0x02 338 #define MSGI 0x04 339 340 /* Information transfer phases */ 341 #define DATA_OUT_PHASE (0) 342 #define DATA_IN_PHASE (IOI) 343 #define COMMAND_PHASE (CDI) 344 #define STATUS_PHASE (CDI|IOI) 345 #define MESSAGE_OUT_PHASE (MSGI|CDI) 346 #define MESSAGE_IN_PHASE (MSGI|CDI|IOI) 347 348 #define PHASE_MASK (MSGI|CDI|IOI) 349 350 /* Some pseudo phases for getphase()*/ 351 #define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 352 #define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 353 #define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 354 355 /* 356 * Macros to read and write the chip's registers. 357 */ 358 #define NCR_READ_REG(sc, reg) \ 359 (*(sc)->sc_glue->gl_read_reg)((sc), (reg)) 360 #define NCR_WRITE_REG(sc, reg, val) \ 361 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val)) 362 363 #ifdef NCR53C9X_DEBUG 364 #define NCRCMD(sc, cmd) do { \ 365 if (ncr53c9x_debug & NCR_SHOWCCMDS) \ 366 printf("<cmd:0x%x>", (unsigned)cmd); \ 367 sc->sc_lastcmd = cmd; \ 368 NCR_WRITE_REG(sc, NCR_CMD, cmd); \ 369 } while (0) 370 #else 371 #define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd) 372 #endif 373 374 /* 375 * DMA macros for NCR53c9x 376 */ 377 #define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc)) 378 #define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc)) 379 #define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc)) 380 #define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \ 381 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize)) 382 #define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc)) 383 #define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc)) 384 385 /* 386 * Macro to convert the chip register Clock Per Byte value to 387 * Sunchronous Transfer Period. 388 */ 389 #define ncr53c9x_cpb2stp(sc, cpb) \ 390 ((250 * (cpb)) / (sc)->sc_freq) 391 392 void ncr53c9x_attach __P((struct ncr53c9x_softc *, 393 struct scsipi_adapter *, struct scsipi_device *)); 394 int ncr53c9x_scsi_cmd __P((struct scsipi_xfer *)); 395 void ncr53c9x_reset __P((struct ncr53c9x_softc *)); 396 int ncr53c9x_intr __P((struct ncr53c9x_softc *)); 397 398 extern int ncr53c9x_dmaselect; 399 400 extern int ncr53c9x_dmaselect; 401
Indexes created Thu Oct 23 22:10:10 GMT 2025